ПОЛУПРОВОДНИКОВЫЙ МОДУЛЬ И СПОСОБ ИЗГОТОВЛЕНИЯ ПОЛУПРОВОДНИКОВОГО МОДУЛЯ

Изобретение относится к силовой полупроводниковой технике. Сущность изобретения: полупроводниковый модуль содержит базовый элемент, изоляционный элемент с двухсторонним металлизированным покрытием, расположенный с помощью первого из обоих металлизированных покрытий на базовом элементе, и по меньшей мере один полупроводниковый элемент, расположенный на другом из обоих металлизированных покрытий. На краевом участке изоляционного элемента расположен электроизоляционный слой, причем поверхность этого изоляционного слоя образует с поверхностью второго металлизированного покрытия общую плоскую поверхность. Предложен также способ изготовления полупроводникового модуля. Техническим результатом изобретения является создание полупроводникового модуля, характеризующегося повышенной диэлектрической прочностью и одновременно простотой изготовления. 2 н. и 8 з.п. ф-лы, 5 ил.

УСТРОЙСТВО С ПЕРЕХОДНЫМИ ОТВЕРСТИЯМИ В ПОДЛОЖКЕ И СПОСОБ ЕГО ПРОИЗВОДСТВА

Изобретение относится к устройству (10) с переходными отверстиями в подложке, содержащему подложку (12), выполненную из материала подложки и имеющую первую поверхность (12а) подложки и вторую поверхность (12b) подложки, противоположную первой поверхности (12а) подложки. Устройство (10) с переходными отверстиями в подложке также содержит множество соседних первых канавок (14), обеспеченных проводящим материалом и проходящих с первой поверхности (12а) подложки внутрь подложки (12), так что между первыми канавками (14) формируется множество спейсеров (16) из материала подложки. Устройство (10) с переходными отверстиями в подложке также содержит вторую канавку (18), обеспеченную проводящим материалом и проходящую со второй поверхности (12b) подложки внутрь подложки (12). Вторая канавка (18) соединена с первыми канавками (14). Устройство 10 с переходными отверстиями в подложке также содержит проводящий слой (20), выполненный из проводящего материала и сформированный на стороне первой поверхности ...

ЭЛЕКТРОННЫЙ МОДУЛЬ ДЛЯ ЭЛЕКТРОННОЙ КАРТОЧКИ

Изобретение относится к электронному модулю, предназначенному, в частности, для установки в электронное устройство типа чип-карты. Технический результат - изготовление электронного модуля ограниченной высоты и реализация карточки с большей толщиной на уровне модуля при использовании его в данной карточке, что повышает механическую прочность последней. Модуль содержит подложку, по меньшей мере, одну поверхность с контактными дорожками и микросхему, закрепленную на подложке и имеющую выходные контакты, каждый из которых соединен с контактной дорожкой подложки. Модуль отличается тем, что соединения между выходными контактами и контактными дорожками образованы швами из адгезивного вязкого токопроводящего вещества, нанесенного по методу раздачи из приспособления типа шприца по рельефу между упомянутыми выходными контактами и контактными дорожками. 2 с. и 4 з.п.ф-лы, 3 ил.

СПОСОБ ИЗГОТОВЛЕНИЯ НЕСУЩЕГО ЭЛЕМЕНТА ДЛЯ ПОЛУПРОВОДНИКОВЫХ ЧИПОВ

Изобретение относится к области крепления на твердом теле полупроводниковых приборов и может быть использовано для крепления полупроводниковых чипов на несущем элементе. Несущий элемент для полупроводникового чипа (23), в частности, для монтажа в чип-карте содержит подложку (15), несущую чип (23), и пленку (10) жесткости, ламинированную на несущую чип (23) сторону подложки (15), имеющую выемку (14), размещающую чип (23) и его выводы (24), край которой снабжен рамкой (12), выполненной за одно целое с пленкой (10). Техническим результатом изобретения является упрощение способа изготовления несущего элемента для полупроводниковых чипов. 7 з.п. ф-лы, 5 ил.

СПОСОБ ИЗГОТОВЛЕНИЯ КАРТ ИЛИ ЭЛЕКТРОННЫХ ЭТИКЕТОК

Изобретение относится к технологии изготовления карт или электронных этикеток, на которых установлены электронные компоненты, Сущность изобретения: способ изготовления карт или электронных этикеток путем сборки их из, по меньшей мере, одной тонкой гибкой подложки (7), проводящего слоя (4) и связывающего слоя (1), содержащих, по меньшей мере, один электронный компонент (11), включает в себя следующие этапы: формируют, по меньшей мере, один сегмент (6) в проводящем слое (4), формируют, по меньшей мере, одно окошко (2) в связывающем слое (1), формируют, по меньшей мере, одно окошко (8) в подложке (7), причем указанное окошко (8) предназначено для размещения электронного компонента (11), накладывают и ламинируют связывающий слой (1) и проводящий слой (4) на подложку для того, чтобы обеспечить совпадение отверстий (6), (2), (8), сделанных ранее, выполняют электрическую схему из множества дорожек, и формируют, по меньшей мере, один электрический контакт (4') для электронного компонента (11), ...

СОЕДИНИТЕЛЬНЫЕ ВЫВОДЫ ЭЛЕКТРОННОГО КОМПОНЕНТА (ВАРИАНТЫ), ЭЛЕКТРОННЫЙ КОМПОНЕНТ (ВАРИАНТЫ) И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ (ВАРИАНТЫ)

Использование: микроэлектроника. Сущность изобретения: соединительные выводы электронного компонента предложено выполнять из дисперсионно твердеющего сплава мартенситного или аустенитного типа определенных составов. Предложен электронный компонент с соединительными выводами из указанных сплавов и способы его изготовления. Техническим результатом изобретения является создание соединительных выводов толщиной менее 0,1 мм для электронного компонента, имеющих механическую прочность, достаточную для осуществления различных операций, обеспечение удобства обращения с электронным компонентом и его монтажа на печатной схеме. 7 с. и 10 з.п.ф-лы.

КОНТАКТИРОВАНИЕ ПОЛУПРОВОДНИКОВЫХ МИКРОСХЕМ В ЧИП-КАРТАХ

... 1. Чип-карта, которая имеет корпус (1) чип-карты, полупроводниковую микросхему (3), и закрепленную в корпусе (1) чип-карты подложку (2), с которой полупроводниковая микросхема (3) связана электрически и механически, при этом корпус (1) чип-карты имеет первую полость (10) и вторую полость (20), причем вторая полость (20) выполнена в основании первой полости (10), так что первая полость (10) простирается в боковые стороны над второй полостью (20), и плоскость (15) основания первой полости (10) охватывает вторую полость (20), при этом подложка (2) размещена в первой полости (10) и на своей верхней стороне (11) имеет верхние плоские контакты (4) для считывания чип-карты, а на своей нижней стороне (12) имеет нижние плоские контакты (5), которые посредством проходящих через подложку (2) проводников (6) контактных отверстий электрически связаны друг с другом, при этом полупроводниковая микросхема (3) посредством электрических соединений (9) связана с нижними плоскими контактами (5) подложки (2 ...

ПЕЧАТНАЯ ПЛАТА, СПОСОБ ИЗГОТОВЛЕНИЯ ПЕЧАТНОЙ ПЛАТЫ И СПОСОБ ПЕРЕНАЛАДКИ ЭЛЕКТРОННОГО УЗЛА НА ПЕЧАТНОЙ ПЛАТЕ

... 1. Печатная плата, представляющая собой плоскую подложку с по крайней мере одним посадочным местом для установки сменного выполненного в отдельном корпусе с заданными размерами электронного компонента типа микросхемы, имеющей по крайней мере с одной стороны отдельного корпуса выстроенные в ряд выводные ламели, при этом в зоне посадочного места по количеству выводных ламелей электронного компонента на плоской подложке сформированы в ряд расположенные печатные токопроводящие участки для закрепления на каждом из них соответствующей выводной ламели, соединенные с печатными проводниками для соединения с другими электронными компонентами, размещаемыми на поверхности пластины в соответствии с принципиальной схемой, отличающаяся тем, что параллельно в ряд расположенным печатным токопроводящим участкам для закрепления выводных ламелей сменного электронного компонента на плоской подложке сформирован ряд дополнительных печатных токопроводящих участков для поверхностного монтажа и закрепления выводных ...

СПОСОБ ИЗГОТОВЛЕНИЯ ГИБКИХ ЭЛЕКТРОННЫХ СХЕМ, ИМЕЮЩИХ КОНФОРМНЫЕ МАТЕРИАЛЬНЫЕ ПОКРЫТИЯ

Предложен способ изготовления гибкой электронной схемы. Способ включает образование формы из позитивного фоторезиста на гибкой полимерной подложке, имеющей множество металлических дорожек, нанесение конформного материального покрытия поверх формы из позитивного фоторезиста, гибкой полимерной подложки и металлических дорожек, удаление излишка конформного материального покрытия путем выполнения прохода ножевого полотна над формой из позитивного фоторезиста, удаление формы из позитивного фоторезиста для открывания полости, заданной конформным материальным покрытием, подачу анизотропной проводящей пасты в полость, вставление кристалла в полость и присоединение кристалла к проводящим дорожкам. Изобретение обеспечивает более точный контроль толщины конформного материального покрытия. 3 н. и 15 з.п. ф-лы, 14 ил.

МОДУЛЬ МИКРОСХЕМЫ И СПОСОБ ИЗГОТОВЛЕНИЯ МОДУЛЯ МИКРОСХЕМЫ

... 1. Модуль микросхемы, содержащий расположенное на внешней стороне (2) контактное поле (3) с нескольким изолированными друг от друга, в основном плоскими контактными элементами (4) из электрически проводящего материала, и по меньшей мере, одну полупроводниковую микросхему (6) с одной или несколькими интегральными полупроводниковыми схемами, которые через соединительные выводы (8) электрически соединены с контактными элементами (4) контактного поля (3), причем контактные элементы (4) модуля (1) микросхемы образованы предварительно изготовленным системным носителем (20) (выводной рамкой) для опоры по меньшей мере одной полупроводниковой микросхемы (6) и по меньшей мере на двух противоположных сторонах модуля (1) микросхемы выставленными наружу, проходящими рядами рядом Друг с другом выводами (8), отличающийся тем, что контактные элементы (4) выполнены для поверхностного монтажа модуля (1) микросхемы на монтажной поверхности (9) внешней печатной платы, соответственно, подложки внешней платы ...

СПОСОБ И УСТРОЙСТВО ДЛЯ ОЧИСТКИ, РАЗДЕЛЕНИЯ, МОДИФИКАЦИИ И/ИЛИ ИММОБИЛИЗАЦИИ ХИМИЧЕСКИХ ИЛИ БИОЛОГИЧЕСКИХ ОБЪЕКТОВ, НАХОДЯЩИХСЯ В ТЕКУЧЕЙ СРЕДЕ, И ОПОРА ИЗ МИКРОПРОВОЛОКИ

... 1. Устройство для очистки, разделения, модификации и/или иммобилизации химических или биологических объектов, находящихся в текучей среде, посредством связывания химического или биологического объекта с функциональным покрытием или лигандами, находящимися на поверхности опор из микропроволоки при отсутствии воздействия магнитного поля, создаемого между опорами из микропроволоки и частицами, находящимися в текучей среде, на разделение названных частиц, которое содержит по меньшей мере одну опору из микропроволоки, закрепленную своими концами и имеющую многослойную структуру, состоящую из центрального стержня и по меньшей мере одного покрывающего слоя и пригодную для связывания химических или биологических объектов, при этом поверхность микропроволоки модифицирована путем присоединения лигандов или нанесением на нее функционального покрытия. ! 2. Устройство по п.1, в котором центральный стержень и покрывающие слои выполнены из материала, выбранного из группы, включающей стеклянный, металлический ...

СПОСОБ ИЗГОТОВЛЕНИЯ ЭЛЕКТРОННЫХ ИЛИ ФУНКЦИОНАЛЬНЫХ УСТРОЙСТВ

... 1. Способ изготовления электронного или функционального прибора с множеством электронных или функциональных устройств на гибкой подложке, включающий в себя этапы обеспечения жесткой подложки, имеющей поверхность нанесения; формирования разделительного слоя на этой поверхности нанесения; нанесения множества областей материала на разделительный слой для создания матрицы устройств; снятия матрицы устройств с поверхности нанесения; прикрепления гибкой подложки к упомянутой матрице. 2. Способ по п.1, в котором по меньшей мере некоторые из упомянутого множества областей материала наносят в виде капель жидкости. 3. Способ по п.1 или 2, в котором этап снятия матрицы устройств с поверхности нанесения происходит после этапа прикрепления гибкой подложки к упомянутой матрице. 4. Способ по п.1 или 2, в котором этап прикрепления гибкой подложки происходит непосредственно после этапа формирования разделительного слоя на поверхности нанесения. 5. Способ изготовления электронного или функционального прибора ...

Halbleiteranordnung mit Metallplatte

Elektronische Schaltungsanordnung

Verbesserte Mehrschichtverpackung

Repeated firing resistant ceramic circuit substrate

A low temperature fired ceramic circuit substrate has laminated insulating layers of ceramic fired at 800-1000 deg C, a silver-based conductive wiring in the inner insulating layer and a gold-based conductive wiring on the surface insulating layer, the novelty being that a metallic interlayer (16), formed from a gold/silver-based thick film paste, is provided between the inner layer wiring (15) and the surface layer wiring (17). Preferably, the gold-silver material contains 10-80 wt.% Au and 90-20 wt.% Ag.

Thixotrope Leiterpaste

Verbesserte Glaskeramik-Kupfer-Verklebung.

Verfahren zur Herstellung einer Halbleitervorrichtung mit einem keramischen Substrat und einem integrierten Schaltungskreis

Verfahren zur Herstellung einer elektrischen Verbindung für eine integrierte Schaltung.

Leiterplatte für Plastikhalbleitergehäuse

MEHRSCHICHTIGE LEITERPLATTE

VERFAHREN UND VORRICHTUNG ZUM ZWEIDIMENSIONALEN AUFBAU VON PARTIKELN

Leistungshalbleitermodul mit Keramiksubstrat

Verfahren zur Bildung einer Drahtbondelektrode auf einer Dickschichtleiterplatte

Verfahren zum Herstellen einer Drahtbondelektrode auf einer Dickschichtleiterplatte, bei welcher eine Kupfer-Dickschicht (2) als Verdrahtungsschicht auf einem isolierenden Substrat (1) gebildet ist und ein auf dem isolierenden Substrat angebrachtes Teil (7) elektrisch mit der Kupfer-Dickschicht (2) über einen Golddraht (8) verbunden ist, mit: einem Schritt des Druckens der Kupfer-Dickschicht (2) auf das isolierende Substrat und des Sinterns der Kupfer-Dickschicht zur Bildung der Verdrahtungsschicht; und einem Schritt des Druckens einer Gold-Dickschicht, welcher vor dem Drucken Kupfer hinzugefügt worden ist, auf das isolierende Substrat und des Sinterns der Gold-Dickschicht als Drahtbondelektrode, um wenigstens partiell die Kupfer-Dickschicht zu überlappen, welche auf dem isolierenden Substrat gebildet ist.

MODUL-AUFBAU MIT INTEGRIERTEM HALBLEITERCHIP UND CHIPTRAEGER

Gehäuse einer integrierten Schaltung.

Gehäuse einer integrierten Schaltung.

Filmträger und Verfahren zur Herstellung desselben.

Leitfähige Muster-Schichtstruktur und Verfahren zur Herstellung der leitfähigen Muster-Schichtstruktur

Zusammensetzungen zum Füllen von Durchgangslöchern

Contactless chip card manufacturing method

The manufacturing method has a conductive adhesive (9) applied via a dosing device to the surface of an antenna contact surface (20) incorporated in the card body, for securing a chip module contact surface, the height of the applied conductive adhesive measured via an electrode (35) displaced perpendicular to the chip card surface, with a voltage applied across the antenna contact surface and the measuring electrode, for providing a voltage discharge in the gas-filled space between the measuring electrode and the deposited conductive adhesive. An Independent claim for a device for a manufacture of chip cards is also provided.

LOTTRAEGER, VERFAHREN ZU DESSEN HERSTELLUNG UND VERFAHREN ZUR MONTAGE VON HALBLEITERANORDNUNGEN UNTER DESSEN VERWENDUNG

Ausweiskarte mit IC-Baustein

Halbleitereinheit und Verfahren zu deren Herstellung

Verfahren zum Erreichen einer selektiven Adhäsionshemmung und -steuerung in Dickschicht-Leitern.

Verbindungsleiter bestehend aus einem spiralförmigen Leiterentwurf.

Elektrischer Schaltungsapparat

Elektronisches System enthaltend Komponente, die durch einen thermisch leitfähigen Klebstoff verbunden sind.

System und Verfahren zur Verstärkung einer Anschlussfläche

Mehrschichtige keramische Platine, Verfahren zu ihrer Herstellung und ihre Anwendung.

Elektronisches Bauteil mit einem Halbleiterchip und Verfahren zu seiner Herstellung

Insulating material metal composite substrate, particularly ceramic metal composite substrate, has insulating layer, metal conductive paths, and power elements

The insulating material metal composite substrate has an insulating layer, metal conductive paths, and power elements, where the power element is arranged on a side of the insulating material metal composite substrate. The electrically conductive connecting elements are provided with two ends (30,31). The insulating material metal composite substrate has a metal plate, at which one end of the electrically conductive connecting elements is arranged. The metal plate is an aluminum plate (2).

Verdrahtungssubstrat

Ein Verdrahtungssubstrat umfasst ein Substrat mit einem Verdrahtungsmuster und ein linienförmiges Isoliermuster, das auf dem Substrat derart gebildet ist, daß es das Verdrahtungsmuster schneidet und einen Teil des Verdrahtungsmusters für eine Anschlußbereichselektrode definiert. Das Isoliermuster umfasst eine Mehrzahl von linienförmigen Abschnitten, die miteinander verbunden sind, um eine rahmenartige Struktur zu bilden.

Device to passivate at least one component such as a position sensor has cover connected to front of carrier substrate to form an inner space and electrically isolated connection to the component

A device to passivate at least one component (20) comprises a housing where a cover (50) is connected to the front side (41) of a carrier substrate (40) in a connection region (42) to form an inner space. There is at least one electrically conductive lead to the component that is electrically isolated from the connection region and near at least one part of the connection region between the front side and a back side of the substrate or on the back of the carrier substrate. An independent claim is also included for a method of producing the above.

Connection between sensor terminal and conductor path applied to glass plate uses conductive connection element ultrasonically welded to conductor path

Connection is provided by electrically conductive connection element (11), e.g. bonding wire, which is ultrasonically welded to conductor path (5) applied to surface of glass plate (1) and which is coupled to sensor terminal (13) mounted on glass plate. Surface (3) of glass plate is ridged at point of connection between conductor path and connection element, ultrasonic welding position lying in furrow between 2 ridges (4). An Independent claim for an application of a sensor terminal connection for a ceramic glass cooking hob surface is also included.

Leistungs-Halbleitervorrichtung

Eine Mehrkantmutter (5) zum Aufnehmen einer Klemmschraube (7) ist fest in eine Mutterneinsetzöffnung (6) eingesetzt, die in dem dünnen Bereich (1a) eines Harzgehäuses (1) ausgebildet ist, wobei sich die Mehrkantmutter mit einer Innenfläche (6a) der Mutterneinsetzöffnung (6) in Berührung befindet. Die Innenfläche (6a) der Mutterneinsetzöffnung (6) weist rund ausgebildete, konkave Aussparungsbereiche (6b) an Stellen auf, die einem entsprechenden Eckbereich (5b) der Mehrkantmutter (5) gegenüberliegen, so daß sich die Eckbereiche (5b) der Mehrkantmutter (5) nicht mit dem Harzgehäuseelement in Berührung befinden und dadurch eine Rißbildung des Harzgehäuses verhindert ist.

Chip module e.g. for chip card

The chip module (10) has a chip (11) and a substrate (12) in contact with it and an insulating layer (13) on the substrate. The terminal conductors (14,15) stretch, side by side with a gap, on the insulation layers. The chip is made with two spigots (16,17) that pass through a passivation layer (18) and project beyond this. These spigots are the contact metallisations engaging in the terminal conductors and locate these in position. In addition, to provide good electrical contact between the terminal conductors and the contact region (21) for the chip, the recesses (19) are filled with bonding material (22) which conducts well.

Microwave module comprising substrate with HF and LF layers forming distribution network structures, includes intervening insulating layer

The high frequency structure layer (4) is separated from the low frequency structure layer (3) by the insulating layer (1). An Independent claim is included for the method of manufacture, which especially employs fine pitch flip-chip technology for bonding to the substrate.

Semiconducting chip housing has wiring plane with at least one resistor and/or capacitor in form of board-on-chip ball grid array with wiring structure of one or more layers

The semiconducting chip housing has a wiring plane (2) with at least one resistor (R) and/or capacitor (C). The wiring plane is in the form of a board-on-chip ball grid array and contains a wiring structure of one or more layers. At least one capacitor in the wiring plane decouples an applied voltage.

Leitpaste zum Verschluss von Vias in keramischen Leiterplatten

Solderable electric contact element - has silver@-tin@ alloy layer below gold@-tin@ solder alloy layer

A solderable electric contact element consists of an Fe-Ni alloy backing bearing a layer system of a metallic layer and, on part of the metallic layer surface, a 60-90 wt.% Au/10-40 wt.% Sn solder alloy layer, the novelty being that the metallic layer (3) consists of a 50-90 wt.% Ag/10-50 wt.% Sn alloy. ADVANTAGE - The Ag-Sn alloy layer is less expensive than prior art Au layers but has similar electrical and physico-chemical properties and prevents uncontrolled flow of the Au-Sn solder alloy on the contact element surface.

GITTERANORDNUNG UND VERFAHREN ZU DEREN HERSTELLUNG

Schaltungsmodul

Wolfram/Kupfer-Verbundpulver

Thick film circuit board useful as an IC substrate installed in an automobile engine compartment

A circuit board has a conduction suppressing agent between silver-containing wiring portions to prevent conduction in the silver deposited on the substrate between the wiring portions. Independent claims are also included for the following: (i) an insulating paste composition containing a potassium compound; (ii) a conductive paste composition comprising a dispersion of silver-containing metal powder and an inorganic binder in an organic vehicle and which also contains a potassium compound; (iii) a conductive paste composition comprising an organic dispersion of silver-containing metal powder and an inorganic binder formed of a substance which prevents evaporation of the silver from the metal powder; (iv) a conductive paste composition comprising a dispersion of silver-containing metal powder in an organic vehicle; (v) an insulating paste composition which is used between the wiring portions of the above circuit board and which comprises the conduction suppressing agent; (vi) a conductive ...

Bauelement und Verfahren zur Herstellung des Bauelementes

The invention relates to a component with at least one integrated electronic circuit (20). At least one interposer (10) is located in the area of a main surface of the integrated electronic circuit. According to the invention, the component is characterised in that the interposer (10) is provided with recesses which are essentially vertical in relation to a main surface of the integrated electronic circuit (20).

PACKAGES FOR ENCLOSING SEMICONDUCTOR ELEMENTS

CHIPKARTE MIT EINEM FLEXIBLEN CHIP

Halbleitereinheit

Eine Halbleitereinheit umfasst eine Basis, die eine Oberfläche aufweist, auf der eine erste Isolationsschicht angeordnet ist, eine zweite Isolationsschicht, die von der ersten Isolationsschicht getrennt ist, um einen Bereich dazwischen auszubilden, und die parallel zu der Oberfläche der Basis angeordnet ist, auf der die erste Isolationsschicht angeordnet ist, eine einzelne leitfähige Schicht, die über der ersten Isolationsschicht und der zweiten Isolationsschicht angeordnet ist, und eine Halbleitervorrichtung, die mit der leitfähigen Schicht verbunden ist.

INFILTRIERTE NANOPORÖSE MATERIALIEN UND VERFAHREN ZU DEREN HERSTELLUNG

HALBLEITERGEHÄUSE, HALBLEITERVORRICHTUNG, ELEKTRONIKELEMENT UND HERSTELLUNG EINES HALBLEITERGEHÄUSES

PARALLELEBENENSUBSTRAT

Kugelmatrix-Verbinder

SEMICONDUCTOR PACKAGE

Leiterplatte mit verbesserten Positionierungsmitteln

Electronic component with semiconductor chip, has substrate attached via adhesive layer on to active chip surface

An electronic component with contact surfaces (3) in the region of a bond channel (5) or in bond surfaces in bonding pads and with a substrate (6) glued via an adhesive layer (14) on to the active chip surface, for wiring of the contact connection surfaces, and conductor paths (8), solder contact surfaces (9) and a solder stop layer (12), in which the substrate is provided with expansion joints (15) An Independent claim is given for a method of manufacturing an electronic component.

Semiconductor system comprises substrate with contact pad connected to e.g. solder beads, system being encapsulated on at least five sides and mechanical decoupling system mounted between encapsulation and semiconductor

Semiconductor system comprises a substrate (10) with a contact pad (11) which is connected by conductors (12) to connectors, e.g. solder beads (13). The system is encapsulated (14) on at least five sides and a mechanical decoupling system (15) is mounted between the encapsulation and the semiconductor. An independent claim is included for a method for making the semiconductor system.

Protective coating for electronic device contg. fluorinated acrylate] - and/or fluorinated polyurethane and opt. acrylic] resin, applied as organic soln.

Protective surface coating material for electronic devices consists of (a) 0.01-2 (wt.)% fluorinated acrylate (IA) and/or fluorinated polyurethane ((B) and 99.99-98% completely or partly fluorinated hydrocarbon cpd. (II); or (b) 0.01-2% (I), 1.5-35% acrylic resin (III) and 98.49-63% organic solvent (IV). Pref. (IA) is an N-lower alkyl-perfluoroalkylsulphonamido-acrylic acid, -acrylamide, -acrylonitrile or -alkyl (meth)acrylate; ((B) a reaction prod. of an N-lower alkyl-perfluoroalkylsulphonamidoalkanol and isocyanate; (III) a resin from acrylic acid, alkyl acrylate, methacrylate, acrylonitrile, N-vinylpyrrolidone, styrene or 2-chloro-styrene; and (IV) a mixt. of MEK and butyl acetate. USE/ADVANTAGE - The compsn. is claimed for coating circuit boards and laminated substrates. Good protection is obtd. and selective coating is unnecessary, which improves the efficiency and quality.

nehr feines Nickelpulver

Halbleitervorrichtung mit Metallplatten und Halbleiterchip

Es wird eine Halbleitervorrichtung geschaffen, die aufweist: einen Halbleiterchip (10); eine erste Metallplatte (20), die mittels einer ersten Lötschicht (51) auf einer Seite des Chips (10) angeordnet ist; eine zweite Metallplatte (40), die mittels einer zweiten Lötschicht (52) auf der anderen Seite des Chips (10) angeordnet ist; eine dritte Metallplatte (30), die mittels einer dritten Lötschicht (53) auf der zweiten Metallplatte (40) angeordnet ist; eine Stützeinrichtung (80, 85, 87) zum Halten eines Abstands zwischen dem Chip (10) und der ersten Metallplatte (20) und/oder zwischen dem Chip (10) und der zweiten Metallplatte (40); und eine Aufnahmeeinrichtung (90) zum Aufnehmen von überschüssigem Lot, wenn die dritte Lötschicht (53) das überschüssige Lot aufweist.

Multifunktionaler Schutzschild für mikroelektronische Schaltungen und Sensoren insbesondere für sog. Chip-Karten

Verfahren zur Herstellung von Wolfram-Kupfer-Mischoxiden

Verfahren zur Herstellung eines Wolfram-Kupfer-Mischoxids mit folgenden Stufen: - Mischen äquimolarer Mengen eines Wolframoxids und eines Kupferoxids, wobei das Wolframoxid oder das Kupferoxid oder beide in einer hydratisierten Form vorliegen, - Mahlen der Mischung, - Dehydratisieren der Mischung durch langsames Erhitzen und - Brennen der Mischung an der Luft bei 600 °C bis 800 °C bis zum Abschluss der Umwandlung der Reaktionspartner in CuWO4.

Manufacturing ceramic multilayer circuit of green ceramic foils

Into the green ceramic foils are stamped through contact apertures (1) and filled with an A6 conductive paste. Then A6 etc. conductive path (2) are printed onto the foils. The ceramic foils are assembled into a stack (3) and interconnected by compression, followed by sintering. During and/or after sintering outer A6 conductive paths (4) and/or contacts (5) are deposited onto the outer sides (10) of the foil stack and a metal protection layer, preferably of Ni and/or Au is coated onto the outer conductive paths and/or contacts, i.e. the latter are first coated with an Ni layer and then with an Au film.

Elektrische Baugruppe mit Abstandshaltern zwischen mehreren Schaltungsträgern

Elektrische Baugruppe (1), aufweisend einen Schaltungsträger (2, 23) mit mindestens einem elektrischen Stromkreis (21), der mindestens ein auf einem Oberflächenabschnitt (237) des Schaltungsträgers (2, 23) angeordnetes elektrischen Bauelement (22, 221) aufweist, und mindestens einen weiteren Schaltungsträger (3, 33) mit mindestens einem weiteren elektrischen Stromkreis (31), wobei der Schaltungsträger (2, 23) und der weitere Schaltungsträger (3, 33) derart aneinander angeordnet sind, dass ein Zwischenraum (6) zwischen dem Schaltungsträger (2) und dem weiteren Schaltungsträger (3) vorhanden ist und sich das Leistungshalbleiterbauelement (221) in dem Zwischenraum (6) befindet, der Stromkreis (21) und der weitere Stromkreis (31) über mindestens eine elektrische Verbindungsleitung (5) elektrisch leitend miteinander verbunden sind, das auf dem Oberflächenabschnitt (237) des Schaltungsträgers (2, 21) angeordnete Bauelement (22, 21) dem weiteren Schaltungsträger (3, 33) gegenüberliegend angeordnet ...

Compact semiconductor element comprises a wafer having a chip region, a substrate arranged on the chip region, conducting bodies, a distancing device between the wafer and the substrate and component contacts

Compact semiconductor element comprises a wafer having a chip region, a substrate arranged on the chip region, conducting bodies, a distancing device between the wafer and the substrate and component contacts. Compact semiconductor element comprises a wafer having a chip region (10) with a dielectric contacting assembly surface (101) provided with several contacting spots (100) for the access to the inner circuits of the chip region; a substrate arranged on the chip region of the wafer and having a switching arrangement lying over the assembly surface; conducting bodies (30) arranged between the assembly surface and the switching arrangement surface to connect contacting spots to soldering points; a distancing device between the wafer and the substrate; and component contacts formed on another surface of the substrate opposite the switching arrangement. An Independent claim is also included for a process for the production of the semiconductor element. Preferred Features: The distancing ...

Laminierter Kondensator und Montageanordnung

Laminierter Kondensator mit folgenden Merkmalen: einem Kondensatorkörper (43) mit einem laminierten Stapel einer Mehrzahl von dielektrischen Schichten (42); zumindest einem Paar einer ersten und einer zweiten inneren Elektrode (44, 45), die sich gegenüberliegen, wobei zumindest eine der dielektrischen Schichten (42) zwischen denselben angeordnet ist, in dem Kondensatorkörper (43); einer Mehrzahl von ersten Durchführungsleitern (46), die zumindest eine der dielektrischen Schichten (42) durchdringen und die innerhalb des Kondensatorkörpers (43) vorgesehen sind, wobei die ersten Durchführungsleiter (46) von den zweiten inneren Elektroden (45) elektrisch isoliert und mit den ersten inneren Elektroden (44) elektrisch verbunden sind, und einer Mehrzahl von zweiten Durchführungsleitern (47), die den Kondensatorkörper (43) durchdringen und innerhalb des Kondensatorkörpers (43) vorgesehen sind, wobei die zweiten Durchführungsleiter (47) von den ersten inneren Elektroden (44) elektrisch isoliert ...

Vorrichtung mit mindestens einem Halbleiterbauteil und einer Leiterplatte und Verfahren zur Herstellung einer elektromechanischen Verbindung zwischen beiden

Die Erfindung betrifft eine Vorrichtung mit einem Halbleiterbauteil (1) und einer Leiterplatte (2). Das Halbleiterbauteil (1) weist Außenkontakte (3) und die Leiterplatte (2) weist Kontaktanschlüsse (4) auf. Die Kontaktanschlüsse (4) zeigen eine zentrale Blindöffnung (5), in welche die Außenkontakte (3) des Halbleiterbauteils (1) hineinragen und kraftschlüssig mit den Kontaktanschlussflächen (4) in Eingriff stehen. Bei dem Verfahren zum elektromechanischen Verbinden der beiden Teile zu einer Vorrichtung werden lediglich nach dem Ausrichten die beiden Komponenten aufeinander gepresst.

Semiconductor chip on a carrier and connection process has foil with structured metallization giving electrical contact between chip and carrier surfaces

A semiconductor chip (1) which is permanently attached to a carrier comprises a foil (2) having structured metallization (3) meeting the contact surfaces of the carrier and of the chip to provide electrical connection between them. An Independent claim is also included for a process for connecting the chip and carrier as above.

Electronic component, for use as ceramic module in mobile radio equipment, comprises covering unit and semiconductor chip and/or passive component arranged between substrate and upper covering plate of covering unit

An electronic component comprises a covering unit (3) and a semiconductor chip and/or passive component arranged between a substrate and an upper covering plate (2) of the covering unit. The covering unit is supported on the surface of the substrate via a spacer (5). The substrate has metal-coated corner regions (6, 7, 8, 9) electrically or mechanically connected to corresponding molded corner region (10-13) of the covering unit. An Independent claim is also included for the production of an electronic component. Preferred Features: A metal layer (14-17) is applied to the corner regions in a thickness of 0.5-500 microns m.

Multilayer circuit module for wireless communication system has passive high frequency components and passive base component layer

A connection integration region includes at least one connecting layer (404,408) for electrically coupling the circuit components (409). A passive base component integration region has a passive base component layer (405,407). A passive high frequency component integration region comprises passive high frequency components. An Independent claim is included for a method of manufacturing a multilayer circuit module.

Leistungshalbleitermodul

Es wird ein Leistungshalbleitermodul offenbart. Eine Ausführungsform enthält ein Mehrschichtsubstrat mit mehreren Metallschichten und mehreren Keramikschichten, wobei die Keramikschichten zwischen den Metallschichten liegen.

A method of manufacturing an integrated circuit package and an integrated circuit package

A method of manufacturing an integrated circuit package

SEMICONDUCTOR DEVICE ARRANGEMENTS

... 1403371 Semi-conductor devices MULLARD Ltd 15 Nov 1972 [12 Jan 1972 5 May 1972] 1390/72 and 21029/72 Heading H1K The invention relates to a wiring arrangement, e.g. for a motor vehicle, in which semi-conductor devices are mounted on a flexible service strip 1 (Fig. 1) comprising a plurality of conductors 2, 3 on a flexible insulating strip 4 so that the device terminals are connected to the conductors 2, 3. Each device comprises a semi-conductor element, such as a thyristor or a switching transistor 11 (Fig. 6) including an integrated emitterbase resistor, mounted on a metal carrier 10 which constitutes one terminal, electrodes 15, 16 on the upper surface of the element 11 being contacted by metal foil conductors 21, 22 isolated from the carrier 10 by an insulating backing 23. Various modifications of the foil structure 12 including conductors 21, 22 and and backing 23 are described. Flat contact areas 25, 26 of the conductors 21, 22, and in some cases also of the metal carrier 10, are ...

METHODS OF MANUFACTURING SEMI-CONDUCTOR DEVICES

... 1435320 Semi-conductor devices PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 25 April 1973 [28 April 1972] 19596/73 Heading H1K Conductive tracks which overlie an insulating layer of a planar semi-conductor device and contact zones of the device through apertures in the layer are formed by depositing lower and upper auxiliary layers over the insulating layer, forming therein a pattern of apertures corresponding to areas where conductive tracks are not required, the apertures being somewhat larger in the lower auxiliary layer due to undercutting, depositing one or more conductive layers overall and then etching away either or both of the auxiliary layers in order to remove the overlying conductive layers to leave the desired tracks in the apertures. Particularly if the combined thickness of the auxiliary layers is greater than that of the conductive layers the undercutting causes discontinuity or thinning of the conductive layers at the edges of the apertures, this facilitating etching ...

MOUNTING OF ELECTRONIC DEVICES

CARRIER SUBSTRATE AND METHOD FOR PREPARING THE SAME

Process for Packaging Multilead Semiconductor Devices and Resulting Product.

... 1,197,751. Semi-conductor devices. TEXAS INSTRUMENTS Inc. 18 July, 1967 [29 July, 1966], No. 33023/67. Heading H1K. A semi-conductor body 48 containing an integrated circuit is positioned in an aperture in an insulating support 42 so that contact pads on the body 48 engage the ends 46a of conductive strips 46 on the support 42, which ends 46a overlap the aperture. The outer ends 46b, which extend to or almost to the periphery of the support 42, are at least as far apart as the inner ends 46a and, in the embodiment shown, comprise lands to which are attached terminal pins 50 extending through the support 42 to enable the assembly to be plugged into a socket. Plastics encapsulant 52 encloses the assembly. In another embodiment tapering conductive strips (86), Fig. 8 (not shown), extend radially from a semi-conductor body (88) situated in a circular aperture (84) in the insulating support (82), and terminate at the four outer edges of the support (82). A heatconducting metal plate (90) is ...

PACKAGE FOR AN ELECTRONIC ASSEMBLY

... 1,256,332. Component assemblies. NORTH AMERICAN ROCKWELL CORP. 11 June, 1970, No. 28398/70. Heading H1R. [Also in Division H2] A package for circuit boards 12 to 17 comprises a housing formed by walls 8 to 11, base 6 and cover 5, the walls having ridges 21 forming slots 20 mating with and supporting the boards, and conductive strips 30 to contact and interconnect edge contacts 31 on the boards. Preferably the walls overlap adjacent wall edges sequentially (Fig. 5, not shown) and strips 35, 36 of fusible metal are provided for bonding the assembly by heating. Conductive strips 30 may also be of fusible metal. As shown the cover 5 supports contact pins 18 connected to printed circuitry on its lower surface, and a socket shroud 3 accommodates cable plugs 4 making contact with pins 18.

"CARRIER SUBSTRATE FOR ELECTRICAL CIRCUIT ELEMENT "

PURPOSE:To form a thin film circuit element having required accuracy without necessitating trimming by providing an electrode layer for connection to the circuit element on the topmost layer of insulating films, providing an element layer having the thin film circuit on any of other insulating films, and providing conductor wirings for connecting the electrode layer and external connecting terminals through the element layer. CONSTITUTION:Insulating layers 9a, 9b and 9c are formed on an insulating board. A thin film circuit element such as a thin film resistor is formed thereon. Therefore, irregularities, warping and the like on the surface of the insulating board, e.g. a ceramic substrate 6 are absorbed with the insulating films. The thin film circuit element is formed without the effects of the roughness of the surface of the insulating board. Therefore, the circuit element having the desired constants can be formed accurately. As a result, correction such as trimming is not required.

CERAMIC SUBSTRATE FOR HYBRID MICROCIRCUITS AND METHOD OF MAKING THE SAME

Hybrid laminate

A hybrid laminate comprises: a substrate layer containing a compact of first powders; and a functional material layer being in contact with the substrate layer and containing a compact of second powders; wherein the compact of the first powders comprises a glass material; the compact of the second powders comprises a ceramic material having at least one specific electric property selected from dielectricity, magnetism, resistivity and insulation; at least a part of the first powders is in a sintered state; and the second powders are in an unsintered state and are bonded together by diffusion or a flow of a part of the material of the substrate layer into the functional material layer.

A printed circuit board assembly including an interposer

A printed circuit board assembly includes a printed circuit board 22 having a first coefficient of thermal expansion, an integrated circuit die 24 having a base formed from a material having a second coefficient of thermal expansion, and an interposer 30 having a coefficient of thermal expansion intermediate the first and second coefficients of thermal expansion for electrically connecting the board 22 and the die 24. The interposer may be formed from a sheet of material with through holes 32 for electrically connecting the die to the board when a conductive material 26, 28 fills the holes. Alternatively, the interposer may have legs for connecting the die to the board (figure 5). The interposer may be formed from a powdered metal injection molding compound or a polyimide of bismuth telluride. The interposer may be used to connect a silicon based switch such as a field effect transistor to a glass epoxy based PCB.

SOLDERABLE ADHESIVE LAYER

INTEGRAL PROTECTIVE ENCLOSURE FOR AN ASSEMBLY MOUNTED ON A FLEXIBLE PRINTED CIRCUIT BOARD

Described is a flexible electrical assembly comprising a TAB device mounted on one surface of a flexible printed circuit board, a heat sink with a set of crimping members thereon mounted on an opposite surface of the printed circuit board and a protective cover with attachment holes therein positioned above the TAB device. The protective cover is mounted so that the holes are aligned with similar ones in the printed circuit board. The crimping members are inserted through the holes and are folded onto the protective cover to form a unified structure.

Molecular synthesis

Molecular synthesis is carried out on a substrate (1) provided with a nanofabricated surface structure (2, 3) typically formed by means of a scanning tunneling microscope. The resulting surface structure acts as a molecular template and components parts of a molecular structure are moved to the template e.g. by control potentials applied to surface electrodes (4) formed by electron beam lithography on the substrate. A long molecular chain can be assembled using the substrate to form the chain from a plurality of component molecular parts. Alternatively, the substrate, with the assembled molecular chain, can be used as a catalyst. ...

Integral copper column withsolder bump flip-chip

Wiring board and method for manufacturing the same

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Electronic module with vertical connector between conductor patterns

The present invention generally relates to a new structure to be used with electronic modules such as printed circuit boards and semiconductor package substrates. Furthermore there are presented herein methods for manufacturing the same. According to an aspect of the invention, the aspect ratio of through holes is significantly improved. Aspect ratio measures a relationship of a through hole or a micro via conductor in the direction of height divided width. According to the aspect of the invention, the aspect ratio can be increased over that of the prior art solution by a factor of ten or more.

Circuit substrate and manufacturing method thereof and package structure and manufacturing method thereof

A circuit substrate includes the following elements. A conductive layer and a dielectric layer are disposed on an inner circuit structure in sequence, and a plurality of conductive blind vias are embedded in the dielectric layer and connected to a portion of the conductive layer. A plating seed layer is disposed between each of the first blind vias and the first conductive layer. Another conductive layer is disposed on the dielectric layer, wherein a portion of the another conductive layer is electrically connected to the conductive layer through the conductive blind vias. A third plating seed layer is disposed between the third conductive layer and each of the first blind vias and on the first dielectric layer.

Energy Conditioning Circuit Arrangement for Integrated Circuit

The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

Flexible circuit structure with stretchability and method of manufacturing the same

In one example embodiment, a flexible circuit structure with stretchability is provided that includes a flexible substrate, a plurality of flexible bumps formed on the flexible substrate, and a metal layer formed on the plurality of flexible bumps and the flexible substrate.

Semiconductor chip device with polymeric filler trench

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Multi-function and shielded 3d interconnects

A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

Semiconductor device having semiconductor member and mounting member

A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.

Multilayer printed wiring board and method for manufacturing multilayer printed wiring board

A method for manufacturing a multilayer printed wiring board includes preparing a first resin insulative material having a first conductive circuit on or in the first resin insulative material, forming a second resin insulative material on the first resin insulative material and the first conductive circuit, forming on a surface of the second resin insulative material a first concave portion to be filled with a conductive material for formation of a second conductive circuit, forming on the surface of the second resin insulative material a pattern having a second concave portion and post portions to be filled with the conductive material for formation of a plane conductor, and filling the conductive material in the first concave portion and the second concave portion such that the second conductive circuit and the plane conductor are formed.

Circuit Board Packaged with Die through Surface Mount Technology

A package of a circuit board and a die are packed through surface mount technology (SMT). The shortest circuit is formed with at a low cost. Thus, the package can work in high speed and high frequency applications.

Package with embedded chip and method of fabricating the same

A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.

Method of manufacturing multilayer wiring substrate

A method of manufacturing a multilayer wiring substrate is provided. A foil of a metal-foil-clad resin insulation material is brought into contact with a foil of a metal-foil-clad support substrate. A peripheral edge portion of the resin insulation material exposed as a result of removal of a peripheral edge portion of the foil is adhered to the foil of the support substrate. A plurality of conductor layers and a plurality of resin insulation layers are laminated so as to obtain a laminate structure having a wiring laminate portion, which is to become the multilayer wiring substrate. The laminate structure is cut along a boundary between the wiring laminate portion and a surrounding portion, and the surrounding portion is removed. The wiring laminate portion is separated from the support substrate along the boundary between the two foils.

Through wiring substrate and manufacturing method thereof

A through wiring substrate includes a substrate having a first face and a second face; and a through-wire formed by filling, or forming a film of, an electrically-conductive substance into a through-hole, which penetrates between the first face and the second face. The through-hole has a bend part comprising an inner peripheral part that is curved in a recessed shape and an outer peripheral part that is curved in a protruding shape, in a longitudinal cross-section of the through-hole, and at least the inner peripheral part is formed in a circular arc shape in the longitudinal cross-section.

Method of manufacturing circuit board

Disclosed herein is a method of manufacturing a circuit board. The method of manufacturing a circuit board according to a preferred embodiment of the present invention is configured to include (A) forming a cavity 115 for a bump on one surface 111 of a carrier 110, (B) forming a bump 130 in the cavity 115 for the bump through an electroplating process, (C) laminating an insulating layer 140 on one surface 111 of the carrier 110 so as to apply the bump 130, (D) forming a circuit layer 150 including a via 155 connected with the bump 130 on the insulating layer 140, and (E) removing the carrier 110, whereby the process of forming separate solder balls is removed by forming the cavities 111 for the bumps in the carriers 110 to form the bumps, thereby simplifying the process of manufacturing a circuit board and reducing the lead time.

Printed circuit board and method for manufacturing the same

Disclosed herein are a printed circuit board and a method for manufacturing the same. The method for manufacturing a printed circuit board includes: (a) forming at least one plate through hole penetrating through an insulating layer; (b) forming pattern grooves for implementing inner layer circuits on both surfaces of the insulating layer; and (c) filling the plate through hole and the pattern grooves with a conductive material. The method for manufacturing a printed circuit board may provide the printed circuit board having excellent heat radiating characteristics and reduce process cost.

Integrated circuit packaging system with connection structure and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

Laminated wiring board

In a multilayer wiring board 1, a low resistance silicon substrate 2 having a predetermined resistivity and a high resistance silicon substrate 4 having a resistivity higher than the predetermined resistivity are stacked while interposing an insulating layer 3 therebetween. The low resistance silicon substrate 2 is provided with an electric passage part 6 surrounded by a ring-shaped groove 5, while a wiring film 13 electrically connected to the electric passage part 6 through an opening 8 of the insulating layer 3 is disposed on a rear face 4 b of the high resistance silicon substrate 4 and an inner face 11 a of a recess 11. Since the high resistance silicon substrate 4 is thus provided with the wiring film 13, an optical semiconductor element 20 and an electronic circuit element 30 which differ from each other in terms of the number and positions of electrode pads can be electrically connected to each other on the front and rear face sides of the multilayer wiring board 1.

Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

Reduced pth pad for enabling core routing and substrate layer count reduction

Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.

Composition for filling through silicon via (tsv), tsv filling method and substrate including tsv plug formed of the composition

Provided is a composition for filling a Through Silicon Via (TSV) including: a metal powder; a solder powder; a curable resin; a reducing agent; and a curing agent. A TSV filling method using the composition and a substrate including a TSV plug formed of the composition are also provided.

Semiconductor package and method of manufacturing the same

Provided are a semiconductor package and a method of manufacturing the same. a substrate including a first face and a second face, wherein the first and second faces face each other; a first ground pattern disposed on the first face; a second ground pattern disposed on the second face; a plurality of ground via plugs which connect the first ground pattern and the second ground pattern, wherein the plurality of ground via plugs penetrate the substrate; and a first aluminum oxide film interposed between the plurality of ground via plugs, wherein a ground voltage is applied to the plurality of ground via plugs. The semiconductor package may be manufactured using an anodic oxidation process.

Packaging substrate with conductive structure

A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

Packaged semiconductor device for high performance memory and logic

A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.

Manufacturing method of semiconductor device, semiconductor device and mobile communication device

A manufacturing method of a semiconductor device includes: sealing a semiconductor chip with a sealing resin containing a filler; exposing a part of the filler; etching at least a part of the exposed filler; and forming a metal film at least at a part of a surface of the sealing resin including inner surfaces of holes formed at the surface of the sealing resin by the etching.

Semiconductor device and noise suppressing method

A first semiconductor chip ( 200 ) is mounted on a second semiconductor chip ( 100 ). The first semiconductor chip ( 200 ) has a first conductor pattern ( 222 ). The second semiconductor chip ( 100 ) has a second conductor pattern ( 122 ). The second conductor pattern ( 122 ) is formed at a region overlapping the first conductor pattern ( 222 ) in a plan view. At least one element selected from a group consisting of the first conductor pattern ( 222 ) and the second conductor pattern ( 122 ) has a repetitive structure.

Package 3D Interconnection and Method of Making Same

A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members.

Wiring substrate and method of manufacturing the same

A wiring substrate includes a structure in which a plurality of wiring layers are stacked through insulating layers intervening therebetween, and which has a first surface side and a second surface side, the first surface side where a semiconductor element is to be mounted, the second surface side being located at an opposite side to the first surface side, an interposer buried in an outermost one of the insulating layers located at the first surface side, and electrically connected to the semiconductor element to be mounted, and a sheet-shaped member buried in an outermost one of the insulating layers located at the second surface side, wherein, the interposer and the sheet-shaped member are disposed at symmetrical positions symmetrical each other.

Signal routing Optimized IC package ball/pad layout

This invention provides layout schemes for ball/pad regions on a printed circuit board for a small regular ball/pad region grid that provides additional space between ball/pad regions for increased wiring capability. The layout scheme is consistent with printed circuit board manufacturing requirements and minimum wiring channel requirements demanded by high density integrated circuit chips.

System and method for improving frequency response

An electrical system and method for making the same includes a main circuit board and a plurality of contact pads located on a surface of the main circuit board. The contact pads are electrically conductive. Additionally, an integrated circuit package having at least one electrical device is attached to the surface of the main circuit board. A ball grid array made from a plurality of solder balls is located on a bottom side of the integrated circuit package. The ball grid array has a plurality of solder balls being electrically conductive and in electrical communication with the at least one electrical device. The solder balls further include solder balls of different material properties.

Coreless layer laminated chip carrier having system in package structure

A substrate for use in a laminated chip carrier (LCC) and a system in package (SiP) device having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can include thermoset and thermoplastic resin.

Packaging substrate and method of fabricating the same

A packaging substrate includes a core board having a first surface and an opposite second surface; at least a conic through hole formed in the core board and penetrating the first and second surfaces; a plurality of conductive paths formed on a wall of the conic through hole, free from being electrically connected to one another in the conic through hole; and a plurality of first circuits and second circuits disposed on the first and second surfaces of the core board, respectively, and being in contact with peripheries of two ends of the conic through hole, wherein each of the first circuits is electrically connected through each of the conductive paths to each of the second circuits. Compared to the prior art, the packaging substrate has a reduced number of through holes or vias and an increased overall layout density.

Semiconductor device

A semiconductor device includes a first semiconductor chip provided with a first semiconductor element including a plurality of element electrodes; and a first substrate having an element mounting surface on which the first semiconductor chip is mounted. The first substrate includes a plurality of first electrodes, each formed on the element mounting surface; a plurality of first interconnects connected to the first electrodes; a plurality of second electrodes formed on a surface opposite to the element mounting surface; a plurality of second interconnects connected to the second electrodes; a plurality of through-hole interconnects penetrating the first substrate and connecting the first interconnects to the second interconnects; and a third semiconductor element. The first side of the first substrate is shorter than the first side of the first semiconductor chip.

Wiring Board, Semiconductor Device, and Method for Manufacturing Wiring Board

A wiring board provided with a silicon substrate including a through hole that communicates a first surface and a second surface of the silicon substrate. A capacitor is formed on an insulating film, which is applied to the silicon substrate, on the first surface and a wall surface defining the through hole. A capacitor part of the capacitor includes a first electrode, a dielectric layer, and a second electrode that are sequentially deposited on the insulating film on the first surface and the wall surface of the through hole. A penetration electrode is formed in the through hole covered by the first electrode, the dielectric layer, and the second electrode of the capacitor part.

Chip-packaging module for a chip and a method for forming a chip-packaging module

A chip-packaging module for a chip is provided, the chip-packaging module including an isolation material configured to cover a chip on at least one side, the isolation material having a first surface proximate to a first side of a chip, and said isolation material having a second surface facing an opposite direction to the first surface; and at least one layer in connection with the chip first side, the at least one layer further configured to extend from the chip first side to the second surface of the isolation material.

Construction of reliable stacked via in electronic substrates - vertical stiffness control method

A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 μm. The platted through hole landing includes an etched pattern and a copper top surface.

Method for electrical connection between elements of a three-dimensional integrated structure and corresponding device

A link device for three-dimensional integrated structure may include a module having a first end face designed to be in front of a first element of the structure, and a second end face designed to be placed in front of a second element of the structure. The two end faces may be substantially parallel, and the module including a substrate having a face substantially perpendicular to the two end faces and carrying an electrically conducting pattern formed in a metallization level on top of the face and enclosed in an insulating region. The electrically conducting pattern may include a first end part emerging onto the first end face and a second end part emerging onto the second end face and connected to the first end part.

Low-noise flip-chip packages and flip chips thereof

A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit.

Semiconductor element-embedded substrate, and method of manufacturing the substrate

A semiconductor element-embedded substrate includes a semiconductor element; a chip component; a peripheral insulating layer covering at least the outer circumferential side surfaces thereof; an upper surface-side wiring line provided on the upper surface side of the substrate; and a lower surface-side wiring line provided on the lower surface side of the substrate. The built-in semiconductor element includes a terminal on the upper surface side thereof, and this terminal is electrically connected to the upper surface-side wiring line. The built-in chip component includes an upper surface-side terminal electrically connected to the upper surface-side wiring line; a lower surface-side terminal electrically connected to the lower surface-side wiring line; and a through-chip via penetrating through the chip component to connect the upper surface-side terminal and the lower surface-side terminal.

Circuit board, semiconductor device, process for manufacturing circuit board and process for manufacturing semiconductor device

A circuit board ( 1 ) exhibits an average coefficient of thermal expansion (A) of the first insulating layer ( 21 ) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point of equal to or higher than 3 ppm/degrees C. and equal to or lower than 30 ppm/degrees C. Further, an average coefficient of thermal expansion (B) of the second insulating layer ( 23 ) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point is equivalent to an average coefficient of thermal expansion (C) of the third insulating layer ( 25 ) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point. (B) and (C) are larger than (A), and a difference between (A) and (B) and a difference between (A) and (C) are equal to or higher than 5 ppm/degrees C. and equal to or lower than 35 ppm/degrees C.

Laminated and sintered ceramic circuit board, and semiconductor package including the circuit board

A circuit board that can decrease thermal stress acting between a semiconductor element and a board in association with temperature alteration and has high mechanical strength (rigidity) as a whole board (including a multilayer wiring layer) is provided. Ceramic base material having a coefficient of thermal expansion close to that of a semiconductor element and inner layer wiring are integrally sintered, and the circuit board is configured so that fine-lined conductor structure corresponding to a multilayer wiring layer in the inner layer wiring has predetermined width, intralayer interval and interlayer interval. Thereby, thermal stress acting between a semiconductor element and the board when the board is exposed to temperature alteration in a condition where it is joined with the semiconductor element is suppressed, rigidity of the board is maintained, and its reliability against temperature cycle is increased.

Integrated circuit package including a direct connect pad, a blind via, and a bond pad electrically coupled to the direct connect pad

An integrated circuit package including a semiconductor die and a flexible circuit (flex circuit), and a method for forming the integrated circuit package. The flex circuit can include a direct connect pad which is not electrically coupled to an active trace, a blind via electrically coupled to the direct connect pad, and a semiconductor die having a bond pad which is electrically coupled to the direct connect pad using a conductor. The bond pad, the conductor, the direct connect pad, and the blind via can all be vertically aligned, each with the other.

Method of forming microstructures, laser irradiation device, and substrate

A microstructure forming method includes a step A of irradiating a region of a substrate, in which a hole-shaped or groove-shaped microstructure is to be formed, with a circularly or elliptically polarized laser beam having a pulse width of which the pulse duration is on the order of picoseconds or shorter, and scanning a focal point at which the laser beam converges to form a modified region, and a step B of performing an etching process on the substrate in which the modified region is formed and removing the modified region to form a microstructure.

Fabrication method of packaging substrate having through-holed interposer embedded therein

A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.

Substrate Dicing

A method and apparatus for separating a substrate into individual dies and the resulting structure is provided. A modification layer, such as an amorphous layer, is formed within the substrate. A laser focused within the substrate may be used to create the modification layer. The modification layer creates a relatively weaker region that is more prone to cracking than the surrounding substrate material. As a result, the substrate may be pulled apart into separate sections, causing cracks the substrate along the modification layers. Dice or other components may be attached to the substrate before or after separation.

Method for manufacturing a circuit device

A semiconductor substrate and a copper sheet stacked with an insulating resin layer are bonded together at a temperature of 130° C. or below (first temperature) so that an element electrode provided on the semiconductor substrate connects to the copper sheet before a thinning process. Then the semiconductor substrate and the copper sheet, on which the insulating resin layer has been stacked, are press-bonded at a high temperature of 170° C. or above (second temperature) with the copper sheet thinned to thickness of a wiring layer. Then the wiring layer (rewiring) is formed by patterning the thinned copper sheet.

Surface acoustic wave device and production method therefor

A surface acoustic wave device includes a surface acoustic wave element including a plurality of electrode pads, and a mount substrate. The surface acoustic wave element is flip-chip mounted on a die-attach surface of the mount substrate by bumps made of Au. The mount substrate includes at least one resin layer including via-holes, a plurality of mount electrodes provided on the die-attach surface of the mount substrate, and via-hole conductors. The mount electrodes are bonded to the electrode pads via the bumps. The via-hole conductors are provided in the via-holes. At least one of each of the electrode pads and each of the mount electrodes includes a front layer made of Au. At least one of the via-hole conductors is located below the corresponding bump.

High io substrates and interposers without vias

An interconnection component includes a substrate having first and second opposed major surfaces defining a thickness of less than 1000 microns and a first slot extending between the first and second surfaces, the first slot being enclosed by the substrate at the first and second surfaces. The first slot defines an edge surface between the first surface and the second surface. First conductive traces extend along the first surface and are electrically connected with first contact pads that overlie the first surface. Second conductive traces extend along the second surface and electrically connected with second contact pads that overlie the second surface. Interconnect traces extend along the edge surface of the first slot. Each interconnect trace directly connects at least one first trace with at least one second trace.

SURFACE DEPRESSIONS FOR DIE-TO-DIE INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS

Stacked microelectronic dies employing die-to-die interconnects and associated systems and methods are disclosed herein. In one embodiment, a stacked system of microelectronic dies includes a first microelectronic die, a second microelectronic die attached to the first die, and a die-to-die interconnect electrically coupling the first die with the second die. The first die includes a back-side surface, a surface depression in the back-side surface, and a first metal contact located within the surface depression. The second die includes a front-side surface and a second metal contact located at the front-side surface and aligned with the first metal contact of the first die. The die-to-die interconnect electrically couples the first metal contact of the first die with the second metal contact of the second die and includes a flowable metal layer that at least partially fills the surface depression of the first die. 1. An interconnect structure for electrically coupling a first microelectronic die with a second microelectronic die , comprising:a metal interconnect extending through the first die to a back-side of the first die and projecting beyond a recessed surface at the back-side of the die;a metal contact of the second die aligned with the interconnect; anda layer of reflowed metal at least partially surrounding the interconnect and electrically coupling the interconnect to the metal contact of the second die, the layer of reflowed metal conforming to a shape defined by the recessed surface, the interconnect, and the metal contact of the second die.2. The interconnect structure of claim 1 , further comprising a dielectric layer positioned between the layer of reflowed metal and the recessed surface of the substrate.3. The interconnect structure of claim 1 , further comprising an under bump metallization layer positioned between the layer of reflowed metal and a portion of the interconnect.4. The interconnect structure of wherein the recessed surface claim 1 , the ...

Forming Packages Having Polymer-Based Substrates

A method includes applying a polymer-comprising material over a carrier, and forming a via over the carrier. The via is located inside the polymer-comprising material, and substantially penetrates through the polymer-comprising material. A first redistribution line is formed on a first side of the polymer-comprising material. A second redistribution line is formed on a second side of the polymer-comprising material opposite to the first side. The first redistribution line is electrically coupled to the second redistribution line through the via.

Integrated circuit packaging system with encapsulation and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate first side and a substrate second side opposite the substrate first side; attaching a base integrated circuit to the substrate first side; attaching a mountable integrated circuit to the substrate second side; attaching a via base to the substrate second side adjacent the mountable integrated circuit; forming a device encapsulation surrounding the via base and the mountable integrated circuit; and forming a via extension through the device encapsulation and attached to the via base, the via extension exposed from the device encapsulation.

Wiring substrate and method of manufacturing the same

Embodiments of the present invention provide a wiring substrate which is excellent in terms of the reliability of connection between the wiring substrate and a semiconductor chip. In some embodiments the wiring substrate comprises a first build-up layer in which resin insulation layers and conductor layers are laminated alternately. The outermost conductor layer can include a plurality of connection terminal portions to which a semiconductor chip is flip-chip connected. The plurality of connection terminal portions can be exposed through openings of a solder resist layer. Each of the connection terminal portions includes a connection region to which a connection terminal of the semiconductor chip is to be connected, and a wiring region which extends in a planar direction from the connection region and which is narrower than the connection region. The surface of the wiring region has a solder wettability lower than that of the surface of the connection region.

SEMICONDUCTOR DEVICE

A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided at the support substrate in relation to the high frequency electrode, and an external connection electrode that is provided on the other side of the support substrate in relation to the via hole. 1. A semiconductor device comprising:a substrate;a first semiconductor element that is mounted on one side of the substrate;a second semiconductor element including a first electrode that is mounted on the one side of the substrate;a second electrode that is provided on the other side of the substrate connects to the first electrode with a via hole that penetrates through the substrate;wherein the first electrode is positioned within a periphery of the via hole;the second semiconductor element includes rewiring that forms a passive element; andthe substrate and the first semiconductor and the second semiconductor are integrally sealed by molded resin.2. The semiconductor device as claimed in claim 1 , whereinthe first semiconductor element is stacked on the second semiconductor element.3. The semiconductor device as claimed in claim 1 , whereinthe second semiconductor element includes a shield member that is set to ground potential.4. The semiconductor device as claimed in claim 1 , whereinthe second semiconductor element includes a pair of re-wiring structures that include portions that are parallel to each other.5. The semiconductor device as claimed in claim 1 , whereinthe second semiconductor element includes a set of re-wiring structures that have substantially equivalent wiring lengths.6. The semiconductor device as claimed in claim 1 , wherein the via hole related to the first electrode has a diameter larger than a diameter of a second via hole connected to a ...

Radiation-shielded semiconductor device

A semiconductor device is disclosed including an electromagnetic radiation shield. The device may include a substrate having a shield ring defined in a conductance pattern on a surface of the substrate. One or more semiconductor die may be affixed and electrically coupled to the substrate. The one or more semiconductor die may then be encapsulated in molding compound. Thereafter, a metal may be plated around the molding compound and onto the shield ring to form an EMI/RFI shield for the device.

Semiconductor device, electronic device, and semiconductor device manufacturing method

A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on witch a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration.

Ball Grid Array with Improved Single-Ended and Differential Signal Performance

An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns. 13-. (canceled)4. An integrated circuit package comprising a plurality of pins comprising:a plurality of pins, the plurality of pins comprising a first pin, a second pin, a third pin, and a fourth pin, each of the first, second, third, and fourth extending externally to the integrated circuit package, being linearly arranged in a first row and being equally spaced from each other;a fifth pin, a sixth pin, a seventh pin, an eighth pin and a ninth pin extending externally to the integrated circuit package, linearly arranged in a second row separated vertically from the first row and offset horizontally from the first row such that sixth, seventh, eighth and ninth pins are offset from the pins in the first row;wherein said third and seventh pins comprise power/ground pins; andwherein the remaining pins are configured for use as signal pins.5. The integrated circuit package of wherein:an arrangement of the plurality of pins is repeated within the integrated circuit package;the arrangement of the plurality of pins provides equally spaced sets of the plurality of pins.6. The integrated circuit package of wherein:the arrangement of the plurality of pins provides power/ground pins positioned substantially zigzagged across a plurality of rows.7. The integrated circuit package of wherein:the arrangement of the plurality of pins provides power/ground pins positioned substantially diagonally across a plurality of rows.8. The integrated circuit package of wherein:the arrangement of the plurality of pins provides power/ground pins positioned such that each power/ground pin is offset from a group of hexagonally configured signal pins.9. An integrated circuit package comprising: a first ...

MULTIMEDIA PROVIDING SERVICE

Provided is a semiconductor device of higher density, thin thickness and low cost not plagued with low reliability ascribable to concentration of internal stress in an ultimate product. The semiconductor device includes a semiconductor element, and a support substrate arranged on a surface of the semiconductor element opposite to its surface provided with a pad. The support substrate is wider in area than the semiconductor element. The semiconductor device also includes a burying insulating layer on the support substrate for burying the semiconductor element in it, and a fan-out interconnection led out from the pad to an area on the burying insulating layer lying more peripherally outwardly than the semiconductor element; and a reinforcement portion arranged in a preset area above the outer periphery of the semiconductor element for augmenting mechanical strength of the burying insulating layer and the fan-out interconnection (FIG. ). 1. A semiconductor device comprising:a semiconductor element;a support substrate arranged on a surface of said semiconductor element opposite to a surface thereof provided with a pad; said support substrate being bigger in area than said semiconductor element;a burying insulating layer on said support substrate for burying said semiconductor element therein;a fan-out interconnection led out from said pad to an area on said burying insulating layer extending to an area lying more peripherally outwardly than said semiconductor element; anda reinforcement portion via interconnection connected to at least one end of said semiconductor element without being connected to said fan-out interconnection.2. The semiconductor device according to claim 1 , whereinsaid reinforcement portion via interconnection is formed of the same material as that of said fan-out interconnection.3. The semiconductor device according to claim 1 , whereinsaid reinforcement portion via interconnection has a modulus of elasticity higher than that of said fan-out ...

PACKAGE OF ELECTRONIC DEVICE INCLUDING CONNECTING BUMP, SYSTEM INCLUDING THE SAME AND METHOD FOR FABRICATING THE SAME

A package of an electronic device, a system including the same and a method for fabricating the same are provided. The package of the electronic device includes a substrate, a step difference layer and a connecting bump. The substrate allows a connecting contact part to be exposed on a surface thereof. The step difference layer covers the substrate so as to leave the connecting contact part exposed. The connecting bump is connected to the connecting contact part so that one end part of the connecting bump is extended on the step difference layer, and has a sloped upper surface formed by a step difference formed by the step difference layer. 1. A package of an electronic device , comprising:a substrate configured to allow a connecting contact part to be exposed on a surface thereof;a step difference layer configured to cover the substrate so as leave the connecting contact part exposed; anda connecting bump configured to be connected to the connecting contact part so that one end part of the connecting bump is extended on the step difference layer, and have a sloped upper surface formed by a step difference formed by the step difference layer.2. The package of claim 1 , wherein the substrate is a semiconductor substrate of a semiconductor chip claim 1 , on which an integrated circuit is integrated claim 1 , a printed circuit board (PCB) on which the semiconductor chip is to be mounted claim 1 , or a package substrate including an interposer substrate.3. The package of claim 2 , wherein the semiconductor substrate comprises a through electrode providing the connecting contact part as an exposed surface.4. The package of claim 3 , further comprising a conductive layer configured to be connected to the exposed surface of the through electrode on the substrate so as to be used as a contact pad or redistribution layer (RDL).5. The package of claim 1 , wherein the step difference layer comprises an insulating layer having an opening through which the connecting contact ...

Semiconductor Device and Method of Forming Conductive Posts and Heat Sink Over Semiconductor Die Using Leadframe

A semiconductor device has a prefabricated multi-die leadframe with a base and integrated raised die paddle and a plurality of bodies extending from the base. A thermal interface layer is formed over a back surface of a semiconductor die or top surface of the raised die paddle. The semiconductor die is mounted over the raised die paddle between the bodies of the leadframe with the TIM disposed between the die and raised die paddle. An encapsulant is deposited over the leadframe and semiconductor die. Vias can be formed in the encapsulant. An interconnect structure is formed over the leadframe, semiconductor die, and encapsulant, including into the vias. The base is removed to separate the bodies from the raised die paddle. The raised die paddle provides heat dissipation for the semiconductor die. The bodies are electrically connected to the interconnect structure. The bodies operate as conductive posts for electrical interconnect. 1. A method of making a semiconductor device , comprising:providing a substrate including a raised die area and a plurality of conductive bodies extending from the substrate;disposing a semiconductor die over the raised die area between the conductive bodies of the substrate;depositing an encapsulant over the substrate and semiconductor die;forming an interconnect structure over the encapsulant, the interconnect structure being electrically connected to the conductive bodies; andremoving a portion of the substrate to separate the conductive bodies from the raised die area.2. The method of claim 1 , wherein the raised die area provides heat dissipation for the semiconductor die.3. The method of claim 1 , further including disposing a thermal interface material between the semiconductor die and raised die area.4. The method of claim 1 , further including forming a plurality of bumps over the semiconductor die.5. The method of claim 1 , further including:forming a plurality of vias in the encapsulant extending to the conductive bodies; ...

SEMICONDUCTOR PACKAGE FEATURING FLIP-CHIP DIE SANDWICHED BETWEEN METAL LAYERS

Embodiments in accordance with the present invention relate to flip-chip packages for semiconductor devices, which feature a die sandwiched between metal layers. One metal layer comprises portions of the lead frame configured to be in electrical and thermal communication with various pads on a first surface of the die (e.g. IC pads or MOSFET gate or source pads) through a solder ball contact. The other metal layer is configured to be in at least thermal communication with the opposite side of the die. Embodiments of packages in accordance with the present invention exhibit superior heat dissipation qualities, while avoiding the expense of wire bonding. Embodiments of the present invention are particularly suited for packaging of power devices. 1. A package for a semiconductor device , the package comprising:a first metal layer configured to be in thermal and electrical communication with a power device die; anda second metal layer disposed on an opposite side of the power device die from the first metal layer, the second metal layer configured to be in electrical and thermal communication with a pad on a surface of the power device die through physical contact with a solder ball contact, the first metal layer comprising integral leads projecting from a plastic package body encapsulating the power device die, the solder ball contact, and at least a part of the first and second metal layers;wherein the first metal layer is configured to be in electrical communication with the power device die through a second solder ball contact.2. A package for a semiconductor device , the package comprising:a first metal layer configured to be in thermal and electrical communication with a MOSFET die; a first portion configured to be in electrical communication with a gate pad on a surface of the MOSFET die, and', 'a second portion configured to be in electrical and thermal communication with a source pad on the surface of the MOSFET die through physical contact with a solder ball ...

Multi-piece substrate

A multi-piece substrate includes a frame portion, and a unit portion in which multiple wiring boards is arrayed. The frame portion is formed on the periphery of the unit portion, the wiring boards have semiconductor elements built in the wiring boards, respectively, and the frame portion has multiple slits formed such that the slits have openings on the periphery of the frame portion.

STRUCTURE FOR PICKING UP A BURIED LAYER AND METHOD THEREOF

A structure for picking up a buried layer is disclosed. The buried layer is formed in a substrate and has an epitaxial layer formed thereon. One or more isolation regions are formed in the epitaxial layer. The structure for picking up the buried layer includes a contact-hole electrode formed in each of the isolation regions. A bottom of the contact-hole electrode is in contact with the buried layer. As the structure of the present invention is formed in the isolation region without occupying any portion of the active region, its size is much smaller than that of a sinker region of the prior art. Therefore, device area is tremendously reduced. Moreover, as the contact-hole electrode picks up the buried layer by a metal contact, the series resistance of the device can be greatly reduced. A method of forming the above structure is also disclosed. 1. A structure for picking up a buried layer , the buried layer being formed in a substrate and having an epitaxial layer formed thereon , the epitaxial layer having one or more isolation regions formed therein , the structure comprising a contact-hole electrode formed in each of the isolation regions , a bottom of the contact-hole electrode being in contact with the buried layer.2. The structure according to claim 1 , wherein the contact-hole electrode is formed of tungsten.3. The structure according to claim 2 , wherein the contact-hole electrode further comprises a titanium and/or titanium nitride barrier layer formed on its bottom.4. The structure according to claim 1 , wherein the buried layer has a doping concentration of higher than 1×10atoms/cm.5. A method of forming the structure for picking up a buried layer according to claim 1 , comprising:forming a doped region in a substrate by performing an ion implantation process;growing a single crystal silicon epitaxial layer on the doped region via an epitaxial process such that the doped region becomes a buried layer;forming one or more isolation regions in the epitaxial ...

High strength through-substrate vias

A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter.

Package Structures and Methods for Forming the Same

A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface.

Semiconductor Device and Method of Forming EWLB Package Containing Stacked Semiconductor Die Electrically Connected through Conductive Vias Formed in Encapsulant Around Die

A semiconductor device has a first semiconductor die and first encapsulant deposited around the first semiconductor die. A first insulating layer is formed over the first semiconductor die and first encapsulant. A first conductive layer is formed over the first insulating layer and electrically connected to a contact pad of the first semiconductor die. A second semiconductor die is mounted to the first insulating layer and first conductive layer. A second encapsulant is deposited around the second semiconductor die. A second insulating layer is formed over the second semiconductor die and second encapsulant. A second conductive layer is formed over the second insulating layer and electrically connected to a contact pad of the second semiconductor die. A plurality of conductive vias is formed continuously through the first and second encapsulants outside a footprint of the first and second semiconductor die electrically connected to the first and second conductive layers. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;depositing a first encapsulant around the first semiconductor die;forming a first conductive layer over the first encapsulant;disposing a second semiconductor die over the first semiconductor die;depositing a second encapsulant around the second semiconductor die; andforming a second conductive layer over the second encapsulant.2. The method of claim 1 , further including forming a plurality of conductive vias through the first encapsulant and second encapsulant and electrically connected to the first conductive layer and second conductive layer.3. The method of claim 1 , further including:disposing a third semiconductor die over the second semiconductor die;depositing a third encapsulant around the third semiconductor die; andforming a third conductive layer over the third encapsulant.4. The method of claim 1 , further including forming an interconnect structure over the first semiconductor die or second ...

Semiconductor package and semiconductor package module having the same

Disclosed herein is a semiconductor package including: a semiconductor chip having a bonding pad; and a first substrate including a rerouting layer having short type rerouting patterns electrically connected with the bonding pad and formed to be seamlessly connected with each other and a plurality of open type rerouting patterns separately formed on the same layer as the short type rerouting patterns and connection terminals for signal connection each formed on the open type rerouting patterns.

STACKED-CHIP PACKAGES IN PACKAGE-ON-PACKAGE APPARATUS, METHODS OF ASSEMBLING SAME, AND SYSTEMS CONTAINING SAME

A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer. 125-. (canceled)26. An apparatus comprising:a package substrate including a die side and a land side;a chip stack disposed on the die side, wherein the chip stack includes a bottom chip disposed on the die side and a top chip disposed above the bottom chip, wherein the bottom chip is a flip-chip, wherein the top chip is a wire-bond chip, and wherein the chip stack has an offset height; andan interposer disposed on the die side, the interposer including an opening extending therethrough, the chip stack positioned on the package substrate within the opening, the interposer surrounding the chip stack, wherein the interposer accommodates the offset height of the chip stack.271. The apparatus of claim , wherein the interposer includes a bottom side ball-grid array and a top side ball grid array , the apparatus further including:a top package, wherein the top package includes at least one microelectronic device, wherein the top package is mated to the interposer top side ball-grid array; andwherein the interposer bottom side ball-grid array is mated to the die side of the package substrate.28. The apparatus of claim 26 , wherein the chip stack includes a wire-bond second chip disposed between the bottom chip and the top chip.29. The apparatus of claim 26 , wherein the chip stack includes a structure wherein:the bottom chip includes through-silicon vias extending therethrough;a through-silicon via (TSV) coupled second chip disposed on the flip chip, the TSV-coupled second chip being electrically coupled to the substrate using the through-silicon vias of the bottom chip; andthe top chip is disposed on the TSV-coupled second chip.30. The apparatus of claim 26 , wherein the chip stack includes a structure wherein:the bottom chip includes ...

Interposer and semiconductor package with noise suppression features

Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.

INTEGRATED CIRCUIT ASSEMBLY AND METHOD OF MAKING

An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate. 1. An integrated circuit assembly comprising:an insulating layer having a first surface and a second surface;a first active layer contacting the first surface of the insulating layer;a metal bond pad formed on the second surface of the insulating layer;wherein the metal bond pad is electrically connected to the first active layer;a substrate having a first surface and a second surface, the first active layer being coupled to the second surface of the substrate; anda second active layer formed on the first surface of the substrate.2. The integrated circuit assembly of further comprising:a printed circuit board, the printed circuit board being electrically connected to the metal bond pad.3. The assembly of claim 1 , wherein the substrate is less than 100 microns thick.4. The assembly of claim 1 , wherein the substrate is less than 50 microns thick.5. The assembly of claim 1 , wherein the substrate is less than 30 microns thick.6. The assembly of claim 1 , wherein the first active layer or the second active layer includes passive devices.7. The assembly of claim 2 , wherein the printed circuit board is electrically connected with a solder bump to the first active layer.8. The assembly of wherein the printed circuit board is electrically connected to the second active layer through a wire bond.9. The assembly of claim 2 , wherein the printed circuit board is electrically connected with a solder bump to the second active layer.10. The assembly of claim 2 , ...

SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE

A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate. 1. An apparatus , comprising:a first die;a second die including one or more through-silicon vias disposed therein (TSV die), the first die electrically coupled to the TSV die through the one or more through-silicon vias; anda coreless substrate, wherein both the first die and the TSV die are embedded in the coreless substrate, and wherein no surface of the first die protrudes from a surface of the coreless substrate.2. The apparatus of claim 1 , wherein the coreless substrate comprises an encapsulation layer claim 1 , and wherein both the first die and the TSV die are embedded in the encapsulation layer.3. The apparatus of claim 1 , wherein the first die is electrically coupled to the TSV die through the one or more through-silicon vias by one or more corresponding conductive bumps disposed on the first die and by one or more bond pads disposed on the TSV die.4. The apparatus of claim 1 , further comprising:a layer of epoxy flux material disposed between the first die and the TSV die.5. The apparatus of claim 1 , wherein the coreless substrate is free from routing layers between the first die and the TSV die.6. The apparatus of claim 1 , further comprising:a die-bonding film disposed on the first die.7. The apparatus of claim 1 , wherein the first die is fully embedded by the coreless substrate claim 1 , and wherein the TSV die is fully embedded and surrounded in the coreless substrate.8. An apparatus claim 1 , comprising:a memory die comprising a device side and a backside;a logic die including one or more through-silicon vias ...

MULTI-CHIP PACKAGE HAVING A STACKED PLURALITY OF DIFFERENT SIZED SEMICONDUCTOR CHIPS, AND METHOD OF MANUFACTURING THE SAME

Provided is a multi-chip package in which a plurality of semiconductor chips having different sizes are stacked. A multi-chip package may include a substrate, and a plurality of semiconductor chips stacked on the substrate, each of the plurality of semiconductor chips having a different size. Each of the plurality of semiconductor chips including a pad group and a reference region associated with the pad group, each pad group having a plurality of pads, and the plurality of pads in each pad group located at same coordinates with respect to the associated reference region, and each of the plurality of semiconductor chips having their reference regions vertically aligned. 1. A semiconductor device comprising:a first chip; andat least one chip stacked on the first chip, the at least one chip having a different size from the first chip,wherein each of the first chip and the at least one chip has a plurality of pads at center portion, and the first chip and the at least one chip are electrically connected to each other using the pads vertically aligned.2. The semiconductor device of claim 1 , wherein the plurality of pads are formed in a through via hole.3. The semiconductor device of claim 1 , wherein the at least one chip comprises a plurality of chips claim 1 , and the plurality of chips have a different size from each other.4. The semiconductor device of claim 1 , wherein at least a portion of the plurality of pads is arranged at a same distance from each other.5. The semiconductor device of claim 1 , wherein the plurality of pads are arranged in the same arrangement order in each of the first chip and the at least one chip.6. The semiconductor device of claim 1 , wherein the first chip and the at least one chip are electrically connected to each other by bumps disposed on the plurality of pads.7. The semiconductor device of claim 1 , further comprising:a substrate on which the first chip and the at least one chip are stacked.8. The semiconductor device of claim 7 , ...

Integrated circuit devices including electrode support structures and methods of fabricating the same

A semiconductor device includes a plurality of electrode structures perpendicularly extending on a substrate, and at least one support unit extending between the plurality of electrode structures. The support unit includes at least one support layer including a noncrystalline metal oxide contacting a part of the plurality of electrode structures. Related devices and fabrication methods are also discussed.

SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIPS

Disclosed herein is a device that including a first chip having first to fourth terminals and a second chip having fifth to seventh terminals. The first chip further includes a penetration electrode connected between the first and fourth electrodes and a first internal node coupled to of which an electrical potential being changed in response to an electrical potential of the first terminal. The second chip further includes a second internal node coupled to of which an electrical potential being changed in response to an electrical potential of the fifth terminal. The first internal node is electrically coupled to both the second terminal and the sixth terminal. The second internal node is electrically coupled to both the third terminal and the seventh terminal. 1. A semiconductor device comprising:a first chip including first and second surfaces opposed to each other, first, second and third terminals on the first surface, and a fourth terminal on the second surface, the first and fourth terminals being electrically coupled to each other through a penetration electrode penetrating a semiconductor substrate of the first chip, and a first internal node of which an electrical potential being changed in response to an electrical potential of the first terminal; anda second chip stacked with the first chip, the second chip including a third surface facing to the second surface of the first chip, a fourth surface opposed to the third surface, a fifth terminal on the third surface electrically coupled to the fourth terminal of the first chip, sixth and seventh terminals on the third surface, and a second internal node of which an electrical potential being changed in response to an electrical potential of the fifth terminal;the first internal node of the first chip being electrically coupled to both the second terminal of the first chip and the sixth terminal of the second chip, the second internal node of the second chip being electrically coupled to both the third ...

Semiconductor device, semiconductor package, and method for manufacturing semiconductor device

A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first surface, a second surface, and a through hole that extends through the semiconductor substrate from the first surface to the second surface. An insulating layer covers the first surface and includes an opening at a location facing the through hole. An insulating film covers an inner wall of the through hole and an inner wall of the opening. A through electrode is formed in the through hole and the opening that are covered by the insulating film. A first connecting terminal is formed integrally with the through electrode to cover one end of the through electrode exposed from the insulating layer. The first connecting terminal has a larger size than the through electrode as viewed from above.

SEMICONDUCTOR PACKAGE

The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least on opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors. Whereby, the solder mask contacts the first pads directly, and thus results in higher bonding strength, so as to avoid the bridge between the first conductors caused by the first conductors permeating into the interface between the solder mask and the first pads. 1. A semiconductor package , comprising:a substrate comprising a top surface, a pad, an anti-oxidation layer, and a solder mask, wherein the pad is disposed adjacent to the top surface of the substrate, the solder mask overlies and directly contacts a part of the pad and defines a solder mask opening so as to expose a remaining part of the pad, and the anti-oxidation layer is disposed over the remaining part of the pad exposed by the solder mask opening;a chip mounted on the substrate;a plurality of conductive elements electrically connecting the chip and the substrate;a conductor disposed over the anti-oxidation layer; anda molding compound disposed over the top surface of the substrate, wherein the molding compound comprises a first top surface and a second top surface, a first height of the first top surface of the molding compound is ...

WAFER-TO-WAFER STACK WITH SUPPORTING POST

A wafer stack includes: a first wafer having a first substrate and a first device layer having therein at least a chip; a second wafer having a second substrate disposed above the first wafer; and at least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip. 1. A wafer stack , comprising:a first wafer having a first substrate and a first device layer having therein at least a chip;a second wafer having a second substrate disposed above the first wafer; andat least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip.2. The wafer stack according to claim 1 , wherein the second wafer has a second device layer and the metal post has a part in the first device layer and being vertically aligned with that formed in the second device layer.3. The wafer stack according to claim 2 , wherein the first and the second device layers are adjacent to each other claim 2 , so as to configure the first and the second wafers as a face to face wafer stack.4. The wafer stack according to claim 1 , wherein the first device layer is adjacent to the second substrate claim 1 , so as to configure the first and the second wafers as a back to face wafer stack.5. The wafer stack according to claim 1 , wherein the first substrate is adjacent to the second substrate claim 1 , so as to configure the first and the second wafers as a back to back wafer stack.6. The wafer stack according to claim 1 , wherein a second substrate includes a rigid layer claim 1 , and the rigid layer is made up by one selected from the group consisting of silicon substrate claim 1 , silicon dioxide on silicon substrate and silicon nitride/silicon dioxide on silicon substrate.7. The wafer stack according to claim 6 , wherein the first metal post stands on a solid foundation layer of the first substrate.8. ...

Semiconductor device

A semiconductor device includes a structure in which a semiconductor element (chip) is mounted in a cavity formed in a wiring board with an adhesive interposed between the chip and a bottom surface of the cavity, and electrode terminals of the chip are connected via wires to wiring portions formed on the board around the cavity. The chip is mounted in close contact with a side wall of the cavity, the side wall being near a region where a wiring for higher frequency compared with other wirings within the wiring portion is formed. A recessed portion is provided in a region of the bottom surface of the cavity, and a thermal via extending from the bottom surface of the recessed to the outside of the board is provided, the region being near a portion where the chip is in close contact.

Packages with Passive Devices and Methods of Forming the Same

A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM.

Molded interposer package and method for fabricating the same

The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs.

Package carrier and manufacturing method thereof

A manufacturing method of a package carrier is provided. A supporting board having an upper surface which a patterned circuit layer formed thereon is provided. A portion of the upper surface is exposed by the patterned circuit layer. An insulating layer and a conducting layer located at a first surface of the insulating layer are laminated onto the patterned circuit layer. The patterned circuit layer and the exposed portion of the upper surface are covered by the insulating layer. Plural conductive connection structures are formed on the patterned circuit layer. Plural of pads respectively connecting the conductive connection structures and exposing a portion of the first surface of the insulating layer is defined by patterning the conductive layer. The supporting board is removed so as to expose a second surface of the insulating layer. The second surface and a bonding surface of the patterned circuit layer are coplanar.

Methods and Apparatus for Thinner Package on Package Structures

Methods and apparatus for thinner package on package (“PoP”) structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate and a plurality of package on package connectors extending from a bottom surface; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface; wherein at least the second substrate is formed of a plurality of layers of laminated dielectric and conductors. In another embodiment a cavity is formed on the bottom surface of the first substrate and a portion of the another integrated circuit extends partially into the cavity. Methods for making the PoP structures are disclosed.

SEMICONDUCTOR MODULE

According to one embodiment, a semiconductor module includes a semiconductor chip that is mounted on a printed substrate, a terminal electrode that is formed on the printed substrate so as to be electrically connected to the semiconductor chip, a metal coating layer that is formed on the terminal electrode, a plating lead wire that is electrically connected to the terminal electrode, and a gap that is formed in the plating lead wire. 1. A semiconductor module comprising:a semiconductor chip that is mounted on a printed substrate;a terminal electrode that is formed on the printed substrate so as to be electrically connected to the semiconductor chip;a metal coating layer that is formed on the terminal electrode;a lead wire that is electrically connected to the terminal electrode; anda gap that divides the lead wires in a wiring direction.2. The semiconductor module according to claim 1 , whereinthe lead wire is disposed so that end portions of the divided parts thereof face each other in the gap.3. The semiconductor module according to claim 1 , whereinthe metal coating layer is a plated layer, and the lead wire is a plating lead wire.4. The semiconductor module according to claim 1 , further comprisinga constant-voltage pattern that is formed on the printed substrate so as to face the end portion of the lead wire via the gap.5. The semiconductor module according to claim 4 , whereinthe constant-voltage pattern is a voltage source pattern or a ground pattern.6. The semiconductor module according to claim 4 , whereinthe constant-voltage pattern is disposed continuously around the printed substrate at an outer side of the lead wire.7. The semiconductor module according to claim 6 , whereinthe constant-voltage pattern is disposed so as to surround the lead wire.8. The semiconductor module according to claim 1 , further comprisinga solder ball that is formed on the terminal electrode.9. The semiconductor module according to claim 1 , further comprising:a solder resist ...

SEMICONDUCTOR DEVICE STRUCTURES AND ELECTRONIC DEVICES INCLUDING SAME HYBRID CONDUCTIVE VIAS, AND METHODS OF FABRICATION

A conductive via of a semiconductor device includes a relatively small diameter portion extending into an active surface of a fabrication substrate and a corresponding, relatively large diameter portion that extends into a back side of the fabrication substrate. This type of conductive via may be fabricated by forming the relatively small diameter portion before or during BEOL processing, while the large diameter portion of each conductive via may be fabricated after BEOL processing is complete. Electronic devices that include one or more semiconductor devices with such conductive vias are also disclosed. 1. A semiconductor device structure , comprising: an active surface carrying active components; and', 'a back side; and, 'a substrate comprising a semiconductor material and including first ends extending from the active surface into the semiconductor material; and', 'a second end in communication with each of the first ends, the second end extending from the back side into the semiconductor material and having a larger lateral dimension than the first ends., 'at least one via hole, including2. The semiconductor device structure of claim 1 , further comprising at least one of interconnection circuitry for at least one active component and at least one insulation layer for interconnection circuitry positioned above at least one of the first ends of the at least one via hole.3. The semiconductor device structure of claim 1 , wherein the first ends have a lateral dimension of at most about 6 μm.4. The semiconductor device structure of claim 3 , wherein the first ends extend at most about 30 μm into the semiconductor material of the substrate.5. The semiconductor device structure of claim 1 , wherein the second end has a lateral dimension of at most about 50 μm.6. The semiconductor device structure of claim 5 , wherein the second end extends at most about 90 μm from the back side into the semiconductor material of the substrate.7. The semiconductor device structure of ...

BALL GRID ARRAY PACKAGE SUBSTRATE WITH THROUGH HOLES AND METHOD OF FORMING SAME

In accordance with an embodiment, there is provided a substrate of a ball grid array package that includes a first layer including reinforcement fibers. The reinforcement fibers reinforce the first layer such that the first layer has a higher tensile strength relative to a layer in the ball grid array package that is free of reinforcement fibers. In an embodiment, the substrate comprises a second layer disposed adjacent to the first layer with the second layer being free of reinforcement fibers. In an embodiment, the substrate also includes a through hole penetrating each of the first layer and the second layer. The through hole penetrates each of the first layer and the second layer based on each of the first layer and the second layer having been drilled in accordance with a mechanical drilling process. 1. A substrate of a ball grid array package , the substrate comprising:a first layer including reinforcement fibers, wherein the reinforcement fibers reinforce the first layer such that the first layer has a higher tensile strength relative to a layer in the ball grid array package that is free of reinforcement fibers;a second layer disposed adjacent to the first layer, wherein the second layer is free of reinforcement fibers; anda through hole penetrating each of the first layer and the second layer, wherein the through hole penetrates each of the first layer and the second layer based on each of the first layer and the second layer having been drilled in accordance with a mechanical drilling process.2. The substrate of claim 1 , wherein:each of the first layer and the second layer respectively includes a circuit pattern; and; andthe through hole permits the circuit pattern of the first layer to be electrically coupled to the circuit pattern of the second layer.3. The substrate of claim 1 , wherein a diameter of the through hole is at least 80 microns.4. The substrate of claim 1 , wherein a diameter of the through hole is within a range of 100 microns to 150 ...

EPITAXY LEVEL PACKAGING

A method of growth and transfer of epitaxial structures from semiconductor crystalline substrate(s) to an assembly substrate. Using this method, the assembly substrate encloses one or more semiconductor materials and defines a wafer size that is equal to or larger than the semiconductor crystalline substrate for further wafer processing. The process also provides a unique platform for heterogeneous integration of diverse material systems and device technologies onto one single substrate. 1. A method of processing an epitaxial wafer comprising: wherein said plurality of compound semiconductor crystalline wafers and/or portions thereof are derived from wafers having at least one first nominal size including a first diameter;', 'mounting a separate assembly substrate over said assembly pattern, said separate assembly substrate having a second size, including a second diameter which exceeds said first diameter;', 'wherein said separate assembly substrate includes a plurality of through substrate vias extending from a top surface to a bottom surface which contacts said assembly pattern;', 'forming an epitaxial layer in said separate assembly substrate within said plurality of through substrate vias with an epitaxial process., 'arranging a plurality of compound semiconductor crystalline wafers and/or portions thereof into an assembly pattern;'}2. The method of wherein said separate assembly substrate is a solid rigid disc.3. The method of wherein said epitaxial process comprises liquid phase epitaxy (LPE) claim 1 , hydride vapor phase epitaxy (HVPE) claim 1 , metal organic chemical vapor deposition (MOCVD) claim 1 , molecular beam epitaxy (MBE) claim 1 , or other epitaxial growth methods.4. The method of wherein said plurality of compound semiconductor crystalline wafers include at least two separate wafers comprised of two different materials.5. The method of wherein a reactor used for said epitaxial process forms an epitaxial layer on N separate compound semiconductor ...

SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES AND METHODS FOR FABRICATING THE SAME

Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode. 1. A semiconductor device , comprising:a substrate including a via hole therethrough;a through electrode filling the via hole;a via-insulating layer disposed between the through electrode and the substrate; anda buffer layer disposed between the through electrode and the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer.2. The device of claim 1 , wherein the buffer layer includes: tetraethylorthosilicate (TEOS) oxide; low-k dielectric containing a SiO-based material claim 1 , in which C claim 1 , CH claim 1 , CH claim 1 , CHor any combination thereof is added as a ligand; a porous layer of the low-k dielectrics; or any combination thereof.3. The device of claim 2 , wherein the low-k dielectric comprises octamethylcyclotetrasiloxane (OMCTS) claim 2 , dimethyldimethoxysilane (DMDMOS) claim 2 , tetramethylcyclotetrasiloxane (TMCTS) claim 2 , diethoxymethylsilane (DEMS) claim 2 , AURORA™ (ethyl 2-chloro-3-[2-chloro-4-fluoro-5-[4-(difluoromethyl)-4 claim 2 ,5-dihydro-3-methyl-5-oxo-1H-1 claim 2 ,2 claim 2 ,4triazol-1-yl]phenyl]propanoat) claim 2 , or any combination thereof claim 2 , and{'sub': '2', 'the porous layer comprises an insulating layer including the low-k ...

SEMICONDUCTOR DEVICE WITH DIE STACK ARRANGEMENT INCLUDING STAGGERED DIE AND EFFICIENT WIRE BONDING

A semiconductor die package is disclosed. An example of the semiconductor package includes a first group of semiconductor die interspersed with a second group of semiconductor die. The die from the first and second groups are offset from each other along a first axis and staggered with respect to each other along a second axis orthogonal to the first axis. A second example of the semiconductor package includes an irregular shaped edge and a wire bond to the substrate from a semiconductor die above the lowermost semiconductor die in the package. 1. A semiconductor device , comprising:a substrate;a first semiconductor die mounted on the substrate, an x-axis and a y-axis being defined parallel with orthogonal edges of the first semiconductor die;a second semiconductor die mounted on top of the first semiconductor die, the second semiconductor die being offset along the x-axis with respect to the first semiconductor die, and the second semiconductor die being staggered along the y-axis with respect to the first semiconductor die; anda third semiconductor die mounted on top of the second semiconductor die, the third semiconductor die being offset along the x-axis with respect to the second semiconductor die, and the third semiconductor die being staggered along the y-axis to align with the first semiconductor die along the y-axis.2. The semiconductor device of claim 1 , further comprising a fourth semiconductor die mounted on top of the third semiconductor die claim 1 , the fourth semiconductor die being offset along the x-axis with respect to the third semiconductor die claim 1 , and the fourth semiconductor die being staggered along the y-axis to align with the second semiconductor die along the y-axis.3. The semiconductor device of claim 2 , further comprising:die bond pads on each of the first, second, third and fourth semiconductor die;a first set of bond wires connecting corresponding die bond pads on the first and third semiconductor die with the substrate; anda ...

Semiconductor Device Package with Slanting Structures

A semiconductor device package structure includes a substrate with a via contact pad on top surface of the substrate, a terminal pad on bottom surface of the substrate and a conductive through hole through the substrate, wherein the conductive through hole electrically couples the via contact pad and the terminal pad on the substrate; a die having bonding pads thereon, wherein the die is formed on the top surface of the substrate; a slanting structure formed adjacent to at least one side of the die for carrying conductive traces; and a conductive trace formed on upper surface of the slanting structure to offer path between the bonding pads and the via contact pad. 1. A semiconductor device package structure , comprising:a substrate with a via contact pad on a top surface of said substrate, a terminal pad on a bottom surface of said substrate and a conductive through hole through said substrate, wherein said conductive through hole is electrically coupled to said via contact pad and said terminal pad on said substrate;a die having bonding pads thereon, wherein said die is formed on said top surface of said substrate;a slanting structure formed adjacent to at least one side of said die for carrying conductive traces; anda conductive trace formed on a upper surface of said slanting structure to offer electrical path between said bonding pads and said via contact pad.2. The structure of claim 1 , further comprising a refilling material within said conductive through hole.3. The structure of claim 2 , wherein said refilling material comprises aluminum claim 2 , titanium claim 2 , copper claim 2 , nickel claim 2 , silver or the combination thereof.4. The structure of claim 2 , wherein said refilling material comprises Cu/Ni/Au.5. The structure of claim 1 , further comprising an adhesive layer formed between backside surface of said die and said top surface of said substrate.6. The structure of claim 5 , further comprising:a cavity formed from said bottom surface of said ...

SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT

Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via. 1. A semiconductor device comprising:a silicon substrate having a first side and a second side;active circuitry fabricated on the first side of the silicon substrate and including multiple metal routing structures;a conductive interconnect extending vertically through the silicon substrate to the second side such that at least one of the multiple routing structures is located in a horizontal plane located above a top region of the conductive interconnect; andan external electrical interconnect coupled to the conductive interconnect at the second side of the silicon substrate.2. The semiconductor device of wherein the external electrical interconnect comprises a conductive redistribution structure located at the second side of the silicon substrate claim 1 , wherein the conductive redistribution structure is electrically coupled to the conductive interconnect.3. The semiconductor device of wherein the conductive redistribution structure comprises a conductive ball bond pad.4. The semiconductor device of wherein the conductive interconnect has a length to width ratio of about 5:1 to 10:1.5. The semiconductor device of wherein one of the multiple metal routing structures has an electrical connection with the conductive interconnect.6. A semiconductor device comprising:a silicon substrate having a first side and a second side;a conductive interconnect extending from a ...

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

A semiconductor package including a semiconductor chip configured to include a connection terminal electrically connected to wirings for transferring signals. The semiconductor package may include a semiconductor supporting substrate configured to be bonded to the semiconductor chip and include a through-silicon via which allows the connection terminal to be opened. The connection terminal may be formed on a scribe line of a semiconductor wafer and a conductive material contacting the connection terminal may filled in the through-silicon via. 1. An apparatus comprising:a semiconductor chip comprising a connection terminal electrically connected to wirings that are configured to transfer signals; anda semiconductor supporting substrate bonded to the semiconductor chip;a through-silicon via in the semiconductor supporting substrate configured to open the connection terminal, wherein the connection terminal is formed on a scribe line of a semiconductor wafer and a conductive material is filled in the through-silicon via to contact the connection terminal.2. The apparatus of claim 1 , wherein the apparatus is a semiconductor package.3. The apparatus of claim 1 , wherein the conductive material is diced along the scribe line.4. The apparatus of claim 1 , wherein the semiconductor package is bonded to a printed circuit board (PCB) and is electrically connected to the PCB through the conductive material.5. The apparatus of claim 1 , wherein the conductive material comprises a solder ball.6. The apparatus of claim 1 , wherein the conductive material includes a metal material filled by an electroplating mechanism.7. The apparatus of claim 6 , wherein the metal material comprises copper (Cu).8. The apparatus of claim 1 , wherein the semiconductor chip comprises an image sensor chip.9. A method of fabricating a semiconductor package claim 1 , comprising:opening a connection terminal comprised in a semiconductor chip by forming a through-silicon via through a semiconductor ...

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS

A semiconductor device is provided in the present invention. The semiconductor device includes a silicon substrate, configured to bear a chip; a power management module arranged inside the silicon substrate, configured to convert a power supply voltage to an input voltage required by the chip; and an interconnecting system, configured to receive the power supply voltage, transmit the power supply voltage to the power management module, and transmit the input voltage to the chip. With the semiconductor device according to the embodiments of the present invention, the power supply voltage can be directly sent from the silicon substrate to the chip after being generated, thereby shortening the power supply link and reducing the power supply/ground noise. 1. A semiconductor device , comprising:a silicon substrate, configured to bear a chip;a power management module arranged inside the silicon substrate, configured to convert a power supply voltage to an input voltage required by the chip; andan interconnecting system, configured to receive the power supply voltage, transmit the power supply voltage to the power management module, and transmit the input voltage to the chip.2. The semiconductor device according to claim 1 , wherein the interconnecting system comprises a through silicon via claim 1 , the through silicon via is arranged in the silicon substrate claim 1 , and an electric path is arranged in the through silicon via to transmit the power supply voltage and the input voltage.3. The semiconductor device according to claim 2 , wherein the interconnecting system further comprises a solder pad arranged on the upper surface of the silicon substrate claim 2 , the solder pad is configured to electrically connect to the chip claim 2 , and the solder pad is electrically connected to the electric path in the through silicon via.4. The semiconductor device according to claim 2 , wherein the interconnecting system further comprises a solder pad arranged on the lower ...

SEMICONDUCTOR APPARATUS MANUFACTURING METHOD AND SEMICONDUCTOR APPARATUS

There is provided a method of manufacturing the semiconductor apparatus, including: forming through-hole which penetrates a semiconductor substrate at a point that corresponds to a location of an electrode pad; forming an insulating film on a rear surface of the semiconductor substrate, including the interior of the through-hole; forming an adhesion securing layer from a metal or an inorganic insulator on a surface of the insulating film at least in an opening portion of the through-hole; forming a resist layer to serve as a mask in bottom etching on the adhesion securing layer; performing bottom etching to expose the electrode pad; removing the resist layer to obtain the insulating film free of surface irregularities that would otherwise have been created by bottom etching; forming a barrier layer, a seed layer, and a conductive layer by a low-temperature process; and performing patterning. 1. A semiconductor apparatus , comprising:a semiconductor substrate;an electrode pad formed on a front surface of said semiconductor substrate;a through-hole which has an opening portion on a rear surface of said semiconductor substrate that corresponds to a location of said electrode pad and which penetrates said semiconductor substrate;an insulating film formed on an inner wall of said through-hole;a layer formed on said insulating film; anda conductive layer formed on said layer, or on said layer and said insulating film, and on said electrode pad,wherein said electrode pad is in contact with said conductive layer.2. The semiconductor apparatus according to claim 1 , wherein said layer formed on said insulating film is made from one of a metal and an inorganic insulator.3. The semiconductor apparatus according to claim 1 , wherein said layer formed on the insulating film is 0.01 μm to 0.1 μm in thickness.4. The semiconductor apparatus according to claim 1 , wherein said layer formed on said insulating film comprises titanium claim 1 , tungsten or chromium.5. The semiconductor ...

SEMICONDUCTOR DEVICE HAVING SIGNAL LINE AND POWER SUPPLY LINE INTERSECTING WITH EACH OTHER

Disclosed herein is a semiconductor device includes: a plurality of first power supply wirings provided on a first wiring layer and extending in a first direction; a plurality of second power supply wirings provided on a second wiring layer different from the first wiring layer and extending in a second direction intersecting the first direction; a signal wiring provided on the second wiring layer and extending in the second direction; and a plurality of through-hole conductors each electrically connecting an associated one of the first power supply wirings to an associated one of the second power supply wirings. At least a part of the first power supply wirings have a notch in a portion intersecting the signal wiring. 1. A semiconductor device comprising:a plurality of first power supply wirings provided on a first wiring layer and extending in a first direction;a plurality of second power supply wirings provided on a second wiring layer different from the first wiring layer and extending in a second direction intersecting the first direction;a signal wiring provided on the second wiring layer and extending in the second direction; anda plurality of through-hole conductors each electrically connecting an associated one of the first power supply wirings to an associated one of the second power supply wirings,wherein at least a part of the first power supply wirings have a notch in a portion intersecting the signal wiring.2. The semiconductor device as claimed in claim 1 , whereineach of the first power supply wirings whose wiring width in the second direction is smaller than a first width among the first power supply wirings does not have the notch in the portion intersecting the signal wiring, andeach of the first power supply wirings whose wiring width in the second direction is equal to or larger than the first width among the first power supply wirings has the notch in the portion intersecting the signal wiring.3. The semiconductor device as claimed in claim 2 , ...

SEMICONDUCTOR DEVICE

When a material of an organic substrate is glass epoxy and a material of a semiconductor chip is silicon or gallium arsenide, a substrate warp sometimes occurs because of a difference between thermal expansion coefficients of the materials. The shape of the antenna formed on the organic substrate due to such a substrate warp, so that the characteristics of the antenna are sometimes shifted from desired values. An antenna is provided on the substrate on which a semiconductor chip is mounted, and is covered with a resin. The resin has enough hardness to suppress the warp caused by joining the semiconductor chip and the substrate and a transformation of the antenna. By changing a connection relation of adjustment vias after the manufacture of the semiconductor device, the characteristic of the antenna can be changed. 1. A semiconductor device comprising:a semiconductor chip;a substrate used to mount said semiconductor chip;an antenna formed on said substrate and configured to radiate a signal outputted from said semiconductor chip; andresin configured to cover said antenna,wherein said substrate comprises a mounting section used to be mounted on another substrate2. The semiconductor device according to claim 1 , wherein said mounting section comprises solder lands connected to said another substrate.3. The semiconductor device according to claim 1 , wherein said resin seals said semiconductor chip claim 1 , said substrate and at least a part of said antenna to suppress a warp through conjunction of said semiconductor chip and said substrate and a transformation of said substrate.4. The semiconductor device according to claim 3 , wherein said resin comprises metallic oxide equal to or more than 85% weight %.5. The semiconductor device according to claim 1 , wherein said substrate further comprises vias formed in a thickness direction of said substrate and connected with a circuit formed on said substrate claim 1 , andwherein said vias comprises via lands formed on a ...

STRUCTURES AND METHODS TO REDUCE MAXIMUM CURRENT DENSITY IN A SOLDER BALL

Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance. 1. A semiconductor structure , comprising:a contact pad in a last wiring level of a chip; anda plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias,wherein each one of the plurality of wires has substantially the same electrical resistance.2. The semiconductor structure of claim 1 , wherein the plurality of wires are formed from the contact pad.3. The semiconductor structure of claim 1 , wherein:a first one of the plurality of wires has a first length and a first width,a second one of the plurality of wires has a second length and a second width,the first width is different from the second width, andthe first length is different from the second length.4. The semiconductor structure of claim 3 , further comprising:a capping layer on the last wiring level of the chip;a passivation layer on the capping layer;at least one final via in the passivation layer;a ball limiting metallurgy (BLM) layer on the at least one final via and the passivation layer; anda solder bump on the BLM layer.5. The semiconductor structure of claim 4 , wherein:the plurality of vias are disposed in the capping layer;the plurality of vias and the capping layer have substantially coplanar upper surfaces; andthe at least one final vias and the passivation layer have substantially coplanar upper surfaces.6. The semiconductor structure of claim 1 , wherein at least two of the plurality of wires comprise different widths and different lengths.7. The semiconductor structure of claim 1 , wherein at least one of the plurality of wires widens at a location adjacent ...

Interposer substrate manufacturing method and interposer substrate

A method for manufacturing an interposer substrate includes: forming a conductive portion on a first surface of a semiconductor substrate via a first insulating layer, the conductive portion being formed of a first metal; forming a through hole at a second surface side of the semiconductor substrate located on an opposite side to the first surface so as to expose the first insulating layer; forming a second insulating layer on at least an inner wall surface and a bottom surface of the through hole; exposing the conductive portion by removing portions of the first and second insulating layers using a dry etching method that uses an etching gas containing a fluorine gas, the portions of the first and second insulating layers being located on the bottom surface of the through hole; and forming a conductive layer on the second insulating layer and electrically connecting the conductive layer to the conductive portion, wherein when exposing the conductive portion, forming a tapered portion is performed.

PACKAGED MICROELECTRONIC DEVICES RECESSED IN SUPPORT MEMBER CAVITIES, AND ASSOCIATED METHODS

Packaged microelectronic devices recessed in support member cavities, and associated methods, are disclosed. Method in accordance with one embodiment includes positioning a microelectronic device in a cavity of a support member, with the cavity having a closed end with a conductive layer, and an opening through which the cavity is assessable. The microelectronic device can have bond sites, a first surface, and a second surface facing opposite from the first surface. The microelectronic device can be positioned in the cavity so that the second surface faces toward and is carried by the conductive layer. The method can further include electrically coupling the bond sites of the microelectronic device to the conductive layer. In particular embodiments, the microelectronic device can be encapsulated in the cavity without the need for a releasable tape layer to temporarily support the microelectronic device. 1. A microelectronic package , comprising:a first support member comprising a first conductive material, a second conductive material, and a first insulating material between the first conductive material and the second conductive material;an intermediate member having a first side facing the second conductive material of the first support member and a second side facing away from the first side;a second support member comprising a third conductive material, a fourth conductive material, and a second insulating material between the third conductive material and the fourth conductive material, the third conductive material having a first side facing the intermediate member and the second side facing away from the first side, the forth conductive material having a first side facing the second insulating material and a second side facing away from the second insulating material;wherein the package has a cavity extending generally vertically from the first side of the fourth conductive material through the first conductive material of the first support member.2. The ...

Semiconductor Device and Method of Forming a Robust Fan-Out Package including Vertical Interconnects and Mechanical Support Layer

A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad Along First Axis and Narrower than Contact Pad along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first conductive layer over the substrate;forming a first insulating layer over the substrate; andforming a second conductive layer over the first conductive layer, the second conductive layer including a width that is less than a width of the first conductive layer along a first axis and a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis.2. The method of claim 1 , further including forming a second insulating layer over the second conductive layer and first insulating layer.3. The method of claim 1 , further including forming a second insulating layer over the substrate prior to forming the first insulating layer.4. The method of claim 1 , wherein the width of the second conductive layer is greater than the width of the first conductive layer along the second axis by 10-20 micrometers.5. The method of claim 1 , wherein the width of the first conductive layer is greater than the width of the second conductive layer along the first axis by 10-20 micrometers.6. The method ...