CHIP PACKAGE STRUCTURE

A chip package structure including a molding compound, a carrier board, a chip, a plurality of conductive pillars and a circuit board is provided. The carrier board includes a substrate and a redistribution layer. The substrate has a first surface and a second surface. The redistribution layer is disposed on the first surface. The chip and the conductive pillars are disposed on the redistribution layer. The molding compound covers the chip, the conductive pillars, and the redistribution layer. The circuit board is connected with the carrier board, wherein the circuit board is disposed on the molding compound, such that the chip is located between the substrate and the circuit board, and the chip and the redistribution layer are electrically connected with the circuit board through the conductive pillars. Heat generated by the chip is transmitted through the substrate from the first surface to the second surface to dissipate. 1. A chip package structure , comprising:at least one carrier board comprising a substrate and a redistribution layer, wherein the substrate has a first surface and a second surface opposite to each other, and the redistribution layer is disposed on the first surface of the substrate;at least one chip disposed on the redistribution layer;at least one conductive pillar disposed on the redistribution layer, wherein the at least one conductive pillar is located at a periphery of the at least one chip;at least one molding compound disposed on the redistribution layer and covering the at least one chip, the at least one conductive pillar, and the redistribution layer, wherein the at least one conductive pillar passes through the at least one molding compound; anda circuit board disposed on the at least one molding compound, wherein the circuit board is connected with the at least one carrier board through the at least one conductive pillar, such that the at least one chip is located between the substrate and the circuit board, and the at least one ...

Semiconductor device

A semiconductor device including a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer. The silicon substrate has a first surface, a second surface opposite to the first surface and a plurality of through holes. The silicon nanowire clusters are disposed in the through holes of the silicon substrate, respectively. The first circuit layer is disposed on the first surface and connected to the silicon nanowire clusters. The second circuit layer is disposed on the second surface and connected to the silicon nanowire clusters.

Interconnection structure and manufacturing method thereof

An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a substrate, a conductive through via, a dielectric layer, and a conductive layer. The substrate has a first surface and a second surface opposite to each other. The conductive through via is disposed in the substrate and extended from the first surface beyond the second surface. The dielectric layer is disposed on the substrate, wherein the dielectric layer has an opening exposing a portion of the conductive through via. The top surface of the conductive through via protrudes from the bottom surface of the opening. The conductive layer is disposed in the opening and connected to the conductive through via.

INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF

An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a substrate, a conductive through via, a dielectric layer, and a conductive layer. The substrate has a first surface and a second surface opposite to each other. The conductive through via is disposed in the substrate and extended from the first surface beyond the second surface. The dielectric layer is disposed on the substrate, wherein the dielectric layer has an opening exposing a portion of the conductive through via. The top surface of the conductive through via protrudes from the bottom surface of the opening. The conductive layer is disposed in the opening and connected to the conductive through via. 1. A manufacturing method of an interconnection structure , comprising:providing a substrate;forming a conductive through via in the substrate, wherein the substrate has a first surface and a second surface opposite to each other, and the conductive through via is extended from the first surface to the second surface;removing a portion of the substrate from the first surface to expose a portion of the conductive through via;forming a dielectric layer on the substrate, wherein the dielectric layer covers the exposed conductive through via;forming an opening in the dielectric layer, wherein the opening exposes a portion of the conductive through via, and a top surface of the conductive through via protrudes from a bottom surface of the opening; andforming a conductive layer n the opening.2. The method of claim 1 , wherein after a portion of the substrate is removed from the first surface claim 1 , the top surface of the conductive through via is higher than the first surface by 1 μm to 50 μm.3. The method of claim 1 , wherein a method of removing a portion of the substrate from the first surface comprises performing a wet etching process.4. The method of claim 1 , wherein a method of forming the opening comprises performing a laser drilling process ...

CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

A circuit board includes a composite layer of a non-conductor inorganic material and an organic material, a plurality of conductive structures, a first built-up structure, and a second built-up structure. The composite layer of the non-conductor inorganic material and the organic material has a first surface and a second surface opposite to each other and a plurality of openings. The conductive structures are respectively disposed in the openings of the composite layer of the non-conductor inorganic material and the organic material. The first built-up structure is disposed on the first surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures. The second built-up structure is disposed on the second surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures. 1. A circuit board , comprising:a composite layer of a non-conductor inorganic material and an organic material, having a first surface and a second surface opposite to each other and a plurality of openings;a plurality of conductive structures, respectively disposed in the openings of the composite layer of the non-conductor inorganic material and the organic material;a first built-up structure, disposed on the first surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures; anda second built-up structure, disposed on the second surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures.2. The circuit board as recited in claim 1 , wherein a material of the composite layer of the non-conductor inorganic material and the organic material comprises a composite material composed of a ceramic material and a polymer material.3. The circuit board as ...

Measuring apparatus

A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat.

HEAT DISSIPATION STRUCTURE FOR ELECTRONIC DEVICE AND FABRICATION METHOD THEREOF

A heat dissipation structure for an electronic device includes a body having a first surface and a second surface opposite to the first surface. A silicon-containing insulating layer is disposed on the first surface of the body. A chemical vapor deposition (CVD) diamond film is disposed on the silicon-containing insulating layer. A first conductive pattern layer is disposed on the silicon-containing insulating layer, wherein the first conductive pattern layer is enclosed by and spaced apart from the CVD diamond film. A method for fabricating a heat dissipation structure for an electronic device and an electronic package having the heat dissipation structure are also disclosed. 1. A heat dissipation structure for an electronic device , comprising:a body having a first surface and a second surface opposite to the first surface;a silicon-containing insulating layer disposed on the first surface of the body;a chemical vapor deposition diamond film disposed on the silicon-containing insulating layer; anda first conductive pattern layer disposed on the silicon-containing insulating layer, wherein the first conductive pattern layer is enclosed by and spaced apart from the chemical vapor deposition diamond film.2. The structure of claim 1 , wherein the body is a circuit board or package substrate.3. The structure of claim 1 , wherein the body is a semiconductor chip comprising at least one semiconductor device and at least one interconnect structure electrically connected to the semiconductor device therein.4. The structure of claim 3 , wherein the first conductive pattern layer is electrically connected to the interconnect structure.5. The structure of claim 1 , further comprising a second conductive pattern layer disposed on the second surface of the body.6. The structure of claim 5 , wherein the body comprises at least one through via therein claim 5 , which is electrically connected between the first and second conductive pattern layers.7. The structure of claim 6 , ...

Fabricating method and testing method of semiconductor device and mechanical integrity testing apparatus

A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.

SEMICONDUCTOR DEVICE

A semiconductor device including a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer. The silicon substrate has a first surface, a second surface opposite to the first surface and a plurality of through holes. The silicon nanowire clusters are disposed in the through holes of the silicon substrate, respectively. The first circuit layer is disposed on the first surface and connected to the silicon nanowire clusters. The second circuit layer is disposed on the second surface and connected to the silicon nanowire clusters. 1. A semiconductor device comprising:a first silicon substrate comprising a first surface, a second surface opposite to the first surface, and a plurality of through holes;a plurality silicon nanowire clusters disposed in the through holes, respectively;a first circuit layer disposed on the first surface and electrically connected to the silicon nanowire clusters; anda second circuit layer disposed on the second surface and electrically connected to the silicon nanowire clusters.2. The semiconductor device according to claim 1 , further comprising an insulation filling material filled in the through holes.3. The semiconductor device according to claim 1 , wherein the silicon nanowire clusters are of P-type or N-type.4. The semiconductor device according to claim 1 , further comprising at least one through silicon via defined through the first silicon substrate and electrically connecting the first circuit layer with the second circuit layer.5. The semiconductor device according to claim 4 , wherein the through silicon via is electrically connected to the silicon nanowire clusters.6. The semiconductor device according to claim 1 , further comprising at least one integrated circuit unit and an insulation layer disposed on the first surface claim 1 , wherein the insulation layer covers the integrated circuit unit claim 1 , and the first circuit layer is disposed on the insulation layer and ...

WAFER-TO-WAFER STACK WITH SUPPORTING PEDESTAL

A novel three dimensional wafer stack and the manufacturing method therefor are provided. The three dimensional wafer stack includes a first wafer having a first substrate and a first device layer having thereon at least one chip, a second wafer disposed above the first wafer and having a second substrate, and at least one pedestal arranged between and extending from the first substrate to the second substrate. The pedestal arranged in the device layer is used for preventing the low-k materials existing in the device layer from being damaged by the stresses. 1. A method for stacking a three dimensional wafer structure , comprising the steps of:providing a first wafer;disposing a second wafer above the first wafer;forming a supporting structure on the first wafer;forming plural interconnecting vias running through the second wafer for electrically interconnecting opposite sides of the second wafer; andbonding the first and the second wafers for completing the three dimensional wafer structure.2. A method according to claim 2 , wherein the plural interconnecting vias are formed by one of processes selected from a group consisting of UV laser process claim 2 , CO2 laser process claim 2 , and chemical etching process.3. A method according to claim 1 , further comprising a step of filling up a part of the interconnecting vias with an electrically conductive material for electrically interconnecting both sides of the second wafer.4. A method according to claim 3 , further comprising a step of forming an insulator layer around side walls of the part of the interconnecting vias.5. A method according to claim 3 , further comprising a step of forming an electrically conductive layer on the second wafer. The present application is a divisional application of co-pending U.S. application Ser. No. 11/471,165 filed on Jun. 20, 2006, and for which priority is claimed under 35 U.S.C. §120. This application also claims priority of Application No. 94137522 filed at Taiwan on Oct. 26, ...

HYDROGEN/OXYGEN GAS GENERATING APPARATUS AND INTERNAL COMBUSTION ENGINE SYSTEM HAVING THE SAME

An internal combustion engine system including an electric power generating device, a container, a set of positive and negative electrodes and an internal combustion engine is provided. The container contains an electrolytic solution and has a gas outlet. The set of positive and negative electrodes are disposed within the electrolytic solution in the container, wherein the set of positive and negative electrodes are electrically connected to a first power output end and a second power output end of the electric power generating device, respectively. The internal combustion engine is connected to the gas outlet, wherein a gas product directed from the gas outlet is used as a fuel of the internal combustion engine. Further, the electric power generating device can be applied on a hydrogen/oxygen gas generating apparatus and integrated into the internal combustion engine system of a motor vehicle. 1. A hydrogen/oxygen gas generating apparatus , comprising:an electric power generating device;a container, containing an electrolytic solution and having a gas outlet; anda set of positive and negative electrodes, disposed within the electrolytic solution in the container, wherein the set of positive and negative electrodes are electrically connected to a first power output end and a second power output end of the electric power generating device, respectively.2. The hydrogen/oxygen gas generating apparatus as claimed in claim 1 , wherein the electric power generating device comprises:a pipe body; anda thermoelectric conversion module disposed on the pipe body and having the first power output end and the second power output end.3. The hydrogen/oxygen gas generating apparatus as claimed in claim 2 , wherein the electric power generating device further comprises a cold source disposed on the thermoelectric conversion module.4. The hydrogen/oxygen gas generating apparatus as claimed in claim 2 , wherein the thermoelectric conversion module comprises a plurality of ...

Test structure and measurement method thereof

A test structure including a substrate, at least one conductive plug, a first conductive trace and a second conductive trace is provided. The substrate has a first area and a second area. The at lest one conductive plug is disposed in the substrate in the first area, wherein the conductive plug does not penetrate through the substrate. The first conductive trace is disposed on the conductive plug and on the substrate in the first area. The second conductive trace is disposed on the substrate in the second area. It is noted that the first conductive trace and the second conductive trace have the same material and the same shape. A measurement method of the above-mentioned test structure is also provided.

Filled through-silicon via and the fabrication method thereof

By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.

Wafer-to-wafer stack with supporting post

A wafer stack includes: a first wafer having a first substrate and a first device layer having therein at least a chip; a second wafer having a second substrate disposed above the first wafer; and at least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip.

Fabricating method of semiconductor device

A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.

FILLED THROUGH-SILICON VIA AND THE FABRICATION METHOD THEREOF

By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased. 1. A through via , comprising:at least one through-via hole disposed between a first surface and a second surface opposite to the first surface of an isolative substrate and penetrating the isolative substrate; anda conductive material filled within the at least one through-via hole and filled up the at least one through-via hole, the conductive material being a composite material at least comprising a metal material and particles of a supplementary material having a coefficient of thermal expansion lower than a coefficient of thermal expansion of the metal material and having a thermal conductivity higher than a thermal conductivity of the metal material, wherein the metal material is selected from copper, tungsten or aluminum, and the supplementary material is selected from silicon carbide, chemical-vapor deposition silicon carbide, diamond, chemical-vapor deposition diamond, beryllium oxide, aluminum nitride, aluminum oxide, molybdenum or carbon nanotubes.2. The through via as claimed in claim 1 , wherein a diameter of the particles of the supplementary material substantially ranges from tens of nanometers to tens of micrometers.3. The through via as claimed in claim 1 , wherein an addition ratio of the particles of the supplementary material is less than or equal to 50%.4. The through via as claimed in claim 1 , wherein an addition ratio of the particles of the supplementary material substantially ranges from 5% to 50%.5. The through via as claimed in claim 1 , further comprising a first wiring pattern located on the first surface and covering the conductive material filled in the at least one ...

LED LIGHT BULB MODULE

A light emitting diode (LED) light bulb module includes an LED light bulb unit having a first connector; an LED supporting device unit having a second connector which is configured to electrically coupled to the first connector, and a third connector which is configured to electrically coupled to a power supply source; and a thermal insulating structure configured to thermally decouple the LED light bulb unit and the LED supporting device unit. The LED light bulb unit and the LED supporting device unit can be either physically joined or detached from each other, and ideally, two separated heat sink apparatuses, each dedicated to the LED light bulb unit and the LED supporting device unit, respectively may be used. 1. A light emitting diode (LED) supporting device unit , comprising:a body portion comprising at least one LED supporting device;a heat dissipation structure thermally coupled to the body portion;a first connector, allowing the at least one LED supporting device to be electrically coupled to an external LED light bulb unit; anda second connector, allowing the at least one LED supporting device to be electrically coupled to an external power supply.2. The LED supporting device unit of claim 1 , further comprising at least one thermal insulating portion configured to thermally decouple the LED supporting device unit from the external LED light bulb unit coupled to said first connector.3. The LED supporting device unit of claim 2 , the thermal insulating portion is an air space structure fabricated on the LED supporting device unit.4. The LED supporting device unit of claim 1 , wherein the LED supporting device comprises at least one active circuit block and at least one passive circuit block.5. The LED supporting device unit of claim 4 , wherein the active circuit block comprises at least one component of an AC/DC rectifier claim 4 , a DC/DC converter claim 4 , a pulse width modulator claim 4 , a constant current generator claim 4 , or the combinations ...

CIRCUIT BOARD STRUCTURE

A circuit board structure includes a carrier and a patterned circuit layer. The patterned circuit layer is disposed on the carrier, and the patterned circuit layer has at least one fluid channel therein. The fluid channel has a heat absorption section and a heat dissipation section relative to the heat absorption section. A heat source is electrically connected to the patterned circuit layer, and the heat absorption section is adjacent to the heat source. The heat generated by the heat source is transferred from the patterned circuit layer to the heat absorption section of the fluid channel, and is transferred from the heat absorption section to the heat dissipation section for heat dissipation. 1. A circuit board structure suitable for carrying at least one heat source , comprising:a carrier; anda patterned circuit layer, disposed on the carrier, wherein the patterned circuit layer is provided with at least one fluid channel therein, the at least one fluid channel is provided with a heat absorption section and a heat dissipation section relative to the heat absorption section, the at least one heat source is electrically connected to the patterned circuit layer, the heat absorption section is adjacent to the at least one heat source, and the heat generated by the at least one heat source is transferred from the patterned circuit layer to the heat absorption section of the at least one fluid channel, and is transferred from the heat absorption section to the heat dissipation section for heat dissipation,wherein an orthographic projection of the at least one heat source on the carrier is overlapped with an orthographic projection of the heat absorption section of the at least one fluid channel on the carrier.2. The circuit board structure according to claim 1 , wherein the carrier is an insulating substrate claim 1 , and the patterned circuit layer is directly disposed on the carrier.3. The circuit board structure according to claim 2 , wherein a material of the ...

CHIP PACKAGE STRUCTURE

A chip package structure includes a substrate, a first chip, a second chip, a bridge, a plurality of first bumps, a plurality of second bumps, a plurality of third bumps and a plurality of solder balls. A first active surface of the first chip and a second active surface of the second chip face a first surface of the substrate. The bridge includes a high-molecular polymer layer and a pad layer located on the high-molecular polymer layer. The first chip is electrically connected to the substrate through the first bumps. The second chip is electrically connected to the substrate through the second bumps. The first chip and the second chip are electrically connected to the pad layer through the third bumps. The first bumps and the second bumps have the same size. The solder balls are disposed on a second surface of the substrate and electrically connected to the substrate. 1. A chip package structure , comprising:a substrate, having a first surface and a second surface opposite to each other;a first chip, disposed on the first surface of the substrate, having a first active surface facing the first surface, and comprising a plurality of first pads disposed on the first active surface;a second chip, disposed on the first surface of the substrate, having a second active surface facing the first surface, and comprising a plurality of second pads disposed on the second active surface;a bridge, comprising a high-molecular polymer layer and a pad layer located on the high-molecular polymer layer;a plurality of first bumps, disposed between the first chip and the substrate, wherein the first chip is electrically connected to the substrate through the first bumps;a plurality of second bumps, disposed between the second chip and the substrate, wherein the second chip is electrically connected to the substrate through the second bumps, wherein the first bumps and the second bumps have the same size;a plurality of third bumps, disposed between the first chip and the bridge and ...

Probe card testing device

A probe card testing device includes a first sub-circuit board, a second sub-circuit board, a connecting structure layer, a fixing plate, a probe head and a plurality of conductive probes. The first sub-circuit board is electrically connected to the second sub-circuit board by the connecting structure layer. The fixing plate is disposed on the second sub-circuit board and includes an opening and an accommodating groove. The opening penetrates the fixing plate and exposes a plurality of pads on the second sub-circuit board. The accommodating groove is located on a side of the fixing plate relatively far away from the second sub-circuit board and communicates with the opening. The probe head is disposed in the accommodating groove of the fixing plate. The conductive probes are set on the probe head and in the opening of the fixing plate. One end of the conductive probes is in contact with the corresponding pads, respectively.

CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF

The disclosure provides a circuit board structure including at least two sub-circuit boards and at least one connector. Each of the sub-circuit boards includes a plurality of carrier units. The connector is connected between the sub-circuit boards, and a plurality of stress-relaxation gaps are defined between the sub-circuit boards.

CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF

A circuit board structure includes a first sub-circuit board, a second sub-circuit board, and a third sub-circuit board. The first sub-circuit board has an upper surface and a lower surface opposite to each other, and includes at least one first conductive through hole. The second sub-circuit board is disposed on the upper surface of the first sub-circuit board and includes at least one second conductive through hole. The third sub-circuit board is disposed on the lower surface of the first sub-circuit board and includes at least one third conductive through hole. At least two of the first conductive through hole, the second conductive through hole, and the third conductive through hole are alternately arranged in an axial direction perpendicular to an extending direction of the first sub-circuit board. The first sub-circuit board, the second sub-circuit board, and the third sub-circuit board are electrically connected to one another.

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure including a circuit board and a heat generating element is provided. The circuit board includes a plurality of circuit layers and a composite material layer. A thermal conductivity of the composite material layer is between 450 W/mK and 700 W/mK. The heat generating element is disposed on the circuit board and electrically connected to the circuit layers. Heat generated by the heat generating element is transmitted to an external environment through the composite material layer. 1. A package structure , comprising:a circuit board, comprising a plurality of circuit layers and a composite material layer, wherein a thermal conductivity of the composite material layer is between 450 W/mK and 700 W/mK; anda heat generating element, disposed on the circuit board, and electrically connected to the circuit layers, wherein heat generated by the heat generating element is transferred to an external environment through the composite material layer.2. The package structure as claimed in claim 1 , wherein the composite material layer comprises a first material and a second material claim 1 , and a thermal conductivity of the first material is greater than a thermal conductivity of the second material.3. The package structure as claimed in claim 2 , wherein the first material is graphene claim 2 , and the second material is copper.4. The package structure as claimed in claim 1 , wherein the circuit layers comprise an inner circuit layer claim 1 , at least one first build-up circuit layer and at least one second build-up circuit layer claim 1 , the circuit board comprises:a core substrate, comprising a core layer, the composite material layer and the inner circuit layer, wherein the composite material layer and the inner circuit layer are respectively located on two opposite sides of the core layer;a first build-up structure, disposed on one side of the core substrate and comprising at least one first dielectric layer, the at least one first build-up circuit ...

Manufacturing method of circuit carrier board structure

A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.

Circuit board and manufacturing method thereof

A circuit board includes a composite structure layer, at least one conductive structure, a thermally conductive substrate, and a thermal interface material layer. The composite structure layer has a cavity and includes a first structure layer, a second structure layer, and a connecting structure layer. The first structure layer includes at least one first conductive member, and the second structure layer includes at least one second conductive member. The cavity penetrates the first structure layer and the connecting structure layer to expose the second conductive member. The conductive structure at least penetrates the connecting structure layer and is electrically connected to the first conductive member and the second conductive member. The thermal interface material layer is disposed between the composite structure layer and the thermally conductive substrate, and the second structure layer is connected to the thermally conductive substrate through the thermal interface material layer.

Package substrate and manufacturing method thereof

A package substrate includes a multilayer circuit structure, a gas-permeable structure, a heat conducting component, a first circuit layer, a second circuit layer and a build-up circuit structure. The gas-permeable structure and the heat conducting component are respectively disposed in a first and a second through holes of the multilayer circuit structure. The first and the second circuit layers are respectively disposed on an upper and a lower surfaces of the multilayer circuit structure and expose a first and a second sides of the gas-permeable structure. The build-up circuit structure is disposed on the first circuit layer and includes at least one patterned photo-imageable dielectric layer and at least one patterned circuit layer alternately stacked. The patterned circuit layer is electrically connected to the first circuit layer by at least one opening. The build-up circuit structure and the first circuit layer exposed by a receiving opening form a recess.

MANUFACTURING METHOD OF INTERCONNECTION STRUCTURE

An interconnection structure and a manufacturing method thereof are provided. The method includes the following steps. First, a substrate having a first surface and a second surface opposite to each other is provided. Then, a conductive through via extended from the first surface to the second surface is formed in the substrate. Then, a portion of the substrate is removed from the first surface to expose a portion of the conductive through via. Then, a dielectric layer is formed on the substrate, and the dielectric layer covers the exposed conductive through via. Then, an opening is formed in the dielectric layer, wherein the opening exposes a portion of the conductive through via, and the top surface of the conductive through via protrudes from the bottom surface of the opening. Then, a conductive layer is formed in the opening. 1. A manufacturing method of an interconnection structure , comprising:providing a substrate;forming a conductive through via in the substrate, wherein the substrate has a first surface and a second surface opposite to each other, and the conductive through via is extended from the first surface to the second surface;removing a portion of the substrate from the first surface to expose a portion of the conductive through via;forming a dielectric layer on the substrate, wherein the dielectric layer covers the exposed conductive through via;forming an opening in the dielectric layer, wherein the opening exposes a portion of the conductive through via, and a top surface of the conductive through via protrudes from a bottom surface of the opening; andforming a conductive layer in the opening, wherein the conductive layer comprises a seed layer and a conductive material layer and top surfaces of the seed layer and the conductive material layer are respectively aligned with a top surface of the dielectric layer.2. The method of claim 1 , wherein after a portion of the substrate is removed from the first surface claim 1 , the top surface of the ...

CHIP MODULE AND STACKED STRUCTURE

A chip module includes a body, a bump, and a first bonding layer. The bump is disposed on the body. The first bonding layer is disposed on the bump. The first bonding layers and the bump are made of the same conductive material and the first bonding layer is porous. 1. A chip module , comprising:a body;a bump disposed on the body; anda first bonding layer disposed on the bump, wherein the first bonding layers and the bump are made of the same conductive material and the first bonding layer is porous.2. The chip module of claim 1 , wherein the first bonding layer and the bump both are made of copper.3. The chip module of claim 1 , wherein the bump is porous-free.4. The chip module of claim 1 , wherein the first bonding layer is conformally formed on the bump.5. The chip module of claim 1 , wherein the first bonding layer is in contact with the bump.6. The chip module of claim 1 , wherein the first bonding layer is disposed on a top surface of the bump that is opposite to the body.7. The chip module of claim 1 , wherein the first bonding layer is disposed on a side wall of the bump.8. The chip module of claim 1 , wherein the first bonding layer is in contact with the body.9. A stacked structure claim 1 , comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the chip module of ; and'} a circuit layer;', 'a dielectric layer over the circuit layer and having an opening to expose a part of the circuit layer, wherein the first bonding layer of the chip module is in the opening; and', 'a patterned seed layer between the exposed part of the circuit layer and the first bonding layer of the chip module and on a sidewall of the opening, wherein the bump and the first bonding layer of the chip module and the circuit layer and the patterned seed layer of the circuit board are bonded with each other to form an integral solid structure., 'a circuit board, comprising10. The stacked structure of claim 9 , wherein the first bonding layer and the bump of the chip module and the ...

Method for forming circuit board stacked structure

A method for forming a circuit board includes forming a first dielectric layer, a first circuit layer in the first dielectric layer, a second circuit layer on the first dielectric layer, and a plurality of conductive vias in the first dielectric layer and connecting the first circuit layer to the second circuit layer; forming a second dielectric layer on the first dielectric layer and the second circuit layer; forming a plurality of openings in the second dielectric layer to expose a plurality of parts of the second circuit layer; forming a seed layer on the exposed parts of the second circuit layer and sidewalls of the openings; and forming a plurality of bonding layers on the seed layer, wherein the bonding layers and the seed layer are made of copper, and the bonding layers are porous.

PACKAGE STRUCTURE WITH STRUCTURE REINFORCING ELEMENT AND MANUFACTURING METHOD THEREOF

A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element. 1. A package structure , comprising:a redistribution structure comprising a first circuit layer and a second circuit layer disposed over the first circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer;a chip disposed over the redistribution structure and electrically connected to the second circuit layer; ["a reinforcing layer having a Young's modulus in a range of 30 to 200 GPa, wherein the reinforcing layer has a through hole; and", 'a conductive connector disposed in the through hole, wherein a top portion of the conductive connector and a bottom portion thereof are exposed outside the reinforcing layer, and the bottom portion of the conductive connector is electrically connected to the second circuit layer;, 'an inner conductive reinforcing element disposed over the redistribution structure, wherein the inner conductive reinforcing element comprisesa protective layer overlying the chip and a sidewall of the inner conductive reinforcing element; andan antenna pattern disposed over the protective layer and electrically connected to the top portion of the conductive connector.2. The package structure of claim 1 , wherein the inner conductive reinforcing element surrounds the chip.3. The package structure of ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element. 1. A package structure , comprising:a redistribution structure comprising a first circuit layer and a second circuit layer disposed over the first circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer;a chip disposed over the redistribution structure and electrically connected to the second circuit layer;one or more structural reinforcing elements disposed over the redistribution structure, wherein the structural reinforcing element has a Young's modulus of 30 to 200 GPa; anda protective layer overlying the chip and a sidewall of the structural reinforcing element.2. The package structure of claim 1 , wherein the package structure comprises one structural reinforcing element claim 1 , and the structural reinforcing element surrounds the chip.3. The package structure of claim 1 , wherein the package structure comprises a plurality of structural reinforcing elements claim 1 , and one of the structural reinforcing elements is disposed at a first side of the chip claim 1 , and another of the structural reinforcing elements is disposed at a second side of the chip claim 1 , and the second side is opposite or adjacent to the first side.4. The package structure of claim 1 , wherein the structural reinforcing ...

Embedded component structure and manufacturing method thereof

An embedded component structure includes a board, an electronic component, and a dielectric material layer. The board has a through cavity. The board includes an insulating core layer and a conductive member. The insulating core layer has a first surface and a second surface opposite thereto. The through cavity penetrates the insulating core layer. The conductive member extends from a portion of the first surface along a portion of the side wall of the through cavity to a portion of the second surface. The electronic component includes an electrode. The electronic component is disposed in the through cavity. The dielectric material layer is at least filled in the through cavity. The connection circuit layer covers and contacts the conductive member and the electrode. A manufacturing method of an embedded component structure is also provided.

METHOD FOR MANUFACTURING AN INTERPOSER, INTERPOSER AND CHIP PACKAGE STRUCTURE

A method for manufacturing an interposer includes the following steps. Conductive beads is filled in a blind via of a substrate and a solder layer of each conductive bead is melted so as to form a solder post in the blind via. A metal ball of each conductive bead is inlaid in the corresponding solder post such that the solder post and the metal balls inlaid therein construct a conductive though via. Two surfaces of the substrate are planarized such that two ends of the conductive through via are exposed to the two surfaces of the substrate respectively and are flush with the two surfaces of the substrate respectively. A redistribution layer is manufactured at each surface of the substrate such that the two ends of each conductive through via connect the redistribution layers respectively. Besides, an interposer and a chip package structure applied the interposer are also provided. 1. A method of manufacturing an interposer , comprising:providing a substrate, wherein the substrate has a first surface, a second surface opposite to the first surface, and a plurality of blind vias recessed into the first surface;filling the blind vias with a plurality of conductive beads, so that each of the blind vias has the plurality of conductive beads, wherein each of the conductive beads comprises a metal ball and a solder layer enclosing the metal ball;melting the solder layers, so as to form a plurality of solder posts in the blind vias, wherein the metal balls are inlaid in the corresponding solder posts, and each of the solder posts and the metal balls inlaid therein construct a conductive through via;planarizing the first surface of the substrate, such that a first end, close to the first surface, of each of the conductive through vias is flush with the first surface of the substrate;removing a portion of the substrate from the second surface of the substrate till a second end, close to the second surface, of each of the conductive through vias is exposed to the second ...

VAPOR CHAMBER STRUCTURE AND MANUFACTURING METHOD THEREOF

A vapor chamber structure including a thermally conductive shell, a capillary structure layer, and a working fluid is provided. The thermally conductive shell includes a first thermally conductive portion and a second thermally conductive portion. The first thermally conductive portion has at least one first cavity. The second thermally conductive portion and the first cavity define at least one sealed chamber, and a pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer covers an inner wall of the sealed chamber. The working fluid is filled in the sealed chamber. 1. A vapor chamber structure , comprising:a thermally conductive shell comprising a first thermally conductive portion and a second thermally conductive portion, wherein the first thermally conductive portion has at least one first cavity, and the second thermally conductive portion and the at least one first cavity define at least one sealed chamber, wherein a pressure in the at least one sealed chamber is lower than a standard atmospheric pressure;a capillary structure layer covering an inner wall of the at least one sealed chamber; anda working fluid filled in the at least one sealed chamber.2. The vapor chamber structure according to claim 1 , wherein the capillary structure layer comprises a first capillary structure portion and a second capillary structure portion claim 1 , wherein the first capillary structure portion at least covers an inner wall of the at least one first cavity claim 1 , and the second capillary structure portion is configured on the second thermally conductive portion.3. The vapor chamber structure according to claim 2 , wherein the first thermally conductive portion and the second thermally conductive portion are a thermally conductive plate that is integrally formed claim 2 , and the thermally conductive shell is formed by folding the thermally conductive plate in half and then sealing the thermally conductive plate.4. The ...

Vapor chamber structure and manufacturing method thereof

A vapor chamber structure includes a thermally conductive housing, a capillary structure layer, a grid structure layer, and a working fluid. The thermally conductive housing has a sealed chamber, where a pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer is disposed in the sealed chamber. The grid structure layer is disposed in the sealed chamber and arranged along a first direction. A size of the grid structure layer is less than or equal to a size of the capillary structure layer. The working fluid fills the sealed chamber.

Package structure with structure reinforcing element and manufacturing method thereof

A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.

Embedded chip package, manufacturing method thereof, and package-on-package structure

An embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is disposed inside the through-hole. The dielectric material layer is filled inside the through-hole and covers the chip. The build-up circuit structure is disposed on the circuit board. The build-up circuit structure is electrically connected to the conductive via. A lower surface of the chip is exposed outside the dielectric material layer.

Embedded component structure and manufacturing method thereof

An embedded component structure including a circuit board, an electronic component, a dielectric layer and a connection circuit layer and a manufacturing method thereof is provided. The circuit board has a through hole and includes a core layer, a first circuit layer, and a second circuit layer. The first circuit layer and the second circuit layer are disposed on the core layer. The through hole penetrates the first circuit layer and the core layer. The electronic component including a plurality of connection pads is disposed within the through hole where the dielectric layer is filled in. The connection circuit layer covers and contacts a first electrical connection surface of the first circuit layer and at least one of a second electrical connection surface of each of the connection pads.

Circuit board stacked structure and method for forming the same

A circuit board includes a first dielectric layer, a first circuit layer, a second circuit layer, a plurality of conductive vias, a second dielectric layer, a patterned seed layer, and a plurality of bonding layers. The first circuit layer is disposed in the first dielectric layer. The second circuit layer is disposed on the first dielectric layer. The conductive vias are disposed in the first dielectric layer and connect the first circuit layer to the second circuit layer. The second dielectric layer is disposed on the first dielectric layer and the second circuit layer and has a plurality of openings to expose a plurality of parts of the second circuit layer. The patterned seed layer is disposed on the exposed parts of second circuit layer and sidewalls of the openings. The bonding layers are respectively disposed on the patterned seed layer and made of porous copper.

PACKAGE CARRIER AND PACKAGE STRUCTURE

A package carrier includes a plurality of first circuit patterns, a plurality of second circuit patterns and an insulating material layer. The second circuit patterns are disposed between any two the first circuit patterns and are directly connected to the first circuit patterns. In a cross-sectional view, a first thickness of each of the first circuit patterns is greater than a second thickness of each of the second circuit patterns. A first surface of each of the first circuit patterns is aligned with a second surface of each of the second circuit patterns. The insulating material layer at least contacts the first circuit patterns. 1. A package carrier , comprising:a plurality of first circuit patterns;a plurality of second circuit patterns, disposed between any two the first circuit patterns and directly connected to the first circuit patterns, wherein in a cross-sectional view, a first thickness of each of the first circuit patterns is greater than a second thickness of each of the second circuit patterns, and a first surface of each of the first circuit patterns is aligned with a second surface of each of the second circuit patterns; andan insulating material layer, at least contacting the first circuit patterns,wherein the first thickness ranges between 70 μm and 500 μm.2. The package carrier according to claim 1 , wherein the insulating material layer is filled in gaps between the first circuit patterns and directly contacts a side surface of each of the first circuit patterns and a bottom surface of each of the second circuit patterns.3. The package carrier according to claim 1 , wherein the insulating material layer directly contacts a bottom surface of each of the first circuit patterns without contacting the second circuit patterns.4. The package carrier according to claim 3 , further comprising:a substrate, the insulating material layer being located between the first circuit patterns and the substrate.5. The package carrier according to claim 4 , ...

Package carrier having a mesh gas-permeable structure disposed in the through hole

A package carrier includes a multilayer circuit structure, at least one gas-permeable structure, a first outer circuit layer, a second outer circuit layer, a first solder mask and a second solder mask. The multilayer circuit structure has an upper surface and a lower surface opposite to each other and a plurality of through holes. The gas-permeable structure is in the form of a mesh and disposed in at least one of the through holes. The first and the second outer circuit layers respectively at least cover the upper and the lower surfaces. At least one first opening of the first solder mask exposes a portion of the first outer circuit layer and is disposed corresponding to the gas-permeable structure. At least one second opening of the second solder mask exposes a portion of the second outer circuit layer and is disposed corresponding to the gas-peiuieable structure.

Embedded component structure and manufacturing method thereof

An embedded component structure including a circuit board, an electronic component, a dielectric layer and a connection circuit layer and a manufacturing method thereof is provided. The circuit board has a through hole and includes a core layer, a first circuit layer, and a second circuit layer. The first circuit layer and the second circuit layer are disposed on the core layer. The through hole penetrates the first circuit layer and the core layer. The electronic component including a plurality of connection pads is disposed within the through hole where the dielectric layer is filled in. The Young's modulus of the core layer is greater than the Young's modulus of the dielectric layer. The connection circuit layer covers and contacts a first electrical connection surface of the first circuit layer and at least one of a second electrical connection surface of each of the connection pads. A manufacturing method of an embedded component structure is also provided.

CIRCUIT CARRIER BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF

A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided. 1. A manufacturing method of a circuit carrier board structure , comprising:providing a temporary carrier board;forming a first substrate on the temporary carrier board, wherein the first substrate has a first surface and a second surface opposite to the first surface;providing a second substrate having a third surface and a fourth surface opposite to the third surface;disposing an adhesive layer on one of the first substrate and the second substrate, wherein the adhesive layer is located between the first substrate and the second substrate;combining the second surface of the first substrate to the third surface of the second substrate; andremoving the temporary carrier board,wherein the first substrate is electrically connected to the second substrate.2. The manufacturing method of the circuit carrier board structure of claim 1 , wherein the step of forming the first substrate comprises:forming a release layer on the temporary carrier board; andforming a plurality of first build-up layers stacked on the release layer in sequence,wherein each of the first build-up layers comprises ...

CIRCUIT BOARD STRUCTURE

A circuit board structure includes a dielectric substrate, at least one embedded block, at least one electronic component, at least one first build-up circuit layer, and at least one second build-up circuit layer. The dielectric substrate includes a through cavity penetrating the dielectric substrate. The embedded block is fixed in the through cavity. The embedded block includes a first through hole and a second through hole. The electronic component is disposed in the through hole of the embedded block. The first build-up circuit layer is disposed on the top surface of the dielectric substrate and covers the embedded block. The second build-up circuit layer is disposed on the bottom surface of the dielectric substrate and covers the embedded block. 1. A circuit board structure , comprising:a dielectric substrate comprising a top surface and a bottom surface opposite to the top surface and comprising at least one through cavity penetrating the dielectric substrate;at least one embedded block fixed in the at least one through cavity, comprising a top surface and a bottom surface opposite to the top surface, and comprising at least one first through hole;at least one electronic component disposed in the at least one first through hole of the at least one embedded block;at least one first build-up circuit layer disposed on the top surface of the dielectric substrate and covering the at least one embedded block; andat least one second build-up circuit layer disposed on the bottom surface of the dielectric substrate and covering the at least one embedded block.2. The circuit board structure according to claim 1 , wherein the at least one embedded block further comprises at least one second through hole claim 1 , and the circuit board structure further comprises:at least one conductive through via disposed in the second through hole of the at least one embedded block and electrically connected to the at least one first build-up circuit layer and the at least one second ...

Heat-pipe electric power generating device and hydrogen/oxygen gas generating apparatus and internal combustion engine system having the same

Heat-pipe electric power generating device and hydrogen/oxygen gas generating apparatus and internal combustion engine system having the same

A heat-pipe electric power generating device includes a heat pipe having an evaporating end and a condensing end, a non-magnetic shell connected to the condensing end, a generator stator coil disposed at the outer of the non-magnetic shell, a turbine disposed in the heat pipe, a driving axle connected to the turbine and extended into the non-magnetic shell, and a magnetic element disposed at the driving axle and located in the non-magnetic shell. A vapor flow flowing to the condensing end is generated at the evaporating end. The vapor flow drives the turbine to move the magnetic element, such that the generator stator coil generates an induced current. In addition, a hydrogen/oxygen gas generating apparatus and an internal combustion engine system having the heat-pipe electric power generating device are also provided.

Heat-pipe electric-power generating device

A heat-pipe electric-power generating device capable of converting thermal energy to electrical energy is provided. The device includes a heat pipe and the heat pipe has a sealed internal space that can produce a steam-flow from an evaporating end to a condensing end according to a pressure difference caused by a temperature difference between the ends. A steam-flow electric-power generating device has at least a rotating portion disposed in the internal space for generating electric power when driven by a steam-flow. An electrode structure is used for leading the electric power out. The heat pipe is maintained in a sealed condition. In addition, several heat-pipe electric-power generating devices can be arranged into an array to form a heat electric-power generator or disposed inside an apparatus with a heat source for recycling the conventional waste thermal energy into useful electrical energy.

Heat -pipe electric power generating device and hydrogen/oxygen gas generating apparatus and internal combustion engine system having the same

A heat-pipe electric power generating device includes a heat pipe having an evaporating end and a condensing end, a non-magnetic shell connected to the condensing end, a generator stator coil disposed at the outer of the non-magnetic shell, a turbine disposed in the heat pipe, a driving axle connected to the turbine and extended into the non-magnetic shell, and a magnetic element disposed at the driving axle and located in the non-magnetic shell. A vapor flow flowing to the condensing end is generated at the evaporating end. The vapor flow drives the turbine to move the magnetic element, such that the generator stator coil generates an induced current. In addition, a hydrogen/oxygen gas generating apparatus and an internal combustion engine system having the heat-pipe electric power generating device are also provided.

Lighting device with flipped side-structure of LEDs

Disclosed is a lighting device with flipped side-structure of LEDs, which allows emitted lights to travel in parallel with the mounting surface. Single or plural LED chips are mounted on a substrate with their side surfaces facing the substrate surface. The lighting device can be further combined with optical protrusions on the substrate to form a light module for reflecting and mixing lights emitted from the LED chips. It does not require a conventional wire bonding process. The packaging structure also resolves the heat dissipation problem of the LEDs. Electrostatic discharge protection circuits can be included in the light module if desired. The invention achieves good uniformity and high intensity of the combined lights with desired chromaticity.

Chip package structure and manufacturing method thereof

A chip package structure includes a substrate, a chip, a thermal conductive layer, a plurality of signal contacts, and a molding compound. The substrate includes a plurality of first thermal conductive vias, a connecting circuit, and a plurality of signal vias electrically connected to the connecting circuit, and the substrate has a chip disposing region. The chip is disposed on the chip disposing region of the substrate and electrically connected to the signal vias through the connecting circuit. The thermal conductive layer is disposed over the substrate, connected to the first thermal conductive vias, and located above the chip disposing region. Besides, the thermal conductive layer has first openings exposing the signal vias. The signal contacts are respectively disposed in the first openings and connected to the signal vias. The molding compound encapsulates the chip.

Package structure and manufacturing method thereof

A package structure, including a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips, is provided. The bridge includes a silicon substrate, a redistribution layer, and multiple bridge pads. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The bridge is embedded in the intermediate layer. The bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.

Light source module, illuminating apparatus and liquid crystal display

A light source module including an optical plate and at least one light emitting device is provided. The optical plate includes a heat dissipation core plate and at least one electric circuit layer disposed thereon. The light emitting device is disposed on the optical plate and electrically connected to the electric circuit layer. The light source module has the advantages of simple structure and low cost. An illuminating apparatus including the light source module is also provided to generate a uniform light source. The display quality of a liquid crystal display can further be improved by including the illuminating apparatus to serve as a backlight source of the liquid crystal display.

Package structure of light-emitting diode with electrothermal component

Light source module, illuminating apparatus and liquid crystal display

A light source module including an optical plate and at least one light emitting device is provided. The optical plate includes a heat dissipation core plate and at least one electric circuit layer disposed thereon. The light emitting device is disposed on the optical plate and electrically connected to the electric circuit layer. The light source module has the advantages of simple structure and low cost. An illuminating apparatus including the light source module is also provided to generate a uniform light source. The display quality of a liquid crystal display can further be improved by including the illuminating apparatus to serve as a backlight source of the liquid crystal display.

Circuit board structure and manufacturing method thereof

A circuit board structure and a manufacturing method thereof are provided. The circuit board structure includes a composite substrate, a dielectric layer, and a circuit layer. The composite substrate includes a metal substrate doped with non-metal powders and a metal buffer layer. A surface of the metal buffer layer opposite to the other surface of the metal buffer layer in contact with the metal substrate is treated by a polishing process. The dielectric layer is formed on the polished surface of the metal buffer layer, and the circuit layer is formed on the dielectric layer. Alternatively, a barrier layer is interposed between the dielectric layer and the metal buffer layer for preventing a diffusion effect of the metal buffer layer.

Embedded chip package, manufacturing method thereof, and package-on-package structure

An embedded chip package includes a circuit board, a chip, a dielectric material layer, and a build-up circuit structure. The circuit board includes a glass substrate and at least one conductive via. The glass substrate has a first surface, a second surface opposite the first surface, and a through-hole penetrating the glass substrate. The conductive via penetrates the glass substrate. The chip is disposed inside the through-hole. The dielectric material layer is filled inside the through-hole and covers the chip. The build-up circuit structure is disposed on the circuit board. The build-up circuit structure is electrically connected to the conductive via. A lower surface of the chip is exposed outside the dielectric material layer.

Circuit board and manufacturing method thereof

A circuit board includes a composite layer of a non-conductor inorganic material and an organic material, a plurality of conductive structures, a first built-up structure, and a second built-up structure. The composite layer of the non-conductor inorganic material and the organic material has a first surface and a second surface opposite to each other and a plurality of openings. The conductive structures are respectively disposed in the openings of the composite layer of the non-conductor inorganic material and the organic material. The first built-up structure is disposed on the first surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures. The second built-up structure is disposed on the second surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures.

Chip package structure and manufacturing method th

Lighting device with flipped side-structure of LEDs

Disclosed is a lighting device with flipped side-structure of LEDs, which allows emitted lights to travel in parallel with the mounting surface. Single or plural LED chips are mounted on a substrate with their side surfaces facing the substrate surface. The lighting device can be further combined with optical protrusions on the substrate to form a light module for reflecting and mixing lights emitted from the LED chips. It does not require a conventional wire bonding process. The packaging structure also resolves the heat dissipation problem of the LEDs. Electrostatic discharge protection circuits can be included in the light module if desired. The invention achieves good uniformity and high intensity of the combined lights with desired chromaticity.

Measuring apparatus that includes a chip having a through silicon via, a heater, and a stress sensor

A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface.

Composite mode transducer and cooling device having the composite mode transducer

A composite mode transducer for dissipating heat generated by a heat generating element is disclosed. The composite mode transducer includes a transducing module and connection elements. The transducing module includes first and second transducing elements connected in parallel. The connection elements are connected to resonance nodes of the first and second transducing elements. The first and second transducing elements are driven by a multiple-frequency resonance circuit, to produce resonance vibration of composite modes at resonance vibration frequencies of the system. The resulting advantages by using the composite mode transducer are: elimination of local stress concentration, and enhancement of efficiency, endurance and stability of the system. Accordingly, drawbacks of the prior art are overcome. The present invention further provides a cooling device with the composite mode transducer.

Circuit board stacked structure and method for forming the same

A circuit board includes a first dielectric layer, a first circuit layer, a second circuit layer, a plurality of conductive vias, a second dielectric layer, a patterned seed layer, and a plurality of bonding layers. The first circuit layer is disposed in the first dielectric layer. The second circuit layer is disposed on the first dielectric layer. The conductive vias are disposed in the first dielectric layer and connect the first circuit layer to the second circuit layer. The second dielectric layer is disposed on the first dielectric layer and the second circuit layer and has a plurality of openings to expose a plurality of parts of the second circuit layer. The patterned seed layer is disposed on the exposed parts of second circuit layer and sidewalls of the openings. The bonding layers are respectively disposed on the patterned seed layer and made of porous copper.

Semiconductor device

Package structures for integrating thermoelectric components with stacking chips

Package structures for integrating thermoelectric components with stacking chips are presented. The package structures include a chip with a pair of conductive through vias. Conductive elements are disposed one side of the chip contacting the pair of conductive through vias. Thermoelectric components are disposed on the other side of the chip, wherein the thermoelectric component includes a first type conductive thermoelectric element and a second type conductive thermoelectric element respectively corresponding to and electrically connecting to the pair of conductive through vias. A substrate is disposed on the thermoelectric component, wherein the thermoelectric component, the pair of conductive through vias and the conductive element form a thermoelectric current path. Therefore, heat generated from the chip is transferred outward through a thermoelectric path formed from the thermoelectric components, the conductive through vias and the conductive elements.

Heat-pipe electric-power generating device

A heat-pipe electric-power generating device capable of converting thermal energy to electrical energy is provided. The device includes a heat pipe and the heat pipe has a sealed internal space that can produce a steam-flow from an evaporating end to a condensing end according to a pressure difference caused by a temperature difference between the ends. A steam-flow electric-power generating device has at least a rotating portion disposed in the internal space for generating electric power when driven by a steam-flow. An electrode structure is used for leading the electric power out. The heat pipe is maintained in a sealed condition. In addition, several heat-pipe electric-power generating devices can be arranged into an array to form a heat electric-power generator or disposed inside an apparatus with a heat source for recycling the conventional waste thermal energy into useful electrical energy.

Electronic packaging structure and manufacturing method thereof

An electronic packaging structure including a first circuit structure, a second circuit structure and at least one electronic device is provided. The bottom side of the first circuit structure has at least one cavity. The first circuit structure is disposed on the second circuit structure. The first circuit structure and the second circuit structure are electrically connected to each other. The electronic device is disposed on the second circuit structure. The electronic device is disposed corresponding to the cavity of the first circuit structure.

Manufacturing method of circuit carrier board structure

A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.

Multi-layered resonator circuit structure and multi-layered filter circuit structure

A multi-layered resonator circuit structure and a multi-layered filter circuit structure. The multi-layered resonator circuit structure includes a multi-layered substrate, a plurality of resonators and a plurality of conductive components. The multi-layered substrate has a top surface, a bottom surface, and a ground layer. The top surface and the bottom surface face away from each other. The ground layer is located between the top surface and the bottom surface. A part of the plurality of resonators is/are disposed on the top surface. Another part of the plurality of resonators is/are disposed on the bottom surface. The plurality of conductive components is located in the multi-layered substrate. The plurality of resonators is electrically connected to the ground layer, respectively, via the plurality of conductive components.

Probe card testing device

A probe card testing device includes a first sub-circuit board, a second sub-circuit board, a connecting structure layer, a fixing plate, a probe head and a plurality of conductive probes. The first sub-circuit board is electrically connected to the second sub-circuit board by the connecting structure layer. The fixing plate is disposed on the second sub-circuit board and includes an opening and an accommodating groove. The opening penetrates the fixing plate and exposes a plurality of pads on the second sub-circuit board. The accommodating groove is located on a side of the fixing plate relatively far away from the second sub-circuit board and communicates with the opening. The probe head is disposed in the accommodating groove of the fixing plate. The conductive probes are set on the probe head and in the opening of the fixing plate. One end of the conductive probes is in contact with the corresponding pads, respectively.

Apparatus and method for detecting defect between conducting wires and dielectric material of wafer semiconductor and circuit board

Electronic packaging structure and manufacturing method thereof

An electronic packaging structure including a first circuit structure, a second circuit structure and at least one electronic device is provided. The first circuit structure includes a bottom conductive plate having at least one cavity. The first circuit structure is disposed on the second circuit structure. The first circuit structure and the second circuit structure are electrically connected to each other. The electronic device is disposed on the second circuit structure. The electronic device is disposed corresponding to the cavity of the first circuit structure.

Vapor chamber structure and manufacturing method thereof

A vapor chamber structure includes a first flexible substrate, a second flexible substrate, a spacer, a flexible sealing member, and a working fluid. The first flexible substrate includes a first organic material layer, a first copper foil layer, and a first capillary structure layer. The second flexible substrate includes a second organic material layer, a second copper foil layer, and a second capillary structure layer. The first copper foil layer, the first capillary structure layer, the spacer, the second copper foil layer, and the second capillary structure layer are retracted by a distance relative to the first and second organic material layers to form a space. The first and second organic material layers and the flexible sealing member define a sealed chamber. The working fluid is disposed in the sealed chamber and located among the first and second capillary structure layers and grooves of the spacer.

Electronic package structure and manufacturing method thereof

An electronic package structure and its manufacturing method are provided. The electronic package structure includes an interposer, a circuit board, a chip, and a circuit structure. The interposer includes an interposer substrate and a coaxial conductive element located in the interposer substrate. The interposer substrate includes a cavity. The coaxial conductive element includes a first conductive structure, a second conductive structure surrounding the first conductive structure, and a first insulation structure. The first insulation structure is disposed between the first and second conductive structures. The circuit board is disposed on a lower surface of the interposer substrate and electrically connected to the coaxial conductive element. The chip is disposed in the cavity and located on the circuit board, so as to be electrically connected to the circuit board. The circuit structure is disposed on an upper surface of the interposer substrate and electrically connected to the coaxial conductive element.

Package structures for integrating thermoelectric components with stacking chips

Package structures for integrating thermoelectric components with stacking chips are presented. The package structures include a chip with a pair of conductive through vias. Conductive elements are disposed one side of the chip contacting the pair of conductive through vias. Thermoelectric components are disposed on the other side of the chip, wherein the thermoelectric component includes a first type conductive thermoelectric element and a second type conductive thermoelectric element respectively corresponding to and electrically connecting to the pair of conductive through vias. A substrate is disposed on the thermoelectric component, wherein the thermoelectric component, the pair of conductive through vias and the conductive element form a thermoelectric current path. Therefore, heat generated from the chip is transferred outward through a thermoelectric path formed from the thermoelectric components, the conductive through vias and the conductive elements.

Wafer-To-Wafer Stacking

a wafer-to-wafer stacking having a hermetic structure formed therein is provided. The wafer stacking includes a first wafer, including a first substrate and a first device layer having thereon at least one chip and at least one low-k material layer, a second wafer disposed above the first wafer and having a second substrate, and a closed structure disposed on the at least one chip and arranged inside a cutting edge of the at least one chip, wherein the closed structure is extended from one side of the first device layer far from the first substrate to the other side thereof adjacent to the first substrate.

Structure to reduce stress for vias and a fabricating method thereof

Interposer and manufacturing method therefor

Package structure

A package structure includes a first circuit board, a second circuit board, at least one electronic component, at least one conductive lead, and a molding compound. The first circuit board includes a first circuit layer and a second circuit layer. The second circuit board includes a third circuit layer and a fourth circuit layer. The electronic component is disposed between the first circuit board and the second circuit board. The conductive lead contacts at least one of the second circuit layer and the third circuit layer. The conductive lead has a vertical height, and the vertical height is greater than a vertical distance between the second circuit layer and the third circuit layer. The molding compound covers the first circuit board, the second circuit board, the electronic component, and the conductive lead. The molding compound exposes the first circuit layer and the fourth circuit layer, and the conductive lead extends outside the molding compound.

Fabricating method and testing method of semiconductor device and mechanical integrity testing apparatus

Side structure of a bare LED and backlight module thereof

The present invention discloses a side structure of a bare LED and a backlight module thereof, wherein the backlight module is preferably a light source of a display device such as an LCD device. The backlight module includes a flat plate covered with a thermally conductive dielectric material, a plurality of the side structures of the bare LEDs placed on the flat plate and in contact with the thermally conductive dielectric material, and a plurality of reflection parts also placed on the flat plate, each side structure of each bare LED includes a bare LED and two electrically conductive materials coupled to two bonding pads of the side structure of the bare LED respectively, and positioned on the flat plate therefor.

Apparatus and method for detecting defect between conducting wires and dielectric material of wafer semiconductor and circuit board

Hermetic wafer-to-wafer stacking

Light cosmetic mask and light module unit

Structure for reducing stress for vias and fabricating method thereof

A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.

Heat dissipation structure for electronic device and fabrication method thereof

A heat dissipation structure for an electronic device includes a body having a first surface and a second surface opposite to the first surface. A silicon-containing insulating layer is disposed on the first surface of the body. An ultrananocrystalline diamond film is disposed on the silicon-containing insulating layer. A first conductive pattern layer is disposed on the silicon-containing insulating layer and enclosed by the ultrananocrystalline diamond film, wherein the ultrananocrystalline diamond film and the first conductive pattern layer do not overlap with each other as viewed from a top-view perspective. A method for fabricating a heat dissipation structure for an electronic device and an electronic package having the heat dissipation structure are also disclosed.

Wafer-to-wafer stack with supporting pedestal

An electronic device having a stacked structure is provided. The electronic device includes a first electronic layer, a second electronic layer disposed on the first electronic layer, and at least a post. The first electronic layer has a first interface, and including a first substrate and a first device layer disposed on the first substrate. The first interface is located between the first substrate and the first device layer, and the first device layer has a surface opposite to the first interface. The post is arranged in the first device layer, and extending from the first interface to the surface of the first device layer.

Light cosmetic mask and light module unit

Interconnect structure with stress buffering ability and the manufacturing method thereof

IC apparatus, system and method for measuring

Composite mode transducer and cooling device with the composite mode transducer

Packages integrating thermoelectric components with semiconductor chips