Manufacturing method of semiconductor device and semiconductor device

Technical Field

And then discloses this embodiment relates to a method of manufacturing a semiconductor device and semiconductor device.

Background Art

In recent years, to reduce the size of electronic devices, high-performance and the requirements of cost is reduced, accompanied by each semiconductor chip miniaturization and increase of the terminal, is arranged on the semiconductor chip and the miniaturization of the circuit board and stratification of the electronic component on the circuit board to the development of high-density mounting.

The circuit board has been divided into various kinds and becomes very complicated. Such as pseudo-system-on-chip (pseudo   system   on   chip, pseudo   SOC) technology the described, through the use of substrate have been studied to circuit technology of integrally formed, the substrate is by the use of resin packaging a plurality of semiconductor chips with different characteristics, to form. In the pseudo-SOC technology, the re-routing layer (rewiring   layer) which is used for the semiconductor chip adjacent to the wiring part is electrically connected with each other, and so on, is formed in a plurality of semiconductor chips are embedded in the reconstruction of the wafer (  wafer reconstructed).

As a metal material used for forming the pattern, a plurality of technical development has been to develop.

Patent literature 1: discloses number 2009-64954 Japanese Patent;

Patent literature 2: Patent number 4543089 Japanese Patent;

Patent literature 3: discloses number 2001-351923 of the Japanese Patent.

Content of the invention

The purpose of this invention is to provide a method for forming a wiring layer of the optimal shape of the method of manufacturing a semiconductor device.

According to one aspect of the embodiment of, the present invention provides a method of manufacturing a semiconductor device, comprising: forming an insulating layer on a substrate; forming a recess in the stated insulating layer; the insulating layer form a mask pattern, the mask pattern has exposed the 1st opening of the concave part, and the opening is arranged on the outside of the 1st and 2nd is not exposed by the opening of the concave part; the 2nd 1st opening and the opening in the depositing a conductive material to form conductive member 1st and 2nd conductive member; and the upper side of the polishing and removing the insulating layer on the conductive part and the 2nd 1st conductive member in the concave portion in order to leave the stated 1st conductive part.

Through the special pointed out that the element and assembly and can be realized the purpose and advantage of the embodiment.

Understandably, the foregoing general description and the following detailed description are exemplary and explanatory, but not for the protection of the rights requested by the restrictions of the embodiment of.

Description of drawings

Figure 1A is illustrative plan view of a pseudo-SOC according to the embodiment of the wafer;

Figure 1B and Figure 1C is illustrative cross-sectional diagram of a pseudo-SOC according to the embodiment of the wafer;

Figure 2A to Figure 2D is illustrative cross-sectional diagram of the embodiment of shown in pseudo-SOC according to the method of manufacturing a wafer of the main process;

Figure 2E to Figure 2H is illustrative cross-sectional diagram of the embodiment of shown in pseudo-SOC according to the method of manufacturing a wafer of the main process;

Figure 2I to Figure 2L is illustrative cross-sectional diagram of the embodiment of shown in pseudo-SOC according to the method of manufacturing a wafer of the main process;

Figure 2M to Figure 2P is illustrative cross-sectional diagram of the embodiment of shown in pseudo-SOC according to the method of manufacturing a wafer of the main process;

Figure 2Q to Figure 2S is illustrative cross-sectional diagram of the embodiment of shown in pseudo-SOC according to the method of manufacturing a wafer of the main process;

Fig. 2T to Figure 2V is illustrative cross-sectional diagram of the embodiment of shown in pseudo-SOC according to the method of manufacturing a wafer of the main process;

Figure 3A and Figure 3B is illustrative plan view of a pseudo-SOC according to the embodiment of the wafer, and the pseudo-SOC wafer are formed in the wiring conductive member and the conductive member;

Figure 4A and Figure 4B is illustrative plan view of a sample in experiment of 1st;

Figure 4C is illustrative plan view of a sample in experiment of 1st;

Figure 5A to Figure 5C is illustrative cross-sectional diagram of the sample in the 1st experiment showing the manufacturing method of the main process;

Figure 5D to Figure 5F is illustrative cross-sectional diagram of the sample in the 1st experiment showing the manufacturing method of the main process;

Figure 6A and Figure 6B is illustrative plan view of a sample in experiment of 1st;

Figure 6C and Figure 6D is illustrative plan view in the experiment of 1st compared with the sample;

Figure 7A is curves of 1st experiment of the sample in the SUMMARY is shown and the height of the coating of the control sample;

Figure 7B is curves of 1st experiment showing in SUMMARY the sunken conductive member;

Figure 8 is graph of experimental 1st is shown in SUMMARY in warpage of the substrate of the sample;

Figure 9A and 9B describe experimental 2nd are respectively shown in the trench the width of the opening of the height of the curve of the relationship between, and in 2nd experiment describe poroid opening diameter of the curve of the relation between the height of the plating layer;

Figure 10A and 10B are respectively shown be described on the whole surface is formed in the substrate of the wiring forming layer cu of the cross-section of the Image SIM, separate and be described and formed on the substrate of the wiring forming layer cu of the cross-section of the Image SIM.

Mode of execution

Will be described according to the embodiment of the invention for a pseudo-SOC manufacturing method of the wafer.

First of all, reference Figure 1A to fig. 1C describe through the manufacturing method of the embodiment of a pseudo-SOC illustrative structure of the wafer.

Figure 1A is of cross-sectional view according to an embodiment of the layout of the pseudo-SOC wafer, and Figure 1B and 1C is according to the embodiment of the pseudo-SOC wafer. Figure 1B and 1C along the map are 1A line shown in a cross-sectional view and B-B C-C.

In the resin substrate 1a (in-plane) direction of the plane are arranged side-by-side on a plurality of semiconductor chip 1b and 1c are packaged in the resin substrate 1a in, in order to form a reconfigurable wafer 1. In reconstructing the wafer 1 in, into one unit to set a plurality of semiconductor chip (for example, logic and memory chip) is arranged next to each other, and a plurality of units arranged in a matrix form. Pseudo-SOC after the completion of the wafer, the plurality of unit are separated from each other, in order to form each product.

Figure 1A to fig. 1C (and the following description of Figure 2A to fig. 2V, Figure 3A, Figure 3B) shown in an area in the vicinity of a unit, by the two semiconductor chips and 1b and 1c form a unit of Un.

The re-routing layer 21 formed on the reconstruction wafer 1 on. The re-routing layer 21 include used for the semiconductor chip 1b and 1c are electrically connected with each other by the wiring portion 21a, and the draw-out wiring portion to the outside. As shown in Figure 1A shown in a plan view of, in this example, is used for the semiconductor chip 1b and 1c are electrically connected with each other with a plurality of wiring 21a are arranged parallel to each other. Figure 1B is cross-sectional view of along the wiring 21a in the lengthwise direction and the cross-sectional view through the wiring 21a of the part. Figure 1C is cross-sectional view of along the wiring 21a of the width direction of the Figure and the cross section of the wiring 21a cross-part of the.

The routing part 21a is composed of a pattern (2 the   m or smaller line-and-space pattern) to form a fine wiring (  wiring fine), in the pattern, the width of each wiring is the 2   m or less, and in the pattern, the wiring adjacent to each other is the clearance between the the 2   m or less. As will be described below, in this embodiment, fine wiring (for example, wiring 21a) is formed by damascene (damascene).

Next, the reference chart 2A to 2V and reference map 3A and 3B described according to the embodiment of the pseudo-SOC manufacturing method of the wafer. Figure 2A to fig. 2V each of the map is along the 1A a cross-sectional view in line B-B, and shown according to the embodiment of the pseudo-SOC wafer manufacturing method of the main process.

The reference Figure 2A. Preparing the reconstruct the wafer 1. The semiconductor chip 1b and 1c in a reconstruction wafer 1 and the in-plane direction is arranged, so as to expose the semiconductor chip 1b and 1c of the surface, in the semiconductor chip 1b and 1c are positioned on the surface of the terminal. For packaging semiconductor chip 1b and 1c of the resin material (resin substrate 1a material) is an insulating resin, for example, acrylic acid aliphatyl (acrylate-based) resin.

The reference Figure 2B. The seed layer 2 is formed on the resin substrate 1 on the whole surface of. For example, the seed layer 2 is deposited by sputtering to a thickness of 20 nm of Ti layer, by using sputtering and is deposited on the Ti layer in a thickness of 100 nm (copper) layer of formed cu. The Ti layer is formed on the Ti layer between part and substrate cu the adhesion performance function, and prevent oxidation and diffusion function of cu.

The reference Figure 2C. The seed layer 2 to form the thickness of the resist coated on for example the 8   m of the resist layer. Resist pattern RP1 is through exposure resist layer, then utilize such as tetramethyl ammonium hydroxide (TMAH) to develop exposed to form the resist layer. Resist pattern RP1 in the semiconductor chip 1b and 1c on each of the terminals is provided with an opening.

The reference Figure 2D. For example, by using the seed layer 2 as power supply level (power   feeding   layer) to deposit the cu carry on electrolytic plating used as the conductive material, the resist pattern RP1 to an opening formed in each of the pin (pin) 3. Pin 3 is, for example, the height of the coating of the the 3  m. Each pin 3 is electrically connected with the semiconductor chip 1b and 1c of each terminal. Is should be noted, can be appropriately selected according to the design of pin 3 of the height of the plating layer.

The reference Figure 2E. The acetone or the like by removing the resist pattern RP1. Furthermore, remove the pin 3 external seed layer 2. Pin 3 electrically separated from each other. For example, by the use of etching solution of potassium sulfate to carry out wet etch to remove seed layer 2 of layer cu. For example, by using ammonium fluoride solution as the etching solution for wet etching, or such as through the use of CF₄ and O₂ mixed gas as etching gas of dry etching is carried out to remove the seed layer 2 of the Ti layer.

The reference Figure 2F. Embedded with pin 3 of the insulating layer 4 is formed in such a manner: by rotating the coating to coating 4 the thick   m the phenol-based resin, then in the 200 to [...] the 250 [...] (for example, a 250 [...]) carried out under the temperature of curing (hardening).

Reference fig. 2 g. By means of chemical mechanical polishing (chemical   mechanical   polishing, CMP) to polish and remove the insulating layer 4 on the upper part of the, so as to expose the pin 3 of the upper surface.

The reference Figure 2H. For example, the insulating layer 4 is coated on the 2   m thick photosensitive phenol-based resin to form the insulating layer 5. In the subsequent process, the wiring 10 is formed in a wiring groove 6 (  groove wiring) in, the wiring trench 6 is formed on the insulating layer 5 in. According to the wiring 10 of a desired thickness appropriately selecting the insulating layer 5 has a thickness of.

The reference Figure 2I. Through the exposure and developing, in the insulating layer 5 is formed in a wiring groove for defining the 6 pattern, and in such as 250 the under [...] further curing (hardening). Formed on the insulating layer 5 in the wiring trenches 6 exposed pin 3. For example, wiring trenches 6a exposed connecting the semiconductor chip 1b of the terminal of the pin 3, and also the exposed semiconductor chip 1c pins of the terminal of the 3. Formed through the follow-up process for the wiring trench 6a wiring 21a of the semiconductor chip 1b and 1c are electrically connected with each other.

Reference to Figure 2J. The seed layer 7 is formed on the insulating layer 5 is, in order to cover the wiring trench 6 of the inner surface. For example, the seed layer 7 formed by similar to the seed layer 2 is formed in such a manner.

The reference Figure 2K. The seed layer 7 in the thickness of coating on the 8 to resist layer is formed of the resist   m RL2. Resist layer RL2 of the thickness can be thus set up in order to prevent the picture 2M shown in the follow-up process in the electroplating and deposition of a resist layer to cu RL2 on the upper surface.

The reference Figure 2 l. Exposure resist layer RL2, then develop through, for example, TMAH, in order to form the resist pattern RP2. (mask pattern) Resist pattern RP2 with exposed wiring trenches 6 wiring forming opening 8a, an opening is formed is set in the wiring and 8a and not exposed to the outside of the wiring groove 6 of the opening is formed the dummy (dummy) 8b.

The reference Figure 2 m. For example, through the use of the seed layer 7 as to carry on electrolytic plating power supply level , an opening is formed in the wiring forming of the opening 8a and 8b as cu deposition of conductive material. In the wiring forming the opening 8a in, conductive material is filled in a wiring groove 6 in, and further deposited on the insulating layer 5 on the upper surface, in order to form the wiring conductive member 9a. Wiring conductive member 9a is electrically connected with wiring trench 6 of the pin 3. In the dummy forming the opening 8b in, conductive material is deposited on the insulating layer 5 is, in order to form the dummy conductive part 9b.

The implementation of the electroplating, so that the insulating layer 5 on the upper surface of the wiring conductive member 9a is set to be, for example, the height of the coating of the the 3  m. When the wiring conductive member 9a is set to be, for example, the height of the coating of the the 3 when   m, the insulating layer 5 on the upper surface of the dummy conductive part 9b is set to be the height of the coating, e.g., of about 3.5 the  m. Such as the following to be described, preferably, the conductive dummy part 9b is higher than the upper surface of the wiring conductive member 9b of the upper surface.

The reference Figure 2N. The acetone or the like by removing the resist pattern RP2. Furthermore, by, for example, at 150 the implementation under [...] 2 minutes by electroplating growth by annealing of the formed grain cu, in order to stabilize the quality of the film cu. After the electroplating can facilitate such ideals of self-annealing of the annealing conditions, in the particularly preferred one is the 120 to [...] the 200 [...] performed in a low oxygen concentration environment 1 minutes to 10 minutes of annealing, however, the annealing can also be performed in the air. Is should be noted that, when the plating film thickness such as 3 the the   m, can even through in about 24 hours at room temperature (20 the to [...] the 25 [...]) is grown by self-annealing of the grain.

The reference Figure 2O. By CMP to polish and remove the insulation layer 5 on the upper surface of the wiring conductive member 9a and dummy conductive part 9b. Left filled in the insulating layer 5 of the wiring trench 6 the wiring conductive member in 9a, in order to form the wiring 10. Through the CMP also removes the wiring 10 external seed layer 7, so that the wiring 10 for electrically isolating each other. In particular, the semiconductor chip 1b and 1c are electrically connected with each other the wiring 10 is referred to as wiring 21a. In this way, copper wiring 10 can be formed by a damascene method. Is should be noted that here, the copper wiring includes wiring formed of a conductive material, the conductive material as required in the copper is added with other ingredients.

Figure 3A is pseudo-SOC wafer illustrative floorplan of forming wiring conductive member in 9a and dummy conductive part 9b stage. As a wiring by a damascene method for forming 10, (through point marking) typically used for illustrating the semiconductor chip 1b and 1c are connected with each other the wiring 21a.

Is should be noted that, the wiring conductive member 9a and dummy conductive part 9b are respectively corresponding to the profile of resist pattern RP2 wiring forming opening 8a and the dummy forming the opening 8b of the shaped opening. Wiring 21a corresponding to the outline of the wiring trench 6a shape.

Wiring forming the opening 8a of the opening for covering the semiconductor chip 1b and 1c, and include a wiring by a damascene method for forming a region of the shape of the wiring groove. As the dummy forming the opening 8b an example of the shape of the, chart 3A the opening of the slot is shown. The dummy forming the opening 8b is arranged in the wiring forming the opening 8a of the external, and around routing ring-shaped manner to form an opening 8a. The dummy forming the opening 8b is arranged in the semiconductor chip 1b and 1c of the external.

Un regions in the unit region (in this example means the, semiconductor chip 1b and 1c the inner region and the semiconductor chip 1b and 1c the region between) will be fixed as by a damascene method for forming wiring 10 the mount area. Therefore, the conductive dummy part 9b external Un is arranged in the unit area (in this example means that, in the semiconductor chip 1b and 1c of the external) Sc in the scribing area, adjacent to each other or in a unit area of the scribe region Un Sc in between.

The conductive member described by the dummy 9b provide advantages, the dummy conductive member 9b through the CMP polishing and removing insulating layer 5 on the upper surface of the wiring conductive member 9a in order to keep the wiring 10 has been formed when the.

First of all, consider the conductive parts not forming dummy 9b comparison example. Usually, the lug to be polished through a peripheral portion of the CMP polishing is. In this comparison example, the wiring conductive member 9a to the peripheral portion of the polishing. As a result, the wiring conductive member 9a on one side of the peripheral portion of the wiring 10 more easy polishing, it is easy to lead to depression (dishing).

In this embodiment, higher than the wiring conductive member 9a of the conductive part dummy 9b formed on the wiring conductive member 9a of the external. Therefore, dummy conductive part 9b is first on the upper part of the polishing, and therefore the wiring conductive member 9a is a peripheral portion of the polishing. Therefore, wiring can be changed can be suppressed 10 of the concave of the height of the surface.

Is should be noted that, preferably, the conductive dummy part 9b is formed to be higher than the wiring conductive member 9a. However, the conductive member is not set dummy 9b compared with the situation, the conductive member is provided with a dummy 9b under the situation, even when the dummy conductive part 9b is lower than the wiring conductive member 9a at the time, can also be expected to inhibit the wiring conductive member 9a peripheral portion of the the effect of excessive polishing.

Formed at the same time through the electrolytic plating of conductive part dummy 9b and the wiring conductive member 9a under the condition of, the following is considered as used for forming the above wiring conductive part 9a of the conductive part dummy 9b the general principles. The exposed to the dummy forming the opening 8b is less than the exposed surface area of the bottom of the wiring forming the opening 8a when the surface area of the bottom, forming an opening dummy 8b electroplating film will grow in the thickness of the wiring forming the opening 8a the growth in electroplating film, and therefore can be formed higher than the wiring conductive member 9a of the conductive part dummy 9b.

However, can be found, when the wiring forming the opening 8a is too narrow, it is very difficult to form higher than the wiring conductive member 9a of the conductive part dummy 9b. 2nd experiment with the following description will be described together with wiring forming opening 8a the appropriate size.

As shown in Figure 3B shown, conductive dummy part 9b may not be ring-shaped plane is closed. Figure 3B shown a plurality of cylindrical dummy conductive part 9b in order to randomly distributed around the wiring conductive member 9a example. Is should be noted that, the conductive dummy part 9b is not limited to the cylindrical shape of the shape of the (virtual article forming the opening 8b of the shape of the hole is not limited to the cylindrical shape).

As shown in Figure 3A shown, the wiring conductive member 9a is directed to pseudo-SOC of each unit area of the wafer which is Un. In other words, a wiring conductive part 9a cu layer is of a unit area for each separate Un and is set up, but does not need to cover the whole surface of the wafer.

When SOC cu wafer pseudo-layer is formed on the resin substrate 1a on the entire surface of, the resin material of the substrate coefficient of thermal expansion and Young's modulus (Young '   modulus s) are respectively less than cu layer of the fact that the thermal expansion coefficient and Young's modulus, the warping of the wafer, and hence the wiring forming layer by cu crack is produced in the (crack). It is to note, cu coefficient of thermal expansion and Young's modulus are 13 PPM/K and 130GPa.

In this embodiment, for each unit by separating the wiring is formed by the damascene process to form the area of the wiring conductive member 9a, and can be suppressed by the above-mentioned problem caused by the warpage of the described. However, because of such a distribution and provided with wiring conductive member 9a, so that each wiring conductive part 9a to the peripheral portion of the polishing. Dummy conductive part 9b can inhibit the wiring conductive member 9a to the problem of polishing the peripheral portion.

Reference fig. 2P will further describe the manufacturing process. For example, by rotating the coating to coating thickness is 5 the photosensitive   m phenol-based resin in order to form the insulating layer 11.

The reference Figure 2Q. Through the exposure and developing the insulating layer 11 is used for limiting is formed in the through hole 12 of the pattern, and further, the insulating layer 11 in the 250 under [...] curing (hardening). A through hole 12 exposed wiring 10.

The reference Figure 2R. Seed layer 13 is formed on the insulating layer 11 so as to cover the through hole 12 of the inner surface. For example, seed layer 13 by similar to the seed layer 2 is formed in such a manner.

The reference Figure 2S. The seed layer 13 a resist coated on a resist layer is formed. Exposing the resist layer, then develop through, for example, TMAH, in order to form the resist pattern RP3. Resist pattern RP3 is provided with an opening, the opening of each through-hole with the 12 plane shape.

The reference Figure 2 t. For example, by using the seed layer 13 carry on electrolytic plating as power supply level , the resist pattern RP3 in one opening of each of the deposited cu as the conductive material. Conductive material is filled in the through hole 12 in, and further deposited on the insulating layer 11 on the upper surface, in order to form the wiring 14. Wiring 14 is electrically connected with the wiring 10.

Reference fig. 2U. The acetone or the like by removing the resist pattern RP3. Furthermore, similar to removing the seed layer 2 is removed by way of wiring 14 external seed layer 13. Wiring 14 for electrically isolating each other.

Reference fig. 2 V. For example, the photosensitive phenol-based resin is coated on the insulating layer 11 so as to cover the wiring 14. Furthermore, photosensitive phenol-based resin on the exposure and developing, and further in such as 250 the under [...] curing (hardening), in order to form and has a through hole 15 of the insulating layer 16. Each through hole 15 is formed in each wiring 14 on the upper surface.

Next, wiring 17 forming wiring similar to 14 formed in the process of each through hole 15 is, the process reference Figure 2R to fig. 2U described.

Furthermore, with the each wiring 17 on the upper surface of the contact window 18 (contact   window) of the insulating layer 19 by similar to form the insulating layer 16 is formed of the process.

In this way, according to the present embodiment has formed the pseudo-SOC wafer. Formed in the reconstruction of the wafer 1 on the pin 3, the wiring 10, the wiring 14 and wiring 17 integral is referred to as re-routing layer 21. In this embodiment, is to use semi-addition (semi-additive) method for forming pin 3, the routing wiring 14 and 17, and a method for using an insert forming wiring 10.

Described as above, by a damascene method for forming the wiring 10 time, the dummy is conductive part 9b to be retained is formed on the wiring 10 of the wiring conductive member 9a around the implementation of the state of the polishing/removing process. Therefore, can suppress the left behind after the polishing/removing process of the wiring 10 changes the height of upper surface.

Next, describing the experimental 1st, in the experiment in the conductive member by the dummy inhibitory effect on the depression.

First of all, reference Figure 4A to 4C 1st experiment described in the illustrative form the model of the structure of the sample. Figure 4A and Figure 4B is illustrative cross-sectional view of model illustrative plan view of the sample, and Figure 4C along the map is 4A C-C line in a plan view of.

The conductive part 38 is formed on the resin substrate 31 is. Resin substrate 31 in a diameter of about 150 mm (6 inch) circular, and is formed of epoxy resin is comprises a filler. Not embedded in the resin substrate of the semiconductor chip 31 of the wafer corresponding to the reconstructed pseudo-SOC wafer.

As shown in Figure 4A of shown, 13 and Un a unit area is set on the surface of the substrate. Pseudo-SOC Un unit area corresponding to a unit area of the wafer. Each unit region is Un 10 mm square square.

As shown in Figure 4B of shown, the conductive part 38 Un in each unit area is in the form of matrix. The conductive part 38 for example corresponding to the used for the pseudo-SOC in the area of unit of the wafer adjacent to the wiring of the semiconductor chip are connected to each other, and is formed by the damascene process. Each of the conductive part 38 is a diameter of 100 the of cylindaceus   m, and about 2500 conductive part 38 is arranged in the unit area in Un.

Is should be noted that, in order to simplify the description, fig. 4A shown with the conductive part 38 and not distinguish each other. In Figure 4B in, 81 conductive member (9 rows × 9 columns) is shown as the unit region is a conductive part in Un 38. In Figure 4C in, against a unit showing 9 line conductive part 38.

Next, the reference chart 5A to fig. 5F 1st experiment will describe a model of the manufacturing method of the sample. Figure 5A to Figure 5F is cross-sectional diagram, of these cross-sectional view along the Figure 4A C-C line model is shown in the sample manufacturing method of the main process, and show a unit area close to the area of Un.

The reference Figure 5A. In the resin substrate 31 to the thickness of coating on the 5   m phenol-based resin, and then the can 250 carries on solidification under [...] (or hardening), in order to form the insulating layer 32. Furthermore, on the insulating layer 32 is coated with the thickness of 5 the photosensitive   m phenol-based resin. Through the exposure and developing the coated resin to form the is used to define the recess 33 of the pattern, then the can 250 carries on solidification under [...] , in order to form the insulating layer 34.

Seed layer 35 is formed on the insulating layer 34 so as to cover the recess 33 of the inner surface. Seed layer 35 formed in such a way: by sputtering on the insulating layer 34 is deposited to the thickness of 20 nm of Ti layer, and by sputtering is deposited on the Ti layer in a thickness of 100 nm of layer cu.

The reference Figure 5B. The seed layer 35 thickness is coated on the 5  m (as the insulating layer 34 on the upper surface of the thickness) of the resist, in order to form the resist layer RL31.

The reference Figure 5C. Confrontation RL31 an exposure and developing, in order to form the resist pattern RP31. RP31 resist pattern forming an opening having a conductive component the dummy forming the opening 36a and 36b. The conductive part forming the opening 36a in Un with the cell region including all the recess 33 of the shape, and the width is 10 mm.

The dummy forming the opening 36b is set up on the conductive part forming the opening 36a of the external. As the following description of Figure 6A shown, virtual article form an opening 36b in the form of conductive part dummy 37b when RP31 the use of a resist pattern defined in the concave part of the slot, wherein each dummy conductive part 37b in a straight line shape. As the following description of Figure 6B shown, virtual article form an opening 36b in the form a cylindrical dummy conductive part 37b resist pattern used when RP31 poroid defined in the recess.

The reference Figure 5D. By using the seed layer 35 as to deposit power supply level cu carry on electrolytic plating, an opening is formed in the conductive member 36a and the dummy forming the opening 36b respectively in the forming a conductive part 37a and dummy conductive part 37b. Insulating layer 34 on the upper surface of the conductive member 37a is the height of the coating of the the 3  m.

The reference Figure 5E. The acetone or the like by removing the resist pattern RP31. Furthermore, in the 150 implemented under [...] 2 minutes of annealing.

The reference Figure 5F. By CMP to polish and remove the insulating layer 34 on the upper surface of the conductive part 37a and dummy conductive part 37b. Leave conductive part 37a of the recess 33, in order to form the conductive part 38.

In the experiment in 1st, through changing the dummy conductive part 37b to the shape of the sunken inhibitory effect on the assessment.

Figure 6A and 6B are shown in the experiment 1st conductive part dummy 37b plan view illustrative of the form of. Figure 6A and 6B shown is formed with the conductive part 37a and dummy conductive part 37b state. Is should be noted that, the conductive part 37a and dummy conductive part 37b are respectively corresponding to the profile of resist pattern RP31 an opening is formed in the conductive parts 36a and the dummy forming the opening 36b of the shaped opening.

Figure 6A shown straight linear dummy conductive part 37b. In each unit area in Un, four straight linear dummy conductive part 37b is arranged into a ring, so that around the conductive part 37a.

Figure 6B shown a cylindrical dummy conductive part 37b. A plurality of dummy conductive member 37b so as to surround the distribution of each unit area of the conductive part of Un 37a. Is should be noted that, as Figure 6B situation, around the conductive part 37a distribution and a plurality of dummy conductive part 37b can also be overall referred to as dummy conductive part 37b.

Existing manufacturing of the four sample: formed therein with the width of 20 the sharply   m conductive part dummy 37b of sample 1st, formed therein with the width of 5 the straight dummy   m conductive part 37b of sample 2nd, wherein the formed with a diameter of 70 the a cylindrical dummy   m conductive part 37b of sample 3rd, and the diameter of which forms a 5 the cylindrical dummy   m conductive part 37b of sample 4th. Together with the four sample, producing the two kinds of control samples.

Figure 6C and Figure 6D is illustrative floorplan of the control sample are respectively shown. Figure 6C 1st control sample is shown. The 1st control sample sample is such that: in the forming a conductive part 37a in the electroplating process of cu layer 37a is formed on the whole surface of the substrate without the use of a mask pattern. Figure 6D 2nd control sample is shown. In the control sample in the 2nd, not formed a dummy conductive part 37b, and only forms the conductive part 37a to Un for each unit area to be divided.

Figure 7A is curves of 1st to 4th is shown sample SUMMARY of the coating of the sample height of the 2nd and 1st contrast sample and the height of the coating of the control sample. In in each sample, a conductive part is shown on the left side 37a the height of the coating of the (by damascene method for forming wiring forming area of the height of the plating layer), and the right side of the conductive part shown dummy 37b the height of the plating layer (the height of the coating of the dicing region).

In in each sample, the conductive part 37a the height of the coating of the same set as the 3.0  m. In 1st contrast sample (formed on the entire surface thereof cu layer a) in, cu layer of the 3.0   m can be regarded as the dummy the thickness of the conductive part 37b of the height of the plating layer. In 2nd contrast sample (having no dummy conductive member) in, conductive dummy part 37b is the height of the cladding of the 0.0  m.

Dummy conductive part 37b 1st the height of the coating of the sample (in a straight line shape and the width is 20 the  m) is in the 3.5  m, in 2nd sample (in a straight line shape and the width is 5 the  m) is in the 2.2  m, in 3rd sample (is in a cylindrical shape and the diameter of the 70  m) is in the 3.6  m, in 4th sample (is in a cylindrical shape and the diameter to the 5  m) is in the 1.7  m.

In 1st sample (in a straight line shape and the width is 20 the  m) and 3rd sample (is in a cylindrical shape and the diameter of the 70  m) in, forming higher than the conductive part 37a of the conductive part dummy 37b. In 2nd sample (in a straight line shape and the width is 5 the  m) and 4th sample (is in a cylindrical shape and the diameter to the 5  m) in, forming the lower than the conductive part 37a of the conductive part dummy 37b.

Figure 7B shown in the 1st and 4th sample to sample the control samples and 1st 2nd application control sample left behind after the CMP of the conductive part 38 of the curve chart summarizing sunken. In the unit area on the outermost periphery of the conductive part 38 for measuring the sunken.

The sunken 1st contrast sample (formed on the entire surface thereof with cu layer) was 180 nm, compared with the sample in the 2nd (has no dummy conductive member) is 360 nm, in 1st sample (in a straight line shape and the width is 20 the  m) is 150 nm, the 2nd sample (in a straight line shape and the width is 5 the  m) is 300 nm, in 3rd sample (is in a cylindrical shape and the diameter of the 70  m) is 160 nm, sample in the 4th and (is in a cylindrical shape and the diameter to the 5  m) is 310 nm.

As can be seen, and 2nd contrast sample (having no dummy conductive part) compared, in which conductive parts formed with a dummy 37b of the sample in the sample to 4th 1st, sunken is suppressed. In 1st contrast sample (formed on the entire surface thereof cu layer a) in, warping of the substrate as mentioned above it is easy to produce, however, because the cu layer is formed on the whole surface of the sample, it is very difficult to produce the recess. As can be seen, are formed in each of which is higher than the conductive part 37a of the conductive part dummy 37b of the sample in the sample and 3rd 1st, the dent in the 1st control sample is suppressed to the same extent.

Figure 8 shown rollup 1st and 2nd control samples compared with the sample of the curve chart of the warpage of the substrate. In 1st contrast sample (formed on the entire surface thereof cu layer a) in, the warping cu layer on the side of the surface of, the substrate relative to the center portion of the recessed edge portion of the substrate. Through the substrate center portion and the edge portion of the substrate between warpage the height of the estimated difference.

1st contrast sample (on the entire surface thereof cu layer is formed) in the warping amount of the electroplating cu is 0.3 mm, and the after electroplating cu [...] to 0.6 mm. 2nd contrast sample (having no dummy conductive part) the warping amount of the electroplating cu is 0.01 mm, and the remains after annealing 0.01 mm. In the 2nd control sample, is formed on the substrate through the separated cu layer (conductive part 37a) suppressing warping. Similarly, in the 1st to 4th in the sample of the sample, by separating the cu layer (conductive part 37a) warping can be suppressed.

Next, 2nd experiment will be described, the experiment is carried out in order to study used for forming the dummy mask pattern of the conductive members is arranged in the dummy forming the opening of the appropriate size. In the experiment the 2nd, is formed in the resist layer with various size of the opening and through the said opening to carry on electrolytic plating cu layer deposited in the opening size of the study of the relationship between and the plating layer height.

Forming with diagram 6A the linear dummy shows straight the slot-like opening corresponding to the conductive parts, with diagram and 6B cylindrical dummy is shown corresponding to a conductive part of the pore opening. The width of the slot-like opening is changed to the 100  m, the 70  m, the 50  m, the 30  m, the 15  m, the 8  m, the 5 the   m and 2  m. Change of the diameter of the hole opening for the 100  m, the 70  m, the 50  m, the 40  m, the 30  m, the 20  m, the 10 the   m and 5  m.

Figure 9A described is shown and the plating layer the width of the opening of the slot height of the curve chart of the relationship between. As can be seen, slot-like opening that, when its width is smaller than the 15 the   m, the coating height is lowered. By so, it is able, to form the straight linear dummy the conductive part, in order to inhibit reduce the height of the plating layer, preferably the width of the opening of the slot is set to be 15 the   m or more.

Figure 9B poroid described is shown and the plating layer height of the diameter of the curve chart of the relationship between. As can be seen, opening on the hole, when its diameter is smaller than the 40 the   m, the coating height is lowered. It is note, in the form a cylindrical conductive member, in order to suppress the height of the plating layer is reduced, the diameter of the hole-like opening is preferably set as the 40   m or more.

Attention is to be considered, the preferred size of the opening is not limited to the situation of cu, and can be basically applicable to similar formed by the electrolytic plating of the conductive material.

Next, will be described the process of forming wiring of the wiring caused by differences in the different characteristics. If the above described, when the pseudo-SOC by a damascene method for forming the wiring of the wafer, and when the resin is formed on the entire surface of the substrate when the electroplated layer, the wafer warping, cracks can be generated in the wiring. On the other hand, when the plating layer is formed in the resin substrate is each other, warping can be inhibited, and thus improve the quality of the wiring.

Figure 10A shown electronic microscope picture, the electronic microscope picture of the scanning ion microscope (scanning   ion   microscope, SIM) shooting, and shown formed in this manner the cross section of the wiring of the: cu layer is formed in and on the entire surface of the substrate does not need to be part of the layer for polishing and removing cu.

Figure 10B shown electronic microscope picture, the electronic microscope picture of the shooting SIM, and shown formed in this manner the cross section of the wiring of the: cu layer is formed on the substrate are separated from each other, and does not need to be part of the layer for polishing and removing cu.

In Figure 10A and 10B shown in two samples, after the electroplating layer cu, grain cu carry out annealing to grow. Grain from the wiring of the upper portion of the wiring facing the lower part of the growth.

In Figure 10A in the sample, cu layer formed on the whole surface of the substrate, wherein such a pattern can be observed, in the pattern, grain growth stop in mid-thickness, thus divided into the pattern with growth of the crystal grain growth of the lower layer and the upper layer of the crystal grain. In Figure 10A in the sample, by the substrate under the state of warpage and stress cu layer to carry out the annealing. It that, this will lead to growth of the grain is very difficult.

On the other hand, in Figure 10B in the sample, cu layer is formed on the substrate are separated from each other, wherein the grain can be observed from the following table of cu layer on the surface-oriented. It that, because the are separated from each other by forming layer suppresses cu the warping, stress can be reduced, and thus and Figure 10A compared with the sample shown, grain, easy growth. For example, can be considered that, in the above-mentioned embodiment of the copper wiring 10 in, can also be as shown in Figure 10B obtained in the sample shown, as the whole thickness of the wiring on the growth of the crystal grain.

As mentioned above, has made reference to in the embodiment described of the invention, but the invention is not limited to the above embodiment. For example, the staff it is in this field, without departing from the invention within the spirit and scope of, the various changes of the invention, modified, combined, and the like.

In all of the examples described herein and conditional language is used for teaching purposes in order to help the reader understand the invention and the inventor proposed to promote the concept of the prior art, and can be interpreted as is not limited to these specific example and conditions described, the organization of the example in the specification to the description of the present invention to pros and cons. Despite the detailed description of the embodiments of the present invention, but it is understandable that, without departing from the spirit of this invention and within the scope, of the present invention is used as the various changes, substitution, alteration and.