СПОСОБ ВСТРАИВАНИЯ КОМПОНЕНТА В ОСНОВАНИЕ

Изобретение относится к способу, согласно которому полупроводниковые компоненты, образующие часть электронной схемы, или по меньшей мере некоторые из таких компонентов, встраивают в основание, например, в печатную плату в процессе ее изготовления. Технический результат - создание способа, посредством которого бескорпусные микросхемы могут быть встроены в основание надежным, но экономичным образом. Достигается тем, что в основании выполняют сквозные отверстия для полупроводниковых компонентов, причем отверстия проходят между первой и второй поверхностями основания. После выполнения отверстий на вторую поверхность структуры основания наносят полимерную пленку, причем полимерная пленка закрывает сквозные отверстия для полупроводниковых компонентов со стороны второй поверхности структуры основания. Перед отверждением полимерной пленки или после ее частичного отверждения в отверстия вводят полупроводниковые компоненты со стороны первой поверхности. Полупроводниковые компоненты прижимают к полимерной ...

АРХИТЕКТУРА СОЗДАНИЯ ГИБКИХ КОРПУСОВ

ГЕРМЕТИЗИРОВАННЫЕ ИМПЛАНТИРУЕМЫЕ ГЛАЗНЫЕ УСТРОЙСТВА И СПОСОБЫ ИХ ИЗГОТОВЛЕНИЯ

... 1. Имплантируемое глазное устройство, содержащее:первую подложку, имеющую герметизированное межслойное соединение, обеспечивающее проводящий путь для электрической связи от первой стороны первой подложки ко второй стороне первой подложки;вторую подложку, соединенную с первой стороной первой подложки для по меньшей мере частичного формирования герметизированной полости; иэлектронный компонент в герметизированной полости, находящийся в электрической связи с проводящим путем, обеспечиваемым герметизированным межслойным соединением.2. Имплантируемое глазное устройство по п. 1, в котором герметизированное межслойное соединение содержит канал, соединяющий первую и вторую стороны первой подложки, и проводящий материал в канале для обеспечения проводящего пути.3. Имплантируемое глазное устройство по п. 2, в котором проводящий материал имеет коэффициент теплового расширения, приблизительно равный коэффициенту теплового расширения первой подложки.4. Имплантируемое глазное устройство по п. 3, в котором ...

Kontaktsystem mit einem Verbindungsmittel und Verfahren

Die Erfindung betrifft ein Kontaktsystem. Das Kontaktsystem umfasst wenigstens ein insbesondere elektronisches Bauelement. Das Bauelement weist wenigstens einen elektrischen Anschluss auf. Das Kontaktsystem weist wenigstens eine elektrisch leitfähige Schicht auf. Der Anschluss des Bauelements und die elektrisch leitfähige Schicht sind mittels eines elektrisch leitfähigen Verbindungsmittels miteinander verbunden. Erfindungsgemäß ist das elektrisch leitfähige Verbindungsmittel zum Teil mittels eines thermischen Spritzverfahrens und zum Teil mittels Galvanisieren erzeugt.

Halbleitergehäuse und Verfahren zu ihrer Herstellung

Verfahren zum Herstellen eines Halbleitergehäuses, wobei das Verfahren umfasst:Ausbilden mehrerer erster Chipöffnungen (20) auf einem Laminatsubstrat (10), wobei das Laminatsubstrat (10) eine Vorderseite (11) und eine gegenüberliegende Rückseite (12) aufweist;Anordnen mehrerer erster Chips (110) in den mehreren ersten Chipöffnungen (20);Ausbilden eines integrierten Abstandshalters (220) um jeden Chip der mehreren ersten Chips (110), wobei der integrierte Abstandshalter (220) die Querschnittsform eines gedrehten „H“ aufweist und in Lücken (Wg) zwischen dem Laminatsubstrat (10) und einer äußeren Seitenwand jedes Chips der mehreren ersten Chips (110) angeordnet wird, wobei der integrierte Abstandshalter (220) den Chip innerhalb des Laminatsubstrats (10) hält, indem er sich teilweise über einen Teil einer Oberseite jedes Chips der mehreren ersten Chips (110) erstreckt; undAusbilden vorderseitiger Kontakte (125) über der Vorderseite (11) des Laminatsubstrats (10).

ELEKTRONISCHES BAUELEMENTGEHÄUSE

Die Technologie eines elektronischen Bauelementgehäuses ist offenbart. Ein elektronisches Bauelementgehäuse gemäß der vorliegenden Offenbarung kann ein Gehäusesubstrat, eine elektronische Komponente, eine Formmasse, die die elektronische Komponente einkapselt, und eine Redistributionsschicht umfassen, die derart angeordnet ist, dass die Formmasse zwischen dem Gehäusesubstrat und der Redistributionsschicht ist. Die Redistributionsschicht und das Gehäusesubstrat können elektrisch gekoppelt sein. Außerdem können die Redistributionsschicht und die elektronische Komponente elektrisch gekoppelt sein, um die elektronische Komponente und das Gehäusesubstrat elektrisch zu koppeln. Zugeordnete Systeme und Verfahren sind auch offenbart.

Bauelement mit einem Halbleiterchip und Verfahren zur Herstellung eines Moduls mit gestapelten Bauelementen

Bauelement (300), umfassend: einen Träger (30), ein auf dem Träger (30) abgeschiedenes erstes Material (31), wobei das erste Material (31) einen Elastizitätsmodul von unter 100 MPa aufweist, einen über dem ersten Material (31) platzierten Halbleiterchip (11), ein auf dem Träger (30) und dem Halbleiterchip (11) abgeschiedenes zweites Material (12), wobei das zweite Material (12) einen Elastizitätsmodul von unter 100 MPa aufweist, eine Metallschicht (10) umfassend eine erste Fläche (13) und eine der ersten Fläche (13) gegenüberliegende zweite Fläche (14), wobei die Metallschicht (10) über dem zweiten Material (12) platziert ist und ihre erste Fläche (13) dem zweiten Material (12) zugewandt ist, und mindestens ein Durchgangsloch (38, 39), das von der ersten Fläche (13) der Metallschicht (10) durch das zweite Material (12) und den Träger (30) verläuft.

Laminatpackung von Chip auf Träger und in Kavität

Eine Packung (100), umfassend einen Chipträger (102), hergestellt aus einem ersten Material, einen Körper (104), hergestellt aus einem zweiten Material, das sich vom ersten Material unterscheidet, und angeordnet auf dem Chipträger (102) zum Bilden einer Kavität (106), einen Halbleiterchip (108), mindestens teilweise in der Kavität (106) angeordnet, und ein Laminat (110), einkapselnd mindestens eines von mindestens einem Teil des Chipträgers (102), mindestens einem Teils des Körpers (104) und mindestens einem Teil des Halbleiterchips (108).

Integriertes Passivvorrichtungs-Package und Verfahren zum Ausbilden von diesem

Ein Vorrichtungs-Package umfasst einen ersten Die, einen zweiten Die und eine Moldmasse, die sich entlang von Seitenwänden des ersten Die und des zweiten Die erstreckt. Das Package umfasst ferner Umverteilungsschichten (RDLs), die sich seitlich über Kanten des ersten Die und des zweiten Die hinaus erstrecken. Die RDLs umfassen einen Eingabe-/Ausgabekontakt (I/O-Kontakt), der mit dem ersten Die und dem zweiten Die elektrisch verbunden ist, und der I/O-Kontakt ist an einer Seitenwand des Vorrichtungs-Package freigelegt, die im Wesentlichen senkrecht zu einer den RDLs entgegengesetzten Fläche der Moldmasse ist.

INTEGRIERTES SCHALTUNGSPACKAGE UND VERFAHREN

In einer Ausführungsform weist eine Struktur Folgendes auf: einen ersten integrierten Schaltungsdie, der erste Die-Anschlüsse aufweist; eine erste Dielektrikumsschicht auf den ersten Die-Anschlüssen; erste leitfähige Durchkontaktierungen, die sich durch die erste Dielektrikumsschicht hindurch erstrecken, wobei die ersten leitfähigen Durchkontaktierungen an eine erste Untergruppe der ersten Die-Anschlüsse angeschlossen sind; einen zweiten integrierten Schaltungsdie, der an eine zweite Untergruppe der ersten Die-Anschlüsse mit ersten aufschmelzbaren Anschlüssen gebondet ist; ein erstes Verkapselungsmaterial, das den zweiten integrierten Schaltungsdie und die ersten leitfähigen Durchkontaktierungen umgibt, wobei das erste Verkapselungsmaterial und der erste integrierte Schaltungsdie seitlich angrenzend sind; zweite leitfähige Durchkontaktierungen benachbart zu dem ersten integrierten Schaltungsdie; ein zweites Verkapselungsmaterial, das die zweiten leitfähigen Durchkontaktierungen, das erste ...

Multichip-Montageeinheit mit einem Substrat mit mehreren vertikal eingebetteten Plättchen und Verfahren zur Herstellung derselben

Eine Vorrichtung umfasst ein Substrat, welches eine Anschlussfleckseite mit mehreren Kontaktflecken und eine Plättchenseite gegenüber der Anschlussfleckseite aufweist. Die Vorrichtung umfasst ein erstes Plättchen und ein zweites Plättchen, wobei das erste Plättchen und das zweite Plättchen derart in das Substrat eingebettet sind, dass das zweite Plättchen zwischen dem ersten Plättchen und der Anschlussfleckseite des Substrats angeordnet ist.

Bondhügellose Aufbauschicht- und Laminatkernhybridstrukturen und Verfahren für ihre Montage

Eine Struktur enthält ein Hybridsubstrat zum Stützen eines Halbleiterbauelements, das eine bondhügellose Aufbauschicht, in die das Halbleiterbauelement eingebettet ist, und eine Laminatkernstruktur enthält. Die bondhügellose Aufbauschicht und die Laminatkernstruktur werden durch eine Verstärkungsplattierung, die mit einem plattierten Durchgangsloch in der Laminatkernstruktur und einer anschließenden Bondinsel der bondhügellosen Aufbauschichtstruktur verbunden ist, zu einer integralen Vorrichtung gemacht.

MIKROELEKTRONISCHE ANORDNUNGEN

Mikroelektronische Anordnungen und damit verbundene Vorrichtungen und Verfahren werden hierin offenbart. Beispielsweise kann bei einigen Ausführungsbeispielen eine mikroelektronische Anordnung einen ersten Die umfassen, der eine erste Fläche und eine zweite Fläche aufweist; und einen zweiten Die, der zweite Die umfassend eine erste Fläche und eine zweite Fläche, wobei der zweite Die ferner eine Mehrzahl von ersten leitfähigen Kontakten an der ersten Fläche und eine Mehrzahl von zweiten leitfähigen Kontakten an der zweiten Fläche umfasst und der zweite Die zwischen Erste-Ebene-Verbindungskontakten der mikroelektronischen Anordnung und dem ersten Die ist.

VERFAHREN UND APPARAT ZUM PACKEN INTEGRIERTER SCHALTUNGSCHIPS MIT EINER POLYMERFILM-BEDECKUNGSSCHICHT.

Mehrchip-Halbleitermodul und Herstellungsverfahren dafür

Ein Mehrchip-Halbleitermodul weist auf: ein Chipmontageteil mit einem ersten und zweiten Substrat, wobei das erste Substrat hat: eine entgegengesetzte erste und zweite Oberfläche, mehrere erste leitende Kontaktlöcher, die sich durch die erste und zweite Oberfläche erstrecken, und eine erste Schaltungsanordnung, die auf der zweiten Oberfläche strukturiert und mit den ersten leitenden Kontaktlöchern elektrisch verbunden ist, wobei das zweite Substrat hat: eine entgegengesetzte erste und zweite Oberfläche, mehrere zweite leitende Kontaktlöcher, die sich durch die erste und zweite Oberfläche des zweiten Substrats erstrecken, eine zweite Schaltungsanordnung, die auf der zweiten Oberfläche des zweiten Substrats strukturiert und mit den zweiten leitenden Kontaktlöchern elektrisch verbunden ist, und eine darin ausgebildete erste Chipaufnahmeöffnung, wobei die erste Oberfläche des zweiten Substrats auf der zweiten Oberfläche des ersten Substrats verbunden ist, so daß die zweite Schaltungsanordnung ...

Verpackungsstruktur für elektronische Bauteile und Methode zu deren Herstellung

INFO-POP-STRUK'I'UREN MIT HOHLRÄUME AUFWEISENDEN TIVS

Ein Verfahren beinhaltet ein Aufdosieren einer Opferregion über einem Träger und Bilden eines Metallstabs über dem Träger. Der Metallstab überlappt zumindest einen Abschnitt der Opferregion. Das Verfahren beinhaltet ferner ein Einkapseln des Metallstabs und der Opferregion in einem Einkapselungsmaterial, Abnehmen des Metallstabs, der Opferregion und des Einkapselungsmaterials vom Träger und Entfernen zumindest eines Abschnitts der Opferregion, um eine sich von einem Niveau einer Fläche des Einkapselungsmaterials aus in das Einkapselungsmaterial hinein erstreckende Vertiefung zu bilden.

Chipmodul und Verfahren zur Bereitstellung eines Chipmoduls

Chipmodul (20), das einen Halbleiter-Die (2) umfasst, der in ein Leiterplattensubstrat (PCB-Substrat) (10) eingebettet ist, wobei der Die (2) eine Rückseite (16) und eine aktive Vorderseite, die mehrere Kontaktflächen (4) umfasst, aufweist, wobei die Rückseite (16) des Dies (2) durch eine Wärmebrücke (24, 38) mit einer Oberfläche (29) des Chipmoduls (20) gekoppelt ist, wobei wenigstens ein Abschnitt der Rückseite des Dies (2) mit einer gut wärmeleitenden und strukturierten Beschichtung (18) beschichtet ist und ein Innenendabschnitt der Wärmebrücke (24, 38) an die Beschichtung (18) angrenzt.

Gehäuse eines integrierten Schaltkreises und Verfahren zum Bilden desselben

Eine Ausführungsform einer Gehäuse-auf-Gehäuse(PoP)-Vorrichtung umfasst eine Gehäusestruktur, einen Gehäuseträger und eine Vielzahl von Anschlüssen, die die Gehäusestruktur mit dem Gehäuseträger verbinden. Die Gehäusestruktur umfasst einen Logikchip, der mit einem Speicherchip verbunden ist, eine Formmasse, die den Speicherchip umschließt und eine Vielzahl leitfähiger Stifte, die sich durch die Formmasse hindurch erstrecken. Die Vielzahl der leitfähigen Stifte ist an Kontaktpolstern auf dem Logikchip befestigt.

Chipmodul, Isoliermaterial und Verfahren zur Herstellung eines Chipmoduls

Das Chipmodul umfasst einen Träger, einen Halbleiterchip, der auf dem Träger angeordnet oder in den Träger eingebettet ist, und eine Isolierschicht, die mindestens teilweise eine Fläche des Trägers bedeckt, wobei die dielektrische Konstante r und die Wärmeleitfähigkeit der Isolierschicht die Bedingung ·r < 4,0 W·m1·K1 erfüllen.

Elektronisches Bauelement, Anordnung und Verfahren

Elektronisches Bauelement (150, 200, 250, 260, 300), umfassend:mindestens ein Halbleiterbauelement (151, 201, 261, 301) mit einer ersten Seite, einer der ersten Seite gegenüberliegenden zweiten Seite), einer auf der ersten Seite angeordneten ersten Elektrode (162) und einer auf der zweiten Seite angeordneten zweiten Elektrode (164); undeine Verteilerplatine (152, 202, 263, 304), die mindestens zwei nicht leitende Schichten (153, 154, 155, 156) und eine leitende Verteilerstruktur (157) umfasst,wobei das Halbleiterbauelement (151) in die Verteilerplatine (152, 202, 263, 304) eingebettet und mit der Verteilerstruktur (157) elektrisch verbunden ist, wobei die Verteilerplatine (152, 202, 263, 304) zumindest eine an einer Seitenfläche (167) ausgebildete Stufe aufweist, wobei von der ersten Elektrode (162) und der zweiten Elektrode (164) eine jede an einer Stufe elektrisch kontaktierbar ist; und wobei auf einer Stufe eine äußere Kontaktfläche (179) der Verteilerstruktur (157) angeordnet ist.

DIE-GEHÄUSE UND VERFAHREN ZUM BILDEN EINES DIE-GEHÄUSES

Ein Die-Gehäuse ist bereitgestellt. Das Die-Gehäuse kann Folgendes beinhalten: einen Die mit einem ersten Die-Kontakt auf einer ersten Seite des Die und einem zweiten Die-Kontakt auf einer zweiten Seite des Die, die der ersten Seite des Die gegenüberliegt, ein Isolationsmaterial, das lateral dem Die benachbart ist, eine Metallstruktur, die die gesamte Oberfläche des zweiten Die-Kontakts des Die im Wesentlichen direkt kontaktiert, wobei die Metallstruktur aus dem gleichen Material wie der zweite Die-Kontakt gefertigt ist, einen ersten Padkontakt auf der ersten Seite des Die, der den ersten Die-Kontakt elektrisch kontaktiert, und einen zweiten Padkontakt auf der ersten Seite des Die, der den zweiten Die-Kontakt über die Metallstruktur elektrisch kontaktiert, wobei das Isolationsmaterial die Metallstruktur elektrisch von dem ersten Die-Kontakt isoliert.

Hochfrequenz-Halbleitervorrichtung

Semiconductor package for e.g. integrated circuit card in e.g. mobile phone, has external contact terminal provided within through-hole, which electrically connects conductive pattern to semiconductor chip

The semiconductor package (20) has a conductive pattern (24) provided on the substrate (23) and extended over the through-hole (23a). A semiconductor chip (22) is arranged within the through-hole. An external contact terminal (21) provided within the through-hole, electrically connects the conductive pattern to the semiconductor chip. Independent claims are included for the following: (1) semiconductor package formation method; and (2) electronic system formation method.

Reconstituted device including die and functional material

Dies from a wafer are reassembled with passive components and encapsulated to form a reconstituted electronic device 10 comprising a die 11, a passive, functioning component 13 and a metallic redistribution layer 15 which defines an electronic component in an area at least partially above the functioning material. The electronic component may be a metal-oxide-metal capacitor, an inductor or an antenna. The functioning material may be ceramic or it may be a ferrite. The functioning material may surround the die. In one embodiment the functioning material is a ceramic body with a metallic coating 110 (figure 10) on a face opposite that of the surface of the substrate on which the die and functioning material are embedded, a metallic via 102 (figure 9) is included through the ceramic body to contact the metal coating, the redistribution layer/ceramic body/metal coating structure forms a capacitor. In another embodiment the functioning material may be a metal carrier 120 (figure 11) with an ...

A method of manufacturing diodes with ceramic base and dice structure

Transferring logging data from an offset well location to a target well location

Systems and methods for transferring logging data from an offset well location to a target well location by adjusting the logging data to account for the difference in correlated depths between the target well and the offset well where logging data is acquired.

Transferring logging data from an offset well location to a target well location

Transferring logging data from an offset well location to a target well location

PROCEDURE FOR THE PRODUCTION OF COPLANAR CHIP HOUSINGS IN WAFER SIZE

HERSTELLUNG EINER EINE KOMPONENTE UMFASSENDEN SCHICHT

A method for manufacturing a circuit-board layer on a base surface (2), which base surface (2) includes conductor patterns (19). The circuit-board layer being manufactured comprises a conductor-pattern layer (14), an insulating layer (1), and at least one component (6) inside the insulating-material layer (1). According to the invention, the component (6) is attached to the conductor layer (4), the conductor layer (4) is aligned relative to the base surface (2) attached with the aid of an insulating material (1) to the base surface (2). An insulating-material layer (1) is thus formed between the conductor layer (4) and the base surface (2), on which the said at least one component (6) is located. Electrical contacts are formed between the contact areas (7) of the component (6) and the conductor layer (4), in such a way that contact openings (17) are opened at the positions of the contact areas (7) of the component (6) and conductive material is made in the contact openings (17). The conductor ...

ARTS OF MANUFACTURING FOR ELECTRICAL MECHANISM

Verfahren zum Herstellen einer Leiterplatte sowie Leiterplatte

A method for producing a printed circuit board (10) with at least one embedded sensor chip (3), in which at least one sensor face (5) and connectors (4) are arranged on a face of the chip, comprising the following steps: a) providing an adhesive film (1), b) printing a conductor structure (2) made of a conductive paste onto a surface of the adhesive film, c) placing the at least one sensor chip (3) with the face having the at least one sensor face (5) and the connectors (4) onto the conductor structure (2) made of a conductive paste in a registered manner, d) curing the conductive paste, e) applying an insulation layer (6) with a conductor layer (7) lying thereabove onto the surface having the chip (3) of the structure created in the preceding steps, f) laminating the structure created in the preceding steps, g) structuring the conductor layer (7) and forming vias (9) from the conductor layer to the printed conductors (7b, 7c) of the conductor structure on the surface of the adhesive film ...

Method for manufacturing an electronic module

Die vorliegende Erfindung betrifft em elektronisches Modul mit zumindest emer Komponente, die in Isoliermaterial eingebettet ist. Das elektronische Modul umfasst ein erstes Isoliermaterial mit einer ersten Oberfläche und einer zweiten Oberfläche und einer Dicke zwischen der ersten Oberfläche und der zweiten Oberfläche, zumindest eine Öffnung durch das erste Isoliermaterial, ein zweites Isoliermaterial auf der zweiten Oberfläche des ersten Isoliermaterials, zumindest eine Komponente, die in das zweite Isoliermaterial eingebettet ist, zumindest eine leitende Struktur in der zumindest einen Öffnung, wobei die zumindest eine leitende Struktur eine erste Oberfläche und eine zweite Oberfläche hat, wobei die zweite Oberfläche dem zweiten Isoliermaterial zugewandt ist und die erste Oberfläche vom zweiten Isoliermaterial abgewandt ist und eine Distanz zwischen der ersten Oberfläche des ersten Isoliermaterials und der zweiten Oberfläche der zumindest einen leitenden Struktur geringer oder größer ...

Verfahren zum Ankontaktieren und Umverdrahten

The invention relates to a method for contacting and rewiring an electronic component (1) embedded into a printed circuit board (2), characterized by the following steps: applying a first permanent resist layer (9) onto a contact side (8) of the printed circuit board (2), structuring the first permanent resist layer (11) in order to produce recesses (10, 12) in the region of contacts (7) of the electronic component (1), applying a second permanent resist layer (11) onto the structured first permanent resist layer (9), structuring the second permanent resist layer (11) in order to expose the recesses (10) in the region of the contacts (7) and in order to produce recesses (12) corresponding to the desired conductor tracks (15), chemically coating the recesses (10, 12) with copper, galvanically filling the recesses (10, 12) with copper, and removing the excess copper in the regions between the recesses (10, 12).

PROCEDURE FOR THE ESTABLISHMENT OF AN ELECTRONIC CONSTRUCTION UNIT ON A PRINTED CIRCUIT BOARD, PRODUCTION PROCEDURE OF A TRÄGERLAGE AND A SPAN, AS WELL AS SYSTEM CONSISTING OF A PRINTED CIRCUIT BOARD AND AT LEAST AN ELECTRONIC CONSTRUCTION UNIT

Verfahren zur Herstellung einer Leiterplatte mit zumindest einer optoelektronischen Komponente

The invention relates to a method for producing a circuit board having at least one optoelectronic component, which method is characterized by the following steps: a) applying a transparent curable adhesive layer (1) to a carrier layer (2), b) placing at least one optoelectronic component (3) onto the adhesive layer (1) by means of an optically relevant side (4) of the component, c) curing the adhesive layer (1) into a window element (1'), d) embedding the component (3) in a circuit-board composite, e) structuring the carrier layer (2) in order to at least partially expose the window element (1') and to contact the component (3).

VERFAHREN ZUR INTEGRATION WENIGSTENS EINES ELEKTRONISCHEN BAUTEILS IN EINE LEITERPLATTE SOWIE LEITERPLATTE

PROCEDURE FOR EMBEDDING A COMPONENT INTO A BASIS AND FOR THE FORMATION OF A CONTACT

Dispensing process for fabrication of microelectronic packages

METHOD FOR CONTACT BONDING ELECTRONIC COMPONENTS ON AN INSULATING SUBSTRATE AND COMPONENT MODULE PRODUCED ACCORDING TO SAID METHOD

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

LSi package and internal connecting method used therefor

THREE-DIMENSIONAL MULTICHIP MODULE SYSTEMS AND METHODS OF FABRICATION

MULTICHIP INTEGRATED CIRCUIT MODULE AND METHOD OF FABRICATION

ELECTRONIC CIRCUIT COMPRISING CONDUCTIVE BRIDGES AND METHOD FOR MAKING SUCH BRIDGES

The aim of this invention is to obtain a very cheap electronic circuit used for example in a card or a label while maintaining high reliability. It particularly concerns the connection of one or several electronic components on the conductive tracks by means of conductive bridges that traverse the substrate. The electronic circuit according to the invention includes at least one electronic component (6), a substrate (5), on a first face of this substrate an adhesive layer and a conductive layer including a plurality of tracks (4) are applied. The electronic component (6) comprises at least two connection areas (7). One of these connection areas (7) is electrically linked to the conductive layer by a conductive bridge formed by a conductive segment (1) delimited in the conductive layer only. Said segment (1), free from any adhesive substance, traverses the substrate (5) through a passage (2, 3) and links the connection area (7).

MULTIPLE SEMICONDUCTOR CHIP ASSEMBLY AND MANUFACTURE

APPARATUS INCORPORATING SMALL-FEATURE-SIZE AND LARGE-FEATURE-SIZE COMPONENTS AND METHOD FOR MAKING SAME

The present invention relates to the field of fabricating elements on a substrate. In one embodiment, the invention is an apparatus. The apparatus includes a strap having embedded therein an integrated circuit, the integrated circuit having a conductive pad. The apparatus also includes a conductive medium attached to the conductive pad of the integrated circuit. In an alternate embodiment, the invention is a method. The method includes attaching a conductive medium to a strap having embedded therein an integrated circuit such that the conductive medium is connected electrically to the integrated circuit. The method also includes attaching a large-scale component to the conductive medium such that the large-scale component is electrically connected to the conductive medium. The apparatus can also include a thin-film dielectric layer formed over a portion of the integrated circuit and a portion of the substrate.

METHOD FOR FIXING AN ELECTRONIC COMPONENT ON A PRINTED CIRCUIT BOARD AND SYSTEM COMPRISING A PRINTED CIRCUIT BOARD AND AT LEAST ONE ELECTRONIC COMPONENT

In a method for fixing an electronic component (3) on a printed circuit board (2), and contact-connecting the electronic component (3) to the printed circuit board (2), the following steps are provided: - providing the printed circuit board (2) having a plurality of contact and connection pads (8), - providing the electronic component (3) having a number of contact and connection locations (5) corresponding to the plurality of contact and connection pads (8) of the printed circuit board (2), with a mutual spacing reduced in comparison with the spacing of the contact and connection pads (8) of the printed circuit board (2), and ~ arranging or forming at least one interlayer (4) for routing the contact and connection locations (5) of the electronic component (3) between the contact and connection pads (8) of the printed circuit board (2) and the contact and connection locations (5) of the electronic component (3). A method for producing an interlayer (4) for routing and a system having a ...

THREE-DIMENSIONAL MULTICHIP MODULE SYSTEMS AND METHODS OF FABRICATION

... 2106873 9217903 PCTABS00016 Multichip integrated circuit packages and methods of fabrication, along with systems for stacking such packages, are disclosed. In one embodiment, the multichip package has an array of contact pads on an upper surface thereof and an array of contact pads on a lower surface thereof. Connection means are provided for electrically coupling at least some of the contact pads on each package surface with selected ones of the contact pads on the other surface, or selected interconnection metallization which is disposed between integrated circuits located within the package. The contact pads of each surface array are preferably equal in number and vertically aligned such that multiple multichip packages may be readily stacked, with a conductive means disposed therebetween for electrically coupling the contact pads of one package to the pads of another package. In addition, various internal and external heat sink structures are provided which facilitate dissipation of ...

MAGNETIC AND ELECTROMAGNETIC CIRCUIT COMPONENTS HAVING EMBEDDED MAGNETIC MATERIAL IN A HIGH DENSITY INTERCONNECT STRUCTURE

MAGNETIC AND ELECTROMAGNETIC CIRCUIT COMPONENTS HAVING EMBEDDED MAGNETIC MATERIAL IN A HIGH DENSITY INTERCONNECT A magnetic or electromagnetic circuit component includes an embedded magnetic material (e.g., ferromagnetic) in an HDI structure with alternating dielectric and metal or winding layers. In one embodiment, the ferromagnetic material is situated in a substrate well, or cavity, with or without an adhesive. Alternatively, the ferromagnetic material is co-fired with the ceramic substrate and then machined to achieve a required core shape. An electroplating process is employed to construct the metal layer , such process including differential plating for varying the thickness of metal layers and/or other portions of the circuit. Laser ablation or any other suitable technique is employed to make through-holes for insertion of the posts of a ferromagnetic core plate used to complete a magnetic circuit, if required. Advantageously, a magnetic or electromagnetic component may have a height ...

Halbleitervorrichtung

SINGLE-CHIP MODULE INTEGRATED CIRCUITS

Chip Carriers And Semiconductor Devices Including Redistribution Structures With Improved Thermal And Electrical Performance

The antenna module

Semiconductor component and method for manufacturing a semiconductor component

Electronic device and method of manufacturing the same

The invention relates to en electronic device which includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of the second interconnect layer is smaller in area than the opposite end face. The via plug is exposed on the surface of the first interconnect layer facing the second interconnect layer. An insulating resin forming the first interconnect layer is higher in thermal decomposition temperature than an insulating resin forming the second interconnect layer.

Wafer level system packaging method and packaging structure

Integrated circuit device

System and method for embedded chip package with chips stacked in an interconnecting laminate

Semiconductor package

Electronic part module and method of making the same

Manufacturing process for circuit substrate

The invention provides a manufacturing process for a circuit substrate, comprising the following steps of: forming at least a layer of conductive wiring on a support plate; mounting a function element on the conductive wiring; containing the function element by sealing an outer circumference of the function element with a resin layer; forming a through hole at an electrode terminal portion of the function element; forming at least one of wiring layer on the function element; removing the support plate.

Integrated fan-out package and method of fabricating the same

Integrated fan-out package

Surface mount electronic component

A surface-mounted electronic component including balls bonded to its front surface and, on the front surface, a protective resin layer having a thickness smaller than the ball height, wherein grooves extend in the resin layer between balls of the chip.

Semiconductor device

The invention discloses a device which comprises a first semiconductor chip; a moulding compounds layer, embedded with the first semiconductor chip; a first electrical conductive layer, applied to moulding compounds layer, a through-hole, disposed at moulding compounds layer; and solder material, for filling through-hole.

Semiconductor package comprising the aerial and its manufacturing method

Packaging structure and manufacturing method thereof

... 本发明公开种封装结构及其制造方法，该封装结构具有至少部分的第导电元件配置在第基板的贯穿开口(through‑opening)中。导电结构配置在第基板和第导电元件上方，其中该导电结构电性连接至该第基板和该第导电元件的该至少第输入/输出端。导电结构包含第二导电元件、第二基板或导电图案其中至少个。 ...

Semiconductor package and manufacturing method thereof

Manufacturing method of semiconductor device and semiconductor device

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacture method therefor

METHOD OF ASSEMBLING A CHIP IN A FLEXIBLE SUBSTRATE.

METHOD FOR INTEGRATING POWER CHIPS AND POWER ELECTRONIC MODULES

ELECTRONICS COMPONENT HAS ASSEMBLY ON THE SURFACE

L'invention concerne un composant électronique (51) à montage en surface comprenant des billes (29) fixées à sa face avant et, sur la face avant, une couche de résine de protection (43) d'épaisseur inférieure à la hauteur des billes, dans lequel des rainures (53) s'étendent dans la couche de résine (43) entre des billes de la puce.

STRUCTURE Of INTERCONNECTION HAS SURGES PRESENTING ONE OR MORE INCREASE OF CONTACT ON the WALLS OF SURGES AND METHOD FOR REALIZATION

MODULATE CIRCUITS JUST AND MANUFACTORING PROCESS CORRESPONDING

Un module de circuits intégrés comprend des plages de contact thermique (12) sensiblement dans le même plan de surface que les plots de connexion (6, 7) sur les face actives des composants, une plage de contact thermique correspondant à un élément conducteur d'un composant (1), raccordé au plan de masse de celui-ci et situé au plus près d'un point chaud, et des éléments de conduction thermique (12) traversant une structure d'interconnexion de type câblage collectif (9), en regard desdites plages de contact thermique (12), permettant de relier ces plages à un dispositif de dissipation thermique (Dth). Les plages de contact thermique peuvent être réalisées dans le processus de fabrication des composants, ou collectivement, dans le procédé de fabrication du module. De préférence, les plages de contact thermique sont formées sur des ponts à air de transistor de puissance.

MANUFACTORING PROCESS OF THE SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE INCLUDING/UNDERSTANDING A CHIP HAVE CROSSING VIAS

Procédé de fabrication d'un dispositif semi-conducteur et dispositif semi-conducteur, dans lesquels : une première plaquette (32) comprend au moins une première puce de circuits intégrés (2) et une couche de support (7) entourant cette première puce et dont une face avant comprend une face avant de la première couche de support et la face active de la première puce ; une première couche de connexion électrique (33) est placée sur la face avant de la première plaquette et comprend un premier réseau de connexion électrique (12) ; une seconde plaquette (34) est placée sur une face avant de la première couche de connexion électrique et comprend au moins une seconde puce de circuits intégrés (14a) et une couche de support (21a) entourant cette seconde puce, la seconde puce présentant une face active du côté de la première couche de connexion électrique et présentant des passages traversants (24) remplis d'une matière conductrice constituant des vias de connexion électrique (25) ; et une seconde ...

Improved microelectronic component electrical contact pad connection having microelectronic component directly attached printed circuit face with thin isolated attachment and through

L'invention concerne la connexion électrique des plots de contact (7) d'au moins un composant microélectronique (5) directement à des pistes conductrices (11) d'une plaque à circuits imprimés, ce composant ayant des plots métalliques affleurant une face principale; on solidarise le composant (5), par sa face portant les plots (7), à un substrat mince (1) électriquement isolant; on fore des trous (8) à travers le substrat respectivement en regard des plots de manière que ces trous débouchent en affleurement sur les plots (7); et on métallise (12) les trous (8) de manière à établir des liaisons électriques entre les plots formant le fond des trous et des pistes de circuits imprimés (11), dans lesquelles débouchent les trous métallisés, situées sur la face externe du substrat isolant (1).

Multichip module production involves covering a substrate and mounted components with resin and removing substrate to expose resin surface and surfaces of components with revealed mounting lands

TRANSMISSION DEVICE RF INTEGRATED ELECTROMAGNETIC WAVE REFLECTOR

Dispositif de transmission RF (100) comprenant au moins : - un substrat (102) comportant des première et deuxième faces (104, 106) opposées l'une de l'autre ; - un premier circuit électronique de transmission RF (108) disposé sur et/ou dans le substrat ; - une première antenne (112a) disposée du côté de la première face du substrat, espacée de la première face du substrat et reliée électriquement au premier circuit électronique de transmission RF ; - un premier réflecteur d'ondes électromagnétiques couplé à la première antenne et comprenant : - une première surface à haute impédance (114a) comportant au moins plusieurs premiers éléments électriquement conducteurs (118) formant une première structure périodique et disposés sur la première face du substrat en regard de la première antenne ; - un premier plan de masse électriquement conducteur (116a) disposé au moins partiellement en regard de la première antenne.

MODULATE CIRCUITS JUST AND MANUFACTORING PROCESS CORRESPONDING

MODULATE CIRCUITS JUST AND MANUFACTORING PROCESS CORRESPONDING

MODULATE CIRCUITS JUST AND MANUFACTORING PROCESS CORRESPONDING

반도체 디바이스 및 제조 방법

... 반도체 디바이스 및 제조 방법이 제공된다. 리플로우 가능 물질이 관통 비아와 전기 접속하고, 관통 비아는 봉지재를 통해 연장된다. 보호층이 리플로우 가능 물질 위에 형성된다. 실시예에서, 개구부는 리플로우 가능 물질을 노출하기 위해 보호층 내에 형성된다. 다른 실시예에서, 보호층은 리플로우 가능 물질이 보호층으로부터 멀리 연장되도록 형성된다.

ELECTRONIC DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC INSTRUMENT

ELECTRONIC COMPONENT EMBEDDED SUBSTRATE AND METHOD OF MANUFACTURING ELECTRONIC COMPONENT EMBEDDED SUBSTRATE

팬-아웃 반도체 패키지

... 적어도 하나의 관통홀이 형성되며 내부면에 금속층이 배치되는 코어부재와, 상기 관통홀에 배치되는 반도체 칩과, 상기 코어부재와 상기 반도체 칩을 봉합하는 봉합재와, 상기 봉합재의 상면에 배치되는 금속 플레이트 및 상기 봉합재를 관통하여 상기 금속층과 상기 금속 플레이트를 연결하는 벽체를 포함하며, 상기 벽체에는 적어도 하나 이상의 개구부가 형성되는 팬-아웃 반도체 패키지가 개시된다.

칩 패키지

... 패시베이션 층에 다이 접촉 패드들을 가지는 다이를 포함하는 내장형 다이 패키지로서, 상기 다이 접촉 패드는 접착 층에 의해 피처 층의 제1 측면에 결합되고, 필러(pillar)의 층은 상기 피처 층의 제2 측면으로부터 뻗어있고, 상기 다이, 피처층, 및 필러 층은 유전체 재료에 의해 캡슐화되는 상기 내장형 다이 패키지.

POWER SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package having a buried conductive post in sealing resin and manufacturing method thereof

반도체 패키지 및 그 형성 방법

... 본 발명의 실시예들은 반도체 패키지 및 그 형성 방법을 포함한다. 일실시예는, 제1 다이, 제1 전기 연결부, 및 제1 다이와 제1 전기 연결부에 연결된 제1 재배선층을 포함하는 제1 다이 패키지를 형성하는 단계, 제1 다이 패키지 위에 언더필을 형성하는 단계, 제1 전기 연결부의 일부분을 노출시키기 위해 개구부를 갖도록 언더필을 패터닝하는 단계, 상기 언더필의 개구부 내에서 제1 전기 연결부에 연결된 접합 구조체에 의해 제1 다이 패키지에 제2 다이 패키지를 접합하는 단계를 포함하는 방법이다.

DUAL MOLDED MULTI-CHIP PACKAGE SYSTEM

소자 내장형 연성회로기판 및 이의 제조방법

... 제1도전층과, 상기 제1도전층의 상측에 배치되며 복수의 범프홈 및 제1회로패턴에 대응되는 형상으로 제1홈이 형성된 제1절연층과, 상기 제1절연층의 상기 제1홈 내에 형성되어, 상기 제1회로패턴으로 형성된 제1도금층 및 상기 범프홈에 삽입되어 상기 제1도전층과 연결되는 복수의 범프를 구비하는 반도체 소자를 구비하며, 상기 제1도전층에는 제2회로패턴이 형성된 소자 내장형 연성회로기판과 이의 제조방법이 제공된다.

SEMICONDUCTOR PACKAGE

SEMICONDUCTOR DEVICE, STACKED SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE AND MOUNTING STRUCTURE THEREOF, AND MANUFACTURING METHOD THEREOF

디바이스 다이의 링 구조물

... 다이는 금속 패드, 금속 패드 위에 패시베이션 층 및 패시베이션 층 위에 폴리머 층을 포함한다. 금속 필라가 전기적으로 금속 패드에 위에서 연결된다. 금속 링은 상기 금속 필라와 동일 평면 상에 있다. 상기 폴리머 층은 금속 필라 및 금속 링과 동일 평면 상의 부분을 포함한다.

Substrate of Semiconductor Package, Semiconductor Package including the same and Stack Package using the same

Power semiconductor module and fabrication method

A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

Package structure

Disclosed is a package structure including a semiconductor chip disposed in a core board having a first surface and an opposite second surface. The package structure further includes a plurality of first and second electrode pads disposed on an active surface and an opposite inactive surface of the semiconductor chip respectively, the semiconductor chip having a plurality of through-silicon vias for electrically connecting the first and second electrode pads. As a result, the semiconductor chip is electrically connected to the two sides of the package structure via the through-silicon vias instead of conductive through holes, so as to enhance electrical quality and prevent the inactive surface of the semiconductor chip from occupying wiring layout space of the second surface of the core board to thereby increase wiring layout density and enhance electrical performance.

Stack package and method for manufacturing the same

A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

Semiconductor device comprising a passive component of capacitors and process for fabrication

A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.

Gain Enhanced LTCC System-on-Package for UMRR Applications

An apparatus, system, and method for Gain Enhanced LTCC System-on-Package radar sensor. The sensor includes a substrate and an integrated circuit coupled to the substrate, where the integrated circuit is configured to transmit and receive radio frequency (RF) signals. An antenna may be coupled to the integrated circuit and a lens may be coupled to the antenna. The lens may be configured to enhance the gain of the sensor.

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

Wiring board and method for manufacturing the same

A wiring board including a core substrate having an accommodation portion, an electronic component in the accommodation portion having a substrate, a resin layer on a surface of the substrate and an electrode on the resin layer, a first interlayer resin insulation layer on a surface of the core substrate and a surface of the substrate of the component, and a second interlayer resin insulation layer on the opposite surface of the core substrate and a surface of the substrate having the resin layer and electrode. The first insulation layer has resin in the amount greater than the amount of resin in the second insulation layer such that the total amount of resin component including the resin in the first insulation layer is adjusted to be substantially the same as the total amount of resin component including the resin in the second insulation layer and resin in the resin layer.

Package with embedded chip and method of fabricating the same

A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.

Electric part package and manufacturing method thereof

A disclosed electric part package includes a supporting member that includes a first area in which an electric part is arranged, and a second area in which a first opening is positioned, the second area being isolated from the first area; a resin part provided on the supporting member thereby to cover the electric part arranged in the first area, the resin part including an electric terminal exposed in the first opening of the supporting member; and a wiring structure provided on the resin part, the wiring structure being electrically connected to the electric part and the electric terminal of the resin part.

Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

Flexible circuit board and manufacturing method thereof

The present invention provides a high-performance flexible circuit board having excellent flexibility, a fine wiring pattern, and fine electric contacts, and a manufacturing method thereof. In a flexible circuit board ( 20 ), a second insulating layer ( 24 ) made of an inorganic material is positioned between a wiring layer ( 25 ) and a first insulating layer ( 23 ) made of an inorganic material.

Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer

A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

Hybrid bonding interface for 3-dimensional chip integration

Each of a first substrate and a second substrate includes a surface having a diffusion resistant dielectric material such as silicon nitride. Recessed regions are formed in the diffusion resistant dielectric material and filled with a bondable dielectric material. The patterns of the metal pads and bondable dielectric material portions in the first and second substrates can have a mirror symmetry. The first and second substrates are brought into physical contact and bonded employing contacts between metal pads and contacts between the bondable dielectric material portions. Through-substrate-via (TSV) structures are formed through bonded dielectric material portions. The interface between each pair of bonded dielectric material portions located around a TSV structure is encapsulated by two diffusion resistant dielectric material layers so that diffusion of metal at a bonding interface is contained within each pair of bonded dielectric material portions.

Reprogrammable circuit board with alignment-insensitive support for multiple component contact types

The present invention is directed to a system that programmably interconnects integrated circuit chips and other components at near-intra-chip density. The system's contact structure allows it to adapt to components with a wide variety of contact spacings and interconnection requirements, the use of releasable attachment means allows component placement to be modified as needed, the system identifies the contacts and the components to facilitate specifying the inter-component connections, and the system provides signal conditioning and retiming to minimize issues with signal integrity and signal skew.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Magnetic integration double-ended converter

The present invention relates to a method of bonding a chip to an external electric circuit. The conductors of the external electric circuit for connection to the chip are formed with physical extensions and the chip is directly bonded to these extensions. The invention also relates to an electric device comprising at least one chip and an external electric circuit. The chip is directly bonded to physical extensions of conductors of the external electric circuit.

Enhanced Modularity in Heterogeneous 3D Stacks

A computer program product for generating and implementing a three-dimensional (3D) computer processing chip stack plan. The computer readable program code includes computer readable program code configured for receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to at least one layer in the 3D computer processing chip stack plan. The computer readable program code is also configured for identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The computer readable program code is further configured for determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment forms the 3D computer processing chip stack.

Three-dimensional system-in-a-package

A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having a minimum thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements.

Chip-packaging module for a chip and a method for forming a chip-packaging module

A chip-packaging module for a chip is provided, the chip-packaging module including an isolation material configured to cover a chip on at least one side, the isolation material having a first surface proximate to a first side of a chip, and said isolation material having a second surface facing an opposite direction to the first surface; and at least one layer in connection with the chip first side, the at least one layer further configured to extend from the chip first side to the second surface of the isolation material.

Component built-in module, and manufacturing method for component built-in module

A manufacturing method for a component built-in module, including: forming, in a sheet member including resin, a via hole filled up with a conductive paste, a cavity in which an electronic component is to be built, and an adjustment space; and performing a heat press allowing the sheet member to abut against a substrate on which the electronic component has been mounted, wherein the adjustment space is formed so that a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the electronic component, is cancelled by a flow vector of the resin in a neighborhood of the via hole during the heat press, which is directed toward the adjustment space.

Stacked wafer level package having a reduced size

A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.

3D Integrated Microelectronic Assembly With Stress Reducing Interconnects And Method Of Making Same

A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handier with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.

Semiconductor package, electrical and electronic apparatus including the semiconductor package, and method of manufacturing the semiconductor package

In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.

Layered chip package and method of manufacturing same

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

Low profile package and method

In a method aspect, a multiplicity of ICs are attached to routing on a structurally supportive carrier (such as a wafer). The dice are encapsulated and then both the dice and the encapsulant layer are thinned with the carrier in place. A second routing layer is formed over the first encapsulant layer and conductive vias are provided to electrically couple the first and second routing layers as desired. External I/O contacts (e.g. solder bumps) are provided to facilitate electrical connection of the second routing layer (or a subsequent routing layer in stacked packages) to external devices. A contact encapsulant layer is then formed over the first encapsulant layer and the second routing layer in a manner that embeds the external I/O contacts at least partially therein. After the contact encapsulant layer has been formed, the carrier itself may be thinned significantly and singulated to provide a number of very low profile packages. The described approach can also be used to form stacked multi-chip packages.

Semiconductor element-embedded substrate, and method of manufacturing the substrate

A semiconductor element-embedded substrate includes a semiconductor element; a chip component; a peripheral insulating layer covering at least the outer circumferential side surfaces thereof; an upper surface-side wiring line provided on the upper surface side of the substrate; and a lower surface-side wiring line provided on the lower surface side of the substrate. The built-in semiconductor element includes a terminal on the upper surface side thereof, and this terminal is electrically connected to the upper surface-side wiring line. The built-in chip component includes an upper surface-side terminal electrically connected to the upper surface-side wiring line; a lower surface-side terminal electrically connected to the lower surface-side wiring line; and a through-chip via penetrating through the chip component to connect the upper surface-side terminal and the lower surface-side terminal.

Thermal enhanced package

A method of manufacturing an integrated circuit package. The method includes attaching a first surface of a semiconductor die to a thermally and/or electrically conductive substrate, forming a plurality of die connectors on a second surface of the semiconductor die, and encapsulating the semiconductor die and the plurality of die connectors in an encapsulant material. The method also includes removing a portion of the encapsulant material to expose one or more of the plurality of die connectors, thereby forming a routing surface. The method further includes forming a plurality of conductive traces on the routing surface. Each of the plurality of conductive traces is characterized by a first portion in electrical communication with one of the plurality of die connectors and a second portion in electrical communication with a package connector.

Circuit module

A circuit module includes a substrate that has a substantially rectangular parallelepiped shape and includes a plurality of inner conductive layers, an electronic component disposed on a first main surface of the substrate, an insulating layer disposed on the first main surface of the substrate so as to cover the electronic component, a shielding layer disposed on a surface of the insulating layer, and a ground electrode connected to the plurality of inner conductive layers. At least two of the inner conductive layers are directly connected to the shielding layer.

Three dimensional semiconductor assembly board with bump/flange supporting board, coreless build-up circuitry and built-in electronic device

A semiconductor assembly board includes a supporting board, a coreless build-up circuitry and a built-in electronic device. The supporting board includes a bump, a flange and a via hole in the bump. The built-in electronic device extends into the via hole and is electrically connected to the build-up circuitry. The build-up circuitry extends from the flange and the built-in electronic device and provides signal routing for the built-in electronic device. The supporting board provides mechanical support, ground/power plane and heat sink for the coreless build-up circuitry.

Semiconductor Chip Package and Method

A semiconductor chip package and a method to manufacture a semiconductor chip package are disclosed. An embodiment of the present invention comprises a substrate and a semiconductor chip disposed on the substrate and laterally surrounded by a packaging material. The package further comprises a current rail adjacent the semiconductor chip, the current rail isolated from the semiconductor chip by an isolation layer, a first external pad, and a via contact contacting the current rail with the first external pad.

Die package including encapsulated die and method of manufacturing the same

Disclosed herein is a die package including an encapsulated die, including: a die including pads on one side thereof; an encapsulation layer covering lateral sides of the die; a support layer covering the encapsulation layer and one side of the die; a passivation layer formed on the other side of the die such that the pads are exposed therethrough; and a redistribution layer formed on the passivation layer such that one part thereof is connected with the pad. Here, since one side of the die is supported by the support layer and the encapsulation layer is formed on only the lateral side of the die, the warpage of the die package due to the difference in thermal expansion coefficient can be minimized

Semiconductor Device and Method of Forming a Reconfigured Stackable Wafer Level Package with Vertical Interconnect

A semiconductor device has a carrier with a semiconductor die mounting area. A plurality of conductive posts is formed in a periphery of the semiconductor die mounting area and in the carrier. A first portion of the carrier is removed to expose a first portion of the plurality of conductive posts such that a second portion of the plurality of conductive posts is embedded in a second portion of the carrier. A first semiconductor die is mounted to the semiconductor die mounting area and between the first portion of the plurality of conductive posts. A first encapsulant is deposited around the first semiconductor die and around the first portion of the plurality of conductive posts. A second portion of the carrier is removed to expose the second portion of the plurality of conductive posts. An interconnect structure is formed over the plurality of conductive posts and the first semiconductor die.

Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

Methods of Packaging Semiconductor Devices and Structures Thereof

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Multi-piece substrate

A multi-piece substrate includes a frame portion, and a unit portion in which multiple wiring boards is arrayed. The frame portion is formed on the periphery of the unit portion, the wiring boards have semiconductor elements built in the wiring boards, respectively, and the frame portion has multiple slits formed such that the slits have openings on the periphery of the frame portion.

Embedded wafer level optical package structure and manufacturing method

A method of forming an embedded wafer level optical package includes attaching a sensor die, PCB bars and an LED on adhesive tape laminated on a carrier, attaching a dam between two light sensitive sensors of the sensor die, encapsulating the sensor die, the PCB bars, the LED, and the dam in an encapsulation layer, debonding the carrier, grinding a top surface of the encapsulation layer, forming vias through the encapsulation layer to the sensor die and the LED, filling the vias with conductive material, metalizing the top surface of the encapsulation layer, dielectric coating of the top surface of the encapsulation layer, dielectric coating of a bottom surface of the encapsulation layer, patterning the dielectric coating of the bottom surface of the encapsulation layer, and plating the patterned dielectric coating of the bottom surface of the encapsulation layer.

Packages with Passive Devices and Methods of Forming the Same

A device includes a substrate, a metal pad over the substrate, and a passivation layer having a portion over the metal pad. A Post-Passivation Interconnect (PPI) line is disposed over the passivation layer and electrically coupled to the metal pad. An Under-Bump Metallurgy (UBM) is disposed over and electrically coupled to the PPI line. A passive device includes a portion at a same level as the UBM. The portion of the passive device is formed of a same material as the UBM.

Semiconductor package

A semiconductor package includes a first semiconductor package, a second semiconductor package, and a package-connecting member. The first semiconductor package includes a first substrate, a chip stacking portion disposed on the first substrate and including a plurality of first semiconductor chips, and a first sealant for surrounding the chip stacking portion on the first substrate. The second semiconductor package includes a second substrate, at least one second semiconductor chip disposed on the second substrate, and a second sealant for surrounding the second semiconductor chip on the second substrate. The package-connecting member electrically connects the first semiconductor package and the second semiconductor package. The plurality of first semiconductor chips include a first chip including through silicon vias (TSVs) and a second chip electrically connected to the first chip via the TSVs, and the chip stacking portion includes an internal sealant for filling a space between the first chip and the second chip and extending to a side of the second chip.

Composite build-up materials for embedding of active components

Disclosed are composite build-up materials for the manufacture of printed circuit boards, IC substrates, chip packages and the like. The composite build-up materials are suitable for embedding active components such as micro chips. The composite build-up materials comprise a carrier layer ( 1 ), a resin layer with reinforcement ( 2 ), and a resin layer without reinforcement ( 3 ). The active component ( 6 ) is embedded into the resin layer without reinforcement ( 6 ).

System and Method for Fine Pitch PoP Structure

A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.

Workpiece with Semiconductor Chips, Semiconductor Device and Method for Producing a Workpiece with Semiconductor Chips

A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main surface. The workpiece also comprises an electrically conducting layer, arranged on the at least two semiconductor chips, the electrically conducting layer being arranged at least on regions of the second main surface, and a molding compound, arranged on the electrically conducting layer.

Semiconductor Packages and Methods of Forming The Same

In one embodiment, a method of fabricating a semiconductor package includes forming a first plurality of die openings on a laminate substrate. The laminate substrate has a front side and an opposite back side. A plurality of first dies is placed within the first plurality of die openings. An integrated spacer is formed around each die of the plurality of first dies. The integrated spacer is disposed in gaps between the laminate substrate and an outer sidewall of each die of the plurality of first dies. The integrated spacer holds the die within the laminate substrate by partially extending over a portion of a top surface of each die of the plurality of first dies. Front side contacts are formed over the front side of the laminate substrate.

Semiconductor Device and Method for Forming Semiconductor Package Having Build-Up Interconnect Structure Over Semiconductor Die with Different CTE Insulating Layers

A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.

Semiconductor Device and Method of Forming a Robust Fan-Out Package including Vertical Interconnects and Mechanical Support Layer

A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.

Semiconductor module

In the semiconductor module comprising a package substrate, a first semiconductor package, and a semiconductor bare chip, such problems as the occurrence of a wire short caused by warpage of the first semiconductor package and non-filling and the like at the time of resin sealing can be solved. A semiconductor module 10 , having: a semiconductor package 6 , which is obtained by mounting and resin-sealing a semiconductor bare chip on a first package substrate; a semiconductor bare chip 2 ; and a second package substrate 12 , the semiconductor module being characterized in that the semiconductor package 6 is mounted on the second package substrate 12 and the semiconductor bare chip 2 is mounted on the semiconductor package 6.

Semiconductor Method and Device of Forming a Fan-Out Device with PWB Vertical Interconnect Units

A semiconductor device has a modular interconnect unit or interconnect structure disposed in a peripheral region of the semiconductor die. An encapsulant is deposited over the semiconductor die and interconnect structure. A first insulating layer is formed over the semiconductor die and interconnect structure. A plurality of openings is formed in the first insulating layer over the interconnect structure. The openings have a pitch of 40 micrometers. The openings include a circular shape, ring shape, cross shape, or lattice shape. A conductive layer is deposited over the first insulating layer. The conductive layer includes a planar surface. A second insulating layer is formed over the conductive layer. A portion of the encapsulant is removed to expose the semiconductor die and the interconnect structure. The modular interconnect unit includes a vertical interconnect structure. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

Method of making semiconductor assembly with built-in stiffener and semiconductor assembly manufactured thereby

The present invention relates to a method of making a semiconductor assembly. In accordance with a preferred embodiment, the method includes: preparing a dielectric layer and a supporting board including a stiffener, a bump/flange sacrificial carrier and an adhesive, wherein the adhesive bonds the stiffener to the sacrificial carrier and the dielectric layer covers the supporting board; then removing the bump and a portion of the flange to form a cavity and expose the dielectric layer; then mounting a semiconductor device into the cavity; and then forming a build-up circuitry that includes a first conductive via in direct contact with the semiconductor device and provides signal routing for the semiconductor device. Accordingly, the direct electrical connection between the semiconductor device and the build-up circuitry is advantageous to high I/O and high performance, and the stiffener can provide adequate mechanical support for the build-up circuitry and the semiconductor device.

Chip embedded packages and methods for forming a chip embedded package

A chip embedded package is provided, the chip embedded package including: a plurality of dies; wherein a first die of the plurality of dies is a chip implementing a first sensor technology, and wherein a second die of the plurality of dies is a chip implementing a second sensor technology; and wherein the plurality of dies are molded with an encapsulation material; wherein at least one of the first die and the second die includes a film interconnect.

Multi-stacked bbul package

A method including forming a first portion of a build-up carrier on at least one first die, the at least one first die; coupling at least one second die to the first portion of the build-up carrier, the at least one second die separated from the first die by the at least one layer of conductive material disposed between layers of dielectric material; and after coupling the at least one second die to the first portion of the build-up carrier, forming a second portion of the build-up carrier on the at least one second die. An apparatus including a build-up carrier including including alternating layers of conductive material and dielectric material and at least two dice therein in different planes of the build-up carrier.

Package with Passive Devices and Method of Forming the Same

An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar.

Method Of Making 3D Integration Microelectronic Assembly For Integrated Circuit Devices

A microelectronic assembly for packaging/encapsulating IC devices, which includes a crystalline substrate handler having opposing first and second surfaces and a cavity formed into the first surface, a first IC device disposed in the cavity and a second IC device mounted to the second surface, and a plurality of interconnects formed through the crystalline substrate handler. Each of the interconnects includes a hole formed through the crystalline substrate handler from the first surface to the second surface, a compliant dielectric material disposed along the hole's sidewall, and a conductive material disposed along the compliant dielectric material and extending between the first and second surfaces. The compliant dielectric material insulates the conductive material from the sidewall. The second IC device, which can be an image sensor, is electrically coupled to the conductive materials of the plurality of interconnects. The first IC can be a processor for processing the signals from the image sensor.

Method Of Forming 3D Integrated Microelectronic Assembly With Stress Reducing Interconnects

A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handler with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.

Method of Manufacturing a Semiconductor Device with a Carrier Having a Cavity and Semiconductor Device

A method includes providing a carrier having a first cavity, providing a dielectric foil with a metal layer attached to the dielectric foil, placing a first semiconductor chip in the first cavity of the carrier, and applying the dielectric foil to the carrier.

Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias

A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

Embedded integrated circuit package and method for manufacturing an embedded integrated circuit package

A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.

Method of fabricating a semiconductor package

A method of fabricating a semiconductor package is provided, including: disposing a semiconductor element on a carrier; forming an encapsulant on the carrier to encapsulant the semiconductor element; forming at least one through hole penetrating the encapsulant; forming a hollow conductive through hole in the through hole and, at the same time, forming a circuit layer on an active surface of the semiconductor element and the encapsulant; forming an insulating layer on the circuit layer; and removing the carrier. By forming the conductive through hole and the circuit layer simultaneously, the invention eliminates the need to form a dielectric layer before forming the circuit layer and dispenses with the conventional chemical mechanical polishing (CMP) process, thus greatly improving the fabrication efficiency.

INCORPORATION OF PASSIVES AND FINE PITCH THROUGH VIA FOR PACKAGE ON PACKAGE

This disclosure provides systems, methods and apparatus for glass via bars that can be used in compact three-dimensional packages, including package-on-packages (PoPs). The glass via bars can provide high density electrical interconnections in the PoPs. In some implementations, the glass via bars can include integrated passive components. Packaging methods employing glass via bars are also provided. 1. A package-on-package comprising:a bottom package vertically integrated with a second package, whereinthe bottom package includes a first die and a glass via bar;the second package includes a second die; andthe first die is in electrical communication with the second die through the glass via bar.2. The package-on-package of wherein the first die is selected from a logic die claim 1 , a memory die claim 1 , a microelectromechanical systems (MEMS) die claim 1 , a radio frequency (RF) die claim 1 , a power integrated circuit (IC) die claim 1 , a sensor die claim 1 , and an actuator die.3. The package-on-package of wherein the second die is selected from a logic die claim 1 , a memory die claim 1 , a microelectromechanical systems (MEMS) die claim 1 , a radio frequency (RF) die claim 1 , a power integrated circuit (IC) die claim 1 , a sensor die claim 1 , and an actuator die.4. The package-on-package of claim 1 , wherein the first die and the second die are is different types of dies.5. The package-on-package of claim 4 , wherein the first die is a logic die and the second die is a memory die.6. The package-on-package of claim 5 , wherein the memory die attached to a substrate by flip-chip attachment.7. The package-on-package of claim 5 , wherein the memory die is a through-silicon via (TSV) memory die.8. The package-on-package of claim 1 , further comprising a third package vertically integrated with the bottom package and the second package such that the second package is disposed between the bottom package and the third package.9. The package-on-package of claim 1 , ...

Fluid storage and dispensing system including dynamic fluid monitoring of fluid storage and dispensing vessel

A monitoring system for monitoring fluid in a fluid supply vessel during operation including dispensing of fluid from the fluid supply vessel. The monitoring system includes (i) one or more sensors for monitoring a characteristic of the fluid supply vessel or the fluid dispensed therefrom, (ii) a data acquisition module operatively coupled to the one or more sensors to receive monitoring data therefrom and responsively generate an output correlative to the characteristic monitored by the one or more sensors, and (iii) a processor and display operatively coupled with the data acquisition module and arranged to process the output from the data acquisition module and responsively output a graphical representation of fluid in the fluid supply vessel, billing documents, usage reports, and/or resupply requests.

Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure

A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.

Stacked microelectronic packages having patterened sidewall conductors and methods for the fabrication thereof

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

Passive Devices in Package-on-Package Structures and Methods for Forming the Same

A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the polymer, wherein the TAVs are coupled in series. A Redistribution Line (RDL) is underlying the polymer. The RDL electrically couples a first one of the TAVs to a second one of the TAVs.

Semiconductor Device and Method of Forming FO-WLCSP with Multiple Encapsulants

A semiconductor device has a first semiconductor die including TSVs mounted to a carrier with a thermally releasable layer. A first encapsulant having a first coefficient of thermal expansion CTE is deposited over the first semiconductor die. The first encapsulant includes an elevated portion in a periphery of the first encapsulant that reduces warpage. A surface of the TSVs is exposed. A second semiconductor die is mounted to the surface of the TSVs and forms a gap between the first and second semiconductor die. A second encapsulant having a second CTE is deposited over the first and second semiconductor die and within the gap. The first CTE is greater than the second CTE. In one embodiment, the first and second encapsulants are formed in a chase mold. An interconnect structure is formed over the first and second semiconductor die.

Printed Circuit Board and Method for Manufacturing the Same

Provided is a method for manufacturing a printed circuit board. The method for manufacturing the printed circuit board includes applying an adhesive on a support board, attaching an electronic device on the adhesive, forming an insulation layer for burying the electronic device, separating the insulation layer from the support board, forming a lower insulation layer under the insulation layer, and forming a via connected to terminals of the electronic device in the insulation layer or the lower insulation layer. Thus, since an adhesion material of an adhesion film does not remain between the internal circuit patterns, and the internal circuit patterns are not stripped by an adhesion force of the adhesion film, device reliability may be secured.

Compliant printed circuit semiconductor package

A method of making a package for a semiconductor device having electrical terminals. At least one semiconductor device is located on a substrate. A first dielectric layer is printed on at least a portion of the semiconductor device to include first recesses aligned with a plurality of the electrical terminals. A conductive material is deposited in the first recesses forming contact members. A second dielectric layer is printed on at least a portion of the first dielectric layer to include second recesses aligned with a plurality of the first recesses. A conductive material is deposited in at least a portion of the second recesses to include a circuit geometry and a plurality of exposed terminals. A compliant material is deposited in recesses in one or more of the first and second dielectric layers adjacent to a plurality of the exposed terminals.

Semiconductor package and method of manufacturing the same

Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.

Method of fabricating semiconductor package structure

A semiconductor package structure is provided, including: a semiconductor chip having electrode pads disposed thereon and metal bumps disposed on the electrode pads; an encapsulant encapsulating the semiconductor chip; a dielectric layer formed on the encapsulant and having a plurality of patterned intaglios formed therein for exposing the metal bumps; a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps; and a metal foil having a plurality of metal posts disposed on a surface thereof such that the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip. Compared with the prior art, the present invention reduces the overall thickness of the package structure, increases the electrical transmission efficiency and improves the heat dissipating effect.

Land side and die side cavities to reduce package z-height

A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.

High density second level interconnection for bumpless build up layer (bbul) packaging technology

An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive material and dielectric material disposed on the device side of the die, an ultimate conductive layer patterned into a plurality of pads or lands; and a grid array including a plurality of conductive posts disposed on respective ones of the plurality of pads of the ultimate conductive layer of the body, at least one of the posts coupled to at least one of the contact points of the die through at least a portion of the conductive material of the body. A method including forming a body of a build-up carrier including a die, the body of the build-up carrier including an ultimate conductive layer and forming a grid array including a plurality of conductive posts on the ultimate conductive layer of the body.

Methods of providing dielectric to conductor adhesion in package structures

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material.

TWO-SIDED-ACCESS EXTENDED WAFER-LEVEL BALL GRID ARRAY (eWLB) PACKAGE, ASSEMBLY AND METHOD

A two-sided-access (TSA) eWLB is provided that makes it possible to easily access electrical contact pads disposed on both the front and rear faces of the die(s) of the eWLB package. When fabricating the IC die wafer, metal stamps are formed in the IC die wafer in contact with the rear faces of the IC dies. When the IC dies are subsequently reconstituted in an artificial wafer, portions of the metal stamps are exposed through the mold of the artificial wafer. When the artificial wafer is sawed to singulate the TSA eWLB packages and the packages are mounted on PCBs, any electrical contact pad that is disposed on the rear face of the IC die can be accessed via the respective metal stamp of the IC die.

SEMICONDUCTOR PACKAGES AND FORMING METHODS THEREOF

A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure. 1. A semiconductor package , comprising:a redistribution layer structure, having a first side and a second side opposite to the first side;a first semiconductor chip, electrically connected to the first side of the redistribution layer structure;a circuit board structure, electrically connected to the first side of the redistribution layer structure, wherein the circuit board structure comprises a first mask layer having an opening pattern corresponding to first semiconductor chip; andan encapsulation layer, laterally encapsulating the circuit board structure and filling in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.2. The semiconductor package of claim 1 , wherein the opening pattern of the first mask layer comprises a main pattern claim 1 , and a width of the main pattern is greater than a width of the first semiconductor chip.3. The semiconductor package of claim 2 , wherein the opening pattern of the first mask layer further comprises a plurality of channel patterns claim 2 , and each of the plurality of channel patterns extends outwardly from the main pattern.4. The semiconductor package of ...

SEMICONDUCTOR PACKAGE INCLUDING INTERPOSER AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate. 1. A semiconductor package comprising:a package substrate;a semiconductor chip on the package substrate;an interposer substrate on the semiconductor chip, the interposer substrate comprising a first surface facing the semiconductor chip and a trench in the first surface, the trench located to vertically overlap the semiconductor chip; andan insulating filler between the semiconductor chip and the interposer substrate, the insulating filler at least partially filling the trench of the interposer substrate.2. The semiconductor package of claim 1 ,wherein the interposer substrate comprises a first side wall and a second side wall opposite to and facing each other, andwherein the trench extends from the first side wall of the interposer substrate to the second side wall of the interposer substrate.3. The semiconductor package of claim 1 ,wherein the interposer substrate comprises a base insulating layer, and a lower protection insulating layer on a lower surface of the base insulating layer facing the semiconductor chip, andwherein the trench is provided in the lower protection insulating layer.4. The semiconductor package of claim 3 ,wherein the interposer substrate comprises a conductive pattern disposed in the trench, andwherein the conductive pattern comprises an upper surface in contact with the base insulating layer, a lower surface in contact with the lower protection insulating layer and a side wall in contact with the lower protection insulating layer.5. The semiconductor ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first redistribution structure having a first surface in which a first pad and a second pad are embedded and including a first redistribution layer thereon, and a vertical connection structure including a land layer and a pillar layer. The land layer is embedded in the first surface of the first redistribution structure, and a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer. 1. A semiconductor package comprising:a first redistribution structure having a first surface comprising a first pad and a second pad therein, and a second surface opposite the first surface and comprising a first redistribution layer electrically connected to the first pad and the second pad;a vertical connection structure comprising a land layer on the first pad, and a pillar layer on the land layer and electrically connected to the first redistribution layer;a semiconductor chip on the first surface of the first redistribution structure and comprising a connection electrode electrically connected to the second pad;a first encapsulant on at least a portion of the vertical connection structure and comprising a cavity sized to accept the semiconductor chip;a second encapsulant on the first encapsulant and in the cavity; anda first connection bump on the second surface of the first redistribution structure and electrically connected to the first redistribution layer,wherein the land layer is in the first surface of the first redistribution structure, anda width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer thereon.2. The semiconductor package of claim 1 , wherein a thickness of the first pad is greater than a thickness of the land layer of the vertical connection structure.3. The semiconductor package of claim 2 , wherein a thickness of the pillar layer is in a range of about 100 μm to about 200 μm claim 2 ,the thickness of the land layer is in a ...

Electronic component and method for dissipating heat from a semiconductor die

In an embodiment, an electronic component includes a dielectric core layer having a thickness, at least one semiconductor die embedded in the dielectric core layer and electrically coupled to at least one contact pad arranged on a first side of the dielectric core layer, and a heat dissipation layer arranged on a second side of the dielectric core layer and thermally coupled to the semiconductor die. The semiconductor die has a thickness that is substantially equal to, or greater than, or equal to the thickness of the dielectric core layer. The heat dissipation layer includes a material with a substantially isotropic thermal conductivity.

Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same

Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.

Integrated System and Method of Making the Integrated System

A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a first redistribution layer (RDL) disposed on a first main surface of the first packaged component, wherein the first RDL includes first pads. The system further includes a second packaged component having a second component disposed at a first main surface of the second packaged component, the first main surface having second pads and a connection layer between the first packaged component and the second packaged component, wherein the connection layer connects a first plurality of the first pads with the second pads. 1. A method for manufacturing an integrated device , the method comprising:forming a first reconstitution wafer comprising first components;forming a second reconstitution wafer comprising second components;dicing the second reconstitution wafer into second packaged components, the second packaged components comprising the second components;placing the second packaged components on a first main surface of the first reconstitution wafer; anddicing the first reconstitution wafer into integrated devices, each integrated device comprising a first packaged component and a second packaged component.2. The method of claim 1 , further comprising:placing an integrated device on a carrier;bonding the integrated device to the carrier; andencapsulating the integrated device.3. The method of claim 1 , further comprising disposing a first redistribution layer (RDL) on the first main surface of the first reconstitution wafer.4. The method of claim 3 , further comprising claim 3 , before dicing the second reconstitution wafer claim 3 , disposing a second RDL on a first main surface of the second reconstitution wafer claim 3 , wherein placing the second packaged components on the first main surface of the first reconstitution wafer comprises placing the second packaged components with second RDL regions facing ...

Integrated circuit packages and methods of forming same

An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view.

MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING SUCH DEVICES

Microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a packaged microelectronic device can include an interposer substrate with a plurality of interposer contacts. A microelectronic die is attached and electrically coupled to the interposer substrate. The device further includes a casing covering the die and at least a portion of the interposer substrate. A plurality of electrically conductive through-casing interconnects are in contact with and projecting from corresponding interposer contacts at a first side of the interposer substrate. The through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing. The through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to the first side of the interposer substrate. 1. A packaged microelectronic device , comprising:an interposer substrate having a first side with a plurality of interposer contacts and a second side opposite the first side, the second side including a plurality of interposer pads arranged in an array corresponding to a standard JEDEC pinout;a microelectronic die attached and electrically coupled to the interposer substrate;a casing covering the die and at least a portion of the interposer substrate, wherein the casing has a thickness and a top facing away from the interposer substrate; anda plurality of electrically conductive through-casing interconnects in contact with and projecting from corresponding interposer contacts, wherein the through-casing interconnects extend through the thickness of the casing to a terminus at the top of the casing, and wherein the through-casing interconnects are at least partially encapsulated in the casing,wherein the through-casing interconnects comprise a plurality of filaments attached to and projecting away from the interposer contacts in a direction generally normal to ...

PACKAGE CARRIER AND MANUFACTURING METHOD OF PACKAGE CARRIER

A package carrier including a flexible substrate, a first build-up structure and a second build-up structure is provided. The flexible substrate has a first surface and a second surface opposite to each other, and has a first opening connected between the first surface and the second surface. The first build-up structure is disposed on the first surface and covers the first opening. The second build-up structure is disposed on the second surface and has a second opening, and the first opening and the second opening are connected to each other to form a chip accommodating cavity together. In addition, a manufacturing method of the package carrier and a chip package structure having the package carrier are also provided. 1. A package carrier , comprising:a flexible substrate, having a first surface and a second surface opposite to each other, and having a first opening connected between the first surface and the second surface;a first build-up structure, disposed on the first surface and covering the first opening; anda second build-up structure, disposed on the second surface and having a second opening, wherein the first opening and the second opening are connected to each other to form a chip accommodating cavity together.2. The package carrier according to claim 1 , further comprising a patterned barrier layer claim 1 , wherein the patterned barrier layer is disposed on the first surface and extended to a bottom surface of the chip accommodating cavity.3. The package carrier according to claim 2 , wherein the patterned barrier layer is extended along an inner edge of the first opening.4. The package carrier according to claim 1 , wherein a contour of the second opening matches a contour of the first opening.5. The package carrier according to claim 1 , further comprising a patterned conductive layer claim 1 , wherein the patterned conductive layer is disposed on the first surface and extended to a bottom surface of the chip accommodating cavity.6. The package ...

ELECTRONIC COMPONENT DEVICE, METHOD OF MOUNTING ELECTRONIC COMPONENT DEVICE ON CIRCUIT BOARD, AND MOUNTING STRUCTURE OF ELECTRONIC COMPONENT DEVICE ON CIRCUIT BOARD

An electronic component device includes a mount substrate including an outer electrode on one principal surface and a mount electrode on another principal surface, at least one substrate component including a terminal electrode on one principal surface, and that is mounted on the mount substrate by joining the terminal electrode to the mount electrode, and a sealing resin layer that is provided on the mount substrate on which the at least one substrate component is mounted. The sealing resin layer includes a region with a large thickness, and a top surface including an inclination. 1. An electronic component device comprising:a mount substrate including an outer electrode on one principal surface and a mount electrode on another principal surface;at least one substrate component including a terminal electrode on one principal surface, and that is mounted on the mount substrate by the terminal electrode being joined to the mount electrode; anda sealing resin layer that is provided on the mount substrate on which the at least one substrate component is mounted; whereinthe sealing resin layer includes an increased thickness region, and a top surface including an inclination.2. The electronic component device according to claim 1 , wherein when viewed in a planar direction:the mount substrate includes a region with a reduced formation density of the outer electrode; andthe region of the sealing resin layer with the increased thickness and the region of the mount substrate with the reduced formation density of the outer electrode overlap each other.3. The electronic component device according to claim 1 , whereina plurality of the outer electrodes are provided;the outer electrodes include a signal outer electrode and a ground outer electrode; andwhen viewed in a planar direction:the mount substrate includes a region with an increased formation density of the ground outer electrode; andthe increased thickness region of the sealing resin layer and the region of the mount ...

Electronic assembly having multiple substrate segments

An electronic assembly (100) includes a mechanical carrier (102), a plurality of integrated circuits (104A, 104B) disposed on the mechanical carrier, a fan out package (108) disposed on the plurality of integrated circuits, a plurality of singulated substrates (112A, 112B) disposed on the fan out package, a plurality of electronic components (114A, 114B) disposed on the plurality of singulated substrates, and at least one stiffness ring (116A, 116B, 116C) disposed on the plurality of singulated substrates. A method for constructing an electronic assembly includes identifying a group of known good singulated substrates, joining the group of known good singulated substrates into a substrate panel, attaching at least one bridge to the substrate panel that electrically couples at least two of the known good singulated substrates, and mounting a plurality of electronic components onto the substrate panel, each electronic component of the plurality of electronic components corresponding to a respective known good singulated substrate.

PACKAGED DIE STACKS WITH STACKED CAPACITORS AND METHODS OF ASSEMBLING SAME

A stacked-die and stacked-capacitor package vertically arranged capacitors to mirror a semiconductive-device stack. The stacked capacitor can be electrically coupled to one or more semiconductive devices in the stacked architecture. 1a primary die disposed on a package substrate at a primary package level;a subsequent die stacked above the primary die at a subsequent package level; anda first subsequent-level capacitor located at the subsequent package level, wherein the first subsequent-level capacitor is electrically coupled to the subsequent die.. A semiconductive apparatus, comprising: This application is a continuation of U.S. application Ser. No. 16/017,652, filed Jun. 25, 2018, which claims the benefit of priority to Malaysian Application Serial Number PI 2017702405, filed Jun. 29, 2017, all of which are incorporated herein by reference in their entirety.This disclosure relates to power delivery for a stacked-die apparatus that allows for capacitor integration into smaller form-factor packaging.Semiconductive device miniaturization includes challenges for passive devices to be located at useful proximity to other structures.Power-delivery efficiency in semiconductive packages is provided for 3D stacked-dice architectures by decreasing the decoupling loop-inductance path, such as the path from a decoupling capacitor to a semiconductive die the capacitor is servicing. Scaling issues are addressed by stacking a decoupling capacitor into a stacked-die level, which keeps the decoupling capacitor close to a semiconductive die also in the stacked level. Two or more semiconductive devices are arranged in a stacked architecture within a package, and at least one capacitor may be stacked with any given stacked semiconductive device. The architecture may be referred to as stacked-die, stacked-capacitor (SDSC) architecture.In an embodiment, a capacitor stack is vertically arranged to mirror a semiconductive-device stack. In an embodiment, the stacked capacitor is ...

Semiconductor Package and Method

In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

Electronic circuit device and method of manufacturing electronic circuit device

The electronic circuit device according to the present invention including the wiring layer 13 including a plurality of the metal wirings, the photosensitive resin layer 21 made of the photosensitive resin arranged on the wiring layer 13, and the first electronic circuit element 33 arranged in the photosensitive resin layer 21. In this electronic circuit device, a plurality of opening 41 for exposing a part of the wiring layer 13 is formed on the photosensitive resin layer 21, and further, together with three-dimensionally connected to the first electronic circuit element 33, the re-distribution layer 42 on the first electronic circuit element including a plurality of the metal wirings which is three-dimensionally connected via a plurality of openings to a part of the wiring layer 13, and the first external connection terminal 51 connected to the re-distribution layer 42 are formed.

Multi-Stacked Package-on-Package Structures

A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process. 1. A semiconductor package comprising:a redistribution layer;at least one die, disposed on the redistribution layer;a molding compound, disposed on the redistribution layer and encapsulating the at least one die;through interlayer vias, disposed on the redistribution layer and penetrating the molding compound, wherein the through interlayer vias are electrically connected to the redistribution layer and the at least one die;a protection film, disposed on the molding compound and the at least one die, wherein the protection film located on the at least one die includes a trench pattern with trenches of substantially flat bottoms;connectors, disposed on the through interlayer vias; andconductive elements, electrically connected to the redistribution layer.2. The semiconductor package as claimed in claim 1 , further comprising a dielectric material layer disposed on the molding compound claim 1 , on the at least one die and disposed between the molding compound claim 1 , the at least one die and the protection film claim 1 , wherein the dielectric material layer exposes the through interlayer vias.3. The semiconductor package as claimed in claim 2 , wherein the dielectric material layer located on the molding compound includes first openings and the connectors located within the first openings are in direct contact with the through interlayer vias.4. The semiconductor package as claimed in claim 3 ...

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first interconnect structure over the substrate;disposing a first semiconductor die over the first interconnect structure;disposing the substrate over a carrier with the first semiconductor die oriented away from the carrier;depositing an encapsulant over the carrier, substrate, and first semiconductor die;forming a second interconnect structure over the encapsulant and semiconductor die; andremoving the substrate to expose the first interconnect structure after forming the second interconnect structure.2. The method of claim 1 , further including forming a conductive column over the first interconnect structure.3. The method of claim 2 , wherein the conductive column extends from the first interconnect structure to the second interconnect structure ...

LOGIC DRIVE BASED ON MULTICHIP PACKAGE COMPRISING STANDARD COMMODITY FPGA IC CHIP WITH CRYPTOGRAPHY CIRCUITS

A multichip package comprising: a first chip package comprising a first semiconductor IC chip, a first polymer layer in a space beyond and extending from a sidewall of the first semiconductor IC chip, a first through package via in the first polymer layer, and a first interconnection scheme under the first semiconductor IC chip, first polymer layer and first through package via, wherein the first semiconductor IC chip comprises a plurality of volatile memory cells configured to store first data associated with a plurality of resulting values for a look-up table (LUT) and a selection circuit configured to select, in accordance with a first input data set thereof, a data from a second input data set thereof as an output data for the logic operation; a first metal bump under the first chip package; and a non-volatile memory IC chip over the first chip package, wherein the non-volatile memory IC chip comprises a plurality of first non-volatile memory cells configured to store second data associated with the plurality of resulting values for the look-up table (LUT), wherein the first data are associated with the second data. 1. A multichip package comprising:a first chip package comprising a first semiconductor integrated-circuit (IC) chip, a first polymer layer in a space beyond and extending from a sidewall of the first semiconductor integrated-circuit (IC) chip, a first through package via in the first polymer layer, and a first interconnection scheme under the first semiconductor integrated-circuit (IC) chip, first polymer layer and first through package via, wherein a top surface of the first polymer layer, a top surface of the first semiconductor integrated-circuit (IC) chip and a top surface of the first through package via are coplanar, wherein the first interconnection scheme comprises a first interconnection metal layer under the first semiconductor integrated-circuit (IC) chip, first polymer layer and first through package via, wherein the first ...

Multi-Stack Package-on-Package Structures

A package includes a first device die, and a first encapsulating material encapsulating the first device die therein. A bottom surface of the first device die is coplanar with a bottom surface of the first encapsulating material. First dielectric layers are underlying the first device die. First redistribution lines are in the first dielectric layers and electrically coupling to the first device die. Second dielectric layers are overlying the first device die. Second redistribution lines are in the second dielectric layers and electrically coupling to the first redistribution lines. A second device die is overlying and electrically coupling to the second redistribution lines. No solder region connects the second device die to the second redistribution lines. A second encapsulating material encapsulates the second device die therein. A third device die is electrically coupled to the second redistribution lines. A third encapsulating material encapsulates the third device die therein. 1. A package comprising:a first interconnect structure comprising a plurality of dielectric layers and a first plurality of redistribution lines in the plurality of dielectric layers;a first device die over the first interconnect structure;a first encapsulant encapsulating the first device die therein;a second interconnect structure over the first encapsulant, wherein the second interconnect structure comprises a second plurality of redistribution lines therein;a first plurality of through-vias penetrating through the first encapsulant, wherein the first plurality of through-vias electrically connect the first plurality of redistribution lines to the second plurality of redistribution lines;a second device die over and bonding to the second interconnect structure, wherein the second device die comprises a semiconductor substrate, and a second plurality of through-vias penetrating through the semiconductor substrate;a second encapsulant encapsulating the second device die therein; anda ...

Process Control for Package Formation

A method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. The opening is then extended through the first etch stop layer. A second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. The second etching process stops on a second etch stop layer in the plurality of gap-filling layers. The method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via.

Semiconductor Device and Method of Manufacture

A semiconductor device and method of making a conductive connector is provided. In an embodiment an opening is formed within a photoresist by adjusting the center point of an in-focus area during the exposure process. Once the photoresist has been developed to form an opening, an after development baking process is utilized to reshape the opening. Once reshaped, a conductive material is formed into the opening to take on the shape of the opening. 1. A method of manufacturing a semiconductor device , the method comprising:applying a photoresist over a seed layer;exposing the photoresist to a patterned energy source, the patterned energy source having an in-focus area with a center point, the center point located below a surface of the photoresist facing towards the seed layer;developing the photoresist to form an opening; andplating an external connector into the opening.2. The method of claim 1 , further comprising annealing the photoresist after the developing the photoresist claim 1 , wherein the annealing the photoresist reshapes the opening.3. The method of claim 2 , wherein the annealing the photoresist raises a temperature of the photoresist to between about no ° C. and about 130° C.4. The method of claim 1 , wherein the center point is located below the surface of the photoresist a distance of between about 60 μm and about 70 μm.5. The method of claim 1 , further comprising removing a portion of the seed layer not covered by the external connector.6. The method of claim 1 , wherein the developing the photoresist comprises removing an unexposed portion of the photoresist.7. The method of claim 1 , wherein the seed layer is located over an encapsulant around a semiconductor device and a through encapsulant via.8. A method of manufacturing a semiconductor device claim 1 , the method comprising:exposing a photoresist to a patterned energy source, the photoresist being located over an encapsulant located between a semiconductor die and a through encapsulant via; ...

Inductor module

An inductor module includes an insulating flexible substrate including a thermoplastic resin, an IC element included in the flexible substrate, chip capacitors included in the flexible substrate, a chip inductor that includes a magnetic-material body and is located on a first main surface of the flexible substrate, and input and output terminals on a second main surface of the flexible substrate. The IC element may be a switching IC element, the chip inductor may be a choke coil, and the inductor module may be a DC/DC converter module.

Chip package structure with molding layer and method for forming the same

A method for forming a chip package structure is provided. The method includes disposing a chip over a redistribution structure. The method includes forming a molding layer over the redistribution structure adjacent to the chip. The method includes partially removing the molding layer to form a trench in the molding layer, and the trench is spaced apart from the chip.

Underfill Control Structures and Method

A semiconductor device and method of reducing the risk of underbump metallization poisoning from the application of underfill material is provided. In an embodiment a spacer is located between a first underbump metallization and a second underbump metallization. When an underfill material is dispensed between the first underbump metallization and the second underbump metallization, the spacer prevents the underfill material from creeping towards the second underbump metallization. In another embodiment a passivation layer is used to inhibit the flow of underfill material as the underfill material is being dispensed.

MICROELECTRONIC ASSEMBLIES HAVING INTERPOSERS

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a high bandwidth interconnect, a first interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the first interposer is electrically coupled to the high bandwidth interconnect, and a second interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the second interposer is electrically coupled to the high bandwidth interconnect, and wherein the first interposer is electrically coupled to the second interposer via the high bandwidth interconnect. 1. A microelectronic assembly , comprising:a package substrate having a high bandwidth interconnect;a first interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the first interposer is electrically coupled to the high bandwidth interconnect; anda second interposer having high bandwidth circuitry coupled to the package substrate, wherein the high bandwidth circuitry of the second interposer is electrically coupled to the high bandwidth interconnect, and wherein the first interposer is electrically coupled to the second interposer via the high bandwidth interconnect.2. The microelectronic assembly of claim 1 , wherein the high bandwidth interconnect is a waveguide.3. The microelectronic assembly of claim 1 , wherein the high bandwidth circuitry of the first interposer is radio frequency (RF) circuitry.4. The microelectronic assembly of claim 1 , further comprising:a first die having a first surface and an opposing second surface, wherein the first surface of the first die is electrically coupled to a surface of the package substrate and the second surface of the first die is electrically coupled to the first interposer; anda second die having a first surface and an ...

SEMICONDUCTOR DEVICE

Provided is a semiconductor device including an input terminal including a P terminal and an N terminal; a laminated circuit substrate connected to the input terminal; a power substrate provided above the laminated circuit substrate; a connecting section electrically connecting the laminated circuit substrate and the power substrate; a capacitor provided in a conduction path between the P terminal and the N terminal; and a resistor provided in series with the capacitor in the conduction path between the P terminal and the N terminal. The capacitor may be provided in a region where the input terminal or the connecting section is provided, in an overhead view. 1. A semiconductor device comprising:an input terminal including a P terminal and an N terminal;a laminated circuit substrate connected to the input terminal;a power substrate provided above the laminated circuit substrate;a connecting section electrically connecting the laminated circuit substrate and the power substrate;a capacitor provided in a conduction path between the P terminal and the N terminal; anda resistor provided in series with the capacitor in the conduction path between the P terminal and the N terminal, whereinthe capacitor is provided in a region where the input terminal or the connecting section is provided, in an overhead view.2. The semiconductor device according to claim 1 , whereinthe laminated circuit substrate includes a first laminated circuit substrate connected to the P terminal and a second laminated circuit substrate connected to the N terminal, andthe semiconductor device further comprises:a first connecting section that electrically connects the first laminated circuit substrate and the power substrate; anda second connecting section that electrically connects the second laminated circuit substrate and the power substrate.3. The semiconductor device according to claim 2 , whereinthe capacitor is provided in the first connecting section, andthe resistor is provided in the second ...

FULLY INTEGRATED VOLTAGE REGULATOR CIRCUITRY WITHIN A SUBSTRATE

Embodiments herein relate to integrating FIVR switching circuitry into a substrate that has a first side and a second side opposite the first side, where the first side of the substrate to electrically couple with a die and to provide voltage to the die and the second side of the substrate is to couple with an input voltage source. In embodiments, the FIVR switching circuitry may be printed onto the substrate using OFET, CNT, or other transistor technology, or may be included in a separate die that is incorporated within the substrate. 1. A package comprising:a substrate, having a first side and a second side opposite the first side, the first side of the substrate to electrically couple with a die and to provide voltage to the die, and the second side of the substrate to couple with an input voltage source; andwherein the substrate is to include fully integrated voltage regulator (FIVR) circuitry to regulate a voltage to the die.2. The package of claim 1 , wherein at least a portion of the FIVR circuitry is included within another die included within the substrate and electrically coupled with the first side of the substrate and with the second side of the substrate.3. The package of claim 2 , wherein the other die has a first side and a second side opposite the first side claim 2 , and wherein the first side of the other die is adjacent to a metal layer.4. The package of claim 2 , wherein the other die is disposed within a cavity in a layer of the substrate.5. The package of claim 1 , wherein at least a portion of the FIVR circuitry further includes one or more Organic Field Effect Transistors (OFET) within the substrate to provide FIVR switching circuitry.6. The package of claim 5 , wherein at least one of the one or more OFET has a thickness of approximately 1 micrometer.7. The package of claim 5 , wherein a copper (Cu) block is proximate to the OFET to serve as a heat sink for the OFET.8. The package of claim 1 , wherein at least a portion of the FIVR circuitry ...