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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 167050. Отображено 100.
05-01-2012 дата публикации

Driving circuit and liquid crystal display device including the same

Номер: US20120002146A1
Автор: Jin-Cheol Hong, Min-Hwa Kim
Принадлежит: Individual

A tape carrier package (TCP) includes a film, a plurality of output leads and a plurality of input leads on the film, the plurality of output leads and the plurality of input leads being disposed on different sides, first and second TCP alignment marks arranged on opposing sides of the plurality of output leads, and a third TCP alignment mark at a central portion of the plurality of output leads.

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Номер записи: 1
05-01-2012 дата публикации

Copper interconnection structure and method for forming copper interconnections

Номер: US20120003390A1
Автор: Akihiro Shibatomi, Junichi Koike
Принадлежит: Advanced Interconnect Materials LLC

A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer, and a diffusion barrier layer formed between the insulating layer and the interconnection body. The diffusion barrier layer includes an oxide layer including manganese having a compositional ratio of oxygen to manganese (y/x) less than 2.

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Номер записи: 2
05-01-2012 дата публикации

Method for manufacture of integrated circuit package system with protected conductive layers for pads

Номер: US20120003830A1
Автор: Haijing Cao, Qing Zhang, Yaojian Lin
Принадлежит: Individual

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

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Номер записи: 3
05-02-2018 дата публикации

Радиоэлектронный модуль со скрытой поликристаллической меткой из токопроводящего материала

Номер: RU0000176968U1
Автор: Антон Валерьевич Семенов, Виктория Викторовна Горелова, Виталий Николаевич Старцев, Марина Анатольевна Нефедова
Принадлежит: Федеральное государственное унитарное предприятие "18 Центральный научно-исследовательский институт" Министерства обороны Российской Федерации

Полезная модель относится к области радиотехники, а именно к изделиям со скрытыми метками, наносимыми на радиоэлектронные модули, например, регистрационные метки, контрольные рисунки и т.п. для маркировки и последующей идентификации корпусированных радиоэлектронных модулей в любой период их жизненного цикла. Радиоэлектронный модуль со скрытой поликристаллической меткой из радиопоглощающего материала, имеющий, по меньшей мере, два вывода, один для подачи входного электрического сигнала, другой для снятия выходного. При этом метка помещается внутрь корпуса в виде вставки из токопроводящего материала, занимающей не менее 1% объема корпуса, и согласно своим физическим, геометрическим, объемным свойствам вносит свой характерный вклад в искажение проходящего через изделие сигнала, преобразовывая его, таким образом, в своего рода частотный идентификатор, причем условием подлинности радиоэлектронного модуля является совпадение измеренной АЧХ изделия с АЧХ, измеренной и паспортизированной на стадии изготовления упомянутого изделия (радиопортрет изделия). Технический результат заключается в возможности быстрой низкоэнергетической неразрушающей идентификации радиоэлектронного модуля, определении его принадлежности к маркированной партии и, как следствие, установлении факта подлинности исследуемой партии и подлинности изделий. 2 з.п. ф-лы, 3 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 176 968 U1 (51) МПК H01L 23/544 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (52) СПК H01L 23/544 (2017.08) (21)(22) Заявка: 2017107349, 06.03.2017 (24) Дата начала отсчета срока действия патента: Дата регистрации: 05.02.2018 (45) Опубликовано: 05.02.2018 Бюл. № 4 Адрес для переписки: 111123, Москва, Е-123, ФГУП "18 ЦНИИ" МО РФ, руководителю (73) Патентообладатель(и): Федеральное государственное унитарное предприятие "18 Центральный научно-исследовательский институт" Министерства обороны Российской Федерации (RU) (56) Список документов, ...

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Номер записи: 4
12-01-2012 дата публикации

Semiconductor device structures including damascene trenches with conductive structures and related method

Номер: US20120007209A1
Автор: Howard E. Rhodes
Принадлежит: Micron Technology Inc

A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure.

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Номер записи: 5
12-01-2012 дата публикации

Semiconductor chip and method for fabricating the same

Номер: US20120007213A1
Автор: Hyeong Seok Choi, Jin Hui Lee
Принадлежит: Hynix Semiconductor Inc

A semiconductor chip includes: a semiconductor substrate in which a bonding pad is provided on a first surface thereof; a through silicon via (TSV) group including a plurality of TSVs connected to the bonding pad and exposed to a second surface opposite to the first surface of the semiconductor substrate; and a fuse box including a plurality of fuses connected to the plurality of TSVs and formed on the first surface of the semiconductor substrate.

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Номер записи: 6
12-01-2012 дата публикации

Method for Reducing Chip Warpage

Номер: US20120007220A1
Автор: Chun-Ren Cheng, Jiou-Kang Lee, Jung-Huei Peng, Shang-Ying Tsai, Ting-Hau Wu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.

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Номер записи: 7
12-01-2012 дата публикации

Metal wire for a semiconductor device formed with a metal layer without voids therein and a method for forming the same

Номер: US20120007240A1
Автор: Baek Mann Kim, Dong Ha JUNG, Jeong Tae Kim, Soo Hyun Kim, Sun Woo HWANG, Young Jin Lee
Принадлежит: Hynix Semiconductor Inc

A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO 2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO 2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

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Номер записи: 8
12-01-2012 дата публикации

Resin-Encapsulated Semiconductor Device

Номер: US20120007247A1
Автор: Motoharu Haga, Shoji Yasunaga, Yasumasa Kasuya
Принадлежит: ROHM CO LTD

A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more.

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Номер записи: 9
12-01-2012 дата публикации

Power semiconductor module and fabrication method

Номер: US20120009733A1
Автор: Eladio Clemente Delgado, Ernest Wayne Balch, Kevin Matthew Durocher, Paul Alan McConnelee, Raymond Albert Fillion, Richard Alfred Beaupre, Stephen Daley Arthur
Принадлежит: General Electric Co

A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

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Номер записи: 10
19-01-2012 дата публикации

Package structure

Номер: US20120013002A1
Автор: Shih-Ping Hsu
Принадлежит: Unimicron Technology Corp

Disclosed is a package structure including a semiconductor chip disposed in a core board having a first surface and an opposite second surface. The package structure further includes a plurality of first and second electrode pads disposed on an active surface and an opposite inactive surface of the semiconductor chip respectively, the semiconductor chip having a plurality of through-silicon vias for electrically connecting the first and second electrode pads. As a result, the semiconductor chip is electrically connected to the two sides of the package structure via the through-silicon vias instead of conductive through holes, so as to enhance electrical quality and prevent the inactive surface of the semiconductor chip from occupying wiring layout space of the second surface of the core board to thereby increase wiring layout density and enhance electrical performance.

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Номер записи: 11
26-01-2012 дата публикации

Ceramic electronic component and wiring board

Номер: US20120018204A1
Автор: Koji Sato, Yasuhiro Nishisaka, Yukio Sanada
Принадлежит: Murata Manufacturing Co Ltd

A ceramic electronic component includes a ceramic element body having a substantially rectangular parallelepiped shape, and first and second external electrodes. The first and second external electrodes are provided on a first principal surface. Portions of the first and second external electrodes project further than the other portions in a thickness direction. A projecting portion of the first external electrode is provided at one end of the first external electrode in a length direction and a second projecting portion of the second external electrode is provided at another end of the second external electrode in the length direction. Thus, a concave portion is provided between the projecting portions, and a portion of the first principal surface provided between the first and second external electrodes is exposed.

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Номер записи: 12
26-01-2012 дата публикации

Substrate for semiconductor element, method for manufacturing substrate for semiconductor element, and semiconductor device

Номер: US20120018867A1
Автор: Junko Toda, Susumu Maniwa, Takehito Tsukamoto
Принадлежит: Toppan Printing Co Ltd

Provided is a manufacturing method of a semiconductor element substrate including: a step of forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; a step of forming a second photoresist pattern on the second surface of the metallic plate; a step of forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; a step of forming a plurality of concaved parts on the second surface of the metallic plate; a step of forming a resin layer by injecting a resin to the plurality of concaved parts; and a step of etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.

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Номер записи: 13
26-01-2012 дата публикации

Stack package and method for manufacturing the same

Номер: US20120018879A1
Автор: Cheol-Ho JOH, Eun-Hye DO, Hee-Min SHIN, Ji-Eun Kim, Kyu-Won Lee
Принадлежит: Hynix Semiconductor Inc

A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

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Номер записи: 14
26-01-2012 дата публикации

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

Номер: US20120018904A1
Автор: Jianmin Fang, KANG Chen, Xia Feng, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

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Номер записи: 15
02-02-2012 дата публикации

Semiconductor device and method of manufacturing semiconductor device

Номер: US20120025290A1
Автор: Kazuhiko Takada
Принадлежит: Fujitsu Semiconductor Ltd

A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole.

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Номер записи: 16
02-02-2012 дата публикации

Semiconductor device comprising a passive component of capacitors and process for fabrication

Номер: US20120025348A1
Автор: Laurent Marechal, Romain Coffy, Yvon Imbs
Принадлежит: STMicroelectronics Grenoble 2 SAS

A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.

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Номер записи: 17
02-02-2012 дата публикации

Semiconductor device and semiconductor package including the same

Номер: US20120025349A1
Автор: Hyun-seok Kim, Hyung-Dong Lee, Jun-Ho Lee
Принадлежит: Individual

Provided is a semiconductor device capable of removing a power ground grid noise using a small area. The semiconductor device includes a first chip including at least one decoupling capacitor; and a second semiconductor chip stacked over the first semiconductor chip, including internal circuits.

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Номер записи: 18
02-02-2012 дата публикации

Laminated semiconductor substrate, laminated chip package and method of manufacturing the same

Номер: US20120025354A1
Автор: Atsushi Iijima, Hiroyuki Ito, Yoshitaka Sasaki
Принадлежит: Headway Technologies Inc, SAE Magnetics HK Ltd

In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have an electromagnetic shielding layer formed using a ferromagnetic body. The electromagnetic shielding layer is formed in a shielding region except the extending zone. The extending zone is set a part which the wiring electrode crosses, in a peripheral edge part of the device region.

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Номер записи: 19
02-02-2012 дата публикации

Semiconductor device and method of designing a wiring of a semiconductor device

Номер: US20120025377A1
Автор: Hideaki Ikuma, Shoji Seta, Yukihito Oowaki
Принадлежит: Toshiba Corp

A semiconductor device has an LSI chip including a semiconductor substrate, an LSI core section provided at a center portion of the semiconductor substrate and serving as a multilayered wiring layer of the semiconductor substrate, a first rewiring layer provided adjacent to an outer periphery of the LSI core section on the semiconductor substrate and including a plurality of wiring layers, a first pad electrode disposed at an outer periphery of the first rewiring layer, and an insulation layer covering the first pad electrode. The semiconductor device includes a second rewiring layer provided on the LSI chip and including a rewiring connected to the first pad electrode. The semiconductor device includes a plurality of ball electrodes provided on the second rewiring layer. The first rewiring layer is electrically connected to the LSI core section and the first pad electrode.

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Номер записи: 20
02-02-2012 дата публикации

Semiconductor device and method of manufacturing semiconductor device

Номер: US20120025395A1
Автор: Shinichi Chikaki, Takahiro Nakayama
Принадлежит: Renesas Electronics Corp, Ulvac Inc

A semiconductor device includes: a first porous layer that is formed over a substrate and includes a SiO 2 skeleton; a second porous layer that is formed immediately above the first porous layer and includes a SiO 2 skeleton; a via wiring that is provided in the first porous layer; and a trench wiring that is buried in the second porous layer. The first porous layer has a pore density x 1 of 40% or below and the second porous layer has a pore density x 2 of (x 1 +5) % or above.

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Номер записи: 21
02-02-2012 дата публикации

Semiconductor device and method of fabricating the same

Номер: US20120028460A1
Автор: Kazuyuki Higashi, Makoto Wada
Принадлежит: Toshiba Corp

A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member; a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.

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Номер записи: 22
09-02-2012 дата публикации

Method for fabrication of a semiconductor device and structure

Номер: US20120032294A1
Автор: Brian Cronquist, Deepak C. Sekar, Israel Beinglass, Jan Lodewijk de Jong, Zvi Or-Bach
Принадлежит: Monolithic 3D Inc

A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

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Номер записи: 23
09-02-2012 дата публикации

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

Номер: US20120032298A1
Автор: Hideki Fujii, Kenji Furuya, Yuichi Miyagawa
Принадлежит: Renesas Electronics Corp

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

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Номер записи: 24
09-02-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120032323A1
Автор: Akihiro Osaki, Atsushi Ishii, Masahiko Fujisawa, Masahiro Matsumoto
Принадлежит: Renesas Electronics Corp

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

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Номер записи: 25
09-02-2012 дата публикации

Semiconductor device

Номер: US20120032325A1
Автор: Osamu Miyata, Shingo Higuchi
Принадлежит: ROHM CO LTD

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

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Номер записи: 26
09-02-2012 дата публикации

Self-aligned permanent on-chip interconnect structure formed by pitch splitting

Номер: US20120032336A1
Автор: Qinghuang Lin
Принадлежит: International Business Machines Corp

A method of fabricating an interconnect structure is provided. The method includes forming a hybrid photo-patternable dielectric material atop a substrate. The hybrid photo-patternable dielectric material has dual-tone properties with a parabola like dissolution response to radiation. The hybrid photo-patternable dielectric material is then image-wise exposed to radiation such that a self-aligned pitch split pattern forms. A portion of the self-aligned split pattern is removed to provide a patterned hybrid photo-patternable dielectric material having at least one opening therein. The patterned hybrid photo-patternable dielectric material is then converted into a cured and patterned dielectric material having the at least one opening therein. The at least one opening within the cured and patterned dielectric material is then filed with at least an electrically conductive material. Also provided are a hybrid photo-patternable dielectric composition and an interconnect structure.

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Номер записи: 27
09-02-2012 дата публикации

Gain Enhanced LTCC System-on-Package for UMRR Applications

Номер: US20120032836A1
Автор: Atif SHAMIM, Farhan Abdul Ghaffar, Khaled Nabil Salama, Muhammad Umair Khalid
Принадлежит: King Abdullah University of Science and Technology KAUST

An apparatus, system, and method for Gain Enhanced LTCC System-on-Package radar sensor. The sensor includes a substrate and an integrated circuit coupled to the substrate, where the integrated circuit is configured to transmit and receive radio frequency (RF) signals. An antenna may be coupled to the integrated circuit and a lens may be coupled to the antenna. The lens may be configured to enhance the gain of the sensor.

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Номер записи: 28
09-02-2012 дата публикации

Energy Conditioning Circuit Arrangement for Integrated Circuit

Номер: US20120034774A1
Автор: Anthony A. Anthony, William M. Anthony
Принадлежит: X2Y Attenuators LLC

The present invention relates to an interposer substrate for interconnecting between active electronic componentry such as but not limited to a single or multiple integrated circuit chips in either a single or a combination and elements that could comprise of a mounting substrate, substrate module, a printed circuit board, integrated circuit chips or other substrates containing conductive energy pathways that service an energy utilizing load and leading to and from an energy source. The interposer will also possess a multi-layer, universal multi-functional, common conductive shield structure with conductive pathways for energy and EMI conditioning and protection that also comprise a commonly shared and centrally positioned conductive pathway or electrode of the structure that can simultaneously shield and allow smooth energy interaction between grouped and energized conductive pathway electrodes containing a circuit architecture for energy conditioning as it relates to integrated circuit device packaging. The invention can be employed between an active electronic component and a multilayer circuit card. A method for making the interposer is not presented and can be varied to the individual or proprietary construction methodologies that exist or will be developed.

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Номер записи: 29
09-02-2012 дата публикации

Method for Forming a Patterned Thick Metallization atop a Power Semiconductor Chip

Номер: US20120034775A1
Автор: Il Kwan Lee
Принадлежит: Individual

A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK 1 together with its built-in alignment mark using a hot metal process; depositing a top metal layer of sub-thickness TK 2 using a cold metal process thus forming a stacked thick metallization of total thickness TK=TK 1 +TK 2 ; then, use the built-in alignment mark as reference, patterning the stacked thick metallization. A patterned thick metallization is thus formed with the advantages of better metal step coverage owing to the superior step coverage nature of the hot metal process as compared to the cold metal process; and lower alignment error rate owing to the lower alignment signal noise nature of the cold metal process as compared to the hot metal process.

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Номер записи: 30
16-02-2012 дата публикации

Overmolded electronic module with an integrated electromagnetic shield using smt shield wall components

Номер: US20120036710A1
Автор: Larry D. Pottebaum, Philip H. Thompson
Принадлежит: Skyworks Solutions Inc

An electronic module with an integrated electromagnetic shield using surface mount shield wall components has been disclosed. Each surface mount shield wall component provides side shielding of the circuitry within the overmolded electronic module and provides an exposed conductive shield wall section to which a top conductive shield can be applied. By including the shield structure as part of the overmolded electronic module, the need for a separate shield and separate process steps for installing the separate shield can be eliminated. Each surface mount shield wall component comprises a non-conductive portion that provides stability during a reflow soldering process, but at least a sacrificial portion of the non-conductive portion can be removed to reduce the amount of area occupied by the overmoldable shield structure.

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Номер записи: 31
16-02-2012 дата публикации

Method for molecular adhesion bonding at low pressure

Номер: US20120038027A1
Автор: Marcel Broekaart
Принадлежит: Soitec SA

The present invention relates to a method for molecular adhesion bonding between at least a first wafer and a second wafer involving aligning the first and second wafers, placing the first and second wafers in an environment having a first pressure (P 1 ) greater than a predetermined threshold pressure; bringing the first wafer and the second wafer into alignment and contact; and initiating the propagation of a bonding wave between the first and second wafer after the wafers are aligned and in contact by reducing the pressure within the environment to a second pressure (P 2 ) below the threshold pressure. The invention also relates to the three-dimensional composite structure that is obtained by the described method of adhesion bonding.

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Номер записи: 32
16-02-2012 дата публикации

Semiconductor device

Номер: US20120038033A1
Автор: Akira Oga, Masanori Minamio, YOSHIHIRO Tomita
Принадлежит: Panasonic Corp

A semiconductor device includes a first semiconductor chip 1 , a second semiconductor chip 4 , a first lead frame 3 including a first die pad 9 on which the first semiconductor chip 1 is mounted, and a second lead frame 5 including a second die pad 11 on which the second semiconductor chip 4 is mounted. A sealing structure 6 covers the first semiconductor chip 1 and the second semiconductor chip 4 . A noise shield 7 is disposed between the first semiconductor chip 1 and the second semiconductor chip 4.

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Номер записи: 33
16-02-2012 дата публикации

Composite Electronic Circuit Assembly

Номер: US20120039004A1
Автор: Alain Artieri
Принадлежит: ST Ericsson Grenoble SAS, St Ericsson SA

A composite electronic circuit assembly comprises two MOS or CMOS circuit dice ( 100, 200 ) superimposed inside a package. Different modules of the circuit assembly are distributed between the two dice based on the digital, analog, or hybrid nature of said modules. Such a distribution makes it possible to group together the digital modules of the circuit assembly in one of the die and the analog or hybrid modules in the other die. The production cost, development time, and electrical energy consumption of the circuit assembly may thus be reduced.

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Номер записи: 34
23-02-2012 дата публикации

Semiconductor device and method for forming the same

Номер: US20120043592A1
Автор: Chao Zhao, Huilong Zhu, Wenwu Wang
Принадлежит: Institute of Microelectronics of CAS

The present invention provides a semiconductor device. The semiconductor device comprises contact plugs that comprise a first contact plug formed by a first barrier layer arranged on the source and drain regions and a tungsten layer arranged on the first barrier layer; and second contact plugs comprising a second barrier layer arranged on both of the metal gate and the first contact plug and a conductive layer arranged on the second barrier layer. The conductivity of the conductive layer is higher than that of the tungsten layer. A method for forming the semiconductor device is also provided. The present invention provides the advantage of enhancing the reliability of the device when using the copper contact technique.

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Номер записи: 35
23-02-2012 дата публикации

Nonvolatile semiconductor memory device and method for manufacturing same

Номер: US20120043601A1
Автор: Takashi Maeda, Yoshihisa Iwata
Принадлежит: Toshiba Corp

In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

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Номер записи: 36
23-02-2012 дата публикации

Mechanisms for forming copper pillar bumps using patterned anodes

Номер: US20120043654A1
Автор: Chih-Wei Lin, Chung-Shi Liu, Ming-Da Cheng, Wen-Hsiung LU
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

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Номер записи: 37
23-02-2012 дата публикации

Interconnects with improved tddb

Номер: US20120043659A1
Автор: Jing Hui Li, Lawrence A. Clevenger, Wu Ping Liu
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD, International Business Machines Corp

A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.

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Номер записи: 38
23-02-2012 дата публикации

Authentication device, authentication method, and an information storage medium storing a program

Номер: US20120045114A1
Автор: Kenta Ogawa, Yasuhiro MATSUMARU
Принадлежит: Renesas Electronics Corp

There is provided an authentication device including an authentication information storage unit that stores authentication information acquired from an authentication pattern including a part or the entirety of a mottled pattern or a dot pattern formed over an electronic component as information for indentifying each of a plurality of electronic components, an authentication information acquiring unit that acquires a first authentication information acquired from the authentication pattern formed over a first electronic component that is an object to be authenticated, a search unit that searches whether or not the authentication information storage unit stores the first authentication information by using the first authentication information as a search key, and an output unit that outputs a search result of the search unit.

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Номер записи: 39
23-02-2012 дата публикации

Method of making interconnect structure

Номер: US20120045893A1
Автор: Heinrich Koerner
Принадлежит: Individual

One or more embodiments relate to a method of forming a semiconductor device having a substrate, comprising: providing a Si-containing layer; forming a barrier layer over the Si-containing layer, the barrier layer comprising a compound including a metallic element; forming a metallic nucleation_seed layer over the Si-containing layer, the nucleation_seed layer including the metallic element; and forming a metallic interconnect layer over the nucleation_seed layer, wherein the barrier layer and the nucleation_seed layer are formed without exposing the semiconductor device substrate to the ambient atmosphere.

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Номер записи: 40
01-03-2012 дата публикации

Semiconductor structures

Номер: US20120049186A1
Автор: Calvin K. Li, En-Hsing Chen, Paul Wai Kie Poon, Yung-Tin Chen
Принадлежит: En-Hsing Chen, Li Calvin K, Paul Wai Kie Poon, Yung-Tin Chen

Test structures are formed during semiconductor processing with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.

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Номер записи: 41
01-03-2012 дата публикации

Interconnect Structure for Semiconductor Devices

Номер: US20120049371A1
Автор: Hui-Lin Chang, Hung Chun Tsai, Syun-Ming Jang, Yung-Cheng Lu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A cap layer for a copper interconnect structure formed in a first dielectric layer is provided. In an embodiment, a conductive layer is located within a dielectric layer and a top surface of the conductive layer has either a recess, a convex surface, or is planar. An alloy layer overlies the conductive layer and is a silicide alloy having a first material from the conductive layer and a second material of germanium, arsenic, tungsten, or gallium.

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Номер записи: 42
01-03-2012 дата публикации

Bumpless build-up layer package with pre-stacked microelectronic devices

Номер: US20120049382A1
Автор: Pramod Malatkar
Принадлежит: Intel Corp

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

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Номер записи: 43
01-03-2012 дата публикации

Packaging structure of electronic components and a manufacturing method thereof

Номер: US20120051002A1
Автор: Hsing-Kuei Lin, Shing-Yeu Juang
Принадлежит: ACSIP Tech Inc

A manufacturing method of a packaging structure of electronic components is provided, and includes the steps of: providing a substrate including at least an electronic component and a grounding area; covering the electronic component of the substrate with a molding unit; cutting out the molding unit to form a plurality of recessed spaces, wherein the recessed spaces are arranged around the electronic component and at least one of the recessed spaces is electrically connected to the grounding area of the substrate; and forming a plurality of columnar electromagnet barriers in the recessed spaces and an electromagnet barrier layer on an upper surface of the molding unit. A packaging structure of electronic components manufactured by the aforementioned method is also provided.

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Номер записи: 44
01-03-2012 дата публикации

Variable Capacitance Integrated Electronic Circuit Module

Номер: US20120052926A1
Автор: Guillaume Herault, Hervé Marie
Принадлежит: Individual

A digitally controlled variable capacitance integrated electronic circuit module ( 100 ) comprises a set of basic cells in a matrix arrangement. Each basic cell itself comprises a functional block ( 11 ) which can be switched between two individual capacitance values, a control block ( 12 ), and a control junction connecting the control block and the functional block of said basic cell. The functional blocks and the control blocks are grouped into separate regions ( 110, 120 ) of the matrix arrangement, to reduce capacitive interaction between output paths and power supply paths of the module. The functional blocks can still be switched in a winding path order within the matrix arrangement. A module of the invention can be used in an oscillator capable of producing a signal at 4 GHz.

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Номер записи: 45
08-03-2012 дата публикации

Baluns for rf signal conversion and impedance matching

Номер: US20120056297A1
Автор: Petteri Litmanen, Richard Francis Taylor, Siraj Akhtar
Принадлежит: Texas Instruments Inc

A magnetically-coupled structure is integrated with an integrated circuit in back end-of-line (BEOL) digital CMOS fabrication processes. A differential primary (or secondary) coil is formed by patterning a thick copper (Cu) metal layer, and a single-ended secondary (or primary) coil is formed by patterning a thick aluminum (Al) top metal bonding layer. Crossovers and/or cross-unders are formed using thin metal layers. One embodiment provides a stacked balun with a differential primary input winding defined in the copper layer, directly underneath a single-ended spiral winding defined in the aluminum layer. The spiral forms the single-ended secondary output of the balun and is rotated by 90° to prevent metal shorting for its cross-under connections. Another embodiment provides a transformer with one differential primary (or secondary) coil defined in the copper layer and another differential secondary (or primary) coil defined in the aluminum layer and adding a center tap. The position of the tap is selected to compensate for phase differences and provide desired balance.

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Номер записи: 46
08-03-2012 дата публикации

Semiconductor Device

Номер: US20120056298A1
Автор: Koji Kuroki
Принадлежит: Elpida Memory Inc

A semiconductor device includes a first power supply terminal, a second power supply terminal, and first and second capacitors. The first power supply terminal is configured to be supplied with a first electrical potential. The second power supply terminal is configured to be supplied with a second electrical potential. The second electrical potential is different from the first electrical potential. The first and second capacitors are coupled in series between the first and second power supply terminals.

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Номер записи: 47
08-03-2012 дата публикации

Multi-chip package with offset die stacking

Номер: US20120056335A1
Автор: Peter B. Gillingham
Принадлежит: Mosaid Technologies Inc

A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

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Номер записи: 48
15-03-2012 дата публикации

Semiconductor device and method of fabricating the same

Номер: US20120061797A1
Автор: Masahiko Kanda
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor device including a substrate, and an anti-fuse element including a first insulator formed on the substrate, a conductive film formed on the first insulator, the conductive film including a silicide film, a contact formed on the substrate, the contact being disposed adjacent to the conductive film with a second insulator interposed between the contact and the conductive film, the contact being short-circuited to the silicide film.

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Номер записи: 49
15-03-2012 дата публикации

Power Semiconductor Chip Package

Номер: US20120061812A1
Автор: Ralf Otremba
Принадлежит: INFINEON TECHNOLOGIES AG

A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad.

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Номер записи: 50
15-03-2012 дата публикации

Semiconductor device having pad structure with stress buffer layer

Номер: US20120061823A1
Автор: Chao-Wen Shih, Shang-Yun Hou, Shin-puu Jeng, Tzu-Wei Chiu, Tzuan-Horng LIU, Wei-Cheng Wu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

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Номер записи: 51
15-03-2012 дата публикации

Electronic Packaging With A Variable Thickness Mold Cap

Номер: US20120061857A1
Автор: Christopher J. Healy, Gopal C. Jha, Vivek Ramadoss
Принадлежит: Qualcomm Inc

An electronic package with improved warpage compensation. The electronic package includes a mold cap having a variable thickness. The variable thickness can have a mound or dimple design. In another embodiment, a method is provided for reducing unit warpage of an electronic package by designing the topography of a mold cap to compensate for warpage.

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Номер записи: 52
15-03-2012 дата публикации

Semiconductor package integrated with conformal shield and antenna

Номер: US20120062439A1
Автор: Chi-Hong Chan, Kuo-Hsien Liao, Shih Fuyu
Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor package integrated with conformal shield and antenna is provided. The semiconductor package includes a semiconductor element, an electromagnetic interference shielding element, a dielectric structure, an antenna element and an antenna signal feeding element. The electromagnetic interference shielding element includes an electromagnetic interference shielding film and a grounding element, wherein the electromagnetic interference shielding film covers the semiconductor element and the grounding element is electrically connected to the electromagnetic interference shielding layer and a grounding segment of the semiconductor element. The dielectric structure covers a part of the electromagnetic interference shielding element and has an upper surface. The antenna element is formed adjacent to the upper surface of the dielectric structure. The antenna signal feeding element passing through the dielectric structure electrically connects the antenna element and the semiconductor element.

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Номер записи: 53
22-03-2012 дата публикации

Electrical mask inspection

Номер: US20120068174A1
Автор: Anthony I-Chih Chou, Arvind Kumar, Shreesh Narasimha
Принадлежит: International Business Machines Corp

An apparatus and method for electrical mask inspection is disclosed. A scan chain is formed amongst two metal layers and a via layer. One of the three layers is a functional layer under test, and the other two layers are test layers. A resistance measurement of the scan chain is used to determine if a potential defect exists within one of the vias or metal segments comprising the scan chain.

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Номер записи: 54
22-03-2012 дата публикации

Massively Parallel Interconnect Fabric for Complex Semiconductor Devices

Номер: US20120068229A1
Автор: Farhang Yazdani, Majid Bemanian
Принадлежит: Individual

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

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Номер записи: 55
22-03-2012 дата публикации

Low impedance transmisson line

Номер: US20120068238A1
Автор: Baher S. Haroun, Brian P. Ginsburg, Eunyoung Seok, Srinath M. Ramaswamy, Vijay B. Rentala
Принадлежит: Texas Instruments Inc

Transmission lines employing transmission line units or elements within integrated circuits (ICs) are well-known. Typically, different heights for these transmission line units can vary the characteristics of the cell (and transmission line), and there is typically a tradeoff between impedance and space (layout) specifications. Here, a transmission line is provided, which is generally comprised of elements of the same general width, but having differing or tapered heights that allow for impedance adjustments for high frequency applications (i.e., 160 GHz). For example, a transmission line that is coupled to a balun, with the transmission line units decreasing in height near the balun's center tap to adjust the impedance of the transmission line for the balun, is shown.

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Номер записи: 56
22-03-2012 дата публикации

Semiconductor Device Comprising a Metal System Including a Separate Inductor Metal Layer

Номер: US20120068303A1
Автор: Hyung Sun Yook, Poh Ching Sim, Tsui Ping Chu
Принадлежит: Individual

In an integrated circuit an inductor metal layer is provided separately to the top metal layer, which includes the power and signal routing metal lines. Consequently, high performance inductors can be provided, for instance by using a moderately high metal thickness substantially without requiring significant modifications of the remaining metallization system.

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Номер записи: 57
22-03-2012 дата публикации

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

Номер: US20120068319A1
Автор: Daesik Choi, Oh Han Kim, SangMi Park
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

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Номер записи: 58
22-03-2012 дата публикации

Anti-tamper microchip package based on thermal nanofluids or fluids

Номер: US20120068326A1
Автор: James J. McNamara, Jr., Mark D. Poliks, Rabindra N. Das, Voya R. Markovich
Принадлежит: Endicott Interconnect Technologies Inc

A tamper-resistant microchip package contains fluid- or nanofluid-filled capsules, channels, or reservoirs, wherein the fluids, either alone or in combination, can destroy circuitry by etching, sintering, or thermally destructing when reverse engineering of the device is attempted. The fluids are released when the fluid-filled cavities are cut away for detailed inspection of the microchip. Nanofluids may be used for the sintering process, and also to increase the thermal conductivity of the fluid for die thermal management. Through-vias and micro vias may be incorporated into the design to increase circuitry destruction efficacy by improving fluid/chip contact. Thermal interface materials may also be utilized to facilitate chip cooling.

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Номер записи: 59
22-03-2012 дата публикации

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

Номер: US20120068328A1
Автор: Hin Hwa Goh, KANG Chen, Rui Huang, Xusheng Bao, Yung Kuan Hsiao
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

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Номер записи: 60
22-03-2012 дата публикации

Interconnect structure with a planar interface between a selective conductive cap and a dielectric cap layer

Номер: US20120068344A1
Автор: Elbert E. Huang, Griselda Bonilla, Lawrence A. Clevenger, Satyanarayana V. Nitta, Shom Ponoth
Принадлежит: International Business Machines Corp

A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.

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Номер записи: 61
22-03-2012 дата публикации

Structure for nano-scale metallization and method for fabricating same

Номер: US20120068346A1
Автор: Charles W. Koburger, III, Chih-Chao Yang, David V. Horak, Elbert E. Huang, Shom Ponoth, Sivananda K. Kanakasabapathy
Принадлежит: International Business Machines Corp

A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.

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Номер записи: 62
22-03-2012 дата публикации

Identification circuit and method for generating an identification bit using physical unclonable functions

Номер: US20120072476A1
Автор: Marco Bucci, Raimondo Luzzi
Принадлежит: INFINEON TECHNOLOGIES AG

An embodiment of the present invention is an identification circuit installed on an integrated circuit for generating an identification bit, comprising a first circuit to generate a first output signal that is based on random parametric variations in said first circuit, a second circuit to generate a second output signal that is based on random parametric variations in said second circuit, a third circuit capable to be operated in an amplification mode and in a latch mode, wherein in said amplification mode the difference between the first output signal and the second output signal is amplified to an amplified value and, wherein in said latch mode said amplified value is converted into a digital signal.

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Номер записи: 63
29-03-2012 дата публикации

Semiconductor package with through electrodes and method for manufacturing the same

Номер: US20120074529A1
Автор: Jin-Ho Bae, Ki-Young Kim, Myung-Geun PARK
Принадлежит: Hynix Semiconductor Inc

A semiconductor package may include a substrate with a first surface over which bond fingers are formed. At least two semiconductor chips may be stacked on the first surface of the substrate and each chip may have via holes. The semiconductor chips may be stacked such that the respective via holes expose the respective bond fingers of the substrate. Through electrodes may be formed in the via holes. The through electrodes may comprise carbon nanotubes grown from the exposed bond fingers of the substrate, where the through electrodes may be electrically connected with the semiconductor chips.

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Номер записи: 64
29-03-2012 дата публикации

Interposer including air gap structure, methods of forming the same, semiconductor device including the interposer, and multi-chip package including the interposer

Номер: US20120074530A1
Автор: Chang-Hyun Kim, Kyung-Ho Kim
Принадлежит: Individual

Example embodiments of the present invention relate to an interposer of a semiconductor device having an air gap structure, a semiconductor device using the interposer, a multi-chip package using the interposer and methods of forming the interposer. The interposer includes a semiconductor substrate including a void, a metal interconnect, provided within the void, thereby forming an air gap insulating the metal interconnect. The metal interconnect may be connected to a contact element, and may be maintained within the air gap using the contact element.

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Номер записи: 65
29-03-2012 дата публикации

Semiconductor device

Номер: US20120074542A1
Автор: Shin Soyano
Принадлежит: Fuji Electric Co Ltd

A semiconductor device, in which a control circuit board is mountable outside a sheath case and a power semiconductor element is placeable inside the sheath case, includes a metal step support, a shield plate and a metal ring. The support includes a base portion implanted in the sheath case, a connection portion which extends from an end of the base portion, and a step portion formed at a boundary between the base portion and the connection portion. The shield plate is disposed over the step portion such that the connection portion of the support pierces the shield plate. An end of the metal ring protrudes from an end of the connection portion over the shield plate. The semiconductor device is adapted such that the control circuit board is mounted over the protruded end of the metal ring and is fixed onto the connection portion by an engagement member.

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Номер записи: 66
29-03-2012 дата публикации

Semiconductor structure and method for making same

Номер: US20120074572A1
Автор: Andreas STUECKJUERGEN, Juergen Foerster, Thomas Fischer, Werner Robl
Принадлежит: INFINEON TECHNOLOGIES AG

One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

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Номер записи: 67
29-03-2012 дата публикации

Integrated circuit packaging system with warpage control and method of manufacture thereof

Номер: US20120074588A1
Автор: Hin Hwa Goh, KANG Chen, Rui Huang, Xusheng Bao, Yung Kuan Hsiao
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.

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Номер записи: 68
29-03-2012 дата публикации

Corner structure for ic die

Номер: US20120074589A1
Автор: David M. Mahoney, Mohsen H. Mardi
Принадлежит: Xilinx Inc

One or more integrated circuit chips are flip-chip bonded to a first surface of a substrate. A contact array is fabricated on a second surface of the substrate. Corner structures attached to the integrated circuit chip cover at least two corners of the IC chip.

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Номер записи: 69
29-03-2012 дата публикации

Integrated circuit packaging system with a shield and method of manufacture thereof

Номер: US20120075821A1
Автор: Reza Argenty Pagaila
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a first integrated circuit over the substrate; forming an encapsulant around the first integrated circuit and over the substrate; and forming a shield structure within and over the encapsulant while simultaneously forming a vertical interconnect structure.

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Номер записи: 70
29-03-2012 дата публикации

DRAWN DUMMY FeCAP, VIA AND METAL STRUCTURES

Номер: US20120077287A1
Автор: Rajni J. Aggarwal, Scott R. Summerfelt
Принадлежит: Texas Instruments Inc

A process of forming an integrated circuit containing matching components with identical layouts and hydrogen permeable dummy vias in identical configurations over the matching components.

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Номер записи: 71
29-03-2012 дата публикации

High-voltage tolerant voltage regulator

Номер: US20120077551A1
Автор: Florinel G. Balteanu, Jakub F. Pingot, Peter Harris Robert Popplewell
Принадлежит: Skyworks Solutions Inc

Circuits and methodologies related to high-voltage tolerant regulators are disclosed. In some implementations, a voltage regulator can be configured to be capable of being in a regulating state and a bypass state. In the regulating state, an input voltage greater than a selected value can be regulated so as to yield a desired output voltage such as a substantially constant voltage. In the bypass state, an input voltage at or less than the selected value can be regulated so as to yield an output voltage that substantially tracks the input voltage. Such a capability of switching between two modes can provide advantageous features such as reducing the likelihood of damage in a powered circuit due to high input voltage, and extending the operating duration of a power source such as a rechargeable battery. Also disclosed are examples of how the foregoing features can be implemented in different products and methods of operation and fabrication.

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Номер записи: 72
05-04-2012 дата публикации

Device

Номер: US20120080796A1
Автор: Makoto Wada, Yuichi Yamazaki
Принадлежит: Toshiba Corp

According to one embodiment, a device includes an insulating layer with a first trench, a first interconnect layer in the first trench, the first interconnect layer including copper and includes a concave portion, and a first graphene sheet on an inner surface of the concave portion.

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Номер записи: 73
05-04-2012 дата публикации

Off-chip vias in stacked chips

Номер: US20120080807A1
Автор: Belgacem Haba, David Ovrutsky, Ilyas Mohammed, Laura Wills Mirkarimi, Vage Oganesian
Принадлежит: Tessera LLC

A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

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Номер записи: 74
05-04-2012 дата публикации

Chip Capacitor Precursors

Номер: US20120081832A1
Автор: Azuma Chikara
Принадлежит: Texas Instruments Inc

A capacitive precursor includes electrically conductive material layers stacked on a substrate. The electrically conductive layers provide first and second patterns. The patterns each include overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. Dielectric layers are interposed between neighboring electrically conductive material layers for electrical isolation. One or more capacitive precursors can be dropped onto or into a board and during assembly of a packaged semiconductor device and have electrically conducting layers associated with its respective plates connected together to form a capacitor during assembly using conventional assembly steps.

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Номер записи: 75
05-04-2012 дата публикации

Method for manufacturing a semiconductor device having an interconnect structure and a reinforcing insulating film

Номер: US20120083115A1
Автор: Tatsuya Usami
Принадлежит: Renesas Electronics Corp

A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first interconnect, a conductive first plug provided on the upper portion of the Cu silicide layer and connected to the first interconnect, a Cu silicide layer covering the upper portion of the first plug, a first porous MSQ film provided over the side wall from the first interconnect through the first plug and formed to cover the side wall of the first interconnect, the upper portion of the first interconnect, and the side wall of the first plug, and a first SiCN film disposed under the first porous MSQ film to contact with the lower portion of the side wall of the first interconnect and having the greater film density than the first porous MSQ film.

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Номер записи: 76
12-04-2012 дата публикации

Wiring board and method for manufacturing the same

Номер: US20120085572A1
Автор: Shunsuke Sakai
Принадлежит: Ibiden Co Ltd

A wiring board including a core substrate having an accommodation portion, an electronic component in the accommodation portion having a substrate, a resin layer on a surface of the substrate and an electrode on the resin layer, a first interlayer resin insulation layer on a surface of the core substrate and a surface of the substrate of the component, and a second interlayer resin insulation layer on the opposite surface of the core substrate and a surface of the substrate having the resin layer and electrode. The first insulation layer has resin in the amount greater than the amount of resin in the second insulation layer such that the total amount of resin component including the resin in the first insulation layer is adjusted to be substantially the same as the total amount of resin component including the resin in the second insulation layer and resin in the resin layer.

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Номер записи: 77
12-04-2012 дата публикации

Semiconductor device and test system for the semiconductor device

Номер: US20120086003A1
Автор: Sung-Kyu Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package including a stress mitigation unit that mitigates stress to the semiconductor chip. The semiconductor package includes a substrate, a semiconductor chip on the substrate, an encapsulation member formed on the substrate and covering the first semiconductor chip, and the stress mitigation unit mitigating stress from a circumference of the first semiconductor chip to the first semiconductor chip. The stress mitigation unit includes at least one groove formed in the encapsulation member.

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Номер записи: 78
12-04-2012 дата публикации

Integrated Circuits with Magnetic Core Inductors and Methods of Fabrications Thereof

Номер: US20120086102A1
Автор: Alexander Glas, Carsten Ahrens, Renate Hofmann, Wolfgang Klein
Принадлежит: INFINEON TECHNOLOGIES AG

In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil.

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Номер записи: 79
12-04-2012 дата публикации

Package with embedded chip and method of fabricating the same

Номер: US20120086117A1
Автор: Chiang-Cheng Chang, Hsin-Yi Liao, Shih-Kuang Chiu
Принадлежит: Siliconware Precision Industries Co Ltd

A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.

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Номер записи: 80
12-04-2012 дата публикации

Package systems and manufacturing methods thereof

Номер: US20120086127A1
Автор: Chia-Pao SHU, Chun-Wen Cheng, Hsin-Ting HUANG, Jung-Huei Peng, Kuei-Sung CHANG, Shang-Ying Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

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Номер записи: 81
12-04-2012 дата публикации

Transmissive liquid-crystal display in cmos technology with auxiliary storage capacitor

Номер: US20120086683A1
Автор: Josep Segura Puchades
Принадлежит: Commissariat a lEnergie Atomique et aux Energies Alternatives CEA

Techniques for displaying images with an active-matrix liquid-crystal display. These techniques are particularly applicable to small displays, produced, for example, on silicon substrates (in LCOS, or liquid-crystal on silicon, technology). An auxiliary storage capacitor is formed on the drive transistor of a pixel, such that the drive transistor is formed between the liquid crystal and the storage capacitor. The capacitor includes multiple parallel partial capacitors each having an interdigitated structure in a respective metallization level. The metallizations (aluminum and/or copper) are opaque and the capacitor therefore protects the transistor from light, the level of protection being increased with the number of metallization levels used to form the interdigitated structures.

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Номер записи: 82
12-04-2012 дата публикации

Integrated circuit tampering protection and reverse engineering prevention coatings and methods

Номер: US20120088338A1
Автор: Alan P. Boone, Nathan P. Lower, Ross K. Wilcoxon
Принадлежит: ROCKWELL COLLINS INC

A method of protecting an electronics package is discussed along with devices formed by the method. The method involves providing at least one electronic component that requires protecting from tampering and/or reverse engineering. Further, the method includes mixing into a liquid glass material at least one of high durability micro-particles or high-durability nano-particles, to form a coating material. Further still, the method includes depositing the coating material onto the electronic component and curing the coating material deposited.

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Номер записи: 83
19-04-2012 дата публикации

Non-volatile memory device and methods for manufacturing the same

Номер: US20120091424A1
Автор: Chrong-Jung Lin, Ya-Chin King
Принадлежит: Individual

A variable and reversible resistive element includes a transition metal oxide layer, a bottom electrode and at least one conductive plug module. The bottom electrode is disposed under the transition metal oxide layer. The conductive plug module is disposed on the transition metal oxide layer. The conductive plug module includes a metal plug and a barrier layer. The conductive plug is electrically connected with the transition metal oxide layer. The barrier layer surrounds the metal plug, wherein the transition metal oxide layer is made by reacting a portion of a dielectric layer being directly below the metal plug and a portion of the barrier layer contacting the portion of the dielectric layer, wherein the dielectric layer is formed on the bottom electrode. Moreover, a non-volatile memory device and methods for operating and manufacturing the same is disclosed in specification.

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Номер записи: 84
19-04-2012 дата публикации

Scratch protection for direct contact sensors

Номер: US20120091517A1
Автор: Danielle A. Thomas
Принадлежит: Individual

In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum, and at least as great as the lowest hardness for any interlevel dielectric or passivation material employed.

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Номер записи: 85
19-04-2012 дата публикации

Method for Detecting the Repackaging of an Integrated Circuit after it has been Originally Packaged, and Corresponding Integrated Circuit

Номер: US20120091553A1
Автор: Christian Rivero, Pascal Fornara
Принадлежит: STMICROELECTRONICS ROUSSET SAS

An integrated circuit includes active circuitry disposed at a surface of a semiconductor body and an interconnect region disposed above the semiconductor body. A thermoelectric material is disposed in an upper portion of the interconnect region away from the semiconductor body. The thermoelectric material is configured to deliver electrical energy when exposed to a temperature gradient. This material can be used, for example, in a method for detecting the repackaging of the integrated circuit after it has been originally packaged.

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Номер записи: 86
26-04-2012 дата публикации

Bond pad for wafer and package for cmos imager

Номер: US20120098105A1
Автор: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Richard L. Rassel
Принадлежит: International Business Machines Corp

An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.

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Номер записи: 87
26-04-2012 дата публикации

Chip package and manufacturing method thereof

Номер: US20120098109A1
Автор: Dongkyun Ko, Jaesun An, Jung Lee
Принадлежит: Individual

A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.

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Номер записи: 88
26-04-2012 дата публикации

Conductive feature for semiconductor substrate and method of manufacture

Номер: US20120098121A1
Автор: Hsien-Wei Chen, Ying-Ju Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

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Номер записи: 89
26-04-2012 дата публикации

Power/ground layout for chips

Номер: US20120098127A1
Автор: Albert Wu, Chuan-Cheng Cheng, Chung Chyung Han, Sehat Sutardja, Shuhua Yu, Weidan Li
Принадлежит: MARVELL WORLD TRADE LTD

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

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Номер записи: 90
26-04-2012 дата публикации

Chip structure and process for forming the same

Номер: US20120098128A1
Автор: Ching-Cheng Huang, Jin-Yuan Lee, Mou-Shiung Lin
Принадлежит: Megica Corp

A chip with a metallization structure and an insulating layer with first and second openings over first and second contact points of the metallization structure, a first circuit layer connecting the first and second contact points and comprising a first trace portion, first and second via portions between the first trace portion and the first and second contact points, the first circuit layer comprising a copper layer and a first conductive layer under the copper layer and at a sidewall of the first trace portion, and a second circuit layer comprising a second trace portion with a third via portion at a bottom thereof, wherein the second circuit layer comprises another copper layer and a second conductive layer under the other copper layer and at a sidewall of the second trace portion, and a second dielectric layer comprising a portion between the first and second circuit layers.

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Номер записи: 91
26-04-2012 дата публикации

Resistive element and manufacturing method therefor

Номер: US20120098635A1
Автор: Keita Kumamoto
Принадлежит: Renesas Electronics Corp

A higher precision resistive element suppresses variation of the resistance value due to variation of film thickness. A resistive element includes a first portion having a first film thickness and a first width, and a second portion having the first film thickness and a second width determined by the first width. The sum of the first and second widths is constant. The first portion has an upper surface at a position at which a height from the bottom surface of the resistive element first portion is a first height. The resistive element second portion has an upper surface of the resistive element second portion at a position at which a height from a surface including the bottom surface of the resistive element first portion is the first height. The resistive element first portion and the resistive element second portion are coupled to each other via a coupling portion.

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Номер записи: 92
26-04-2012 дата публикации

Method of manufacturing semiconductor device, apparatus for manufacturing same, and storage medium

Номер: US20120100727A1
Автор: Sumie Nagaseki
Принадлежит: Tokyo Electron Ltd

A method of manufacturing a semiconductor device includes steps of: generating positively or negatively charged fine bubbles having substantially zero buoyancy in a coating solution as an insulating film forming material; coating the coating solution including the bubbles on a substrate to form a coating film; and baking the coating film by heating the substrate before the bubbles are removed to obtain a porous low dielectric constant insulating film.

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Номер записи: 93
03-05-2012 дата публикации

Device and method for mounting electronic components

Номер: US20120102726A1
Автор: Hideki Sumi, Kenichi Kaida, Kenichirou Ishimoto, Masahiro Kihara, Noboru Higashi
Принадлежит: Panasonic Corp

An object is to provide an electronic component mounting method in which an adequate component mounting work to which a check result is correctly reflected is enabled and it is possible to satisfy both reduction of the failure occurrence rate and improvement of the working efficiency. An electronic component mounting apparatus in which an appearance checking section which checks a board to detect existence or non-existence of a failure item, and a component mounting section which transfers and mounts an allocated mounting object component to the board in which the check is ended are integrally disposed includes a mounting availability determination processing section 28 d which determines an availability of an execution of an operation of mounting the mounting object component, based on a result of detection of a failure item. In a mounting availability determining process, an availability of an execution of a mounting operation for the mounting object component is automatically determined based on preset failure patterns of the detection result.

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Номер записи: 94
03-05-2012 дата публикации

Semiconductor Device Having Island Type Support Patterns

Номер: US20120104559A1
Автор: Hyun-Chul Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a plurality of cylindrical structures arranged in a first direction and a second direction, and a plurality of unit regions formed in the first direction and the second direction, each of the plurality of unit regions including an island type support pattern supporting the plurality of cylindrical structures contacting side surfaces of the plurality of cylindrical structures and an open region exposing the side surfaces of the plurality of cylindrical structures.

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Номер записи: 95
03-05-2012 дата публикации

Semiconductor package and manufacturing method thereof

Номер: US20120104571A1
Автор: Jin O. YOO
Принадлежит: Samsung Electro Mechanics Co Ltd

There are provided a semiconductor package including an electromagnetic shielding structure having excellent electromagnetic interference (EMI) and electromagnetic susceptibility (EMS) characteristics, while protecting individual elements in an inner portion thereof from impacts, and a manufacturing method thereof. The semiconductor package includes: a substrate having ground electrodes formed on an upper surface thereof; at least one electronic component mounted on the upper surface of the substrate; an insulating molding part including an internal space in which the electronic component is accommodated, and fixed to the substrate such that at least a portion of the ground electrode is externally exposed; and a conductive shield part closely adhered to the molding part to cover an outer surface of the molding part and electrically connected to the externally exposed ground electrodes.

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Номер записи: 96
03-05-2012 дата публикации

Semiconductor package module

Номер: US20120104572A1
Автор: Jin O. YOO
Принадлежит: Samsung Electro Mechanics Co Ltd

There is provided a semiconductor package module capable of minimizing a thickness of the module in spite of including an electronic element having a large size. The semiconductor package module includes: a semiconductor package having a shield formed on an outer surface and a side thereof and at least one receiving part provided in a lower surface thereof, the receiving part having a groove shape; and a main substrate having at least one large element and the semiconductor package mounted on one surface thereof, wherein the large element is received in the receiving part of the semiconductor package and is mounted on the main substrate.

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Номер записи: 97
03-05-2012 дата публикации

Semiconductor module

Номер: US20120104631A1
Автор: Nam-Seog Kim, Seung-Duk Baek, Sun-Won Kang, Tae-Gyeong Chung, Young-hee Song
Принадлежит: Individual

A semiconductor module may include a circuit substrate with a first die on the circuit substrate and a second die on the first die. The first die may include at least one first data input/output pad on a first peripheral portion of the first die and at least one first control/address pad on a third peripheral portion, the third peripheral portion being separate from the first peripheral portion of the first die. The second die may include at least one second data input/output pad on a second peripheral portion and at least one second control/address pad on a fourth peripheral portion. The second peripheral portion of the second die is not overlapped with the first peripheral portion of the first die in plan view. The fourth peripheral portion of the second die overlaps at least a portion of the third peripheral portion of the first die.

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Номер записи: 98
03-05-2012 дата публикации

Thermal Power Plane for Integrated Circuits

Номер: US20120105145A1
Автор: Andreas Huber, Bruno Michel, Harry Barowski, Hubert Harrer, Jochen Supper, Stephan Paredes, Thomas Brunschwiler, Tim Niggemeier
Принадлежит: International Business Machines Corp

A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

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Номер записи: 99
03-05-2012 дата публикации

Solid-state imaging device, semiconductor device, manufacturing methods thereof, and electronic apparatus

Номер: US20120105696A1
Автор: Keiichi Maeda
Принадлежит: Sony Corp

A solid-state imaging device includes an imaging element and a logic element. The imaging element includes a first semiconductor substrate, a first wiring layer, and a first metal layer, in which a pixel region which is a light sensing surface is formed. The logic element includes a second semiconductor substrate, a second wiring layer, and a second metal layer, in which a signal processing circuit that processes a pixel signal obtained at the pixel region is formed. The logic element is laminated to the imaging element so that the first metal layer and the second metal layer are bonded to each other, and the first metal layer and the second metal layer are formed on a region excluding a region in which a penetrating electrode layer penetrating a bonding surface of the imaging element and the logic element is formed.

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Номер записи: 100