SELECTIVE ION FILTERING IN A MULTIPURPOSE CHAMBER

A multipurpose semiconductor process chamber includes a vessel wall that encloses contiguous first and second volumes of the multipurpose chamber, and means for selectively effectively preventing ions moving across a plane that partitions the first volume from the second volume. For example, the means can include an electromagnet, or at least one permanent magnet, that is operable to impose and remove a magnetic field with field lines extending in the plane.

ADVANCED METAL INSULATOR METAL CAPACITOR

A method for fabricating an advanced metal insulator metal capacitor structure includes providing a pattern in a dielectric layer. The pattern includes a set of features in the dielectric layer. A first metal layer is deposited in the set of features in the dielectric layer. A phase change material layer is deposited over the metal layer in the set of features in the dielectric layer. The phase change material is an alloy of tantalum and nitrogen and is an insulator in a deposited state. A surface treatment process is performed on the phase change layer to produce a top surface layer having electrically conductive properties. A second metal layer is deposited on the top surface layer of the phase change layer. In another aspect of the invention, a device is produced using the method.

Low resistance contact structures including a copper fill for trench structures

An electrical device is provided that includes at least one contact surface and an interlevel dielectric layer present atop the electrical device. The interlevel dielectric layer may include at least one trench to the at least one contact surface of the electrical device. A liner of tantalum or tantalum nitride can be present on sidewalls of the trench structure and a base surface of the trench provided by the contact surface of the electrical device. A copper fill promoting liner that includes at least one ruthenium (Ru), rhodium (Rh), iridium (Ir), osmium (Os), molybdenum (Mo), and copper (Cu) may be in direct contact with the liner of tantalum or tantalum nitride. A copper containing metal that fills the at least one trench and is present directly on the copper fill promoting liner.

Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer

Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

Sub-lithographic semiconductor structures with non-constant pitch

Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.

Structure to improve adhesion between top CVD low-K dielectric and dielectric capping layer

An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.

CONDUCTOR-DIELECTRIC STRUCTURE AND METHOD FOR FABRICATING

A conductor-dielectric interconnect structure is fabricated by providing a structure comprising a dielectric layer having a patterned feature therein; depositing a plating seed layer on the dielectric layer in the patterned feature; depositing a sacrificial seed layer on the plating seed layer in the via; reducing the thickness of the sacrificial seed layer by reverse plating; and plating a conductive metal on the sacrificial seed layer in the patterned feature. Also provided is a dielectric layer having a via therein; a plating seed layer on the dielectric layer in the patterned feature; and a discontinuous sacrificial seed layer located in the patterned feature.

Method of patterning damascene structure in integrated circuit design

Disclosed is a method that deposits an aqueous material having a pH between approximately 10 and 11 in a first opening and on an oxide hard mask, deposits an organic material on the aqueous material, and patterns a photoresist over the organic material. The invention then etches the organic material and the aqueous material through the photoresist to form a second opening above the first opening and forms a polymer along sidewalls of the second opening. The invention can then perform a wet cleaning process using an alkali solution having a pH between approximately 10 and 11 to remove the aqueous material from the first opening. By utilizing an alkali aqueous (water-based) material having a pH of approximately 10-11, the invention can use a fairly low pH wet etch (pH of approximately 10-11) to completely remove the aqueous solution from the via, thereby eliminating the conventional problem of having residual organic material left within the via.

Size-filtered multimetal structures

A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.

COPPER INTERCONNECT STRUCTURES AND METHODS OF MAKING SAME

A structure and method of making the structure. The structure includes a dielectric layer on a substrate; a first wire formed in a first trench in the dielectric layer, a first liner on sidewalls and a bottom of the first trench and a first copper layer filling all remaining space in the first trench; a second wire formed in a second trench in the dielectric layer, a second liner on sidewalls and a bottom of the second trench and a second copper layer filling all remaining space in the second trench; and an electromigration stop formed in a third trench in the dielectric layer, a third liner on sidewalls and a bottom of the third trench and a third copper layer filling all remaining space in the third trench, the electromigration stop between and abutting respective ends of the first and second wires.

Hybrid interconnects and method of forming the same

A method for manufacturing a semiconductor device includes forming a trench in at least one dielectric layer; and forming an interconnect structure in the trench, wherein forming the interconnect structure includes forming a first conductive layer on a bottom surface of the trench, and partially filling the trench, and forming a second conductive layer on the first conductive layer, and filling a remaining portion of the trench, wherein the second conductive layer comprises a different material from the first conductive layer, and wherein an amount of the first conductive layer in the trench is controlled so that an aspect ratio of the second conductive layer has a value that is determined to result in columnar grain boundaries in the second conductive layer.

Metal bonding pads for packaging applications

Methods and semiconductor devices for bonding a first semiconductor device to a second semiconductor device include forming metal pads including a textured microstructure having a columnar grain structure at substantially the same angular direction from the top surface to the bottom surface. The textured crystalline microstructures enables the use of low temperatures and low pressures to effect bonding of the metal pads. Also described are methods of packaging and semiconductor devices.

Grain growth promotion layer for semiconductor interconnect structures

An interconnect structure of the single or dual damascene type and a method of forming the same, which substantially reduces the electromigration problem that is exhibited by prior art interconnect structures, are provided. In accordance with the present invention, a grain growth promotion layer, which promotes the formation of a conductive region within the interconnect structure that has a bamboo microstructure and an average grain size of larger than 0.05 microns is utilized. The inventive structure has improved performance and reliability.

Metal interconnect structures with self-forming sidewall barrier layer

BEOL and MOL interconnect structures with a self-forming sidewall barrier layer are provided. In one aspect, a method of forming an interconnect structure includes: patterning a feature(s) in a dielectric; selectively forming a metal layer at a bottom of the at least one feature; depositing a liner layer lining the feature(s), wherein the conformal liner layer includes a metal alloy AB; depositing a metal onto the liner layer to form the interconnect structure; and annealing the interconnect structure under conditions sufficient to form a barrier layer including the component B along vertical sidewalls of the feature(s). A method of forming an interconnect structure including a via and a trench on top of the via is also provided, as is an interconnect structure.

Cobalt contact and interconnect structures

Methods and structures for forming cobalt contact and/or cobalt interconnects includes depositing a stress control layer onto the cobalt layer prior to annealing after which the stress control layer can be removed. The stress control layer prevents formation of defects that can occur in the absence of the stress control layer.

METAL FINFET ANTI-FUSE

Semiconductor structures containing FinFET anti-fuses with reduced breakdown voltage are provided which can be readily integrated with high performance FinFETs. The anti-fuse includes at least one metal structure having a faceted sidewall. The sharp corner of the faceted sidewall of the at least one metal structure causes an electric field concentration, thus reducing the breakdown voltage of the anti-fuse.

ULTRA-THIN METAL WIRES FORMED THROUGH SELECTIVE DEPOSITION

The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a pair of ultra-thin metal wires in an opening using a selective deposition process.

VERTICAL FUSE STRUCTURES

Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein the vertical fuse devices are formed as part of a process flow for fabricating the FINFET devices. For example, a semiconductor device comprises first and second vertical semiconductor fins, a vertical fuse device, and a FINFET device. The vertical fuse device comprises a metal fuse element formed over a portion of the first vertical semiconductor fin, and the FINFET device comprises a metal gate electrode formed over a portion of the second vertical semiconductor fin. The metal fuse element and the metal gate electrode are concurrently formed as part of a replacement metal gate process flow.

HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT

A method of forming a hybrid interconnect structure including dielectric spacers is provided. The method includes forming at least one opening in a dielectric material utilizing a patterned hard mask located on a surface of the dielectric material as a mask, wherein an undercut is present beneath said patterned hard mask. Next, a dense dielectric spacer is formed in the at least one opening and at least partially on exposed sidewalls of the dielectric material. A diffusion barrier and a conductive material are then formed within the at least one opening. 1. A method of forming an interconnect structure comprising:forming at least one opening in a dielectric material utilizing a patterned hard mask located on a surface of said dielectric material as a mask, wherein an undercut is present beneath said patterned hard mask;forming a dense dielectric spacer in said at least one opening and at least partially on exposed sidewalls of said dielectric material;forming a diffusion barrier within said at least one opening on at least said dense dielectric spacer; andforming a conductive material within said at least one opening on said diffusion barrier.2. The method of wherein during said forming the dense dielectric spacer an air gap remains in the undercut.3. The method of wherein said dense dielectric spacer is formed by deposition of a dense dielectric liner and anisotropic etching.4. The method of further comprising forming a plating seed layer on said diffusion barrier and said forming said conductive material is by plating.5. The method of wherein said forming the at least one opening includes lithography and etching claim 1 , said etching forms said undercut and said at least one opening includes a via opening claim 1 , a line opening or a combined line and via opening.6. The method of wherein said forming said diffusion barrier is performed by atomic layer deposition (ALD) claim 1 , chemical vapor deposition (CVD) claim 1 , plasma enhanced chemical vapor deposition ( ...

METALLIC INTERCONNECT STRUCTURES WITH WRAP AROUND CAPPING LAYERS

Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect.

STRUCTURE FOR NANO-SCALE METALLIZATION AND METHOD FOR FABRICATING SAME

A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.

Pre-patterned etch stop for interconnect trench formation overlying embedded MRAM structures

Integration of structures including an embedded magnetoresistive random access memory (MRAM) device such as a magnetic tunneling junction device includes pre-patterned etch stop layers to prevent excessive etching of the interlayer dielectric during a via open step.

MAGNETIC TUNNEL JUNCTION WITH AN ETCHED BOTTOM ELECTRODE HAVING NON-PLANAR SIDEWALLS

Embodiments of the invention are directed to a structure comprising a magnetic tunnel junction (MTJ) element and an etched bottom electrode (BE) communicatively coupled to the MTJ element. The etched BE includes a substantially non-planar BE sidewall.

HIGH-DENSITY MEMORY DEVICES USING OXIDE GAP FILL

A semiconductor structure forms two or more tightly pitched memory devices using a dielectric material for a gap fill material. The approach includes providing two adjacent bottom electrodes in a layer of an insulating material and above a metal layer. Two adjacent pillars are each above one of the two adjacent bottom electrodes where each pillar of the two adjacent pillars is composed of a stack of materials for a memory device. A spacer is around the vertical sides each of the two adjacent pillars. The dielectric material is on the spacer around the vertical sides each of the two adjacent pillars, on the layer of the insulating material between the two adjacent bottom electrodes. The dielectric material fills at least a first portion of a gap between the two adjacent pillars. A low k material covers the dielectric material and exposed portions of the layer of the insulating material.

CONTACT STRUCTURE FORMATION FOR MEMORY DEVICES

A semiconductor structure comprises a memory device comprising a first electrode, at least one memory element layer disposed on the first electrode, and a second electrode disposed on the at least one memory element layer. An encapsulation layer is disposed around side surfaces of the memory device. The semiconductor structure also comprises a conductive cap layer disposed on a top surface of the encapsulation layer and around a portion of side surfaces of the encapsulation layer. A contact is disposed on the second electrode and extends around the side surfaces of the memory device.

ALIGNMENT MARK FOR BACK SIDE POWER CONNECTIONS

A semiconductor device is provided. The semiconductor device includes a first source/drain of a first semiconductor device, and a second source/drain of a second semiconductor device. The semiconductor device further includes a source/drain contact adjoining a first side of the first source/drain, a frontside via adjoining the source/drain contact, and a backside electric contact adjoining a first side of the second source/drain, wherein the backside electric contact is on a side opposite the source/drain contact, and a conductive alignment region. The device further includes a backside interconnect electrically connected to the conductive alignment region, wherein the backside interconnect is on the same side of the first and second source/drain as the backside electric contact, and an alignment region via electrically connected to the conductive alignment region, wherein the alignment region via is on the same side of the first and second source/drain as the source/drain contact and frontside ...

Bottom-up metal gate formation on replacement metal gate finfet devices

BORDERLESS CONTACT STRUCTURE EMPLOYING DUAL ETCH STOP LAYERS

Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed.

Controlled Ion Beam Etch of MTJ

Controlled IBE techniques for MRAM stack patterning are provided. In one aspect, a method of forming an MRAM device includes: patterning an MRAM stack disposed on a dielectric into individual memory cells using IBE landing on the dielectric while dynamically adjusting an etch time to compensate for variations in a thickness of the MRAM stack, wherein each of the memory cells includes a bottom electrode, an MTJ, and a top electrode; removing foot flares from the bottom electrode of the memory cells which are created during the patterning of the MRAM stack; removing residue from sidewalls of the memory cells which includes metal redeposited during the patterning of the MRAM stack and during the removing of the foot flares; and covering the memory cells in a dielectric encapsulant. An MRAM device is also provided.

Metallization interconnect structure formation

Techniques for fabricating a metallic interconnect include forming a first metallization layer that includes a first dielectric layer, a first metallic layer formed in the first dielectric layer and a first capping layer formed on the first dielectric layer and the first metallic layer and forming a second metallization layer that includes a second dielectric layer, a second metallic layer formed in the second dielectric layer and a second capping layer formed on the second dielectric layer and the second metallic layer. A channel is etched in the second capping layer, second dielectric layer, and first capping layer that exposes a portion of the first metallic layer and a portion of the second metallic layer. A metallic interconnect structure is formed in the channel in contact with the exposed portion of the first metallic layer and the exposed portion of the second metallic layer.

Method of forming via contact with resistance control

A first dielectric layer on a substrate is provided. The first dielectric layer has a first level metal line embedded in the dielectric. An opposite gouging feature is created in a top surface of the first level metal line. The opposite gouging feature has a protuberant shape relative to the first level metal line. A second dielectric layer is formed over the first dielectric layer. A compound recess is formed in the second dielectric layer. A first portion of the recess is for a via connector positioned over the opposite gouging feature. A second portion of the recess for a second level metal line. In another aspect of the invention, a device is produced using the method.

ELECTRICAL PROGRAMMABLE METAL RESISTOR

The present invention provides an electrical programmable metal resistor and a method of fabricating the same in which electromigration stress is used to create voids in the structure that increase the electrical resistance of the resistor. Specifically, a semiconductor structure is provided that includes an interconnect structure comprising at least one dielectric layer, wherein said at least one dielectric layer comprises at least two conductive regions and an overlying interconnect region embedded therein, said at least two conductive regions are in contact with said overlying interconnect region by at least two contacts and at least said interconnect region is separated from said at least one dielectric layer by a diffusion barrier, wherein voids are present in at least the interconnect region which increase the electrical resistance of the interconnect region.

Apparatus and Method of Intelligent Multistage System Deactivation

A deactivation management unit for facilitating an intelligent multistage system deactivation process where the deactivation management unit is flexible, facilitates recovery, and renders reverse engineering nearly impossible after the system has been permanently deactivated.

Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures

Embodiments of the invention generally relate to semiconductor devices and more specifically to forming partially silicided and fully silicided structures. Fabricating the partially silicided and fully silicided structures may involve creating one or more gate stacks. A polysilicon layer of a first gate stack may be exposed and a first metal layer may be deposited thereon to create a partially silicided structure. Thereafter, a polysilicon layer of a second gate stack may be exposed and a second metal layer may be deposited thereon to form a fully silicided structure. In some embodiments, the polysilicon layers of one or more gate stacks may not be exposed, and resistors may be formed with the unsilicided polysilicon layers.

Drive-in Mn Before Copper Plating

Techniques for forming Cu interconnects in a dielectric are provided. In one aspect, a method of forming a Cu interconnect structure includes: forming at least one trench in a dielectric; depositing a metal liner into the trench; depositing a Mn-containing seed layer on the metal liner within the trench; annealing the Mn-containing seed layer under conditions sufficient to diffuse Mn from the Mn-containing seed layer to an interface between the dielectric and the metal liner forming a barrier layer between the dielectric and the metal liner; and depositing Cu into the trench to form the Cu interconnect, wherein the Cu is deposited into the trench after the annealing is performed. The metal liner may optionally be reflowed such that it is thicker at a bottom of the trench than along sidewalls of the trench. A Cu interconnect structure is also provided.

Method to generate porous organic dielectric

The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas ...

VOID-FREE METALLIC INTERCONNECT STRUCTURES WITH SELF-FORMED DIFFUSION BARRIER LAYERS

Methods are provided for fabricating void-free metallic interconnect structures with self-formed diffusion barrier layers. A seed layer is deposited to line an etched opening in a dielectric layer. A metallic capping layer is selectively deposited on upper portions and upper sidewall surfaces of the seed layer which define an aperture into the etched opening. An electroplating process is performed to plate metallic material on exposed surfaces of the seed layer within the etched opening, which are not covered by the capping layer to form a metallic interconnect. The capping layer prohibits plating of metallic material on the capping layer and closing the aperture before the electroplating process is complete. A thermal anneal process is performed to cause the metallic material of the metallic capping layer to diffuse though the metallic interconnect and create a self-formed diffusion barrier layer between the metallic interconnect and the surfaces of the etched opening.

BARRIER LAYERS IN TRENCHES AND VIAS

A method of forming a semiconductor structure includes forming at least one trench in a dielectric layer, forming a barrier layer on a bottom of said at least one trench, sidewalls of said at least one trench and a top surface of the dielectric layer, the barrier layer having a non-uniform thickness, and selectively thinning at least a first portion of the barrier layer using one or more cycles comprising forming an oxidized layer in the first portion of the barrier layer using a neutral beam oxidation and removing the oxidized layer using an etching process. 1. A method of forming a semiconductor structure , comprising:forming at least one trench in a dielectric layer;forming a barrier layer on a bottom of said at least one trench, sidewalls of said at least one trench and a top surface of the dielectric layer, the barrier layer having a non-uniform thickness; andselectively thinning at least a first portion of the barrier layer using one or more cycles comprising forming an oxidized layer in the first portion of the barrier layer using a neutral beam oxidation and removing the oxidized layer using an etching process.2. The method of claim 1 , wherein forming the barrier layer comprises using physical vapor deposition.3. The method of claim 2 , wherein forming the barrier layer modifies a shape of said at least one trench by forming a flared top gap opening of said at least one trench and additional area at the bottom of said at least one trench such that a top of said at least one trench and the bottom of said at least one trench are wider than sidewalls of said at least one trench.4. The method of claim 3 , wherein the additional area is formed by flattening the bottom of said at least one trench.5. The method of claim 3 , wherein each cycle of thinning the first portion of the barrier layer comprises atomic layer etching that maintains the modified shape of said at least one trench.6. The method of claim 5 , wherein each cycle of the thinning the first portion ...

Modularized three-dimensional capacitor array

A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

VERTICAL FUSE STRUCTURES

Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein the vertical fuse devices are formed as part of a process flow for fabricating the FINFET devices. For example, a semiconductor device comprises first and second vertical semiconductor fins, a vertical fuse device, and a FINFET device. The vertical fuse device comprises a metal fuse element formed over a portion of the first vertical semiconductor fin, and the FINFET device comprises a metal gate electrode formed over a portion of the second vertical semiconductor fin. The metal fuse element and the metal gate electrode are concurrently formed as part of a replacement metal gate process flow.

Metallic blocking layer for reliable interconnects and contacts

A semiconductor structure is provided that includes a first interconnect dielectric layer containing a first interconnect metal structure embedded therein. A second interconnect dielectric layer containing a second interconnect metal structure embedded therein is located atop the first interconnect dielectric layer. A metallic blocking layer is present that separates a surface of the second interconnect metal structure from a surface of the first interconnect metal structure. The metallic blocking layer has a lower resistivity than the first and second interconnect metal structures. The metallic blocking layer prevents electromigration of metallic ions from the first and second interconnect metal structure.

Grаin grоwth prоmоtiоn lауеr fоr sеmiсоnduсtоr intеrсоnnесt struсturеs

Аn intеrсоnnесt struсturе оf thе singlе оr duаl dаmаsсеnе tуpе аnd а mеthоd оf fоrming thе sаmе, whiсh substаntiаllу rеduсеs thе еlесtrоmigrаtiоn prоblеm thаt is ехhibitеd bу priоr аrt intеrсоnnесt struсturеs, аrе prоvidеd. In ассоrdаnсе with thе prеsеnt invеntiоn, а grаin grоwth prоmоtiоn lауеr, whiсh prоmоtеs thе fоrmаtiоn оf а соnduсtivе rеgiоn within thе intеrсоnnесt struсturе thаt hаs а bаmbоо miсrоstruсturе аnd аn аvеrаgе grаin sizе оf lаrgеr thаn 0.05 miсrоns is utilizеd. Тhе invеntivе struсturе hаs imprоvеd pеrfоrmаnсе аnd rеliаbilitу.

Struсturе tо imprоvе аdhеsiоn bеtwееn tоp СVD lоw-К diеlесtriс аnd diеlесtriс саpping lауеr

Аn intеrсоnnесt struсturе in whiсh thе аdhеsiоn bеtwееn аn uppеr lеvеl lоw-k diеlесtriс mаtеriаl, suсh аs а mаtеriаl соmprising еlеmеnts оf Si, С, О, аnd Н, аnd аn undеrlуing diffusiоn саpping diеlесtriс, suсh аs а mаtеriаl соmprising еlеmеnts оf С, Si, N аnd Н, is imprоvеd bу inсоrpоrаting аn аdhеsiоn trаnsitiоn lауеr bеtwееn thе twо diеlесtriс lауеrs. Тhе prеsеnсе оf thе аdhеsiоn trаnsitiоn lауеr bеtwееn thе uppеr lеvеl lоw-k diеlесtriс аnd thе diffusiоn bаrriеr саpping diеlесtriс саn rеduсе thе сhаnсе оf dеlаminаtiоn оf thе intеrсоnnесt struсturе during thе pасkаging prосеss. Тhе аdhеsiоn trаnsitiоn lауеr prоvidеd hеrеin inсludеs а lоwеr SiОх оr SiОN-соntаining rеgiоn аnd аn uppеr С grаdеd rеgiоn. Меthоds оf fоrming suсh а struсturе, in pаrtiсulаrlу thе аdhеsiоn trаnsitiоn lауеr, аrе аlsо prоvidеd.

Struсturе tо imprоvе аdhеsiоn bеtwееn tоp СVD lоw-К diеlесtriс аnd diеlесtriс саpping lауеr

Аn intеrсоnnесt struсturе in whiсh thе аdhеsiоn bеtwееn аn uppеr lеvеl lоw-k diеlесtriс mаtеriаl, suсh аs а mаtеriаl соmprising еlеmеnts оf Si, С, О, аnd Н, аnd аn undеrlуing diffusiоn саpping diеlесtriс, suсh аs а mаtеriаl соmprising еlеmеnts оf С, Si, N аnd Н, is imprоvеd bу inсоrpоrаting аn аdhеsiоn trаnsitiоn lауеr bеtwееn thе twо diеlесtriс lауеrs. Тhе prеsеnсе оf thе аdhеsiоn trаnsitiоn lауеr bеtwееn thе uppеr lеvеl lоw-k diеlесtriс аnd thе diffusiоn bаrriеr саpping diеlесtriс саn rеduсе thе сhаnсе оf dеlаminаtiоn оf thе intеrсоnnесt struсturе during thе pасkаging prосеss. Тhе аdhеsiоn trаnsitiоn lауеr prоvidеd hеrеin inсludеs а lоwеr SiОх оr SiОN-соntаining rеgiоn аnd аn uppеr С grаdеd rеgiоn. Меthоds оf fоrming suсh а struсturе, in pаrtiсulаrlу thе аdhеsiоn trаnsitiоn lауеr, аrе аlsо prоvidеd.

Struсturе tо imprоvе аdhеsiоn bеtwееn tоp СVD lоw-К diеlесtriс аnd diеlесtriс саpping lауеr

Аn intеrсоnnесt struсturе in whiсh thе аdhеsiоn bеtwееn аn uppеr lеvеl lоw-k diеlесtriс mаtеriаl, suсh аs а mаtеriаl соmprising еlеmеnts оf Si, С, О, аnd Н, аnd аn undеrlуing diffusiоn саpping diеlесtriс, suсh аs а mаtеriаl соmprising еlеmеnts оf С, Si, N аnd Н, is imprоvеd bу inсоrpоrаting аn аdhеsiоn trаnsitiоn lауеr bеtwееn thе twо diеlесtriс lауеrs. Тhе prеsеnсе оf thе аdhеsiоn trаnsitiоn lауеr bеtwееn thе uppеr lеvеl lоw-k diеlесtriс аnd thе diffusiоn bаrriеr саpping diеlесtriс саn rеduсе thе сhаnсе оf dеlаminаtiоn оf thе intеrсоnnесt struсturе during thе pасkаging prосеss. Тhе аdhеsiоn trаnsitiоn lауеr prоvidеd hеrеin inсludеs а lоwеr SiОх оr SiОN-соntаining rеgiоn аnd аn uppеr С grаdеd rеgiоn. Меthоds оf fоrming suсh а struсturе, in pаrtiсulаrlу thе аdhеsiоn trаnsitiоn lауеr, аrе аlsо prоvidеd.

METAL-INSULATOR-METAL CAPACITOR STRUCTURE SUPPORTING DIFFERENT VOLTAGE APPLICATIONS

A metal-insulator-metal (MIM) capacitor structure includes a substrate extending along a first direction to define a length, a second direction orthogonal to the first direction to define a width, and a third direction orthogonal to the first and second direction to define a height. The substrate includes a first capacitance region and a second capacitance region. The first capacitance region has a first maximum operating voltage (Vmax) and the second capacitance region has a second Vmax that is greater than the first Vmax.

Embedding MRAM device in advanced interconnects

A technique relates to an integrated circuit (IC). Pillars of a set of memory elements are formed. A bilayer dielectric is formed between the pillars, the bilayer dielectric having an upper dielectric material formed on a lower dielectric material without requiring an etch of the lower dielectric material prior to forming the upper dielectric material, thereby preventing a void in the bilayer dielectric, the lower dielectric material including one or more flowable dielectric materials.

MRAM DEVICE WITH WRAP-AROUND TOP ELECTRODE

A semiconductor device including a magnetic tunnel junction (MTJ) stack and an upper word line of the MTJ stack surrounding vertical side surfaces of the MTJ stack. A semiconductor device including a magnetic tunnel junction (MTJ) stack and an upper word line for the MTJ stack surrounding vertical side surfaces and an upper surface of a reference layer of the MTJ stack. A method including forming a forming a magnetic tunnel junction (MTJ) stack and forming a dielectric encapsulation layer surrounding vertical side surfaces of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode of the MTJ stack.

METHOD FOR IMPROVING THE SELECTIVITY OF A CVD PROCESS

A method of forming a noble metal cap on a conductive material embedded in a dielectric material in an interconnect structure. The method includes the step of contacting (i) a conductive material having a bare upper surface partially embedded in a dielectric material and (ii) vapor of a noble metal containing compound, in the presence of carbon monoxide and a carrier gas. The contacting step is carried out at a temperature, pressure and for a length of time sufficient to produce a noble metal cap disposed directly on the upper surface of the conductive material without substantially extending into upper surface of the dielectric material or leaving a noble metal residue onto the dielectric material.

SIZE-FILTERED MULTIMETAL STRUCTURES

A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width. 1. A method of forming a structure , said method comprising:forming a first trench having a width greater than a threshold distance and a second trench having a width not greater than said threshold distance in a dielectric layer located on a substrate;forming a blocking material layer in said first trench and said second trench;removing said blocking material layer from within said first trench while said second trench is filled with a remaining portion of said blocking material layer;filling said first trench with a first metallic material and planarizing said first metallic material to form a first metallic structure within said first trench;removing said remaining portion of said blocking material layer selective to said dielectric material layer; andfilling said second trench with a second metallic material different from said first metallic material.2. The method of claim 1 , further comprising planarizing said second metallic material to form a second metallic structure within said second trench.3. The method of claim 2 ...

Simultaneous formation of liner and metal conductor

In one aspect of the invention, a method for fabricating an advanced metal conductor structure includes providing a conductive line pattern including a set of conductive line trenches in a dielectric layer. Each conductive line trench of the conductive line pattern having parallel vertical sidewalls and a horizontal bottom. A surface treatment of the dielectric layer is performed. The surface treatment produces an element enriched surface layer in which a concentration of a selected element in a surface portion of the parallel sidewalls and horizontal bottoms of the conductive line trenches is increased. A first metal layer is deposited on the element enriched surface layer. A first thermal anneal is performed which simultaneously reflows the first metal layer to fill a first portion of the conductive line trenches and causes a chemical change at interfaces of the first metal layer and the element enriched surface layer creating a liner which is an alloy of the first metal and selected ...

Modulating microstructure in interconnects

Recrystallization and grain growth of an interconnect metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 600° C., for example, for short anneal times of five to 180 minutes by forming a metal stress locking layer on the interconnect metal before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the interconnect metal by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing or wet etching leaving the metal interconnect with low stress and improved grain size and texture. Annealing can be done in a forming gas or nitrogen gas atmosphere.

Noble metal cap for interconnect structures

An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface.

Interconnect structure and method for Cu/ultra low k integration

A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line. A method of forming such an interconnect ...

Advanced metallization for damage repair

An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the contact hole including a bottom surface, and sidewalls extending from the bottom surface to a top surface is provided. The bottom surface of the dielectric layer is in contact with a lower layer of the integrated circuit device. A tungsten via is disposed within the at least one contact hole, the tungsten via having a bottom surface in contact with the lower layer and a top surface. A tungsten nitride layer is disposed on the top surface of the tungsten via to repair etch damage done to the tungsten via.

Reflow interconnect using Ru

A method for forming conductive structures for a semiconductor device includes depositing a reflow liner on walls of trenches formed in a dielectric layer and depositing a reflow material on the reflow liner. The reflow material is reflowed to collect in a lower portion of the trenches. The depositing and the reflowing steps are repeated until the trenches are aggregately filled with the reflow material. The reflow material is planarized to form conductive structures in the trenches.

METALLIC INTERCONNECT STRUCTURES WITH WRAP AROUND CAPPING LAYERS

Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect.

Interconnect structures, design structure and method of manufacture

An interconnect structure is provided that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing. The metal interconnect is formed in a dielectric material. A metal cap is selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous.

Redundancy design with electro-migration immunity and method of manufacture

An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.

BACK END OF LINE METALLIZATION

Interconnect structures and methods for forming the interconnect structures generally include a subtractive etching process to form a fully aligned top via and metal line interconnect structure. The interconnect structure includes a top via and a metal line formed of an alternative metal other than copper or tungsten. A conductive etch stop layer is intermediate the top via and the metal line. The top via is fully aligned to the metal line.

Metal resistors having nitridized metal surface layers with different nitrogen content

A semiconductor structure containing at least two metal resistor structures having different amounts of nitrogen on the resistor surface is provided. The resulted resistances (and hence resisitivty) of the two metal resistors can be either the same or different. The semiconductor structure may include a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first metal layer portion and a first nitridized metal surface layer having a first nitrogen content. The semiconductor structure further includes a second metal resistor structure located on a second portion of the dielectric-containing substrate and spaced apart from the first metal resistor structure. The second metal resistor structure includes, from bottom to top, a second metal layer portion and a second nitridized metal surface layer having a second nitrogen content that differs from the first nitrogen content.

BORDERLESS CONTACTS FOR METAL GATES THROUGH SELECTIVE CAP DEPOSITION

A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region. 1. A semiconductor device comprising:a gate structure present on a channel portion of a substrate, wherein the gate structure comprises a gate dielectric layer and at least one metal gate conductor;a source region and a drain region present on opposing sides of the channel portion of the substrate;a dielectric spacer adjacent to the gate structure;an etch stop layer on the entire exterior surface of the dielectric spacer, wherein an upper surface of the etch stop layer is coplanar with an upper surface of the gate structure;a metal oxide gate cap on the upper surface of the etch stop layer and the upper surface of the gate structure;contacts that extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region.2. (canceled)3. The semiconductor device of claim 1 , wherein the etch stop layer is composed of a metal oxide that is selected from the group consisting of zirconium oxide claim 1 , aluminum oxide claim 1 , magnesium oxide claim 1 , hafnium oxide claim 1 , lanthium oxide claim 1 , cerium oxide claim 1 , strontium oxide claim 1 , titanium oxide and a combination thereof.4. The semiconductor device of claim 1 , wherein the etch stop layer is a conformal layer.5. The semiconductor device of claim 4 , wherein the etch stop layer has a ...

Interconnect structure having a via with a via gouging feature and dielectric liner sidewalls for BEOL integration

An interconnect structure including a lower interconnect level with a first dielectric layer having a first conductive material embedded therein; a dielectric capping layer located on the first dielectric layer and some portions of the first conductive material; an upper interconnect level including a second dielectric layer having at least one via opening filled with a second conductive material and at least one overlying line opening filled with the second conductive material disposed therein, wherein the at least one via opening is in contact with the first conductive material in the lower interconnect level by a via gouging feature; a dielectric liner on sidewalls of the at least one via opening; and a first diffusion barrier layer on sidewalls and a bottom of both the at least one via opening and the at least one overlying line opening. A method of forming the interconnect structure is also provided.

Grаin grоwth prоmоtiоn lауеr fоr sеmiсоnduсtоr intеrсоnnесt struсturеs

Аn intеrсоnnесt struсturе оf thе singlе оr duаl dаmаsсеnе tуpе аnd а mеthоd оf fоrming thе sаmе, whiсh substаntiаllу rеduсеs thе еlесtrоmigrаtiоn prоblеm thаt is ехhibitеd bу priоr аrt intеrсоnnесt struсturеs, аrе prоvidеd. In ассоrdаnсе with thе prеsеnt invеntiоn, а grаin grоwth prоmоtiоn lауеr, whiсh prоmоtеs thе fоrmаtiоn оf а соnduсtivе rеgiоn within thе intеrсоnnесt struсturе thаt hаs а bаmbоо miсrоstruсturе аnd аn аvеrаgе grаin sizе оf lаrgеr thаn 0.05 miсrоns is utilizеd. Тhе invеntivе struсturе hаs imprоvеd pеrfоrmаnсе аnd rеliаbilitу.

Struсturе tо imprоvе аdhеsiоn bеtwееn tоp СVD lоw-К diеlесtriс аnd diеlесtriс саpping lауеr

Аn intеrсоnnесt struсturе in whiсh thе аdhеsiоn bеtwееn аn uppеr lеvеl lоw-k diеlесtriс mаtеriаl, suсh аs а mаtеriаl соmprising еlеmеnts оf Si, С, О, аnd Н, аnd аn undеrlуing diffusiоn саpping diеlесtriс, suсh аs а mаtеriаl соmprising еlеmеnts оf С, Si, N аnd Н, is imprоvеd bу inсоrpоrаting аn аdhеsiоn trаnsitiоn lауеr bеtwееn thе twо diеlесtriс lауеrs. Тhе prеsеnсе оf thе аdhеsiоn trаnsitiоn lауеr bеtwееn thе uppеr lеvеl lоw-k diеlесtriс аnd thе diffusiоn bаrriеr саpping diеlесtriс саn rеduсе thе сhаnсе оf dеlаminаtiоn оf thе intеrсоnnесt struсturе during thе pасkаging prосеss. Тhе аdhеsiоn trаnsitiоn lауеr prоvidеd hеrеin inсludеs а lоwеr SiОх оr SiОN-соntаining rеgiоn аnd аn uppеr С grаdеd rеgiоn. Меthоds оf fоrming suсh а struсturе, in pаrtiсulаrlу thе аdhеsiоn trаnsitiоn lауеr, аrе аlsо prоvidеd.

Grаin grоwth prоmоtiоn lауеr fоr sеmiсоnduсtоr intеrсоnnесt struсturеs

Аn intеrсоnnесt struсturе оf thе singlе оr duаl dаmаsсеnе tуpе аnd а mеthоd оf fоrming thе sаmе, whiсh substаntiаllу rеduсеs thе еlесtrоmigrаtiоn prоblеm thаt is ехhibitеd bу priоr аrt intеrсоnnесt struсturеs, аrе prоvidеd. In ассоrdаnсе with thе prеsеnt invеntiоn, а grаin grоwth prоmоtiоn lауеr, whiсh prоmоtеs thе fоrmаtiоn оf а соnduсtivе rеgiоn within thе intеrсоnnесt struсturе thаt hаs а bаmbоо miсrоstruсturе аnd аn аvеrаgе grаin sizе оf lаrgеr thаn 0.05 miсrоns is utilizеd. Тhе invеntivе struсturе hаs imprоvеd pеrfоrmаnсе аnd rеliаbilitу.

ADDITIVE INTERCONNECT FORMATION

A semiconductor substrate has a metal via in the substrate, and has, on the substrate, a metal line that is less than 8 nanometers (nm) wide and at least 20 nm tall. A method for making a semiconductor structure includes forming a metal via in a substrate; forming a mandrel atop and offset from the via; depositing a metal-containing liner onto the mandrel; exposing the top of the mandrel by anisotropically etching the liner, thereby defining a separate portion of the liner at each side of the mandrel; and growing a metal line on each portion of the liner.

High-density memory devices using oxide gap fill

A semiconductor structure forms two or more tightly pitched memory devices using a dielectric material for a gap fill material. The approach includes providing two adjacent bottom electrodes in a layer of an insulating material and above a metal layer. Two adjacent pillars are each above one of the two adjacent bottom electrodes where each pillar of the two adjacent pillars is composed of a stack of materials for a memory device. A spacer is around the vertical sides each of the two adjacent pillars. The dielectric material is on the spacer around the vertical sides each of the two adjacent pillars, on the layer of the insulating material between the two adjacent bottom electrodes. The dielectric material fills at least a first portion of a gap between the two adjacent pillars. A low k material covers the dielectric material and exposed portions of the layer of the insulating material.

STRUCTURE AND METHOD FOR CREATING RELIABLE VIA CONTACTS FOR INTERCONNECT APPLICATIONS

A reliable and mechanical strong interconnect structure is provided that does not include gouging features in the bottom of the an opening, particularly at a via bottom. Instead, the interconnect structures of the present invention utilize a Co-containing buffer layer that is selectively deposited on exposed surfaces of the conductive features that are located in a lower interconnect level. The selective deposition is performed through at least one opening that is present in a dielectric material of an upper interconnect level. The selective deposition is performed by electroplating or electroless plating. The Co-containing buffer layer comprises Co and at least one of P and B. W may optionally be also present in the Co-containing buffer layer.

Material for forming metal matrix composite and metal matrix composite bulk

A metal matrix composite material includes 60-90 wt. % of aluminum alloy powders and 10-40 wt. % Fe-based amorphous alloy powders. The aluminum alloy powders are used as the matrix of the metal matrix composite material, and the Fe-based amorphous alloy powders include FeaCrbMocSidBeYf, wherein 48 at. %≤a≤50 at. %, 21 at. %≤b≤23 at. %, 18 at. %≤c≤20 at. %, 3 at. %≤D≤5 at. %, 2 at. %≤c≤4 at. %, and 2 at. %≤f≤4 at. %.

Interconnect structure containing various capping materials for programmable electrical fuses

A structure and design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

ENHANCED MECHANICAL STRENGTH VIA CONTACTS

The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.

Systems and Methods for Controlling of Electro-Migration

Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest ...

Dual damascene dual alignment interconnect scheme

A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions.

Silicon carbide and silicon nitride interconnects

A method for fabricating an interconnect for integrated circuit is described. A recess is provided in a first dielectric layer comprising a first dielectric and a second dielectric layer comprised of a second dielectric. The first and second dielectric layers are disposed over a substrate. The second dielectric layer is disposed over the first dielectric layer. The recess is filled with a metal conductor. A chemical mechanical polishing process removes the metal conductor from field areas on the second dielectric layer. The second dielectric layer is removed. An interconnect element is created having a top face which protrudes higher than a top face of the first dielectric layer. The metal conductor of the interconnect element has direct contact with the first dielectric layer. In other aspects of the invention, the interconnect structure is described.

High density planar magnetic domain wall memory apparatus

A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.

Electrically programmable metal fuse

A metal electrically programmable fuse (eFuse) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming.

BEOL electrical fuse and method of forming the same

A BEOL eFuse is provided that includes a fuse element-containing layer having an entirely planar topmost surface. An upper portion of the fuse element-containing layer including the entirely planar topmost surface is present above a topmost surface of a second interconnect dielectric material layer, and a lower portion of the fuse-element containing layer is present in an opening that is formed in the second interconnect dielectric material layer and has a surface that contacts a first electrode structure that is partially embedded in a first interconnect dielectric material layer which underlies the second interconnect dielectric material layer. A second electrode structure that is present in a third interconnect dielectric material layer that overlies the second interconnect dielectric material layer contacts a portion of the planar topmost surface of the fuse-element-containing layer.

OVERLAY-TOLERANT VIA MASK AND REACTIVE ION ETCH (RIE) TECHNIQUE

A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal. 1. A method comprising:first etching a substrate according to a first mask, wherein the first etching forms a first etch feature to a first depth and the first etching forms a sliver opening in the substrate;filling said sliver opening with a fill material;forming a second mask by removing a portion of the first mask;second etching said substrate exposed by said second mask, wherein the second etching is selective to the fill material, the second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature; andfilling the first etch feature and the second etch feature with a conductive metal.2. The method of claim 1 , wherein the first etch feature comprises at least one via opening and the second etch feature comprises line trenches claim 1 , and wherein filling the first etch feature and the second etch feature with the conductive metal forms lines and at least one via in the substrate.3. The method of claim 2 , wherein at least one of the line trenches intersects with at least one of the at least one via openings.4. The method of claim 2 , wherein the mask comprises a first mask layer that is patterned to include first mask openings that correspond ...

Forming Gate Contact Over Active Free of Metal Recess

Techniques for forming contact over active gate free of metal recess are provided. In one aspect, a method for forming a COAG device includes: forming gates over an active area of a wafer; forming source and drains on opposite sides of the gates; burying the gates in an ILD; forming source/drain contacts in the ILD between the gates; depositing a sacrificial metal selectively on the source/drain contacts with first gaps present in the sacrificial metal over the gates; filling the first gaps with a first dielectric material to form gate caps over the gates; selectively removing the sacrificial metal which forms second gaps between the gate caps over the source/drain contacts; and filling the second gaps with a second dielectric material to form source/drain caps over the source/drain contacts. A COAG device is also provided.

BEOL integration with advanced interconnects

An alloy liner is located on a diffusion barrier liner and both are present in at least a via portion of a combined via/line opening that is present in an interconnect dielectric material. The alloy liner includes an alloy of a first metal or metal alloy having a first bulk resistivity and a second metal or metal alloy having a second bulk resistivity that is higher than the first bulk resistivity. A first electrically conductive structure is located on the alloy liner and is present in at least the via portion of the combined via/line opening. The first electrically conductive structure includes the second metal or metal alloy. A second electrically conductive structure can be present in at least the line portion of the combined via/line opening. The second electrically conductive structure may include a metal or metal alloy having the first or second bulk resistivity.

Liner-free and partial liner-free contact/via structures

A liner-free or partial liner-free contact/via structure that is embedded within a dielectric capping layer and positioned between an electrically conductive structure and an overlying contact structure is provided.

Simultaneous formation of liner and metal conductor

An advanced metal conductor structure and a method for constructing the structure are described. A method for fabricating an advanced metal conductor structure provides a conductive line pattern including a set of conductive line trenches in a dielectric layer. Each conductive line trench of the conductive line pattern has parallel vertical sidewalls and a horizontal bottom. A surface treatment of the dielectric layer is performed. The surface treatment produces an element enriched surface layer in which a concentration of a selected element in a surface portion of the parallel sidewalls and horizontal bottoms of the conductive line trenches is increased. A metal layer is deposited on the element enriched surface layer. A thermal anneal process is then performed which simultaneously reflows the metal layer to fill the conductive line trenches and causes a chemical change at interfaces of the metal layer and the element enriched surface layer creating a liner which is an alloy of the metal ...

Metal reflow for middle of line contacts

A method of forming a contact in a semiconductor device includes forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD) material arranged between the first gate and the second gate to form a trench that extends from a surface of the first gate and a surface of the second gate to the substrate; depositing a liner along a sidewall of the trench and an endwall of the trench in contact with the substrate; depositing by a physical vapor deposition method (PVD) a layer of metal on a surface of the first gate and a surface of the second gate; and heating to reflow metal from the layer of metal on the surface of the first gate and the second gate into the trench and form the contact.

MOSFET gate and source/drain contact metallization

A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals.

CONDUCTIVE INTERCONNECT HAVING A SEMI-LINER AND NO TOP SURFACE RECESS

According to embodiments of the present invention, a semiconductor wafer includes a substrate and an interlayer dielectric located on the substrate. The interlayer dielectric includes an interconnect. A barrier layer is located in between the interconnect and the interlayer dielectric. A semi-liner layer is located in between the interconnect and the barrier layer. The interlayer dielectric, the interconnect, and barrier layer form a substantially planar surface opposite the substrate. The interconnect has an interconnect height from a base to the substantially planar surface and a semi-liner height of the semi-liner layer is less than the interconnect height such that liner layer does not extend to the planar surface.

FABRICATING VIAS WITH LOWER RESISTANCE

An interconnection for a device in an integrated circuit includes a substrate on which a first metal line is embedded in a first dielectric layer. A via gouge is etched in the first metal line. A second dielectric layer is deposited over the first metal line and the first dielectric layer. A first via recess is etch through the second dielectric layer where the first via recess aligned to the via gouge. A second metal layer is deposited in the first via recess and the via gouge, forming a first via.

Method of forming a three-dimensional bonded semiconductor structure having nitridized oxide regions

A first semiconductor structure including a first bonding oxide layer having a first metallic bonding structure embedded therein and a second semiconductor structure including a second bonding oxide layer having a second metallic bonding structure embedded therein are provided. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. Each nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layer and nitridized metallic regions located in an upper portion of the metallic bonding structures. The nitrogen within the nitridized metallic regions is then removed to restore the upper portion of the metallic bonding structures to its original composition. Bonding is performed to form a dielectric bonding interface between the nitridized oxide regions present in the first and second structures, and a metallic bonding interface between the first and second metallic bonding structures.

Metal cap with ultra-low kappa dielectric material for circuit interconnect applications

An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided.

REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY AND METHOD OF MANUFACTURE

An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, a design structure of the IC interconnect and a method of manufacture of the IC interconnect is provided. The structure has electro-migration immunity and redundancy of design, which includes a plurality of wires laid out in parallel and each of which are coated with a liner material. Two adjacent of the wires are physically contacted to each other.

ADVANCED E-FUSE STRUCTURE WITH HYBRID METAL CONTROLLED MICROSTRUCTURE

A structure of an e-Fuse device in a semiconductor device is described. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper layer and an aspect ratio reducing layer, and the fuse element is comprised of a fine grained copper structure.

Struсturе tо imprоvе аdhеsiоn bеtwееn tоp СVD lоw-К diеlесtriс аnd diеlесtriс саpping lауеr

Аn intеrсоnnесt struсturе in whiсh thе аdhеsiоn bеtwееn аn uppеr lеvеl lоw-k diеlесtriс mаtеriаl, suсh аs а mаtеriаl соmprising еlеmеnts оf Si, С, О, аnd Н, аnd аn undеrlуing diffusiоn саpping diеlесtriс, suсh аs а mаtеriаl соmprising еlеmеnts оf С, Si, N аnd Н, is imprоvеd bу inсоrpоrаting аn аdhеsiоn trаnsitiоn lауеr bеtwееn thе twо diеlесtriс lауеrs. Тhе prеsеnсе оf thе аdhеsiоn trаnsitiоn lауеr bеtwееn thе uppеr lеvеl lоw-k diеlесtriс аnd thе diffusiоn bаrriеr саpping diеlесtriс саn rеduсе thе сhаnсе оf dеlаminаtiоn оf thе intеrсоnnесt struсturе during thе pасkаging prосеss. Тhе аdhеsiоn trаnsitiоn lауеr prоvidеd hеrеin inсludеs а lоwеr SiОх оr SiОN-соntаining rеgiоn аnd аn uppеr С grаdеd rеgiоn. Меthоds оf fоrming suсh а struсturе, in pаrtiсulаrlу thе аdhеsiоn trаnsitiоn lауеr, аrе аlsо prоvidеd.

Grаin grоwth prоmоtiоn lауеr fоr sеmiсоnduсtоr intеrсоnnесt struсturеs

Аn intеrсоnnесt struсturе оf thе singlе оr duаl dаmаsсеnе tуpе аnd а mеthоd оf fоrming thе sаmе, whiсh substаntiаllу rеduсеs thе еlесtrоmigrаtiоn prоblеm thаt is ехhibitеd bу priоr аrt intеrсоnnесt struсturеs, аrе prоvidеd. In ассоrdаnсе with thе prеsеnt invеntiоn, а grаin grоwth prоmоtiоn lауеr, whiсh prоmоtеs thе fоrmаtiоn оf а соnduсtivе rеgiоn within thе intеrсоnnесt struсturе thаt hаs а bаmbоо miсrоstruсturе аnd аn аvеrаgе grаin sizе оf lаrgеr thаn 0.05 miсrоns is utilizеd. Тhе invеntivе struсturе hаs imprоvеd pеrfоrmаnсе аnd rеliаbilitу.

Struсturе tо imprоvе аdhеsiоn bеtwееn tоp СVD lоw-К diеlесtriс аnd diеlесtriс саpping lауеr

Аn intеrсоnnесt struсturе in whiсh thе аdhеsiоn bеtwееn аn uppеr lеvеl lоw-k diеlесtriс mаtеriаl, suсh аs а mаtеriаl соmprising еlеmеnts оf Si, С, О, аnd Н, аnd аn undеrlуing diffusiоn саpping diеlесtriс, suсh аs а mаtеriаl соmprising еlеmеnts оf С, Si, N аnd Н, is imprоvеd bу inсоrpоrаting аn аdhеsiоn trаnsitiоn lауеr bеtwееn thе twо diеlесtriс lауеrs. Тhе prеsеnсе оf thе аdhеsiоn trаnsitiоn lауеr bеtwееn thе uppеr lеvеl lоw-k diеlесtriс аnd thе diffusiоn bаrriеr саpping diеlесtriс саn rеduсе thе сhаnсе оf dеlаminаtiоn оf thе intеrсоnnесt struсturе during thе pасkаging prосеss. Тhе аdhеsiоn trаnsitiоn lауеr prоvidеd hеrеin inсludеs а lоwеr SiОх оr SiОN-соntаining rеgiоn аnd аn uppеr С grаdеd rеgiоn. Меthоds оf fоrming suсh а struсturе, in pаrtiсulаrlу thе аdhеsiоn trаnsitiоn lауеr, аrе аlsо prоvidеd.

LOCAL INTERCONNECTS HAVING DIFFERENT MATERIAL COMPOSITIONS

A semiconductor device and formation thereof. The semiconductor device including: a first bottom interconnect formed within a first dielectric layer and located within a logic area of the semiconductor device; a second bottom interconnect formed within the first dielectric layer and located within a memory area of the semiconductor device; and a memory device formed on top of the second bottom interconnect located within the memory area of the semiconductor device, wherein: a first metal material used to form the first bottom interconnect located in the logic area is different than a second metal material used to form the second bottom interconnect located in the memory area.

HIGH DENSITY TWO-TIER MRAM STRUCTURE

Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a semiconductor structure. The semiconductor structure may include an embedded magnetic random access memory (MRAM) array electrically connected between a bottom metal level and a top metal level. The MRAM array may include a first tier with first MRAM cells and first vias above the first MRAM cells, and a second tier with second MRAM cells and second vias below the second MRAM cells.

Semiconductor resistor structures embedded in a middle-of-the-line (MOL) dielectric

A resistor structure composed of a metal liner is embedded within a MOL dielectric material and is located, at least in part, on a surface of a doped semiconductor material structure. The resistor structure is located on a same interconnect level of the semiconductor structure as a lower contact structure and both structures are embedded within the same MOL dielectric material. The metal liner that provides the resistor structure is composed of a metal or metal alloy having a higher resistivity than a metal or metal alloy that provides the contact metal of the lower contact structure.

IMPROVED BOTTOM ELECTRODE FOR SEMICONDUCTOR MEMORY DEVICE

A structure and a method for fabricating a bottom electrode for an integrated circuit device are described. A first dielectric layer is provided over a substrate and the first dielectric layer has a recess. A bottom electrode is formed over the recess. The bottom electrode consists of a microstud layer disposed completely within the recess of the dielectric and conforming to the recess, a bottom pedestal disposed on a top surface of the microstud and a top pedestal on a top surface of the bottom pedestal. The material used for the bottom pedestal has a lower electrochemical voltage than a material used for the microstud. A conductive element of the integrated circuit device is formed on a top surface of the bottom electrode. A first portion of the bottom electrode is disposed in and conforms to the recess. A second portion of the bottom electrode and the conductive element are conical sections.

VERTICAL ELECTRICAL FUSE

A vertical electrical fuse (eFuse) is provided that can be blown utilizing a relatively small current. The vertical eFuse is embedded in various dielectric material layers and includes a fuse link that is located between, and vertically connected to, first and second electrically conductive structures, the fuse link having a gouging feature at the bottom thereof.

Tunable resistor with curved resistor elements

A resistor structure is provided that contains curved resistor elements. The resistor structure is embedded within an interconnect dielectric material and the resistivity of an electrical conducting resistive material of the resistor structure can be tuned to a desired resistivity during the manufacturing of the resistor structure. Notably, an electrical conducting metallic structure having a concave outermost surface is provided in a dielectric material layer. A doped metallic insulator layer is formed on the concave outermost surface of the metallic structure. A controlled surface treatment process is then performed to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material. An interconnect dielectric material can then be formed to embed the entirety of the remaining doped metallic insulator layer and the electrical conducting resistive material.

SEMICONDUCTOR CAPACITOR

An improved semiconductor capacitor and method of fabrication is disclosed. A nitride stack, comprising alternating sublayers of slow-etch and fast-etch nitride is deposited on a substrate. The nitride stack is etched via an anisotropic etch technique such as reactive ion etch. A wet etch then etches the nitride stack, forming a corrugated shape. The corrugated shape increases surface area, and hence increases the capacitance of the capacitor. 1. A semiconductor capacitor comprising:a base dielectric layer;a nitride stack disposed on the base dielectric layer, the nitride stack comprised of a plurality of nitride sublayers, wherein a first subset of the nitride sublayers are comprised of fast-etch nitride, and wherein a second subset of the nitride sublayers are comprised of slow-etch nitride, and wherein the nitride stack is comprised of alternating sublayers of fast-etch nitride and slow-etch nitride:a trench formed within the nitride stack, the trench comprising an interior surface having a corrugated shape;a first metal layer, the first metal layer disposed on the interior surface of the trench;a high-K dielectric layer disposed on the first metal layer; anda second metal layer disposed on the high-K dielectric layer, and filling the trench.2. The semiconductor capacitor of claim 1 , wherein the slow-etch nitride has a density ranging from about 2.6 g/cc to about 2.8 g/cc.3. The semiconductor capacitor of claim 1 , wherein the fast-etch nitride has a density ranging from about 2.0 g/cc to about 2.4 g/cc.4. The semiconductor capacitor of claim 1 , wherein the first metal layer is comprised of a material selected from the group consisting of ruthenium and tantalum.5. The semiconductor capacitor of claim 1 , wherein the high-K dielectric layer is comprised of a material selected from the group consisting of hafnium oxide claim 1 , hafnium silicate claim 1 , and zirconium oxide.6. The semiconductor capacitor of claim 1 , wherein each sublayer of fast-etch nitride ...

SEMICONDUCTOR CAPACITOR

A semiconductor capacitor and its method of fabrication are disclosed. A non-linear nitride layer is used to increase the surface area of a capacitor plate, resulting in increased capacitance without increase in chip area used for the capacitor. 1. A semiconductor capacitor comprising:a first dielectric layer;a second dielectric layer disposed over the first dielectric layer;a cavity formed within the second dielectric layer;a metal plug disposed within the cavity;a nitride layer having a non-linear cross section, extending from the metal plug;a first metal layer disposed over the nitride layer;a third dielectric layer disposed over the first metal layer; anda second metal layer disposed over the third dielectric layer.2. The semiconductor capacitor of claim 1 , wherein the nitride layer is comprised of a slow-etch nitride.3. The semiconductor capacitor of claim 1 , wherein the non-linear cross section comprises an L-shaped cross section.4. The semiconductor capacitor of claim 1 , wherein the nitride layer extends from the metal plug at an intermediate point along the metal plug.5. The semiconductor capacitor of claim 1 , wherein the nitride layer is formed in a closed shape around the metal plug.6. The semiconductor capacitor of claim 5 , wherein the nitride layer is formed in a circular shape around the metal plug.7. The semiconductor capacitor of claim 1 , wherein the nitride layer has a thickness ranging from about 80 to about 120 angstroms.8. The semiconductor capacitor of claim 1 , wherein the first metal layer is comprised of tungsten.9. The semiconductor capacitor of claim 1 , wherein the first metal layer is comprised of ruthenium.10. A method of fabricating a semiconductor capacitor claim 1 , comprising:forming a cavity in a first dielectric layer;depositing a nitride stack comprising a slow-etch nitride layer disposed between two fast-etch nitride layers in the cavity;etching a portion of the nitride stack within the cavity;depositing a metal plug in the ...

STRUCTURE AND METALLIZATION PROCESS FOR ADVANCED TECHNOLOGY NODES

The problem of poor adherence of a dielectric coating on a patterned metal structure can be solved by forming an adhesion layer on exposed surfaces of such metal structure prior to deposition of such dielectric. According to an embodiment, the invention provides a method to form a self-aligned adhesion layer on the surface of metal interconnect structure within an integrated circuit by exposing the metal structure to a controlled atmosphere and a flow of nitrogen-containing gas. 1. A method to form a self-aligned adhesion layer within an integrated circuit , wherein said integrated circuit includes metal interconnect structure conductively connected to at least one semiconductor device , the method comprising:{'sup': −6', '−10, 'exposing said metal interconnect structure to a controlled atmosphere, said controlled atmosphere at a temperature between 100 C and 600 C and at a pressure between 10and 10torr, and'}introducing a flow of nitrogen-containing gas.2. The method of wherein said controlled atmosphere is at a temperature between 150 C and 500 C and at a pressure between 10and 10torr and said introducing step comprises:introducing said flow of nitrogen-containing gas at a rate between 50 sccm and 1800 sccm, andmaintaining pressure below 10 torr.3. The method of further comprising:sustaining said introducing step for a time effective to form said adhesion layer having thickness greater than 5 A.4. The method of wherein said flow of gas is below 1500 sccm while pressure is maintained below 1 torr.5. The method of wherein said controlled atmosphere is at a temperature between 100 C and 400 C and said introducing step comprises:forming a plasma in said controlled atmosphere,flowing said nitrogen-containing gas at a rate between 1300 sccm and 1700 sccm, andsustaining said introducing step for a time effective to form said adhesion layer having thickness greater than 5 A.6. The method of wherein said controlled atmosphere is within a chamber having a top electrode and ...

METAL CAP WITH ULTRA-LOW k DIELECTRIC MATERIAL FOR CIRCUIT INTERCONNECT APPLICATIONS

An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided. 1. A method of forming an interconnect structure comprising:providing a dielectric material having a dielectric constant of about 3.0 or less, said dielectric material having at least one conductive material embedded within said dielectric material, said at least one conductive material having an upper surface that is bare; andforming a noble metal cap directly on said upper surface of said at least one conductive material, said noble metal cap does not substantially extend onto an upper surface of said dielectric material that is adjacent to said at least one conductive material, said noble metal cap forming does not result in noble metal residues on the upper surface of said dielectric material, and said forming includes a chemical deposition process that is performed at a temperature of about 300° C. or less.2. The method of wherein said chemical deposition process includes chemical vapor deposition process or atomic layer deposition.3. The method of wherein said temperature is less than about 200° C.4. The method of wherein said upper surface of said dielectric material is coplanar with said upper surface of said at least one conductive ...

STRUCTURE AND METHODS OF FORMING CONTACT STRUCTURES

A contact structure and a method of forming the contact structure. The structure includes: a silicide layer on and in direct physical contact with a top substrate surface of a substrate; an electrically insulating layer on the substrate; and an aluminum plug within the insulating layer. The aluminum plug has a thickness not exceeding 25 nanometers in a direction perpendicular to the top substrate surface. The aluminum plug extends from a top surface of the silicide layer to a top surface of the insulating layer. The aluminum plug is in direct physical contact with the top surface of the silicide layer and is in direct physical contact with the silicide layer. The method includes: forming the silicide layer on and in direct physical contact with the top substrate surface of the substrate; forming the electrically insulating layer on the substrate; and forming the aluminum plug within the insulating layer. 1. A contact structure , comprising:a silicide layer on and in direct physical contact with a top substrate surface of a substrate;an electrically insulating layer on the substrate; andan aluminum plug within the insulating layer, said aluminum plug having a thickness not exceeding 25 nanometers in a direction perpendicular to the top substrate surface, said aluminum plug extending in said direction from a top surface of the silicide layer to a top surface of the insulating layer, said aluminum plug being in direct physical contact with the top surface of the silicide layer and being in direct physical contact with the silicide layer.2. The structure of claim 1 , wherein the insulating layer is in direct physical contact with the top surface of the silicide layer claim 1 , and wherein the insulating layer is separated from the top substrate surface by the silicide layer.3. The structure of claim 1 , wherein the insulating layer is in direct physical contact with a side surface of the silicide layer that is perpendicular to the top surface of the silicide layer claim ...

Creation of vias and trenches with different depths

Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS

Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided. 1. A method comprising:depositing a plurality of dielectric layers on top of a semiconductor structure, said plurality of dielectric layers being separated by at least one etch-stop layer;creating multiple openings from a top surface of said plurality of dielectric layers down into said plurality of dielectric layers by a non-selective etching process, wherein at least one of said multiple openings has a depth below said etch-step layer; andcontinuing etching said multiple openings by a selective etching process until one or more openings of said multiple openings that are above said etch-stop layer reach and expose said etch-stop layer.2. The method of claim 1 , wherein said etch-stop layer is a first etch-stop layer; said plurality of dielectric layers are further separated by a second etch-stop layer that is separated from and underneath said first etch-stop layer; and said at least one of said multiple openings is a first opening; further comprising creating a second opening of said multiple openings that has a depth below said second etch-stop layer.3. The method of claim 2 , wherein continuing said etching of said multiple openings comprises etching said multiple openings by said ...

INTEGRATED CIRCUIT LINE WITH ELECTROMIGRATION BARRIERS

An integrated circuit comprising an electromigration barrier includes a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line. 1. An integrated circuit comprising an electromigration barrier , comprising:a line, the line comprising a first conductive material, the line further comprising a plurality of line segments separated by one or more electromigration barriers, wherein the one or more electromigration barriers comprise a second conductive material that isolates electromigration effects within individual segments of the line.2. The integrated circuit of claim 1 , wherein the second conductive material comprises a cobalt-tungsten-phosphorus compound.3. The integrated circuit of claim 1 , wherein the first conductive material comprises copper formed by a damascene process.4. The integrated circuit of claim 1 , further comprising a layer comprising the second conductive material formed over the line.5. The integrated circuit of claim 4 , further comprising a dielectric liner formed over the layer comprising the second conductive material.6. The integrated circuit of claim 5 , wherein the dielectric liner comprises a first NBLoK cap layer.7. The integrated circuit of claim 5 , further comprising a first inter-layer dielectric layer formed over the dielectric liner.8. The integrated circuit of claim 1 , wherein the line contacts a via of the integrated circuit.9. The integrated circuit of claim 8 , wherein the first conductive material of the line contacts the via of the integrated circuit.10. The integrated circuit of claim 8 , wherein the via extends through a second interlayer dielectric layer of the integrated circuit.11. The integrated circuit of claim 10 , wherein the via additionally ...

FINFET FUSE WITH ENHANCED CURRENT CROWDING

A method forms an eFuse structure that has a pair of adjacent semiconducting fins projecting from the planar surface of a substrate (in a direction perpendicular to the planar surface). The fins have planar sidewalls (perpendicular to the planar surface of the substrate) and planar tops (parallel to the planar surface of the substrate). The tops are positioned at distal ends of the fins relative to the substrate. An insulating layer covers the tops and the sidewalls of the fins and covers an intervening substrate portion of the planar surface of the substrate located between the fins. A metal layer covers the insulating layer. A pair of conductive contacts are connected to the metal layer at locations where the metal layer is adjacent the top of the fins. 1. An eFuse structure comprising:a substrate having a planar surface;a pair of adjacent semiconducting fins projecting from said planar surface of said substrate in a direction perpendicular to said planar surface, said fins having planar sidewalls perpendicular to said planar surface of said substrate and planar tops parallel to said planar surface of said substrate, said tops being positioned at distal ends of said fins relative to said substrate;an insulating layer covering said tops and said sidewalls of said fins and covering an intervening substrate portion of said planar surface of said substrate located between said fins;a metal layer covering said insulating layer; anda pair of conductive contacts connected to said metal layer at locations where said metal layer is adjacent said top of said fins.2. The eFuse structure according to claim 1 , said sidewalls and said tops of said fins forming right-angle corners claim 1 , and said sidewalls of said fins and said intervening substrate portion forming right angle corners.3. The eFuse structure according to claim 1 , further comprising a polysilicon layer on said metal layer claim 1 , said conductive contacts extending through said polysilicon layer to contact ...

AIR-DIELECTRIC FOR SUBTRACTIVE ETCH LINE AND VIA METALLIZATION

A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via. 1. A method to form interconnected metallization layers , the method comprising:providing a layer of conductive features including at least two line members disposed on a substrate, at least one said line member connected to a via member extending away from said substrate, said at least two said line members spaced from one another by less than or equal to an effective distance;depositing a coating to form an air gap between said line members; andexposing a top end of said via.2. The method of wherein said coating comprises a poorly conformal dielectric layer.3. The method of further comprising;forming a dielectric layer having a substantially flat top surface over said layer of conductive features prior to said exposing step.4. The method of wherein coating has a nominal thickness and said via has a height greater than said nominal thickness.5. The method of wherein said at least two line members are spaced by a gap claim 1 , said gap having an aspect ratio greater than 2.6. The method of wherein said aspect ratio is between 3 and 10.7. The method of further comprising:forming a second conductive layer in conductive contact with said top end.8. The method of further comprising:forming an opening into said air gap, anddepositing dielectric material onto said coating and at least partially filling said opened air gap.9. A structure formed according to the method of .10. ...

Method to fabricate copper wiring structures and structures formed tehreby

Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias.

REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY AND METHOD OF MANUFACTURE

An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires. 1. A method to fabricate a ribbon wire structure comprising:forming wires in an insulation material;wrapping the wires with a liner material;forming spaces between the wires by removing the insulating material between adjacent wires; anddepositing a metal layer in the spaces to form additional wires, between and adjacent to the wires already formed.2. The method of claim 1 , further comprising planarizing the deposited metal layer.3. The method of claim 1 , wherein adjacent ones of the wires and the additional wires are devoid of insulator material therebetween.4. The method of claim 1 , wherein the wires and the additional wires form a cluster-of-via structure at an intersection between inter-level wires.5. The method of claim 4 , wherein the liner material covers a top side of each of the wires and the additional wires claim 4 , and the liner material is shared with a top one of the inter-level wires.6. The method of claim 4 , wherein the liner material covers a bottom side of each of the wires and the additional wires claim 4 , and the liner material is shared with a bottom one of the inter-level wires.7. The method of claim 1 , wherein the forming spaces comprising etching the insulation material using a reactive ion etching process.8. The method of claim 7 , further comprising redepositing the liner material to conformally coat the etched surface.9. The method of claim 8 , wherein the metal layer is deposited in the spacer ...

FORMING BORDERLESS CONTACT FOR TRANSISTORS IN A REPLACEMENT METAL GATE PROCESS

Embodiments of the present invention provide a method of forming a semiconductor structure. The method includes creating an opening inside a dielectric layer, the dielectric layer being formed on top of a substrate and the opening exposing a channel region of a transistor in the substrate; depositing a work-function layer lining the opening and covering the channel region; forming a gate conductor covering a first portion of the work-function layer, the first portion of the work-function layer being on top of the channel region; and removing a second portion of the work-function layer, the second portion of the work-function layer surrounding the first portion of the work-function layer, wherein the removal of the second portion of the work-function layer insulates the first portion of the work-function layer from rest of the work-function layer. 1. A method comprising:creating an opening inside a dielectric layer, said dielectric layer being formed on top of a substrate and said opening exposing a channel region of a transistor in said substrate;depositing a work-function layer lining said opening and covering said channel region;forming a gate conductor covering a first portion of said work-function layer, said first portion of said work-function layer being on top of said channel region; andremoving a second portion of said work-function layer, said second portion of said work-function layer surrounding said first portion of said work-function layer,wherein said removal of said second portion of said work-function layer insulates said first portion of said work-function layer from rest of said work-function layer.2. The method of claim 1 , wherein forming said gate conductor comprises:forming sidewall spacers along sidewalls of said opening;filling said opening, surrounded by said sidewall spacers, with a conductive material to form said gate conductor; andapplying a chemical-mechanical-polishing (CMP) process to remove excess of said conductive material that are ...

LAYERED STRUCTURE WITH FUSE

A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material. 1. A structure , comprising:a substrate;a first electrode in the substrate, wherein a first direction is oriented perpendicular to a top surface of the first electrode, and wherein the first electrode comprises a first electrically conductive material;a first dielectric layer above both the substrate and the first electrode in the first direction, wherein a top surface of the first dielectric layer is further from the top surface of the first electrode than is any other surface of the first dielectric layer, and wherein the first dielectric layer comprises a first dielectric material and a second dielectric material;a second dielectric layer above the first dielectric layer in the first direction, wherein a bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer, and wherein the second dielectric layer comprises the second dielectric material; anda fuse element buried in the first dielectric layer.2. The structure of claim 1 , wherein a bottom surface of the fuse element is in direct physical contact with the top surface of the first electrode.3. The structure of claim 2 , further comprising:a second electrode in ...

Design structure for interconnect structure containing various capping materials for electrical fuse and other related applications

A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

REDUNDANT METAL BARRIER STRUCTURE FOR INTERCONNECT APPLICATIONS

A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive material which are also present within the opening. The redundant diffusion barrier includes a single layered or multilayered structure comprising Ru and a Co-containing material including pure Co or a Co alloy including at least one of N, B and P. 1. A method of forming a semiconductor structure comprising:providing a dielectric material having a dielectric constant of about 4.0 or less located above a substrate, the dielectric material having at least one opening located therein;forming a diffusion barrier within the at least one opening;forming a redundant diffusion barrier layer comprising Ru and a Co-containing material on the diffusion barrier within the at least one opening;filling the remaining portion of the at least one opening with a conductive material, andplanarizing the diffusion barrier, the redundant diffusion barrier layer, and the conductive material to provide a structure in which the diffusion barrier, redundant diffusion barrier layer and the conductive material each has an upper surface that is co-planar to an upper surface of the dielectric material.2. The method of further comprising forming a lower interconnect level located beneath an upper interconnect level including said structure claim 1 , wherein the lower interconnect level and the upper interconnect level are spaced apart in part by a dielectric capping layer.3. The method of wherein said Co-containing material is pure Co.4. The method of wherein said Co-containing material is a Co alloy including one of N claim 1 , P and B.5. The method of wherein said redundant diffusion barrier layer is a bilayer structure comprising a top layer of Ru and a bottom ...

STRUCTURE AND METHOD OF REDUCING ELECTROMIGRATION CRACKING AND EXTRUSION EFFECTS IN SEMICONDUCTOR DEVICES

A structure for reducing electromigration cracking and extrusion effects in semiconductor devices includes a first metal line formed in a first dielectric layer; a cap layer formed over the first metal line and first dielectric layer; a second dielectric layer formed over the cap layer; and a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer. 1. A method of reducing electromigration cracking and extrusion effects in semiconductor devices , the method comprising:forming a first metal line in a first dielectric layer;forming a cap layer over the first metal line and first dielectric layer;forming a second dielectric layer over the cap layer; andforming a void formed in the second dielectric layer, stopping on the cap layer, wherein the void is located in a manner so as to isolate structural damage due to electromigration effects of the first metal line, the effects including one or more of extrusions of metal material from the first metal line and cracks from delamination of the cap layer with respect to the first dielectric layer.2. The method of claim 1 , further comprising forming a sealing dielectric material over the second dielectric layer claim 1 , the sealing dielectric material configured to pinch off upper portions of the void while maintaining lower portions of the void.3. The method of claim 2 , wherein the sealing dielectric material is formed by chemical vapor deposition (CVD).4. The method of claim 3 , wherein the void is localized around an anode end of the first metal line so as to prevent extrusions from the anode end from shorting to an adjacent second metal line formed in the first dielectric layer.5. The method of claim ...

ELECTRICALLY PROGRAMMABLE METAL FUSE

A metal electrically programmable fuse (“eFuse”) includes a metal strip, having a strip width, of a metal line adjoined to wide metal line portions, having widths greater than the metal strip width, at both ends of the metal strip. The strip width can be a lithographic minimum dimension, and the ratio of the length of the metal strip to the strip width is greater than 5 to localize heating around the center of the metal strip during programming. Localization of heating reduces required power for programming the metal eFuse. Further, a gradual temperature gradient is formed during the programming within a portion of the metal strip that is longer than the Blech length so that electromigration of metal gradually occurs reliably at the center portion of the metal strip. Metal line portions are provides at the same level as the metal eFuse to physically block debris generated during programming. 1. A structure comprising an electrically programmable fuse (eFuse) , said eFuse comprising an integral assembly of a metal strip , a first metal line portion , and a second metal line portion without an interface thereamongst , wherein said integral assembly is embedded in a wiring level dielectric material layer , a first end of said metal strip is adjoined to said first metal line portion , a second end of said metal strip is adjoined to said second metal line portion , said first metal line portion and said second metal line portion have widths that are greater than a strip width of said metal strip , and said first metal line portion and said second metal line portion collectively block all line-of-sight horizontal directions from an entirety of sidewalls of said strip portion.2. The structure of claim 1 , wherein said metal strip includes at least one rectangular parallelepiped each having said strip width.3. The structure of claim 2 , wherein said at least one rectangular parallelepiped is a single rectangular parallelepiped that extends between said first metal line ...

SEMICONDUCTOR SWITCHING DEVICE AND METHOD OF MAKING THE SAME

A switching device including a first dielectric layer having a first top surface, two conductive features embedded in the first dielectric layer, each conductive feature having a second top surface that is substantially coplanar with the first top surface of the first dielectric layer, and a set of discrete islands of a low diffusion mobility metal between the two conductive features. The discrete islands of the low diffusion mobility metal may be either on the first top surface or embedded in the first dielectric layer. The electric conductivity across the two conductive features of the switching device increases when a prescribed voltage is applied to the two conductive features. A method of forming such a switching device is also provided. 1. A switching device comprising:a first dielectric layer having a first top surface;two conductive features embedded in the first dielectric layer, each conductive feature having a second top surface that is substantially coplanar with the first top surface of the first dielectric layer; anda set of discrete islands of a low diffusion mobility metal on the first top surface of the first dielectric layer and between the two conductive features.2. The switching device of claim 1 , wherein the electric conductivity across the two conductive features increases when a prescribed voltage is applied to the two conductive features.3. The switching device of claim 1 , wherein the discrete islands of the low diffusion mobility metal are in direct contact with the first top surface.4. The switching device of claim 1 , wherein the low diffusion mobility metal has a value of diffusivity less than 10m/s in the first dielectric layer.5. The switching device of claim 4 , wherein the low diffusion mobility metal is selected from the group consisting of Ru claim 4 , Rh claim 4 , Pd claim 4 , Ag claim 4 , Os claim 4 , Ir claim 4 , Pt claim 4 , Au claim 4 , Co claim 4 , Ta claim 4 , Ti claim 4 , Mn claim 4 , W claim 4 , and alloys comprising at ...

LOW-PROFILE LOCAL INTERCONNECT AND METHOD OF MAKING THE SAME

Embodiments of the present invention provide a structure. The structure includes a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, the gate stacks having spacers formed at sidewalls thereof; and one or more conductive contacts formed directly on top of the semiconductor substrate and interconnecting at least one source/drain of one of the plurality of field-effect-transistors to at least one source/drain of another one of the plurality of field-effect-transistors, wherein the one or more conductive contacts is part of a low-profile local interconnect that has a height lower than a height of the gate stacks. 1. A structure comprising:a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, said gate stacks having spacers formed at sidewalls thereof; andone or more conductive contacts formed directly on top of said semiconductor substrate and interconnecting at least one source/drain of one of said plurality of field-effect-transistors to at least one source/drain of another one of said plurality of field-effect-transistors,wherein said one or more conductive contacts is part of a low-profile local interconnect (LPLI), said LPLI having a height lower than a height of said gate stacks.2. The structure of claim 1 , wherein said one or more conductive contacts of said LPLI are formed directly adjacent to said spacers of said gate stacks.3. The structure of claim 1 , further comprising one or more vias formed on top of said one or more conductive contacts and directly next to said spacers of said gate stacks.4. The structure of claim 3 , wherein said one or more vias are made of a same material as that of said one or more conductive contacts claim 3 , and have a same height as said height of said gate stacks.5. The structure of claim 3 , wherein said gate stacks including a cap layer on top thereof claim 3 , further comprising:a conductive path line formed directly above, ...

ENHANCED DIFFUSION BARRIER FOR INTERCONNECT STRUCTURES

Alternative methods of fabricating an interconnect structure in which an enhanced diffusion barrier including an in-situ formed metal nitride liner formed between an interconnect dielectric material and an overlying metal diffusion barrier liner are provided. In one embodiment, the method includes forming at least one opening into an interconnect dielectric material. A nitrogen enriched dielectric surface layer is formed within exposed surfaces of the interconnect dielectric material utilizing thermal nitridation. A metal diffusion barrier liner is formed on the nitrogen enriched dielectric surface. During and/or after the formation of the metal diffusion barrier liner, a metal nitride liner forms in-situ in a lower region of the metal diffusion barrier liner. A conductive material is then formed on the metal diffusion barrier liner. The conductive material, the metal diffusion barrier liner and the metal nitride liner that are located outside of the at least one opening are removed to provide a planarized conductive material, a planarized metal diffusion barrier liner and a planarized metal nitride liner, each of which includes an upper surface that is co-planar with the nitrogen enriched dielectric surface layer of the interconnect dielectric material. 1. A method of forming an interconnect structure , said method comprising:forming at least one opening into an interconnect dielectric material;forming a nitrogen enriched dielectric surface layer within exposed surfaces of said interconnect dielectric material, wherein said nitrogen enriched dielectric surface layer is formed by thermal nitridation in a non-plasma nitrogen-containing ambient, said nitrogen enriched dielectric surface layer has a higher nitrogen content than a remaining portion of the interconnect dielectric material;forming a metal diffusion barrier liner on said nitrogen enriched dielectric surface layer, wherein during and/or after said forming the metal diffusion barrier liner, a metal nitride ...

Interconnect structures and methods for back end of the line integration

A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer. 1. A method of forming a semiconductor structure , comprising:forming a sacrificial conductive material layer;forming a trench in the sacrificial conductive material layer;forming a conductive feature in the trench;removing the sacrificial conductive material layer selective to the conductive feature; andforming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer.2. The method of claim 1 , further comprising:forming a second sacrificial conductive material layer on the sacrificial conductive material layer and the conductive feature;forming a second trench in the second sacrificial conductive material layer; andforming a second sacrificial conductive feature in the second trench and contacting the conductive feature.3. The method of claim 2 , further comprising removing the second sacrificial conductive material layer selective to the second conductive feature.4. The method of claim 3 , wherein the forming the insulating layer comprises forming the insulating layer around the conductive feature and the second conductive feature such that the conductive feature and the second conductive feature are embedded in the insulating layer.5. The method of claim 1 , wherein the forming the conductive feature in the trench comprises electroplating.6. The method of claim 5 , further comprising using the sacrificial conductive material layer as at least one of a seed material and an anode for the electroplating ...

SURFACE REPAIR STRUCTURE AND PROCESS FOR INTERCONNECT APPLICATIONS

A method is provided which includes providing a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material and the upper surface of the at least one conductive material has hollow-metal related defects that extend inward into the at least one conductive material; and filling the hollow-metal related defects with a surface repair material. 1. A method of fabricating an interconnect structure comprising:providing a dielectric material having a dielectric constant of about 4.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material and the upper surface of the at least one conductive material has hollow-metal related defects that extend inward into the at least one conductive material; andfilling said hollow-metal related defects with a surface repair material.2. The method of wherein said filling the hollow-metal related defects with the surface repair material includes selecting one of Ru claim 1 , Co claim 1 , Rh claim 1 , Pt claim 1 , W claim 1 , and Ir as said surface repair material.3. The method of wherein said filling the hollow-metal related defects with the surface repair material includes selecting a alloy of Co(W claim 1 ,P claim 1 ,B) as said surface repair material.4. The method of wherein said filling the hollow-metal defects comprises a deposition selected from the group consisting of chemical vapor deposition (CVD) claim 1 , plasma enhanced chemical vapor deposition (PECVD) claim 1 , and atomic layer deposition (ALD).5. The method of wherein said deposition is performed at a temperature of 200° C. or less.6. The method of wherein said deposition is performed at a temperature of 150° C. of less.7. The method of wherein said filling the ...

Discontinuous/non-uniform metal cap structure and process for interconnect integration

A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform.

BORDERLESS INTERCONNECT LINE STRUCTURE SELF-ALIGNED TO UPPER AND LOWER LEVEL CONTACT VIAS

A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed. 1. A method of forming a structure comprising:forming an underlying metal via embedded in an underlying dielectric material layer on a substrate;depositing a metal layer on a top surface of said underlying dielectric material layer;patterning said metal layer to form a metal block having a facing pair of sidewalls; andetching an upper portion of said underlying metal via within an area that does not underlie said metal block.2. The method of claim 1 , further comprising forming an integrated line and via structure of integral construction by removing an upper portion of said metal block claim 1 , wherein said integrated line and via structure includes a metal line having a substantially constant width and at least one overlying metal via having said substantially constant width.3. The method of claim 2 , wherein said facing pair of sidewalls is spaced from each other by said substantially constant width.4. The method of claim 2 , wherein a remaining portion of said upper portion of said underlying metal via after said etching forms an upper underlying metal via portion that has a pair of sidewalls laterally ...

Formation of alloy liner by reaction of diffusion barrier and seed layer for interconnect application

An interconnect structure including an alloy liner positioned directly between a diffusion barrier and a Cu alloy seed layer as well as methods for forming such an interconnect structure are provided. The alloy liner of the present invention is formed by thermally reacting a previously deposited diffusion barrier metal alloy layer with an overlying Cu alloy seed layer. During the thermal reaction, the metal alloys from the both the diffusion barrier and the Cu alloys seed layer react forming a metal alloy reaction product between the diffusion barrier and the Cu seed layer.

Hybrid Copper Interconnect Structure and Method of Fabricating Same

A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region. The copper regions containing the different impurities levels can be achieved utilizing a combination of physical vapor deposition of a copper region having a low impurity level (i.e., less than 20 ppm) and copper reflow, with electroplating another copper region having a high impurity level (i.e., 100 ppm or greater). 1. An interconnect structure comprising:a patterned dielectric material having at least one opening located therein;a dual material liner located at least on sidewalls of the patterned dielectric material within the at least one opening;a first copper region containing a first impurity level located within a bottom region of said at least one opening; anda second copper region containing a second impurity level located within a top region of said at least one opening and atop the first copper region, wherein said first impurity level of the first copper region is different from the second impurity level of the second copper region.2. The interconnect structure of claim 1 , wherein said first impurity level of said first copper region is greater than the second impurity level of said second copper region.3. The ...

SEMICONDUCTOR STRUCTURE HAVING A WETTING LAYER

A semiconductor structure which includes a semiconductor substrate and a metal gate structure formed in a trench or via on the semiconductor substrate. The metal gate structure includes a gate dielectric; a wetting layer selected from the group consisting of cobalt and nickel on the gate dielectric lining the trench or via and having an oxygen content of no more than about 200 ppm (parts per million) oxygen; and an aluminum layer to fill the remainder of the trench or via. There is also disclosed a method of forming a semiconductor structure in which a wetting layer is formed from cobalt amidinate or nickel amidinate deposited by a chemical vapor deposition process. 1. A semiconductor structure comprising:a semiconductor substrate; anda metal gate structure formed in a trench or via on the semiconductor substrate, the metal gate structure comprising:a gate dielectric;a wetting layer selected from the group consisting of cobalt and nickel on the gate dielectric lining the trench or via and having an oxygen content of no more than about 200 ppm (parts per million) oxygen; andan aluminum layer to fill the remainder of the trench or via.2. The semiconductor structure of wherein the wetting layer is oxygen free.3. The semiconductor structure of wherein the wetting layer has a thickness of 5 to 20 angstroms.4. The semiconductor structure of further comprising a metallic layer between the gate dielectric and the wetting layer.5. The semiconductor structure of wherein the metallic layer is a workfunction metal and the semiconductor structure is a PFET claim 4 , the workfunction metal including a dual layer comprising a first layer selected from the group consisting of titanium nitride claim 4 , ruthenium and tantalum nitride and a second layer selected from the group consisting of tantalum carbide and titanium aluminum.6. The semiconductor structure of wherein the wetting layer is directly on the second layer of the workfunction metal.7. The semiconductor structure of ...

SIZE-FILTERED MULTIMETAL STRUCTURES

A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width. 1. A structure comprising:a dielectric layer located on a substrate;a first metallic structure comprising a first metallic portion including a first metallic material and embedded in said dielectric layer; anda second metallic structure comprising a second metallic portion including a second metallic material different from said first metallic material and embedded in said dielectric layer.2. The structure of claim 1 , wherein a topmost surface of said first metal structure is coplanar with a topmost surface of said second metal structure.3. The structure of claim 1 , wherein said first metallic structure further comprises at least one first metallic liner having first outer sidewalls contacting said dielectric layer and first inner sidewalls contacting said first metallic portion claim 1 , and said second metallic structure further comprises at least one second metallic liner having second outer sidewalls contacting said dielectric layer and second inner sidewalls contacting said second metallic portion.4. The structure of ...

Tungsten metallization: structure and fabrication of same

A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur.

SEMICONDUCTOR CAPACITOR

A semiconductor capacitor and its method of fabrication are disclosed. A non-linear nitride layer is used to increase the surface area of a capacitor plate, resulting in increased capacitance without increase in chip area used for the capacitor. 19-. (canceled)10. A method of fabricating a semiconductor capacitor , comprising:forming a cavity in a first dielectric layer;depositing a nitride stack comprising a slow-etch nitride layer disposed between two fast-etch nitride layers in the cavity;etching a portion of the nitride stack within the cavity;depositing a metal plug in the cavity;removing the fast-etch nitride layers of the nitride stack while preserving the slow-etch nitride layer of the nitride stack;depositing a first metal layer over the slow-etch nitride layer;depositing a second dielectric layer over the first metal layer; anddepositing a second metal layer over the second dielectric layer.11. The method of claim 10 , further comprising performing an isotropic etch on the second metal layer.12. The method of claim 10 , wherein depositing a nitride stack comprises:depositing a first fast-etch nitride layer having a thickness ranging from about 60 angstroms to about 240 angstroms;depositing a slow-etch nitride layer over the first fast-etch nitride layer, the slow-etch nitride layer having a thickness ranging from about 40 angstroms to about 120 angstroms; anddepositing a second fast-etch nitride layer over the slow-etch nitride layer, the second fast-etch nitride layer having a thickness ranging from about 60 angstroms to about 240 angstroms.13. The method of claim 10 , wherein depositing the fast-etch nitride layers and the slow-etch nitride layer is performed via atomic layer deposition.14. The method of claim 10 , wherein depositing the fast-etch nitride layers and the slow-etch nitride layer is performed via chemical vapor deposition.15. The method of claim 10 , wherein depositing a first metal layer over the slow-etch nitride layer is performed via ...

INTEGRATED CIRCUIT STRUCTURE HAVING SELECTIVELY FORMED METAL CAP

Methods of forming an integrated circuit structure utilizing a selectively formed and at least partially oxidized metal cap over a gate, and associated structures. In one embodiment, a method includes providing a precursor structure including a transistor having a metal gate; forming an etch stop layer over an exposed portion of the metal gate; at least partially oxidizing the etch stop layer; and forming a dielectric layer over the at least partially oxidized etch stop layer. 1. A method of forming an integrated circuit structure , the method comprising:providing a precursor structure including a transistor having a metal gate and spacers adjacent the metal gate;forming an etch stop layer over an exposed portion of the metal gate;at least partially oxidizing the etch stop layer; andforming a dielectric layer over the at least partially oxidized etch stop layer.2. The method of claim 1 , further comprising:forming an opening in the dielectric layer extending to the etch stop layer; andforming a contact in the opening.3. The method of claim 2 , wherein the forming of the opening in the dielectric layer includes etching the dielectric layer claim 2 , wherein the etch stop layer prevents etching of the metal gate during the etching claim 2 , and wherein the etch stop layer physically and electrically isolates the metal gate from the contact after the forming of the contact.4. The method of claim 1 , wherein the etch stop layer is selectively formed over only the exposed portion of the metal gate as a metal layer.5. The method of claim 4 , wherein the at least partially oxidizing of the etch stop layer includes oxidizing substantially an entirety of the etch stop layer.6. The method of claim 4 , wherein the at least partially oxidizing of the etch stop layer includes oxidizing only an outer portion of the etch stop layer.7. The method of claim 4 , wherein the metal layer includes at least one of cobalt (Co) claim 4 , manganese (Mn) claim 4 , tungsten (W) claim 4 , ...

Electrical Fuse With Metal Line Migration

An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is coupled to the first contact and to the second contact, that has a third electromigration resistance that is lower than the second electromigration resistance. The first circuit element is coupled to the first contact and the second circuit element coupled to the second contact. The fuse is configured to conduct a programming current from the first contact to the second contact through the metal line. Further, the programming current causes the metal line to electromigrate away from the second contact to electrically isolate the second circuit element from the first circuit element. 1. A circuit apparatus comprising:a fuse including a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is coupled to the first contact and to the second contact, that has a third electromigration resistance that is lower than the second electromigration resistance;a first circuit element coupled to the first contact; anda second circuit element coupled to the second contact, wherein the fuse is configured to conduct a programming current from the first contact to the second contact through the metal line and wherein the programming current causes the metal line to electromigrate away from the second contact to electrically isolate the second circuit element from the first circuit element.2. The circuit apparatus of claim 1 , wherein the programming current is a first programming current claim 1 , wherein the fuse is configured to conduct a second programming current through the metal line and wherein the first programming current heats the metal line to aid the electromigration of the ...

Interconnect Structure With An Electromigration and Stress Migration Enhancement Liner

An electromigration and stress migration enhancement liner is provided for use in an interconnect structure. The liner includes a metal that has a thickness at a bottom of the at least one via opening and on an exposed portion of an underlying conductive feature that is greater than a remaining thickness that is located on exposed sidewalls of the interconnect dielectric material. The thinner portion of the electromigration and stress migration enhancement liner is located between the interconnect dielectric material and an overlying diffusion barrier. The thicker portion of the electromigration and stress migration enhancement liner is located between the underlying conductive feature and the diffusion barrier as well as between an adjacent dielectric capping layer and the diffusion barrier. The remainder of the at least one via opening is filled with an adhesion layer and a conductive material. 1. An interconnect structure comprising:a first interconnect dielectric material having at least one conductive feature located therein;a dielectric capping layer located atop the first interconnect dielectric material and a portion of the at least one conductive feature;a second interconnect dielectric material having at least one via opening that is in contact with an exposed portion of the at least one conductive feature located on said dielectric capping layer;an electromigration and stress migration enhancement liner located within the at least one via opening, said electromigration and stress migration enhancement liner comprising a metal that has a thickness at a bottom of said at least one via opening and on the exposed portion of the at least one conductive feature that is at least 3 times greater than a remaining thickness that is located on exposed sidewalls of said second interconnect dielectric material;a diffusion barrier located on the electromigration and stress migration enhancement liner and within said at least one via opening;an adhesion liner located on ...

Metal Alloy Cap Integration

A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy cap, and a capping layer. 1. A metal interconnect structure , comprising:a dielectric layer having a recessed line pattern;a liner material on sidewalls and bottom surfaces of the recessed line pattern;a copper material filling at least a portion of the recessed line pattern;an alloy cap selectively on a top portion of the recessed line pattern; anda capping layer on the dielectric layer and the alloy cap, wherein alloy elements are absent from sidewalls of the recessed line pattern.2. The structure of claim 1 , wherein the alloy cap is thin claim 1 , having a thickness in the range of 1 nm to 6 nm.3. The structure of claim 1 , wherein the alloy cap is thick claim 1 , having a thickness in the range of 3 nm to 10 nm claim 1 , and at least a portion of the alloy cap is embedded in the copper material.4. The structure of claim 1 , wherein the alloy cap is comprised of a material selected from the group of manganese claim 1 , copper-manganese claim 1 , cobalt claim 1 , aluminum claim 1 , iridium claim 1 , ruthenium claim 1 , cobalt-tungsten-phosphorus claim 1 , platinum and combinations thereof.5. The structure of claim 1 , wherein the liner material is comprised of cobalt claim 1 , ...

Use of Gas Cluster Ion Beam To Reduce Metal Void Formation In Interconnect Structures

A gas cluster ion beam process is used to reduce and/or even eliminate metal void formation in an interconnect structure. In one embodiment, gas cluster ion beam etching forms a chamfer opening in an interconnect dielectric material. In another embodiment, gas cluster ion beam etching reduces the overhang profile of a diffusion barrier or a multilayered stack of a diffusion barrier and a plating seed layer that is formed within an opening located in an interconnect dielectric material. In yet another embodiment, a gas cluster ion beam process deactivates a surface of an interconnect dielectric material that is located at upper corners of an opening that is formed therein. In this embodiment, the gas cluster ion beam process deposits a material that deactivates the upper corners of each opening that is formed into an interconnect dielectric material. 1. A method of reducing metal void formation in an interconnect structure comprising:forming a plurality of openings within an interconnect dielectric material, each opening of said plurality of openings having upper corners that are substantially square;performing a gas cluster ion beam etching process to said upper corners of each opening to provide beveled corners, said gas cluster ion beam etching process including beams of gas cluster ions each of which has an angle incident to the upper surface of the interconnect dielectric material of 5° or less;forming a diffusion barrier within each opening of the plurality of openings;forming a conductive material atop the diffusion barrier; andremoving portions of the diffusion barrier and the conductive material that extend outside of each opening of the plurality of openings to provide a planarized interconnect structure.2. The method of claim 1 , wherein said gas cluster ion beam etching process is performed utilizing a reactive gas.3. The method of claim 2 , wherein said reactive gas comprises at least one of nitrogen trifluoride (NF) claim 2 , carbon tetrafluoride (CF) ...

Metal Alloy Cap Integration

A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. The metal alloy capping layer is also reflowed on the copper. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy capping layer, and a dielectric cap. 1. A method of forming a metal interconnect structure , comprising steps of:forming a liner on top surfaces of a dielectric material and on sidewalls and bottom surfaces of a recessed line pattern in the dielectric material;depositing a copper seed layer on the liner;reflowing the deposited copper seed layer on the liner;filling at least a portion of the recessed line pattern with copper;forming an alloy capping layer on the copper comprising an alloying element and copper;reflowing the deposited alloy capping layer on the copper;depositing an electroplated copper layer on the reflowed alloy capping layer;planarizing the electroplated copper layer to the top surfaces of the dielectric material; anddepositing a dielectric cap, wherein the alloy element in the structure is segregated and distributed along an interface between the reflowed copper and the dielectric cap.2. The method of wherein between the steps of planarizing and depositing a dielectric cap claim 1 , further comprising polishing down to the alloy capping layer at a bottom surface of the electroplated copper layer.3. The ...

IGZO NANOPARTICLE AND MANUFACTURING METHOD AND USE THEREOF

The present disclosure provides an IGZO nanoparticle, including an InGaZnOcrystal structure and a trace element, wherein the InGaZnOcrystal structure has a formula represented by formula: x(InO)−y(GaO)−z(ZnO), wherein x:y:z=1:1:0.5-2, and the trace element includes boron and/or aluminum, which is present in an amount of about 100-1000 ppm. The present disclosure also provides a manufacturing method for the IGZO nanoparticle and a sputter target containing the IGZO particles. 1. An indium gallium zinc oxide (IGZO) nanoparticle , comprising an InGaZnOcrystal structure and a trace element , wherein the InGaZnOcrystal structure has a formula represented by formula (I):{'br': None, 'i': x', 'y', 'z, 'sub': 2', '3', '2', '3, '(InO)−(GaO)−(ZnO)\u2003\u2003(I),'}wherein x:y:z=1:1:0.5-2, and the trace element includes boron and/or aluminum, which is present in an amount of about 100-1000 ppm.2. The indium gallium zinc oxide (IGZO) nanoparticle according to claim 1 , having a purity of more than about 99%.3. The indium gallium zinc oxide (IGZO) nanoparticle according to claim 1 , wherein the indium gallium zinc oxide (IGZO) nanoparticle is a single phase of InGaZnOcrystal structure.4. The indium gallium zinc oxide (IGZO) nanoparticle according to claim 1 , wherein the indium gallium zinc oxide (IGZO) nanoparticle is free of ZnGaOspinel phase.5. The indium gallium zinc oxide (IGZO) nanoparticle according to claim 1 , wherein the indium gallium zinc oxide (IGZO) nanoparticle has an average particle size of smaller than about 100 nm and a l/d aspect ratio of about 1.6. A sputter target claim 1 , prepared by compression molding and sintering the indium gallium zinc oxide (IGZO) nanoparticle according to .7. A manufacturing method for an indium gallium zinc oxide (IGZO) nanoparticle claim 1 , comprising:dissolving an indium compound, a gallium compound, and a zinc compound in a solvent, wherein the indium compound, the gallium compound, and the zinc compound have an indium:gallium ...

E-FUSES CONTAINING AT LEAST ONE UNDERLYING TUNGSTEN CONTACT FOR PROGRAMMING

Semiconductor structures are provided containing an electronic fuse (E-fuse) that includes a fuse element and at least one underlying tungsten contact that is used for programming the fuse element. In some embodiments, a pair of neighboring tungsten contacts is used for programming the fuse element. In another embodiment, an overlying conductive region can be used in conjunction with one of the underlying tungsten contacts to program the fuse element. In the disclosed structures, the fuse element is in direct contact with upper surfaces of a pair of underlying tungsten contacts. In one embodiment, the semiconductor structures may include an interconnect level located atop the fuse element. The interconnect level has a plurality of conductive regions embedded therein. In other embodiments, the fuse element is located within an interconnect level that is located atop the tungsten contacts. 1. A semiconductor structure comprising:a plurality of tungsten contacts located within a dielectric material;a fuse element located atop a portion of the dielectric material and spanning a pair of neighboring tungsten contacts of the plurality of tungsten contacts;a dielectric capping layer located atop the fuse element, the dielectric material and any remaining tungsten contacts of the plurality of tungsten contacts; andan interconnect level located atop the dielectric capping layer, wherein said interconnect level comprises another dielectric material having at least one conductive region located therein, wherein at least one of said tungsten contacts of said pair of neighboring tungsten contacts is used for programming said fuse element.2. The semiconductor structure of claim 1 , wherein both said tungsten contacts of said pair of neighboring tungsten contacts are used for programming said fuse element.3. The semiconductor structure of claim 1 , wherein said at least one conductive region is used for programming and represents an anode of an E-Fuse claim 1 , and one of said ...

FORMATION OF AIR GAP WITH PROTECTION OF METAL LINES

A microelectronic substrate which includes a dielectric layer overlying a semiconductor region of a substrate, the dielectric layer having an exposed top surface; a plurality of metal lines of a first metal disposed within the dielectric layer, each metal line having edges and a surface exposed at the top surface of the dielectric layer; a dielectric cap layer having a first portion overlying the surfaces of the metal lines and a second portion overlying the dielectric layer between the metal lines, the first portion has a first height above the surface of the dielectric layer, and the second portion has a second height above the surface of the dielectric layer, the second height being greater than the first height; and an air gap disposed between the metal lines, the air gap underlying the second portion of the cap layer. 1. A microelectronic substrate , comprising:a dielectric layer overlying a semiconductor region of a substrate, the dielectric layer having an exposed top surface;a plurality of metal lines consisting essentially of a first metal disposed within the dielectric layer, each metal line having edges and a surface exposed at the top surface of the dielectric layer;a dielectric cap layer having a first portion overlying the surfaces of the metal lines and a second portion overlying the dielectric layer between the metal lines, the first portion has a first height above the surface of the dielectric layer, and the second portion has a second height above the surface of the dielectric layer, the second height being greater than the first height; andat least one air gap devoid of the dielectric layer disposed between the metal lines, the air gap underlying the second portion of the cap layer.2. The microelectronic substrate as claimed in claim 1 , wherein the metal lines consist essentially of copper.3. The microelectronic substrate as claimed in claim 1 , wherein the cap layer includes at least one of silicon carbide claim 1 , silicon nitride claim 1 , or ...

TUNGSTEN METALLIZATION: STRUCTURE AND FABRICATION OF SAME

A local interconnect structure is provided in which a tungsten region, i.e., tungsten stud, that is formed within a middle-of-the-line (MOL) dielectric material is not damaged and/or contaminated during a multiple interconnect patterning process. This is achieved in the present disclosure by forming a self-aligned tungsten nitride passivation layer within a topmost surface and upper sidewalls portions of the tungsten region that extend above a MOL dielectric material which includes a first interconnect pattern formed therein. During the formation of the self-aligned tungsten nitride passivation layer, a nitrogen enriched dielectric surface also forms within exposed surface of the MOL dielectric material. A second interconnect pattern is then formed adjacent to, but not connect with, the first interconnect pattern. Because of the presence of the self-aligned tungsten nitride passivation layer on the tungsten region, no damaging and/or contamination of the tungsten region can occur. 1. A method of forming a semiconductor structure comprising:forming a tungsten region within a middle-of-the-line (MOL) dielectric material, said tungsten region having a topmost surface that is coplanar with an upper surface of the MOL dielectric material;forming another dielectric material atop the MOL dielectric and the tungsten region;forming a first interconnect pattern into one portion of the another dielectric material and the MOL dielectric material, wherein upper sidewall portions of the tungsten region are exposed;performing a nitridation process providing a self-aligned tungsten nitride passivation layer within the topmost surface and upper sidewall portions of the tungsten region, and a nitrogen enriched dielectric surface within exposed surfaces of both the another dielectric material and the MOL dielectric material;forming a second interconnect pattern into another portion of the another dielectric material and the MOL dielectric material; andfilling remaining portions of the ...

REPLACEMENT GATE MOSFET WITH RAISED SOURCE AND DRAIN

A disposable dielectric spacer is formed on sidewalls of a disposable material stack. Raised source/drain regions are formed on planar source/drain regions by selective epitaxy. The disposable dielectric spacer is removed to expose portions of a semiconductor layer between the disposable material stack and the source/drain regions including the raised source/drain regions. Dopant ions are implanted to form source/drain extension regions in the exposed portions of the semiconductor layer. A gate-level dielectric layer is deposited and planarized. The disposable material stack is removed and a gate stack including a gate dielectric and a gate electrode fill a cavity formed by removal of the disposable material stack. Optionally, an inner dielectric spacer may be formed on sidewalls of the gate-level dielectric layer within the cavity prior to formation of the gate stack to tailor a gate length of a field effect transistor. 1. A semiconductor structure comprising a field effect transistor located on a semiconductor substrate , said field effect transistor comprising:a semiconductor portion including a body region, source/drain extension regions laterally contacting said body region, and planar source/drain regions laterally contacting said source/drain extension regions and having a same type of doping as said source/drain extension regions;a gate stack, from bottom to top, of a gate dielectric and a gate conductor, wherein said gate stack contacts said body region and a portion of each of said source/drain extension regions; andraised source/drain regions having a same type of doping as said source/drain extension regions, wherein each of said raised source/drain regions contacts a top surface of said planar source/drain regions and is laterally spaced from said gate stack by a same distance.2. The semiconductor structure of claim 1 , further comprising a gate-level dielectric layer contacting top surfaces of said source/drain extension region claim 1 , top surfaces ...

3D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY

The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided. 1. A capacitor , comprising:an insulating layer on a substrate, said insulating layer including a via having sidewalls and a bottom;a first electrode overlying said sidewalls and at least a portion of said bottom of said via;a first high-k dielectric material layer overlying said first electrode;a first conductive plate over said first high-k dielectric material layer;a second high-k dielectric material layer formed to overlie the first conductive plate and to leave a remaining portion of said via unfilled; anda second electrode formed in said remaining portion of said via, wherein said first conductive plate is substantially parallel to said first electrode and is not in contact with said first and second electrodes.2. The capacitor of claim 1 , further comprising a second conductive plate and a third high-k dielectric material layer between said second high-k dielectric material layer and said second electrode claim 1 , wherein said second conductive plate is substantially parallel to said first electrode and is not in contact with said first and second electrodes and said first conductive plate.3. The capacitor of claim 1 , further comprising:a lower ...

3D VIA CAPACITOR WITH A FLOATING CONDUCTIVE PLATE FOR IMPROVED RELIABILITY

The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided. 1. A method of forming a capacitor , comprising:providing a substrate having a lower interconnect level including a first dielectric layer having a first conductive feature embedded therein, a first dielectric capping layer on said lower interconnect level, an insulating layer on said first dielectric capping layer, and a patterned hardmask layer having a top surface on said insulating layer, wherein said insulating layer has a via that extends partially through said first dielectric capping layer, said via having sidewalls and a bottom;forming a first electrode layer over said sidewalls and said bottom of said via and said top surface of said hardmask layer;forming a first high-k dielectric material layer over said first electrode layer;forming a first conductive plate layer over said first high-k dielectric material layer;forming a via gouging at said bottom of said via by removing a portion of said first conductive plate layer, a portion of said first high-k dielectric material layer, a portion of said first electrode layer, a portion of said first dielectric capping layer and a portion of said first conductive feature, said via gouging having ...

BORDERLESS CONTACT STRUCTURE EMPLOYING DUAL ETCH STOP LAYERS

Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed. 1. A semiconductor structure comprising:at least one gate structure located on a semiconductor substrate, wherein each of said at least one gate structure includes, from bottom to top, a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric;a second etch stop layer located on said at least one gate structure;a first contact-level dielectric layer and a second contact-level dielectric layer located over said second etch stop layer;at least one gate contact via structure embedded in said first and second contact-level dielectric layers, wherein each of said at least one gate contact via structure extends through said first and second contact-level dielectric layers, said second etch stop layer, one of said at least one gate cap dielectric, and one of said at least one first etch stop layer; andat least one source/drain contact via structure embedded in said first and second contact-level dielectric layers, wherein each of said at least one source/drain contact via structure extends through said ...

ELECTRICAL FUSE STRUCTURE AND METHOD OF FABRICATING SAME

A high programming efficiency electrical fuse is provided utilizing a dual damascene structure located atop a metal layer. The dual damascene structure includes a patterned dielectric material having a line opening located above and connected to an underlying via opening. The via opening is located atop and is connected to the metal layer. The dual damascene structure also includes a conductive feature within the line opening and the via opening. Dielectric spacers are also present within the line opening and the via opening. The dielectric spacers are present on vertical sidewalls of the patterned dielectric material and separate the conductive feature from the patterned dielectric material. The presence of the dielectric spacers within the line opening and the via opening reduces the area in which the conductive feature is formed. As such, a high programming efficiency electrical fuse is provided in which space is saved. 1. An electrical fuse structure comprising:a patterned dielectric material including a via opening and a line opening located atop a metal layer, wherein the line opening is located above and connected to the via opening and the via opening is located above and connected to the metal layer;a conductive feature including at least a diffusion barrier and a conductive material present in the via opening and line opening; anddielectric spacers located within the via opening and the line opening and separating the conductive feature from sidewalls of the patterned dielectric material.2. The electrical fuse structure of further comprising a patterned dielectric capping layer present between the metal layer and the patterned dielectric material.3. The electrical fuse structure of wherein a base of each dielectric spacer within the via opening is located directly on an exposed surface of the patterned dielectric capping layer.4. The electrical fuse structure of wherein a base of each dielectric spacer within the via opening is located directly on an ...

INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS, AND DESIGN STRUCTURE THEREOF

A structure and design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure. 1. An interconnect structure comprising:a first macro having a first e-fuse programmability comprising an upper wiring layer capped by a first capping material; anda second macro having a second e-fuse programmability comprising an upper wiring layer capped by a second capping material having interfacial properties which are different than that of the first macro.2. The interconnect structure of claim 1 , wherein the first macro further includes an interface comprising the upper wiring layer and the first capping material claim 1 ,the second macro further includes an interface comprising the upper wiring layer and the second capping material, andthe first capping material is different than the second capping material.3. The interconnect structure of claim 2 , wherein the first capping material comprises SiN and the second capping material comprises one of: Co(W claim 2 ,P claim 2 ,B) claim 2 , Ru claim 2 , Ir claim 2 , Rh and Pt.4. The interconnect structure of claim 2 , wherein the second capping material and/or the upper wiring layer of the second macro is damaged to degrade adhesion between the second capping material and the upper wiring layer of the second macro.5. The interconnect structure of claim 1 , wherein the first capping material and the second capping material is a same material claim 1 , and the second capping material and/or the upper wiring layer of the second macro is damaged thereby providing a degraded electromigration (EM) resistance than that of the first macro.6. The interconnect structure of claim 5 , wherein ...

ENHANCED DIFFUSION BARRIER FOR INTERCONNECT STRUCTURES

Alternative methods of fabricating an interconnect structure in which an enhanced diffusion barrier including an in-situ formed metal nitride liner formed between an interconnect dielectric material and an overlying metal diffusion barrier liner are provided. In one embodiment, at least one opening is formed into an interconnect dielectric material. A nitrogen enriched dielectric surface layer is formed within exposed surfaces of the interconnect dielectric material utilizing thermal nitridation. A metal diffusion barrier liner is the formed. During and/or after the formation of the metal diffusion barrier liner, a metal nitride liner forms in-situ in a lower region of the metal diffusion barrier liner. A conductive material is then formed on the metal diffusion barrier liner. The conductive material, the metal diffusion barrier liner and the metal nitride liner that are located outside of the at least one opening are removed to provide a planarized structure. 1. An interconnect structure comprising:an interconnect dielectric material comprising at least one opening located therein, wherein said interconnect dielectric material has undamaged exposed surfaces;a conductive material located within the at least one opening, said conductive material is separated from the interconnect dielectric material by a diffusion barrier comprising at least an in-situ formed metal nitride liner and an overlying metal diffusion barrier liner.2. The interconnect structure of claim 1 , wherein said undamaged exposed surfaces are nitrogen enriched dielectric surfaces.3. The interconnect structure of claim 1 , further comprising a second metal nitride located between the in-situ formed metal nitride liner and the overlying metal diffusion barrier liner.4. The interconnect structure of claim 3 , wherein said in-situ formed metal nitride liner and the second metal nitride liner comprise the same metal claim 3 , but with a different nitrogen content.5. The interconnect structure of claim 1 ...

Borderless contact structure

A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.

STRUCTURE FOR NANO-SCALE METALLIZATION AND METHOD FOR FABRICATING SAME

A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography. 1. An interconnect structure comprising:at least two layers on a substrate, said layers comprising metal interconnect structure embedded within dielectric material, each of said layers having at least one via that extends to the top of said layer and at least one line formed along the bottom of said layer,wherein said at least one via of the lower of said layers extends into the upper of said layers.2. The interconnect structure of wherein said at least one via of said upper layer extends to said at least one via of the lower of said layers.3. The interconnect structure of further comprising an adhesion layer formed between said at least two layers.4. The interconnect structure of wherein a surface of said at least one line of said upper layer is in direct contact with an adhesion layer claim 1 , which adhesion layer is in direct contact with dielectric material of said lower layer.5. An interconnect structure comprising:at least two dielectric layers on a substrate, said at least two dielectric layers each comprising a metal via and a metal line within a single layer of dielectric material, wherein said metal line of each said at least two dielectric layers is along the bottom of its respective dielectric layer.6. The interconnect structure of wherein said metal via of the upper of said at least two dielectric layers consists essentially of tungsten.7. The interconnect structure of wherein said metal line of the upper of said at least two ...

DUAL-METAL SELF-ALIGNED WIRES AND VIAS

Method of forming a semiconductor structure which includes forming first conductive spacers on a semiconductor substrate; forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers; recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers; depositing an ILD to cover the first and second spacers except for an exposed edge of the first conductive spacers; patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD; and filling the recesses with an insulating material to leave unrecessed edges of the first conductive spacers as vias to subsequent wiring features. 1. A method of forming a semiconductor structure comprising:forming first conductive spacers on a semiconductor substrate;forming second conductive spacers with respect to the first conductive spacers, at least one of the second conductive spacers adjacent to and in contact with each of the first conductive spacers to form combined conductive spacers;recessing the second conductive spacers with respect to the first conductive spacers so that the first conductive spacers extend beyond the second conductive spacers;depositing an interlayer dielectric (ILD) to cover the first and second spacers except for an exposed edge of the first conductive spacers;patterning the exposed edges of the first conductive spacers to recess the edges of the first conductive spacers in predetermined locations to form recesses with respect to the ILD and unrecessed edges with respect to the ILD; andfilling the recesses with an insulating material to leave the un-recessed edges of the first conductive spacers as vias to subsequent wiring ...

METALLIC CAPPED INTERCONNECT STRUCTURE WITH HIGH ELECTROMIGRATION RESISTANCE AND LOW RESISTIVITY

An interconnect structure including a metallic cap that covers 80 to 99% of the entire surface of an underlying conductive metal feature is provided utilizing a metal reflow process. Laterally extending portions of the conductive metal feature are located on vertical edges of the metallic cap, and each of the laterally extending portions of the conductive metal feature has an uppermost surface that is coplanar with an uppermost surface of the metallic cap. 1. An interconnect structure comprising:an interconnect dielectric material having an opening located therein;a diffusion barrier located on wall surfaces of the interconnect dielectric material within the opening;a conductive metal feature located on said diffusion barrier and partially filling said opening; anda metallic cap located on a portion of the conductive metal feature within said opening, wherein said conductive metal feature has laterally extending portions located on each vertical edge of the metallic cap, and each of the laterally extending portions of the conductive metal feature has an uppermost surface that is coplanar with an uppermost surface of the metallic cap.2. The interconnect structure of claim 1 , wherein each laterally extending portion of the conductive metal feature is positioned between one vertical edge of said metallic cap and an upper portion of said diffusion barrier.3. The interconnect structure of claim 1 , wherein the uppermost surface of each laterally extending portion of the conductive metal feature and the uppermost surface of the metallic cap are coplanar with an uppermost surface of the interconnect dielectric material.4. The interconnect structure of claim 1 , wherein said metallic cap covers from 80 to 99% of the conductive metal feature.5. The interconnect structure of claim 1 , wherein said interconnect dielectric material is porous.6. The interconnect structure of claim 1 , wherein said metallic cap comprises a metal or metal alloy that is more resistant to corrosion ...

HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT

A hybrid interconnect structure (of the single or dual damascene type) is provided in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance. Moreover, the hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing. 1. An interconnect structure comprising:a dielectric material havening at least one opening therein;a dense dielectric spacer located partially within the at least one opening and in direct contact with a first sidewall portion of the dielectric material;a diffusion barrier located within the at least one opening, wherein a first surface of the diffusion barrier directly contacts a surface of the dense dielectric spacer and wherein a second surface of the diffusion barrier directly contacts a second sidewall portion of the dielectric material; anda conductive material located on said diffusion barrier.2. The interconnect structure of wherein said dielectric material has a dielectric constant of about 4.0 or less.3. The interconnect structure of wherein said dielectric material is one of SiO claim 2 , a silsesquioxane claim 2 , a C doped oxide that include atoms of Si claim 2 , C claim 2 , O and H claim 2 , SiC(N claim 2 ,H) and a thermosetting polyarylene ether.4. The interconnect structure of wherein said dielectric material is porous.5. The interconnect structure of wherein said dense dielectric spacer is comprised of SiO claim 1 , SiN claim 1 , SiC claim 1 , a silsesquioxane claim 1 , a C ...

HYBRID INTERCONNECT STRUCTURE FOR PERFORMANCE IMPROVEMENT AND RELIABILITY ENHANCEMENT

A hybrid interconnect structure is provided that includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance. Moreover, the hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing. 1. An interconnect structure comprising:a lower interconnect level comprising a first dielectric material having a first conductive material embedded therein; andan upper interconnect level comprising a second dielectric material having at least one opening that is in contact with said first conductive material of the lower interconnect level, wherein said second dielectric material has a second conductive material embedded within said at least one opening that is laterally spaced apart from said second dielectric material by a diffusion barrier and a dense dielectric spacer, said diffusion barrier is in contact with at least said second conductive material.2. The interconnect structure of further comprising an air gap located between said dense dielectric spacer and an upper portion of said second dielectric material.3. The interconnect structure of wherein said second dielectric material is one of SiO claim 1 , a silsesquioxane claim 1 , a C doped oxide that include atoms of Si claim 1 , C claim 1 , O and H claim 1 , SiC(N claim 1 ,H) and a thermosetting polyarylene ether.4. The interconnect structure of wherein said second dielectric material is porous.5. The interconnect structure of wherein said dense dielectric spacer is comprised of SiO claim 1 , SiN claim 1 , SiC claim 1 , a silsesquioxane claim 1 , a C doped oxide that include atoms of Si claim 1 , C ...

STRUCTURE AND PROCESS FOR METALLIZATION IN HIGH ASPECT RATIO FEATURES

A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack of at least one semiconductor device. In one embodiment, the noble metal-containing material is plug located within the lower region of the contact opening and an upper region of the contact opening includes a conductive metal-containing material. The conductive metal-containing material is separated from plug of noble metal-containing material by a bottom walled portion of a U-shaped diffusion barrier. In another embodiment, the noble metal-containing material is present throughout the entire contact opening. 1. A method of fabricating a semiconductor structure comprising:providing a structure including at least one semiconductor device located on a surface of a semiconductor substrate, said at least one semiconductor device including at least a material stack having an upper surface that is comprised of a metal semiconductor alloy;forming a dielectric material on said surface of said semiconductor substrate, said dielectric material including a contact opening that extends to the upper surface of said material stack, said contact opening having an aspect ratio of greater than 3:1; andfilling said contact opening with at least a noble metal-containing material utilizing a selective deposition process selected from chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, and plasma enhanced atomic layer deposition, said noble metal-containing material is present at least within a lower region of said contact opening and is in direct contact with said upper surface of said material stack.2. The method of further comprising forming at least a U-shaped diffusion barrier and a conductive metal-containing material within said contact ...

Metal Alloy Cap Integration

A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. The metal alloy capping layer is also reflowed on the copper. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy capping layer, and a dielectric cap. 1. A method of forming a metal interconnect structure , comprising steps of:providing a recessed pattern in a dielectric material;filling at least a portion of the recessed pattern with copper;forming an alloy capping layer on the copper comprising an alloying element ;reflowing the deposited alloy capping layer on the copper;planarizing the structure to expose a top surface of the dielectric material; anddepositing a dielectric cap, wherein the alloying element in the metal interconnect structure is distributed along an interface between the copper and the dielectric cap.2. The method of claim 1 , further comprising forming another copper layer on the reflowed alloy capping layer.3. The method of claim 2 , wherein between the steps of planarizing and depositing the dielectric cap claim 2 , further comprising polishing down to the alloy capping layer at a bottom surface of the another copper layer.4. The method of wherein after reflowing claim 1 , the deposited alloy capping layer comprises copper.5. The method of wherein the alloy capping layer is formed in the recessed pattern and ...

MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY

A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage. 1. A method of manufacturing a semiconductor structure , said method comprising:forming at least one switching device on a semiconductor substrate;forming at least one capacitor-side via structure contacting one node of said at least one switching device; andforming at least one capacitor, each of said at least one capacitor comprising at least three conductive plates and at least one node dielectric on said semiconductor substrate, wherein said at least three conductive plates vertically overlie or underlie one another and are separated from one another by said at least one node dielectric, and a laterally protruding portion of one of said at least three conductive plates contacts said at least one capacitor-side via structure, wherein said at least three conductive plates and at least one node dielectric are components of a capacitor module.2. The method of claim 1 , further comprising:forming at least one power-supply-side via structure contacting another node of said at least one switching device; andforming a power-supply-side plate contacting said at least one power-supply-side via structure.3. The method of claim 1 , further comprising:forming a first conductive plate over said semiconductor substrate;forming a ...

ELECTRICAL FUSE AND METHOD OF MAKING

A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing compressive stress liner material over the fuse material, and patterning the compressive stress liner material. 1. A semiconductor device , comprising:a fuse element; anda compressive stress material that reduces an electro-migration resistance of the fuse element, wherein the compressive stress material comprises a compressive stress component imparted during deposition.2. The semiconductor device of claim 1 , wherein the fuse element comprises:first and second contact portions; anda neck connecting the first and second contact portions, the neck having a cross-sectional area less than each of the first and second contact portions.3. The semiconductor device of claim 1 , further comprising a second material atop the compressive stress material.4. The semiconductor device of claim 1 , wherein the fuse element comprises one of silicon claim 1 , silicon plus metal silicide claim 1 , copper claim 1 , copper alloy claim 1 , aluminum claim 1 , aluminum alloy claim 1 , and tungsten.5. The semiconductor device of claim 1 , wherein the compressive stress material comprises one of titanium claim 1 , titanium nitride claim 1 , tantalum claim 1 , tantalum nitride claim 1 , tungsten claim 1 , silicon oxide claim 1 , silicon nitride claim 1 , silicon carbide claim 1 , nitrogen-doped silicon carbide claim 1 , and hydrogen-doped silicon carbide.6. The semiconductor device of claim 5 , wherein the compressive stress material has a thickness in the range of about 5 nm to 100 nm.7. A semiconductor device claim 5 , comprising:a fuse element; anda compressive stress material that reduces an electro-migration resistance of the fuse element,wherein the fuse element ...

Mask free protection of work function material portions in wide replacement gate electrodes

In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.

MASK FREE PROTECTION OF WORK FUNCTION MATERIAL PORTIONS IN WIDE REPLACEMENT GATE ELECTRODES

In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics. 1. A method of forming a semiconductor structure including a field effect transistor (FET) , said method comprising:forming a gate cavity laterally surrounded by a planarization dielectric layer on a semiconductor substrate, wherein a top surface of said semiconductor substrate is exposed at a bottom of said gate cavity;forming a gate dielectric over said top surface of said semiconductor substrate in said gate cavity;forming a work function material layer on said gate dielectric;forming a dielectric material portion on an horizontal portion of said work function material layer within said gate cavity;etching said work function material layer, wherein a remaining portion of said work function material layer becomes a work function material portion; andforming a conductive material portion over said dielectric material portion and said work function material portion, wherein a gate electrode of said field effect transistor comprises said conductive material portion and said work function material portion.2. The method of claim 1 , wherein said forming of said dielectric material portion comprises:depositing a dielectric material layer on said work function material layer; andplanarizing said dielectric material layer ...

SPACER FOR ENHANCING VIA PATTERN OVERLAY TOLERENCE

After formation of line openings in a hard mask layer, hard mask level spacers are formed on sidewalls of the hard mask layer. A photoresist is applied and patterned to form a via pattern including a via opening. The overlay tolerance for printing the via pattern is increased by the lateral thickness of the hard mask level spacers. A portion of a dielectric material layer is patterned to form a via cavity pattern by an etch that employs the hard mask layer and the hard mask level spacers as etch masks. The hard mask level spacers are subsequently removed, and the pattern of the line is subsequently transferred into an upper portion of the dielectric material layer, while the via cavity pattern is transferred to a lower portion of the dielectric material layer. 1. A method of forming a metal interconnect structure comprising:forming a hard mask layer over a dielectric material layer;patterning said hard mask layer with a line pattern including a line opening having a first width;forming a hard mask level spacer on sidewalls of said line opening, wherein inner sidewalls of said hard mask level spacer define another line opening having a second width less than said first width;applying a photoresist layer over said hard mask layer and lithographically patterning said photoresist layer with a via pattern that includes a via opening overlying said another line opening; andtransferring, employing an etch, a composite pattern including an intersection of said via opening and said another line opening into a portion of said dielectric material layer.2. The method of claim 1 , wherein said etch employs said photoresist layer claim 1 , said hard mask layer claim 1 , and said hard mask level spacer as etch masks.3. The method of claim 1 , further comprising removing said hard mask level spacer selective to said dielectric material layer.4. The method of claim 3 , further comprising etching said dielectric material layer employing said hard mask layer as an etch mask after said ...

BORDERLESS CONTACTS FOR METAL GATES THROUGH SELECTIVE CAP DEPOSITION

A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region. 1. A method of forming contacts to a semiconductor device comprising:providing a gate structure having a metal gate conductor on the channel portion of a substrate, wherein an intralevel dielectric is present on the substrate adjacent to the gate structure;forming a metal gate cap on the upper surface of the metal gate conductor;forming a dielectric cap on the intralevel dielectric;removing the metal gate cap selectively to the dielectric cap and the metal gate conductor to provide a void overlying the metal gate conductor;filling the void overlying the metal gate conductor with a metal oxide cap;etching the dielectric cap and the intralevel dielectric using an etch chemistry that is selective to the metal oxide cap to provide an opening to at least one of a source region and a drain region that is present on opposing sides of the channel portion of the substrate; and deposition of a metal on the upper surface of the metal gate conductor and an upper surface of the intralevel dielectric, wherein the thickness of the metal for the metal gate cap is greater on the metal gate conductor than the intralevel dielectric; and', 'etching the metal that is present on the intralevel dielectric with an isotropic etch., 'forming a metal fill in the opening to provide a contact to said at least one of the ...

HYBRID COPPER INTERCONNECT STRUCTURE AND METHOD OF FABRICATING SAME

A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region. 1. An interconnect structure comprising:a patterned dielectric material having at least one opening located therein;a dual material liner located at least on sidewalls of the patterned dielectric material within the at least one opening;a first copper region containing a first impurity level located within a bottom region of said at least one opening; anda second copper region containing a second impurity level located within a top region of said at least one opening and atop the first copper region, wherein said first impurity level of said first copper region is less than the second impurity level of said second copper region.2. The interconnect structure of claim 1 , wherein said second impurity level of the second copper region has an amount of impurities of 100 ppm or greater claim 1 , and the first impurity level of said first copper region has an amount of impurities of less than 20 ppm.3. The interconnect structure of claim 2 , wherein said impurities within said second impurity level of said second region of copper comprises at least one of carbon claim 2 , chloride claim 2 , oxygen and sulfur.4. The interconnect structure of ...

DUAL-METAL SELF-ALIGNED WIRES AND VIAS

Disclosed is a semiconductor structure which includes a semiconductor substrate and a wiring layer on the semiconductor substrate. The wiring layer includes a plurality of fin-like structures comprising a first metal; a first layer of a second metal on each of the plurality of fin-like structures wherein the first metal is different from the second metal, the first layer of the second metal having a height less than each of the plurality of fin-like structures; and an interlayer dielectric (ILD) covering the plurality of fin-like structures and the first layer of the second metal except for exposed edges of the plurality of fin-like structures at predetermined locations, and at locations other than the predetermined locations, the height of the plurality of fin-like structures has been reduced so as to be covered by the ILD. 1. A semiconductor structure comprising:a semiconductor substrate; a plurality of fin-like structures having a height (H), width (W) and length (L) such that L>H>W, each of the fin-like structures comprising a first metal;', 'a first layer of a second metal on each of the plurality of fin-like structures wherein the first metal is different from the second metal; and', 'an interlayer dielectric (ILD) covering the plurality of fin-like structures except for exposed edges of the plurality of fin-like structures at predetermined locations., 'a wiring layer on the semiconductor substrate, the wiring layer comprising2. The semiconductor structure of wherein the fin-like structures extend beyond the first layer of the second metal such that only the exposed edges of the fin-like structures are exposed and the first layer of the second metal being covered by the ILD.3. The semiconductor structure of wherein the first layer of the second metal has a height claim 1 , H claim 1 , such that H is greater than H.4. The semiconductor structure of wherein each of the fin-like structures comprising a second layer of the second metal such that the second metal ...

SELF-ALIGNED METAL-INSULATOR-METAL (MIM) CAPACITOR

A metal-insulator-metal (MIM) capacitor structure integrated within a back-end-of-the-line (BEOL) structure is provided. The MIM capacitor structure includes a lower electrode, i.e., a first conductive material, embedded within a dielectric material of the BEOL structure, a dielectric material liner having a dielectric constant of equal to, or greater than, silicon dioxide located atop the lower electrode, and an upper electrode, i.e., a second conductive material, positioned between vertical portions of the dielectric material liner and atop a horizontal connecting portion of the dielectric material liner. In accordance with the present disclosure, the vertical portions of the dielectric material liner do not extend onto an upper surface of the dielectric material that includes the lower electrode. 1. A semiconductor structure comprising:a diffusion barrier and a first conductive material embedded within a dielectric material, wherein the diffusion barrier separates the first conductive material from the dielectric material and wherein the diffusion barrier and the first conductive material have upper surfaces that are coplanar with an upper surface of the dielectric material;insulator material portions present at least on the upper surface of the dielectric material, each insulator material portion having a sidewall surface that is vertically coincident to an outermost vertical edge of the diffusion barrier or an outermost vertical edge of the first conductive material;a dielectric material liner having a dielectric constant of equal to, or greater than, silicon dioxide located atop the first conductive material and between said insulator material portions, wherein said dielectric material liner has vertical portions that extend from a horizontal connecting portion; anda second conductive material positioned between the vertical portions of said dielectric material liner and located atop the horizontal connecting portion of said dielectric material liner, wherein ...

DUAL DAMASCENE DUAL ALIGNMENT INTERCONNECT SCHEME

A stack of a first metal line and a first dielectric cap material portion is formed within a line trench of first dielectric material layer. A second dielectric material layer is formed thereafter. A line trench extending between the top surface and the bottom surface of the second dielectric material layer is patterned. A photoresist layer is applied over the second dielectric material layer and patterned with a via pattern. An underlying portion of the first dielectric cap material is removed by an etch selective to the dielectric materials of the first and second dielectric material layer to form a via cavity that is laterally confined along the widthwise direction of the line trench and along the widthwise direction of the first metal line. A dual damascene line and via structure is formed, which includes a via structure that is laterally confined along two independent horizontal directions. 1. A metal interconnect structure comprising:a dielectric material stack including at least a first dielectric material layer and a second dielectric material layer overlying said first dielectric material layer;a stack, from bottom to top, of a first metal line and a dielectric cap material portion, said stack located within said first dielectric material layer and wherein an upper surface of said dielectric cap material portion is coplanar with an upper surface of said first dielectric material layer; anda dual damascene line and via structure including a second metal line and a via structure, wherein said second metal line is embedded within said second dielectric material layer and said via structure is embedded within said first dielectric material layer.2. The metal interconnect structure of claim 1 , wherein said first metal line extends along a first horizontal lengthwise direction claim 1 , said second metal line extends along a second horizontal lengthwise direction that is different from said first horizontal lengthwise direction.3. The metal interconnect ...

REPLACEMENT METAL GATE PROCESSING WITH REDUCED INTERLEVEL DIELECTRIC LAYER ETCH RATE

A semiconductor structure includes an interlevel dielectric (ILD) layer disposed over a semiconductor substrate and a transistor gate structure formed on the substrate; and a shallow gas cluster ion beam (GCIB) layer infused in a top portion of the ILD layer; wherein the GCIB layer has a slower etch rate with respect to the ILD layer. 1. A semiconductor structure , comprising:an interlevel dielectric (ILD) layer disposed over a semiconductor substrate and a planarized replacement transistor gate structure formed on the substrate; anda shallow gas cluster ion beam (GCIB) layer infused in a top portion of the ILD layer;wherein the GOB layer has a slower etch rate with respect to the ILD layer.2. The structure of claim 1 , wherein the ILD layer comprises an oxide layer.3. The structure of claim 2 , wherein the transistor gate structure comprises a high-K dielectric layer and a metal gate layer.4. The structure of claim 3 , wherein the etch rate of the GCIB is about 5 times slower than that of the ILD layer.5. The structure of claim 4 , wherein the GCIB comprises a silicon rich oxide.6. The structure of claim 5 , wherein the GCIB layer has a thickness of about 10 nanometers (nm) or less.7. The structure of claim 6 , wherein the ILD layer has a thickness of about 40 nm.8. The structure of claim 1 , further comprising a channel region defined in the semiconductor substrate claim 1 , below the planarized replacement transistor gate structure claim 1 , wherein the channel region is free from ions of the shallow GCIB layer infused in the top portion of the ILD layer. This application is a continuation of U.S. patent application Ser. No. 13/524,576, filed Jun. 15, 2012, the disclosure of which is incorporated by reference herein in its entirety.The present invention relates generally to semiconductor device manufacturing and, more particularly, to implementing replacement metal gate processing with a reduced interlevel dielectric layer (ILD) etch rate.Field effect transistors ...

HIGH-NITROGEN CONTENT METAL RESISTOR AND METHOD OF FORMING SAME

A thin film metal resistor is provided that includes an in-situ formed metal nitride layer formed in a lower region of a metal nitride layer. The in-situ formed metal nitride layer, together with the overlying metal nitride layer, from a thin film metal resistor which has a nitrogen content that is greater than 60 atomic % nitrogen. The in-situ formed metal nitride layer is present on a nitrogen enriched dielectric surface layer. The presence of the in-situ formed metal nitride layer in the lower region of the metal nitride layer provides a two-component metal resistor having greater than 60 atomic % nitrogen therein. 1. A metal resistor structure comprising:a dielectric material layer having a nitrogen enriched dielectric surface layer located in an upper region thereof; anda metal nitride layer located atop said nitrogen enriched dielectric surface layer, wherein said metal nitride layer is separated from said nitrogen enriched dielectric surface layer of said dielectric material layer by an in-situ formed metal nitride layer.2. The metal resistor structure of claim 1 , wherein said metal nitride layer and said in-situ formed metal nitride layer comprise a bilayer resistor with a distinct interface located therebetween.3. The metal resistor structure of claim 1 , wherein said metal nitride layer and said in-situ formed metal nitride layer provide a resistor having a graded nitrogen content.4. The metal resistor structure of claim 1 , wherein said metal nitride layer and said in-situ formed metal nitride layer provide a resistor having greater than 60 atomic % nitrogen located therein.5. The metal resistor structure of claim 1 , wherein said metal nitride layer and said in-situ formed metal nitride layer are components of a patterned resistor structure claim 1 , and wherein another dielectric material layer is located on exposed portions of said nitrogen enriched dielectric surface layer and said patterned resistor structure claim 1 , and further wherein said ...

LOW COST ANTI-FUSE STRUCTURE

An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure. 1. A semiconductor structure comprising:an interconnect dielectric material having at least one opening located therein; a diffusion barrier liner located within the at least one opening and in direct contact with at least sidewall surfaces of the interconnect dielectric material,', 'a first conductive metal plug located within the at least one opening and located on an exposed surface of the diffusion barrier liner, wherein said first conductive metal plug includes vertical sidewall portions that extend upward from an uppermost surface of the first conductive metal plug,', 'an anti-fuse material liner located on an exposed surface of the first conductive metal plug and an exposed surface of the vertical sidewall portions,', 'a second conductive metal plug located on an exposed surface of the anti-fuse material liner, wherein each of the diffusion barrier liner, the vertical sidewall portions, the anti-fuse material liner, and the second conductive metal plug have an uppermost surface that is co-planar with an uppermost surface of the interconnect dielectric material; and, 'an anti-fuse structure located within the least one opening, wherein the anti-fuse structure comprisesan interconnect structure located within a portion of the interconnect dielectric material that lies laterally adjacent the interconnect dielectric material including the anti-fuse structure, wherein said ...

LOW COST ANTI-FUSE STRUCTURE AND METHOD TO MAKE SAME

An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure. 1. A method of forming a semiconductor structure , said method comprising:forming at least one opening within an interconnect dielectric material; and forming a contiguous layer of a diffusion barrier material on an exposed uppermost surface of the interconnect dielectric material and at least within the at least one opening;', 'forming a contiguous layer of a first conductive metal on an exposed surface of the contiguous layer of the diffusion barrier material;', 'performing a reflow anneal which causes portions of the contiguous layer of the first conductive metal to flow into the at least one opening forming a first conductive metal plug within the at least one opening, wherein a remaining portion of the contiguous layer of the first conductive metal which is present inside and outside the at least one opening remains in contact with said first conductive metal plug;', 'forming a contiguous layer of an anti-fuse material on exposed surfaces of the first conductive metal plug and the remaining portion of the contiguous layer of the first conductive metal;', 'forming a contiguous layer of a second conductive metal on an exposed surface of the contiguous layer of the anti-fuse material; and', 'removing a portion of the contiguous layer of the second conductive metal, a portion of the contiguous layer of the anti-fuse material, remaining portions of the contiguous layer of the first ...

MOSFET GATE AND SOURCE/DRAIN CONTACT METALLIZATION

A MOSFET is described incorporating a common metal process to make contact to the source, drain and the metal gate respectively which may be formed concurrently with the same metal or metals. 1. A method for fabricating a field effect transistor comprising:selecting a Si containing substrate having a source, drain and channel regions exposed through openings in a dielectric layer, said openings to said channel region having sidewall spacers;forming a dielectric layer on said channel region;forming a metal gate layer over said dielectric layer;forming a metal silicide in said source and drain regions;forming a first metal liner layer over said metal silicide in said source and drain regions and over said metal gate layer and over the sidewalls of said openings in said dielectric layer;forming a second metal layer over said first metal liner layer having a thickness to fill said openings; andplanarizing said first metal layer and said second metal layer down to said dielectric layer.2. The method of wherein said forming a first metal liner layer includes forming a layer selected from the group consisting of tantalum claim 1 , titanium claim 1 , titanium nitride claim 1 , tantalum nitride claim 1 , titanium silicon nitride claim 1 , ruthenium claim 1 , ruthenium oxide claim 1 , ruthenium phosphorus claim 1 , hafnium claim 1 , zirconium claim 1 , aluminum claim 1 , manganese claim 1 , copper manganese claim 1 , iridium claim 1 , copper iridium claim 1 , cobalt claim 1 , cobalt tungsten claim 1 , cobalt tungsten phosphorus claim 1 , tungsten claim 1 , lanthanum claim 1 , lutetium claim 1 , transition metal elements claim 1 , rare earth elements claim 1 , a metal carbide claim 1 , a conductive metal oxide and combinations thereof.3. The method of wherein said forming a second metal layer includes forming a layer selected from the group consisting of copper claim 1 , ruthenium claim 1 , palladium claim 1 , platinum claim 1 , cobalt claim 1 , nickel claim 1 , ruthenium ...

PROFILE CONTROL IN INTERCONNECT STRUCTURES

The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening. 1. A method of forming a semiconductor structure comprising:forming a first dielectric material having at least one conductive region embedded therein;forming a second dielectric material above said first dielectric material and said conductive region;forming a via opening in said second dielectric material;forming a profile control liner on exposed surfaces within said via opening located in said second dielectric material;forming a line opening in said second dielectric material, said line opening is connected with said via opening, wherein said profile control liner remains on said exposed surfaces within said via opening during said forming of said line opening;exposing an upper surface of said at least one conductive region within said first dielectric material by removing at least a portion of said profile control liner within said via opening;forming a diffusion barrier liner within the line opening and the via opening; andforming a conductive material within remaining portions of said line opening and the via opening.2. The method of claim 1 , wherein said second dielectric material comprises a low dielectric constant material.3. The method of claim 1 , wherein said second dielectric material comprises silicon claim 1 , carbon claim 1 , and oxygen.4. The method of claim 1 , wherein said second dielectric material comprises pores.5. The method of claim 1 , wherein said exposing the upper surface of said at least one conductive region within said first dielectric material further comprises removing a portion of said ...

LOW COST ANTI-FUSE STRUCTURE

An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure. 1. A semiconductor structure comprising:an interconnect dielectric material having at least one opening located therein; and a diffusion barrier liner located within the at least one opening and in direct contact with at least sidewall surfaces of the interconnect dielectric material;', 'a first conductive metal plug located within the at least one opening and located on an exposed surface of the diffusion barrier liner, wherein said first conductive metal plug includes vertical sidewall portions that extend upward from an uppermost surface of the first conductive metal plug;', 'an anti-fuse material liner located on an exposed surface of the first conductive metal plug and an exposed surface of the vertical sidewall portions; and', 'a second conductive metal plug located on an exposed surface of the anti-fuse material liner, wherein each of the diffusion barrier liner, the vertical sidewall portions, the anti-fuse material liner, and the second conductive metal plug have an uppermost surface that is co-planar with an uppermost surface of the interconnect dielectric material., 'an anti-fuse structure located within the least one opening, wherein the anti-fuse structure comprises2. The semiconductor structure of wherein the interconnect dielectric material has a dielectric constant of about 4.0 or less.3. The semiconductor structure of claim 2 , wherein said interconnect dielectric ...

METHOD TO IMPROVE FINE CU LINE RELIABILITY IN AN INTEGRATED CIRCUIT DEVICE

Structure and methods for forming a semiconductor structure. The semiconductor structure includes a plurality of layers comprising at least one copper interconnect layer. The copper interconnect layer provides an electrical conduit between one of physically adjacent layers in the semiconductor structure and an integrated circuit in the semiconductor structure and an electronic device. A plurality of studs is positioned within the at least one copper interconnect layer. The studs are spaced apart by a distance less than or equal to a Blech length of the at least one copper interconnect layer. The Blech length is a length below which damage due to electromigration of metal atoms within the at least one copper interconnect layer does not occur. The plurality of studs comprises copper atom diffusion barriers. 1. A semiconductor structure , comprising: physically adjacent layers in said semiconductor structure, and', 'an integrated circuit in said semiconductor structure and an electronic device; and, 'a plurality of layers comprising at least one copper interconnect layer, said copper interconnect layer providing an electrical conduit between at least one of said Blech length comprising a length below which damage due to electromigration of metal atoms within said at least one copper interconnect layer does not occur,', 'said plurality of studs comprising copper atom diffusion barriers., 'a plurality of studs positioned within said at least one copper interconnect layer, said studs being spaced apart by a distance less than or equal to a Blech length of said at least one copper interconnect layer,'}2. The structure of claim 1 , said at least one copper interconnect layer comprising a copper metal line.3. The structure of claim 1 , said plurality of studs comprising copper (Cu).4. The structure of claim 1 , said plurality of studs comprising one of tantalum (Ta) claim 1 , tantalum nitride (TaN) claim 1 , titanium (Ti) claim 1 , titanium nitride (TiN) claim 1 , tungsten ( ...

Interconnect structures and methods for back end of the line integration

A method of forming a semiconductor structure includes forming a sacrificial conductive material layer. The method also includes forming a trench in the sacrificial conductive material layer. The method further includes forming a conductive feature in the trench. The method additionally includes removing the sacrificial conductive material layer selective to the conductive feature. The method also includes forming an insulating layer around the conductive feature to embed the conductive feature in the insulating layer.

Single fin cut employing angled processing methods

Fin-defining spacers are formed on an array of mandrel structure. Mask material portions can be directionally deposited on fin-defining spacers located on one side of each mandrel structure, while not deposited on the other side. A photoresist layer is subsequently applied and patterned to form an opening, of which the overlay tolerance increases by a pitch of fin-defining spacers due to the mask material portions. Alternately, a conformal silicon oxide layer can be deposited on fin-defining spacers and structure-damaging ion implantation is performed only on fin-defining spacers located on one side of each mandrel structure. A photoresist layer is subsequently applied and patterned to form an opening, from which a damaged silicon oxide portion and an underlying fin-defining spacer are removed, while undamaged silicon oxide portions are not removed. An array of semiconductor fins including a vacancy can be formed by transferring the pattern into a semiconductor layer.

PLANAR RESISTIVE RANDOM-ACCESS MEMORY (RRAM) DEVICE WITH A SHARED TOP ELECTRODE

Embodiments of the present invention are directed to forming a planar Resistive Random Access Memory (RRAM) device with a shared top electrode. In a non-limiting embodiment of the invention, a first trench having a first width and a second trench having a second width less than the first width are formed in a dielectric layer. A bottom liner is formed on sidewalls of the first trench. The bottom liner pinches off the second trench. A top liner is formed on sidewalls of the bottom liner in the first trench. The top liner is formed such that a portion of the bottom liner at a bottommost region of the first trench remains exposed. The exposed portion of the bottom liner is removed, and a memory cell material is formed in the first trench. 1. A method for forming a semiconductor device , the method comprising:forming a first trench having a first width and a second trench having a second width less than the first width in a dielectric layer;forming a bottom liner on sidewalls of the first trench, the bottom liner pinching off the second trench;forming a top liner on sidewalls of the bottom liner in the first trench, the top liner formed such that a portion of the bottom liner at a bottommost region of the first trench remains exposed;removing the exposed portion of the bottom liner; andforming a memory cell material in the first trench.2. The method of claim 1 , wherein the top liner does not fill the second trench due to pinch off.3. The method of claim 2 , wherein an air gap is formed between the top liner and the bottom liner in the second trench.4. The method of claim 1 , wherein the first width is more than 10 nm and the second width is less than 10 nm.5. The method of claim 1 , wherein removing the exposed portion of the bottom liner comprises etching the bottom liner selective to the top liner.6. The method of claim 5 , wherein the top liner comprises a conductive material having etch selectivity with respect to a wet etch chemistry used to remove the exposed ...

ELECTRICAL FUSE WITH METAL LINE MIGRATION

An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is coupled to the first contact and to the second contact, that has a third electromigration resistance that is lower than the second electromigration resistance. The first circuit element is coupled to the first contact and the second circuit element coupled to the second contact. The fuse is configured to conduct a programming current from the first contact to the second contact through the metal line. Further, the programming current causes the metal line to electromigrate away from the second contact to electrically isolate the second circuit element from the first circuit element. 1. A method for programming an electrical fuse device comprising:coupling a cathode element to a contact that is connected to a metal line;coupling an anode element to the metal line; andactivating the anode and cathode elements to apply a programming current through the contact and the metal line such that the metal line electromigrates away from the contact as a result of said activating.2. The method of claim 1 , wherein the contact is a first contact claim 1 , wherein the coupling the anode element further comprises coupling the anode element to a second contact such that the activating causes the programming current to flow between the second contact and the first contact through the metal line.3. The method of claim 2 , wherein the programming current is a first programming current and wherein the method further comprises:coupling a second cathode element and a second anode element to the metal line, wherein the activating comprises activating the second cathode element and the second anode element to apply a second programming current through the metal line, wherein the ...

VIA CLEANING TO REDUCE RESISTANCE

A method includes forming at least a first via in a multilayer structure comprising a first layer and a second layer formed over the first layer, the first via extending from a top of the second layer to a top of a first contact formed in the first layer and forming a polymer film on at least a portion of sidewalls of the first via by etching the top of the first contact using a cleaning process. 1. A method for forming a semiconductor structure , comprising:forming at least a first via in a multilayer structure comprising a first layer and a second layer formed over the first layer, the first via extending from a top of the second layer to a top of a first contact formed in the first layer; andforming a polymer film on at least a portion of sidewalls of the first via by etching the top of the first contact using a cleaning process.2. The method of claim 1 , wherein the cleaning process comprises an in situ reactive ion etching.3. The method of claim 2 , wherein the cleaning process utilizes argon gas.4. The method of claim 2 , wherein the cleaning process utilizes argon gas and helium gas.5. The method of claim 2 , wherein the cleaning process utilizes a flow of one or more inert gases exceeding 1200 standard cubic centimeters per minute.6. The method of claim 2 , wherein the cleaning process utilizes a radio frequency powered magnetic field of at least 300 watts.7. The method of claim 1 , wherein forming at least one via in the multilayer structure comprises:forming the first via and at least a second via extending from the top of the second layer to a top of a second contact formed in the first layer;forming at least a first trench extending from the top of the second layer partially through the second layer, the first trench connecting the first via and the second via.8. The method of claim 7 , wherein the first via claim 7 , the second via and the first trench form a chamfer having a high chamfering angle.9. The method of claim 1 , wherein the polymer film ...

METHOD FOR WAFER-WAFER BONDING

A first semiconductor structure including a first bonding oxide layer having a first metallic bonding structure embedded therein and a second semiconductor structure including a second bonding oxide layer having a second metallic bonding structure embedded therein are provided. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. Each nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layer and nitridized metallic regions located in an upper portion of the metallic bonding structures. The nitrogen within the nitridized metallic regions is then removed to restore the upper portion of the metallic bonding structures to its original composition. Bonding is performed to form a dielectric bonding interface between the nitridized oxide regions present in the first and second structures, and a metallic bonding interface between the first and second metallic bonding structures. 1. A three-dimensional (3D) bonded semiconductor structure comprising:a first semiconductor structure including a first wafer, a first interconnect structure, and a first bonding oxide layer having a first nitrogen enriched oxide upper surface, wherein at least one first metallic bonding structure is embedded in, and is in direct physical contact with sidewall surfaces of, said first bonding oxide layer and said first nitrogen enriched oxide upper surface; anda second semiconductor structure including a second wafer, a second interconnect structure, and a second bonding oxide layer having a second nitrogen enriched oxide upper surface, wherein at least one second metallic bonding structure is embedded in, and is in direct physical contact with sidewall surfaces of, said second bonding oxide layer and said second nitrogen enriched oxide upper surface, wherein a bonding interface is present between said first and second nitrogen enriched oxide upper surfaces and another bonding interface is present ...

3D BONDED SEMICONDUCTOR STRUCTURE WITH AN EMBEDDED CAPACITOR

A first semiconductor structure including a first bonding oxide layer having a first metallic structure embedded therein and a second semiconductor structure including a second bonding oxide layer having second metallic structure embedded therein are provided. A high-k dielectric material is formed on a surface of the first metallic structure. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. The nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layers and either a nitridized high-k dielectric material located in at least an upper portion of the high k dielectric material or a nitridized metallic region located in an upper portion of the second metallic structure. The nitrogen within the nitridized metallic region is then selectively removed to restore the upper portion of the second metallic structure to its original composition. Bonding is then performed. 1. A method of forming a three-dimensional (3D) bonded semiconductor structure , said method comprising:providing a first semiconductor structure including a first wafer, a first interconnect structure, and a first bonding oxide layer containing at least one first metallic structure embedded therein, and a second semiconductor structure including a second wafer, a second interconnect structure, and a second bonding oxide layer containing at least one second metallic structure embedded therein;forming a high-k dielectric material on a surface of said at least one first metallic structure;performing a nitridation process to provide a first nitrided surface layer comprising first nitridized oxide regions in an upper portion of said first bonding oxide layer and a nitridized high-k dielectric material in at least an upper portion of said high-k dielectric material, and to provide a second nitrided surface layer comprising second nitridized oxide regions in an upper portion of said second bonding oxide layer ...

INTEGRATED CIRCUIT STRUCTURE HAVING SELECTIVELY FORMED METAL CAP

An integrated circuit structure with a selectively formed and at least partially oxidized metal cap over a gate. In one embodiment, an integrated circuit structure has: a substrate; a metal gate located over the substrate; at least one liner layer over the substrate and substantially surrounding the metal gate; and an at least partially oxidized etch stop layer located directly over the metal gate, the etch stop layer including at least one of cobalt (Co), manganese (Mn), tungsten (W), iridium (Ir), rhodium (Rh) or ruthenium (Ru). 1. An integrated circuit structure comprising:a substrate;a metal gate located over the substrate;at least one liner layer over the substrate and substantially surrounding the metal gate; andan at least partially oxidized etch stop layer located directly over the metal gate, the etch stop layer including at least one of cobalt (Co), manganese (Mn), tungsten (W), iridium (Ir), rhodium (Rh) or ruthenium (Ru).2. The integrated circuit structure of claim 1 , further comprising a spacer member adjacent to the at least one liner layer claim 1 , wherein the etch stop layer is formed over only the metal gate and the at least one liner layer.3. The integrated circuit structure of claim 1 , wherein the etch stop layer is only partially oxidized.4. The integrated circuit structure of claim 1 , wherein the etch stop layer is completely oxidized.5. An integrated circuit structure comprising:a substrate;a metal gate located over the substrate;at least one liner layer over the substrate and substantially surrounding the metal gate;an at least partially oxidized etch stop layer located directly over the metal gate, the etch stop layer including at least one of cobalt (Co), manganese (Mn), tungsten (W), iridium (Ir), rhodium (Rh) or ruthenium (Ru),wherein the at least partially oxidized etch stop layer has a thickness of approximately 0.5 nanometers (nm); anda dielectric layer over the at least partially oxidized etch stop layer.6. The integrated circuit ...

Interconnect Structures with Selective Barrier for BEOL Applications

Interconnect structures with selective barrier for back-end-of-line (BEOL) applications are provided. In one aspect, an interconnect structure includes: a dielectric disposed over at least one metal line; at least one feature present in the dielectric over the at least one metal line; a barrier layer lining only surfaces of the dielectric within the at least one feature; at least one interconnect present in the at least one feature over the barrier layer, wherein the at least one interconnect is in direct contact with the at least one feature. A method of forming an interconnect structure is also provided. 1. An interconnect structure , comprising:a dielectric disposed over at least one metal line;at least one feature present in the dielectric over the at least one metal line;a barrier layer lining only surfaces of the dielectric within the at least one feature; andat least one interconnect present in the at least one feature over the barrier layer, wherein the at least one interconnect is in direct contact with the at least one metal line.2. The interconnect structure of claim 1 , wherein the at least one feature is selected from the group consisting of: a trench claim 1 , a via claim 1 , or combinations thereof.3. The interconnect structure of claim 1 , wherein the at least one feature comprises a via and a trench on top of the via that is aligned with the via.4. The interconnect structure of claim 1 , wherein the barrier layer comprises a material selected from the group consisting of: tantalum nitride (TaN) claim 1 , titanium nitride (TiN) claim 1 , titanium oxide (TiOx) claim 1 , tungsten carbide (WC) claim 1 , and combinations thereof.5. The interconnect structure of claim 1 , wherein the barrier layer has a thickness of from about 2 nm to about 5 nm and ranges therebetween.6. The interconnect structure of claim 1 , wherein the at least one interconnect comprises a metal selected from the group consisting of: copper (Cu) claim 1 , tungsten (W) claim 1 , cobalt ...

HYBRID INTERCONNECTS AND METHOD OF FORMING THE SAME

A method for manufacturing a semiconductor device includes forming a trench in at least one dielectric layer; and forming an interconnect structure in the trench, wherein forming the interconnect structure includes forming a first conductive layer on a bottom surface of the trench, and partially filling the trench, and forming a second conductive layer on the first conductive layer, and filling a remaining portion of the trench, wherein the second conductive layer comprises a different material from the first conductive layer, and wherein an amount of the first conductive layer in the trench is controlled so that an aspect ratio of the second conductive layer has a value that is determined to result in columnar grain boundaries in the second conductive layer. 1. A semiconductor device , comprising:at least one dielectric layer;a trench formed in the at least one dielectric layer; and a first conductive layer on a bottom surface of the trench, and partially filling the trench; and', 'a second conductive layer on the first conductive layer, and filling a remaining portion of the trench;, 'an interconnect structure formed in the trench, wherein the interconnect structure compriseswherein the second conductive layer comprises a different material from the first conductive layer; andwherein the second conductive layer comprises columnar grain boundaries.2. The semiconductor device according to claim 1 , wherein an aspect ratio of the second conductive layer has a value that is determined to result in the columnar grain boundaries in the second conductive layer.3. The semiconductor device according to claim 2 , wherein the aspect ratio is defined as height of the second conductive layer divided by a width of the second conductive layer.4. The semiconductor device according to claim 3 , wherein the second conductive layer comprises copper claim 3 , and the aspect ratio is less than 2.5.5. The semiconductor device according to claim 4 , wherein the first conductive layer ...

INTERCONNECT ARCHITECTURE WITH ENHANCED RELIABILITY

Interconnect structures having enhanced reliability is provided in which an electrically conductive structure having a line portion and a via portion is formed utilizing a subtractive process. In some embodiments, a non-conductive barrier liner is formed on physically exposed sidewalls of the via portion and physically exposed sidewalls and a topmost surface of the line portion of the electrically conductive structure. An electrically conductive metal cap is formed on a topmost surface of the via portion of the electrically conductive structure. In other embodiments, a conductive barrier spacer is formed on physically exposed sidewalls of the via portion and physically exposed sidewalls of the line portion of the electrically conductive structure. An electrically conductive metal cap is formed on a topmost surface of the via portion of the electrically conductive structure. 1. An interconnect structure comprising:at least one electrically conductive structure located on a first dielectric material layer, wherein the at least one electrically conductive structure comprises a via portion located on a line portion;a non-conductive barrier liner located on physically exposed sidewalls and a topmost surface of the line portion and sidewalls of the via portion of the at least one electrically conductive structure;a second dielectric material layer embedding the at least one electrically conductive structure and the non-conductive barrier liner; andan electrically conductive metal cap located on a topmost surface of the via portion of the at least one electrically conductive structure.2. The interconnect structure of claim 1 , wherein a sub-surface of the first dielectric material layer that is located at a footprint of the at least one electrically conductive structure is physically exposed and a portion of the non-conductive barrier liner is located on the sub-surface of the first dielectric material layer.3. The interconnect structure of claim 1 , further comprising an ...

METHOD FOR FORMING IMPROVED LINER LAYER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

A method for manufacturing a semiconductor device includes conformally depositing a liner layer on a top surface of a dielectric layer, and on sidewall and bottom surfaces of an opening in the dielectric layer, annealing the liner layer, wherein the annealing is performed in at least one of a nitrogen (N) and ammonia (NH) ambient, at a temperature of about 60° C. to about 500° C., and at a power of about 200 Watts to about 4500 Watts, and forming a conductive layer on the liner layer on the top surface of the dielectric layer, and on the liner layer in a remaining portion of the opening. 1. A method for manufacturing a semiconductor device , comprising:conformally depositing a liner layer on a top surface of a dielectric layer, and on sidewall and bottom surfaces of an opening in the dielectric layer;{'sub': 2', '3, 'annealing the liner layer, wherein the annealing is performed in at least one of a nitrogen (N) and ammonia (NH) ambient, at a temperature of about 60° C. to about 500° C., and at a power of about 200 Watts to about 4500 Watts; and'}forming a conductive layer directly on the liner layer on the top surface of the dielectric layer, and directly on the liner layer in a remaining portion of the opening;wherein the liner layer forms at least one of a halogen barrier and a diffusion barrier.2. The method according to claim 1 , wherein the liner layer is deposited using atomic layer deposition (ALD).3. The method according to claim 1 , wherein the liner layer comprises titanium nitride.4. The method according to claim 3 , wherein a density of the liner layer is greater than about 4.5 g/cm.5. The method according to claim 3 , wherein the liner layer further comprises carbon claim 3 , and the annealing reduces an amount of carbon in the liner layer.6. The method according to claim 3 , wherein the annealing removes nitrogen containing claim 3 , organic residue from the liner layer.7. The method according to claim 3 , wherein the annealing increases a ratio of ...

METHOD FOR FORMING IMPROVED LINER LAYER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

A method for manufacturing a semiconductor device includes conformally depositing a liner layer on a top surface of a dielectric layer, and on sidewall and bottom surfaces of an opening in the dielectric layer, annealing the liner layer, wherein the annealing is performed in at least one of a nitrogen (N) and ammonia (NH) ambient, at a temperature of about 60° C. to about 500° C., and at a power of about 200 Watts to about 4500 Watts, and forming a conductive layer on the liner layer on the top surface of the dielectric layer, and on the liner layer in a remaining portion of the opening. 1. A semiconductor device , comprising:a dielectric layer;an opening formed in the dielectric layer;a liner layer on sidewall and bottom surfaces of the opening; anda conductive layer on the liner layer in the opening;{'sup': '3', 'wherein the liner layer comprises titanium nitride, and a density of the liner layer is greater than about 4.5 g/cm.'}2. The semiconductor device according to claim 1 , wherein the liner layer and the conductive layer form at least part of an interconnect.3. The semiconductor device according to claim 1 , wherein the liner layer and the conductive layer form at least part of a gate structure.4. The semiconductor device according to claim 3 , wherein the liner layer is formed on a gate dielectric.5. The semiconductor device according to claim 3 , wherein the liner layer is formed on a gate spacer.6. The semiconductor device according to claim 1 , wherein a thickness of the liner layer is in a range of about 5 angstroms to about 20 nm.7. The semiconductor device according to claim 6 , wherein a thickness of the liner layer is in a range of about 5 nm to about 10 nm.8. The semiconductor device according to claim 1 , wherein the liner layer is an oxygen diffusion barrier.9. The semiconductor device according to claim 1 , wherein the liner layer is a halogen diffusion barrier.10. The semiconductor device according to claim 1 , wherein the liner layer is a ...

Void-free metallic interconnect structures with self-formed diffusion barrier layers

Methods are provided for fabricating void-free metallic interconnect structures with self-formed diffusion barrier layers. A seed layer is deposited to line an etched opening in a dielectric layer. A metallic capping layer is selectively deposited on upper portions and upper sidewall surfaces of the seed layer which define an aperture into the etched opening. An electroplating process is performed to plate metallic material on exposed surfaces of the seed layer within the etched opening, which are not covered by the capping layer to form a metallic interconnect. The capping layer prohibits plating of metallic material on the capping layer and closing the aperture before the electroplating process is complete. A thermal anneal process is performed to cause the metallic material of the metallic capping layer to diffuse though the metallic interconnect and create a self-formed diffusion barrier layer between the metallic interconnect and the surfaces of the etched opening.

LINER-FREE AND PARTIAL LINER-FREE CONTACT/VIA STRUCTURES

A liner-free or partial liner-free contact/via structure that is embedded within a dielectric capping layer and positioned between an electrically conductive structure and an overlying contact structure is provided. 1. A semiconductor structure comprising:a lower portion of a volume expanded electrically conductive structure embedded in a first dielectric material layer;a dielectric capping layer located on the first dielectric material layer, wherein the dielectric capping layer has a contact via/opening comprising a lower portion and an upper portion, wherein the lower portion of the contact/via opening contains an upper portion of the volume expanded electrically conductive structure;a gap located beneath the dielectric capping layer, wherein the gap separates the dielectric capping layer from a surface of the lower portion of the volume expanded electrically conductive structure embedded in the first dielectric material layer;a contact/via diffusion barrier liner and a contact/via structure present in the upper portion of the contact/via opening; anda contact structure located above the dielectric capping layer, the contact/via diffusion barrier liner, and the contact/via structure, wherein the contact structure is embedded in a second dielectric material layer.2. The semiconductor structure of claim 1 , wherein the contact structure embedded in the second dielectric material layer comprises an electrically conductive structure.3. The semiconductor structure of claim 2 , further comprising a diffusion barrier liner located on sidewalls and a bottommost surface of the electrically conductive structure embedded in the second dielectric material layer.4. The semiconductor structure of claim 1 , wherein the contact structure embedded in the second dielectric material layer comprises a non-volatile memory device.5. The semiconductor structure of claim 4 , wherein the non-volatile memory device includes a ferroelectric (FE) memory device claim 4 , a resistive random ...

INTEGRATED CIRCUIT HAVING A SINGLE DAMASCENE WIRING NETWORK

A method for fabricating a multi-layered wafer includes depositing a metal liner following by a seed layer including a metal in a trench arranged in an inter-metal dielectric (IMD). An end of the trench contacts a metal via of an interconnect structure. Heat is applied to drive the metal of the seed layer into the IMD and form a barrier layer along a sidewall of the trench. 1. A method of fabricating a wafer , the method comprising:depositing a metal liner followed by a seed layer in a trench arranged in an inter-metal dielectric (IMD), an end of the trench contacting a metal via of an interconnect structure, and the seed layer comprising a metal; andapplying heat to drive the metal of the seed layer into the IMD and form a barrier layer along a-sidewalls of the trench and at least partially along sidewalls of the metal via.2. The method of claim 1 , wherein the seed layer comprises manganese claim 1 , copper claim 1 , or a combination thereof.3. The method of further comprising depositing another metal to fill the trench.4. The method of claim 3 , wherein the another metal comprises copper claim 3 , tungsten claim 3 , aluminum claim 3 , cobalt claim 3 , ruthenium claim 3 , rhodium claim 3 , platinum claim 3 , or any combination thereof.5. The method of claim 1 , wherein the barrier layer comprises a compound that results from reaction of the metal in the seed layer and a compound of the IMD.6. The method of claim 1 , wherein the seed layer is manganese.7. The method of claim 1 , wherein the seed layer comprises copper and manganese.8. A method of fabricating a wafer claim 1 , the method comprising:depositing a metal liner following by a seed layer in a trench arranged in an inter-metal dielectric (IMD), an end of the trench contacting a metal via of an interconnect structure, the metal via comprising a metal fill, the seed layer comprising a first metal and a second metal; andapplying heat to drive the first metal into the IMD and form a barrier layer along a ...

METALLIZATION LAYER FORMATION PROCESS

A method of forming cut conductive lines is provided. The method includes forming a trough in a dielectric cover layer over a plurality of electrical contacts. The method further includes filling the trough with a planarization layer, and forming a plurality of vias in the planarization layer and the dielectric cover layer, wherein each of the plurality of vias is aligned with one of the plurality of electrical contacts. The method further includes removing the planarization layer, and forming a sacrificial via plug in each of the plurality of vias in the dielectric cover layer. The method further includes forming a fill layer in the trough, and forming a planarization layer opening through the fill layer, wherein the planarization layer opening is positioned between two adjacent sacrificial via plugs. The method further includes forming a separator in the planarization layer opening. 1. A method of forming cut conductive lines , comprising:forming a sacrificial via plug in each of a plurality of vias in a dielectric cover layer;forming a fill layer on the dielectric cover layer;forming a planarization layer opening through the fill layer, wherein the planarization layer opening is positioned between two adjacent sacrificial via plugs; andforming a separator in the planarization layer opening.2. The method of claim 1 , wherein the separator is made of an electrically insulating claim 1 , dielectric material.3. The method of claim 1 , wherein the separator includes a separator projection extending below the top surface of the dielectric cover layer.4. The method of claim 1 , wherein the sacrificial via plugs are made of a material selected from the group consisting of polycrystalline or amorphous silicon claim 1 , polycrystalline or amorphous germanium claim 1 , polycrystalline or amorphous silicon-germanium claim 1 , titanium oxide (TiO) claim 1 , aluminum oxide (AlO) claim 1 , or a combination thereof.5. The method of claim 1 , further comprising removing the fill ...

FABRICATION OF PHASE CHANGE MEMORY CELL IN INTEGRATED CIRCUIT

A phase change memory (PCM) cell in an integrated circuit and a method of fabricating it involve depositing a layer of PCM material on a surface of a dielectric, and patterning the layer of PCM material into a plurality of PCM blocks. Heater material is formed on both sidewalls of each of the plurality of the PCM blocks to form a plurality of PCM cells. Each of the plurality of the PCM blocks and the heater material on both the sidewalls represents a PCM cell. An additional layer of the dielectric is deposited above and between the plurality of the PCM cells, and trenches are formed in the dielectric. Trenches are formed in contact with each side of each of the plurality of the PCM cells. Metal is deposited in each of the trenches. Current flow in the metal heats the heater material of one of the PCM cells. 1. A structure used to form a memory devices within an integrated circuit , the structure comprising:a plurality of phase change memory (PCM) cells, wherein each PCM cell includes PCM material between heater material on a first side and a second side of the PCM material;a plurality of metal components, wherein the heater material on the first side of the PCM material and the heater material on the second side of the PCM material of each of the plurality of the PCM cells is in contact with one of the plurality of the metal components; anddielectric directly above and below the plurality of the PCM cells.2. The structure according to claim 1 , wherein the heater material is tantalum nitride (TaN).3. The structure according to claim 1 , wherein the metal is copper (Cu) claim 1 , aluminum (Al) claim 1 , ruthenium (Ru) claim 1 , cobalt (Co) claim 1 , or tungsten (W).4. The structure according to claim 1 , wherein the PCM material is germanium-antimony-tellurium (GST).5. The structure according to claim 1 , wherein the plurality of metal components are metal wires.6. The structure according to claim 5 , further comprising a first metal level below the dielectric claim ...

SEMICONDUCTOR DEVICE WITH REDUCED VIA RESISTANCE

A semiconductor interconnect structure having a first electrically conductive structure having a plurality of bottom portions; a dielectric capping layer, at least a portion of the dielectric capping layer being in contact with a first bottom portion of the plurality of bottom portions; and a second electrically conductive structure in electrical contact with a second bottom portion of the plurality of bottom portions. A method of forming the interconnect structure is also provided. 1. A method of fabricating a semiconductor interconnect structure , the method comprising:providing a semiconductor structure including a first dielectric layer having a first electrically conductive structure embedded therein, a second dielectric layer located above the first dielectric layer, the second dielectric layer and the first dielectric layer having a segment of a dielectric capping layer located therebetween, and a segment of a metal capping layer located therebetween, the segment of metal capping layer covering at least a portion of a top surface of the first electrically conductive structure;forming an opening in the second dielectric layer and the metal capping layer, thereby exposing at least a portion of the first electrically conductive structure and a portion of the dielectric capping layer; andforming a second electrically conductive structure in the opening, such that a first bottom portion of the second electrically conductive structure is located over a portion of the dielectric capping layer, and such that a second bottom portion of the second electrically conductive structure is in electrical contact with the portion of the first electrically conductive structure.2. The method of claim 1 , wherein forming the second electrically conductive structure in the opening further comprises:depositing a first liner material in the opening;removing a portion of the first liner material that is over the portion of the first electrically conductive structure included in the ...

SUB-LITHOGRAPHIC SEMICONDUCTOR STRUCTURES WITH NON-CONSTANT PITCH

Fin structures and methods of manufacturing fin structures using a dual-material sidewall image transfer mask to enable patterning of sub-lithographic features is disclosed. The method of forming a plurality of fins includes forming a first set of fins having a first pitch. The method further includes forming an adjacent fin to the first set of fins. The adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch. The first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process. 1. A method of forming a plurality of fins , comprising:forming a first set of fins having a first pitch; andforming an adjacent fin to the first set of fins, wherein the adjacent fin and a nearest fin of the first set of fins have a second pitch larger than the first pitch,wherein the first set of fins and the adjacent fin are sub-lithographic features formed using a sidewall image transfer process.2. The method of claim 1 , wherein: a first structure of a first group of materials; and', 'a second structure of a second group of materials; and, 'the first set of fins initially comprisethe adjacent fin initially comprises a third structure comprising the second group of materials,wherein an underlying material of the first group of materials and an underlying material of the second group of materials is a same material which form a first fin and a second fin of the first set of fins, and the adjacent fin.3. The method of claim 2 , further comprising:removing material from over the underlying material from the second structure and the third structure through same processing steps to form the second fin and the adjacent fin; andremoving material from over the underlying material from the first structure to form the first fin.4. The method of claim 3 , wherein the removing the material from the first structure is performed in different processing steps than removing the material from the second ...