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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 923. Отображено 195.
05-01-2017 дата публикации

POROUS SILICON RELAXATION MEDIUM FOR DISLOCATION FREE CMOS DEVICES

Номер: US20170005113A1
Автор: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana, CHENG KANGGUO, DIVAKARUNI RAMACHANDRA, KIM JEEHWAN, LI JUNTAO, SADANA DEVENDRA K, Cheng Kangguo, Divakaruni Ramachandra, Kim Jeehwan, Li Juntao, Sadana Devendra K.
Принадлежит:

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer. 1. A method for forming complementary metal oxide semiconductor devices , comprising:masking a first portion of a tensile-strained silicon layer of a silicon on insulator substrate with a hard mask;doping a second portion of the tensile-strained silicon layer outside the first portion;removing the hard mask;growing an undoped silicon layer on the doped portion and the first portion, wherein the undoped silicon layer becomes a tensile-strained undoped silicon layer;relaxing strain in the undoped silicon layer over the doped portion by converting the doped portion to a porous silicon to form a relaxed silicon layer;converting the porous silicon to an oxide;growing a SiGe layer on the relaxed silicon layer;oxidizing the SiGe layer to convert the relaxed silicon layer to a compressed SiGe layer; andetching fins in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.2. The method as recited in claim 1 , wherein doping the second portion of the tensile-strained silicon layer includes boron doping the second portion.3. The method as recited in claim 1 , wherein relaxing strain in the undoped silicon layer over ...

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Номер записи: 1
22-09-2016 дата публикации

ASYMMETRIC FET

Номер: US20160276437A1
Автор: Kangguo Cheng, Joseph Ervin, Juntao Li, Chengwen Pei, Geng Wang, CHENG KANGGUO, ERVIN JOSEPH, LI JUNTAO, PEI CHENGWEN, WANG GENG, Cheng Kangguo, Ervin Joseph, Li Juntao, Pei Chengwen, Wang Geng
Принадлежит:

After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that are not covered by a gate structure, at least one dielectric layer is formed to cover the first-side and the second-side epitaxial semiconductor regions and the gate structure. A second-side contact opening is formed within the at least one dielectric layer to expose an entirety of the second-side epitaxial semiconductor region. The exposed second-side epitaxial semiconductor region can be replaced by a new second-side epitaxial semiconductor region having a composition different from the first-side epitaxial semiconductor region or can be doped by additional dopants, thus creating an asymmetric first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region. Each of the first-side epitaxial semiconductor region and the second-side epitaxial semiconducting region can function as either a source or a drain ...

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Номер записи: 2
19-12-2017 дата публикации

Metal reflow for middle of line contacts

Номер: US0009847261B2
Автор: Juntao Li, Junli Wang, Chih-Chao Yang, LI JUNTAO, WANG JUNLI, YANG CHIH-CHAO, Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method of forming a contact in a semiconductor device includes forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD) material arranged between the first gate and the second gate to form a trench that extends from a surface of the first gate and a surface of the second gate to the substrate; depositing a liner along a sidewall of the trench and an endwall of the trench in contact with the substrate; depositing by a physical vapor deposition method (PVD) a layer of metal on a surface of the first gate and a surface of the second gate; and heating to reflow metal from the layer of metal on the surface of the first gate and the second gate into the trench and form the contact.

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Номер записи: 3
27-03-2018 дата публикации

Electrical and optical via connections on a same chip

Номер: US9929290B2
Автор: LI JUNTAO, CHENG KANGGUO, PEI CHENGWEN, WANG GENG, ERVIN JOSEPH, Li Juntao, Cheng Kangguo, Pei Chengwen, Wang Geng, Ervin Joseph
Принадлежит: GLOBALFOUNDRIES INC, GLOBALFOUNDRIES INC.

The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of manufacture. The structure includes an optical through substrate via (TSV) comprising an optical material filling the TSV. The structure further includes an electrical TSV which includes a liner of the optical material and a conductive material filling remaining portions of the electrical TSV.

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Номер записи: 4
14-02-2017 дата публикации

Formation of SiGe nanotubes

Номер: US9570299B1
Автор: CHENG KANGGUO, HE HONG, KHAKIFIROOZ ALI, LI JUNTAO, Cheng Kangguo, He Hong, Khakifirooz Ali, Li Juntao
Принадлежит: IBM, International Business Machines Corporation

Techniques for forming nanostructured materials are provided. In one aspect of the invention, a method for forming nanotubes on a buried insulator includes the steps of: forming one or more fins in a SOI layer of an SOI wafer, wherein the SOI wafer has a substrate separated from the SOI layer by the buried insulator; forming a SiGe layer on the fins; annealing the SiGe layer under conditions sufficient to drive-in Ge from the SiGe layer into the fins and form a SiGe shell completely surrounding each of the fins; and removing the fins selective to the SiGe shell, wherein the SiGe shell which remains forms the nanotubes on the buried insulator. A nanotube structure and method of forming a nanotube device are also provided.

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Номер записи: 5
27-12-2016 дата публикации

Method of forming semiconductor fins on SOI substrate

Номер: US9530701B2
Автор: CHENG KANGGUO, ERVIN JOSEPH, LI JUNTAO, PEI CHENGWEN, WANG GENG, Cheng Kangguo, Ervin Joseph, Li Juntao, Pei Chengwen, Wang Geng
Принадлежит: IBM, International Business Machines Corporation

An approach to forming fins for a semiconductor device on a silicon-on-insulator wafer. The approach includes depositing a layer of mandrel material and etching the layer of mandrel material to form a mandrel. The approach includes depositing a layer of a dielectric material on the semiconductor layer and around the mandrel and etching the layer of the dielectric material to form one or more spacers next to the sidewalls of the mandrel, followed by removing the mandrel. Additionally, the approach includes depositing a layer of amorphous semiconductor material around said one or more spacers and heating it to transform into a layer of re-crystallized semiconductor material through solid phase epitaxy. Furthermore, the approach includes removing portions of the layer of re-crystallized semiconductor material from each of the horizontal surfaces of the silicon-on-insulator wafer including the area where the one or more spacers were removed to form one or more fins.

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Номер записи: 6
03-07-2013 дата публикации

Method of isolating non-grouting sections for geological chemical grouting

Номер: CN103184736A
Автор: Yao Xin, Shi Jun, Deng Qiang, Li Juntao, Liu Chao, Wang Yuanxun, Liao Jun, Jiao Ruifeng, Wei Shangwei, Huang Jianzhong
Принадлежит:

The invention discloses a method of isolating non-grouting sections for geological chemical grouting. The method comprises the following steps: hole drilling, drilled hole flushing, water pressurizing, non-grouting section isolation, water drainage, chemical grouting construction, slurry closing, cement replacement, solidifying and hole sealing, wherein non-grouting section isolation comprises determining of the non-grouting sections and the grouting sections and operation of isolating the non-grouting sections; the non-grouting sections at hole opening sections are drilled into the section bottoms of the non-grouting sections by adopting a geological drilling rig; a seamless steel tube is down to the section bottoms of the non-grouting sections; imbedding of hole opening pipes is performed by adopting cement grout or chemical grouting materials both with the ratio of 0.5 to 1, so that closed isolation is realized; each non-grouting section between two grouting sections is drilled into ...

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Номер записи: 7
15-08-2017 дата публикации

Integrated strained stacked nanosheet FET

Номер: US0009735269B1
Автор: Kangguo Cheng, Ramachandra Divakaruni, Juntao Li, Xin Miao, CHENG KANGGUO, DIVAKARUNI RAMACHANDRA, LI JUNTAO, MIAO XIN, Cheng Kangguo, Divakaruni Ramachandra, Li Juntao, Miao Xin
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

Transistors and methods of forming the same include forming a fin of alternating layers of a channel material and a sacrificial material. Stress liners are formed in contact with both ends of the fin. The stress liners exert a stress on the fin. The sacrificial material is etched away from the fin, such that the layers of the channel material are suspended between the stress liners. A gate stack is formed over and around the suspended layers of channel material.

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Номер записи: 8
26-12-2017 дата публикации

Anti-fuses with reduced programming voltages

Номер: US0009852982B1
Автор: Chengwen Pei, Kangguo Cheng, Juntao Li, Geng Wang, PEI CHENGWEN, CHENG KANGGUO, LI JUNTAO, WANG GENG, Pei Chengwen, Cheng Kangguo, Li Juntao, Wang Geng
Принадлежит: GLOBALFOUNDRIES INC., GLOBALFOUNDRIES INC, GLOBALFOUNDRIES Inc.

Device structures for an anti-fuse and methods for manufacturing device structures for an anti-fuse. The anti-fuse includes a first terminal comprised of a fin. The fin includes a section with an edge and inclined surfaces that intersect at the edge. The anti-fuse further includes a second terminal covering the edge and the inclined surfaces of the fin, and an isolation dielectric layer on the inclined surfaces and the edge of the fin. The second terminal is separated from the edge and inclined surfaces of the fin by the isolation dielectric layer. The edge and inclined surfaces on the firm may be formed by oxidizing an upper section of the fin in a trench to form an oxide layer, and then removing the oxide layer to expose the edge and inclined surfaces.

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Номер записи: 9
25-08-2016 дата публикации

EPITAXIAL SILICON GERMANIUM FIN FORMATION USING SACRIFICIAL SILICON FIN TEMPLATES

Номер: US20160247883A1
Автор: Hong He, Juntao Li, Junli Wang, Chih-Chao Yang, HE HONG, LI JUNTAO, WANG JUNLI, YANG CHIH-CHAO, He Hong, Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит:

A method of forming semiconductor fins includes forming a plurality of sacrificial template fins from a first semiconductor material; epitaxially growing fins of a second semiconductor material on exposed sidewall surfaces of the sacrificial template fins; and removing the plurality of sacrificial template fins.

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Номер записи: 10
19-09-2017 дата публикации

Integrated LDMOS and VFET transistors

Номер: US9768166B1
Автор: CHENG KANGGUO, LI JUNTAO, WANG GENG, ZHANG QINTAO, Cheng Kangguo, Li Juntao, Wang Geng, Zhang Qintao
Принадлежит: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

Embodiments are directed to devices and methods for integrating laterally diffused metal oxide semiconductor (LDMOS) technology on vertical field effect transistor (VFET) technology, which enables VFET applications to be broadened to include power amplifiers. By providing a combined asymmetric underlapped drain, high current, low subthreshold slope and LDMOS lightly doped drain, high drain resistance and high drain voltage are enabled.

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Номер записи: 11
16-01-2018 дата публикации

Electrical fuse and/or resistor structures

Номер: US0009870989B2
Автор: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li, BASKER VEERARAGHAVAN S, CHENG KANGGUO, KHAKIFIROOZ ALI, LI JUNTAO, Basker Veeraraghavan S., Cheng Kangguo, Khakifirooz Ali, Li Juntao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.

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Номер записи: 12
29-08-2017 дата публикации

Multiple finFET formation with epitaxy separation

Номер: US0009748245B1
Автор: Kangguo Cheng, Juntao Li, Peng Xu, CHENG KANGGUO, LI JUNTAO, XU PENG, Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A semiconductor device including an nFET device and pFET device adjacent one another. The semiconductor device includes a shallow trench isolator (STI), a gate and a substrate having fins extending upwardly through the STI. The fins include: nFET fins disposed in an nFET epi well formed in the STI and pFET fins disposed in a pFET epi well formed in the STI, a top the STI being above a top of the fins.

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Номер записи: 13
09-01-2018 дата публикации

FinFET with uniform shallow trench isolation recess

Номер: US0009865598B1
Автор: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu, BI ZHENXING, CHENG KANGGUO, LI JUNTAO, XU PENG, Bi Zhenxing, Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

Disclosed herein are processes and structures for uniform STI recessing. A method of making a semiconductor device includes initially forming a dense region of at least two fins on a substrate. The fins have a hard mask layer on a surface. The dense region with the fins is adjacent to an isolated region without fins within a distance of a pitch of the fins. An oxide is deposited on the dense and isolated regions. The oxide is polished, stopping on the hard mask layer on the fins, and removing more oxide in the isolated region. Polishing results in forming a non-uniform oxide surface. The hard mask layer is removed from the fins. An etch process is performed to further recess the oxide in the dense and isolated regions, such that a thickness of the oxide in the dense region and the isolated region is substantially uniform.

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Номер записи: 14
26-12-2017 дата публикации

Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation

Номер: US0009853054B2
Автор: Kangguo Cheng, Juntao Li, Zuoguang Liu, Xin Miao, CHENG KANGGUO, LI JUNTAO, LIU ZUOGUANG, MIAO XIN, Cheng Kangguo, Li Juntao, Liu Zuoguang, Miao Xin
Принадлежит: International Business Machines Corporation, IBM

A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.

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Номер записи: 15
18-04-2017 дата публикации

Vertical transistor having uniform bottom spacers

Номер: US0009627511B1
Автор: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang, CHENG KANGGUO, LI JUNTAO, WANG GENG, ZHANG QINTAO, Cheng Kangguo, Li Juntao, Wang Geng, Zhang Qintao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure that includes a fin on a semiconductor substrate, forming a source junction or a drain junction at an upper surface of the semiconductor substrate and at a base of the fin and epitaxially growing a rare earth oxide (REO) spacer to have a substantially uniform thickness along respective upper surfaces of the source or drain junction and on opposite sides of the fin structure.

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Номер записи: 16
27-03-2018 дата публикации

Porous silicon relaxation medium for dislocation free CMOS devices

Номер: US9929060B2
Автор: CHENG KANGGUO, DIVAKARUNI RAMACHANDRA, KIM JEEHWAN, LI JUNTAO, SADANA DEVENDRA K, Cheng Kangguo, Divakaruni Ramachandra, Kim Jeehwan, Li Juntao, Sadana Devendra K.
Принадлежит: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

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Номер записи: 17
25-05-2017 дата публикации

CRITICAL DIMENSION SHRINK THROUGH SELECTIVE METAL GROWTH ON METAL HARDMASK SIDEWALLS

Номер: US20170148730A1
Автор: Hsueh-Chung H. Chen, Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin, CHEN HSUEH-CHUNG H, HE HONG, LI JUNTAO, YANG CHIH-CHAO, YIN YUNPENG, Chen Hsueh-Chung H., He Hong, Li Juntao, Yang Chih-Chao, Yin Yunpeng
Принадлежит:

A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

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Номер записи: 18
05-12-2017 дата публикации

Fabrication of a vertical fin field effect transistor having a consistent channel width

Номер: US0009837405B1
Автор: Kangguo Cheng, Juntao Li, CHENG KANGGUO, LI JUNTAO, Cheng Kangguo, Li Juntao
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

A method of forming a vertical fin field effect transistor having a consistent channel width, including forming one or more vertical fin(s) on the substrate, wherein the one or more vertical fin(s) have a tapered profile, oxidizing the one or more vertical fin(s) to form an oxide by consuming at least a portion of the vertical fin material, and removing the oxide from the one or more vertical fin(s), wherein the one or more vertical fin(s) include a tapered upper portion, a tapered lower portion and a straight channel portion there between.

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Номер записи: 19
19-09-2012 дата публикации

Construction method of concrete cut-off wall in sludge soil with high water content

Номер: CN102677630A
Автор: Huang Enzhong, Lu Ping, Jin Zhengping, Lu Hongbo, Wang Tianzhao, Li Juntao, Guo Zhongcheng, Han Xinhua
Принадлежит:

The invention relates to a construction method of a concrete cut-off wall in sludge soil with high water content. The construction method mainly comprises the steps of building a guide wall, preparing high-specific-gravity slurry, carrying out joint drilling to form grooves by an abrasion drill and an impact drill which are combined with each other, cleaning the bottom and replacing slurry, carrying out joint construction, manufacturing and installing a steel reinforcement cage, pouring concrete and the like. A construction technology of the concrete cut-off wall designed by the invention is suitable for carrying out high-quality drilling and grooving on river dams under the condition of a soft soil foundation by virtue of an abrasion drill and a percussion drill which are combined; the construction mechanism is clear and the construction quality is easy to control; after the construction is finished, a strict detection means and a reliable reinforcement measure can ensure that the engineering ...

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Номер записи: 20
24-08-2017 дата публикации

METHOD AND STRUCTURE FOR FORMING DIELECTRIC ISOLATED FINFET WITH IMPROVED SOURCE/DRAIN EPITAXY

Номер: US20170243959A1
Автор: Kangguo Cheng, Juntao Li, CHENG KANGGUO, LI JUNTAO, Cheng Kangguo, Li Juntao
Принадлежит:

Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.

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Номер записи: 21
08-05-2013 дата публикации

Blade double-supporting variable-section nozzle ring assembly for bi-directional positioning of poking disc

Номер: CN103089344A
Автор: Wu Xuewen, Li Juntao, Liu Renmei, Hu Qiang
Принадлежит:

The invention discloses a poking disc bi-directional positioning blade double-supporting variable-section nozzle ring assembly which enables a poking disc to be reliably positioned in axial and radial directions, protects the a poking disc from deformation and mis-positioning when a load is large at high temperature, and prevents a shift fork from be dropped out of the poking disc due to the deformation or mis-positioning of the poking disc. The nozzle ring assembly is composed of a rear cover 1, a spring piece 2, a blade 3, a spacer sleeve 4, a mounting disc 5, a heat insulation support disc 6, the poking disc 7, a limiting disc 8, the shift fork 9 and a limiting pin 10. The poking disc 7 is placed in a restricted space formed by the heat insulation support disc 6 and the limiting disc 8, and the poking disc 7 is positioned in the axial and radial directions. The heat insulation support disc 6 and the limiting disc 8 are welded to the mounting disc 5 through the spacer sleeve 4, and the ...

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Номер записи: 22
17-07-2013 дата публикации

Turbocharged direct-current electric actuating mechanism and method for automatically controlling blade openness thereof

Номер: CN103206301A
Автор: Li Juntao, Dong Zhongrong, Yang Qiqing, Liu Zhongfa, Zeng Jiaping
Принадлежит:

The invention discloses a turbocharged direct-current electric actuating mechanism and a method for automatically controlling blade openness thereof. The turbocharged direct-current electric actuating mechanism comprises a direct-current motor, a speed reducing mechanism, a position detecting sensor and a circuit control board, a signal processing circuit comprises a transient voltage restraining and stabilizing module, a PWM (pulse-width modulation) port, a CAN (controller area network) port, a controller, a direct-current motor driving module and a position sensor signal regulating module, the transient voltage restraining and stabilizing module is connected with the PWM port, the CAN port and the direct-current circuit driving module, the controller is connected with the direct-current motor driving module which is connected with the direct-current motor, the speed reducing mechanism is connected with the position detecting sensor and a turbocharger spraying nozzle ring assembly, and ...

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Номер записи: 23
02-01-2018 дата публикации

Asymmetric FET

Номер: US0009859373B2
Автор: Kangguo Cheng, Joseph Ervin, Juntao Li, Chengwen Pei, Geng Wang, CHENG KANGGUO, ERVIN JOSEPH, LI JUNTAO, PEI CHENGWEN, WANG GENG, Cheng Kangguo, Ervin Joseph, Li Juntao, Pei Chengwen, Wang Geng
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that are not covered by a gate structure, at least one dielectric layer is formed to cover the first-side and the second-side epitaxial semiconductor regions and the gate structure. A second-side contact opening is formed within the at least one dielectric layer to expose an entirety of the second-side epitaxial semiconductor region. The exposed second-side epitaxial semiconductor region can be replaced by a new second-side epitaxial semiconductor region having a composition different from the first-side epitaxial semiconductor region or can be doped by additional dopants, thus creating an asymmetric first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region. Each of the first-side epitaxial semiconductor region and the second-side epitaxial semiconducting region can function as either a source or a drain ...

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Номер записи: 24
27-06-2017 дата публикации

Self-forming embedded diffusion barriers

Номер: US0009691656B2
Автор: Cyril Cabral, Jr., Daniel C. Edelstein, Juntao Li, Takeshi Nogami, CABRAL JR CYRIL, EDELSTEIN DANIEL C, LI JUNTAO, NOGAMI TAKESHI, Cabral, Jr. Cyril, Edelstein Daniel C., Li Juntao, Nogami Takeshi
Принадлежит: International Business Machines Corporation, IBM

Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an Mx level including an Mx metal in an Mx dielectric, an Mx+1 level above the Mx level including an Mx+1 metal in an Mx+1 dielectric, an embedded diffusion barrier adjacent to the Mx+1 dielectric; and a seed alloy region adjacent to the Mx+1 metal separating the Mx metal from the Mx+1 metal. The embedded diffusion barrier may include a barrier-forming material such as manganese, aluminum, titanium, or some combination thereof. The seed alloy region may include a seed material such as cobalt, ruthenium, or some combination thereof.

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Номер записи: 25
10-04-2018 дата публикации

Transistor with improved air spacer

Номер: US0009941352B1
Автор: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu, BI ZHENXING, CHENG KANGGUO, LI JUNTAO, XU PENG, Bi Zhenxing, Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит: International Business Machines Corporation, IBM

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate stack disposed on a substrate. A gate contact is disposed in contact with an end portion of the gate stack. An air gap spacer is disposed in contact with a portion of the gate stack. The end portion of the gate stack is absent the air gap spacer. The method includes forming a gate contact in contact with a gate stack. A spacer surrounding at least a portion of the gate stack is removed after the gate contact has been formed. The removal of the spacer forms a trench surrounding the gate stack and stopping at the gate contact. An air gap spacer is formed within the trench.

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Номер записи: 26
21-03-2017 дата публикации

Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy

Номер: US0009601514B1
Автор: Kangguo Cheng, Juntao Li, CHENG KANGGUO, LI JUNTAO, Cheng Kangguo, Li Juntao
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in the source/drain regions on dielectrically isolated fin portions. The fin portions are located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions are oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.

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Номер записи: 27
08-06-2017 дата публикации

METAL REFLOW FOR MIDDLE OF LINE CONTACTS

Номер: US20170162448A1
Автор: Juntao Li, Junli Wang, Chih-Chao Yang, LI JUNTAO, WANG JUNLI, YANG CHIH-CHAO, Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит:

A method of forming a contact in a semiconductor device includes forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD) material arranged between the first gate and the second gate to form a trench that extends from a surface of the first gate and a surface of the second gate to the substrate; depositing a liner along a sidewall of the trench and an endwall of the trench in contact with the substrate; depositing by a physical vapor deposition method (PVD) a layer of metal on a surface of the first gate and a surface of the second gate; and heating to reflow metal from the layer of metal on the surface of the first gate and the second gate into the trench and form the contact.

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Номер записи: 28
04-04-2017 дата публикации

Vertical finfet with strained channel

Номер: US0009614077B1
Автор: Kangguo Cheng, Ramachandra Divakaruni, Juntao Li, CHENG KANGGUO, DIVAKARUNI RAMACHANDRA, LI JUNTAO, Cheng Kangguo, Divakaruni Ramachandra, Li Juntao
Принадлежит: International Business Machines Corporation, IBM

A vertical transistor including a strained vertical semiconductor material channel pillar and a method of forming the same are provided. A strained vertical semiconductor materials pillar is first formed and is used to provide the strained vertical semiconductor material channel pillar of the vertical transistor of the present application. The strained vertical semiconductor material pillar is always mechanically anchored during various vertical transistor processing steps so that in the final structure strain is preserved.

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Номер записи: 29
27-10-2016 дата публикации

METHOD AND STRUCTURE OF FORMING FINFET ELECTRICAL FUSE STRUCTURE

Номер: US20160315049A1
Автор: Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin, HE HONG, LI JUNTAO, YANG CHIH-CHAO, YIN YUNPENG, He Hong, Li Juntao, Yang Chih-Chao, Yin Yunpeng
Принадлежит:

An e-Fuse structure is provided on a surface of an insulator layer of a semiconductor-on-insulator substrate (SOI). The e-Fuse structure includes a first metal semiconductor alloy structure of a first thickness, a second metal semiconductor alloy structure of the first thickness, and a metal semiconductor alloy fuse link is located laterally between and connected to the first and second metal semiconductor alloy structures. The metal semiconductor alloy fuse link has a second thickness that is less than the first thickness.

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Номер записи: 30
27-03-2018 дата публикации

Vertical fuse structures

Номер: US9929091B2
Автор: LI JUNTAO, WANG JUNLI, YANG CHIH-CHAO, Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит: IBM, International Business Machines Corporation

Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein the vertical fuse devices are formed as part of a process flow for fabricating the FINFET devices. For example, a semiconductor device comprises first and second vertical semiconductor fins, a vertical fuse device, and a FINFET device. The vertical fuse device comprises a metal fuse element formed over a portion of the first vertical semiconductor fin, and the FINFET device comprises a metal gate electrode formed over a portion of the second vertical semiconductor fin. The metal fuse element and the metal gate electrode are concurrently formed as part of a replacement metal gate process flow.

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Номер записи: 31
30-05-2017 дата публикации

Middle of the line integrated eFuse in trench EPI structure

Номер: US0009666527B1
Автор: Hong He, Juntao Li, Junli Wang, Chih-Chao Yang, HE HONG, LI JUNTAO, WANG JUNLI, YANG CHIH-CHAO, He Hong, Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

A fuse includes a semiconductor layer having a dielectric material formed thereon. An epitaxially grown material is formed in a trench within the dielectric material. The epitaxially grown material includes a peak region. A fuse metal is formed over the peak region and extends along sidewalls of the trench and over the dielectric material outside the trench. Contacts are formed outside the trench connecting to fuse metal over the dielectric material.

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Номер записи: 32
13-09-2016 дата публикации

FinFET with reduced source and drain resistance

Номер: US0009443977B1
Автор: Kangguo Cheng, Juntao Li, Xin Miao, Junli Wang, CHENG KANGGUO, LI JUNTAO, MIAO XIN, WANG JUNLI, Cheng Kangguo, Li Juntao, Miao Xin, Wang Junli
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method for forming a semiconductor device comprises patterning and etching a fin in a semiconductor substrate, forming a gate stack over the fin, epitaxially growing a first semiconductor material on exposed portions of the fin, epitaxially growing a second semiconductor material on exposed portions of the first semiconductor material, and performing an etching process that removes exposed portions of the first semiconductor material and exposed portions of the second semiconductor material, the etching process is operative to remove portions of the first semiconductor material at a faster rate than the second semiconductor material such that a first cavity is formed adjacent to the fin.

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Номер записи: 33
05-12-2017 дата публикации

Asymmetrical vertical transistor

Номер: US0009837403B1
Автор: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu, BI ZHENXING, CHENG KANGGUO, LI JUNTAO, XU PENG, Bi Zhenxing, Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method of fabricating asymmetric vertical field effect transistors (VFETs) includes forming mandrels above a substrate comprising a first semiconductor material. A first set of spacers is formed adjacent to each side of the mandrels, and trenches are formed in portions of the substrate that are not below one of the mandrels or one of the first set of spacers. The method also includes filling the trenches with a second semiconductor material that is different from the first semiconductor material and forming a second set of spacers adjacent to each respective one of the first set of spacers. The second set of spacers is above the second semiconductor material. A plurality of fins is formed such that each one of the plurality of fins includes a portion of the substrate and a portion of the second semiconductor material. Gates are formed between each adjacent pair of fins.

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Номер записи: 34
30-03-2017 дата публикации

BULK FIN STI FORMATION

Номер: US20170092544A1
Автор: Kangguo Cheng, Juntao Li, Xin Miao, CHENG KANGGUO, LI JUNTAO, MIAO XIN, Cheng Kangguo, Li Juntao, Miao Xin
Принадлежит:

Techniques for STI in fin device structures formed on bulk substrates are provided. In one aspect, a method of forming a fin device in a bulk substrate includes the steps of: forming fins and trenches in between the fins in the bulk substrate; and annealing the bulk substrate in an oxygen ambient under conditions sufficient to form a thermal oxide on sidewalls of the fins and which completely fills the trenches, wherein the thermal oxide forms a STI region between each of the fins. A method of forming a fin device in a bulk substrate is also provided where a deposited STI oxide is used in combination with a thermal oxide. A fin device is also provided.

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Номер записи: 35
10-04-2018 дата публикации

Electrical fuse and/or resistor structures

Номер: US0009941205B2
Автор: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li, BASKER VEERARAGHAVAN S, CHENG KANGGUO, KHAKIFIROOZ ALI, LI JUNTAO, Basker Veeraraghavan S., Cheng Kangguo, Khakifirooz Ali, Li Juntao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.

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Номер записи: 36
04-09-2013 дата публикации

Method for machining variable-section nozzle ring blade of turbocharger

Номер: CN103273404A
Автор: Li Juntao, Yang Qiqing, Wu Xuewen, Zeng Jiaping, Hu Qiang, Lin Chunlan
Принадлежит:

The invention discloses a method for machining a variable-section nozzle ring blade of a turbocharger. The method includes clamping a blade (1) on a rotary fixture; manufacturing a grinding wheel (2) according to the shape of the blade; acquiring the ratio of the feeding width to the feeding depth of the grinding wheel according to ground quantities of a blade rod (3) and a lower end surface (4) of the blade; enabling the grinding wheel to rotate under the control of a computer and obliquely feeding the grinding wheel according to a ratio angle relative to the blade; grinding and machining the blade rod and the lower end surface of the blade simultaneously and automatically measuring the blade rod and the lower end surface of the blade; and automatically withdrawing the grinding wheel after machining requirements are met until a workpiece is machined. The method has the advantages that the blade rod and the lower end surface of the variable-section nozzle ring blade which originally needs ...

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Номер записи: 37
06-07-2017 дата публикации

STRESS MEMORIZATION TECHNIQUE FOR STRAIN COUPLING ENHANCEMENT IN BULK FINFET DEVICE

Номер: US20170194206A1
Автор: Kangguo Cheng, Juntao Li, Chun-Chen Yeh, CHENG KANGGUO, LI JUNTAO, YEH CHUN-CHEN, Cheng Kangguo, Li Juntao, Yeh Chun-Chen
Принадлежит:

A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.

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Номер записи: 38
31-01-2017 дата публикации

Porous silicon relaxation medium for dislocation free CMOS devices

Номер: US0009559120B2
Автор: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana, CHENG KANGGUO, DIVAKARUNI RAMACHANDRA, KIM JEEHWAN, LI JUNTAO, SADANA DEVENDRA K, Cheng Kangguo, Divakaruni Ramachandra, Kim Jeehwan, Li Juntao, Sadana Devendra K.
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

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Номер записи: 39
05-06-2013 дата публикации

Chemical grouting technology

Номер: CN103132528A
Автор: Yao Xin, Shi Jun, Deng Qiang, Li Juntao, Liu Chao, Wang Yuanxun, Yang Jun, Huang Ping, Li Xiao, Wei Shangwei, Huang Jianzhong
Принадлежит:

The invention discloses a chemical grouting technology. The chemical grouting technology comprises process steps of drilling holes, washing drilling holes and pressurized-water, non-irrigation section isolation, water discharge, chemical grouting construction, cement displacement and to-be-coagulated and hole sealing. By adopting a non-irrigation section isolation technology, the chemical grouting technology enhances pertinency of soft and weak low permeation crushed zone chemical grouting, improves construction progress and treatment effect to a large extent, and abandons pre-grouting epoxy by adopting a 'wind-slurry' unified rushing water technology; an earlier period driving rock mass water process greatly reduces acetone storage amount on construction spot by directly grouting high permeating type epoxy resin grouting slurry, and guarantees safety; in the meantime, due to the fact that the epoxy is not grouted any more, so that chemical grouting cost and environment pollution stake ...

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Номер записи: 40
12-09-2017 дата публикации

Forming a fin cut in a hardmask

Номер: US0009761450B1
Автор: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu, BI ZHENXING, CHENG KANGGUO, LI JUNTAO, XU PENG, Bi Zhenxing, Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method of fabricating a hard mask structure is provided. According to the method, a hard mask layer is disposed over a substrate. The hard mask layer includes a lower hard mask layer disposed over the substrate and an upper hard mask layer disposed over the lower hard mask layer. The hard mask layer is patterned and the upper hard mask layer is removed by selectively etching the upper hard mask layer until reaching the lower hard mask layer to form a top portion of the hard mask structure having a first dimension. A spacer material is disposed on a sidewall of the top portion of the hard mask structure. The lower hard mask layer is removed by selectively etching the lower mask layer until reaching the substrate to form a bottom portion of the hard mask structure having a second dimension.

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Номер записи: 41
07-08-2013 дата публикации

Water-phase normal-temperature preparation method of tin-cobalt amorphous composite material

Номер: CN103236527A
Автор: Li Juntao, Wu Zhenguo, Sun Shigang, Zhong Benhe, Huang Ling, Guo Xiaodong
Принадлежит:

The invention relates to a water-phase normal-temperature preparation method of a tin-cobalt amorphous composite material, and relates to a lithium ion battery negative electrode material. According to the invention, the pH value of deionized water is regulated to 0.5-2 by using acid; a tin source, a cobalt source, a surfactant, and a stabilizing agent are added, such that a solution A is obtained; the pH value of deionized water is regulated to 12-14 by using alkali, and a reducing agent is added, such that a solution B is obtained; the solution A, the solution B, and a dispersing agent are mixed, and a reaction is carried out; the pH of the solution is regulated to 0.5-2 by using acid; the solution is stirred, and pump filtration and washing are carried out until an obtained filtrate is neutral; a filter cake obtained by pump filtration is dispersed in an organic solvent; the organic solvent is transferred into a hydrothermal kettle and is subjected to solvothermal processing; the temperature ...

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Номер записи: 42
30-01-2018 дата публикации

Strained CMOS on strain relaxation buffer substrate

Номер: US0009882050B1
Автор: Kangguo Cheng, Juntao Li, Balasubramanian Pranatharthiharan, CHENG KANGGUO, LI JUNTAO, PRANATHARTHIHARAN BALASUBRAMANIAN, Cheng Kangguo, Li Juntao, Pranatharthiharan Balasubramanian
Принадлежит: International Business Machines Corporation, IBM

An advanced FinFET structure is described. The structure includes a strain relaxation buffer (SRB) substrate. A set of cut silicon fins is on the SRB substrate. Each fin in the set of cut silicon fins has a vertical face at a fin end of a respective cut silicon fin. A set of cut silicon germanium fins is on the substrate. Each fin in the set of silicon germanium fins has a vertical face at a fin end of a respective cut silicon germanium fin. A set of tensile dielectric structures contact the vertical faces of the cut silicon fins to maintain tensile strain at the fin ends of the set of cut silicon fins. A set of compressive dielectric structures contact the vertical faces of respective fin ends of the cut silicon germanium fins to maintain compressive strain at the fin ends of the set of cut silicon fins.

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Номер записи: 43
27-09-2016 дата публикации

Y-FET with self-aligned punch-through-stop (PTS) doping

Номер: US0009455314B1
Автор: Kangguo Cheng, Ramachandra Divakaruni, Juntao Li, CHENG KANGGUO, DIVAKARUNI RAMACHANDRA, LI JUNTAO, Cheng Kangguo, Divakaruni Ramachandra, Li Juntao
Принадлежит: International Business Machines Corporation, IBM

A semiconductor structure is provided that includes at least one punch-through stop base structure having concave outermost sidewalls and located on a semiconductor surface of a semiconductor substrate. The structure further includes a pair of semiconductor fins extending upwards from a topmost surface of the at least one punch through stop base structure. The structure even further includes a trench isolation structure located laterally adjacent each of the concave outermost sidewalls of the at least one punch-through stop base structure, wherein a dopant source dielectric material liner is located on each of the concave outermost sidewalls of the at least one punch-through stop base structure and is present between the at least one punch-through stop base structure and the trench isolation structure.

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Номер записи: 44
19-09-2017 дата публикации

Contact having self-aligned air gap spacers

Номер: US9768118B1
Автор: LI JUNTAO, WANG JUNLI, YANG CHIH-CHAO, Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит: IBM, International Business Machines Corporation

A semiconductor device includes a semiconductor substrate, and a dielectric layer on an upper surface of the semiconductor substrate. A contact stack is formed in the dielectric layer. The contact stack includes an electrically conductive contact element, and a contact liner on first and second opposing sidewalls of the contact element. A first air gap is interposed between the dielectric layer and the contact liner on the first side wall, and a second air gap interposed between the dielectric layer and the contact liner on the second side wall.

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Номер записи: 45
03-11-2016 дата публикации

SILICON GERMANIUM ALLOY FINS WITH REDUCED DEFECTS

Номер: US20160322501A1
Автор: Kangguo Cheng, Hong He, Juntao Li, CHENG KANGGUO, HE HONG, LI JUNTAO, Cheng Kangguo, He Hong, Li Juntao
Принадлежит:

A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide upper portion has a greater germanium content than the narrower lower portion. In other embodiments, the silicon germanium alloy fin has a narrow upper portion and a wider lower portion. In this embodiment, the narrow upper portion of the silicon germanium alloy fin has a greater germanium content than the wider lower portion of the silicon germanium alloy fin.

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Номер записи: 46
24-11-2016 дата публикации

DIRECTLY FORMING SiGe FINS ON OXIDE

Номер: US20160343621A1
Автор: Kangguo Cheng, Hong He, Juntao Li, Junli Wang, CHENG KANGGUO, HE HONG, LI JUNTAO, WANG JUNLI, Cheng Kangguo, He Hong, Li Juntao, Wang Junli
Принадлежит:

Semiconductor mandrel structures are formed extending upward from a remaining portion of a semiconductor substrate. A first oxide isolation structure is formed on exposed surfaces of the remaining portion of the semiconductor substrate and between each semiconductor mandrel structure. A silicon germanium alloy fin is formed on opposing sidewalls of each semiconductor mandrel structure that is present in a pFET device region of the semiconductor substrate and directly on a surface of each first oxide isolation structure. Each semiconductor mandrel structure is removed and a second oxide isolation structure is formed between each first oxide isolation structure and extending beneath a bottommost surface of each first oxide isolation structure.

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Номер записи: 47
22-08-2017 дата публикации

Stress retention in fins of fin field-effect transistors

Номер: US0009741856B2
Автор: Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li, Fee Li Lie, Stuart A. Sieg, John R. Sporre, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LI JUNTAO, LIE FEE LI, SIEG STUART A, SPORRE JOHN R, Kanakasabapathy Sivananda K., Karve Gauri, Li Juntao, Lie Fee Li, Sieg Stuart A., Sporre John R.
Принадлежит: International Business Machines Corporation, IBM

Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.

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Номер записи: 48
06-03-2018 дата публикации

Epitaxial silicon germanium fin formation using sacrificial silicon fin templates

Номер: US0009911601B2
Автор: Hong He, Juntao Li, Junli Wang, Chih-Chao Yang, HE HONG, LI JUNTAO, WANG JUNLI, YANG CHIH CHAO, He Hong, Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method of forming semiconductor fins includes forming a plurality of sacrificial template fins from a first semiconductor material; epitaxially growing fins of a second semiconductor material on exposed sidewall surfaces of the sacrificial template fins; and removing the plurality of sacrificial template fins.

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Номер записи: 49
01-08-2017 дата публикации

Electrical fuse and/or resistor structures

Номер: US0009721885B2
Автор: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li, BASKER VEERARAGHAVAN S, CHENG KANGGUO, KHAKIFIROOZ ALI, LI JUNTAO, Basker Veeraraghavan S., Cheng Kangguo, Khakifirooz Ali, Li Juntao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.

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Номер записи: 50
18-12-2013 дата публикации

Niobium steel clad plate welding process

Номер: CN103447665A
Автор: Li Baogan, Li Juntao
Принадлежит:

The invention provides a niobium steel clad plate welding process. By adjusting the welding current and controlling the speed during welding, when a niobium plate layer of a niobium steel clad plate is welded, the situation that a niobium plate layer which is 0.01mm thick at a joint of the niobium plate layer and a steel plate layer is not welded is ensured, accordingly, the steel plate layer can not be melted by high temperature generated when the niobium plate layer is welded, and the defect that the strength of a welded joint sharply declines and even the welded joint cracks due to the mutual melting of niobium and steel caused by the situation that the niobium plate layer leaks by welding is overcome. The niobium steel clad plate welding process has a very high practical value.

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Номер записи: 51
30-01-2018 дата публикации

Middle of the line integrated efuse in trench EPI structure

Номер: US0009881869B2
Автор: Hong He, Juntao Li, Junli Wang, Chih-Chao Yang, HE HONG, LI JUNTAO, WANG JUNLI, YANG CHIH-CHAO, He Hong, Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

A fuse includes a semiconductor layer having a dielectric material formed thereon. An epitaxially grown material is formed in a trench within the dielectric material. The epitaxially grown material includes a peak region. A fuse metal is formed over the peak region and extends along sidewalls of the trench and over the dielectric material outside the trench. Contacts are formed outside the trench connecting to fuse metal over the dielectric material.

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Номер записи: 52
08-08-2017 дата публикации

iFinFET

Номер: US0009728621B1
Автор: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang, CHENG KANGGUO, LI JUNTAO, WANG GENG, ZHANG QINTAO, Cheng Kangguo, Li Juntao, Wang Geng, Zhang Qintao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method of manufacturing an integrated circuit is provided. According to the method, a layered fin including a plurality of sacrificial layers and semiconductor layers wherein two adjacent semiconductor layers are separated by the sacrificial layer is provided on a semiconductor substrate. A gate over the layered fin and a spacer surrounding a sidewall of the gate are then formed. The sacrificial layers are subsequently removed to provide a structure in which two adjacent semiconductor layers are separated by a gap. The method further includes forming an insulator in the gap and forming source and drain regions located on the layered fin. The insulator includes a high-K dielectric material surrounded by a low-K dielectric material, both of which are in contact with the two adjacent semiconductor layers.

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Номер записи: 53
15-08-2017 дата публикации

Stacked nanowire devices

Номер: US0009735234B1
Автор: Kangguo Cheng, Ramachandra Divakaruni, Juntao Li, CHENG KANGGUO, DIVAKARUNI RAMACHANDRA, LI JUNTAO, Cheng Kangguo, Divakaruni Ramachandra, Li Juntao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.

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Номер записи: 54
01-12-2016 дата публикации

PREVENTING STRAINED FIN RELAXATION

Номер: US20160351590A1
Автор: Kangguo Cheng, Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li, Fee Li Lie, Derrick Liu, Chun Wing Yeung, CHENG KANGGUO, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LI JUNTAO, LIE FEE LI, LIU DERRICK, YEUNG CHUN WING, Cheng Kangguo, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Li Juntao, Lie Fee Li, Liu Derrick, Yeung Chun Wing
Принадлежит:

A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

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Номер записи: 55
19-09-2017 дата публикации

Method and structure of forming FinFET electrical fuse structure

Номер: US9768276B2
Автор: HE HONG, LI JUNTAO, YANG CHIH-CHAO, YIN YUNPENG, He Hong, Li Juntao, Yang Chih-Chao, Yin Yunpeng
Принадлежит: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

An e-Fuse structure is provided on a surface of an insulator layer of a semiconductor-on-insulator substrate (SOI). The e-Fuse structure includes a first metal semiconductor alloy structure of a first thickness, a second metal semiconductor alloy structure of the first thickness, and a metal semiconductor alloy fuse link is located laterally between and connected to the first and second metal semiconductor alloy structures. The metal semiconductor alloy fuse link has a second thickness that is less than the first thickness.

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Номер записи: 56
13-03-2018 дата публикации

Vertical antifuse structures

Номер: US0009917090B1
Автор: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang, CHENG KANGGUO, LI JUNTAO, WANG GENG, ZHANG QINTAO, Cheng Kangguo, Li Juntao, Wang Geng, Zhang Qintao
Принадлежит: International Business Machines Corporation, IBM

Semiconductor devices and methods are provided in which vertical antifuse devices are integrally formed with vertical FET devices, wherein the vertical antifuse devices are formed as part of a process flow for fabricating the vertical FET devices. For example, a semiconductor device comprises a lower source/drain region formed on a substrate, and first and second vertical semiconductor fins formed on the lower source/drain region. First and second metal gate electrodes are formed on sidewalls of the first and second vertical semiconductor fins, respectively. An upper source/drain region is formed on an upper surface of the first vertical semiconductor fin, and a vertical source/drain contact is formed in contact with the upper source/drain region formed on the first vertical semiconductor fin. An upper end of the second vertical semiconductor fin is encapsulated in an insulating material so that the upper end of the second vertical semiconductor fin is floating.

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Номер записи: 57
16-03-2017 дата публикации

POROUS SILICON RELAXATION MEDIUM FOR DISLOCATION FREE CMOS DEVICES

Номер: US20170076999A1
Автор: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana, CHENG KANGGUO, DIVAKARUNI RAMACHANDRA, KIM JEEHWAN, LI JUNTAO, SADANA DEVENDRA K, Cheng Kangguo, Divakaruni Ramachandra, Kim Jeehwan, Li Juntao, Sadana Devendra K.
Принадлежит:

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer. 1. A method for forming complementary metal oxide semiconductor devices , comprising:masking a first portion of a tensile-strained silicon layer of a silicon on insulator substrate with a hard mask;etching a second portion of the tensile-strained silicon layer outside the first portion;doping the second portion of the tensile-strained silicon layer outside the first portion;growing an undoped silicon layer on the doped portion;removing the hard mask;relaxing strain in the undoped silicon layer over the doped portion by converting the doped portion to a porous silicon to form a relaxed silicon layer;converting the porous silicon to an oxide;growing a SiGe layer on the relaxed silicon layer;oxidizing the SiGe layer to convert the relaxed silicon layer to a compressed SiGe layer; andetching fins in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.2. The method as recited in claim 1 , wherein doping the second portion of the tensile-strained silicon layer include boron doping the second portion.3. The method as recited in claim 1 , wherein relaxing strain in the undoped silicon layer over the doped portion ...

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Номер записи: 58
13-02-2018 дата публикации

Method and structure for forming a dense array of single crystalline semiconductor nanocrystals

Номер: US0009892910B2
Автор: Kangguo Cheng, Hong He, Juntao Li, CHENG KANGGUO, HE HONG, LI JUNTAO, Cheng Kangguo, He Hong, Li Juntao
Принадлежит: International Business Machines Corporation, IBM

A dense array of semiconductor single crystalline semiconductor nanocrystals is provided in the present application by forming an amorphous semiconductor material layer surrounding a plurality of patterned nanostructures comprised of a single crystalline semiconductor material portion. A thermal anneal, i.e., (solid phase epitaxy), is then performed to crystallize a portion of the amorphous semiconductor material layer that is in contact with each single crystalline semiconductor material portion and to provide a plurality of spaced apart single crystalline nanocrystals on a surface of an insulator. A remaining portion of the amorphous semiconductor material layer that was not crystallized is thereafter removed.

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Номер записи: 59
08-06-2017 дата публикации

METAL REFLOW FOR MIDDLE OF LINE CONTACTS

Номер: US20170162393A1
Автор: Juntao Li, Junli Wang, Chih-Chao Yang, LI JUNTAO, WANG JUNLI, YANG CHIH-CHAO, Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит:

A method of forming a contact in a semiconductor device includes forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD) material arranged between the first gate and the second gate to form a trench that extends from a surface of the first gate and a surface of the second gate to the substrate; depositing a liner along a sidewall of the trench and an endwall of the trench in contact with the substrate; depositing by a physical vapor deposition method (PVD) a layer of metal on a surface of the first gate and a surface of the second gate; and heating to reflow metal from the layer of metal on the surface of the first gate and the second gate into the trench and form the contact.

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Номер записи: 60
17-11-2016 дата публикации

METHOD AND STRUCTURE FOR FORMING A DENSE ARRAY OF SINGLE CRYSTALLINE SEMICONDUCTOR NANOCRYSTALS

Номер: US20160336176A1
Автор: Kangguo Cheng, Hong He, Juntao Li, CHENG KANGGUO, HE HONG, LI JUNTAO, Cheng Kangguo, He Hong, Li Juntao
Принадлежит:

A dense array of semiconductor single crystalline semiconductor nanocrystals is provided in the present application by forming an amorphous semiconductor material layer surrounding a plurality of patterned nanostructures comprised of a single crystalline semiconductor material portion. A thermal anneal, i.e., (solid phase epitaxy), is then performed to crystallize a portion of the amorphous semiconductor material layer that is in contact with each single crystalline semiconductor material portion and to provide a plurality of spaced apart single crystalline nanocrystals on a surface of an insulator. A remaining portion of the amorphous semiconductor material layer that was not crystallized is thereafter removed.

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Номер записи: 61
20-02-2018 дата публикации

Forming gates with varying length using sidewall image transfer

Номер: US0009899383B2
Автор: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang, CHENG KANGGUO, LI JUNTAO, WANG GENG, ZHANG QINTAO, Cheng Kangguo, Li Juntao, Wang Geng, Zhang Qintao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

A chip includes multiple first transistors in a first region and multiple second transistors in a second region. A gap between adjacent first transistors has a same width as a gap between adjacent second transistors. Gates of the second transistors have a length substantially the same as twice a length of two adjacent first transistors plus the distance between said two adjacent first transistors.

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Номер записи: 62
16-03-2017 дата публикации

FIN ISOLATION ON A BULK WAFER

Номер: US20170076992A1
Автор: Hong He, Juntao Li, Junli Wang, Chih-Chao Yang, HE HONG, LI JUNTAO, WANG JUNLI, YANG CHIH-CHAO, He Hong, Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит:

A method for forming a semiconductor device includes etching first fins into a bulk semiconductor substrate and exposing a portion of the first fins through a first dielectric layer formed over the first fins. A first film is deposited over the first fins in a region for n-type devices, and a second film is deposited over the first fins in a region for p-type devices. The first film and the second film are etched to form second fins in the regions for n-type devices and for the region for p-type devices. The second fins are protected. The first fins are removed from the first dielectric layer to form an isolation layer separating the second fins from the substrate. 1. A method for forming a semiconductor device , comprising:etching first fins into a bulk semiconductor substrate;exposing a portion of the first fins through a first dielectric layer formed over the first fins;depositing a first film over the first fins in a region for n-type devices;depositing a second film over the first fins in a region for p-type devices;etching the first film and the second film to form second fins in the regions for n-type devices and for the region for p-type devices;protecting the second fins; andremoving the first fins from the first dielectric layer to form an isolation layer separating the second fins from the substrate.2. The method as recited in claim 1 , wherein depositing the first film over the first fins in a region for n-type devices includes epitaxially growing the first film on the first fins.3. The method as recited in claim 1 , wherein depositing the second film over the first fins in a region for p-type devices includes:epitaxially growing materials for the second film on the first fins; andthermally mixing the materials to form the second film.4. The method as recited in claim 1 , wherein at least one of the first film and the second film includes an amorphous phase and further comprising: recrystallizing the at least one of the first film and the second film.5. ...

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Номер записи: 63
16-05-2017 дата публикации

Bulk fin STI formation

Номер: US0009653359B2
Автор: Kangguo Cheng, Juntao Li, Xin Miao, CHENG KANGGUO, LI JUNTAO, MIAO XIN, Cheng Kangguo, Li Juntao, Miao Xin
Принадлежит: International Business Machines Corporation, IBM

Techniques for STI in fin device structures formed on bulk substrates are provided. In one aspect, a method of forming a fin device in a bulk substrate includes the steps of: forming fins and trenches in between the fins in the bulk substrate; and annealing the bulk substrate in an oxygen ambient under conditions sufficient to form a thermal oxide on sidewalls of the fins and which completely fills the trenches, wherein the thermal oxide forms a STI region between each of the fins. A method of forming a fin device in a bulk substrate is also provided where a deposited STI oxide is used in combination with a thermal oxide. A fin device is also provided.

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Номер записи: 64
25-05-2017 дата публикации

METHOD OF FABRICATING ANTI-FUSE FOR SILICON ON INSULATOR DEVICES

Номер: US20170148733A1
Автор: Kangguo Cheng, Ali Khakifirooz, Juntao Li, CHENG KANGGUO, KHAKIFIROOZ ALI, LI JUNTAO, Cheng Kangguo, Khakifirooz Ali, Li Juntao
Принадлежит:

A method includes depositing a first hard mask layer on a first substrate; lithographically patterning and etching the first substrate to form a semiconductor link connected to an anode semiconductor region and a cathode semiconductor region; removing the first hard mask layer from the first substrate; depositing a second hard mask layer on the first substrate; patterning a photoresist on the first substrate and etching to form an opening in the semiconductor link; etching to remove portions of the second hard mask layer to expose a portion of a sidewall of the semiconductor link; removing the photoresist from the first substrate and the semiconductor link; and recessing the sidewalls of the semiconductor link forming first anti-fuse tip and second anti-fuse tip to form an anti-fuse with an opening between the first and second anti-fuse tips.

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Номер записи: 65
21-11-2012 дата публикации

Preparation method of nanoscale silicon materials for lithium ion battery cathode materials

Номер: CN102790206A
Автор: Sun Shigang, Liu Jie, Zhang Qian, Li Juntao, Huang Ling
Принадлежит:

The invention discloses a preparation method of nanoscale silicon materials for lithium ion battery cathode materials and relates to nanoscale silicon materials. The preparation method of the nanoscale silicon materials for the lithium ion battery cathode materials is simple in process, cheap in raw materials, easy for production and industrialization and controllable in grain size and grain size range. The preparation method includes: dispersing silicon powder into solvent so as to obtain suspension; centrifuging the suspension for the first time so as to obtain upper suspension, and mechanically pulverizing large solid silicon particles on the lower layer for recycling; and centrifuging the upper suspension for the second time, and taking and drying solids on the lower layer so that the nanoscale silicon materials are obtained.

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Номер записи: 66
23-03-2017 дата публикации

STRESS MEMORIZATION TECHNIQUE FOR STRAIN COUPLING ENHANCEMENT IN BULK FINFET DEVICE

Номер: US20170084743A1
Автор: Kangguo Cheng, Juntao Li, Chun-Chen Yeh, CHENG KANGGUO, LI JUNTAO, YEH CHUN-CHEN, Cheng Kangguo, Li Juntao, Yeh Chun-Chen
Принадлежит:

A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins. 1. A semiconductor device , comprising:a bulk substrate having staircase fin structures including a larger base portion below a shallow trench isolation region and a narrower top portion above the shallow trench isolation region;a defect introduced into the substrate by a pre-amorphization implant to couple strain into the top portion of the fins;a gate structure formed transversely over the top portion of the fins; andsource and drain regions formed on the top portion of the fins on opposite sides of the gate structure.2. The semiconductor device as recited in claim 1 , wherein the pre-amorphization implant includes a material selected from the group consisting of Ge and Xe.3. The semiconductor device as recited in claim 1 , wherein the staircase fin structures include an abrupt step between the larger base portion and the narrower top portion.4. The semiconductor device as recited in claim 1 , wherein the narrower top portion is buried in the source and drain regions.5. The semiconductor device as recited in claim 1 , wherein the top portion includes a trapezoidal shape.6. The semiconductor device as recited in claim 1 , wherein the top portion includes a rectangular shape. Technical FieldThe present invention relates to semiconductor devices and processing, and more particularly to a staircase fin field effect transistor ( ...

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Номер записи: 67
05-09-2017 дата публикации

Fabrication of vertical field effect transistor structure with strained channels

Номер: US0009755073B1
Автор: Kangguo Cheng, Juntao Li, CHENG KANGGUO, LI JUNTAO, Cheng Kangguo, Li Juntao
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, including forming one or more vertical fins on a substrate, forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins, forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks, forming an anchor wall adjacent to and in contact with one or more fin segment endwalls, and removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.

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Номер записи: 68
06-10-2016 дата публикации

HYBRID ASPECT RATIO TRAPPING

Номер: US20160293704A1
Автор: Kangguo Cheng, Ramachandra Divakaruni, Hong He, Juntao Li, CHENG KANGGUO, DIVAKARUNI RAMACHANDRA, HE HONG, LI JUNTAO, Cheng Kangguo, Divakaruni Ramachandra, He Hong, Li Juntao
Принадлежит:

A semiconductor structure includes a material stack located on a surface of a semiconductor substrate. The material stack includes, from bottom to top, a silicon germanium alloy portion that is substantially relaxed and defect-free and a semiconductor material pillar that is defect-free. A dielectric material structure surrounds sidewalls of the material stack and is present on exposed portions of the semiconductor substrate.

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Номер записи: 69
13-03-2018 дата публикации

Porous silicon relaxation medium for dislocation free CMOS devices

Номер: US0009917021B2
Автор: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana, CHENG KANGGUO, DIVAKARUNI RAMACHANDRA, KIM JEEHWAN, LI JUNTAO, SADANA DEVENDRA K, Cheng Kangguo, Divakaruni Ramachandra, Kim Jeehwan, Li Juntao, Sadana Devendra K.
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

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Номер записи: 70
01-11-2016 дата публикации

Epitaxial silicon germanium fin formation using sacrificial silicon fin templates

Номер: US0009484201B2
Автор: Hong He, Juntao Li, Junli Wang, Chih-Chao Yang, HE HONG, LI JUNTAO, WANG JUNLI, YANG CHIH-CHAO, He Hong, Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method of forming semiconductor fins includes forming a plurality of sacrificial template fins from a first semiconductor material; epitaxially growing fins of a second semiconductor material on exposed sidewall surfaces of the sacrificial template fins; and removing the plurality of sacrificial template fins.

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Номер записи: 71
23-03-2017 дата публикации

STRESS MEMORIZATION TECHNIQUE FOR STRAIN COUPLING ENHANCEMENT IN BULK FINFET DEVICE

Номер: US20170084744A1
Автор: Kangguo Cheng, Juntao Li, Chun-Chen Yeh, CHENG KANGGUO, LI JUNTAO, YEH CHUN-CHEN, Cheng Kangguo, Li Juntao, Yeh Chun-Chen
Принадлежит:

A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins. 1. A method for forming strained fins , comprising:recessing a dielectric fill into trenches in a substrate to form shallow trench isolation regions, the trenches being etched into the substrate to form fins;etching the fins above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins;forming gate structures over the top portions of the fins;epitaxially growing raised source and drain regions on opposite sides of the gate structure; andperforming a pre-amorphization implant to generate defects in the substrate to induce strain and to couple the strain into the top portions of the fins.2. The method as recited in claim 1 , further comprising performing a stress memorization technique (SMT) anneal to propagate the strain after the pre-amorphization implant.3. The method as recited in claim 1 , further comprising:forming mandrels;forming spacers on the mandrels to form an etch mask for etching the trenches; andetching the trenches in the substrate, using the etch mask, to form the fins.4. The method as recited in claim 1 , further comprising:depositing a high aspect ratio process (HARP) oxide into the trenches and over the substrate; andplanarizing the HARP oxide to a top of the fins.5. The method as recited in claim 1 , wherein the etching the fins above the shallow trench ...

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Номер записи: 72
19-12-2017 дата публикации

Multiple finFET formation with epitaxy separation

Номер: US0009847246B1
Автор: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang, CHENG KANGGUO, LI JUNTAO, WANG GENG, ZHANG QINTAO, Cheng Kangguo, Li Juntao, Wang Geng, Zhang Qintao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A semiconductor device includes a buried epitaxially grown substrate and a silicon on insulator (SOI) layer. The device also includes a buried oxide (BOX) layer between the buried epitaxially grown substrate and the SOI layer, an isolation trench having first width (w1), a contact trench having a second width (w2) and a capacitive trench having a third width (w3). Methods are described that allow the formation of the trenches in a normal process flow.

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Номер записи: 73
09-05-2017 дата публикации

Vertical FET symmetric and asymmetric source/drain formation

Номер: US0009647120B1
Автор: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu, BI ZHENXING, CHENG KANGGUO, LI JUNTAO, XU PENG, Bi Zhenxing, Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method for forming features of a vertical FET device, starting with a semiconductor substrate that includes fins and a horizontal surface. The fins also have a base, a top, and sidewalls. An etch process is performed to create bottom lateral recesses at the base of the fins. The method continues with growing a bottom source/drain region in the bottom recesses which forms PN junctions, and etching the fins to form top lateral recesses at the top of the fins. The method continues with growing a top source/drain region in the top recesses of the fins, therefore forming PN junctions.

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Номер записи: 74
06-03-2018 дата публикации

Integrated strained stacked nanosheet FET

Номер: US0009911834B2
Автор: Kangguo Cheng, Ramachandra Divakaruni, Juntao Li, Xin Miao, CHENG KANGGUO, DIVAKARUNI RAMACHANDRA, LI JUNTAO, MIAO XIN, Cheng Kangguo, Divakaruni Ramachandra, Li Juntao, Miao Xin
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

Transistors include multiple stress liners. One or more channel structures are suspended at opposite ends from the plurality of stress liners. The stress liners provide a stress on the one or more channel structures. A gate is formed over and around the one or more channel structures, defining a channel region of the one or more channel structures that is covered by the gate. A source and drain region are formed on opposite sides of the gate.

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Номер записи: 75
28-03-2017 дата публикации

Hybrid aspect ratio trapping

Номер: US0009608067B2
Автор: Kangguo Cheng, Ramachandra Divakaruni, Hong He, Juntao Li, CHENG KANGGUO, DIVAKARUNI RAMACHANDRA, HE HONG, LI JUNTAO, Cheng Kangguo, Divakaruni Ramachandra, He Hong, Li Juntao
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

A semiconductor structure includes a material stack located on a surface of a semiconductor substrate. The material stack includes, from bottom to top, a silicon germanium alloy portion that is substantially relaxed and defect-free and a semiconductor material pillar that is defect-free. A dielectric material structure surrounds sidewalls of the material stack and is present on exposed portions of the semiconductor substrate.

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Номер записи: 76
04-12-2013 дата публикации

Tantalum-steel composite plate welding process

Номер: CN103418922A
Автор: Li Baogan, Li Juntao
Принадлежит:

Provided is a tantalum-steel composite plate welding process. By means of adjusting welding currents and controlling the welding speed, when a tantalum plate layer of a tantalum-steel composite plate is welded, the situation that the tantalum plate layer with a thickness of 0.01mm at the connection portion of the tantalum plate layer and a steel plate layer is not welded is guaranteed, so high temperature generated when the tantalum plate layer is welded cannot melt the steel plate layer, the defects that open soldering occurs to the tantalum plate layer, as a result, tantalum and steel are fused, the strength of the welding portion is dramatically reduced, and even cracking defects occur are overcome, and high practical value is achieved.

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Номер записи: 77
26-09-2012 дата публикации

RFID (Radio Frequency Identification) label with air-sensitive device, RFID system and air concentration detection method

Номер: CN102693448A
Автор: Huo Lingyu, Liu Bingwu, Wang Yuquan, Tian Zhiyong, Li Juntao
Принадлежит:

The invention provides an RFID (Radio Frequency Identification) label with an air-sensitive device, an RFID system and an air concentration detection method. Two pins are arranged on a chip of the RFID label; a parallel structure is formed by the air-sensitive device and an antenna of the RFID label; a logical circuit for controlling switch-on/off is arranged on a line connecting the air-sensitive device with the chip of the RFID label; the connecting line and the logical circuit for controlling switch-on/off are one parts of the chip; when the logical circuit is switched off, the air-sensitive device is not in parallel connection with the antenna, and after the air-sensitive device is placed for a period of time under the condition of a certain air concentration, a first resonant frequency and the signal strength of the antenna are kept unchanged; when the logical circuit is switched on, the air-sensitive device is in parallel connection with the antenna, and after the air-sensitive device ...

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Номер записи: 78
30-08-2016 дата публикации

Stress memorization technique for strain coupling enhancement in bulk finFET device

Номер: US0009431521B1
Автор: Kangguo Cheng, Juntao Li, Chun-Chen Yeh, CHENG KANGGUO, LI JUNTAO, YEH CHUN-CHEN, Cheng Kangguo, Li Juntao, Yeh Chun-Chen
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.

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Номер записи: 79
30-08-2016 дата публикации

Directly forming SiGe fins on oxide

Номер: US0009431425B1
Автор: Kangguo Cheng, Hong He, Juntao Li, Junli Wang, CHENG KANGGUO, HE HONG, LI JUNTAO, WANG JUNLI, Cheng Kangguo, He Hong, Li Juntao, Wang Junli
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

Semiconductor mandrel structures are formed extending upward from a remaining portion of a semiconductor substrate. A first oxide isolation structure is formed on exposed surfaces of the remaining portion of the semiconductor substrate and between each semiconductor mandrel structure. A silicon germanium alloy fin is formed on opposing sidewalls of each semiconductor mandrel structure that is present in a pFET device region of the semiconductor substrate and directly on a surface of each first oxide isolation structure. Each semiconductor mandrel structure is removed and a second oxide isolation structure is formed between each first oxide isolation structure and extending beneath a bottommost surface of each first oxide isolation structure.

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Номер записи: 80
31-01-2017 дата публикации

Ultra-thin metal wires formed through selective deposition

Номер: US0009558999B2
Автор: Juntao Li, Chih-Chao Yang, Yunpeng Yin, LI JUNTAO, YANG CHIH-CHAO, YIN YUNPENG, Li Juntao, Yang Chih-Chao, Yin Yunpeng
Принадлежит: GLOBALFOUNDRIES INC., GLOBALFOUNDRIES INC

The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a pair of ultra-thin metal wires in an opening using a selective deposition process.

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Номер записи: 81
01-12-2016 дата публикации

CRITICAL DIMENSION SHRINK THROUGH SELECTIVE METAL GROWTH ON METAL HARDMASK SIDEWALLS

Номер: US20160351448A1
Автор: Hsueh-Chung H. Chen, Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin, CHEN HSUEH-CHUNG H, HE HONG, LI JUNTAO, YANG CHIH-CHAO, YIN YUNPENG, Chen Hsueh-Chung H., He Hong, Li Juntao, Yang Chih-Chao, Yin Yunpeng
Принадлежит:

A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

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Номер записи: 82
13-12-2016 дата публикации

Anti-fuse structure and method for manufacturing the same

Номер: US0009520357B1
Автор: Hong He, Juntao Li, Junli Wang, Chih-Chao Yang, HE HONG, LI JUNTAO, WANG JUNLI, YANG CHIH-CHAO, He Hong, Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит: International Business Machines Corporation, IBM

A method for manufacturing a semiconductor device includes forming a fin extending between first and second pads on a substrate, removing a central portion of the fin to create an opening between a first part of the fin extending from the first pad and a second part of the fin extending from the second pad, growing first and second epitaxial layers in the opening on a side of respective first and second parts of the fin, stopping the growth of the first and second epitaxial layers prior to merging, forming a silicide layer on the first and second pads, first and second parts of the fin and first and second epitaxial layers, wherein there is a gap between portions of the silicide layer on the first and second epitaxial layers in the opening, and depositing a dielectric layer on the silicide layer, filling in the gap.

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Номер записи: 83
07-09-2017 дата публикации

DIRECTIONAL DEPOSITION OF PROTECTION LAYER

Номер: US20170256644A1
Автор: Hong He, Juntao Li, Junli Wang, Chih-Chao Yang, HE HONG, LI JUNTAO, WANG JUNLI, YANG CHIH-CHAO, He Hong, Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит:

A method for forming a fin device includes forming semiconductor fins over a first dielectric layer. A second dielectric layer is directionally deposited into or on the first dielectric layer and on tops of the fins on horizontal surfaces. The second dielectric layer is configured to protect the first dielectric layer in subsequent processing. Sidewalls of the fins are precleaned while the first dielectric layer is protected by the second dielectric layer. The second dielectric layer is removed to expose the first dielectric layer in a protected state.

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Номер записи: 84
12-12-2017 дата публикации

High density nanosheet diodes

Номер: US0009842835B1
Автор: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang, CHENG KANGGUO, LI JUNTAO, WANG GENG, ZHANG QINTAO, Cheng Kangguo, Li Juntao, Wang Geng, Zhang Qintao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

Embodiments are directed to a method for forming a semiconductor structure by depositing a stack of alternating layers of two materials over a substrate and defining field-effect transistor and diode regions. The method further includes depositing a mask, where the mask covers only the field-effect transistor region while leaving the diode region uncovered. The method further includes doping the material in the diode region with a dopant, implanting epitaxial material with another dopant to form PN junctions, stripping the mask from the structure, forming a metal gate conductor over the field-effect transistor region, and depositing a metal over the substrate to create terminals.

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Номер записи: 85
21-02-2017 дата публикации

Preventing strained fin relaxation by sealing fin ends

Номер: US0009576979B2
Автор: Kangguo Cheng, Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li, Fee Li Lie, Derrick Liu, Chun Wing Yeung, CHENG KANGGUO, DORIS BRUCE B, HE HONG, KANAKASABAPATHY SIVANANDA K, KARVE GAURI, LI JUNTAO, LIE FEE LI, LIU DERRICK, YEUNG CHUN WING, Cheng Kangguo, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Li Juntao, Lie Fee Li, Liu Derrick, Yeung Chun Wing
Принадлежит: International Business Machines Corporation, IBM

A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

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Номер записи: 86
15-06-2017 дата публикации

BULK SILICON GERMANIUM FinFET

Номер: US20170170173A1
Автор: Kangguo Cheng, Juntao Li, Shogo Mochizuki, CHENG KANGGUO, LI JUNTAO, MOCHIZUKI SHOGO, Cheng Kangguo, Li Juntao, Mochizuki Shogo
Принадлежит:

A bulk SiGe FinFET which includes: a plurality of SiGe fins and a bulk semiconductor substrate, the SiGe fins extending from the bulk semiconductor substrate; the SiGe fins having a top portion and a bottom portion, a part of the bottom portion being doped to form a punchthrough stop; the bulk semiconductor substrate having a top portion in contact with the SiGe fins and comprising a gradient of germanium and silicon, and a bottom portion of silicon in contact with the top portion such that the gradient has a composition of SiGe at the top portion in contact with the SiGe fins that is the same composition of SiGe as in the SiGe fins, the proportion of germanium atoms in the gradient gradually decreasing and the proportion of silicon atoms in the gradient gradually increasing in the gradient until the top portion contacts the bottom portion.

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Номер записи: 87
03-04-2018 дата публикации

Nanosheet transistors having different gate dielectric thicknesses on the same chip

Номер: US0009935014B1
Автор: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang, CHENG KANGGUO, LI JUNTAO, WANG GENG, ZHANG QINTAO, Cheng Kangguo, Li Juntao, Wang Geng, Zhang Qintao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.

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Номер записи: 88
06-07-2017 дата публикации

ANTI-FUSE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20170194250A1
Автор: Hong He, Juntao Li, Junli Wang, Chih-Chao Yang, HE HONG, LI JUNTAO, WANG JUNLI, YANG CHIH-CHAO, He Hong, Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит:

A method for manufacturing a semiconductor device includes forming a fin extending between first and second pads on a substrate, removing a central portion of the fin to create an opening between a first part of the fin extending from the first pad and a second part of the fin extending from the second pad, growing first and second epitaxial layers in the opening on a side of respective first and second parts of the fin, stopping the growth of the first and second epitaxial layers prior to merging, forming a silicide layer on the first and second pads, first and second parts of the fin and first and second epitaxial layers, wherein there is a gap between portions of the silicide layer on the first and second epitaxial layers in the opening, and depositing a dielectric layer on the silicide layer, filling in the gap.

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Номер записи: 89
14-11-2017 дата публикации

Approach to minimization of strain loss in strained fin field effect transistors

Номер: US0009818875B1
Автор: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu, BI ZHENXING, CHENG KANGGUO, LI JUNTAO, XU PENG, Bi Zhenxing, Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.

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Номер записи: 90
23-01-2018 дата публикации

Systems and methods for graphics process units power management

Номер: US0009875516B2
Автор: Juntao Li, Steven Gao, LI JUNTAO, GAO STEVEN, Li Juntao, Gao Steven
Принадлежит: MARVELL WORLD TRADE LTD., MARVELL WORLD TRADE LTD, Marvell World Trade Ltd.

Systems and methods are provided for frequency adjustment of graphics process units (GPUs). A system includes: a command parser configured to parse one or more first commands associated with one or more future GPU operations to obtain command information, a processing component configured to determine an operation time for the future GPU operations based at least in part on the command information, and a frequency control component configured to adjust a GPU frequency based at least in part on the operation time for the future GPU operations.

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Номер записи: 91
27-10-2016 дата публикации

METHOD AND STRUCTURE OF FORMING FINFET ELECTRICAL FUSE STRUCTURE

Номер: US20160315175A1
Автор: Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin, HE HONG, LI JUNTAO, YANG CHIH-CHAO, YIN YUNPENG, He Hong, Li Juntao, Yang Chih-Chao, Yin Yunpeng
Принадлежит:

An e-Fuse structure is provided on a surface of an insulator layer of a semiconductor-on-insulator substrate (SOI). The e-Fuse structure includes a first metal semiconductor alloy structure of a first thickness, a second metal semiconductor alloy structure of the first thickness, and a metal semiconductor alloy fuse link is located laterally between and connected to the first and second metal semiconductor alloy structures. The metal semiconductor alloy fuse link has a second thickness that is less than the first thickness.

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Номер записи: 92
15-08-2017 дата публикации

Bulk silicon germanium FinFET

Номер: US0009735155B2
Автор: Kangguo Cheng, Juntao Li, Shogo Mochizuki, CHENG KANGGUO, LI JUNTAO, MOCHIZUKI SHOGO, Cheng Kangguo, Li Juntao, Mochizuki Shogo
Принадлежит: International Business Machines Corporation, IBM

A bulk SiGe FinFET which includes: a plurality of SiGe fins and a bulk semiconductor substrate, the SiGe fins extending from the bulk semiconductor substrate; the SiGe fins having a top portion and a bottom portion, a part of the bottom portion being doped to form a punchthrough stop; the bulk semiconductor substrate having a top portion in contact with the SiGe fins and comprising a gradient of germanium and silicon, and a bottom portion of silicon in contact with the top portion such that the gradient has a composition of SiGe at the top portion in contact with the SiGe fins that is the same composition of SiGe as in the SiGe fins, the proportion of germanium atoms in the gradient gradually decreasing and the proportion of silicon atoms in the gradient gradually increasing in the gradient until the top portion contacts the bottom portion.

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Номер записи: 93
13-02-2018 дата публикации

Stress memorization technique for strain coupling enhancement in bulk finFET device

Номер: US0009892973B2
Автор: Kangguo Cheng, Juntao Li, Chun-Chen Yeh, CHENG KANGGUO, LI JUNTAO, YEH CHUN CHEN, Cheng Kangguo, Li Juntao, Yeh Chun-Chen
Принадлежит: International Business Machines Corporation, IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION

A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.

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Номер записи: 94
12-10-2017 дата публикации

DIRECTIONAL DEPOSITION OF PROTECTION LAYER

Номер: US20170294524A1
Автор: Hong He, Juntao Li, Junli Wang, Chih-Chao Yang, HE HONG, LI JUNTAO, WANG JUNLI, YANG CHIH-CHAO, He Hong, Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит:

A method for forming a fin device includes forming semiconductor fins over a first dielectric layer. A second dielectric layer is directionally deposited into or on the first dielectric layer and on tops of the fins on horizontal surfaces. The second dielectric layer is configured to protect the first dielectric layer in subsequent processing. Sidewalls of the fins are precleaned while the first dielectric layer is protected by the second dielectric layer. The second dielectric layer is removed to expose the first dielectric layer in a protected state.

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Номер записи: 95
05-06-2013 дата публикации

Grouting material replacement technology in geologic chemistry grouting

Номер: CN103132527A
Автор: Yao Xin, Shi Jun, Deng Qiang, Li Juntao, Liu Chao, Wang Yuanxun, Zeng Sikai, Xu Yong, Wei Shangwei, Huang Jianzhong
Принадлежит:

The invention discloses grouting material replacement technology in geologic chemistry grouting. The grouting comprises the following steps of hole drilling, hole flushing and water pressing, non-grouting segment separation, water discharging, chemical grouting construction, grouting closuring, cement replacing and curdling and hole sealing. The cement replacing includes that after chemical grouting closuring is finished, cement grout is injected from a return pipe to a hole by a grouting machine and tools, a valve of a grout inlet is opened, chemical grout liquid and cement are replaced in a vent in the top of the grout inlet pipe and curdle for 8 hours, and then the hole is swept. The replaced chemical grout liquid is collected and conducted with centralized processing. According to the grouting material replacement technology in the geologic chemistry grouting, chemical grouting construction characteristics are combined, the existing construction equipment is fully used, the operation ...

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Номер записи: 96
24-10-2017 дата публикации

Integrated device with P-I-N diodes and vertical field effect transistors

Номер: US0009799647B1
Автор: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang, CHENG KANGGUO, LI JUNTAO, WANG GENG, ZHANG QINTAO, Cheng Kangguo, Li Juntao, Wang Geng, Zhang Qintao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

An integrated device is provided. The integrated device includes a substrate having a doped upper surface section and an insulator to define first and second substrate regions on opposite sides thereof. Vertical transistors are operably arranged on the doped upper surface section at the first substrate region. P-I-N diodes are operably arranged on the doped upper surface section at the second substrate region.

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Номер записи: 97
10-08-2017 дата публикации

STACKED NANOWIRE DEVICES

Номер: US20170229538A1
Автор: Kangguo Cheng, Ramachandra Divakaruni, Juntao Li, CHENG KANGGUO, DIVAKARUNI RAMACHANDRA, LI JUNTAO, Cheng Kangguo, Divakaruni Ramachandra, Li Juntao
Принадлежит:

A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.

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Номер записи: 98
23-05-2017 дата публикации

Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation

Номер: US0009659960B1
Автор: Kangguo Cheng, Juntao Li, Zuoguang Liu, Xin Miao, CHENG KANGGUO, LI JUNTAO, LIU ZUOGUANG, MIAO XIN, Cheng Kangguo, Li Juntao, Liu Zuoguang, Miao Xin
Принадлежит: International Business Machines Corporation, IBM

A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.

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Номер записи: 99
22-08-2017 дата публикации

Metal reflow for middle of line contacts

Номер: US0009741577B2
Автор: Juntao Li, Junli Wang, Chih-Chao Yang, LI JUNTAO, WANG JUNLI, YANG CHIH-CHAO, Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM, International Business Machines Corporation

A method of forming a contact in a semiconductor device includes forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD) material arranged between the first gate and the second gate to form a trench that extends from a surface of the first gate and a surface of the second gate to the substrate; depositing a liner along a sidewall of the trench and an endwall of the trench in contact with the substrate; depositing by a physical vapor deposition method (PVD) a layer of metal on a surface of the first gate and a surface of the second gate; and heating to reflow metal from the layer of metal on the surface of the first gate and the second gate into the trench and form the contact.

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Номер записи: 100
06-03-2014 дата публикации

SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY

Номер: US20140061793A1
Автор: Cheng Kangguo, Ervin Joseph, Li Juntao, Pei Chengwen, Todi Ravi M., Wang Geng
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device. 1. A method of forming a semiconductor structure comprising:forming a dielectric mandrel structure having vertical sidewalls on a single crystalline semiconductor material layer;forming an amorphous semiconductor material layer on said vertical sidewalls and a top surface of said single crystalline semiconductor material layer;converting said amorphous semiconductor material layer into an epitaxial semiconductor material layer employing a crystalline structure of said single crystalline semiconductor material layer as a template; andforming an epitaxial semiconductor fin from said epitaxial semiconductor material layer by removing horizontal portions of said epitaxial semiconductor material layer.2. The method of claim 1 , further comprising removing said dielectric mandrel structure selective to said epitaxial semiconductor fin and said single crystalline semiconductor material layer.3. The method of claim 1 , wherein said conversion of said amorphous semiconductor material layer into said epitaxial semiconductor material layer is performed by solid phase epitaxy in ...

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Номер записи: 101
06-01-2022 дата публикации

Self-Aligned Source and Drain Contacts

Номер: US20220005934A1
Автор: Cheng Kangguo, Li Juntao, Park Chanro, Xie Ruilong
Принадлежит:

Self-aligned semiconductor FET device source and drain contacts and techniques for formation thereof are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate; source and drains on opposite sides of the at least one gate; gate spacers offsetting the at least one gate from the source and drains; lower source and drain contacts disposed on the source and drains; upper source and drain contacts disposed on the lower source and drain contacts; and a silicide present between the lower source and drain contacts and the upper source and drain contacts. 1. A semiconductor field-effect transistor (FET) device , comprising:at least one gate disposed on a substrate;source and drains on opposite sides of the at least one gate;gate spacers offsetting the at least one gate from the source and drains;lower source and drain contacts disposed on the source and drains;upper source and drain contacts disposed on the lower source and drain contacts; anda silicide present between the lower source and drain contacts and the upper source and drain contacts, wherein the upper source and drain contacts overhang the silicide such that a top of the silicide directly contacts only a portion of a bottom-most surface of the upper source and drain contacts.2. The semiconductor FET device of claim 1 , wherein a top surface of the lower source and drain contacts is recessed a depth d below top surfaces of the gates and the gate spacers.3. The semiconductor FET device of claim 2 , wherein d is from about 5 nm to about 10 nm and ranges therebetween.4. The semiconductor FET device of claim 2 , wherein the silicide is present in a space between the gate spacers directly over the lower source and drain contacts.5. The semiconductor FET device of claim 2 , further comprising:a metal layer disposed on the lower source and drain contacts.6. The semiconductor FET device of claim 5 , wherein the metal layer comprises nickel (Ni) claim 5 , and wherein the ...

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Номер записи: 102
13-01-2022 дата публикации

CROSS-BAR FIN FORMATION

Номер: US20220013366A1
Автор: Cheng Kangguo, Li Juntao, Park Chanro, Xie Ruilong
Принадлежит:

A first mask layer is formed on top of a semiconductor substrate. A mandrel material is formed perpendicular to the first mask layer. A second mask layer is formed on one or more exposed surfaces of the mandrel material. The mandrel material is removed. A pattern of the first mask layer and the second mask layer is transferred into the semiconductor substrate. 1. A method of forming a semiconductor structure , the method comprising:forming a first mask layer on top of a semiconductor substrate;forming a mandrel material perpendicular to the first mask layer;forming a second mask layer on one or more exposed surfaces of the mandrel material;removing the mandrel material; andtransferring a pattern of the first mask layer and the second mask layer into the semiconductor substrate.2. The method of claim 1 , further comprising:forming a cut masking layer over at least a portion of the mandrel material, at least a portion of the second mask layer, and at least a portion of the first mask layer;selectively removing the mandrel material and the second mask layer not covered by the cut masking layer; andremoving the cut masking layer.3. The method of claim 1 , wherein a width of the material layer is between 5 nanometers (nm) and 20 nm and wherein the material layer is selected from the group consisting of silicon nitride (SiN) claim 1 , silicon carbide (SiC) claim 1 , silicon oxynitride (SiON) claim 1 , carbon-doped silicon oxide (SiOC) claim 1 , silicon-carbon-nitride (SiCN) claim 1 , boron nitride (BN) claim 1 , silicon boron nitride (SiBN) claim 1 , siliconboron carbonitride (SiBCN) claim 1 , silicon oxycarbonitride (SiOCN) claim 1 , silicon oxide claim 1 , titanium nitride (TiN).4. The method of claim 1 , wherein the mandrel material is between 10 nm and 50 nm and wherein the mandrel material is selected from the group consisting of amorphous silicon (aSi) claim 1 , polycrystalline silicon claim 1 , amorphous silicon germanium (aSiGe) claim 1 , and polycrystalline ...

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Номер записи: 103
04-01-2018 дата публикации

STRAINED AND UNSTRAINED SEMICONDUCTOR DEVICE FEATURES FORMED ON THE SAME SUBSTRATE

Номер: US20180005892A1
Автор: Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит:

Embodiments of the invention are directed to a configuration of semiconductor devices having a substrate and a first feature formed on the substrate, wherein the first feature includes a first preserve region having compressive strain that extends throughout the first preserve region, and wherein the first feature further includes a cut region comprising a dielectric. 1. A configuration of semiconductor devices comprising:a substrate; anda first feature formed on the substrate;wherein the first feature comprises a first preserve region having compressive strain that extends throughout the first preserve region;wherein the first feature further comprises a first cut region comprising a dielectric.2. The semiconductor devices of further comprising a second feature formed on the substrate.3. The semiconductor devices of claim 2 , wherein the second feature comprises a second preserve region having substantially no compressive strain.4. The semiconductor devices of claim 1 , wherein the first feature comprises a first fin.5. The semiconductor devices of claim 4 , wherein the first preserve region comprises a channel region of the first fin.6. The semiconductor devices of claim 5 , wherein the second feature comprises a second fin.7. The semiconductor devices of claim 6 , wherein the second preserve region comprises a channel region of the second fin.8. The semiconductor devices of further comprising a first gate formed over the channel region of the first fin.9. The semiconductor devices of further comprising a second gate formed over the channel region of the second fin.10. The semiconductor devices of claim 3 , wherein the substrate comprises silicon.11. The semiconductor devices of claim 10 , wherein the first preserve region comprises silicon germanium.12. The semiconductor devices of claim 11 , wherein the dielectric of the first cut region comprises an oxide.13. The semiconductor devices of claim 12 , wherein the second preserve region comprises silicon.14. A ...

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Номер записи: 104
04-01-2018 дата публикации

INTEGRATED CAPACITORS WITH NANOSHEET TRANSISTORS

Номер: US20180006113A1
Автор: Cheng Kangguo, Demarest James J., Gaudiello John G., Li Juntao
Принадлежит:

A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same substrate. The nanosheets in the capacitor have a width and are coupled to one another by sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width, and wherein the nanosheets and the sacrificial layers are conductively coupled to the substrate. The nanosheets in the FET devices are spaced apart and free of sacrificial layers. The nanosheets in the FET device have a width less than half the width of the nanosheets in the capacitor region. 1. A semiconductor device comprising:a capacitor region and a FET region defined by a plurality of stackedly and alternatingly arranged nanosheets and sacrificial layers disposed on a substrate,wherein the nanosheets in the capacitor region have a width and are coupled to one another by the sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width;wherein the nanosheets in the FET region are spaced apart and free of sacrificial layers, the nanosheets in the FET region having a width less than half the width of the nanosheets in the capacitor region.2. The semiconductor device of claim 1 , wherein each one of the nanosheets has a thickness equal to each one of the sacrificial layers.3. The semiconductor device of claim 1 , wherein the nanosheets comprise silicon and the sacrificial layers comprise silicon-germanium.4. The semiconductor device of claim 1 , wherein the substrate underlying the capacitor region is conductive claim 1 , and the stackedly and alternatingly arranged nanosheets and sacrificial layers of the capacitor region are conductively coupled to the substrate.5. The semiconductor device of claim 1 , wherein the substrate underlying the FET region is free of dopants that make the alternatingly arranged nanosheets and sacrificial layers of the capacitor region conductive.6. The ...

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Номер записи: 105
04-01-2018 дата публикации

STRAINED AND UNSTRAINED SEMICONDUCTOR DEVICE FEATURES FORMED ON THE SAME SUBSTRATE

Номер: US20180006119A1
Автор: Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит:

Embodiments are directed to a method of forming a feature of a semiconductor device. The method includes forming the feature from a semiconductor material having compressive strain that extends throughout a cut region of the feature and throughout a preserve region of the feature. The method further includes converting the cut region of the feature to a dielectric. 1. A method of forming a feature of a semiconductor device , the method comprising:forming the feature from a semiconductor material;wherein the feature comprises a preserve region and a cut region;wherein the feature comprises compressive strain imparted to the feature by the semiconductor material;wherein the compressive strain extends throughout the cut region of the feature and throughout the preserve region of the feature; andconverting the cut region of the feature to a dielectric.2. The method of claim 1 , wherein the feature comprises a fin.3. The method of claim 2 , wherein the preserve region of the fin comprises a channel region of the semiconductor device.4. The method of further comprising forming a gate over the channel region.5. The method of claim 1 , wherein converting the cut region of the feature to a dielectric comprises oxidizing the cut region.6. The method of claim 1 , wherein:the feature is formed on a silicon substrate; andthe semiconductor material comprises silicon germanium.7. The method of claim 1 , wherein:the compressive strain extending throughout the cut region and the preserve region comprises a predetermined percentage of compressive strain; andconverting the cut region of the feature to a dielectric does not reduce the predetermined percentage.8. The method of claim 7 , wherein converting the cut region of the feature to a dielectric increases the predetermined percentage.9. A method of forming features of semiconductor devices claim 7 , the method comprising:forming a first feature on a substrate, wherein the first feature comprises a first semiconductor material ...

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Номер записи: 106
03-01-2019 дата публикации

SILICON GERMANIUM FIN IMMUNE TO EPITAXY DEFECT

Номер: US20190006510A1
Автор: Cheng Kangguo, Li Juntao, Miao Xin
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method for forming a semiconductor structure includes forming at least one fin on a semiconductor substrate. The least one fin includes a semiconducting material. A gate is formed over and in contact with the at least one fin. A germanium comprising layer is formed over and in contact with the at least one fin. Germanium from the germanium comprising layer is diffused into the semiconducting material of the at least one fin. 1. A method of forming a semiconductor structure , the method comprising:forming at least one fin on a semiconductor substrate, the least one fin comprising a semiconductor material;forming a gate over and in contact with the at least one fin;depositing a germanium comprising layer over and in contact with an exposed top surface of the at least one fin; anddiffusing germanium from the germanium comprising layer into the semiconducting material of the at least one fin.2. The method of claim 1 , wherein the gate is a dummy gate claim 1 , removing the dummy gate; and', 'after removing the dummy gate, forming a gate stack over and in contact with the at least one fin., 'wherein after the diffusing the method further comprises'}3. The method of claim 2 , further comprising:forming a spacer layer in contact with the dummy gate, wherein the gate stack is formed in contact with the spacer layer after the dummy gate has been removed.4. The method of claim 2 , wherein forming the gate stack comprises:forming a dielectric layer over and in contact with the at least one fin.5. The method of claim 4 , wherein forming the gate stack further comprises:after forming the gate dielectric layer, forming a gate conductor layer over and in contact with the gate dielectric layer.6. The method of claim 2 , further comprising:forming a spacer layer on sidewalls of the gate stack.7. The method of claim 2 , further comprising:after forming the gate stack, forming a source region and a drain region in contact with the at least one fin.8. The method of claim 7 , wherein ...

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Номер записи: 107
02-01-2020 дата публикации

Vertical transistors with various gate lengths

Номер: US20200006553A1
Автор: ChoongHyun Lee, Juntao Li, Kangguo Cheng, Shogo Mochizuki
Принадлежит: International Business Machines Corp

A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, at least two spacer layers are formed around a first fin of the plurality of fins, and a single spacer layer is formed around a second fin of the plurality of fins. The at least two spacer layers include a first spacer layer including a first material and a second spacer layer including a second material different from the first material. The single spacer layer includes the second material. The method also includes selectively removing part of the first spacer layer to expose part of the first fin, and epitaxially growing a source/drain region around the exposed part of the first fin.

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Номер записи: 108
11-01-2018 дата публикации

ANTI-FUSE WITH REDUCED PROGRAMMING VOLTAGE

Номер: US20180012897A1
Автор: Cheng Kangguo, Li Juntao, Pei Chengwen, Wang Geng
Принадлежит:

A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field. 1. A semiconductor device having transistors and anti-fuses integrated thereon , comprising:an epitaxially grown semiconductor layer formed on a substrate;a transistor region including a semiconductor material formed over the semiconductor layer to form a device channel for a transistor;an anti-fuse region including a defective semiconductor layer formed on an oxide in the anti-fuse region; andgate structures formed between source and drain regions in the transistor region and the anti-fuse region, wherein the defective semiconductor layer is programmable by an applied field on the gate structures in the anti-fuse region.2. The device as recited in claim 1 , further comprising contacts formed in the transistor region and the anti-fuse region.3. The device as recited in claim 1 , wherein the defective semiconductor layer includes Si and forms a conductive path by activating a gate of the gate structure in the anti-fuse region above a threshold voltage.4. The device as recited in claim 1 , wherein the semiconductor layer includes SiGe and the semiconductor material includes strained Si in the transistor region.5. The device as recited in claim 1 , further comprising:a shallow trench isolation region formed between the transistor region and the anti-fuse region.6. The device as recited in claim 1 , wherein the source and drain regions are formed on ...

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Номер записи: 109
14-01-2021 дата публикации

FLOATING GATE PREVENTION AND CAPACITANCE REDUCTION IN SEMICONDUCTOR DEVICES

Номер: US20210013322A1
Автор: Cheng Kangguo, Li Juntao, Park Chanro, Xie Ruilong
Принадлежит:

A method for fabricating a semiconductor structure includes forming a plurality of vertical fins on a semiconductor substrate. The method further includes depositing a first dielectric layer in a shallow trench isolation region on the semiconductor substrate. The method further includes forming a plurality of dummy gate structures over each of the vertical fins. The method further includes depositing a hardmask on the dummy gate. The method further includes depositing a spacer layer on the exterior surfaces of the first dielectric layer, the dummy gate structures, the hardmask and the fins. The method further includes depositing a second dielectric layer on a portion of the spacer layer. The method further includes recessing spacer layer to expose a portion of the hardmask and the plurality of fins. The method further includes forming a source/drain region on the exposed portion of the plurality of fins. 1. A method for fabricating a semiconductor structure comprising:forming a plurality of vertical fins on a semiconductor substrate;depositing a first dielectric layer in a shallow trench isolation region on the semiconductor substrate;forming a plurality of dummy gate structures over each of the vertical fins;depositing a hardmask on the dummy gate;depositing a spacer layer on the exterior surfaces of the first dielectric layer, the dummy gate structures, the hardmask and the fins;depositing a second dielectric layer on a portion of the spacer layer;recessing the spacer layer to expose a portion of the hardmask and the plurality of fins; andforming a source/drain region on the exposed portion of the plurality of fins.2. The method of claim 1 , wherein the semiconductor substrate and each of the vertical fins comprise silicon.3. The method of claim 1 , wherein the second dielectric layer is recessed to below a top surface of the spacer layer.4. The method of claim 1 , further comprising:depositing a contact etching stop layer on the source drain region, a top surface ...

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Номер записи: 110
09-01-2020 дата публикации

SELF-ALIGNED SILICIDE/GERMANIDE FORMATION TO REDUCE EXTERNAL RESISTANCE IN A VERTICAL FIELD-EFFECT TRANSISTOR

Номер: US20200013681A1
Автор: Cheng Kangguo, Lee Choonghyun, Li Juntao, Xu Peng
Принадлежит:

A method for manufacturing a vertical transistor device includes respectively forming a first and second plurality of fins in first and second device regions on a substrate. A plurality of bottom source/drain regions are formed adjacent lower portions of each of the fins, and a sacrificial layer is formed in the first device region on a first bottom source/drain region of the plurality of bottom source/drain regions. In the method, gate structures are formed on the bottom source/drain regions and sacrificial layer, and portions of the gate structures are removed to expose the sacrificial layer in the first device region and a second bottom source/drain region of the plurality of bottom source/drain regions in the second device region. The method further includes depositing a germanium oxide layer on the exposed sacrificial layer and second bottom source/drain region, and converting the germanium oxide layer to a plurality of silicide/germanide layers. 1. A vertical transistor device , comprising:a first plurality of fins in a first device region on a substrate;a second plurality of fins in a second device region on the substrate;a plurality of bottom source/drain regions on the substrate adjacent lower portions of each of the first and second plurality of fins in the first and second device regions;a plurality of gate structures on the plurality of bottom source/drain regions;at least one of a plurality of silicide layers and a plurality of germanide layers on the plurality of bottom source/drain regions adjacent the plurality of gate structures.2. The vertical transistor device according to claim 1 , wherein a plurality of sacrificial layers are positioned on lateral sides each of the at least one of the plurality of silicide layers and the plurality of germanide layers in the first device region.3. The vertical transistor device according to claim 2 , wherein the plurality of sacrificial layers comprise silicon germanium.4. The vertical transistor device according ...

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Номер записи: 111
09-01-2020 дата публикации

VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICE WITH REDUCED GATE VARIATION AND REDUCED CAPACITANCE

Номер: US20200013879A1
Автор: Cheng Kangguo, Lee Choonghyun, Li Juntao, Mochizuki Shogo
Принадлежит:

A method of forming a fin field effect transistor device is provided. The method includes forming a vertical fin on a substrate, and depositing a sidewall liner on exposed surfaces of the vertical fin. The method further includes removing a portion of the substrate below the sidewall liner to form a support pillar below the vertical fin. The method further includes laterally etching the support pillar to form a thinned support pillar, and forming a bottom source/drain layer on the substrate and the thinned support pillar, wherein the bottom source/drain layer has a non-uniform thickness. 1. A method of forming a fin field effect transistor device , comprising:forming a vertical fin on a substrate;depositing a sidewall liner on exposed surfaces of the vertical fin;removing a portion of the substrate below the sidewall liner to form a support pillar below the vertical fin;laterally etching the support pillar to form a thinned support pillar; andforming a bottom source/drain layer on the substrate and the thinned support pillar, wherein the bottom source/drain layer has a non-uniform thickness.2. The method of claim 1 , further comprising depositing a capping layer on the bottom source/drain layer.3. The method of claim 2 , further comprising converting the capping layer to a bottom spacer layer.4. The method of claim 3 , wherein the capping layer is converted to the bottom spacer layer through exposure to an oxidizing agent at a temperature in a range of about 400° C. to about 800° C.5. The method of claim 3 , wherein the capping layer is silicon-germanium.6. The method of claim 5 , wherein the capping layer has a germanium concentration in a range of about 40 atomic percent (at. %) to about 60 at. %.7. The method of claim 3 , further comprising removing the sidewall liner claim 3 , and forming a gate dielectric layer on the vertical fin claim 3 , bottom spacer layer claim 3 , and bottom source/drain layer.8. The method of claim 7 , wherein the gate dielectric layer ...

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Номер записи: 112
18-01-2018 дата публикации

DNA SEQUENCING WITH STACKED NANOPORES

Номер: US20180016629A1
Автор: Bi Zhenxing, Cheng Kangguo, Li Juntao, Miao Xin
Принадлежит:

A sensing device includes a stack of dielectric layers having conductive materials disposed between the dielectric layers. A nanopore is disposed through the stacks of dielectric layers and separates the conductive materials to provide electrodes on opposite sides of the nanopore. Contacts connect to each of the electrodes. 1. A sensing device , comprising:a stack of dielectric layers having conductive materials disposed between the dielectric layers;a nanopore disposed through the stack of dielectric layers and separating the conductive materials to provide electrodes on opposite sides of the nanopore; andcontacts connecting to each of the electrodes.2. The sensing device as recited in claim 1 , wherein the conductive materials includes conductive lines.3. The sensing device as recited in claim 2 , wherein the conductive lines form a staircase structure with a longest conductive line at a first level and shorter conductive lines at each successive level.4. The sensing device as recited in claim 2 , wherein the conductive lines include nanowires.5. The sensing device as recited in claim 1 , wherein the conductive lines have tips extending into the nanopore.6. The sensing device as recited in claim 1 , wherein the stack of dielectric layers is formed on a substrate.7. The sensing device as recited in claim 6 , wherein the substrate includes integrated circuitry.8. The sensing device as recited in claim 7 , wherein the integrated circuitry includes a sensor circuit to measure tunneling current differences when a molecule is present in the nanopore.9. The sensing device as recited in claim 6 , wherein the nanopore extends through the substrate.10. The sensing device as recited in claim 1 , wherein the electrodes on opposite sides of the nanopore form two or more electrode pairs claim 1 , wherein each electrode pair forms a sensor for measuring tunneling current changes when a molecule is present between the electrodes.11. A sensing device claim 1 , comprising:a stack ...

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Номер записи: 113
03-02-2022 дата публикации

Forming single and double diffusion breaks for fin field-effect transistor structures

Номер: US20220037194A1
Автор: Junli Wang, Juntao Li, Kangguo Cheng, Ruilong Xie
Принадлежит: International Business Machines Corp

A method of forming a semiconductor structure includes forming a plurality of fins over a substrate, at least a portion of one or more of the fins providing one or more channels for one or more fin field-effect transistors. The method also includes forming a plurality of active gate structures over the fins, forming at least one single diffusion break trench between a first one of the active gate structures and a second one of the active gate structures, and forming at least one double diffusion break trench between a third one of the active gate structures and a fourth one of the active gate structures. The double diffusion break trench has a stepped height profile in the substrate, the stepped height profile comprising a first depth with a first width and a second depth less than the first depth with a second width greater than the first width.

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Номер записи: 114
03-02-2022 дата публикации

Scalable Device for FINFET Technology

Номер: US20220037212A1
Автор: Chanro Park, Juntao Li, Kangguo Cheng, Ruilong Xie
Принадлежит: International Business Machines Corp

Scalable device designs for FINFET technology are provided. In one aspect, a method of forming a FINFET device includes: patterning fins in a substrate which include a first fin(s) corresponding to a first FINFET device and a second fin(s) corresponding to a second FINFET device; depositing a conformal gate dielectric over the fins; depositing a conformal sacrificial layer over the gate dielectric; depositing a sacrificial gate material over the sacrificial layer; replacing the sacrificial layer with a first workfunction-setting metal(s) over the first fin(s) and a second workfunction-setting metal(s) over the second fin(s); removing the sacrificial gate material; forming dielectric gates over the first workfunction-setting metal(s), the second workfunction-setting metal(s) and the gate dielectric forming gate stacks; and forming source and drains in the fins between the gate stacks, wherein the source and drains are separated from the gate stacks by inner spacers. A FINFET device is also provided.

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Номер записи: 115
17-01-2019 дата публикации

INDUCTOR WITH FERROMAGNETIC CORES

Номер: US20190019617A1
Автор: Cheng Kangguo, Li Juntao, Wang Geng, Zhang Qintao
Принадлежит:

An inductor device includes a substrate, and a plurality of first trenches including a first metal on the substrate to form first metal layers. The first metal layers are arranged substantially parallel to the substrate. A plurality of second trenches including a second metal is over the first metal layers and includes first portions and second portions. The first portions are substantially parallel to and interdigitate the first metal layers. The second portions are substantially perpendicular to the first portions, extend from ends of the first portions, and are oriented in opposite directions such that the second portions extend over ends of adjacent first metal layers. A plurality of vias connects the first metal layers to the second metal layers. A plurality of magnetic trenches is over the first metal layers, under the second metal layers, and substantially parallel to the second portions of the plurality of second trenches. 1. An inductor device , comprising:a substrate;a plurality of first trenches comprising a first metal arranged on the substrate, the plurality of first trenches forming first metal layers, the first metal layers being arranged substantially parallel to the substrate;a plurality of second trenches comprising a second metal arranged over the first metal layers and forming second metal layers, the plurality of second trenches comprising two portions, first portions and second portions, the first portions arranged substantially parallel to and interdigitating the first metal layers, and the second portions arranged substantially perpendicular to the first portions, extending from both ends of the first portions, and oriented in opposite directions such that the second portions extend over ends of adjacent first metal layers;a plurality of vias connecting the first metal layers to the second metal layers; anda plurality of magnetic trenches arranged on the substrate, the plurality of magnetic trenches being arranged over the first metal layers, ...

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Номер записи: 116
17-01-2019 дата публикации

ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES

Номер: US20190019752A1
Автор: Basker Veeraraghavan S., Cheng Kangguo, Khakifirooz Ali, Li Juntao
Принадлежит:

Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material. 1. A semiconductor structure , comprising:metal gates having a capping material on a top surface thereof;contact structures in recesses in a dielectric material between the metal gates;an opening in the dielectric material, wherein the opening is between the contact structures; andan insulator material and metal material within the opening.2. The semiconductor structure of wherein the metal material contacts surfaces of the dielectric material in the opening.3. The semiconductor structure of claim 2 , wherein the insulator material is in a trench in the metal material.4. The semiconductor structure of claim 1 , wherein the contact structures each comprise a liner formed in one of the recesses in the dielectric material.5. The semiconductor structure of claim 4 , wherein the metal material contacts the liner of each of the contact structures.6. The semiconductor structure of claim 1 , wherein top surfaces of the dielectric layer claim 1 , the capping material claim 1 , the contact structures claim 1 , the insulator material claim 1 , and the metal material are co-planar.7. The semiconductor structure of claim 1 , further comprising:another dielectric layer over the dielectric layer, the capping material, the contact structures, the insulator material, and the metal material; andadditional contacts in the other dielectric layer.8. The semiconductor structure of claim 7 , wherein the additional contacts contact the contact structures claim 7 , ...

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Номер записи: 117
17-01-2019 дата публикации

ANTI-FUSE WITH REDUCED PROGRAMMING VOLTAGE

Номер: US20190019803A1
Автор: Cheng Kangguo, Li Juntao, Pei Chengwen, Wang Geng
Принадлежит:

A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field. 1. A semiconductor device having transistors and anti-fuses integrated thereon , comprising:a transistor region having a device channel for a transistor;an anti-fuse region including a defective semiconductor layer formed on an oxide over a semiconductor layer over which the transistor is formed; andgate structures formed in the transistor region and in the anti-fuse region, wherein the defective semiconductor layer is programmable by an applied field on the gate structures in the anti-fuse region.2. The device as recited in claim 1 , further comprising contacts formed in the transistor region and the anti-fuse region.3. The device as recited in claim 1 , wherein the defective semiconductor layer includes Si and forms a conductive path by activating a gate of the gate structure in the anti-fuse region above a threshold voltage.4. The device as recited in claim 1 , wherein the semiconductor layer includes SiGe and the semiconductor material includes strained Si in the transistor region.5. The device as recited in claim 1 , further comprising:a shallow trench isolation region formed between the transistor region and the anti-fuse region.6. The device as recited in claim 1 , wherein the source and drain regions are formed on the semiconductor material in the transistor region and the defective semiconductor layer in the anti-fuse region.7. The device ...

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Номер записи: 118
17-01-2019 дата публикации

EXTREMELY THIN SILICON-ON-INSULATOR SILICON GERMANIUM DEVICE WITHOUT EDGE STRAIN RELAXATION

Номер: US20190019811A1
Автор: Cheng Kangguo, Li Juntao, Liu Zuoguang, Miao Xin
Принадлежит:

A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium. 1. A method of forming a semiconductor structure , the method comprising:oxidizing at least a first exposed portion and a second exposed portion of a strained silicon germanium layer formed on top of a substrate, the oxidizing forming at least one patterned strained silicon germanium area within the strained silicon germanium layer comprising a first oxide end region and a second oxide end region corresponding to the first and second exposed portions, respectively, of the strained silicon germanium layer.2. The method of claim 1 , wherein the oxidizing further forms a portion of the first and second oxide regions within the at least first portion of the strained silicon germanium layer laterally beyond a portion of the first and second oxide regions extending above a top surface of the strained silicon germanium layer.3. The method of claim 1 , wherein the oxidizing further forms a portion of the first and second oxide regions above a top surface of the strained silicon germanium layer.4. The method of claim 1 , further comprising:forming a gate stack on and in contact with the at least first portion of the strained silicon germanium layer.5. The method of claim 4 , wherein forming the gate stack comprises:forming a gate dielectric in contact with the first portion of the strained silicon germanium layer; andforming a gate electrode in contact with the gate dielectric.6. The method of claim 4 , further comprising:forming a source ...

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Номер записи: 119
16-01-2020 дата публикации

Cyclic Selective Deposition for Tight Pitch Patterning

Номер: US20200020540A1
Автор: Bi Zhenxing, Cheng Kangguo, Kong Dexin, Li Juntao
Принадлежит:

Techniques for tight pitch patterning of fins using a cyclic selective deposition process are provided. In one aspect, a method of patterning fins in a wafer includes: forming at least one mandrel on the wafer; forming alternating layers of a first dielectric and a second dielectric alongside the at least one mandrel; removing the at least one mandrel; removing either the first dielectric or the second dielectric; and patterning the fins in the wafer using whichever of the first dielectric or the second dielectric that remains as fin hardmasks. A finFET device and method for forming a finFET device are also provided. 1. A method of patterning fins in a wafer , the method comprising the steps of:forming at least one mandrel on the wafer;forming alternating layers of a first dielectric and a second dielectric alongside the at least one mandrel;removing the at least one mandrel;removing either the first dielectric or the second dielectric; andpatterning the fins in the wafer using whichever of the first dielectric or the second dielectric that remains as fin hardmasks.2. The method of claim 1 , further comprising the steps of:depositing the second dielectric selectively onto the first dielectric;depositing the first dielectric selectively onto the second dielectric; andrepeating the depositing steps x times until a desired number of the fin hardmasks are formed.3. The method of claim 2 , further comprising the steps of:forming spacers alongside the at least one mandrel;depositing, in a first iteration, the first dielectric onto the spacers.4. The method of claim 2 , further comprising the step of:removing excess material from the first dielectric and the second dielectric deposited on top of the at least one mandrel.5. The method of claim 2 , wherein multiple mandrels are formed on the wafer claim 2 , the method further comprising the steps of:forming the alternating layers of the first dielectric and the second dielectric alongside each of the mandrels with trenches ...

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Номер записи: 120
16-01-2020 дата публикации

Forming Bottom Source and Drain Extension on Vertical Transport FET (VTFET)

Номер: US20200020804A1
Автор: Cheng Kangguo, Lee Choonghyun, Li Juntao, Mochizuki Shogo
Принадлежит:

Techniques for forming bottom source and drain extensions in VTFET devices are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming a liner at a base of the fins having a higher diffusivity for dopants than the fins; forming sidewall spacers alongside an upper portion of the fins; forming bottom source/drains on the liner at the base of the fins including the dopants; annealing the wafer to diffuse the dopants from the bottom source/drains, through the liner, into the base of the fins to form bottom extensions; removing the sidewall spacers; forming bottom spacers on the bottom source/drains; forming gate stacks alongside the fins above the bottom spacers; forming top spacers above the gate stacks; and forming top source/drains above the top spacers at tops of the fins. A VTFET device is also provided. 1. A method of forming a vertical transport field effect transistor (VTFET) device , comprising the steps of:patterning fins in a wafer;forming a liner at a base of the fins, wherein the liner has a higher diffusivity for dopants than the fins;forming sidewall spacers alongside an upper portion of the fins, wherein the sidewall spacers partially overlap the liner;forming bottom source and drains on the liner at the base of the fins below the sidewall spacers, wherein the bottom source and drains comprise the dopants;annealing the wafer to diffuse the dopants from the bottom source and drains, through the liner, into the base of the fins to form bottom extensions;removing the sidewall spacers;forming bottom spacers on the bottom source and drains;forming gate stacks alongside the fins above the bottom spacers;forming top spacers above the gate stacks; andforming top source and drains above the top spacers at tops of the fins.2. The method of claim 1 , wherein the fins comprise silicon (Si).3. The method of claim 2 , wherein the liner comprises silicon germanium (SiGe).4. The method of claim 3 , wherein the SiGe has a ...

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Номер записи: 121
21-01-2021 дата публикации

Phase change memory cell with second conductive layer

Номер: US20210020833A1
Автор: Junli Wang, Juntao Li, Kangguo Cheng, Ruilong Xie
Принадлежит: International Business Machines Corp

A method may include forming a via opening in a dielectric layer, depositing a first conductive layer along a bottom and a sidewall of the via opening, depositing a second conductive layer on top of the first conductive layer. The method may further include recessing the first conductive layer to form a trench and exposing a sidewall of the second conductive layer, depositing a non-conductive material in the trench, and depositing a phase change material layer on top of the dielectric layer. The top surface of the second conductive layer may be in direct contact with a bottom surface of the phase change material layer.

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Номер записи: 122
10-02-2022 дата публикации

VERTICAL STACKED NANOSHEET CMOS TRANSISTORS WITH DIFFERENT WORK FUNCTION METALS

Номер: US20220044973A1
Автор: Cheng Kangguo, Li Juntao, Park Chanro, Xie Ruilong
Принадлежит:

A method for forming a semiconductor device includes forming a structure having at least a first nanosheet stack for a first device, a second nanosheet stack for a second device and disposed over the first nanosheet stack, a disposable gate structure, and a gate spacer. The disposable gate structure and sacrificial layers of the first and second nanosheet stacks are removed thereby forming a plurality of cavities. A conformal gate dielectric layer is formed in the plurality cavities and surrounding at least portions of the first and second nanosheet stacks. A first conformal work function layer is formed in contact with the gate dielectric layer. Portions of the first conformal work function layer are removed without using a mask from at least the second nanosheet stack. A second conformal work function layer is formed on exposed portions of the gate dielectric layer. 1. A semiconductor device comprising at least:a first nanosheet stack for a first device;a second nanosheet stack for a second device, wherein the second nanosheet stack is disposed on top of the first nanosheet stack; and a gate dielectric layer surrounding a first set of nanosheet layers of the first nanosheet stack and a second set of nanosheet layers of the second nanosheet stack;', 'a first work function layer in contact with at least a first portion of the gate dielectric layer surrounding the first set of nanosheet layers and pinched off between each nanosheet layer of the first set of nanosheet layers;', 'a second work function layer in contact with at least second portion of the gate dielectric layer surrounding the second set of nanosheet layers, wherein a gap exists between portions of the second work function layer between each nanosheet layer of the second set of nanosheet layers; and', 'a gate conductor layer formed in contact with the second work function layer, wherein the gate conductor layer fills the gap between the portions of the second work function layer., 'a gate structure ...

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Номер записи: 123
10-02-2022 дата публикации

NANOSHEET TRANSISTOR WITH ASYMMETRIC GATE STACK

Номер: US20220045193A1
Автор: Cheng Kangguo, Guo Dechao, Kang Tsung-Sheng, Li Juntao, LI Tao, Radens Carl, Xie Ruilong
Принадлежит:

Embodiments of the present invention are directed to methods and resulting structures for nanosheet devices having asymmetric gate stacks. In a non-limiting embodiment of the invention, a nanosheet stack is formed over a substrate. The nanosheet stack includes alternating semiconductor layers and sacrificial layers. A sacrificial liner is formed over the nanosheet stack and a dielectric gate structure is formed over the nanosheet stack and the sacrificial liner. A first inner spacer is formed on a sidewall of the sacrificial layers. A gate is formed over channel regions of the nanosheet stack. The gate includes a conductive bridge that extends over the substrate in a direction orthogonal to the nanosheet stack. A second inner spacer is formed on a sidewall of the gate. The first inner spacer is formed prior to the gate stack, while the second inner spacer is formed after, and consequently, the gate stack is asymmetrical. 1. A semiconductor device comprising:a nanosheet stack over a substrate; anda gate over channel regions of the nanosheet stack, the gate comprising a conductive bridge to a second nanosheet stack, the conductive bridge extending over the substrate in a direction orthogonal to the nanosheet stack.2. The semiconductor device of further comprising a dielectric gate structure over the nanosheet stack and the gate.3. The semiconductor device of further comprising:a first inner spacer on a first end of the nanosheet stack; anda second inner spacer on a second end of the nanosheet stack;wherein a gate dielectric extends between the first inner spacer and the gate but not between the second inner spacer and the gate.4. The semiconductor device of further comprising a first source or drain region on a sidewall of the first inner spacer.5. The semiconductor device of further comprising a second source or drain region on a sidewall of the second inner spacer.6. The semiconductor device of further comprising a gate contact on a surface of the conductive bridge. ...

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Номер записи: 124
10-02-2022 дата публикации

UNIFORM INTERFACIAL LAYER ON VERTICAL FIN SIDEWALLS OF VERTICAL TRANSPORT FIELD-EFFECT TRANSISTORS

Номер: US20220045196A1
Автор: Cheng Kangguo, Lee Choonghyun, Li Juntao, Mochizuki Shogo
Принадлежит:

A method of forming a semiconductor structure includes patterning a hard mask layer over a top surface of a substrate. The method also includes forming a first portion of one or more vertical fins below the patterned hard mask layer. The method further includes forming a top spacer on sidewalls of the hard mask layer and the first portion of the one or more vertical fins. The method further includes forming a second portion of the one or more vertical fins in the substrate below the top spacer and trimming sidewalls of the second portion of the one or more vertical fins. The method further includes forming an interfacial layer on the trimmed sidewalls of the second portion of the one or more vertical fins. The one or more vertical fins provide one or more vertical transport channels for one or more vertical transport field-effect transistors. 1. A semiconductor structure , comprising:a substrate;one or more vertical fins disposed over a top surface of the substrate, the one or more vertical fins comprising a first portion proximate top surfaces thereof and a second portion below the first portion;a top spacer disposed on sidewalls of the first portion of the one or more vertical fins; andan interfacial layer disposed on sidewalls of the second portion of the one or more vertical fins;wherein the one or more vertical fins provide vertical transport channels for one or more vertical transport field-effect transistors.2. The semiconductor structure of claim 1 , wherein the first top spacers protect the interfacial layer such that the interfacial layer has a uniform thickness.3. The semiconductor structure of claim 1 , further comprising a gate stack disposed over the interfacial layer.4. The semiconductor structure of claim 3 , wherein the gate stack comprises:a gate dielectric layer having an inverted-L shape profile proximate the top surface of the one or more vertical fins; anda gate conductor layer having an inverted-L shape profile below the inverted-L shape ...

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Номер записи: 125
23-01-2020 дата публикации

FORMATION OF SEMICONDUCTOR DEVICES INCLUDING ELECTRICALLY PROGRAMMABLE FUSES

Номер: US20200027830A1
Автор: Li Juntao, Yang Chih-Chao
Принадлежит:

A method for fabricating a semiconductor device including an electrically programmable fuse includes patterning dielectric material formed on a first electrode including a first conductive material to create one or more openings, and forming second conductive material within the one or more openings. Forming the second conductive material includes forming one or more voids encapsulated by the second conductive material such that the one or more voids have boundaries defined in part by portions of the second conductive material disposed between the one or more voids and the dielectric material. The portions of the second conductive material correspond to fuse links. 1. A method for fabricating a semiconductor device including an electrically programmable fuse , comprising:patterning dielectric material formed on a first electrode including a first conductive material to create one or more openings; andforming second conductive material within the one or more openings, including forming one or more voids encapsulated by the second conductive material such that the one or more voids have boundaries defined in part by portions of the second conductive material disposed between the one or more voids and the dielectric material, the portions of the second conductive material corresponding to fuse links.2. The method of claim 1 , further comprising forming a diffusion barrier prior to forming the second conductive material.3. The method of claim 1 , wherein forming the second conductive material further includes non-conformally depositing the second conductive material claim 1 ,4. The method of claim 3 , wherein the second conductive material is non-conformally deposited by employing physical vapor deposition (PVD).5. The method of claim 1 , wherein forming the second conductive material further includes forming the second conductive material via electroplating.6. The method of claim 1 , further comprising forming one or more second electrodes by planarizing the second ...

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Номер записи: 126
23-01-2020 дата публикации

TECHNIQUES FOR FORMING VERTICAL TRANSPORT FET

Номер: US20200027991A1
Автор: Cheng Kangguo, Lee Choonghyun, Li Juntao
Принадлежит:

Techniques for reducing work function metal variability along the channel of VFET devices are provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a wafer; forming bottom source/drains at a base of the fins and bottom spacers on the bottom source/drains; forming gate stacks over the fins including a gate conductor having a combination of work function metals including an outer layer and at least one inner layer of the work function metals; isotropically etching the work function metals which recesses the gate stacks with an outwardly downward sloping profile; isotropically etching the at least one inner layer while covering the outer layer of the work function metals to eliminate the outwardly downward sloping profile of the gate stacks; forming top spacers above the gate stacks; and forming top source and drains at tops of the fins. A VTFET device is also provided. 1. A method of forming a vertical transport field-effect transistor (VTFET) device , the method comprising the steps of:patterning fins in a wafer;forming bottom source and drains at a base of the fins;forming bottom spacers on the bottom source and drains;forming gate stacks over the fins, the gate stacks comprising a gate conductor having a combination of work function metals comprising an outer layer and at least one inner layer of the work function metals;isotropically etching the outer layer and the at least one inner layer of the work function metals which, due to the combination of the work function metals, recesses the gate stacks with an outwardly downward sloping profile;isotropically etching the at least one inner layer of the work function metals while covering the outer layer of the work function metals to eliminate the outwardly downward sloping profile of the gate stacks;forming top spacers above the gate stacks; andforming top source and drains at tops of the fins over the top spacers.2. The method of claim 1 , further comprising the steps of: ...

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Номер записи: 127
17-02-2022 дата публикации

FIELD EFFECT TRANSISTOR DEVICES WITH SELF-ALIGNED SOURCE/DRAIN CONTACTS AND GATE CONTACTS POSITIONED OVER ACTIVE TRANSISTORS

Номер: US20220051942A1
Автор: Bi Zhenxing, Cheng Kangguo, Kong Dexin, Li Juntao
Принадлежит:

A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner. 1. A transistor device , comprising:at least three active gate structures with each active gate structure including a gate spacer and a gate electrode on a substrate;a source/drain contact between each adjacent pair of the at least three active gate structures;a gate contact on each of the gate electrodes, wherein at least a portion of the gate contact is on a portion of a source/drain cap; anda gate buffer between a portion of the gate spacer and the gate contact for each of the at least three active gate structures.2. The transistor device of claim 1 , further comprising a source/drain in the substrate beneath each of the source/drain contacts.3. The transistor device of claim 2 , wherein at least a portion of each of the source/drains is beneath the gate spacer and at least a portion of the gate electrode of at least one of the active gate structures.4. The transistor device of claim 3 , further comprising a source/drain lead on each of the source/drain contacts claim 3 , wherein a portion of the source/drain lead is directly on a portion of the gate spacer.5. The transistor device of claim 4 , further comprising a gate liner ...

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Номер записи: 128
30-01-2020 дата публикации

LATERAL SEMICONDUCTOR NANOTUBE WITH HEXAGONAL SHAPE

Номер: US20200035488A1
Автор: Cheng Kangguo, Lee Choonghyun, Li Juntao, Xu Peng
Принадлежит:

A method of forming a semiconductor structure includes forming one or more fins disposed on a substrate, rounding surfaces of the one or more fins, forming faceted sidewalk from the rounded surfaces of the one or more fins, and forming a lateral semiconductor nanotube shell on the faceted sidewalk. The lateral semiconductor nanotube shell comprises a hexagonal shape. 1. A semiconductor structure , comprising:a substrate; anda lateral semiconductor nanotube shell disposed on a top surface of the substrate;wherein the lateral semiconductor nanotube shell comprises a hexagonal shape.2. The semiconductor structure of claim 1 , wherein the lateral semiconductor nanotube shell comprises silicon germanium (SiGe).3. The semiconductor structure of claim 1 , wherein the lateral semiconductor nanotube shell comprises single-crystal SiGe with a {111} crystalline orientation.4. The semiconductor structure of claim 1 , further comprising:an insulator filled in the lateral semiconductor nanotube shell;a gate dielectric disposed over a portion of exterior sidewalk of the lateral semiconductor nanotube shell; anda gate conductor disposed over the gate dielectric.5. The semiconductor structure of claim 1 , further comprising:an inner gate dielectric disposed on interior sidewalls of the lateral semiconductor nanotube shell;an inner gate conductor disposed on interior sidewalk of the inner gate dielectric;an outer gate dielectric disposed over a portion of exterior sidewalls of the lateral semiconductor nanotube shell; andan outer gate conductor disposed over the outer gate dielectric.6. The semiconductor structure of claim 1 , further comprising a dielectric layer disposed between the top surface of the substrate and the lateral semiconductor nanotube shell.7. The semiconductor structure of claim 1 , further comprising claim 1 , between the top surface of the substrate and the lateral semiconductor nanotubea fin of substrate material;an indent region disposed over the fin of ...

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Номер записи: 129
08-02-2018 дата публикации

ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES

Номер: US20180040557A1
Автор: Basker Veeraraghavan S., Cheng Kangguo, Khakifirooz Ali, Li Juntao
Принадлежит:

Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material. 1. A method comprising:forming metal gates having a capping material on a top surface thereof;protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material;forming an insulator material and metal material within the recess;forming contact structures in the dielectric material between the metal gates, wherein the recess is formed between the contact structures and first filled with the metal material followed by the insulator material; andforming a contact in direct electrical contact with the metal material.2. The method of claim 1 , wherein the recess is formed as an opening in the dielectric material above the contact structures.3. The method of claim 1 , further comprising removing excess insulator material formed on the metal material outside the recess.4. The method of claim 1 , further comprising forming a pattern on the insulator material prior to forming the contact.5. A method comprising:forming metal gate structures in a dielectric material;forming a capping material over the metal gate structures;forming a mask over the capping material of the metal gate structures;recessing the dielectric material between the metal gate structures by an etching process while the mask over the capping material protects the capping material and the metal gate structures;depositing insulator material and metal material within the recess in the dielectric material;forming contact structures in ...

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Номер записи: 130
08-02-2018 дата публикации

Fabrication of a vertical fin field effect transistor having a consistent channel width

Номер: US20180040716A1
Автор: Juntao Li, Kangguo Cheng
Принадлежит: International Business Machines Corp

A method of forming a vertical fin field effect transistor having a consistent channel width, including forming one or more vertical fin(s) on the substrate, wherein the one or more vertical fin(s) have a tapered profile, oxidizing the one or more vertical fin(s) to form an oxide by consuming at least a portion of the vertical fin material, and removing the oxide from the one or more vertical fin(s), wherein the one or more vertical fin(s) include a tapered upper portion, a tapered lower portion and a straight channel portion there between.

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Номер записи: 131
06-02-2020 дата публикации

POROUS SILICON RELAXATION MEDIUM FOR DISLOCATION FREE CMOS DEVICES

Номер: US20200043811A1
Автор: Cheng Kangguo, Divakaruni Ramachandra, Kim Jeehwan, Li Juntao, Sadana Devendra K.
Принадлежит:

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer. 1. A method for forming complementary metal oxide semiconductor devices , the method comprising:doping a second portion of a tensile-strained silicon layer outside a first portion to form a doped portion;growing an undoped silicon layer on the doped portion; andrelaxing strain in the undoped silicon layer over the doped portion by converting the doped portion to an oxide to form a relaxed layer.2. The method as recited in claim 1 , further comprising growing a SiGe layer on the relaxed layer.3. The method as recited in claim 2 , further comprising oxidizing the SiGe layer to convert the relaxed layer to a compressed SiGe layer.4. The method as recited in claim 3 , further comprising etching fins from the tensile-strained silicon layer and the compressed SiGe layer.5. The method as recited in claim 4 , wherein doping the second portion of the tensile-strained silicon layer includes boron doping the second portion.6. The method as recited in claim 5 , wherein converting the doped portion to an oxide to form a relaxed layer includes converting the doped portion to a porous silicon then converting the porous silicon to the oxide.7. The method as recited in claim 6 , wherein converting the doped ...

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Номер записи: 132
18-02-2021 дата публикации

SELF-ALIGNED TOP VIA SCHEME

Номер: US20210050259A1
Автор: Cheng Kangguo, Li Juntao, Radens Carl, Xie Ruilong, Yang Chih-Chao
Принадлежит:

A semiconductor device includes a base structure including a lower level via and a lower level dielectric layer, a conductive pillar including an upper level line and an upper level via disposed on the lower level via, and a protective structure disposed between the lower level via and the upper level line. The protective structure includes a material having an etch rate less than or equal to that of the lower level via. 1. A method for fabricating a semiconductor device , comprising:forming an upper conductive layer on a lower level dielectric layer of a base structure and a protective structure formed on a lower level via of the base structure, the protective structure including a conductive cap layer on the lower level via; andforming a conductive pillar including an upper level line from the upper conductive layer using a subtractive patterning process, wherein the protective structure mitigates damage to the lower level via during the subtractive patterning process.2. The method of claim 1 , further comprising forming the protective structure on the lower level via.3. The method of claim 2 , wherein the conductive cap layer is formed including a material having an etch rate less than or equal to that of the lower level via.4. The method of claim 3 , wherein the conductive cap layer includes a low-R conductive material.5. The method of claim 2 , further comprising recessing the lower level via prior to forming the protective structure.6. The method of claim 5 , wherein the conductive cap layer is formed to have a top surface coplanar with a top surface of the lower level dielectric layer.7. The method of claim 1 , wherein forming the conductive pillar further includes forming an upper level via on the upper level line.8. The method of claim 1 , further comprising forming an upper level dielectric layer.9. A method for fabricating a semiconductor device claim 1 , comprising:forming an upper conductive layer on a lower level dielectric layer of a base structure ...

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Номер записи: 133
06-02-2020 дата публикации

Vertical Transistors with Different Gate Lengths

Номер: US20200043915A1
Автор: Cheng Kangguo, Li Juntao, Miao Xin, Zhang Chen
Принадлежит:

Techniques for forming VFETs with differing gate lengths are provided. In one aspect, a method for forming a VFET device includes: patterning fins in a substrate, wherein at least one of the fins includes a vertical fin channel of a FET and at least another one of the fins includes a vertical fin channel of a FET forming a bottom source and drain; forming bottom spacers on the bottom source and drain; forming gates surrounding the vertical fin channel of the FET and FET forming top spacers on the gate; and forming top source and drains at the tops of the fins by varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET and the FET such that the FETFET have an effective gate length LgateLgate wherein LgateLgate A VFET device is also provided. 1. A method for forming a vertical field-effect-transistor (VFET) device , comprising the steps of:depositing a doped epitaxial layer onto a substrate;{'b': 1', '2, 'patterning fins in the doped epitaxial layer and the substrate using fin hardmasks, wherein at least one of the fins comprises a vertical fin channel of a first FET device (FET) and at least another one of the fins comprises a vertical fin channel of a second FET device (FET);'}forming a bottom source and drain in the substrate beneath the fins;forming bottom spacers on the bottom source and drain;{'b': 1', '2, 'forming gates surrounding the vertical fin channel of the FET and the vertical fin channel of the FET;'}forming top spacers on the gates; and{'b': 1', '2', '1', '1', '2', '2', '1', '2, 'forming top source and drains at the tops of the fins, wherein the step of forming the top source and drains comprises varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET and the vertical fin channel of the FET such that the FET has an effective gate length Lgate and the FET has an effective gate length Lgate, and wherein Lgate>Lgate.'}2. The method of claim ...

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Номер записи: 134
06-02-2020 дата публикации

Vertical Transistors with Different Gate Lengths

Номер: US20200043916A1
Автор: Cheng Kangguo, Li Juntao, Miao Xin, Zhang Chen
Принадлежит:

Techniques for forming VFETs with differing gate lengths are provided. In one aspect, a method for forming a VFET device includes: patterning fins in a substrate, wherein at least one of the fins includes a vertical fin channel of a FET1 and at least another one of the fins includes a vertical fin channel of a FET2; forming a bottom source and drain; forming bottom spacers on the bottom source and drain; forming gates surrounding the vertical fin channel of the FET1 and FET2; forming top spacers on the gate; and forming top source and drains at the tops of the fins by varying a positioning of the top source and drains relative to at least one of the vertical fin channel of the FET1 and the FET2 such that the FET1/FET2 have an effective gate length Lgate1/Lgate2, wherein Lgate1>Lgate2. A VFET device is also provided. 1. A vertical field-effect-transistor (VFET) device , comprising:fins patterned in a substrate, wherein at least one of the fins comprises a vertical fin channel of a first FET device (FET1) and at least another one of the fins comprises a vertical fin channel of a second FET device (FET2), and wherein the fins extend partway through the substrate;a bottom source and drain in the substrate beneath the fins;bottom spacers on the bottom source and drain;gates surrounding the vertical fin channel of the FET1 and the vertical fin channel of the FET2;top spacers on the gates; andtop source and drains at the tops of the fins, wherein a positioning of the top source and drains relative to the vertical fin channel of the FET1 and the vertical fin channel of the FET2 is different such that the FET1 has an effective gate length Lgate1 and the FET2 has an effective gate length Lgate2, and wherein Lgate1>Lgate2.2. The VFET device of claim 1 , wherein the vertical fin channel of the FET1 and the vertical fin channel of the FET2 are undoped.3. The VFET device of claim 1 , wherein the gates surrounding the vertical fin channel of the FET1 and the vertical fin channel ...

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Номер записи: 135
16-02-2017 дата публикации

ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES

Номер: US20170047286A1
Автор: Basker Veeraraghavan S., Cheng Kangguo, Khakifirooz Ali, Li Juntao
Принадлежит:

Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material. 1. A method comprising:forming metal gates having a capping material on a top surface thereof;protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material;forming an insulator material and metal material within the recess; andforming a contact in direct electrical contact with the metal material.2. The method of claim 1 , wherein the protecting of the metal gates comprises forming a masking material over the capping material during the etching process.3. The method of claim 1 , wherein the insulator material and the capping material are of a same material.4. The method of claim 1 , further comprising planarizing the insulator material and metal material claim 1 , prior to forming of the contact.5. The method of claim 1 , wherein the forming of the recess includes etching the dielectric material and a gate module.6. The method of claim 5 , further comprising forming a second insulator material over the metal material.7. The method of claim 6 , further comprising planarizing the insulator material claim 6 , metal material and second insulator material claim 6 , prior to forming of the contact.8. The method of claim 7 , wherein the forming of the contact comprising forming an opening through the second insulator material to expose a surface of the metal material claim 7 , and depositing a metal within the opening.9. The method of claim 1 , further comprising forming contact structures in ...

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Номер записи: 136
16-02-2017 дата публикации

ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES

Номер: US20170047288A1
Автор: Basker Veeraraghavan S., Cheng Kangguo, Khakifirooz Ali, Li Juntao
Принадлежит:

Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material. 1. A structure comprising:an efuse formed between gate metals in a dielectric material;the gate metals including a nitride capping material;the efuse is provided within a recess of the dielectric material; andthe efuse comprises a nitride insulator material and a metal material which is in contact with a contact structure formed in an insulator material above the efuse.2. The structure of claim 1 , wherein the metal material claim 1 , the nitride insulator material claim 1 , and the nitride capping material have surfaces which are planar with one another.3. The structure of claim 1 , further comprising an oxide insulator material in contact with the metal material claim 1 , the nitride insulator material claim 1 , and the nitride capping material.4. The structure of claim 3 , wherein the contact structure is in direct electrical contact with the metal material.5. The structure of claim 4 , wherein the contact structure is in an opening of the oxide insulator material.6. The structure of claim 1 , wherein the gate metals are replacement gate metals.7. The structure of claim 1 , further comprising an insulator material formed over the metal material.8. The structure of claim 7 , wherein the insulator material is a nitride material.9. The structure of claim 8 , wherein the metal material is between the nitride material and the nitride insulator material claim 8 , and portions of the metal material claim 8 , the nitride material and the nitride ...

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Номер записи: 137
15-02-2018 дата публикации

AIR GAP SPACER FORMATION FOR NANO-SCALE SEMICONDUCTOR DEVICES

Номер: US20180047615A1
Автор: Cheng Kangguo, Haigh Thomas J., Li Juntao, Liniger Eric G., Mehta Sanjay C., Nguyen Son V., Park Chanro, Yamashita Tenko
Принадлежит:

Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure. 1. A method , comprising:forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures;etching the insulating material to form a space between the first and second metallic structures; anddepositing a layer of dielectric material over the first and second metallic structures to form an air gap in the space between the first and second metallic structures;wherein the first metallic structure comprises a gate structure of a transistor and wherein the second metallic structure comprises a source/drain contact;wherein an upper portion of the air gap is disposed above an upper surface the first metallic structure and below an upper surface of the second metallic structure; andwherein a bottom portion of the air gap is disposed below a bottom surface of the second metallic structure.2. The method of claim 1 , further comprising:forming a BEOL (back-end-of-line) interconnect ...

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Номер записи: 138
15-02-2018 дата публикации

AIR GAP SPACER FORMATION FOR NANO-SCALE SEMICONDUCTOR DEVICES

Номер: US20180047617A1
Автор: Cheng Kangguo, Haigh Thomas J., Li Juntao, Liniger Eric G., Mehta Sanjay C., Nguyen Son V., Park Chanro, Yamashita Tenko
Принадлежит:

Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure. 1. A semiconductor device , comprising:a first metallic structure and a second metallic structure disposed adjacent to each other on a substrate with a space disposed between the first and second metallic structures; anda dielectric capping layer formed over the first and second metallic structures to form an air gap in the space between the first and second metallic structures;wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.2. The device of claim 1 , wherein the first metallic structure comprises a first metal line formed in an ILD (interlevel dielectric) layer of a BEOL (back-end-of-line) interconnect structure claim 1 , and wherein the second metallic structure comprises a second metal line formed in the ILD layer of the BEOL interconnect structure.3. The device of claim 2 , wherein the portion of the air gap extends above the first metal line and above the second metal line.4. The device of claim 1 , wherein the first metallic structure comprises a ...

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Номер записи: 139
15-02-2018 дата публикации

ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES

Номер: US20180047671A1
Автор: Basker Veeraraghavan S., Cheng Kangguo, Khakifirooz Ali, Li Juntao
Принадлежит:

Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material. 1. A structure comprising:an efuse formed between gate metals in a dielectric material;the gate metals including a nitride capping material;the efuse is provided within a recess of the dielectric material; andthe efuse comprises a nitride insulator material and a metal material which is in contact with a contact structure formed in an insulator material above the efuse.2. The structure of claim 1 , wherein the insulator material is over the metal material.3. The structure of claim 2 , wherein the insulator material is a nitride material.4. The structure of claim 3 , wherein the metal material is between the nitride material and the nitride insulator material claim 3 , and portions of the metal material claim 3 , the nitride material and the nitride insulator material are planar with one another.5. The structure of claim 4 , further comprising a contact which extends through an opening of the nitride material and makes direct electrical contact with a surface of the metal material.6. The structure of claim 5 , wherein an insulator is provided over the nitride material and the contact which extends through an opening of the insulator.7. The structure of claim 1 , wherein the efuse is a metal material.8. The structure of claim 7 , wherein the contact structure is in electrical contact with the metal material.9. The structure of claim 8 , wherein the contact structure is in an opening of an oxide insulator material.10. The structure of claim 8 , ...

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Номер записи: 140
15-02-2018 дата публикации

STRUCTURE AND METHOD FOR FORMING STRAINED FINFET BY CLADDING STRESSORS

Номер: US20180047845A1
Автор: Cheng Kangguo, Li Juntao
Принадлежит:

Various methods and structures for fabricating a strained semiconductor fin of a FinFET device. A strained semiconductor fin structure includes a substrate, a semiconductor fin disposed on the substrate, the semiconductor fin having two fin ends, and a stressor material cladding wrapped around a portion of each of the two fin ends forming a strained semiconductor fin that includes at least one strained channel fin having stressor cladding wrapped around at least one end of the strained channel fin thereby straining the at least one strained channel fin. The stressor cladding can be a compressive nitride stressor to compressively strain a compressively strained silicon germanium fin. The stressor cladding can be a tensile nitride stressor to tensily strain a tensily strained silicon fin. 1. A method for fabricating a fin semiconductor structure , the method comprising:forming at least one semiconductor fin on a substrate;depositing a dielectric fill adjacent to the fin;patterning to remove a portion of the fin and the dielectric;etching the dielectric selective to the fin so that at least one fin end is exposed; anddepositing a stressor material at, and wrapped around and cladding, the at least one fin end to produce at least one strained fin.2. The method of claim 1 , wherein the at least one strained fin comprises a compressively strained fin.3. The method of claim 2 , wherein the compressively strained fin comprises silicon germanium.4. The method of claim 2 , wherein the stressor material comprises a compressive stressor cladding wrapped around at least one end of each of the at least one strained fin.5. The method of claim 4 , wherein the compressive stressor cladding comprises compressive nitride.6. The method of claim 1 , wherein the at least one strained fin comprises a tensily strained fin.7. The method of claim 6 , wherein the tensily strained fin comprises silicon.8. The method of claim 6 , wherein the stressor material comprises a tensile stressor ...

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Номер записи: 141
26-02-2015 дата публикации

METHODS OF FORMING GATE STRUCTURES FOR FINFET DEVICES AND THE RESULTING SMEICONDUCTOR PRODUCTS

Номер: US20150054078A1
Автор: Li Juntao, Ponoth Shom, Xie Ruilong
Принадлежит:

One method disclosed herein includes forming a stack of material layers to form gate structures, performing a first etching process to define an opening through the stack of materials that defines an end surface of the gate structures, forming a gate separation structure in the opening and performing a second etching process to define side surfaces of the gate structures. A device disclosed herein includes first and second active regions that include at least one fin, first and second gate structures, wherein each of the gate structures have end surfaces, and a gate separation structure positioned between the gate structures, wherein opposing surfaces of the gate separation structure abut the end surfaces of the gate structures, and wherein an upper surface of the gate separation structure is positioned above an upper surface of the at least one fin. 1. A method of forming a plurality of gate structures , comprising:forming a stack of material layers to form said plurality of gate structures above a semiconductor substrate;performing at least one first etching process through a first patterned etch mask on said stack of material layers to define at least one opening therethrough, wherein said at least one opening defines an end surface of said plurality of gate structures;removing said first patterned etch mask;forming a gate separation structure in said at least one opening; andwith said gate separation structure in position in said at least one opening, performing at least one second etching process through a second patterned etch mask on said stack of material layers to define side surfaces of said plurality of gate structures.2. The method of claim 1 , wherein said at least one opening is comprised of a plurality of spaced-apart openings and wherein said gate separation structure is formed in each of said spaced-apart openings.3. The method of claim 1 , wherein said at least one opening is a continuous opening and wherein said gate separation structure is formed ...

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Номер записи: 142
14-02-2019 дата публикации

Stacked Nanowires

Номер: US20190051535A1
Автор: Bi Zhenxing, Cheng Kangguo, Li Juntao, Miao Xin
Принадлежит:

Techniques for producing stacked SiGe nanowires using a condensation process without parasitic Ge nanowires as an undesired by-product. In one aspect, a method of forming SiGe nanowires includes the steps of: forming a stack of alternating Si and SiGe layers on a wafer; patterning fins in the stack; selectively thinning the SiGe layers in the fins such that the Si and SiGe layers give the fins an hourglass shape; burying the fins in an oxide material; and annealing the fins under conditions sufficient to diffuse Ge from the SiGe layers in the fins to the Si layers in the fins to form the SiGe nanowires. A FET device and method for formation thereof are also provided. 1. A field effect transistor (FET) device , comprising:at least one stack of silicon germanium (SiGe) nanowires; anda gate at least partially surrounding a portion of each of the SiGe nanowires that serves as a channel region of the FET device, wherein portions of the SiGe nanowires extending out from the gate serve as source and drain regions of the FET device, and wherein the SiGe nanowires have a uniform diameter throughout the source, drain, and channel regions of the FET device.2. The FET device of claim 1 , further comprising inner spacers between the channel region and the source and drain regions.3. The FET device of claim 2 , wherein the inner spacers are formed from an oxide material.4. The FET device of claim 1 , wherein the gate fully surrounds the portion of each of the SiGe nanowires in a gate-all-around (GAA) configuration.5. The FET device of claim 1 , wherein the gate is a metal gate.6. The FET device of claim 5 , wherein the gate comprises an n-type workfunction setting metal.7. The FET device of claim 6 , wherein the n-type workfunction setting metal is selected from the group consisting of: titanium nitride and tantalum nitride.8. The FET device of claim 5 , wherein the gate comprises a p-type workfunction setting metal.9. The FET device of claim 8 , wherein the p-type workfunction ...

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Номер записи: 143
22-02-2018 дата публикации

ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES

Номер: US20180053720A1
Автор: Basker Veeraraghavan S., Cheng Kangguo, Khakifirooz Ali, Li Juntao
Принадлежит:

Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material. 1. A structure , comprising: contact trenches in interlevel dielectric material;', 'a liner material within the contact trenches; and', 'a conductive material on the liner material; and, 'a contact structure between gate structures and which comprisesan insulator material on a planarized surface of the conductive material, the liner material, the gate structures and exposed portions of the interlevel dielectric material;a metal material in an opening in the insulator material and on a surface of the insulator material; andan insulator layer within the opening and on the metal material.2. The structure of claim 1 , wherein the insulator material is oxide.3. The structure of claim 1 , wherein the conductive material is WSix.4. The structure of claim 1 , wherein the insulator layer is be nitride or oxide.5. The structure of claim 1 , further comprising contacts in direct electrical contact with the metal material in the contact structure through an interlevel insulator.6. The structure of claim 1 , wherein the metal material and the insulator material form an effuse that extends over two adjacent contact structures.7. The structure of claim 6 , wherein the contact structures extend into an underlying BOX layer.8. A structure claim 6 , comprising: contact trenches in interlevel dielectric material;', 'a liner material within the contact trenches; and', 'a conductive material on the liner material; and, 'at least two contact structures between gate ...

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Номер записи: 144
22-02-2018 дата публикации

INTEGRATED DEVICE WITH P-I-N DIODES AND VERTICAL FIELD EFFECT TRANSISTORS

Номер: US20180053758A1
Автор: Cheng Kangguo, Li Juntao, Wang Geng, Zhang Qintao
Принадлежит:

An integrated device is provided. The integrated device includes a substrate having a doped upper surface section and an insulator to define first and second substrate regions on opposite sides thereof. Vertical transistors are operably arranged on the doped upper surface section at the first substrate region. P-I-N diodes are operably arranged on the doped upper surface section at the second substrate region. 1. An integrated device , comprising:a substrate having a doped upper surface section and an insulator to define first and second substrate regions on opposite sides thereof;vertical transistors operably arranged on the doped upper surface section at the first substrate region; andP-I-N diodes operably arranged on the doped upper surface section at the second substrate region.2. The integrated device according to claim 1 , wherein:the vertical transistors comprise vertical field effect transistors (VFETs),the substrate comprises an un-doped semiconductor substrate layer underlying the doped upper surface section, andthe insulator comprises a shallow trench insulator extending to the un-doped semiconductor substrate layer through the doped upper surface section.3. The integrated device according to claim 1 , wherein:the doped upper surface section comprises N+ doping at a first sub-region of the first substrate region and P+ doping at a second sub-region of the first substrate region,a first sub-group of the vertical transistors associated with the first sub-region comprises N+ source and drain contacts, anda second sub-group of the vertical transistors associated with the second sub-region comprises P+ source and drain contacts.4. The integrated device according to claim 1 , further comprising:an intrinsic layer disposed on the doped upper surface section at the second substrate region; anda doped layer disposed over each one of the P-I-N diodes at the second substrate region.5. The integrated device according to claim 4 , wherein the doped upper surface ...

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Номер записи: 145
22-02-2018 дата публикации

VERTICAL ANTIFUSE STRUCTURES

Номер: US20180053767A1
Автор: Cheng Kangguo, Li Juntao, Wang Geng, Zhang Qintao
Принадлежит:

Semiconductor devices and methods are provided in which vertical antifuse devices are integrally formed with vertical FET devices, wherein the vertical antifuse devices are formed as part of a process flow for fabricating the vertical FET devices. For example, a semiconductor device comprises a lower source/drain region formed on a substrate, and first and second vertical semiconductor fins formed on the lower source/drain region. First and second metal gate electrodes are formed on sidewalls of the first and second vertical semiconductor fins, respectively. An upper source/drain region is formed on an upper surface of the first vertical semiconductor fin, and a vertical source/drain contact is formed in contact with the upper source/drain region formed on the first vertical semiconductor fin. An upper end of the second vertical semiconductor fin is encapsulated in an insulating material so that the upper end of the second vertical semiconductor fin is floating. 1. A method for fabricating a semiconductor device , comprising:forming a lower source/drain region on a semiconductor substrate;forming a plurality of vertical semiconductor fins on the lower source/drain region, the plurality of vertical semiconductor fins comprising a first vertical semiconductor fin and a second vertical semiconductor fin;forming a first metal gate electrode on a sidewall surface of the first vertical semiconductor fin, and a second metal gate electrode on a sidewall surface of the second vertical semiconductor fin;forming an insulating layer to insulate the first and second metal gate electrodes;forming an upper source/drain region on an upper surface of the first vertical semiconductor fin;forming a vertical source/drain contact to the upper source/drain region formed on the upper surface of the first vertical semiconductor fin; andencapsulating an upper end of the second vertical semiconductor fin in an insulating material so that the upper end of the second vertical semiconductor fin ...

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Номер записи: 146
22-02-2018 дата публикации

FORMATION OF INNER SPACER ON NANOSHEET MOSFET

Номер: US20180053837A1
Автор: Bi Zhenxing, Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит:

A method of forming a field effect transistor (FET) includes performing an oxidation on a nanosheet structure having alternating sheets of silicon and silicon germanium. An oxide etch is performed to remove portions of the sheets of silicon germanium. Other embodiments are also described herein. 1. A method of forming portions of a transistor , the method comprising:performing an oxidation on alternating sheets of silicon and silicon germanium of a nanosheet structure; andperforming an oxide etch to remove portions of the sheets of silicon germanium; wherein:{'b': '2', 'sub': '2', 'the oxide etch is an isotropic oxide etch (SiO and GeO) that is configured to remove more material from the sheets silicon germanium than the sheets of silicon and further configured such that approximately the same amount of material is removed from each sheet.'}2. The method of wherein:performing the oxidation comprises performing a low-temperature radio-frequency plasma oxidation.3. The method of wherein:the low-temperature radio-frequency plasma oxidation is configured to oxidize the sheets of silicon germanium more than the sheets of silicon.4. (canceled)5. The method of wherein:the oxide etch is an isotropic dry oxide etch configured to remove more material from the sheets of silicon germanium than the sheets of silicon.6. The method of wherein:the isotropic dry etch comprises the use of ammonia with fluorine as a reaction gas.7. The method of wherein:a dummy gate structure is positioned above the alternating sheets of silicon and silicon germanium.8. The method of further comprising:depositing a hard mask layer on the nanosheet structure;oxidizing the hard mask layer;removing portions of the hard mask layer to reveal areas of the nanosheet structure to be etched;etching the revealed areas of the nanosheet structure; andremoving the hard mask layer.9. The method of wherein:the hard mask layer is a nitride.10. The method of wherein:the hard mask is selected from SiN, atomic layer ...

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Номер записи: 147
22-02-2018 дата публикации

ILD PROTECTION IN VFET DEVICES

Номер: US20180053844A1
Автор: Bi Zhenxing, Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит:

A method of forming a semiconductor device and resulting structures having an etch-resistant interlayer dielectric (ILD) that maintains height during a top epitaxy clean by forming a dielectric layer on a semiconductor structure; wherein the dielectric layer includes a first dielectric material; converting at least a portion of the dielectric layer to a second dielectric material; and exposing the portion of the dielectric layer to an etch material; wherein the etch material includes a first etch characteristic defining a first rate at which the etch material etches the first dielectric material; and wherein the etch material further includes a second etch characteristic defining a second rate at which the etch material etches the portion of the dielectric layer; wherein the first rate is different than the second rate. 1. A method for forming a semiconductor device , the method comprising:forming a dielectric layer on a semiconductor structure;wherein the dielectric layer comprises a first dielectric material;converting at least a portion of the dielectric layer to a second dielectric material; andexposing the portion of the dielectric layer to an etch material;wherein the etch material comprises a first etch characteristic comprising a first rate at which the etch material etches the first dielectric material; andwherein the etch material further comprises a second etch characteristic comprising a second rate at which the etch material etches the portion of the dielectric layer;wherein the first rate is different than the second rate.2. The method of claim 1 , wherein forming the semiconductor structure comprises:forming a bottom epitaxy region on a substrate;forming a semiconductor fin on the bottom epitaxy region;forming a gate stack over a channel region of the semiconductor fin;forming a hard mask overlying the semiconductor fin; andforming a conformal liner on the substrate, the gate stack, and the hard mask.3. The method of claim 1 , wherein exposing the ...

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Номер записи: 148
25-02-2021 дата публикации

VERTICAL TRANSISTOR WITH SELF-ALIGNED GATE

Номер: US20210057565A1
Автор: Cheng Kangguo, Li Juntao, Park Chanro, Xie Ruilong
Принадлежит:

A method of forming a vertical transistor is provided. The method includes forming a first set of vertical fins in a first row on a first bottom source/drain layer, and a second set of vertical fins in a second row on a second bottom source/drain layer, wherein the vertical fins in the same row are separated by a spacing with a sidewall-to-sidewall distance, S, and the vertical fins in the same column of adjacent rows are separated by a gap having a gap distance, G. The method further includes forming a gate metal layer on the first set of vertical fins and the second set of vertical fins, wherein the gate metal layer does not fill in the gap between vertical fins in the same column, and forming a cover layer plug in the remaining gap after forming the gate metal layer. 1. A method of forming a vertical transistor , comprising:{'sub': D', 'D, 'forming a first set of vertical fins in a first row on a first bottom source/drain layer, and a second set of vertical fins in a second row on a second bottom source/drain layer, wherein the vertical fins in the same row are separated by a spacing with a sidewall-to-sidewall distance, S, and the vertical fins in the same column of adjacent rows are separated by a gap having a gap distance, G;'}forming a gate metal layer on the first set of vertical fins and the second set of vertical fins, wherein the gate metal layer does not fill in the gap between vertical fins in the same column; andforming a cover layer plug in the remaining gap after forming the gate metal layer.2. The method of claim 1 , wherein the first bottom source/drain layer is n-doped and the second bottom source/drain layer is p-doped.3. The method of claim 1 , wherein the sidewall-to-sidewall distance claim 1 , S claim 1 , is in a range of about 15 nm to about 60 nm.4. The method of claim 1 , wherein the end wall-to-end wall gap distance claim 1 , G claim 1 , is in a range of about 30 nm to about 80 nm.5. The method of claim 1 , wherein the top surface of the ...

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Номер записи: 149
13-02-2020 дата публикации

VFET DEVICES WITH ILD PROTECTION

Номер: US20200051806A1
Автор: Bi Zhenxing, Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит:

A method of forming a semiconductor device and resulting structures having an etch-resistant interlayer dielectric (ILD) that maintains height during a top epitaxy clean by forming a dielectric layer on a semiconductor structure; wherein the dielectric layer includes a first dielectric material; converting at least a portion of the dielectric layer to a second dielectric material; and exposing the portion of the dielectric layer to an etch material; wherein the etch material includes a first etch characteristic defining a first rate at which the etch material etches the first dielectric material; and wherein the etch material further includes a second etch characteristic defining a second rate at which the etch material etches the portion of the dielectric layer; wherein the first rate is different than the second rate. 1. A semiconductor device having an etch-resistant interlayer dielectric (ILD) during a top epitaxy clean , the device comprising:a semiconductor structure;a dielectric layer formed on the semiconductor structure;a first material implanted in a first portion of the dielectric layer to form a second material, the second material having a higher etch resistance than the dielectric layer with respect to an etch material; anda top epitaxy region formed on a pre-cleaned surface of a semiconductor fin of the semiconductor structure.2. The device of claim 1 , the semiconductor structure further comprising:a substrate;a bottom epitaxy region formed on the substrate;a semiconductor fin formed on the bottom epitaxy region;a gate stack formed over a channel region of the semiconductor fin;a hard mask overlying the semiconductor fin; anda conformal liner formed on the substrate, the gate stack, and the hard mask.3. The device of claim 1 , wherein the dielectric layer is silicon dioxide (SiO) claim 1 , the first material is nitrogen claim 1 , and the second material is a silicon oxynitride (SiON).4. The method of claim 1 , wherein the first portion of the ...

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Номер записи: 150
13-02-2020 дата публикации

AIRGAP FORMATION IN BEOL INTERCONNECT STRUCTURE USING SIDEWALL IMAGE TRANSFER

Номер: US20200051850A1
Автор: Cheng Kangguo, De Silva Ekmini A., Li Juntao, Song Yi, Xu Peng
Принадлежит:

A method and structure of forming air gaps with a sidewall image transfer process such as self-aligned double patterning to reduce capacitances. Different materials can be provided in the mandrel and non-mandrel regions to enlarge a process window for metal line end formation. 1. A back end of the line (BEOL) interconnect structure comprising:a plurality of lines comprising a metal conductor separated by a space having a width of less than 20 nm, wherein the plurality of metal conductor lines are provided on an ultralow k dielectric; andan oxide provided in the space including an airgap therein.2. The BEOL interconnect structure of claim 1 , wherein the metal conductor comprises Cu claim 1 , Co claim 1 , Al claim 1 , AlCu claim 1 , Ti claim 1 , TiN claim 1 , Ta claim 1 , TaN claim 1 , W claim 1 , WN claim 1 , MoN claim 1 , Pt claim 1 , Pd claim 1 , Os claim 1 , Ru claim 1 , IrO2 claim 1 , ReO2 claim 1 , ReO3 claim 1 , alloys thereof claim 1 , or mixtures thereof.3. The BEOL interconnect structure of claim 1 , wherein the metal conductor comprises copper or copper and an alloying element.4. The BEOL interconnect structure of claim 3 , wherein the alloying element is in an amount from about 0.001 weight percent (wt. %) to about 10 wt %.5. The BEOL interconnect structure of claim 1 , wherein the ultralow k dielectric is intermediate line ends.6. The BEOL interconnect structure of further comprising a first insulator intermediate line ends of at least one of the plurality of the plurality of metal conductor lines corresponding to a mandrel region and a second insulator intermediate line ends of at least one of the plurality of the plurality of metal conductor lines corresponding to a non-mandrel region claim 1 , wherein the first insulator is a different material than the second insulator.7. The BEOL interconnect structure of claim 1 , wherein an oxide and/or a nitride is intermediate line ends.8. The BEOL interconnect structure of claim 1 , wherein the plurality of ...

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Номер записи: 151
13-02-2020 дата публикации

RRAM CELLS IN CROSSBAR ARRAY ARCHITECTURE

Номер: US20200052037A1
Автор: Ando Takashi, Cheng Kangguo, Kong Dexin, Li Juntao
Принадлежит:

A method is presented for forming vertical crossbar resistive random access memory (RRAM) cells. The method includes forming a substantially U-shaped bottom electrode over a substrate, filling the U-shaped bottom electrode with a first conductive material, capping the U-shaped bottom electrode with a dielectric cap, depositing a high-k material, and forming a top electrode such that active areas of the RRAM cells are vertically aligned and the U-shaped bottom electrode is shared between neighboring RRAM cells. 1. A method for forming vertical crossbar resistive random access memory (RRAM) cells , the method comprising:forming a substantially U-shaped bottom electrode over a substrate;filling the U-shaped bottom electrode with a first conductive material;capping the U-shaped bottom electrode with a dielectric cap;depositing a high-k material; andforming a top electrode such that active areas of the RRAM cells are vertically aligned and the U-shaped bottom electrode is shared between neighboring RRAM cells.2. The method of claim 1 , further comprising claim 1 , before forming the U-shaped bottom electrode:forming a plurality of dielectric pillars over a substrate;forming a dielectric layer over the plurality of dielectric pillars; andetching the dielectric layer to form dielectric regions between the plurality of dielectric pillars.3. The method of claim 1 , further comprising claim 1 , after forming the U-shaped bottom electrode claim 1 , removing the dielectric pillars to form recesses.4. The method of claim 3 , further comprising filling the recesses with a second conductive material.5. The method of claim 4 , further comprising forming first vias in direct contact with the second conductive material.6. The method of claim 5 , further comprising forming second vias between the substrate and the U-shaped bottom electrode.7. The method of claim 6 , wherein the plurality of dielectric pillars include nitride pillars and the dielectric layer includes an oxide layer.8. ...

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Номер записи: 152
13-02-2020 дата публикации

VERTICAL TRANSPORT FIELD-EFFECT TRANSISTORS WITH STRAINED CHANNELS

Номер: US20200052079A1
Автор: ANDERSON Brent A., Cheng Kangguo, Li Juntao
Принадлежит:

A method of forming a semiconductor structure includes forming at least one fin disposed over a top surface of a substrate, the fin providing a vertical transport channel for a vertical transport field-effect transistor. The method also includes forming a top source/drain region disposed over a top surface of the fin, and forming a first contact trench at a first end of the fin and a second contact trench at a second end of the fin, the first and second contact trenches being self-aligned to the top source/drain region. The method further includes forming inner spacers on sidewalls of the first contact trench and the second contact trench, and forming contact material in the first contact trench and the second contact trench between the inner spacers. The contact material comprises a stressor material that induces vertical strain in the fin. 1. A method of forming a semiconductor structure , comprising:forming at least one fin disposed over a top surface of a substrate, the at least one fin providing a vertical transport channel for a vertical transport field-effect transistor;forming a top source/drain region disposed over a top surface of the at least one fin;forming a first contact trench at a first end of the at least one fin and a second contact trench at a second end of the at least one fin, the first and second contact trenches being self-aligned to the top source/drain region;forming inner spacers on sidewalls of the first contact trench and the second contact trench; andforming contact material in the first contact trench and the second contact trench between the inner spacers;wherein the contact material comprises a stressor material that induces vertical strain in the at least one fin.2. The method of claim 1 , wherein:the first contact trench provides an opening that reveals a portion of a top surface of a bottom source/drain region at the first end of the at least one fin;the second contact trench provides an opening that reveals a portion of a gate ...

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Номер записи: 153
13-02-2020 дата публикации

BOTTOM SPACER STRUCTURE FOR VERTICAL FIELD EFFECT TRANSISTOR AND METHOD OF FORMING SAME

Номер: US20200052094A1
Автор: Cheng Kangguo, Lee Choonghyun, Li Juntao, Mochizuki Shogo
Принадлежит:

A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, sacrificial spacer layers are formed on the plurality of fins, and portions of the semiconductor substrate located under the sacrificial spacer layers and located at sides of the plurality of fins are removed. Bottom source/drain regions are grown in at least part of an area where the portions of the semiconductor substrate were removed, and sacrificial epitaxial layers are grown on the bottom source/drain regions. The method also includes diffusing dopants from the bottom source/drain regions and the sacrificial epitaxial layers into portions of the semiconductor substrate under the plurality of fins. The sacrificial epitaxial layers are removed, and bottom spacers are formed in at least part of an area where the sacrificial epitaxial layers were removed. 1. A method for manufacturing a semiconductor device , comprising:forming a plurality of fins on a semiconductor substrate;forming sacrificial spacer layers on the plurality of fins;removing portions of the semiconductor substrate located under the sacrificial spacer layers and located at sides of the plurality of fins;growing bottom source/drain regions in at least part of an area where the portions of the semiconductor substrate were removed;growing sacrificial epitaxial layers on the bottom source/drain regions;diffusing dopants from the bottom source/drain regions and the sacrificial epitaxial layers into portions of the semiconductor substrate under the plurality of fins;removing the sacrificial epitaxial layers; andforming bottom spacers in at least part of an area where the sacrificial epitaxial layers were removed.2. The method according to claim 1 , wherein the bottom spacers are formed in spaces between top surfaces of the bottom source/drain regions and bottom surfaces of the sacrificial spacer layers.3. The method according to claim 2 , wherein top surfaces of the bottom ...

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Номер записи: 154
13-02-2020 дата публикации

METHOD AND STRUCTURE FOR FORMING VERTICAL TRANSISTORS WITH VARIOUS GATE LENGTHS

Номер: US20200052114A1
Автор: Cheng Kangguo, Lee Choonghyun, Li Juntao, Mochizuki Shogo
Принадлежит:

Various methods and structures for fabricating a plurality of vertical fin FETs on the same semiconductor substrate in which a first gate length of a first gate in a first vertical fin FET is less than a second gate length of a second gate in a second vertical fin FET. A difference in gate lengths between different vertical fin FETs can be precisely fabricated by using atomic layer silicon germanium epitaxy. Gate length offset is formed at a bottom source/drain junction region of each vertical fin FET transistor, which allows downstream processing for all vertical fin FET transistors to be the same. 1. A semiconductor structure comprising:a first vertical fin field-effect transistor formed on a semiconductor substrate, the first vertical fin field-effect transistor comprising a first vertical fin, a first bottom source/drain junction layer disposed on the semiconductor substrate and a first gate disposed on the first bottom source/drain junction layer, the first gate having a first gate length; anda second vertical fin field-effect transistor formed on the semiconductor substrate, the second vertical fin field-effect transistor comprising a second vertical fin, a second bottom source/drain junction layer disposed on the semiconductor substrate and a second gate disposed on the second bottom source/drain junction layer, the second gate having a second gate length that is greater than the first gate length, the first vertical fin including a staircase feature inside the first bottom source/drain junction layer and the second vertical fin does not include a staircase feature inside the second bottom source/drain junction layer.2. The semiconductor structure of claim 1 , wherein the staircase feature includes a step from a vertically lower portion of the first vertical fin to a vertically higher portion of the first vertical fin.3. The semiconductor structure of claim 2 , wherein the vertically lower portion of the first vertical fin in the staircase feature has a first ...

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Номер записи: 155
21-02-2019 дата публикации

FIN-TYPE FET WITH LOW SOURCE OR DRAIN CONTACT RESISTANCE

Номер: US20190058044A1
Автор: Cheng Kangguo, Li Juntao, Wu Heng, Xu Peng
Принадлежит:

Embodiments of the invention are directed to methods of forming a FinFET. A non-limiting example method includes forming a fin across from a major surface of a substrate. A dummy gate is formed around a channel region of the fin. A source region or a drain region is formed on the fin, and the dummy gate is replaced with a metal gate structure. Subsequent to replacing the dummy gate with the metal gate structure, dopants are inserted into the source region or the drain region. 119.-. (canceled)20. A configuration of fin-type field effect transistors (FinFETs) comprising:a substrate comprising a major surface having an NFET region and a PFET region;a first fin across from the NFET region of the major surface of the substrate;a second fin across from the PFET region of the major surface of the substrate;a first metal gate around a first channel region of the first fin;a second metal gate around a second channel region of the second fin;a second doped source region or a second doped drain region on the second fin;a first doped source region or a first doped drain region on the first fin;a layer of sidewall spacer material in the NFET region and the PFET region;wherein a first segment of the layer of the sidewall spacer material is along a first sidewall of the first metal gate;wherein a second segment of the layer of the sidewall spacer material is along a second sidewall of the second metal gate;wherein a thickness dimension of the layer of sidewall spacer material is substantially uniform and extends through first segment of the layer of sidewall spacer material and the second segment of the layer of sidewall spacer material. The present invention relates in general to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to fabrication methods and resulting structures for fin-type field effect transistors (FinFETs) having low source/drain (S/D) contact resistance.A FinFET is a type of non-planar ...

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Номер записи: 156
21-02-2019 дата публикации

FIN-TYPE FET WITH LOW SOURCE OR DRAIN CONTACT RESISTANCE

Номер: US20190058045A1
Автор: Cheng Kangguo, Li Juntao, Wu Heng, Xu Peng
Принадлежит:

Embodiments of the invention are directed to methods of forming a FinFET. A non-limiting example method includes forming a fin across from a major surface of a substrate. A dummy gate is formed around a channel region of the fin. A source region or a drain region is formed on the fin, and the dummy gate is replaced with a metal gate structure. Subsequent to replacing the dummy gate with the metal gate structure, dopants are inserted into the source region or the drain region. 17-. (canceled)8. A method of forming fin-type field effect transistors (FinFETs) , the method comprising:forming a substrate comprising a major surface having a first region and a second region;forming a first fin across from the first region of the major surface of the substrate;forming a second fin across from the second region of the major surface of the substrate;forming a first dummy gate around a first channel region of the first fin;forming a second dummy gate around a second channel region of the second fin;forming a first interlayer dielectric (ILD) over the first region, wherein the first ILD comprises a first dielectric material;forming a second source region or a second drain region on the second fin;forming a second ILD over the second region, wherein the second ILD comprises a second dielectric material that is different from the first dielectric material;removing the first ILD from over the first region;forming a first source region or a first drain region on the first fin;replacing the first dummy gate with a first metal gate structure; andreplacing the second dummy gate with a second metal gate structure.9. The method of further comprising claim 8 , subsequent to replacing the first dummy gate with the first metal gate structure claim 8 , removing the first ILD and inserting first dopants into the first source region or the first drain region.10. The method of further comprising claim 9 , subsequent to replacing the second dummy gate with the second metal gate structure claim ...

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Номер записи: 157
01-03-2018 дата публикации

Vertical fuse structures

Номер: US20180061758A1
Автор: Chih-Chao Yang, Junli Wang, Juntao Li
Принадлежит: International Business Machines Corp

Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein the vertical fuse devices are formed as part of a process flow for fabricating the FINFET devices. For example, a semiconductor device comprises first and second vertical semiconductor fins, a vertical fuse device, and a FINFET device. The vertical fuse device comprises a metal fuse element formed over a portion of the first vertical semiconductor fin, and the FINFET device comprises a metal gate electrode formed over a portion of the second vertical semiconductor fin. The metal fuse element and the metal gate electrode are concurrently formed as part of a replacement metal gate process flow.

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Номер записи: 158
01-03-2018 дата публикации

VERTICAL FUSE STRUCTURES

Номер: US20180061759A1
Автор: Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит:

Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein the vertical fuse devices are formed as part of a process flow for fabricating the FINFET devices. For example, a semiconductor device comprises first and second vertical semiconductor fins, a vertical fuse device, and a FINFET device. The vertical fuse device comprises a metal fuse element formed over a portion of the first vertical semiconductor fin, and the FINFET device comprises a metal gate electrode formed over a portion of the second vertical semiconductor fin. The metal fuse element and the metal gate electrode are concurrently formed as part of a replacement metal gate process flow. 1. A semiconductor device , comprising:a plurality of vertical semiconductor fins formed on a semiconductor substrate, the plurality of vertical semiconductor fins comprising a first vertical semiconductor fin and a second vertical semiconductor fin;a vertical fuse device comprising a metallic fuse element formed over a portion of the first vertical semiconductor fin, wherein the metallic fuse element comprises a first conformal metallic layer formed on the portion of the first vertical semiconductor fin, and a first metallic electrode layer formed on the first conformal metallic layer; anda FINFET (Fin Field Effect Transistor) device comprising a metallic gate electrode formed over a portion of the second vertical semiconductor fin, wherein the metallic gate electrode comprises a high-k metallic gate stack structure conformally formed on the portion of the second vertical semiconductor fin and a second metallic electrode layer formed on the high-k metallic gate stack structure, wherein the high-k metallic gate stack structure comprises a conformal layer of dielectric material formed on the portion of the second vertical semiconductor fin and a second conformal metallic layer formed on the conformal layer of dielectric ...

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Номер записи: 159
20-02-2020 дата публикации

FORMING VERTICAL TRANSISTOR DEVICES WITH GREATER LAYOUT FLEXIBILITY AND PACKING DENSITY

Номер: US20200058565A1
Автор: Cheng Kangguo, Lee Choonghyun, Li Juntao
Принадлежит:

A method of forming a fin field effect transistor circuit is provided. The method includes forming a plurality of vertical fins on a substrate, and forming a protective liner having a varying thickness on the substrate and plurality of vertical fins. The method further includes removing thinner portions of the protective liner from the substrate to form protective liner segments on the plurality of vertical fins. The method further includes removing portions of the substrate exposed by removing the thinner portions of the protective liner to form trenches adjacent to at least one pair of vertical fins and two substrate mesas. The method further includes laterally etching the substrate mesa to widen the trench, reduce the width of the substrate mesa to form a supporting pillar, and undercut the at least one pair of vertical fins, and forming a first bottom source/drain layer in the widened trench. 1. A method of forming a fin field effect transistor circuit , comprising:forming a plurality of vertical fins on a substrate;forming a protective liner having a varying thickness on the substrate and plurality of vertical fins;removing thinner portions of the protective liner from the substrate to form protective liner segments on the plurality of vertical fins;removing portions of the substrate exposed by removing the thinner portions of the protective liner to form trenches adjacent to at least one pair of vertical fins and two substrate mesas;laterally etching the substrate mesa to widen the trench, reduce the width of the substrate mesa to form a supporting pillar, and undercut the at least one pair of vertical fins; andforming a first bottom source/drain layer in the widened trench.2. The method of claim 1 , further comprising removing the first bottom source/drain layer from a widened trench claim 1 , and forming a second bottom source/drain layer in the widened trench.3. The method of claim 2 , wherein the first bottom source/drain layer includes a first dopant type ...

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Номер записи: 160
20-02-2020 дата публикации

FORMATION OF SEMICONDUCTOR DEVICES INCLUDING ELECTRICALLY PROGRAMMABLE FUSES

Номер: US20200058587A1
Автор: Li Juntao, Yang Chih-Chao
Принадлежит:

A method for fabricating a semiconductor device including an electrically programmable fuse includes forming conductive material within one or more openings formed through a dielectric material disposed on a first electrode, and forming one or more second electrodes by planarizing the conductive material. Forming the conductive material includes forming one or more voids encapsulated by the conductive material such that the one or more voids have boundaries defined in part by portions of the conductive material corresponding to fuse links disposed between the one or more voids and the dielectric material. 1. A method for fabricating a semiconductor device including an electrically programmable fuse , comprising:forming conductive material within one or more openings formed through a dielectric material disposed on a first electrode, including forming one or more voids encapsulated by the conductive material such that the one or more voids have boundaries defined in part by portions of the conductive material corresponding to fuse links disposed between the one or more voids and the dielectric material; andforming one or more second electrodes by planarizing the conductive material.2. The method of claim 1 , further comprising forming a diffusion barrier prior to forming the conductive material.3. The method of claim 1 , wherein forming the conductive material further includes non-conformally depositing the conductive material.4. The method of claim 3 , wherein the conductive material is non-conformally deposited by employing physical vapor deposition (PVD).5. The method of claim 1 , wherein forming the conductive material further includes forming the conductive material via electroplating.6. The method of claim 1 , further comprising programming the electrically programmable fuse by applying a voltage to the first electrode and at least one of the one or more second electrodes.7. The method of claim 1 , wherein the one or more voids are formed having five sides.8. A ...

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Номер записи: 161
20-02-2020 дата публикации

FORMATION OF SEMICONDUCTOR DEVICES INCLUDING ELECTRICALLY PROGRAMMABLE FUSES

Номер: US20200058588A1
Автор: Li Juntao, Yang Chih-Chao
Принадлежит:

A semiconductor device including an electrically programmable fuse includes a substrate, a first electrode on the substrate, dielectric material on the first electrode, one or more second electrodes including a conductive material disposed on the first electrode between portions of the dielectric material, and one or more voids encapsulated by the conductive material such that the one or more voids have boundaries defined in part by portions of the conductive material corresponding to fuse links disposed between the one or more voids and the dielectric material. 1. A semiconductor device including an electrically programmable fuse , comprising:a substrate;a first electrode on the substrate;dielectric material on the first electrode;one or more second electrodes including a conductive material disposed on the first electrode between portions of the dielectric material; andone or more voids encapsulated by the conductive material such that the one or more voids have boundaries defined in part by portions of the conductive material corresponding to fuse links disposed between the one or more voids and the dielectric material.2. The device of claim 1 , wherein the first electrode includes at least one material selected from the group consisting of: copper (Cu) claim 1 , tungsten (W) claim 1 , and aluminum (Al).3. The device of claim 2 , wherein the first electrode includes an aluminum copper alloy.4. The device of claim 1 , wherein the first electrode has a thickness of from about 80 nm to about 500 nm.5. The device of claim 1 , wherein the dielectric material has a thickness from about 200 nm to about 400 nm.6. The device of claim 1 , further comprising a conformal diffusion barrier.7. The device of claim 1 , wherein at least one of the one or more second electrodes is electrically programmed.8. A semiconductor device including an electrically programmable fuse claim 1 , comprising:a substrate;a first electrode on the substrate;dielectric material on the first ...

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Номер записи: 162
01-03-2018 дата публикации

VERTICAL FIELD EFFECT TRANSISTOR INCLUDING INTEGRATED ANTIFUSE

Номер: US20180061844A1
Автор: Cheng Kangguo, Li Juntao, Wang Geng, Zhang Qintao
Принадлежит:

A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate. 1. A vertical field effect transistor (FET) , comprising:a vertical semiconductor channel including a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region;an electrically conductive gate that encapsulates the vertical semiconductor channel; anda split-channel antifuse device between the source/drain region and the electrically conductive gate, the split-channel antifuse device including a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.2. The vertical FET of claim 1 , wherein the gate dielectric comprises:a first dielectric layer that has a first thickness and has a first end that contacts the substrate; anda second dielectric layer that has a second thickness different from the first thickness, and that has a first end contacting a second end of the first dielectric layer.3. The vertical FET of claim 3 , wherein the first dielectric layer has a first dielectric breakdown strength that is less than a second dielectric breakdown strength of the second dielectric layer.4. The vertical FET of claim 3 , wherein the first thickness is less than the second thickness.5. The vertical FET of claim 4 , wherein the first thickness defines the first dielectric breakdown strength and the second thickness defines the second dielectric breakdown strength.6. The vertical ...

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Номер записи: 163
01-03-2018 дата публикации

VERTICAL FIELD EFFECT TRANSISTOR INCLUDING INTEGRATED ANTIFUSE

Номер: US20180061845A1
Автор: Cheng Kangguo, Li Juntao, Wang Geng, Zhang Qintao
Принадлежит:

A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate. 1. A method of integrating an antifuse device with a vertical field effect transistor (FET) , the method comprising:forming a vertical semiconductor channel on an upper surface of a semiconductor substrate;forming a split-channel gate dielectric on the outer surface of the vertical semiconductor channel; andforming an electrically conductive gate that encapsulates the split-channel gate dielectric and the vertical semiconductor channel.2. The method of claim 1 , wherein forming the split-channel gate dielectric includes forming a first dielectric layer having a first thickness and forming a second dielectric layer having a second thickness greater than the first thickness.3. The method of claim 2 , further comprising epitaxially growing a source/drain region from a first end of the vertical channel region located opposite a second end of the vertical channel region that contacts the upper surface of the semiconductor substrate.4. The method of claim 3 , wherein forming the split-channel gate dielectric further includes forming the first dielectric layer on an upper surface of the semiconductor substrate.5. The method of claim 4 , wherein forming the split-channel gate dielectric further comprises forming the second dielectric layer between the first dielectric layer and the source/drain region.6. The method of claim 1 , wherein forming the first and second dielectric layers comprises ...

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Номер записи: 164
01-03-2018 дата публикации

Closely packed vertical transistors with reduced contact resistance

Номер: US20180061967A1
Автор: Juntao Li, Kangguo Cheng, Peng Xu, Zhenxing Bi
Принадлежит: International Business Machines Corp

A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a semiconductor structure on a doped region of a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin. A liner is formed on the gate and the semiconductor fin, and a dielectric layer is formed on the liner. Portions of the liner are removed to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer. A recessed opening is formed by recessing portions of the liner from the exposed sidewall of the dielectric layer. A top epitaxy region is formed on the exposed portions of the semiconductor fin and dielectric layer such that an extension of the top epitaxy region fills the recessed opening. The top epitaxy region is confined between portions of the liner.

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Номер записи: 165
20-02-2020 дата публикации

INVERSE T-SHAPED CONTACT STRUCTURES HAVING AIR GAP SPACERS

Номер: US20200058759A1
Автор: Cheng Kangguo, Lee Choonghyun, Li Juntao, Wu Heng, Xu Peng
Принадлежит:

A method of fabricating air gap spacers is provided. The method includes forming gate structures to extend upwardly from a substrate with source or drain (S/D) regions disposed between the gate structures and with contact trenches defined above the S/D regions and between the gate structures. The method further includes disposing contacts in the contact trenches. The method also includes configuring the contacts to define open-ended air gap spacer trenches with the gate structures. In addition, the method includes forming a cap over the open-ended air gap spacer trenches to define the open-ended air gap spacer trenches as air gap spacers. The gate structures have an initial structure prior to and following the disposing and the configuring of the contacts and prior to and following the forming of the cap. 1. A method of fabricating air gap spacers , the method comprising:forming gate structures to extend from a substrate with source or drain (S/D) regions and contact trenches;disposing contacts in the contact trenches;configuring the contacts to define open-ended air gap spacer trenches with the gate structures; andcapping the open-ended air gap spacer trenches to define the open-ended air gap spacer trenches as air gap spacers,the gate structures having an initial structure prior to and following the disposing and the configuring of the contacts and prior to and following the capping.2. The wafer fabrication method according to claim 1 , wherein the gate structures each have a same initial structure prior to the disposing and the configuring of the contacts and the capping.3. The wafer fabrication method according to claim 2 , wherein the gate structures each have the same initial structure following the disposing and the configuring of the contacts and the capping.4. The wafer fabrication method according to claim 1 , wherein the initial structure comprises:a gate stack;a dielectric material lid; anddielectric material spacers.5. The wafer fabrication method ...

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Номер записи: 166
20-02-2020 дата публикации

VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES WITH SELF-ALIGNED SOURCE AND DRAIN JUNCTIONS

Номер: US20200058767A1
Автор: Cheng Kangguo, Lee Choonghyun, Li Juntao, Mochizuki Shogo
Принадлежит:

A method of forming a fin field effect transistor device is provided. The method includes forming a plurality of vertical fins on a substrate. The method further includes forming a bottom source/drain layer adjacent to the plurality of vertical fins, and growing a doped layer on the bottom source/drain layer and sidewalls of the plurality of vertical fins. The method further includes forming a dummy gate liner on the doped layer and the bottom source/drain layer, and forming a dummy gate fill on the dummy gate liner. The method further includes forming a protective cap layer on the dummy gate fill, and removing a portion of the protective cap layer to expose a top surface of the plurality of vertical fins. 1. A method of forming a fin field effect transistor device , comprising:forming a plurality of vertical fins on a substrate;forming a bottom source/drain layer adjacent to the plurality of vertical fins;growing a doped layer on the bottom source/drain layer and sidewalls of the plurality of vertical fins;forming a dummy gate liner on the doped layer and the bottom source/drain layer;forming a dummy gate fill on the dummy gate liner;forming a protective cap layer on the dummy gate fill; andremoving a portion of the protective cap layer to expose a top surface of the plurality of vertical fins.2. The method of claim 1 , further comprising forming a top source/drain on each of the plurality of vertical fins.3. The method of claim 2 , further comprising removing a portion of the protective cap layer to form protective spacers on each of the top source/drains.4. The method of claim 3 , further comprising removing the dummy gate fill and a portion of the dummy gate liner to expose portions of the doped layer on the sidewalls of the plurality of vertical fins.5. The method of claim 4 , further comprising removing a portion of the doped layer to form upper and lower cavities claim 4 , and upper doped layer segments between the vertical fin and protective spacers.6. The ...

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Номер записи: 167
20-02-2020 дата публикации

FIN FIELD-EFFECT TRANSISTORS WITH ENHANCED STRAIN AND REDUCED PARASITIC CAPACITANCE

Номер: US20200058771A1
Автор: Cheng Kangguo, Lee Choonghyun, Li Juntao, Mochizuki Shogo
Принадлежит:

A method of forming a semiconductor structure includes forming a substrate, the substrate having a first portion with a first height and second recessed portions with a second height less than the first height. The method also includes forming embedded source/drain regions disposed over top surfaces of the second recessed portions of the substrate, and forming one or more fins from a portion of the substrate disposed between the embedded source/drain regions, the one or more fins providing channels for fin field-effect transistors (FinFETs). The method further includes forming a gate stack disposed over the one or more fins, and forming inner oxide spacers disposed between the gate stack and the source/drain regions. 1. A method of forming a semiconductor structure , comprising:forming a substrate, the substrate comprising a first portion with a first height and second recessed portions with a second height less than the first height;forming embedded source/drain regions disposed over top surfaces of the second recessed portions of the substrate;forming one or more fins from the first portion of the substrate disposed between the embedded source/drain regions, the one or more fins providing channels for fin field-effect transistors;forming a gate stack disposed over the one or more fins; andforming inner oxide spacers disposed between the gate stack and the embedded source/drain regions; performing an oxidation to form an oxide layer on sidewalls of the embedded source/drain regions and surfaces of the one or more fins, an oxidation rate of the embedded source/drain regions being greater than an oxidation rate of the one or more fins; and', 'etching the oxide layer to remove portions of the oxide layer from the surface of the one or more fins and to thin portions of the oxide layer disposed on sidewalls of the embedded source/drain regions, the thinned portions of the oxide layer disposed on the sidewalls of the embedded source/drain regions comprising the inner ...

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Номер записи: 168
12-03-2015 дата публикации

ULTRA-THIN METAL WIRES FORMED THROUGH SELECTIVE DEPOSITION

Номер: US20150069625A1
Автор: Li Juntao, Yang Chih-Chao, Yin Yunpeng
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a pair of ultra-thin metal wires in an opening using a selective deposition process. 1. A method of forming a semiconductor device , the method comprising:forming a pair of metal wires in an opening formed in a dielectric layer.2. The method of claim 1 , wherein the forming the pair of metal wires in the opening formed in the dielectric layer comprises:forming a pair of metal wires through a selective deposition technique.3. The method of claim 1 , further comprising:forming a pair of liner regions on sidewalls of the opening, the pair of liner regions being adjacent to and contacting the pair of metal wires and contacting a portion of a bottom of the opening.4. The method of claim 1 , further comprising:forming a center region in the opening, the center region located between and contacting the pair of metal wires.5. The method of claim 4 , wherein the forming the center region in the opening comprises:forming a pair of diffusion barriers on the pair of metal wires through a selective deposition technique, the pair of diffusion barriers being separated by a portion of the bottom of the opening; andforming a dielectric region on the portion of the bottom of the opening.6. The method of claim 4 , wherein the forming the center region in the opening comprises:forming a pair of diffusion barriers on the pair of metal wires through a selective deposition technique, the pair of diffusion barriers being separated by a portion of the bottom of the opening;forming a dielectric cap between an upper portion of the pair of diffusion barriers; andleaving a region below the dielectric cap unfilled to form an air-gap region defined by the portion of the bottom of the opening, the pair of diffusion barriers, and the dielectric cap.7. The method of claim 4 , wherein the forming the center region in the opening comprises ...

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Номер записи: 169
10-03-2016 дата публикации

METHODS OF FORMING GATE STRUCTURES FOR FINFET DEVICES AND THE RESULTING SEMICONDUCTOR PRODUCTS

Номер: US20160071928A1
Автор: Li Juntao, Ponoth Shom, Xie Ruilong
Принадлежит:

A transistor device includes first and second spaced-apart active regions positioned in a semiconductor substrate, each of the respective first and second spaced-apart active regions having at least one fin. First and second spaced-apart gate structures are positioned above the respective first and second active regions, each of the first and second gate structures having end surfaces. A gate separation structure is positioned between the first and second spaced-apart gate structures, wherein first and second opposing surfaces of the gate separation structure abut an entirety of the respective end surfaces of the first and second spaced-apart gate structures, and wherein an upper surface of the gate separation structure is positioned at a greater height level above the semiconductor substrate than an upper surface of the at least one fin of each of the respective first and second spaced-apart active regions. 1. A transistor device , comprising:first and second spaced-apart active regions positioned in a semiconductor substrate, each of said respective first and second spaced-apart active regions comprising at least one fin;first and second spaced-apart gate structures positioned above said respective first and second active regions, respectively, each of said first and second gate structures comprising end surfaces; anda gate separation structure positioned between said first and second spaced-apart gate structures, wherein first and second opposing surfaces of said gate separation structure abut an entirety of said respective end surfaces of said first and second spaced-apart gate structures, and wherein an upper surface of said gate separation structure is positioned at a greater height level above said semiconductor substrate than an upper surface of said at least one fin comprising each of said respective first and second spaced-apart active regions.2. The transistor device of claim 1 , wherein said upper surface of said gate separation structure is positioned ...

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Номер записи: 170
08-03-2018 дата публикации

ELECTRICAL FUSE AND/OR RESISTOR STRUCTURES

Номер: US20180068948A1
Автор: Basker Veeraraghavan S., Cheng Kangguo, Khakifirooz Ali, Li Juntao
Принадлежит:

Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material. 1. A method comprising:forming metal gates having a capping material on a top surface thereof;protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material;forming an insulator material and metal material within the recess;forming contact structures in the dielectric material between the metal gates, wherein the recess is formed as an opening in the dielectric material above the contact structures, and the opening is first filled with the metal material followed by the insulator; andforming a contact in direct electrical contact with the metal material.2. The method of claim 1 , wherein the recess is formed between the contact structures.3. The method of claim 1 , further comprising removing excess insulator material formed on the metal material outside the recess.4. The method of claim 1 , further comprising forming a pattern on the insulator material prior to forming the contact.5. A method comprising:forming metal gate structures in a dielectric material;forming a capping material over the metal gate structures;forming a mask over the capping material of the metal gate structures;recessing the dielectric material between the metal gate structures by an etching process while the mask over the capping material protects the capping material and the metal gate structures;depositing insulator material and metal material within the recess in the dielectric material;forming contact ...

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Номер записи: 171
08-03-2018 дата публикации

EXTREMELY THIN SILICON-ON-INSULATOR SILICON GERMANIUM DEVICE WITHOUT EDGE STRAIN RELAXATION

Номер: US20180069024A1
Автор: Cheng Kangguo, Li Juntao, Liu Zuoguang, Miao Xin
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium. 1. A semiconductor structure comprising:a substrate;a strained silicon germanium layer disposed on the substrate, wherein the strained silicon germanium layer is free of edge strain relaxation;a plurality of gate stacks, wherein each gate stack of the plurality of gates stacks is disposed on and in contact with a different portion of the strained silicon germanium layer;a first plurality of oxide regions within and formed from the strained silicon germanium layer; anda second plurality of oxide regions within and formed from the strained silicon germanium layer, wherein each different portion of the strained silicon germanium layer is situated between and contacts one oxide region in the first plurality of oxide regions and one oxide region in the second plurality of oxide regions.2. The semiconductor structure of claim 1 , wherein each oxide region in the first and second plurality of oxide regions comprises a portion that extends above a top surface of the strained silicon germanium layer.3. The semiconductor structure of claim 2 , wherein each oxide region in the first and second plurality of oxide regions further comprises a portion that extends laterally beyond the portion extending above the top surface of the strained silicon germanium layer.4. The semiconductor structure of claim 1 , further comprising:a buried oxide layer between the substrate and the strained silicon germanium layer.5. The semiconductor structure of ...

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Номер записи: 172
08-03-2018 дата публикации

STRAINED CMOS ON STRAIN RELAXATION BUFFER SUBSTRATE

Номер: US20180069026A1
Автор: Cheng Kangguo, Li Juntao, Pranatharthiharan Balasubramanian
Принадлежит:

A method for constructing an advanced FinFET structure is described. A first long silicon fin for n-type FinFET devices and a first long silicon germanium fin for p-type FinFET devices are provided on a strain relaxation buffer (SRB) substrate. The first long silicon fin is cut forming a first and a second cut silicon fin so that the first and second cut silicon fin have a vertical face at a fin end. The first long silicon germanium fin is cut forming a first and a second cut silicon germanium fin, the first and the second cut silicon germanium cut fin have a vertical face at a fin end. A tensile dielectric structure is formed which contacts the vertical faces of the first and second cut silicon fins to maintain tensile strain in the first and second cut silicon fins. A compressive dielectric structure is formed which contacts the vertical faces of the silicon germanium fins to maintain compressive strain in the first and second cut silicon germanium fins. 1. A method for fabricating a FinFET device comprising:providing a first long silicon fin for n-type FinFET devices and a first long silicon germanium fin for p-type FinFET devices on a strain relaxation buffer (SRB) substrate;cutting the first long silicon fin forming a first and a second cut silicon fin, each of the first and second cut silicon fins having a vertical face at a fin end of the respective cut silicon fin;cutting the first long silicon germanium fin forming a first and a second cut silicon germanium fins, each of the first and the second cut silicon germanium cut fin having a vertical face at a fin end of the respective cut silicon germanium fin;forming a tensile dielectric structure which contacts the vertical faces of the first and second cut silicon fins to maintain tensile strain in the first and second cut silicon fins; andforming a compressive dielectric structure which contacts the vertical faces of the silicon germanium fins to maintain compressive strain in the first and second cut silicon ...

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Номер записи: 173
08-03-2018 дата публикации

PREVENTING STRAINED FIN RELAXATION

Номер: US20180069027A1
Автор: Cheng Kangguo, Doris Bruce B., He Hong, Kanakasabapathy Sivananda K., Karve Gauri, Li Juntao, LIE Fee Li, Liu Derrick, Yeung Chun Wing
Принадлежит:

A semiconductor structure includes a stained fin, a gate upon the strain fin, and a spacer upon a sidewall of the gate and upon an end surface of the strained fin. The end surface of the strained fin is coplanar with a sidewall of the gate. The spacer limits relaxation of the strained fin. 1. A semiconductor structure comprising:a strained fin upon a substrate;a gate upon the substrate and upon the strained fin, wherein a sidewall of the gate is coplanar with a fin end surface of the strained fin; anda spacer upon the sidewall of the gate and upon the fin end surface of the strained fin.2. The semiconductor structure of claim 1 , wherein the spacer limits relaxation of the strained fin.3. The semiconductor structure of claim 1 , wherein the gate is an inactive gate.4. The semiconductor structure claim 1 , wherein the gate is electrically inactive.5. The semiconductor structure of claim 4 , wherein the spacer prevents epitaxial nodule growth from the fin end surface.6. The semiconductor structure of claim 1 , wherein the substrate is a multilayered substrate.7. A wafer comprising:a strained fin upon a substrate;a gate upon the substrate and upon the strained fin, wherein a sidewall of the gate is coplanar with a fin end surface of the strained fin; anda spacer upon the sidewall of the gate and upon the fin end surface of the strained fin.8. The wafer of claim 1 , wherein the spacer limits relaxation of the strained fin.9. The wafer of claim 1 , wherein the gate is an inactive gate.10. The wafer claim 1 , wherein the gate is electrically inactive.11. The wafer of claim 1 , wherein the spacer prevents epitaxial nodule growth from the fin end surface.12. The wafer of claim 1 , wherein the substrate is a multilayered substrate.13. A semiconductor structure fabrication method comprising:forming a strained fin upon a substrate;forming a gate upon the substrate and upon the strained fin, wherein a sidewall of the gate is coplanar with a fin end surface of the strained fin; ...

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Номер записи: 174
08-03-2018 дата публикации

FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR HAVING A CONSISTENT CHANNEL WIDTH

Номер: US20180069097A1
Автор: Cheng Kangguo, Li Juntao
Принадлежит:

A method of forming a vertical fin field effect transistor having a consistent channel width, including forming one or more vertical fin(s) on the substrate, wherein the one or more vertical fin(s) have a tapered profile, oxidizing the one or more vertical fin(s) to form an oxide by consuming at least a portion of the vertical fin material, and removing the oxide from the one or more vertical fin(s), wherein the one or more vertical fin(s) include a tapered upper portion, a tapered lower portion and a straight channel portion there between. 1. A method of forming a vertical fin field effect transistor having a consistent channel width , comprising:forming one or more vertical fin(s) on a substrate, wherein the one or more vertical fin(s) have a tapered profile;oxidizing the one or more vertical fin(s) to form an oxide by consuming at least a portion of the vertical fin material; andremoving the oxide from the one or more vertical fin(s), wherein the one or more vertical fin(s) include a tapered upper portion, a tapered lower portion, and a straight channel portion there between.2. The method of claim 1 , wherein oxidizing the one or more vertical fin(s) involves a thermal oxidation.3. The method of claim 1 , wherein the exposed faces of the tapered lower portion of the one or more vertical fin(s) are {111} crystal planes.4. The method of claim 1 , wherein exposed sidewalls of the straight channel portion of each of the one or more vertical fins are {110} crystal planes.5. The method of claim 1 , further comprising introducing a dopant into at least a portion of the substrate and tapered lower portion to form a bottom source/drain.6. The method of claim 1 , further comprising removing the tapered upper portion of the one or more vertical fin(s).7. The method of claim 6 , further comprising forming a top source/drain on each of the one or more vertical fins.8. The method of claim 7 , wherein the top source/drain on each of the one or more vertical fins grow together ...

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Номер записи: 175
08-03-2018 дата публикации

STRAINED CMOS ON STRAIN RELAXATION BUFFER SUBSTRATE

Номер: US20180069118A1
Автор: Cheng Kangguo, Li Juntao, Pranatharthiharan Balasubramanian
Принадлежит:

A FinFET device includes a strain relaxation buffer (SRB) substrate. A set of cut silicon fins is on the SRB substrate. Each fin in the set of cut silicon fins has a pair of long vertical faces and a pair of short vertical faces. Pairs of the cut silicon fins are oriented so that respective short vertical faces of the pair are oriented opposite to each other. A set of cut silicon germanium fins is on the SRB substrate. Each fin in the set of silicon germanium fins has a pair of long vertical faces and a pair of short vertical faces. Pairs of the cut silicon germanium fins are oriented so that respective short vertical faces of the pair are oriented opposite to each other. A set of tensile dielectric structures bridge between the short vertical faces of respective pairs of the cut silicon fins to maintain tensile strain at the fin ends of the pair of cut silicon fins. A set of compressive dielectric structures bridge between the short vertical faces of respective pairs of the cut silicon germanium fins to maintain compressive strain at the fin ends of the pair of cut silicon germanium fins. 1. A FinFET device comprising:a strain relaxation buffer (SRB) substrate;a set of cut silicon fins on the SRB substrate, each fin in the set of cut silicon fins having a pair of long vertical faces and a pair of short vertical faces, where pairs of the cut silicon fins are oriented so that respective short vertical faces of the pair are oriented opposite to each other;a set of cut silicon germanium fins on the SRB substrate, each fin in the set of silicon germanium fins having a pair of long vertical faces and a pair of short vertical faces, where pairs of the cut silicon germanium fins are oriented so that respective short vertical faces of the pair are oriented opposite to each other;a set of tensile dielectric structures, wherein respective ones of the tensile dielectric structures bridge between the short vertical faces of respective pairs of the cut silicon fins to maintain ...

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Номер записи: 176
09-03-2017 дата публикации

Formation of SiGe Nanotubes

Номер: US20170069492A1
Автор: Cheng Kangguo, He Hong, Khakifirooz Ali, Li Juntao
Принадлежит:

Techniques for forming nanostructured materials are provided. In one aspect of the invention, a method for forming nanotubes on a buried insulator includes the steps of: forming one or more fins in a SOI layer of an SOI wafer, wherein the SOI wafer has a substrate separated from the SOI layer by the buried insulator; forming a SiGe layer on the fins; annealing the SiGe layer under conditions sufficient to drive-in Ge from the SiGe layer into the fins and form a SiGe shell completely surrounding each of the fins; and removing the fins selective to the SiGe shell, wherein the SiGe shell which remains forms the nanotubes on the buried insulator. A nanotube structure and method of forming a nanotube device are also provided. 1. A method for forming nanotubes on a buried insulator , the method comprising the steps of:forming one or more fins in a silicon-on-insulator (SOI) layer of an SOI wafer, wherein the SOI wafer has a substrate separated from the SOI layer by the buried insulator;forming a silicon germanium (SiGe) layer on the fins;annealing the SiGe layer under conditions sufficient to drive-in germanium (Ge) from the SiGe layer into the fins and form a SiGe shell completely surrounding each of the fins; andremoving the fins selective to the SiGe shell, wherein the SiGe shell which remains forms the nanotubes on the buried insulator.2. The method of claim 1 , wherein the SiGe layer comprises epitaxial SiGe claim 1 , the method further comprising the step of:growing the SiGe layer on the fins.3. The method of claim 1 , wherein the conformal SiGe layer has a thickness T of from about 1 nanometers (nm) to about 100 nm claim 1 , and ranges therebetween.4. The method of claim 1 , wherein the conditions comprise a temperature of from about 400° C. to about 1200° C. claim 1 , and ranges therebetween.5. The method of claim 1 , wherein the conditions comprise a duration of from about 1 millisecond to about 60 minutes claim 1 , and ranges therebetween.6. The method of claim ...

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Номер записи: 177
27-02-2020 дата публикации

SELF-ALIGNED VERTICAL FIN FIELD EFFECT TRANSISTOR WITH REPLACEMENT GATE STRUCTURE

Номер: US20200066599A1
Автор: Cheng Kangguo, Li Juntao, Miao Xin, Yamashita Tenko, Zhang Chen
Принадлежит:

A method of forming a vertical field effect transistor device is provided. The method includes forming one or more fin stacks on a substrate, wherein the fin stacks include a lower junction plate, a vertical fin on the top surface of the lower junction plate, and an upper junction plate on the top surface of the vertical fin. The method further includes removing a portion of the lower junction plate and upper junction plate to form recessed spaces, and forming an inner spacer in the recessed spaces. The method further includes forming a sacrificial layer on the exposed surfaces of the vertical fin and the substrate. The method further includes forming a protective liner on the sacrificial layer and inner spacers, and removing the portion of the sacrificial layer on the surface of the substrate to leave a hanging portion of the protective liner extending below the inner spacer. 1. A method of forming a vertical field effect transistor device , comprising:forming one or more fin stacks on a substrate, wherein the fin stacks include a lower junction plate, a vertical fin on the top surface of the lower junction plate, and an upper junction plate on the top surface of the vertical fin;removing a portion of the lower junction plate and upper junction plate to form recessed spaces;forming an inner spacer in the recessed spaces;forming a sacrificial layer on the exposed surfaces of the vertical fin and the substrate;forming a protective liner on the sacrificial layer and inner spacers; andremoving the portion of the sacrificial layer on the surface of the substrate to leave a hanging portion of the protective liner extending below the inner spacer.2. The method of claim 1 , wherein a supporting pillar is formed underneath the fin stack by recessing the substrate.3. The method of claim 2 , further comprising removing the protective liner.4. The method of claim 3 , further comprising forming a doped layer adjacent to the supporting pillar.5. The method of claim 4 , further ...

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Номер записи: 178
27-02-2020 дата публикации

RRAM CELLS IN CROSSBAR ARRAY ARCHITECTURE

Номер: US20200066797A1
Автор: Ando Takashi, Cheng Kangguo, Kong Dexin, Li Juntao
Принадлежит:

A method is presented for forming vertical crossbar resistive random access memory (RRAM) cells. The method includes forming a substantially U-shaped bottom electrode over a substrate, filling the U-shaped bottom electrode with a first conductive material, capping the U-shaped bottom electrode with a dielectric cap, depositing a high-k material, and forming a top electrode such that active areas of the RRAM cells are vertically aligned and the U-shaped bottom electrode is shared between neighboring RRAM cells. 1. A method for forming vertical crossbar resistive random access memory (RRAM) cells , the method comprising:forming a substantially U-shaped bottom electrode over a substrate;filling the U-shaped bottom electrode with a first conductive material; andforming a top electrode such that active areas of the RRAM cells are vertically aligned.2. The method of claim 1 , further comprising capping the U-shaped bottom electrode with a dielectric cap.3. The method of claim 2 , further comprising depositing a high-k material after forming the dielectric cap.4. The method of claim 3 , wherein the U-shaped bottom electrode is shared between neighboring RRAM cells.5. The method of claim 4 , further comprising claim 4 , before forming the U-shaped bottom electrode:forming a plurality of dielectric pillars over the substrate;forming a dielectric layer over the plurality of dielectric pillars; andetching the dielectric layer to form dielectric regions between the plurality of dielectric pillars.6. The method of claim 5 , further comprising claim 5 , after forming the U-shaped bottom electrode claim 5 , removing the dielectric pillars to form recesses.7. The method of claim 6 , further comprising filling the recesses with a second conductive material.8. The method of claim 7 , further comprising forming first vias in direct contact with the second conductive material.9. The method of claim 8 , further comprising forming second vias between the substrate and the U-shaped bottom ...

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Номер записи: 179
27-02-2020 дата публикации

RRAM CELLS IN CROSSBAR ARRAY ARCHITECTURE

Номер: US20200066798A1
Автор: Ando Takashi, Cheng Kangguo, Kong Dexin, Li Juntao
Принадлежит:

A method is presented for forming vertical crossbar resistive random access memory (RRAM) cells. The method includes forming a substantially U-shaped bottom electrode over a substrate, filling the U-shaped bottom electrode with a first conductive material, capping the U-shaped bottom electrode with a dielectric cap, depositing a high-k material, and forming a top electrode such that active areas of the RRAM cells are vertically aligned and the U-shaped bottom electrode is shared between neighboring RRAM cells. 1. A semiconductor structure for forming vertical crossbar resistive random access memory (RRAM) cells , the semiconductor structure comprising:a substantially U-shaped bottom electrode disposed over a substrate;a conductive material disposed within the U-shaped bottom electrode;a dielectric cap disposed over the U-shaped bottom electrode;a high-k material disposed adjacent the U-shaped bottom electrode and the dielectric cap; anda top electrode constructed such that active areas of the RRAM cells are vertically aligned.2. The semiconductor structure of claim 1 , wherein the U-shaped bottom electrode is shared between neighboring RRAM cells.3. The semiconductor structure of claim 1 , wherein the high-k material includes titanium nitride (TiN).4. The semiconductor structure of claim 1 , wherein the top electrode includes TiN/aluminum (Al)-containing alloy/TiN.5. The semiconductor structure of claim 1 , wherein the bottom electrode includes TiN.6. The semiconductor structure of claim 1 , wherein first vias are constructed between the substrate and the U-shaped bottom electrode.7. The semiconductor structure of claim 1 , wherein conductive regions are constructed adjacent opposed ends of the U-shaped bottom electrode.8. The semiconductor structure of claim 7 , wherein second vias are constructed over the conductive regions.9. The semiconductor structure of claim 8 , wherein the first vias are vertically offset from the second vias.10. The semiconductor structure ...

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Номер записи: 180
27-02-2020 дата публикации

METHOD AND STRUCTURE FOR FORMING A VERTICAL FIELD-EFFECT TRANSISTOR

Номер: US20200066881A1
Автор: Cheng Kangguo, Lee Choonghyun, Li Juntao, Xu Peng
Принадлежит:

A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a second semiconductor layer including a first concentration of germanium on the first semiconductor layer, and forming a third semiconductor layer on the second semiconductor layer. The first and third semiconductor layers each have a concentration of germanium, which is greater than the first concentration of germanium. The first, second and third semiconductor layers are patterned into at least one fin. The method further includes covering the second semiconductor layer with a mask layer. In the method, a bottom source/drain region and a top source/drain region are simultaneously grown from the first semiconductor layer and the third semiconductor layer, respectively. The mask layer is removed from the second semiconductor layer, and a gate structure is formed on and around the second semiconductor layer. 1. A vertical field-effect transistor device , comprising:at least one fin disposed on a semiconductor substrate, wherein the at least one fin comprises a semiconductor channel layer comprising a first concentration of germanium;a bottom source/drain region adjacent a lower portion of the at least one fin;a top source/drain region above the semiconductor channel layer; anda gate structure between the top and bottom source/drain regions;wherein the top and bottom source/drain regions each comprise a concentration of germanium which is greater than the first concentration of germanium; andwherein the gate structure is aligned with the top source/drain region.2. The vertical field-effect transistor device according to claim 1 , wherein upper surfaces of the gate structure have an orientation that conforms to an orientation of bottom sides of the top source/drain region.3. The vertical field-effect transistor device according to claim 2 , wherein upper surfaces of the gate structure are parallel to the bottom sides of the top source/ ...

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Номер записи: 181
27-02-2020 дата публикации

CLOSELY PACKED VERTICAL TRANSISTORS WITH REDUCED CONTACT RESISTANCE

Номер: US20200066882A1
Автор: Bi Zhenxing, Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит:

A method of forming a semiconductor device and resulting structures having closely packed vertical transistors with reduced contact resistance by forming a semiconductor structure on a doped region of a substrate, the semiconductor structure including a gate formed over a channel region of a semiconductor fin. A liner is formed on the gate and the semiconductor fin, and a dielectric layer is formed on the liner. Portions of the liner are removed to expose a top surface and sidewalls of the semiconductor fin and a sidewall of the dielectric layer. A recessed opening is formed by recessing portions of the liner from the exposed sidewall of the dielectric layer. A top epitaxy region is formed on the exposed portions of the semiconductor fin and dielectric layer such that an extension of the top epitaxy region fills the recessed opening. The top epitaxy region is confined between portions of the liner. 1. A method for fabricating a semiconductor device , the method comprising:forming a vertical semiconductor structure on a bottom doped region of a substrate, the vertical semiconductor structure comprising a gate formed over a channel region of a semiconductor fin, the gate between a bottom spacer and a top spacer;forming a conformal liner on a surface of the bottom spacer, on a sidewall of the gate, and on a top surface of the top spacer;forming a top epitaxy region on a surface of the semiconductor fin and the top surface of the top spacer, the top epitaxy region confined between portions of the liner;forming a first contact on a surface of the bottom doped region, the first contact prevented from electrically shorting to the gate by portions of the liner formed between the first contact and the semiconductor structure; andforming a second contact wrapping around a top surface and a sidewall of the top epitaxy region, said second contact prevented from electrically shorting to the gate by portions of the liner formed between the second contact and the semiconductor ...

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Номер записи: 182
15-03-2018 дата публикации

METHOD AND STRUCTURE FOR FORMING A DENSE ARRAY OF SINGLE CRYSTALLINE SEMICONDUCTOR NANOCRYSTALS

Номер: US20180076029A1
Автор: Cheng Kangguo, He Hong, Li Juntao
Принадлежит:

A dense array of semiconductor single crystalline semiconductor nanocrystals is provided in the present application by forming an amorphous semiconductor material layer surrounding a plurality of patterned nanostructures comprised of a single crystalline semiconductor material portion. A thermal anneal, i.e., (solid phase epitaxy), is then performed to crystallize a portion of the amorphous semiconductor material layer that is in contact with each single crystalline semiconductor material portion and to provide a plurality of spaced apart single crystalline nanocrystals on a surface of an insulator. A remaining portion of the amorphous semiconductor material layer that was not crystallized is thereafter removed. 1. A semiconductor structure comprising:a plurality of single crystalline semiconductor nanocrystals located on a mesa structure of an insulator layer portion, said insulator layer portion having an undulating surface and wherein a portion of said mesa structure protrudes into a portion of each of said single crystalline semiconductor nanocrystals.2. The semiconductor structure of claim 1 , wherein each single crystalline semiconductor nanocrystal is a nanoball.3. The semiconductor structure of claim 1 , wherein each single crystalline semiconductor nanocrystal is a nanorod.4. The semiconductor structure of claim 1 , wherein each single crystalline semiconductor nanocrystal has a diameter of less than 20 nm.5. The semiconductor structure of claim 1 , wherein each single crystalline semiconductor nanocrystal is spaced apart for its nearest neighboring single crystalline semiconductor nanocrystal by a distance of 20 nm or less.6. The semiconductor structure of claim 1 , wherein each single crystalline semiconductor nanocrystal comprises a single semiconductor material.7. The semiconductor structure of claim 1 , wherein each single crystalline semiconductor nanocrystal comprises a core of a first semiconductor material and a shell of a second semiconductor ...

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Номер записи: 183
16-03-2017 дата публикации

Porous silicon relaxation medium for dislocation free cmos devices

Номер: US20170076998A1
Автор: Devendra K. Sadana, Jeehwan Kim, Juntao Li, Kangguo Cheng, Ramachandra Divakaruni
Принадлежит: International Business Machines Corp

A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.

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Номер записи: 184
05-03-2020 дата публикации

IFINFET

Номер: US20200075721A1
Автор: Cheng Kangguo, Li Juntao, Miao Xin, Zhang Chen
Принадлежит:

A technique relates to a semiconductor device. A stack includes two or more nanowires separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanowires in the stack. A separation space between the two or more nanowires is less than two times a thickness of the high-k dielectric material formed on a side wall of the two or more nanowires. A source or a drain formed on sides of the stack. 1. A semiconductor device comprising:a stack comprising two or more nanowires separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanowires in the stack, wherein a separation space between the two or more nanowires is less than two times a thickness of the high-k dielectric material formed on a side wall of the two or more nanowires; anda source or a drain formed on sides of the stack.2. The semiconductor device of claim 1 , wherein the high-k dielectric material is continuous between the two or more nanowires at least at the center portion of the two or more nanowires.3. The semiconductor device of claim 2 , wherein the high-k dielectric material is continuous means that the high-k dielectric material is in direct contact with an upper nanowire and a bottom nanowire of the two or more nanowires.4. The semiconductor device of claim 1 , wherein the stack comprises an inner spacer.5. The semiconductor device of claim 4 , wherein the inner spacer is formed on side portions of the high-k dielectric material in the stack.6. The semiconductor device of claim 5 , wherein the source or the drain is adjacent to the inner spacer formed on the side portions of the high-k dielectric material.7. The semiconductor device of further comprising a metal gate formed on a top one of the two or more nanowires.8. The semiconductor device of claim 1 , wherein the high-k dielectric material is formed on top of a top one of the two or more ...

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Номер записи: 185
05-03-2020 дата публикации

VERTICAL TRANSPORT FET DEVICES HAVING A SACRIFICIAL DOPED LAYER

Номер: US20200075747A1
Автор: Cheng Kangguo, Lee Choonghyun, Li Juntao, Mochizuki Shogo
Принадлежит:

Methods of fabrication and semiconductor structures includes vertical transport field effect transistors (VTFETs) including a top source/drain extension formed with a sacrificial doped layer. The sacrificial doped layer provides the doping source to form the extension and protects the top of the fin during fabrication so as to prevent thinning, among other advantages. 1. A method of forming one or more vertical field effect transistors comprising:forming one or more vertical fin channels in a silicon substrate comprising thereon an epitaxially grown undoped silicon-germanium layer and a doped epitaxially grown silicon layer on the undoped silicon germanium layer;epitaxially growing a bottom source/drain adjacent each of the one or more vertical fin channels;diffusing dopant ions from the bottom source/drain region into each lower portion of the one or more vertical fin channels to form a doped bottom portion and diffusing dopant ions from the doped epitaxially grown silicon layer into each top portion of the one or more vertical fin channels to form a doped top portion;forming a gate structure about each of the one or more vertical fin channels;depositing an interlayer dielectric;patterning the interlayer dielectric and removing the doped epitaxially grown silicon layer and the epitaxially grown undoped silicon-germanium layer from the one or more vertical fin channels; andepitaxially growing a top source/drain on the doped top portion of each of the one or more vertical fin channels to define the one or more vertical field effect transistors.2. The method of claim 1 , wherein diffusing the dopant ions to form the top and bottom doped portions in each of the one or more vertical fin channels comprises a high temperature annealing process at a temperature effective to drive in the dopant ions from the sacrificial dopant layer to the top portion and drive in dopants from the bottom source/drain region to the bottom portion.3. The method of claim 1 , wherein the ...

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Номер записи: 186
18-03-2021 дата публикации

BACK END OF LINE STRUCTURES WITH METAL LINES WITH ALTERNATING PATTERNING AND METALLIZATION SCHEMES

Номер: US20210082714A1
Автор: Cheng Kangguo, Li Juntao, Park Chanro, Xie Ruilong, Yang Chih-Chao
Принадлежит:

Techniques are provided to fabricate semiconductor devices. For example, a method includes forming an interconnect structure having a base, a first conductive metal layer disposed on the base; and a first hardmask layer disposed on the first conductive metal layer. Metal lines are formed by subtractive etching. The metal lines have negative tapered sidewalk, and an opening is formed between adjacent metal lines. A first interlevel dielectric layer is deposited in the openings. A portion of the first interlevel dielectric layer is removed to form trench openings having positive tapered sidewalls. A dielectric layer is deposited in one of the openings. A liner layer and a second conducting metal layer are deposited in the other trench openings. The liner layer and the second conductive metal layer are recessed. A second hardmask layer is deposited on a top surface of the liner layer and the second conductive metal layer. 1. A method comprising:forming an interconnect structure comprising a base, a first conductive metal layer disposed on the base, and a first hardmask layer disposed on the first conductive metal layer;forming metal lines by patterning the first hardmask layer and the first conductive metal layer above the base by subtractive etching, wherein the metal lines have negative tapered sidewalls, and further wherein an opening is formed between adjacent metal lines;depositing a first interlevel dielectric layer in the opening between the adjacent metal lines;removing a portion of the first interlevel dielectric layer to form trench openings having positive tapered sidewalls;depositing a dielectric layer in a trench opening;depositing a liner layer on the exterior surfaces of the other trench openings;depositing a second conductive metal layer on the liner layer;recessing the liner layer and the second conductive metal layer; anddepositing a second hardmask layer on a top surface of the liner layer and the second conductive metal layer.2. The method of claim ...

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Номер записи: 187
18-03-2021 дата публикации

VERTICAL METAL-AIR TRANSISTOR

Номер: US20210083075A1
Автор: Cheng Kangguo, Li Juntao, Park Chanro, Xie Ruilong
Принадлежит:

A method of forming a vertical metal-air transistor device is provided. The method includes forming a precursor stack with a stack template on the precursor stack on a substrate. The method further includes forming a bottom spacer on the substrate around the precursor stack, and depositing a liner casing on the precursor stack. The method further includes depositing a conductive gate layer on the bottom spacer and liner casing. The method further includes reducing the size of the stack template to form a template post on the precursor stack, and forming a stack cap on the template post and precursor stack. 1. A method of forming a vertical metal-air transistor device , comprising:forming a precursor stack with a stack template on the precursor stack on a substrate;forming a bottom spacer on the substrate around the precursor stack;depositing a liner casing on the precursor stack;depositing a conductive gate layer on the bottom spacer and liner casing;reducing the size of the stack template to form a template post on the precursor stack; andforming a stack cap on the template post and precursor stack.2. The method of claim 1 , further comprising forming an interlayer dielectric (ILD) layer on the stack cap.3. The method of claim 2 , further comprising removing the template post to form a cavity in the stack cap that exposes a portion of a top surface of the precursor stack.4. The method of claim 3 , wherein the precursor stack includes an upper electrode column claim 3 , a lower electrode column claim 3 , and a graphene plate between the upper electrode column and lower electrode column.5. The method of claim 4 , further comprising extending the cavity through the upper electrode column claim 4 , graphene plate claim 4 , and lower electrode column to form an upper electrode annulus claim 4 , graphene ring claim 4 , and lower electrode annulus.6. The method of claim 5 , further comprising removing the graphene ring to form an interstice between the upper electrode ...

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Номер записи: 188
26-03-2015 дата публикации

Raised Source/Drain and Gate Portion with Dielectric Spacer or Air Gap Spacer

Номер: US20150087120A1
Автор: Adam Thomas N., Cheng Kangguo, Khakifirooz Ali, Li Juntao, Reznicek Alexander
Принадлежит:

A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes epitaxial raised source/drain (RSD) regions formed on the surface of a semiconductor substrate through selective epitaxial growth. In one embodiment, the faceted side portions of the RSD regions are utilized to form cavity regions which may be filled with a dielectric material to form dielectric spacer regions. Spacers may be formed over the dielectric spacer regions. In another embodiment, the faceted side portions may be selectively grown to form air gap spacer regions in the cavity regions. A conformal spacer layer with interior and exterior surfaces may be formed in the cavity region, creating an air gap spacer defined by the interior surfaces of the conformal spacer layer. 1. A method of forming a semiconductor device , the method comprising:forming a gate portion on a surface of a semiconductor substrate, the gate portion having gate sidewalls;forming gate spacers on the gate sidewalls and on the surface of the semiconductor substrate, the gate spacers having first sidewalls;forming raised source/drain (RSD) regions on the surface of the semiconductor substrate, the RSD regions having a faceted side portion contacting the gate spacers at the surface of the semiconductor substrate, thereby forming cavity regions defined by the gate sidewalls and the faceted side portion of the RSD regions;filling the cavity regions with a dielectric material, thereby forming dielectric regions; andforming second spacers on the first sidewalls and on a top surface of the dielectric regions, the second spacers having second sidewalls.2. The method of claim 1 , further comprising forming a silicide layer on an upper surface of the RSD regions claim 1 , the silicide layer contacting the second sidewalls.3. The method of claim 1 , wherein the forming RSD regions comprises selectively growing the faceted side portion to rise in a direction normal to the surface of the ...

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Номер записи: 189
22-03-2018 дата публикации

TRENCH CONTACT RESISTANCE REDUCTION

Номер: US20180082950A1
Автор: Bi Zhenxing, Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит:

A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer over the source/drain, and forming an inter-level dielectric (ILD) layer over the sacrificial layer. The method further includes forming trenches that extend partially into the sacrificial layer, removing the sacrificial layer to expose an upper surface of the source/drain, and filling the trenches with at least one conducting material. The sacrificial layer is germanium (Ge) and the at least one conducting material includes three conducting materials. 1. A semiconductor device , comprising:source/drain formed over a semiconductor substrate;an inter-level dielectric (ILD) layer formed over the source/drain; anda first portion of trenches that extend partially through the ILD layer at a non-perpendicular angle with respect to the semiconductor substrate;wherein an upper surface of the source/drain is exposed to create a second portion of the trenches which extends laterally beyond sidewalls of the first portion of the trenches; andwherein the trenches are filled with a plurality of conducting materials each extending entirely within the second portion of the trenches.2. The device of claim 1 , wherein a gate structure is formed on the semiconductor substrate.3. The device of claim 2 , wherein spacers are formed adjacent the gate structure.4. The device of claim 3 , wherein the trenches run transversely to a longitudinal axis of the gate structure.5. (canceled)6. (canceled)7. The device of claim 1 , wherein the plurality of conducting materials cover an entire upper surface of the source/drain.8. The device of claim 1 , wherein the plurality of conducting materials are three conducting materials.9. The device of claim 8 , wherein the first conducting material is titanium (Ti) claim 8 , the second conducting material is titanium nitride (TiN) claim 8 , and the third conducting material is Tungsten (W).10. The ...

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Номер записи: 190
22-03-2018 дата публикации

CONTACT HAVING SELF-ALIGNED AIR GAP SPACERS

Номер: US20180082951A1
Автор: Li Juntao, Wang Junli, Yang Chih-Chao
Принадлежит:

A semiconductor device includes a semiconductor substrate, and a dielectric layer on an upper surface of the semiconductor substrate. A contact stack is formed in the dielectric layer. The contact stack includes an electrically conductive contact element, and a contact liner on first and second opposing sidewalls of the contact element. A first air gap is interposed between the dielectric layer and the contact liner on the first side wall, and a second air gap interposed between the dielectric layer and the contact liner on the second side wall. 1. A semiconductor device , comprising;a semiconductor substrate;a dielectric layer on an upper surface of the semiconductor substrate;at least one contact stack formed in the dielectric layer, the at least one contact stack including an electrically conductive contact element and a contact liner on first and second opposing sidewalls of the contact element; anda first air gap interposed between the dielectric layer and the contact liner on the first side wall, and a second air gap interposed between the dielectric layer and the contact liner on the second side wall.2. The semiconductor device of claim 1 , wherein the contact liner comprises titanium.3. The semiconductor device of claim 2 , wherein a width of the first and second air gaps is substantially equal to a width of the contact liner.4. The semiconductor device of claim 2 , wherein a width of the first and second air gaps is greater than a width of the contact liner.5. The semiconductor device of claim 2 , wherein the contact element comprises a metal.6. The semiconductor device of claim 5 , wherein the contact element comprises tungsten.7. The semiconductor device of claim 2 , wherein the at least one least one contact stack includes a plurality of contact stacks claim 2 , each contact stack separated from one another by a portion of the dielectric layer.8. The semiconductor device of claim 7 , wherein the plurality of contact stacks includes a first contact stack ...

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Номер записи: 191
22-03-2018 дата публикации

TRENCH CONTACT RESISTANCE REDUCTION

Номер: US20180082953A1
Автор: Bi Zhenxing, Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит:

A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer over the source/drain, and forming an inter-level dielectric (ILD) layer over the sacrificial layer. The method further includes forming trenches that extend partially into the sacrificial layer, removing the sacrificial layer to expose an upper surface of the source/drain, and filling the trenches with at least one conducting material. The sacrificial layer is germanium (Ge) and the at least one conducting material includes three conducting materials. 1. A method of forming a semiconductor device , the method comprising:forming a source/drain over a semiconductor substrate;forming a single sacrificial layer directly in contact with the source/drain;forming an inter-level dielectric (ILD) layer contacting the single sacrificial layer;forming a first portion of trenches that extend through the ILD layer at an oblique angle with respect to the semiconductor substrate, and into a first section of the single sacrificial layer such that the single sacrificial layer remains in contact with an entire upper surface of the source/drain;removing a second section of the single sacrificial layer to expose the entire upper surface of the source/drain and to create a second portion of the trenches which extends laterally beyond sidewalls of the first portion of the trenches; andfilling the first and second portions of the trenches with one or more a plurality of conducting materials each extending entirely within the second onion of the trenches.2. The method of claim further comprising forming a gate structure on the semiconductor substrate.3. The method of claim 2 , further comprising forming spacers adjacent the gate structure.4. The method of claim 3 , wherein the trenches run transversely to a longitudinal axis of the gate structure.5. The method of claim 1 , wherein the sacrificial layer is germanium (Ge).6. The ...

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Номер записи: 192
22-03-2018 дата публикации

NANOSHEET CAPACITOR

Номер: US20180083046A1
Автор: Cheng Kangguo, Li Juntao, Wang Geng, Zhang Qintao
Принадлежит:

Embodiments are directed to a method of forming a semiconductor device and resulting structures having a nanosheet capacitor by forming a first nanosheet stack over a substrate. The first nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. A second nanosheet stack is formed over the substrate adjacent to the first nanosheet stack. The second nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. Exposed portions of the first and second nanosheets of the second nanosheet stack are doped and gates are formed over channel regions of the first and second nanosheet stacks. 1. A semiconductor device comprising:a nanosheet stack formed over a substrate, the nanosheet stack comprising a first nanosheet vertically stacked over a second nanosheet;a first source or drain region adjacent to a first end of the nanosheet stack;a second source or drain region adjacent to a second end of the nanosheet stack, the first and second ends on opposite sides of the nanosheet stack;a dopant formed in a channel region of the first and second nanosheets of the nanosheet stack; anda gate formed over the channel region of the first and second nanosheets of the nanosheet stack:,wherein the first source or drain region, the second source or drain region, and the first and second nanosheets comprise a same doping type; andwherein the first and second nanosheets are sufficiently doped such that the first and second nanosheets act as a single electrode between the first and second source or drain regions.2. (canceled)3. The semiconductor device of claim 1 , wherein the first and second source or drain regions are n-type doped regions and the dopant comprises an n-type dopant.4. The semiconductor device of claim 3 , wherein the n-type dopant is selected from the group consisting of phosphorus and arsenic.5. The semiconductor device of claim 1 , wherein the first and second source or drain regions are p-type doped regions and the ...

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Номер записи: 193
02-04-2015 дата публикации

Self-aligned vias formed using sacrificial metal caps

Номер: US20150091181A1
Автор: Chih-Chao Yang, Juntao Li, Yunpeng Yin
Принадлежит: International Business Machines Corp

A method including forming a sacrificial metal cap on a metal line formed in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; removing the sacrificial metal cap selective to the second dielectric layer and metal line to form a cap opening; forming a dielectric cap in the cap opening and on the metal line; forming an interconnect dielectric layer over the dielectric cap and the second dielectric layer; forming an interconnect opening in the interconnect dielectric layer; removing a portion of the dielectric cap exposed by the interconnect opening selective to the interconnect dielectric layer, the second dielectric layer, and the metal line; and forming an interconnect structure in the interconnect opening, the interconnect structure comprising a contact line above a via, the via having an upper via portion with angled sidewalls and a lower via portion with substantially vertical sidewalls.

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Номер записи: 194
12-03-2020 дата публикации

METHOD AND STRUCTURE FOR FORMING VERTICAL TRANSISTORS WITH SHARED GATES AND SEPARATE GATES

Номер: US20200083111A1
Автор: Bi Zhenxing, Cheng Kangguo, Li Juntao, Xu Peng
Принадлежит:

A method for manufacturing a semiconductor device includes forming a fin on a substrate, removing one or more portions of the fin prior to forming a gate structure on the fin, forming the gate structure on the fin, and simultaneously removing one or more additional portions of the fin and one or more portions of the gate structure aligned with the one or more additional portions of the fin to create a fin edge portion aligned with a gate structure edge portion. 1. A semiconductor device , comprising:a first vertical transistor on a substrate;a second vertical transistor positioned adjacent the first vertical transistor on the substrate, wherein the first and second vertical transistors respectively comprise first and second fins; anda shared gate structure formed around the first and second fins.2. The semiconductor device according to claim 1 , wherein the first and second fins respectively comprise first and second edges positioned opposite and spaced apart from each other claim 1 , and wherein the shared gate structure extends between the first and second edges.3. The semiconductor device according to claim 2 , further comprising a contact formed on the shared gate structure between the first and second edges.4. The semiconductor device according to claim 3 , further comprising a dielectric layer formed on the shared gate structure between the first and second edges.5. The semiconductor device according to claim 4 , wherein the contact is formed through the dielectric layer.6. The semiconductor device according to claim 2 , wherein the first and second fins respectively comprise third and fourth edges respectively aligned with first and second edges of the shared gate structure.7. The semiconductor device according to claim 6 , wherein:the first and second fins each comprise a bottom source/drain region and a top source/drain region;edges of the bottom and top source/drain regions of the first fin are aligned with the first edge of the shared gate structure in ...

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Номер записи: 195