Gepackte Halbleitervorrichtung und Verfahren zum Packen der Halbleitervorrichtung

Mechanismen zum Ausbilden einer Formmasse auf einem Halbleitervorrichtungssubstrat zum Ermöglichen von Fan-Out-Strukturen beim Wafer-Level-Packaging (WLP) werden bereitgestellt. Die Mechanismen umfassen das Bedecken von Abschnitten von Oberflächen einer Isolierschicht, die ein Kontaktpad umgibt. Die Mechanismen verbessern die Zuverlässigkeit der Packung und der Prozesssteuerung des Packprozesses. Die Mechanismen reduzieren außerdem das Risiko von Delaminieren an Grenzflächen und übermäßiges Ausgasen der Isolierschicht während nachfolgender Verarbeitung. Die Mechanismen verbessern ferner den Endpunkt einer Planarisierung. Durch Verwenden einer Schutzschicht zwischen dem Kontaktpad und der Isolierschicht kann Kupferaußendiffusion reduziert werden, und die Haftung zwischen dem Kontaktpad und der Isolierschicht kann ebenfalls verbessert werden.

Multichip-Montageeinheit mit einem Substrat mit mehreren vertikal eingebetteten Plättchen und Verfahren zur Herstellung derselben

Eine Vorrichtung umfasst ein Substrat, welches eine Anschlussfleckseite mit mehreren Kontaktflecken und eine Plättchenseite gegenüber der Anschlussfleckseite aufweist. Die Vorrichtung umfasst ein erstes Plättchen und ein zweites Plättchen, wobei das erste Plättchen und das zweite Plättchen derart in das Substrat eingebettet sind, dass das zweite Plättchen zwischen dem ersten Plättchen und der Anschlussfleckseite des Substrats angeordnet ist.

Bondhügellose Aufbauschicht- und Laminatkernhybridstrukturen und Verfahren für ihre Montage

Eine Struktur enthält ein Hybridsubstrat zum Stützen eines Halbleiterbauelements, das eine bondhügellose Aufbauschicht, in die das Halbleiterbauelement eingebettet ist, und eine Laminatkernstruktur enthält. Die bondhügellose Aufbauschicht und die Laminatkernstruktur werden durch eine Verstärkungsplattierung, die mit einem plattierten Durchgangsloch in der Laminatkernstruktur und einer anschließenden Bondinsel der bondhügellosen Aufbauschichtstruktur verbunden ist, zu einer integralen Vorrichtung gemacht.

MIKROELEKTRONISCHE ANORDNUNGEN

Mikroelektronische Anordnungen und damit verbundene Vorrichtungen und Verfahren werden hierin offenbart. Beispielsweise kann bei einigen Ausführungsbeispielen eine mikroelektronische Anordnung einen ersten Die umfassen, der eine erste Fläche und eine zweite Fläche aufweist; und einen zweiten Die, der zweite Die umfassend eine erste Fläche und eine zweite Fläche, wobei der zweite Die ferner eine Mehrzahl von ersten leitfähigen Kontakten an der ersten Fläche und eine Mehrzahl von zweiten leitfähigen Kontakten an der zweiten Fläche umfasst und der zweite Die zwischen Erste-Ebene-Verbindungskontakten der mikroelektronischen Anordnung und dem ersten Die ist.

Verpackungsstruktur für elektronische Bauteile und Methode zu deren Herstellung

Verfahren zur Herstellung eines elektronischen Bauelements und elektronisches Bauelement

Die Anmeldung betrifft ein Verfahren zur Herstellung eines elektronischen Bauelements (2). Bei dem vorgeschlagenen Verfahren wird zunächst eine Passivierungsschicht (3), die ein Polymer aufweist, auf einen Träger (1) aufgebracht. Anschließend wird ein Halbleiterchip (5) auf der Passivierungsschicht (3) so angeordnet, dass elektrisch aktive Bereiche des Halbleiterchips (5) der Passivierungsschicht (3) zugewandt sind. In einem weiteren Schritt wird der Halbleiterchip (5) mit der Passivierungsschicht (3) durch ein Aushärten des Polymers stoffschlüssig verbunden zum Fixieren des Halbleiterchips (5) auf der Passivierungsschicht (3). Daraufhin wird der Halbleiterchip (5) in eine Vergussmasse (8) vergossen. In einem weiteren Schritt wird eine Umverdrahtungslage (15) hergestellt, welche die Passivierungsschicht (3) und Leiterbahnen (14) umfasst. Dieser Schritt kann vor dem Anordnen des Halbleiterchips (15) auf der Passivierungsschicht (3) oder nach dem Vergießen des Halbleiterchips (5) durchgeführt ...

Chipmodul und Verfahren zur Bereitstellung eines Chipmoduls

Chipmodul (20), das einen Halbleiter-Die (2) umfasst, der in ein Leiterplattensubstrat (PCB-Substrat) (10) eingebettet ist, wobei der Die (2) eine Rückseite (16) und eine aktive Vorderseite, die mehrere Kontaktflächen (4) umfasst, aufweist, wobei die Rückseite (16) des Dies (2) durch eine Wärmebrücke (24, 38) mit einer Oberfläche (29) des Chipmoduls (20) gekoppelt ist, wobei wenigstens ein Abschnitt der Rückseite des Dies (2) mit einer gut wärmeleitenden und strukturierten Beschichtung (18) beschichtet ist und ein Innenendabschnitt der Wärmebrücke (24, 38) an die Beschichtung (18) angrenzt.

HALBLEITERBAUELEMENT UND HERSTELLUNGSVERFAHREN

Ein integriertes Fan-Out-Package wird eingesetzt, wobei die dielektrischen Materialien unterschiedlicher Umverteilungsschichten eingesetzt werden, um die integrierten Fan-Out-Package-Prozessflüsse mit anderen Package-Anwendungen zu integrieren. Bei einigen Ausführungsformen wird eine Ajinomoto-Aufbaufolie oder ein Prepreg-Material als das Dielektrikum in mindestens einigen der überlagerten Umverteilungsschichten eingesetzt.

Elektronisches Bauelement, Anordnung und Verfahren

Elektronisches Bauelement (150, 200, 250, 260, 300), umfassend:mindestens ein Halbleiterbauelement (151, 201, 261, 301) mit einer ersten Seite, einer der ersten Seite gegenüberliegenden zweiten Seite), einer auf der ersten Seite angeordneten ersten Elektrode (162) und einer auf der zweiten Seite angeordneten zweiten Elektrode (164); undeine Verteilerplatine (152, 202, 263, 304), die mindestens zwei nicht leitende Schichten (153, 154, 155, 156) und eine leitende Verteilerstruktur (157) umfasst,wobei das Halbleiterbauelement (151) in die Verteilerplatine (152, 202, 263, 304) eingebettet und mit der Verteilerstruktur (157) elektrisch verbunden ist, wobei die Verteilerplatine (152, 202, 263, 304) zumindest eine an einer Seitenfläche (167) ausgebildete Stufe aufweist, wobei von der ersten Elektrode (162) und der zweiten Elektrode (164) eine jede an einer Stufe elektrisch kontaktierbar ist; und wobei auf einer Stufe eine äußere Kontaktfläche (179) der Verteilerstruktur (157) angeordnet ist.

DIE-GEHÄUSE UND VERFAHREN ZUM BILDEN EINES DIE-GEHÄUSES

Ein Die-Gehäuse ist bereitgestellt. Das Die-Gehäuse kann Folgendes beinhalten: einen Die mit einem ersten Die-Kontakt auf einer ersten Seite des Die und einem zweiten Die-Kontakt auf einer zweiten Seite des Die, die der ersten Seite des Die gegenüberliegt, ein Isolationsmaterial, das lateral dem Die benachbart ist, eine Metallstruktur, die die gesamte Oberfläche des zweiten Die-Kontakts des Die im Wesentlichen direkt kontaktiert, wobei die Metallstruktur aus dem gleichen Material wie der zweite Die-Kontakt gefertigt ist, einen ersten Padkontakt auf der ersten Seite des Die, der den ersten Die-Kontakt elektrisch kontaktiert, und einen zweiten Padkontakt auf der ersten Seite des Die, der den zweiten Die-Kontakt über die Metallstruktur elektrisch kontaktiert, wobei das Isolationsmaterial die Metallstruktur elektrisch von dem ersten Die-Kontakt isoliert.

HALBLEITER-BAUELEMENT UND VERFAHREN ZU DESSEN HERSTELLUNG

Ein Verfahren weist die folgenden Schritte auf: Herstellen einer Vorrichtungsstruktur, wobei das Herstellen der Vorrichtungsstruktur das Herstellen einer ersten Umverteilungsstruktur über und in elektrischer Verbindung mit einer Halbleitervorrichtung und das Herstellen eines Formmaterials um die erste Umverteilungsstruktur und die Halbleitervorrichtung umfasst; Herstellen einer zweiten Umverteilungsstruktur über dem Formmaterial und der ersten Umverteilungsstruktur, wobei die zweite Umverteilungsstruktur mit der ersten Umverteilungsstruktur elektrisch verbunden ist; Befestigen einer Verbindungsstruktur an der zweiten Umverteilungsstruktur, wobei die Verbindungsstruktur ein Kernsubstrat aufweist und mit der zweiten Umverteilungsstruktur elektrisch verbunden ist; und Abscheiden eines Unterfüllungsmaterials auf Seitenwänden der Verbindungsstruktur und zwischen der zweiten Umverteilungsstruktur und der Verbindungsstruktur.

Verfahren zur Herstellung eines Halbleiterbauteils mit Durchkontakten zwischen Oberseite und Rückseite

Die Erfindung betrifft ein Verfahren zur Herstellung eines Halbleiterbauteils (1) mit Durchkontakten (2) zwischen Oberseite (3) und Unterseite (4), wobei die Durchkontakte (2) in mindestens einem Randbereich (5) des Halbleiterbauteils (1) angeordnet sind. Die Durchkontakte (2) verbinden elektrisch miteinander Außenkontaktflächen (7, 8) des Halbleiterbauteils (1) auf der Oberseite (3) und Unterseite (4). Eine Kunststoffgehäusemasse (10) umgibt mindestens einen Halbleiterchip (9) mit Kontaktflächen (11) auf der aktiven Oberseite (12) des Halbleiterchips (9). Die Kontaktflächen (11) stehen mit den Durchkontakten (2) über eine Verdrahtungsstruktur (14) elektrisch in Verbindung, wobei die Durchkontakte (2) in mindestens einer vorgefertigten Durchkontaktleiste (15) angeordnet sind, die in dem Randbereich (5) des Halbleiterbauteils (1) positioniert ist.

Elektronische Baugruppe und Verfahren zu deren Herstellung

Die vorliegende Erfindung betrifft eine elektronische Baugruppe (50, 50') mit einem Leiterplattenmehrschichtaufbau (10) aus mindestens zwei elektrisch leitenden Schichten (12, 14), die jeweils mindestens einen über den Mehrschichtaufbau (10) hinausragenden Schichtabschnitt (12.2, 14.1, 14.2) aufweisen, der einen zur direkten Ankontaktierung eines zusätzlichen passiven Bauelements (C, C'; L;) ausgebildeten Anschlussbereich definiert.

A method of manufacturing diodes with ceramic base and dice structure

PROCEDURE FOR THE ESTABLISHMENT OF AN ELECTRONIC CONSTRUCTION UNIT ON A PRINTED CIRCUIT BOARD, PRODUCTION PROCEDURE OF A TRÄGERLAGE AND A SPAN, AS WELL AS SYSTEM CONSISTING OF A PRINTED CIRCUIT BOARD AND AT LEAST AN ELECTRONIC CONSTRUCTION UNIT

Verfahren zur Herstellung einer Leiterplatte mit zumindest einer optoelektronischen Komponente

The invention relates to a method for producing a circuit board having at least one optoelectronic component, which method is characterized by the following steps: a) applying a transparent curable adhesive layer (1) to a carrier layer (2), b) placing at least one optoelectronic component (3) onto the adhesive layer (1) by means of an optically relevant side (4) of the component, c) curing the adhesive layer (1) into a window element (1'), d) embedding the component (3) in a circuit-board composite, e) structuring the carrier layer (2) in order to at least partially expose the window element (1') and to contact the component (3).

METHOD FOR FIXING AN ELECTRONIC COMPONENT ON A PRINTED CIRCUIT BOARD AND SYSTEM COMPRISING A PRINTED CIRCUIT BOARD AND AT LEAST ONE ELECTRONIC COMPONENT

In a method for fixing an electronic component (3) on a printed circuit board (2), and contact-connecting the electronic component (3) to the printed circuit board (2), the following steps are provided: - providing the printed circuit board (2) having a plurality of contact and connection pads (8), - providing the electronic component (3) having a number of contact and connection locations (5) corresponding to the plurality of contact and connection pads (8) of the printed circuit board (2), with a mutual spacing reduced in comparison with the spacing of the contact and connection pads (8) of the printed circuit board (2), and ~ arranging or forming at least one interlayer (4) for routing the contact and connection locations (5) of the electronic component (3) between the contact and connection pads (8) of the printed circuit board (2) and the contact and connection locations (5) of the electronic component (3). A method for producing an interlayer (4) for routing and a system having a ...

Verfahren zum Verbinden einer integrierten Schaltung mit äusseren elektrischen Zuleitungen

Halbleitervorrichtung

Chip Carriers And Semiconductor Devices Including Redistribution Structures With Improved Thermal And Electrical Performance

The antenna module

Post-passivation interconnect structure and methods thereof

Wafer level system packaging method and packaging structure

Integrated passive device wafer level package the fan leaves three-dimensional stacked structure and method for making the same

Wafer packaging method

Integrated fan-out package

Packaging structure and manufacturing method thereof

... 本发明公开种封装结构及其制造方法，该封装结构具有至少部分的第导电元件配置在第基板的贯穿开口(through‑opening)中。导电结构配置在第基板和第导电元件上方，其中该导电结构电性连接至该第基板和该第导电元件的该至少第输入/输出端。导电结构包含第二导电元件、第二基板或导电图案其中至少个。 ...

Manufacturing method of semiconductor device and semiconductor device

Improved microelectronic component electrical contact pad connection having microelectronic component directly attached printed circuit face with thin isolated attachment and through

L'invention concerne la connexion électrique des plots de contact (7) d'au moins un composant microélectronique (5) directement à des pistes conductrices (11) d'une plaque à circuits imprimés, ce composant ayant des plots métalliques affleurant une face principale; on solidarise le composant (5), par sa face portant les plots (7), à un substrat mince (1) électriquement isolant; on fore des trous (8) à travers le substrat respectivement en regard des plots de manière que ces trous débouchent en affleurement sur les plots (7); et on métallise (12) les trous (8) de manière à établir des liaisons électriques entre les plots formant le fond des trous et des pistes de circuits imprimés (11), dans lesquelles débouchent les trous métallisés, situées sur la face externe du substrat isolant (1).

팬-아웃 반도체 패키지

... 적어도 하나의 관통홀이 형성되며 내부면에 금속층이 배치되는 코어부재와, 상기 관통홀에 배치되는 반도체 칩과, 상기 코어부재와 상기 반도체 칩을 봉합하는 봉합재와, 상기 봉합재의 상면에 배치되는 금속 플레이트 및 상기 봉합재를 관통하여 상기 금속층과 상기 금속 플레이트를 연결하는 벽체를 포함하며, 상기 벽체에는 적어도 하나 이상의 개구부가 형성되는 팬-아웃 반도체 패키지가 개시된다.

팬-아웃 반도체 패키지

... 본 개시는 관통홀을 갖는 제1연결부재, 제1연결부재의 관통홀에 배치되며 접속패드가 배치된 활성면 및 활성면의 반대측에 배치된 비활성면을 갖는 프로세서칩, 제1연결부재의 관통홀에 배치되며 접속패드가 배치된 활성면을 가지며 복수의 다이가 적층된 형태의 메모리칩, 제1연결부재와 메모리칩과 프로세서칩의 비활성면의 적어도 일부를 봉합하는 봉합재, 및 제1연결부재와 메모리칩의 활성면과 프로세서칩의 활성면 상에 배치된 제2연결부재를 포함하며, 제1 및 제2연결부재는 프로세서칩의 접속패드 및 메모리칩의 접속패드와 전기적으로 연결된 재배선층을 각각 포함하며, 프로세서칩의 접속패드 및 메모리칩의 접속패드는 제2연결부재의 재배선층을 통하여 서로 전기적으로 연결된 팬-아웃 반도체 패키지에 관한 것이다.

칩 패키지

... 패시베이션 층에 다이 접촉 패드들을 가지는 다이를 포함하는 내장형 다이 패키지로서, 상기 다이 접촉 패드는 접착 층에 의해 피처 층의 제1 측면에 결합되고, 필러(pillar)의 층은 상기 피처 층의 제2 측면으로부터 뻗어있고, 상기 다이, 피처층, 및 필러 층은 유전체 재료에 의해 캡슐화되는 상기 내장형 다이 패키지.

SEMICONDUCTOR PACKAGE

적층가능 마이크로전자 패키지 구조

... 마이크로전자 어셈블리(8)는 제 1 면(14) 및 제 2 면(16) 및 기판 콘택(24)이 있는 기판(12)을 가지는 제 1 마이크로전자 패키지(10A)를 포함한다. 제 1 패키지는 기판 콘택과 전기적으로 접속되고 제 1 면 상에서 서로로부터 이격되어 제 1 및 제 2 마이크로전자 소자 사이에 상호접속 영역을 제공하는 소자 콘택(24)을 가지는 제 1 및 제 2 마이크로전자 소자(40)를 더 포함한다. 제 2 면에서의 복수 개의 패키지 단자(26)는 패키지를 외부 컴포넌트와 접속시키기 위하여 기판 콘택과 상호접속된다. 복수 개의 스택 단자(58)는 패키지를 기판의 제 1 면에 상재하는 컴포넌트와 접속시키기 위하여 상호접속 영역 내의 제 1 면에서 노출된다. 어셈블리는 제 1 마이크로전자 패키지에 상재하며 제 1 마이크로전자 패키지의 스택 단자에 결합되는 단자(26)를 가지는 제 2 마이크로전자 패키지(10B)를 더 포함한다.

ELECTRONIC COMPONENT PACKAGE AND MANUFACTURING METHOD THEREOF

The present disclosure relates to an electronic component package and a manufacturing method thereof. The electronic component package comprises: a frame having a through hole; an electronic component disposed in the through hole of the frame; and a re-distribution section disposed on one side of the frame and the electronic component, wherein at least one first wiring layer electrically connected to the electronic component is disposed inside the frame through the re-distribution section. COPYRIGHT KIPO 2016 ...

ALIGNMENT MARK WITH GRATING PATTERNS AND METHOD FORMING SAME

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Disclosed is a semiconductor package where a semiconductor chip and a mounting device are packaged together. The semiconductor package according to the embodiment of the present invention includes a semiconductor chip, a mounting block where a first mounting device is mounted on a substrate having a circuit, and a wiring part which electrically connects the semiconductor chip and the mounting block. So, the semiconductor chip can be separated from the substrate having the mounting device. COPYRIGHT KIPO 2016 ...

SEMICONDUCTOR CHIP PACKAGE AND A METHOD FOR MANUFACTURING THE SAME, CAPABLE OF EFFECTIVELY EMITTING HEAT GENERATED IN A SEMICONDUCTOR CHIP TO THE OUTSIDE

PURPOSE: A semiconductor chip package and a method for manufacturing the same are provided to form an insulation layer and a solder resist layer of a semiconductor layer by a heat conductive low dielectric material, thereby increasing heat emitting effects of the semiconductor chip package. CONSTITUTION: A semiconductor chip(10) comprises an active surface(12) on which a chip pad(11) is formed. A heat conductive low dielectric molding film(20) exposes the active surface. An insulation layer(30) includes the first opening for exposing one area of the chip pad. A rewiring pattern(40) is electrically connected to the chip pad. A solder resist layer(50) comprises the second opening exposing one area of the rewiring pattern. COPYRIGHT KIPO 2011 ...

THREE DIMENSIONAL INTEGRATED MICROELECTRONIC ASSEMBLY FOR AN INTEGRATED CIRCUIT DEVICE AND A MANUFACTURING METHOD THEREOF

PURPOSE: A three dimensional integrated microelectronic assembly for an integrated circuit device and a manufacturing method thereof are provided to improve reliability using a crystal substrate package structure having fan-in and fan-out pads in order to package an IC chip. CONSTITUTION: A crystalline structure handler(10) comprises a first surface and a second surface which face each other. A cavity is formed inside the first surface. A first IC device is prepared in a first cavity. A second IC device is mounted on the second surface. A plurality of wires are formed through the crystallization substrate handler. Each wire comprises a hole having a sidewall, a compliant dielectric material(28), and a conductive material. The compliant dielectric material is prepared along the sidewall. COPYRIGHT KIPO 2013 ...

리세싱된 엣지들을 갖는 반도체 디바이스 및 그 제조방법

... 패키지 엣지를 따라 리세싱된 영역들을 활용하는 디바이스 및 제조 방법이 제공된다. 예를 들어, 집적형 팬 아웃 패키지에 있어서, 단품화 이후 유전체층들이 다이의 엣지들로부터 리세싱 백(recessed back)되도록, 유전체층들, 예컨대 재분배층들의 폴리머층들은 스크라이브 라인을 따라 제거된다. 모서리 영역들은 더욱 리세싱될 수 있다. 리세싱된 영역들은 삼각형, 둥근형, 또는 이와 다른 형상일 수 있다. 몇몇의 실시예들에서, 하나 이상의 모서리 영역들은 남아있는 모서리 영역들에 비해 더욱 리세싱될 수 있다. 재분배층들은 전측면 재분배층들과 후측면 재분배층들 중 하나 또는 이 둘 모두를 따라 리세싱될 수 있다.

SEMICONDUCTOR HOUSING PACKAGE, SEMICONDUCTOR PACKAGE STRUCTURE INCLUDING THE SAME, AND PROCESSOR BASED SYSTEM INCLUDING THE SEMICONDUCTOR PACKAGE STRUCTURE CAPABLE OF IMPLEMENTING HIGH INTEGRATION

PURPOSE: A semiconductor housing package, a semiconductor package structure including the same, and a processor based system including the semiconductor package structure are provided to reduce the manufacturing costs of the processor based system by minimizing the use of a printed circuit board. CONSTITUTION: A housing chip(77) is surrounded with a mold layer(84) and is exposed from the mold layer. Rewiring patterns are extended from the mold layer to the housing chip. The rewiring patterns are electrically connected to the housing chip. A housing terminal is protruded from the rewiring patterns. A circuit board(3) is electrically connected to the housing terminals. COPYRIGHT KIPO 2012 ...

반도체 패키지 및 그 제조방법

... 본 발명은 반도체 패키지 및 그 제조 방법이 제공된다. 반도체 패키지는 제1 절연 패턴, 제1 절연층, 및 재배선 패턴을 포함하는 재배선층; 및 상기 재배선층 상에 배치되고, 칩 패드를 갖는 반도체칩을 포함할 수 있다. 상기 제1 절연 패턴은 폴리머 및 제1 무기 필러를 포함할 수 있다. 상기 제1 절연층은 상기 제1 절연 패턴 상에 제공될 수 있다. 상기 재배선 패턴은 상기 제1 절연 패턴 및 상기 제1 절연층을 관통하며, 상기 칩 패드와 접속할 수 있다.

SEMICONDUCTOR PACKAGE AND A MANUFACTURING METHOD THEREOF, REDUCING A PROCESS TIME WITHOUT THE INSULATION OF A VIA HOLE

PURPOSE: A semiconductor package and a manufacturing method thereof are provided to prevent a wafer or semiconductor die from being damaged previously by forming a via hole in an encapsulant around the semiconductor die and not forming the via hole in the wafer made of silicon. CONSTITUTION: A semiconductor die(110) includes a plurality of bond pads. An encapsulant(120) is formed while covering the side of the semiconductor die. A plurality of pillars(130) is formed in the edge of the encapsulant while passing through the encapsulant. An electrical connection member(140) electrically connects a bond pad of the semiconductor die and the pillar. The semiconductor die is positioned in the center of the encapsulant and an upper side(110a) is exposed. The lower surface of the semiconductor die makes the same pane as the lower surface of the encapsulant and is exposed. © KIPO 2009 ...

집적된 고전압 디바이스들을 갖는 실리콘 다이

... 기판 상에 복수의 제1 디바이스들 및 복수의 제1 인터커넥트들을 형성하는 단계; 복수의 제2 디바이스들을 포함하는 제2 디바이스 층을 상기 복수의 제1 인터커넥트들 중의 인터커넥트들에 연결하는 단계, 및 상기 제2 디바이스 층 상에 복수의 제2 인터커넥트들을 형성하는 단계를 포함하는 방법. 복수의 제1 인터커넥트들과 복수의 제2 인터커넥트들 사이에 배치된 복수의 제1 회로 디바이스들을 포함하는 제1 디바이스 층, 및 상기 복수의 제1 인터커넥트들 및 상기 복수의 제2 인터커넥트들 중의 하나에 병치되어 연결된 복수의 제2 디바이스들을 포함하는 제2 디바이스 층을 포함하고, 상기 복수의 제1 디바이스들 및 상기 복수의 제2 디바이스들 중의 하나는 상기 복수의 제1 디바이스들 및 상기 복수의 제2 디바이스들 중의 다른 하나보다 더 고전압 범위를 갖는 디바이스들을 포함하는 장치.

SEMICONDUCTOR DEVICE WHICH FORMS A RE-DISTRIBUTION LAYER AND A MANUFACTURING METHOD THEREOF

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent the imbalance of the top height of a conductive member by forming a second conductive layer when eliminating a first conductive layer. CONSTITUTION: Insulating layers(32,34) are formed on the top of a substrate. A first opening is formed on the insulating layer. The first opening exposes a concave part(33). second opening is arranged at the exterior of the first opening and does not expose the concave part. A first conductive and a second conductive member are formed inside the first opening and the second opening by depositing conductive materials. The first conductive member is left within the concave part. COPYRIGHT KIPO 2013 ...

Multi-die package comprising unit specific alignment? and unit specific routing

Fan-out semiconductor package

Semiconductor package and board for mounting the same

Heterogeneous chip integration with low loss interconnection through adaptive patterning

Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.

Semiconductor packages

Semiconductor packages are provided. One of the semiconductor packages includes a first chip, a second chip and a molding compound. The first chip has at least one first via and a protection layer thereon, and the at least one first via is formed in the protection layer. The second chip has at least one second via thereon. The molding layer encapsulates the first and second chips. The at least one second via is disposed in and contact with the molding layer, and top surfaces of the protection layer, the at least one first via and the at least one second via are substantially coplanar with a top surface of the molding layer.

Fan-out semiconductor package module

A fan-out semiconductor package module includes: a structure including a wiring member including wiring patterns, one or more first passive components disposed on the wiring member and electrically connected to the wiring pattern, and a first encapsulant encapsulating at least portions of each of the one or more first passive components, and having a first through-hole penetrating through the wiring member and the first encapsulant; a semiconductor chip disposed in the first through-hole of the structure and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; a second encapsulant encapsulating at least portions of the semiconductor chip and filling at least portions of the first through-hole; and a connection member disposed on the structure and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads and the wiring patterns.

Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate

A microelectronic package 100 includes a microelectronic element 101 having a memory storage array. Terminals 104 on a surface 110 of a substrate 102 are configured for connection to an external component. Substrate contacts 121 exposed at an opposite surface 108 of the substrate 102 face and are joined to element contacts 111 of the microelectronic element 101. The terminals can include first terminals 104 arranged at positions within first and second sets 114, 124 thereof disposed on respective opposite sides of a theoretical axis 132. Each set of first terminals 104 can be configured to carry address information usable by circuitry within the microelectronic package 100 to determine an addressable memory location in the memory storage array. The signal assignments of the first terminals 104 in the first set 114 can be a mirror image of the signal assignments of the first terminals in the second set 124.

Semiconductor package and method of manufacture

Disclosed is a method of manufacturing a semiconductor package, comprising disposing a semiconductor component in a recessed part of a carrier member, forming an adhesive material in the recessed part and the circumference of the semiconductor component, forming a dielectric layer on the adhesive material and the semiconductor component, forming a circuit layer on the dielectric layer to electrically connect the semiconductor component, and removing the lower part of the recessed part of the carrier member to retain the part on the sidewall of the recessed part as a support portion. The invention eliminates the need to form the conventional medium board and can thus reduce manufacturing costs and further provides the semiconductor package as described above.

Dicing in wafer level package

A method includes placing a first device die and a second device die over a carrier, with a scribe line between the first device die and the second device die. The first device die and the second device die are encapsulated with an encapsulating material, which has a portion in the scribe line. The method further includes forming a dielectric layer over the encapsulating material, performing a first die-saw to form a first trench in the scribe line, performing a second die-saw to form a second trench in the scribe line, and performing a third die-saw on the scribe line to separate the first device die from the second device die.

A semiconductor package structure

The present invention provides a semiconductor package structure. The structure includes a molding compound having a dicing lane region. A semiconductor die is disposed in the molding compound and surrounded by the dicing lane region. The semiconductor die has a first surface and a second surface opposite thereto. The structure further includes a redistribution layer (RDL) structure disposed on the first surface of the semiconductor die and covering the molding compound. The RDL structure has an opening aligned with the dicing lane region.

Semiconductor package structure and manufacturing method thereof

A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to each other. The package structure is over the first surface, and includes a die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the exposed first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant encapsulates the package structure, and exposes at least part of the second conductive terminals ...

Semiconductor device and method of forming low profile 3d fan-out package

A semiconductor device includes a substrate having an insulating layer and a conductive layer embedded in the insulating layer. The conductive layer is patterned to form conductive pads or conductive pillars. The substrate includes a first encapsulant formed over the conductive layer. A first opening is formed through insulating layer and first encapsulant using a stamping process or laser direct ablation. The substrate is separated into individual units, which are mounted to a carrier. A semiconductor die is disposed in the first opening in the substrate. A second encapsulant is deposited over the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and substrate. An opening is formed through the second encapsulant and through the insulating layer to expose the conductive layer. A bump is formed in the second opening over the conductive layer outside a footprint of the semiconductor die.

Integrated fan-out package

An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which raises toward sidewalls of the integrated circuit component. The insulating encapsulation encapsulates the uplifted edge and the integrated circuit component. The redistribution circuit structure is disposed on the integrated circuit component and the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals of the integrated circuit component. A method of fabricating the integrated fan-out package is also provided.

Package substrate and its fabrication method

This disclosure provides a package substrate and its fabrication method. The package substrate includes: a molding compound body; a first circuit device having a plurality of first terminals on its top surface and disposed in the molding compound body; a plurality of first conductive vias formed in the molding compound body and connected to the first terminals; a second circuit device having a plurality of second terminals on its top surface and disposed in the molding compound body; a plurality of second conductive vias formed in the molding compound body and connected to the second terminals; and a redistribution layer formed on the molding compound body and having at least one conductive wire which connects the first conductive vias and the second conductive vias; wherein the first terminals have a first depth in the molding compound body, the second terminals have a second depth in the molding compound body, and the first depth is not equal to the second depth.

Thin-film capacitor and semiconductor device

A thin-film capacitor (20) disposed on a rewiring layer (10) of a semiconductor device (100) including a semiconductor chip (50), wherein the thin-film capacitor (20) comprises: a capacitor unit (21) made up of a first electrode (21A), a dielectric body (21B) formed on the first electrode, and a second electrode (21C) formed on the dielectric body; and an adhesion section (22) which is provided to the bottom surface of the first electrode (21A) and is used when adhering the thin-film capacitor (20) to a protective film (52) of the semiconductor chip (50). The total thickness of the capacitor unit (21) and the adhesion section (22) is 20 [mu]m or less.

Package structures

A package structure and methods for forming the same are provided. The package structure includes an integrated circuit die in a package layer. The package structure also includes a first passivation layer covering the package layer and the integrated circuit die, and a second passivation layer over the first passivation layer. The package structure further includes a seed layer and a conductive layer in the second passivation layer. The seed layer covers the top surface of the first passivation layer and extends into the first passivation layer. The conductive layer covers the seed layer and extends into the first passivation layer. In addition, the package structure includes a third passivation layer covering the second passivation layer. The seed layer further extends from the top surface of the first passivation layer to the third passivation layer along a sidewall of the conductive layer.

Method and system for packing optimization of semiconductor devices

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

Semiconductor packages including a bridge die

A semiconductor package includes a semiconductor die and a bridge die. The bridge die is configured to include a through via formed in a body of the bridge die and a capacitor electrically coupled to the through via.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING SUPPORTING LAYER OVERSEMICONDUCTOR DIE IN THIN FAN-OUTWAFER LEVEL CHIP SCALE PACKAGE

Package structure and manufacture method thereof

A package structure including a semiconductor die, an insulating encapsulant, a dielectric layer, and a redistribution layer is provided. The semiconductor die has an active surface, a back surface opposite to the active surface, and a plurality of conductive bumps disposed on the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the he insulating encapsulant and electrically connected to the plurality of conductive bumps. The dielectric layer is disposed between the insulating encapsulant and the redistribution layer, wherein the dielectric layer encapsulates at least a portion of each of the plurality of conductive bumps. A manufacturing method of the package structure is also provided.

Chip structure and manufacturing method thereof

A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion protrudes from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

Component embedded package carrier and manufacturing method thereof

Semiconductor device and method

Fan-out semiconductor package

METHOD OF FORMING SEMICONDUCTOR DEVICE

Semiconductor device and method of forming an embedded sop fan-out package

Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods

SUBSTRATE-LESS STACKABLE PACKAGE WITH WIRE-BOND INTERCONNECT

A method for making a microelectronic unit (10) includes forming wire bonds (32) on a conductive bonding surface (30') of a patternable metallic element (28'). The wire bonds are formed having bases (34) joined to the first surface and end surfaces (38) remote from the first surface. The wire bonds have edge surfaces (36) extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer (42) over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements (28) beneath the wire bonds and insulated from one another by portions of the encapsulation layer.

EXPANDED SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE

A semiconductor device (1) is provided with: a first semiconductor chip (2) that is provided with first electrodes (21) on the surface; and an expanded semiconductor chip (3) which comprises a second semiconductor chip (31) and a resin expanded part (33) that is formed outwardly from at least one lateral surface of the second semiconductor chip, said expanded semiconductor chip (3) being provided with second electrodes (35) on the surface. The first semiconductor chip and the expanded semiconductor chip are arranged so that the surfaces on which the first electrodes and the second electrodes are formed face each other, and the first electrodes and the second electrodes are connected with each other. Among the second electrodes of the expanded semiconductor chip, those connected with the first electrodes are formed only on the resin expanded part.

PACKAGING METHODS FOR IMAGER DEVICES

An imager device is disclosed which includes at least one photosensitive element positioned on a front surface of a substrate and a conductive structure extending at least partially through an opening defined in the substrate to conductively couple to an electrical contact or bond pad on the first surface. An insulating material of a conductive laminate film and/or a mold compound material is positioned within the opening between at least a portion of the conductive structure and the substrate. Also disclosed is a device that comprises a substrate and a plurality of openings in the substrate, wherein each of the openings is adapted to be positioned above an imager device when the substrate is positioned above and secured to an imager substrate. A method of forming an imager device is also disclosed.

METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE

A method of manufacturing a semiconductor structure include: providing a die including a die pad disposed over the die; disposing a conductive member over the die pad of the die; forming a molding surrounding the die and the conductive member; disposing a dielectric layer over the molding, the die and the conductive member; and forming an interconnect structure including a land portion and a plurality of via portions. The land portion is disposed over the dielectric layer, the plurality of via portions are disposed over the conductive member and protruded from the land portion to the conductive member through the dielectric layer, and each of the plurality of via portions at least partially contacts with the conductive member.

Integrated Circuit Structure and Method of Forming

An integrated circuit structure and method of forming is provided. A die is placed on a substrate and encased in molding compound. A redistribution layer is formed overlying the die and the substrate is removed. One or more surface mounted devices and/or packages are connected to the redistribution layer on an opposite side of the redistribution layer from the die. The redistribution layer is connected to a printed circuit board.

Semiconductor package and method of manufacturing the same

A semiconductor package including an internal package including at least one semiconductor chip sealed with an internal seal, an external substrate on which the internal package is mounted, and an external seal sealing the internal package is provided. Also provided is a method of manufacturing the semiconductor package including forming an internal package including at least one semiconductor chip sealed with an internal seal, mounting the internal package on an external substrate, and sealing the internal package with an external seal. The internal seal and the external seal have different Young's moduli, for example, a Young's modulus of the internal seal is smaller than a Young's modulus of the external seal. Accordingly, the semiconductor package is less susceptible to warpage and can be handled with relative ease in subsequent semiconductor package processes.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a semiconductor chip having an active surface, on which a connection pad is disposed, and an inactive surface disposed to oppose the active surface, a heat dissipation member, disposed on the inactive surface of the semiconductor chip, having a plurality of holes and including a graphite-based material, an encapsulant covering at least a portion of each of the semiconductor chip and the heat dissipation member, and a connection member, disposed on the active surface of the semiconductor chip, including a redistribution layer electrically connected to the connection pad. 0 Подробнее

Package apparatus and manufacturing method thereof

A package apparatus comprises a first conductive wiring layer, a first conductive pillar layer, a first conductive glue layer, an internal component, a second conductive pillar layer, a first molding compound layer and a second conductive wiring layer. The first conductive pillar layer is disposed on the first conductive wiring layer. The first conductive glue layer is disposed on the first conductive wiring layer. The internal component has a first electrode layer and a second electrode layer, wherein the first electrode layer is disposed and electrical connected to the first conductive glue layer. The second conductive pillar layer is disposed on the second electrode layer. Wherein the first conductive wiring layer, the first conductive pillar layer, the first conductive glue layer, the internal component and the second conductive pillar layer are disposed inside the first molding compound layer.

Semiconductor device and manufacturing method of the same

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.

NEW DUAL-GATE TRENCH IGBT WITH BURIED FLOATING P-TYPE SHIELD

A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

ELECTRONIC DEVICE PACKAGE AND FABRICATING METHOD THEREOF

Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 μm or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof.

MICROELECTRONIC PACKAGES CONTAINING OPPOSING DEVICES AND METHODS FOR THE FABRICATION THEREOF

Microelectronic packages and methods for fabricating microelectronic packages are provided. The fabrication method may be carried-out utilizing a preformed panel having a frontside cavity and a backside cavity in which first and second microelectronic devices are positioned, respectively. One or more frontside RDL layers are produced over the frontside of the preformed panel in ohmic contact with or otherwise electrically coupled to the first microelectronic device. Similarly, one or more backside RDL layers are formed over the backside of the preformed panel in ohmic contact with or otherwise electrically coupled to the second microelectronic device. A frontside contact array is produced over the frontside of the preformed panel and electrically coupled to at least the first microelectronic device through the frontside RDL layers. Lastly, the preformed panel is singulated to yield a microelectronic package including a package body in which the first and second microelectronic devices are ...

Method of making demountable interconnect structure

A method for making an interconnect structure includes applying a first metal layer to an electronic device, wherein the electronic device comprises at least one I/O contact and the first metal layer is located on a surface of the I/O contact; applying a removable layer to the electronic device. The removable layer is adjacent to the first metal layer. An adhesive layer is applied to the electronic device or to a base insulative layer. The electronic device is secured to the base insulative layer using the adhesive layer. The first metal layer and removable layer are disposed between the electronic device and the base insulative layer.

Fan-out semiconductor package

A fan-out semiconductor package includes: a core member having a through-hole and having first fiducial marks disposed on an upper surface thereof in the vicinity of the through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads and second fiducial marks disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip, wherein the first fiducial marks are disposed to be symmetrical to each other with respect to a center of the through-hole on a plane view, and the second fiducial marks are disposed to be symmetrical to each other with respect to a center of the semiconductor chip on the plane view.

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

High frequency module and manufacturing method thereof

A high frequency module includes: a semiconductor chip provided over a first surface side of a resin layer; a first waveguide provided over the first surface side of the resin layer and sealed together with the semiconductor chip by a resin; a wire provided over a second surface side of the resin layer and electrically coupled to the semiconductor chip and extending to a position of the first waveguide; a second waveguide bonded to the first waveguide; and a metal plate provided over the first surface side of the resin layer at a position opposite to the first waveguide and electrically coupled to the wire, wherein a part of the wire extending to the position of the first waveguide serves as an antenna coupler.

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes a first circuit layer, at least one electrical element, a first molding layer, an electronic component and a second molding layer. The at least one electrical element is disposed over a first surface of the first circuit layer and electrically connected to the first circuit layer. The first molding layer is disposed over the first surface of the first circuit layer. The first molding layer encapsulates an edge of the at least one electrical element, and a lower surface of the first molding layer and a lower surface of the at least one electrical element are substantially coplanar. The electronic component is disposed over a second surface of the first circuit layer and is electrically connected to the first circuit layer. The second molding layer is disposed over the second surface of the first circuit layer and encapsulates the electronic component.

SEMICONDUCTOR DEVICE AND POWER CONVERTER

A semiconductor device includes: at least one power semiconductor element; a sealing resin disposed so as to seal the power semiconductor element; and a plurality of electrical terminals each electrically connected to the power semiconductor element and each including a protrusion protruding from a surface of the sealing resin. The protrusion includes a first part that is provided on a side of the sealing resin in a protrusion direction of the protrusion and of which a cross-section intersecting the protrusion direction has one of a circular shape and an oval shape.

Chip package structure having at least one chip and at least one thermally conductive element and manufacturing method thereof

A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.

Package structure and method of manufacturing the same

Provided are a package structure and a method of manufacturing the same. The package structure includes a die, a passive device, and a package. The die has a front side and a backside opposite to each other. The package is disposed on the backside of the die. The passive device is disposed between the backside of the die and the package.

Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process

The present disclosure relates to a bulk complementary-metal-oxide-semiconductor (CMOS) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the thinned device die. Herein, a silicon material with a resistivity between 5 Ohm-cm and 30000 Ohm-cm does not exist between the second mold compound and the thinned device die.

SEMICONDUCTOR DEVICE

A semiconductor device includes: on an upper surface of a second semiconductor chip on a circuit board, a ring dam section formed at an outer circumference of a mounting region above which a first semiconductor chip is mounted; and an interconnect extending from the dam section to a center section of the first semiconductor chip or the second semiconductor chip in a region in which the first semiconductor chip faces the second semiconductor chip. The interconnect is electrically connected to a connection terminal on a circuit formation surface of the first or second semiconductor chip at the center section of the first or second semiconductor chip. The dam section and the interconnect are power supply interconnects or ground interconnects.

SEMICONDUCTOR PACKAGE

A semiconductor package includes: a connection member including a plurality of connection pads and a redistribution layer; a semiconductor chip disposed on the connection member; an encapsulant sealing the semiconductor chip; a passivation layer disposed on the connection member; a plurality of under bump metallurgy (UBM) pads disposed on the passivation layer; and a plurality of UBM vias connecting the plurality of UBM pads to the plurality of connection pads, respectively, wherein the plurality of UBM pads include a first UBM pad overlapped with the semiconductor chip in a stacking direction, and a second UBM pad located outside of the overlapped region, and the first connection pad has an area larger than an area of an associated first UBM pad while the associated first UBM pad is overlapped in the stacking direction, and has an area larger than an area of the second connection pad.

Grinding wheel design with elongated teeth arrangement

A grinding wheel includes a base disk, and a plurality of teeth protruding beyond a surface of the base disk. The plurality of teeth is aligned to an elongated ring encircling a center of the grinding wheel.

Supporting InFO Packages to Reduce Warpage

A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die. 18.-. (canceled)9. A method comprising:encapsulating a first device die and a second device die in an encapsulating material;forming redistribution lines over the first device die and the second device die;forming electrical connectors overlying and electrically coupling to the first device die and the second device die through the redistribution lines;performing a singulation on the encapsulating material, wherein the first device die and the second device die are sawed into a package; andattaching the package to a dummy support die, wherein the dummy support die extends beyond edges of the package in each of four lateral directions.1011-. (canceled)12. The method of further comprising bonding a bridge die to the package claim 9 , wherein the bridge die is on an opposite side of the redistribution lines than the first device die and the second device die.13. The method of claim 12 , wherein the dummy support die is bonded to have a first portion overlapped by the first device die claim 12 , and a second portion overlapped by the second device die.1420.-. (canceled)21. A method comprising: a first device die;', 'a second device die;', 'an encapsulating material encapsulating the first device die and the second device die therein, wherein opposite sides of the adhesive film are in physical contact with the encapsulating material and the blank die; and', 'a plurality of redistribution lines over and ...

FAN-OUT POP STACKING PROCESS

Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.

Semiconductor package and manufacturing method thereof

A semiconductor package includes a redistribution structure, a memory wafer, semiconductor dies and conductive vias. The memory wafer, disposed over the redistribution structure, includes at least one memory die. The semiconductor dies are disposed side by side with respect to each other, between the memory wafer and the redistribution structure, and are electrically connected to the redistribution structure. The conductive vias electrically connect the at least one memory die with the redistribution structure. A semiconductor package includes a redistribution structure, a reconstructed wafer, and a heat sink. The reconstructed wafer is disposed on the redistribution structure. The reconstructed wafer includes logic dies and memory dies. The logic dies are electrically connected to the redistribution structure. The memory dies are electrically connected to the redistribution structure and vertically stacked with the logic dies. The heat sink is disposed on the reconstructed wafer. The heat ...

Millimeter wave antenna and EMI shielding integrated with fan-out package

Systems and methods of manufacture are disclosed for a semiconductor device assembly having a semiconductor device having a first side and a second side opposite of the first side, a mold compound region adjacent to the semiconductor device, a redistribution layer adjacent to the first side of the semiconductor device, a dielectric layer adjacent to the second side of the semiconductor device, a first via extending through the mold compound region that connects to at least one trace in the dielectric layer, and an antenna structure formed on the dielectric layer and connected to the semiconductor device through the first via.

Package structure

Disclosed is a package structure including a semiconductor chip disposed in a core board having a first surface and an opposite second surface. The package structure further includes a plurality of first and second electrode pads disposed on an active surface and an opposite inactive surface of the semiconductor chip respectively, the semiconductor chip having a plurality of through-silicon vias for electrically connecting the first and second electrode pads. As a result, the semiconductor chip is electrically connected to the two sides of the package structure via the through-silicon vias instead of conductive through holes, so as to enhance electrical quality and prevent the inactive surface of the semiconductor chip from occupying wiring layout space of the second surface of the core board to thereby increase wiring layout density and enhance electrical performance.

Bumpless build-up layer package with pre-stacked microelectronic devices

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

Electric part package and manufacturing method thereof

A disclosed electric part package includes a supporting member that includes a first area in which an electric part is arranged, and a second area in which a first opening is positioned, the second area being isolated from the first area; a resin part provided on the supporting member thereby to cover the electric part arranged in the first area, the resin part including an electric terminal exposed in the first opening of the supporting member; and a wiring structure provided on the resin part, the wiring structure being electrically connected to the electric part and the electric terminal of the resin part.

Semiconductor Device and Method of Manufacture Thereof

A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.

Semiconductor package and manufacturing method therefor

According to one embodiment, there is provided a semiconductor package including: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure.

Flexible circuit board and manufacturing method thereof

The present invention provides a high-performance flexible circuit board having excellent flexibility, a fine wiring pattern, and fine electric contacts, and a manufacturing method thereof. In a flexible circuit board ( 20 ), a second insulating layer ( 24 ) made of an inorganic material is positioned between a wiring layer ( 25 ) and a first insulating layer ( 23 ) made of an inorganic material.

Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer

A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

Semiconductor package and method for manufacturing semiconductor package

A semiconductor package includes a semiconductor chip including a circuit forming surface and a side surface, and a sealing insulation layer that seals the circuit forming surface and the side surface of the semiconductor chip, the sealing insulation layer having a first surface on a side of the circuit forming surface. At least one wiring layer and at least one insulation layer are formed one on top of the other on the first surface. The wiring layer formed on the first surface is electrically connected to the semiconductor chip. The insulation layer has a reinforcement member installed therein.

Semiconductor package and method for manufacturing the same

Manufacturing a semiconductor package includes preparing a semiconductor chip having a top surface with bumps electrically connected to bonding pads, a bottom surface opposite to the top surface and side surfaces joining the top surface to the bottom surface. The bottom surface of the semiconductor chip is attached to a base substrate. A heat pressure process is performed to form a wiring support member on the base substrate to cover the top surface and the side surfaces of the semiconductor chip while exposing each of the bumps. Wirings are formed to be electrically connected to the bumps on the wiring support member. The base substrate is removed from the semiconductor chip and the wiring support member.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Chip-packaging module for a chip and a method for forming a chip-packaging module

A chip-packaging module for a chip is provided, the chip-packaging module including an isolation material configured to cover a chip on at least one side, the isolation material having a first surface proximate to a first side of a chip, and said isolation material having a second surface facing an opposite direction to the first surface; and at least one layer in connection with the chip first side, the at least one layer further configured to extend from the chip first side to the second surface of the isolation material.

On-chip interconnects with reduced capacitance and method of afbrication

An electronics interconnection system is provided with reduced capacitance between a signal line and the surrounding dielectric material. By using a non-homogenous dielectric, the effective dielectric constant of the material is reduced. This reduction results in less power loss from the signal line to the dielectric material, and therefore reduces the number of buffers needed on the signal line. This increases the speed of the signal, and reduces the power consumed by the interconnection system. The fabrication techniques provided are advantageous because they can be preformed using today's standard IC fabrication techniques.

Stacked wafer level package having a reduced size

A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

Component-embedded substrate

In a component-embedded substrate, a component and wiring block units are embedded in a component-embedded layer; conductive layers are located on all surfaces of the wiring block units; the component and the wiring block units are arranged such that lower surface side conductive layers of the wiring block units and electrodes of the component contact lower surface side wiring layers; via-hole conductors are located in respective upper positions relative to upper surface side conductive layers of the wiring block units and the electrodes of the component; and upper surface side wiring layers of the component-embedded layer are thus electrically connected to upper surface side conductive layers of the wiring block units, and the electrodes of the component by the via-hole conductors.

3D Integrated Microelectronic Assembly With Stress Reducing Interconnects And Method Of Making Same

A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handier with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.

Semiconductor package, electrical and electronic apparatus including the semiconductor package, and method of manufacturing the semiconductor package

In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.

Integrated circuit packaging system with interconnects and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit to the substrate; attaching a vertical interconnect over the substrate; forming an encapsulation on the substrate and covering the vertical interconnect; and forming a rounded cavity, having a curved side, in the encapsulation with the vertical interconnect exposed in the rounded cavity.

Semiconductor device package and method of manufacturing thereof

A semiconductor device package includes a semiconductor device having connection pads formed thereon, with the connection pads being formed on first and second surfaces of the semiconductor device with edges of the semiconductor device extending therebetween. A first passivation layer is applied on the semiconductor device and a base dielectric laminate is affixed to the first surface of the semiconductor device that has a thickness greater than that of the first passivation layer. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface and the edges of the semiconductor device, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate sheet to form a connection with the connection pads.

Fabrication method of packaging substrate having through-holed interposer embedded therein

A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.

Semiconductor Device and Method of Manufacturing a Semiconductor Device Including Grinding Steps

A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.

Method of processing at least one die and die arrangement

In various embodiments, a method of processing at least one die may include: forming at least one placeholder element over at least one contact pad of at least one die; forming a die embedding layer to at least partially embed the at least one die and the at least one placeholder element; removing the at least one placeholder element to form at least one opening in the at least one die embedding layer and expose the at least one contact pad of the at least one die; filling the at least one opening with electrically conductive material to electrically contact the at least one contact pad of the at least one die.

Semiconductor Chip Package and Method

A semiconductor chip package and a method to manufacture a semiconductor chip package are disclosed. An embodiment of the present invention comprises a substrate and a semiconductor chip disposed on the substrate and laterally surrounded by a packaging material. The package further comprises a current rail adjacent the semiconductor chip, the current rail isolated from the semiconductor chip by an isolation layer, a first external pad, and a via contact contacting the current rail with the first external pad.

Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

Integrated circuit and method of making

Circuits and methods of fabricating circuits are disclosed herein. An embodiment of the circuit includes a die having a side, wherein a connection point is located on the side. A dielectric layer having a first side, a second side, and at least one via extending between the first side and the second side, is located proximate the side of the die. The via is electrically connected to the connection point. A conductive layer is located adjacent the second side of the first dielectric layer, wherein at least a portion of the conductive layer is electrically connected to the via.

Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate

A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with at least one external component. The substrate can have substrate contacts on the first surface facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid.

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Semiconductor Device and Method of Laser-Marking Laminate Layer Formed Over EWLB With Tape Applied to Opposite Surface

A semiconductor device has a semiconductor die with a plurality of bumps formed on contact pads disposed over its active surface. An encapsulant is formed over the semiconductor die. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die is mounted to a translucent tape with the bumps embedded in the translucent tape. The translucent tape has layers of polyolefin, acrylic, and polyethylene terephthalate. A back surface of the semiconductor die undergoes backgrinding to reduce die thickness. The tape undergoes UV curing. A laminate layer is formed over the back surface of the semiconductor die. The laminate layer undergoes oven curing. The laminate layer is laser-marked while the tape remains applied to the bumps. The tape is removed after laser-marking the laminate layer. Alternately, the tape can be removed prior to laser-marking. The tape reduces die warpage during laser-marking.

Embedded Electrical Component Surface Interconnect

An electrical component package is disclosed comprising: an electrical component having an embedded surface, a structure attached to the electrical component opposite the embedded surface, a conductive adhesive directly attached to the embedded surface, where the conductive adhesive is shaped to taper away from the embedded surface, and an encapsulation material covering the conductive adhesive and the electrical component. In various embodiments, the tapered conductive adhesive facilitates the securing of the conductive adhesive to the electrical component by the encapsulation material. Also disclosed are various methods of forming an electrical component package having a single interface conductive interconnection on the embedded surface. The conductive interconnection is configured to maintain an interconnection while under stress forces. Further disclosed in a method of applied a conductive adhesive that enables design flexibility regarding the shape and depth of the conductive interconnection.

Method of manufacturing semiconductor device and method of manufacturing electronic device

A method of manufacturing a semiconductor device, includes: providing a first adhesive layer on a support member; providing a film on the first adhesive layer; arranging a semiconductor element on the film; providing a resin layer on the film on which the semiconductor element is arranged, and forming a substrate including the semiconductor element and the resin layer on the film; and separating the film and the substrate from the first adhesive layer.

Semiconductor chip package, semiconductor module, and method for manufacturing same

In one embodiment, a semiconductor chip package includes an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip disposed cm the opening part; a conductive part filling the via hole; an inner insulation layer formed on bottom surfaces of the semiconductor chip and the insulation frame so as to expose a bottom surface of the conductive part; and an inner signal pattern formed on the inner insulation layer and electrically connecting the semiconductor chip and the conductive part. Embodiments also relate to a semiconductor module including a vertical stack of a plurality of the semiconductor chip packages, and to a method for manufacturing the same.

Integrated Antennas in Wafer Level Package

A semiconductor module having one or more integrated antennas in a single package is provided herein. The semiconductor module has a bonding interconnect structure that connects an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package. 1. A semiconductor module , comprising:a package comprising an integrated circuit (IC) device embedded within a package molding compound layer; andan interface layer comprising:a redistribution layer coupled to the IC device and the package molding compound layer;at least one integrated antenna structure comprised within the interface layer and coupled to the IC device; anda bonding interconnect structure having three dimensional interconnect structures configured to physically and electrically connect the IC device externally from the package molding compound layer to a printed circuit board (PCB) at a connection area located in a position that supports the package as a cantilevered structure, wherein at least part of one or more of the at least one integrated antenna structures is outside of the connection area.2. The module of claim 1 , wherein the connection area is located at the center of the package to form a double cantilever structure having portions of the package extending beyond the connection area in two opposite directions.3. The module of claim 1 , wherein the at least one of the integrated antenna structures is configured at greater center-to-center distance from the IC ...

Fully molded fan-out

A method for manufacturing a device package may include constructing a spacer element coupled with a surface of a semiconductor die unit, where the spacer element is configured to create a gap between the semiconductor die unit and a surface of a carrier, and encapsulating the semiconductor die unit within a mold compound, where the encapsulating includes introducing the mold compound into the gap.

Method for producing semiconductor device

A method for producing a semiconductor device, including a semiconductor chip, for improving production efficiency and the flexibility of production design is provided. The method comprises: preparing a semiconductor chip having a first main surface on which an electroconductive member is formed; preparing a supporting structure in which, over a support configured to transmit radiation, a radiation curable pressure-sensitive adhesive layer and a first thermosetting resin layer are laminated in this order; arranging the semiconductor chips on the first thermosetting resin layer to face the first thermosetting resin layer to a second main surface of the semiconductor chips opposite to the first main surface; laminating a second thermosetting resin layer over the first thermosetting resin layer to cover the semiconductor chips; and curing the radiation curable pressure-sensitive adhesive layer by irradiating from the support side to peel the radiation curable pressure-sensitive adhesive layer from the first thermosetting resin layer.

Method Of Making 3D Integration Microelectronic Assembly For Integrated Circuit Devices

A microelectronic assembly for packaging/encapsulating IC devices, which includes a crystalline substrate handler having opposing first and second surfaces and a cavity formed into the first surface, a first IC device disposed in the cavity and a second IC device mounted to the second surface, and a plurality of interconnects formed through the crystalline substrate handler. Each of the interconnects includes a hole formed through the crystalline substrate handler from the first surface to the second surface, a compliant dielectric material disposed along the hole's sidewall, and a conductive material disposed along the compliant dielectric material and extending between the first and second surfaces. The compliant dielectric material insulates the conductive material from the sidewall. The second IC device, which can be an image sensor, is electrically coupled to the conductive materials of the plurality of interconnects. The first IC can be a processor for processing the signals from the image sensor.

Method Of Forming 3D Integrated Microelectronic Assembly With Stress Reducing Interconnects

A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handler with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.

Wafer-level device packaging

The present invention relates to a semiconductor device packaged at the wafer level such that an entire packaged device is formed prior to separation of individual devices. The semiconductor device package includes a semiconductor chip having one or more bonding pads associated with the chip and a protective layer bonded over the semiconductor chip. An insulation layer is positioned on at least side edges and a lower surface of the semiconductor chip. Interconnection/bump metallization is positioned adjacent one or more side edges of the semiconductor chip and is electrically connected to at least one bonding pad. A compact image sensor package can be formed that is vertically integrated with a digital signal processor and memory chip along with lenses and a protective cover.

Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias

A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

METHODS OF MAKING COMPLIANT SEMICONDUCTOR CHIP PACKAGES

A semiconductor chip package is fabricated including providing a compliant layer over a contact bearing face of a semiconductor chip, with a bottom surface of the compliant layer adjacent that chip face, a top surface facing away from the bottom surface, and at least one sloping surface extending between the top and bottom surfaces. Bond ribbons can be formed atop the compliant layer, each bond ribbon electrically coupling one of the contacts with an associated conductive terminal at the top surface of the compliant layer. A bond ribbon can include a strip extending along the sloping surface. The strip may have a substantially constant thickness in a direction away from the sloping surface. 1. (canceled)2. A compliant semiconductor chip package assembly comprising:a semiconductor chip having a major surface and plurality of chip contacts at said major surface;a compliant layer having a bottom surface adjacent to said major surface, a top surface raised above and remote from said major surface and a sloped surface between said top and bottom surfaces and adjacent at least one of the chip contacts, wherein the bottom surface of the compliant layer is fully spaced apart from each of the chip contacts in a lateral direction parallel to said major surface; anda bond ribbon formed of electrically conductive material deposited to overlie and extend along said sloped surface from said bottom surface to said top surface of said compliant layer, said bond ribbon electrically coupled to said at least one chip contact.3. The assembly as claimed in claim 2 , wherein the bond ribbon is a strip of electrically conductive material overlying and extending along the sloped surface from the bottom surface to the top surface.4. The assembly as claimed in claim 2 , further comprising an electrically conductive terminal overlying said semiconductor chip claim 2 , wherein said compliant layer supports said terminal over said semiconductor chip.5. The assembly as claimed in claim 2 , ...

Method of manufacturing semiconductor device

In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

Passive Devices in Package-on-Package Structures and Methods for Forming the Same

A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the polymer, wherein the TAVs are coupled in series. A Redistribution Line (RDL) is underlying the polymer. The RDL electrically couples a first one of the TAVs to a second one of the TAVs.

Compliant printed circuit semiconductor package

A method of making a package for a semiconductor device having electrical terminals. At least one semiconductor device is located on a substrate. A first dielectric layer is printed on at least a portion of the semiconductor device to include first recesses aligned with a plurality of the electrical terminals. A conductive material is deposited in the first recesses forming contact members. A second dielectric layer is printed on at least a portion of the first dielectric layer to include second recesses aligned with a plurality of the first recesses. A conductive material is deposited in at least a portion of the second recesses to include a circuit geometry and a plurality of exposed terminals. A compliant material is deposited in recesses in one or more of the first and second dielectric layers adjacent to a plurality of the exposed terminals.

Semiconductor package and method of manufacturing the same

Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.

Method of fabricating semiconductor package structure

A semiconductor package structure is provided, including: a semiconductor chip having electrode pads disposed thereon and metal bumps disposed on the electrode pads; an encapsulant encapsulating the semiconductor chip; a dielectric layer formed on the encapsulant and having a plurality of patterned intaglios formed therein for exposing the metal bumps; a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps; and a metal foil having a plurality of metal posts disposed on a surface thereof such that the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip. Compared with the prior art, the present invention reduces the overall thickness of the package structure, increases the electrical transmission efficiency and improves the heat dissipating effect.

High density second level interconnection for bumpless build up layer (bbul) packaging technology

An apparatus including a die including a device side; and a build-up carrier including a body including a plurality of alternating layers of conductive material and dielectric material disposed on the device side of the die, an ultimate conductive layer patterned into a plurality of pads or lands; and a grid array including a plurality of conductive posts disposed on respective ones of the plurality of pads of the ultimate conductive layer of the body, at least one of the posts coupled to at least one of the contact points of the die through at least a portion of the conductive material of the body. A method including forming a body of a build-up carrier including a die, the body of the build-up carrier including an ultimate conductive layer and forming a grid array including a plurality of conductive posts on the ultimate conductive layer of the body.

Novel three dimensional integrated circuits stacking approach

A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer die are provided. By forming a first redistribution structure over the interposer die with TSVs, the die(s) bonded to the interposer die can have edge(s) beyond the boundary of the interposer die. In addition, a second redistribution structure may be formed on the opposite surface of the interposer die from the redistribution structure. The second redistribution structure enables reconfiguration and fan-out of bonding structures for external connectors of the interposer die.

Thermally Enhanced Package-on-Package (PoP)

A method and structure for providing improved thermal management in multichip and package on package (PoP) applications. A first substrate attached to a second smaller substrate wherein the second substrate is encircled by a heat ring attached to the first substrate, the heat ring comprising heat conducting materials and efficient heat dissipating geometries. The first substrate comprises a heat generating chip and the second substrate comprises a heat sensitive chip. A method is presented providing the assembled structure with increased heat dissipation away from the heat sensitive chip.

TWO-SIDED-ACCESS EXTENDED WAFER-LEVEL BALL GRID ARRAY (eWLB) PACKAGE, ASSEMBLY AND METHOD

A two-sided-access (TSA) eWLB is provided that makes it possible to easily access electrical contact pads disposed on both the front and rear faces of the die(s) of the eWLB package. When fabricating the IC die wafer, metal stamps are formed in the IC die wafer in contact with the rear faces of the IC dies. When the IC dies are subsequently reconstituted in an artificial wafer, portions of the metal stamps are exposed through the mold of the artificial wafer. When the artificial wafer is sawed to singulate the TSA eWLB packages and the packages are mounted on PCBs, any electrical contact pad that is disposed on the rear face of the IC die can be accessed via the respective metal stamp of the IC die.

Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.

METHODS OF FORMING MOLDED PANEL EMBEDDED DIE STRUCTURES

Methods of forming molded panel coreless package structures are described. Those methods and structures may include fabrication of embedded die packages using large panel format and use of molding to improve rigidity of the panel, as well as to embed the die in a non-sacrificial mold material. The methods and structures described include methods for manufacturing thin, coreless substrate architectures which possess low warpage. 1. A method of forming a packaging structure comprising:forming a first thin foil on a first side of a base foil and a second thin foil on a second side of the base foil;attaching at least one die directly on the first thin foil and attaching at least one die directly on the second thin foil;forming a molding material on the first thin foil and forming a molding material on the second thin foil, wherein the at least one die are embedded in the molding material; andforming at least one build up layer on the molding material disposed on the first thin foil and forming at least one build up layer on the molding material disposed on the second thin foils.2. The method of further comprising wherein the molding material comprises a non-sacrificial molding material.3. The method of further comprising wherein the molding material is applied to the first and second thin foil by using a compression technique.4. The method of further comprising forming conductive bumps on the at least one build up layer.5. The method of further comprising wherein the at least one die is embedded in the molding material.6. The method of further comprising wherein the package structure comprises a dual sided molded panel structure claim 1 , wherein a first molded panel is disposed on the first side of the base foil claim 1 , and a second molded panel is disposed on the second side of the base foil.7. The method of further comprising de-paneling the first molded panel from the first side of the base foil claim 6 , and de-paneling the second molded panel from the second ...

SEMICONDUCTOR PACKAGES AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGES

A semiconductor package includes a redistribution wiring layer having redistribution wirings, a semiconductor chip on the redistribution wiring layer, a frame on the redistribution wiring layer, the frame surrounding the semiconductor chip, and the frame having core connection wirings electrically connected to the redistribution wirings, and an antenna structure on the frame, the antenna structure including a ground pattern layer, a first antenna insulation layer, a radiator pattern layer, a second antenna insulation layer, and a director pattern layer sequentially stacked on one another. 1. A semiconductor package , comprising:a redistribution wiring layer having redistribution wirings;a semiconductor chip on the redistribution wiring layer;a frame on the redistribution wiring layer, the frame surrounding the semiconductor chip, and the frame having core connection wirings electrically connected to the redistribution wirings; andan antenna structure on the frame, the antenna structure including a ground pattern layer, a first antenna insulation layer, a radiator pattern layer, a second antenna insulation layer, and a director pattern layer sequentially stacked on one another.2. The semiconductor package as claimed in claim 1 , wherein the first antenna insulation layer has a first thermal expansion coefficient claim 1 , and the second antenna insulation layer has a second thermal expansion coefficient smaller than the first thermal expansion coefficient.31314. The semiconductor package as claimed in claim 2 , wherein the second thermal expansion coefficient is within a range of / to / of the first thermal expansion coefficient.4. The semiconductor package as claimed in claim 2 , wherein the second thermal expansion coefficient of the second antenna insulation layer is a same as a thermal expansion coefficient of the frame.5. The semiconductor package as claimed in claim 1 , wherein the first antenna insulation layer has a first thickness claim 1 , and the second ...

THREE-DIMENSIONAL MEMORY DEVICES HAVING HYDROGEN BLOCKING LAYER AND FABRICATION METHODS THEREOF

Embodiments of three-dimensional (3D) memory devices have a blocking layer and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, an array of NAND memory strings each extending vertically through the memory stack, a plurality of logic devices above the array of NAND memory strings, a semiconductor layer above and in contact with the logic devices, a pad-out interconnect layer above the semiconductor layer, and a blocking layer vertically between the semiconductor layer and the pad-out interconnect layer and configured to block outgassing of hydrogen. 1. A memory device , comprising:a memory array;a plurality of logic devices above the memory array;a semiconductor layer above and in contact with the logic devices;a pad-out interconnect layer above the semiconductor layer; anda blocking layer vertically between the semiconductor layer and the pad-out interconnect layer,wherein the semiconductor layer is vertically between the plurality of logic devices and the blocking layer.2. The memory device of claim 1 , wherein the blocking layer comprises a high dielectric constant (high-k) dielectric material.3. The memory device of claim 1 , wherein a thickness of the blocking layer is between about 1 nm and about 100 nm.4. The memory device of claim 1 , wherein the blocking layer extends laterally to cover the semiconductor layer.5. The memory device of claim 1 , wherein the blocking layer is configured to block outgassing of the hydrogen from the logic devices into or beyond the pad-out interconnect layer during fabrication of the memory device.6. The memory device of claim 1 , further comprising:a first bonding layer above the memory array and comprising a plurality of first bonding contacts;a second bonding layer below the logic devices and above the first bonding layer and comprising a plurality of second bonding contacts; anda ...

INTERCONNECT STRUCTURES

Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers. 1. (canceled)2. A method of manufacturing a device , the method comprising:forming a cavity in a substrate extending at least partially through a thickness of the substrate from a surface of the substrate;providing a conductive material in the cavity and over the surface of the substrate;removing a portion of the conductive material thereby forming a recess on an upper surface of the conductive material;providing a fill layer over the upper surface of the conductive material and the surface of the substrate;removing a portion of the fill layer; andforming a second cavity in the substrate extending at least partially though the thickness of the substrate from the surface of the substrate, a width of the second cavity being wider than a width of the cavity.3. The method of claim 1 , further comprising polishing the surface of the substrate.4. The method of claim 1 , further comprising preparing the substrate for direct bonding.5. The method of claim 1 , wherein the removing the portion of the fill layer comprises preparing the substrate for direct bonding.6. The method of claim 1 , wherein the removing the portion of the fill layer defines a bonding ...

SEMICONDUCTOR PACKAGE INCLUDING INTERPOSER AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate. 1. A semiconductor package comprising:a package substrate;a semiconductor chip on the package substrate;an interposer substrate on the semiconductor chip, the interposer substrate comprising a first surface facing the semiconductor chip and a trench in the first surface, the trench located to vertically overlap the semiconductor chip; andan insulating filler between the semiconductor chip and the interposer substrate, the insulating filler at least partially filling the trench of the interposer substrate.2. The semiconductor package of claim 1 ,wherein the interposer substrate comprises a first side wall and a second side wall opposite to and facing each other, andwherein the trench extends from the first side wall of the interposer substrate to the second side wall of the interposer substrate.3. The semiconductor package of claim 1 ,wherein the interposer substrate comprises a base insulating layer, and a lower protection insulating layer on a lower surface of the base insulating layer facing the semiconductor chip, andwherein the trench is provided in the lower protection insulating layer.4. The semiconductor package of claim 3 ,wherein the interposer substrate comprises a conductive pattern disposed in the trench, andwherein the conductive pattern comprises an upper surface in contact with the base insulating layer, a lower surface in contact with the lower protection insulating layer and a side wall in contact with the lower protection insulating layer.5. The semiconductor ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first redistribution structure having a first surface in which a first pad and a second pad are embedded and including a first redistribution layer thereon, and a vertical connection structure including a land layer and a pillar layer. The land layer is embedded in the first surface of the first redistribution structure, and a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer. 1. A semiconductor package comprising:a first redistribution structure having a first surface comprising a first pad and a second pad therein, and a second surface opposite the first surface and comprising a first redistribution layer electrically connected to the first pad and the second pad;a vertical connection structure comprising a land layer on the first pad, and a pillar layer on the land layer and electrically connected to the first redistribution layer;a semiconductor chip on the first surface of the first redistribution structure and comprising a connection electrode electrically connected to the second pad;a first encapsulant on at least a portion of the vertical connection structure and comprising a cavity sized to accept the semiconductor chip;a second encapsulant on the first encapsulant and in the cavity; anda first connection bump on the second surface of the first redistribution structure and electrically connected to the first redistribution layer,wherein the land layer is in the first surface of the first redistribution structure, anda width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer thereon.2. The semiconductor package of claim 1 , wherein a thickness of the first pad is greater than a thickness of the land layer of the vertical connection structure.3. The semiconductor package of claim 2 , wherein a thickness of the pillar layer is in a range of about 100 μm to about 200 μm claim 2 ,the thickness of the land layer is in a ...

MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers. Each redistribution structure in the multiple stacked tiers includes redistribution patterns, the redistribution structure closest to the first semiconductor die further includes a thermally conductive layer connected to the first semiconductor die, wherein a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally conductive layer of the redistribution structure closest to the first semiconductor die, and the thermally conductive layer is electrically isolated from the second semiconductor dies in the multiple stacked tiers and the first semiconductor die. 1. A memory device , comprising:a first semiconductor die; and second semiconductor dies laterally wrapped by an encapsulant; and', 'a redistribution structure disposed on the second semiconductor dies and the encapsulant, wherein the second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers, each redistribution structure in the multiple stacked tiers includes redistribution patterns, the redistribution structure closest to the first semiconductor die further includes a thermally conductive layer connected to the first semiconductor die, a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally ...

Integrated circuit packages and methods of forming same

An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view.

Electronic assembly having multiple substrate segments

An electronic assembly (100) includes a mechanical carrier (102), a plurality of integrated circuits (104A, 104B) disposed on the mechanical carrier, a fan out package (108) disposed on the plurality of integrated circuits, a plurality of singulated substrates (112A, 112B) disposed on the fan out package, a plurality of electronic components (114A, 114B) disposed on the plurality of singulated substrates, and at least one stiffness ring (116A, 116B, 116C) disposed on the plurality of singulated substrates. A method for constructing an electronic assembly includes identifying a group of known good singulated substrates, joining the group of known good singulated substrates into a substrate panel, attaching at least one bridge to the substrate panel that electrically couples at least two of the known good singulated substrates, and mounting a plurality of electronic components onto the substrate panel, each electronic component of the plurality of electronic components corresponding to a respective known good singulated substrate.

Semiconductor Package and Method

In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

Electronic circuit device and method of manufacturing electronic circuit device

The electronic circuit device according to the present invention including the wiring layer 13 including a plurality of the metal wirings, the photosensitive resin layer 21 made of the photosensitive resin arranged on the wiring layer 13, and the first electronic circuit element 33 arranged in the photosensitive resin layer 21. In this electronic circuit device, a plurality of opening 41 for exposing a part of the wiring layer 13 is formed on the photosensitive resin layer 21, and further, together with three-dimensionally connected to the first electronic circuit element 33, the re-distribution layer 42 on the first electronic circuit element including a plurality of the metal wirings which is three-dimensionally connected via a plurality of openings to a part of the wiring layer 13, and the first external connection terminal 51 connected to the re-distribution layer 42 are formed.

Multi-Stacked Package-on-Package Structures

A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material. 1. A package structure , comprising:a first dielectric layer;a first semiconductor device over the first dielectric layer;a first redistribution line in the first dielectric layer;a second dielectric layer over the first semiconductor device;a second semiconductor device over the second dielectric layer;a second redistribution line in the second dielectric layer;a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line;a conductive ball over the conductive through-via and electrically connected to the second redistribution line; anda molding material surrounding the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.2. The package structure of claim 1 , wherein a bottom of the conductive ball is lower than the top of the molding material.3. The package structure of claim 1 , wherein the molding material has a portion vertically overlapping the first semiconductor device.4. The package structure of claim 1 , wherein the top of the molding material is higher than a top of the first semiconductor ...

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first interconnect structure over the substrate;disposing a first semiconductor die over the first interconnect structure;disposing the substrate over a carrier with the first semiconductor die oriented away from the carrier;depositing an encapsulant over the carrier, substrate, and first semiconductor die;forming a second interconnect structure over the encapsulant and semiconductor die; andremoving the substrate to expose the first interconnect structure after forming the second interconnect structure.2. The method of claim 1 , further including forming a conductive column over the first interconnect structure.3. The method of claim 2 , wherein the conductive column extends from the first interconnect structure to the second interconnect structure ...

Multi-Stack Package-on-Package Structures

A package includes a first device die, and a first encapsulating material encapsulating the first device die therein. A bottom surface of the first device die is coplanar with a bottom surface of the first encapsulating material. First dielectric layers are underlying the first device die. First redistribution lines are in the first dielectric layers and electrically coupling to the first device die. Second dielectric layers are overlying the first device die. Second redistribution lines are in the second dielectric layers and electrically coupling to the first redistribution lines. A second device die is overlying and electrically coupling to the second redistribution lines. No solder region connects the second device die to the second redistribution lines. A second encapsulating material encapsulates the second device die therein. A third device die is electrically coupled to the second redistribution lines. A third encapsulating material encapsulates the third device die therein. 1. A package comprising:a first interconnect structure comprising a plurality of dielectric layers and a first plurality of redistribution lines in the plurality of dielectric layers;a first device die over the first interconnect structure;a first encapsulant encapsulating the first device die therein;a second interconnect structure over the first encapsulant, wherein the second interconnect structure comprises a second plurality of redistribution lines therein;a first plurality of through-vias penetrating through the first encapsulant, wherein the first plurality of through-vias electrically connect the first plurality of redistribution lines to the second plurality of redistribution lines;a second device die over and bonding to the second interconnect structure, wherein the second device die comprises a semiconductor substrate, and a second plurality of through-vias penetrating through the semiconductor substrate;a second encapsulant encapsulating the second device die therein; anda ...

Semiconductor Device and Method of Manufacture

A semiconductor device and method of making a conductive connector is provided. In an embodiment an opening is formed within a photoresist by adjusting the center point of an in-focus area during the exposure process. Once the photoresist has been developed to form an opening, an after development baking process is utilized to reshape the opening. Once reshaped, a conductive material is formed into the opening to take on the shape of the opening. 1. A method of manufacturing a semiconductor device , the method comprising:applying a photoresist over a seed layer;exposing the photoresist to a patterned energy source, the patterned energy source having an in-focus area with a center point, the center point located below a surface of the photoresist facing towards the seed layer;developing the photoresist to form an opening; andplating an external connector into the opening.2. The method of claim 1 , further comprising annealing the photoresist after the developing the photoresist claim 1 , wherein the annealing the photoresist reshapes the opening.3. The method of claim 2 , wherein the annealing the photoresist raises a temperature of the photoresist to between about no ° C. and about 130° C.4. The method of claim 1 , wherein the center point is located below the surface of the photoresist a distance of between about 60 μm and about 70 μm.5. The method of claim 1 , further comprising removing a portion of the seed layer not covered by the external connector.6. The method of claim 1 , wherein the developing the photoresist comprises removing an unexposed portion of the photoresist.7. The method of claim 1 , wherein the seed layer is located over an encapsulant around a semiconductor device and a through encapsulant via.8. A method of manufacturing a semiconductor device claim 1 , the method comprising:exposing a photoresist to a patterned energy source, the photoresist being located over an encapsulant located between a semiconductor die and a through encapsulant via; ...

Package-on-package structure and method of manufacturing package

A package-on-package (PoP) structure includes a first package and a second package stacked on the first package. The first package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The die includes an amorphous layer located on the rear surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is on the active surface of the die and is electrically connected to the conductive structures and the die.

Inductor module

An inductor module includes an insulating flexible substrate including a thermoplastic resin, an IC element included in the flexible substrate, chip capacitors included in the flexible substrate, a chip inductor that includes a magnetic-material body and is located on a first main surface of the flexible substrate, and input and output terminals on a second main surface of the flexible substrate. The IC element may be a switching IC element, the chip inductor may be a choke coil, and the inductor module may be a DC/DC converter module.

Method of Forming RDLS and Structure Formed Thereof

A method includes encapsulating a device die in an encapsulating material, planarizing the device die and the encapsulating material, and forming a first plurality of conductive features electrically coupling to the device die. The step of forming the first plurality of conductive features includes a deposition-and-etching process, which includes depositing a blanket copper-containing layer, forming a patterned photo resist over the blanket copper-containing layer, and etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer. 1. A method comprising:encapsulating a device die in an encapsulating material; and depositing a blanket copper-containing layer;', 'forming a patterned photo resist over the blanket copper-containing layer; and', 'etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer., 'forming a first plurality of conductive features electrically coupling to the device die, wherein the forming the first plurality of conductive features comprises a deposition-and-etching process comprising2. The method of claim 1 , wherein the first plurality of conductive features have tilted sidewalls having tilt angles smaller than about 85 degrees.3. The method of claim 1 , wherein the forming the first plurality of conductive features further comprises:depositing a hard mask over the blanket copper-containing layer; andetching the hard mask using the patterned photo resist as an etching mask, wherein the blanket copper-containing layer is etched using the etched hard mask as an etching mask.4. The method of further comprising depositing an adhesion layer claim 3 , with the adhesion layer and the hard mask being formed of a same material claim 3 , wherein the blanket copper-containing layer is over and contacting the adhesion layer.5. The method of claim 3 , wherein the hard mask is etched in a wet etching process. ...

SEMICONDUCTOR PACKAGE HAVING REDISTRIBUTION LAYER

A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias. 1. A semiconductor package comprising:a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity;a first semiconductor chip in the cavity;a plurality of conductive vias in the plurality of through holes;a first redistribution layer on the silicon substrate, the first redistribution layer connected to the first semiconductor chip and the plurality of conductive vias; anda second redistribution layer below the silicon substrate, the second redistribution layer connected to the first semiconductor layer and the plurality of conductive vias.2. The semiconductor package of claim 1 , further comprising: 'the first encapsulant is between an inner side surface of the cavity and a side surface of the first semiconductor chip.', 'a first encapsulant in the cavity,'}3. The semiconductor package of claim 2 , further comprising: 'the adhesive is between the first encapsulant and the second redistribution layer.', 'an adhesive in the cavity, wherein'}4. The semiconductor package of claim 1 , whereinan upper end of the first semiconductor chip and a lower end of the first semiconductor chip are respectively located at a same level as an upper end of the silicon substrate and a lower end of the silicon substrate.5. The semiconductor package of claim 1 , whereinthe first semiconductor chip includes a through electrode, andthe through electrode passes through the first semiconductor chip in a vertical direction.6. The semiconductor ...

STIFFENER-INTEGRATED INTERCONNECT BYPASSES FOR CHIP-PACKAGE APPARATUS AND METHODS OF ASSEMBLING SAME

A stiffener includes an integrated cable-header recess that couples a semiconductor package substrate flexible cable. The flexible cable connects to a device on a board without using interconnections that are arrayed through the board. A semiconductive die is coupled to the semiconductor package substrate and flexible cable through the cable-header recess. 1. A semiconductor package frame stiffener , comprising:a frame stiffener body including a top surface and a die-side ledge that is opposite the top surface, further including a die-side interconnect surface that is opposite the top surface, and further including a land-side interconnect surface that is parallel planar with the die-side interconnect surface;a through hole that communicates from the top surface to the die-side ledge, and from the top surface to the die-side interconnect surface:an integrated cable-header recess that communicates to the top surface, wherein the integrated cable-header recess is adjacent to the die-side interconnect surface and adjacent to the land-side interconnect surface; anda through-frame-stiffener interconnect (TFSI) that communicates from the land-side interconnect surface, through the frame stiffener and into the integrated cable-header recess.2. The semiconductor package frame stiffener of claim 1 , further including a cable header electrically coupled to the TFSI.3. The semiconductor package frame stiffener of claim 1 , further including:a cable header electrically coupled to the TFSI; anda flexible cable coupled to the cable header.4. The semiconductor package frame stiffener of claim 1 , further including:a cable header electrically coupled to the TFSI;a flexible cable coupled to the cable header;a passive device opposite the integrated cable-header recess, wherein the passive device is coupled to a folded redistribution layer at the land-side interconnect surface;a semiconductor package substrate including a die side and a land side, wherein the die side is in contact ...

Electric Magnetic Shielding Structure in Packages

A package includes a device die, a molding material molding the device die therein, and a through-via penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via. A metal ring is close to edges of the package, wherein the metal ring is coplanar with the redistribution line. 1. A method comprising:encapsulating a device die in an encapsulating material; and forming a first portion over the encapsulating material;', 'forming a second portion under the encapsulating material; and', 'forming a plurality of through-vias penetrating through the encapsulating material, wherein the plurality of through-vias electrically connects the first portion to the second portion of the metal shield, and wherein the device die and the metal shield are in a package., 'forming a metal shield to enclose the device die therein, wherein the forming the metal shield comprises2. The method of claim 1 , wherein the forming the first portion of the metal shield comprises forming a metal ring claim 1 , with each side-portion of the metal ring adjacent to and parallel to a respective edge of the package.3. The method of claim 2 , wherein the forming the first portion of the metal shield further comprises forming a metal ring extension encircled by the metal ring claim 2 , wherein the metal ring extension is connected to the metal ring.4. The method of further comprising electrically grounding the metal shield.5. The method of claim 4 , wherein the electrically grounding the metal shield is achieved by electrically connecting the metal shield through a plurality of solder regions claim 4 , each located at a corner of the package.6. The method of claim 1 , wherein the plurality of through-vias comprises four corner through-vias claim 1 , each at a corner of the package claim 1 , and the method further comprises:attaching four solder regions to electrically coupling to the metal shield, each ...

EMI Shielding Structure in InFO Package

A method includes forming a metal post over a first dielectric layer, attaching a second dielectric layer over the first dielectric layer, encapsulating a device die, the second dielectric layer, a shielding structure, and the metal post in an encapsulating material, planarizing the encapsulating material to reveal the device die, the shielding structure, and the metal post, and forming an antenna electrically coupling to the device die. The antenna has a portion vertically aligned to a portion of the device die. 1. A device comprising:a device die;an encapsulating material;a shielding structure encapsulated in the encapsulating material, wherein the device die is in the shielding structure;a through-via penetrating through the encapsulating material; andan antenna having at least a portion overlapping the shielding structure, wherein the antenna is electrically connected to the device die through the through-via.2. The device of claim 1 , wherein the shielding structure comprises:a conductive cap over the device die; anda side-shielding structure underlying and connected to the conductive cap, wherein the side-shielding structure forms a ring encircling the device die.3. The device of claim 2 , wherein the device die and the shielding structure are both encapsulated in the encapsulating material claim 2 , and edges of the conductive cap are in contact with the encapsulating material to form interfaces.4. The device of further comprising a die-attach film claim 2 , wherein the device die is attached to a surface of the conductive cap through the die-attach film.5. The device of claim 2 , wherein the conductive cap and the side-shielding structure have distinguishable interfaces in between.6. The device of claim 1 , wherein the shielding structure is an integrated unit formed of a homogeneous material.7. The device of claim 1 , wherein the shielding structure comprises a conductive paste.8. A device comprising:a molding compound; a top portion; and', 'a first ...

Mixing Organic Materials into Hybrid Packages

A method includes forming an interposer, which includes a semiconductor substrate, and an interconnect structure over the semiconductor substrate. The method further includes bonding a device die to the interposer, so that a first metal pad in the interposer is bonded to a second metal pad in the device die, and a first surface dielectric layer in the interposer is bonded to a second surface dielectric layer in the device die. The method further includes encapsulating the device die in an encapsulating material, forming conductive features over and electrically coupling to the device die, and removing the semiconductor substrate. A part of the interposer, the device die, and portions of the conductive features in combination form a package. 1. A package comprising: an interposer;', 'a device die underlying and bonded to the interposer;', 'a first encapsulating material encapsulating the device die therein, wherein the first encapsulating material is overlapped by a portion of the interposer;, 'a device package comprisinga second encapsulating material encapsulating the device package therein;at least one dielectric layer overlapping the second encapsulating material and the device package; andconductive features in the at least one dielectric layer, wherein the conductive features are electrically coupled to the device die through the interposer.2. The package of claim 1 , wherein a first metal pad in the interposer is bonded to a second metal pad in the device die claim 1 , and a first surface dielectric layer in the interposer is bonded to a second surface dielectric layer in the device die.3. The package of further comprising a supporting substrate underlying a semiconductor substrate of the device die.4. The package of further comprising an additional dielectric layer on the supporting substrate claim 3 , wherein the additional dielectric layer is bonded to the semiconductor substrate of the device die.5. The package of claim 4 , wherein the additional ...

Integrated Circuit Packages and Methods of Forming Same

An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view. 1. A method comprising:forming a conductive column over a carrier;attaching an integrated circuit die to the carrier, the integrated circuit die being disposed adjacent the conductive column;forming an encapsulant around the conductive column and the integrated circuit die;removing the carrier to expose a first surface of the conductive column and a second surface of the encapsulant;forming a polymer material over and in physical contact with the first surface and the second surface; andcuring the polymer material to form an annular-shaped structure, wherein an inner edge of the annular-shaped structure overlaps the first surface in a plan view, and wherein an outer edge of the annular-shaped structure overlaps the second surface in the plan view.2. The method of claim 1 , wherein the polymer material comprises a UV curable polymer material.3. The method of claim 2 , wherein curing the polymer material comprises exposing the polymer material to UV light.4. The method of claim 1 , wherein the polymer material comprises a thermally curable polymer material.5. The method of claim 4 , wherein curing the polymer material comprises performing a thermal treatment on the polymer material.6. The ...

Release Film as Isolation Film in Package

A method includes forming a release film over a carrier, forming a metal post on the release film, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, decomposing a first portion of the release film to separate a second portion of the release film from the carrier, and forming an opening in the release film to expose the metal post.

Release Film as Isolation Film in Package

A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device. 1. A method comprising:forming a release film over a carrier;attaching a device over the release film through a die-attach film;encapsulating the device in an encapsulating material;performing a planarization on the encapsulating material to expose the device;forming redistribution lines to electrically couple to the device;detaching the device and the encapsulating material from the carrier while the die-attach film remains attached to the device;after the detaching of the device and the encapsulating material from the carrier, removing the die-attach film to expose a back surface of the device; andapplying a thermal conductive material on the back surface of the device.2. The method of further comprising:dispensing an underfill to contact the thermal conductive material.3. The method of claim 1 , wherein after the die-attach film is removed claim 1 , a recess is formed to extend into the encapsulating material claim 1 , and the thermal conductive material is filled into the recess.4. The method of claim 1 , wherein the thermal conductive material has a thermal conductivity higher than about 1 W/k*m.5. The method of claim 1 , wherein the thermal conductive material is selected from the group consisting of solder claim 1 , silver claim 1 , copper paste claim 1 , and combinations thereof.6. The method of further comprising:forming a metal post over the carrier, wherein the metal post is encapsulated in the encapsulating material, wherein in the removing the die-attach film, a portion of the ...

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package includes a semiconductor die, a first redistribution structure, a conductive structure, and an insulating encapsulant. The first redistribution structure includes a dielectric protrusion. The first redistribution structure includes a die attach region and a peripheral region surrounding the die attach region. The semiconductor die is disposed on the first redistribution structure within the die attach region. The dielectric protrusion is disposed in the peripheral region and extends in a thickness direction of the semiconductor die. The conductive structure is disposed on the first redistribution structure within the in the peripheral region and encapsulates the semiconductor dielectric protrusion. The conductive structure is electrically coupled to the first redistribution structure and the semiconductor die. The insulator is disposed on the first redistribution structure and encapsulates the semiconductor die and the conductive structure. 1. A semiconductor package , comprising:a semiconductor die;a first redistribution structure comprising a dielectric protrusion, wherein the first redistribution structure comprises a die attach region and a peripheral region surrounding the die attach region, the semiconductor die is disposed on the first redistribution structure within the die attach region, and the dielectric protrusion is disposed in the peripheral region and extends in a thickness direction of the semiconductor die;a conductive structure disposed on the first redistribution structure within the peripheral region and encapsulating the dielectric protrusion, wherein the conductive structure is electrically coupled to the first redistribution structure and the semiconductor die; andan insulating encapsulant disposed on the first redistribution structure and encapsulating the semiconductor die and the conductive structure.2. The semiconductor package of claim 1 , wherein the conductive structure comprises a recess complementary in shape ...

SEMICONDUCTOR DEVICE WITH INTEGRATED HEAT DISTRIBUTION AND MANUFACTURING METHOD THEREOF

A semiconductor package having an internal heat distribution layer and methods of forming the semiconductor package are provided. The semiconductor package can include a first semiconductor device, a second semiconductor device, and an external heat distribution layer. The first semiconductor device can comprise a first semiconductor die and an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface. The second semiconductor device can comprise a second semiconductor die and can be stacked on the top surface of the first semiconductor device. The external heat distribution layer can cover an external surface of the second semiconductor device and the side surface of the first semiconductor device. The external heat distribution layer further contacts an internal heat distribution layer on a top surface of the first semiconductor die. 1. A semiconductor package , comprising: a first semiconductor die;', 'an external surface comprising a top surface, a bottom surface, and a side surface joining the bottom surface to the tope surface; and', 'an internal heat distribution layer on a top surface of the first semiconductor die, the internal heat distribution layer extending to the side surface of the first semiconductor device;, 'a first semiconductor device comprisinga second semiconductor device comprising a second semiconductor die stacked on the top surface of the first semiconductor device; and covering an external surface of the second semiconductor device and the side surface of the first semiconductor device; and', 'contacting the internal heat distribution layer along the side surface of the first semiconductor device., 'an external heat distribution layer2. The semiconductor package of claim 1 , further comprising a plurality of fins projecting from the external heat distribution layer.3. The semiconductor package of claim 2 , wherein the internal heat distribution layer claim 2 , the ...

Method of packaging chip and chip package structure

A method of packaging a chip includes laminating a first substrate with a second substrate, the first substrate being capable of withstanding a greater stress than the second substrate; applying an adhesive layer on the second substrate; bonding the chip on the adhesive layer; and forming an encapsulation layer that covers at least the chip.

Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor Devices

Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature. 1. A semiconductor device comprising:a protection pattern located over an encapsulant;a dielectric material isolating the protection pattern, the dielectric material extending from over the encapsulant to over a semiconductor die;conductive redistribution elements within the dielectric material, the conductive redistribution elements electrically connecting the semiconductor die to an external connection; anda packaged semiconductor device connected to the external connection.2. The semiconductor device of claim 1 , wherein the packaged semiconductor device is a package-on-package device.3. The semiconductor device of claim 2 , wherein the package-on-package device comprises dynamic random access memory devices.4. The semiconductor device of claim 1 , wherein the conductive redistribution elements are a same size as conductive elements of the protection pattern.5. The semiconductor device of claim 1 , further comprising through vias extending from a first side of the encapsulant to a second side of the encapsulant.6. The semiconductor device of claim 1 , wherein a portion of the protection pattern material extends beneath the conductive redistribution elements.7. A semiconductor device comprising:a conductive redistribution layer extending over both a first semiconductor device and an encapsulant adjacent to the first semiconductor device;a protection pattern located over the encapsulant, the protection pattern comprising a second conductive ...

Semiconductor Device with Shielding Structure for Cross-Talk Reduction

A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

Semiconductor package and method for manufacturing a semiconductor package

A semiconductor package includes at least one semiconductor element, an encapsulant, a first circuitry, a second circuitry and at least one first stud bump. The encapsulant covers at least a portion of the semiconductor element. The encapsulant has a first surface and a second surface opposite to the first surface. The first circuitry is disposed adjacent to the first surface of the encapsulant. The second circuitry is disposed adjacent to the second surface of the encapsulant. The first stud bump is disposed in the encapsulant, and electrically connects the first circuitry and the second circuitry. The first stud bump contacts the second circuitry directly.

CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

A method for forming a chip package structure is provided. The method includes forming a first dielectric layer over a carrier substrate. The first dielectric layer is a continuous dielectric layer and has openings. The method includes forming a first wiring layer over the first dielectric layer and in the openings. The first dielectric layer and the first wiring layer together form a redistribution structure, and the redistribution structure has a first surface and a second surface. The method includes disposing a first chip and a first conductive bump over the first surface. The method includes forming a first molding layer over the first surface. The method includes removing the carrier substrate. The method includes disposing a second chip and a second conductive bump over the second surface. The method includes forming a second molding layer over the second surface. 1. A method for forming a chip package structure , comprising:forming a first dielectric layer over a carrier substrate, wherein the first dielectric layer has first openings;forming a first wiring layer over the first dielectric layer and in the first openings, wherein the first dielectric layer and the first wiring layer together form a redistribution structure, and the redistribution structure has a first surface and a second surface opposite to the first surface;disposing a first chip and a first conductive bump over the first surface, wherein the first conductive bump is between the first chip and the redistribution structure;forming a first molding layer over the first surface to surround the first chip and the first conductive bump;removing the carrier substrate;disposing a second chip and a second conductive bump over the second surface, wherein the second conductive bump is between the second chip and the redistribution structure; andforming a second molding layer over the second surface to surround the second chip and the second conductive bump.2. The method for forming the chip package ...

FAN-OUT PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Package structures and methods for forming the same are provided. A package structure includes a semiconductor die. The semiconductor die includes a passivation layer over a semiconductor substrate. The semiconductor die also includes a conductive pad in the passivation layer. The passivation layer partially exposes a top surface of the conductive pad. The package structure also includes an encapsulation layer surrounding the semiconductor die. The package structure further includes a dielectric layer covering the semiconductor die and the encapsulation layer. In addition, the package structure includes a redistribution layer covering the dielectric layer. The redistribution layer extends in the dielectric layer to be physically connected to the top surface of the conductive pad. 1. A package structure , comprising:a semiconductor die, comprising:a passivation layer over a semiconductor substrate; anda conductive pad in the passivation layer, wherein the passivation layer partially exposes a top surface of the conductive pad;an encapsulation layer surrounding the semiconductor die;a conductive pillar surrounded by the encapsulation layer and protruding from the encapsulation layer;a dielectric layer covering the semiconductor die and the encapsulation layer; anda redistribution layer covering the dielectric layer, wherein the redistribution layer extends in the dielectric layer to be physically connected to the top surface of the conductive pad.2. The package structure as claimed in claim 1 , wherein the dielectric layer adjoins the conductive pad claim 1 , the passivation layer and the encapsulation layer.3. (canceled)4. The package structure as claimed in claim 1 , wherein the dielectric layer extends in the passivation layer claim 1 , and the top surface of the conductive pad is partially exposed by the dielectric layer.5. (canceled)6. The package structure as claimed in claim 1 ,wherein the redistribution layer is in contact with the conductive pillar and the ...

Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same

An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs. 1. A package comprising: a first device die;', 'a first molding compound extending along sidewalls of the first device die; and', 'a first through intervia (TIV) extending through the first molding compound;, 'a first fan-out tier comprisingone or more first fan-out redistribution layers (RDLs) over the first fan-out tier and bonded to the first device die;a second fan-out tier over the one or more first fan-out RDLs, wherein the second fan-out tier comprises a second device die bonded to the one or more first fan-out RDLs, wherein the one or more first fan-out RDLs electrically connects the first device die to the second device die;one or more second fan-out RDLs on an opposing side of the first fan-out tier from the one or more first fan-out RDLs, wherein the first TIV electrically connects the one or more first fan-out RDLs to the one or more second fan-out RDLs; anda plurality of external connectors at least partially disposed in the one or more second fan-out RDLs, wherein the plurality of external connectors are further disposed on conductive features in the one or more second fan ...

Structure and Formation Method for Chip Package

Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.

Integrated Circuit Packages and Methods of Forming Same

An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening.

Array substrate, method for manufacturing the same and display panel

An array substrate, a method for manufacturing the same and a display panel are provided. The array substrate comprises: a substrate; a bare chip fixed on the substrate, the bare chip comprising pins; a buffer layer and a first metallic layer disposed sequentially on the bare chip, the first metallic layer comprising outer leads in one-to-one correspondence with the pins of the bare chip, the outer leads being connected electrically to the pins corresponding thereto of the bare chip, and the outer leads being electrically insulated from each other; a thin film transistor; and a first signal wire and a first connecting wire disposed in a same layer as a gate electrode of the thin film transistor, and a second signal wire and a second connecting wire disposed in a same layer as a source electrode and a drain electrode of the thin film transistor.

METHIOD OF MANUFACTURING AN IMPLANTABLE ELECTRODE ARRAY BY FORMING PACKAGES AROUND THE ARRAY CONTROL MODULES AFTER THE CONTROL MODULES ARE BONDED TO SUBSTRATES

A method of forming an implantable electrode array that includes one or more packaged control modules. A control module is packaged by mounting the module to a substrate and forming a containment ring around the module. A conformal coating is disposed over the surface of the module to cover the carrier. Within the containment ring, the conformal coating hardens to form a non-porous shell around the control module. The one or more packaged control modules are placed in a flexible array. Electrodes that are mounted to or embedded in the flexible carrier are connected to the one or more control modules. 1. A method of assembling an implantable electrode array , said method including the steps of: forming a containment ring on a first surface of a substrate;', 'mounting a control module to the first surface of the substrate so that the control module is disposed in the containment ring;', 'applying a coating to the first surface of the substrate so that the coating is disposed in the containment ring around the control module so that the coating forms a non-porous shell in the containment ring around the control module;', 'bonding a lid over the containment ring so that the lid extends over the control module and the shell so as to form at least one packaged control module, 'packaging at least one control module according to the steps ofembedding the at least one packaged control module in a flexible carrier; andelectrically connecting the at least one packaged control module to at least one electrode that is disposed over or embedded in the flexible carrier.2. The method of assembling an implantable electrode array of claim 1 , wherein: said step of forming a containment ring of the first surface of the substrate is performed by forming the containment ring so that the containment ring is at least partially located inwardly of an outer perimeter of the containment ring;', 'in said step of applying a coating to the first surface of the substrate, the coating is applied ...

REDISTRIBUTION LAYER CONNECTION

Examples herein include die to metallization structure connections that eliminate the solder joint to reduce the resistance and noise on the connection. In one example, a first die is attached to a metallization layer by a plurality of copper interconnections and a second is attached to the metallization layer opposite the first die through another plurality of copper interconnections. In this example, the copper interconnects may connect the respective die to a metallization structure in the metallization layer. 1. A package comprising:a metallization layer;a first die electrically coupled to a first side of the metallization layer;a second die electrically coupled to a second side of the metallization layer opposite the first side of the metallization layer;a first plurality of copper interconnections between the first die and the metallization layer; anda second plurality of copper interconnections between the second die and the metallization layer.2. The package of claim 1 , further comprising a first metallization structure in the metallization layer wherein the first plurality of copper interconnections are connected to the first metallization structure.3. The package of claim 2 , further comprising a second metallization structure in the metallization layer wherein the second plurality of copper interconnections are connected to the second metallization structure.4. The package of claim 3 , wherein the first metallization structure is coupled to the second metallization structure.5. The package of claim 3 , wherein the first metallization structure is one of copper claim 3 , silver claim 3 , gold claim 3 , or similar metals.6. The package of claim 5 , wherein the second metallization structure is one of copper claim 5 , silver claim 5 , gold claim 5 , or similar metals.7. The package of claim 1 , wherein the first plurality of copper interconnections comprises at least one copper die bump and at least one copper pillar.8. The package of claim 7 , wherein the ...

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

At least some embodiments of the present disclosure relate to a method for manufacturing a bonding structure. The method includes: providing a substrate with a seed layer; forming a conductive pattern on the seed layer; forming a dielectric layer on the substrate and the conductive pattern; and removing a portion of the dielectric layer to expose an upper surface of the conductive pattern without consuming the seed layer. 1. A method for manufacturing a bonding structure , comprising:providing a substrate with a seed layer;forming a conductive pattern on the seed layer;forming a dielectric layer on the substrate and the conductive pattern; andremoving a portion of the dielectric layer to expose an upper surface of the conductive pattern without consuming the seed layer.2. The method of claim 1 , wherein forming the dielectric layer further comprises:forming a first dielectric layer conformably to the substrate and the conductive pattern; andforming a second dielectric layer on the first dielectric layer.3. The method of claim 2 , wherein forming the first dielectric layer comprises performing a chemical vapor deposition operation and forming the second dielectric layer comprises performing a spin coating operation.4. The method of claim 3 , wherein the first dielectric layer comprises silicon oxide claim 3 , and the second dielectric layer comprises spin-coating dielectric.5. The method of claim 3 , wherein an interface is between the first dielectric layer and the second dielectric layer.6. The method of claim 3 , wherein removing the portion of the dielectric layer further comprises performing a surface treatment to expose the upper surface of the conductive pattern.7. The method of claim 6 , wherein performing the surface treatment to expose the upper surface of the conductive pattern forms a recess in the first dielectric layer.8. The method of claim 6 , wherein performing the surface treatment comprises utilizing an etching chemistry more selective to the first ...

Electronic apparatus and method for fabricating the same

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

Semiconductor Device and Method of Forming Wafer-Level Interconnect Structures with Advanced Dielectric Characteristics

A semiconductor device has a build-up interconnect structure including a first insulating layer with a first material and a second insulating layer with a second material. A first conductive layer is formed over the first insulating layer, and the second insulating layer is formed over the first conductive layer. An optional third insulating layer has the second material and is formed over the second insulating layer. A fourth insulating layer has the first material and is formed over the third insulating layer. The second, third, and fourth insulating layers are cured sequentially or simultaneously. The first material includes a greater tensile strength, elastic modulus, and CTE than the second material. The build-up interconnect structure is formed over a semiconductor wafer or semiconductor die in a reconstituted panel. Alternatively, the build-up interconnect structure is formed over a carrier and a semiconductor die is mounted over the build-up interconnect structure. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;depositing an encapsulant over the semiconductor die;forming a first insulating layer including a first material over the semiconductor die and encapsulant;forming a first conductive layer over the first insulating layer;forming a second insulating layer including a second material over the first insulating layer and first conductive layer, the second material different from the first material; andforming a third insulating layer including the first material over the second insulating layer.2. The method of claim 1 , further including:disposing a modular interconnect unit adjacent to the semiconductor die; andforming the first insulating layer over the modular interconnect unit.3. The method of claim 1 , further including curing the second insulating layer prior to forming the third insulating layer.4. The method of claim 1 , further including:forming a second conductive layer over the second insulating layer; ...

Antenna in Embedded Wafer-Level Ball-Grid Array Package

A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant. 1. A method of making a semiconductor device , comprising:providing a substrate;forming an antenna over the substrate;forming a ground plane over the substrate opposite the antenna;disposing a semiconductor die adjacent to the substrate; anddepositing an encapsulant over the substrate and semiconductor die.2. The method of claim 1 , further including:providing a dummy die;forming a conductive layer on the dummy die; anddisposing the dummy die over the semiconductor die prior to depositing the encapsulant.3. The method of claim 2 , further including removing the dummy die by backgrinding the dummy die and encapsulant.4. The method of claim 1 , further including forming a conductive layer to electrically couple the antenna to the semiconductor die.5. The method of claim 1 , further including forming the ground plane and the antenna over the substrate prior to depositing the encapsulant.6. The method of claim 1 , further including forming a conductive bump on the ground plane.7. The method of claim 1 , wherein the substrate includes a conductive via between the antenna and semiconductor die.8. A method of making ...

EMBEDDED MILLIMETER-WAVE PHASED ARRAY MODULE

Embodiments of an embedded mm-wave radio integrated circuit into a substrate of a phased array module are disclosed. In some embodiments, the phased array module includes a first set of substrate layers made of a first material. The mm-wave radio integrated circuit may be embedded in the first set of substrate layers. A second set of substrate layers may be coupled to the first set of substrate layers. The second set of substrate layers may be made of a second material that has a lower electrical loss than the first material. The second set of substrate layers may include a plurality of antenna elements coupled through vias to the mm-wave radio integrated circuit. 1. A method for fabricating a phased array module , the method comprising:embedding a radio integrated circuit into a first set of substrates comprising a first material; andcoupling a second set of substrates to the first set of substrates wherein the second set of substrates comprises a second material having a lower electrical loss than the first material, the second set of substrates comprising a plurality of antenna elements coupled to the radio integrated circuit through one or more vias.2. The method of wherein coupling the second set of substrates to the first set of substrates comprises coupling with a row of solder balls and further comprising embedding the radio integrated circuit into the first set of substrates in a substrate layer adjacent to the second set of substrates.3. The method of and further comprising:coupling the second set of substrates to the first set of substrates with a first row of solder balls;coupling a second row of solder balls to the first set of substrates; andcoupling the radio integrated circuit to the second row of substrates with a first set of vias.4. The method of and further comprising coupling the plurality of antenna elements to the radio integrated circuit through the one or more vias that are coupled to the first row of solder balls.5. The method of wherein ...

RECESSED AND EMBEDDED DIE CORELESS PACKAGE

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands. 16-. (canceled)7. A package structure , comprising:a dielectric material, wherein the dielectric material includes a first surface, a second surface that is spaced apart from the first surface, and a protruding portion that projects from the first surface and includes the second surface; anda die at least partially disposed in the dielectric material, and is at least partially embedded in the protruding portion of the dielectric material.8. The package structure of claim 7 , wherein the first surface is parallel the second surface.9. The package structure of claim 7 , wherein the die is attached to the dielectric material with an adhesive film.10. The package structure of claim 7 , wherein the package structure is a first package structure claim 7 , wherein the package structure includes a second package structure claim 7 , wherein the first and second package structures are coupled together in a package-on-package (PoP) configuration.11. The package structure of claim 10 , wherein the first package structure includes one or more interconnects comprising vias with contact pads claim 10 , to provide electric coupling with the second package structure.12. The package structure of claim 11 , wherein the one or more interconnects are first interconnects claim 11 , wherein the second package structure includes one or more second interconnects to couple with respective ones of the first interconnects.13. The package structure of claim 12 , further comprising one ...

Microelectronic packages and methods for the fabrication thereof

Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers.

ON-CHIP INTERCONNECTS WITH REDUCED CAPACITANCE AND METHOD OF FABRICATION THEREOF

An electronics interconnection system is provided with reduced capacitance between a signal line and the surrounding dielectric material. By using a non-homogenous dielectric, the effective dielectric loss of the material is reduced. This reduction results in less power loss from the signal line to the dielectric material, which reduces the number of buffers needed on the signal line. This increases the speed of the signal, and reduces the power consumed by the interconnection system. The fabrication techniques provided are advantageous because they can be fabricated using today's standard IC fabrication techniques. 1. A high speed electronics interconnection system for interconnecting two or more on-chip electronic elements , the interconnection system comprising: wherein said xy-plane is a horizontal plane defined by Cartesian coordinates along the X and Y axes, such that height coordinate of said xy-plane is measured along vertical Z, and', 'wherein said at least one signal conductor has a length that is significantly larger than either its height or width at any point along its length;, 'at least one electrical signal plane comprising at least one signal conductor for carrying an electrical signal along an xy-plane,'} at least one dielectric layer, and', wherein each said at least one first open trench is grouped with one of said at least one signal conductor,', 'wherein said at least one first open trench has a length that is significantly larger than either its height or width at any point along its length,', 'wherein said at least one first open trench may be continuous or interrupted,', 'wherein said at least one first open trench has a length that is either the same as the length of the said at least one signal conductor to which it is grouped, or has as length that is shorter than the length of the said at least one signal conductor to which it is grouped,', 'wherein each said at least one first open trench runs parallel with and directly above and/or ...

Semiconductor package with dual sides of metal routing

A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.