Wafer packaging method

Technical Field

The invention relates to a chip packaging method.

Background Art

In the chip package technology in the field, there is a package type is the integrated circuit chip (IC chip) mounted on the circuit substrate (circuit substrate), and via circuit substrate electrically connected to the lower level of the electronic element, such as the main board or module board and the like. In accordance with the actual demand, a plurality of wafer can be arranged in the same line on the base plate to form a multi-chip packaging structure, these wafer can be through the circuit substrate to each other transmission signal. However, the current of the line width of the wiring substrate (line width) and the line distance (line pitch) not in accordance with the wafer transferring a signal between a plurality of requirements.

Content of the invention

The present invention provides a wafer packaging method, can be made out of the chip package structure, its in accordance with the multi-chip between the requirements of the transmission signal.

The invention chip packaging method comprises the following steps: a plurality of 1st configuration in a carrier plate on the wafer, wherein the wafer is provided with a 1st 1st has a source surface, and a plurality of 1st 1st in the conductive pin is disposed on an upper surface; a plurality of 2nd conductive column via a 2nd a 2nd of the wafer active surface by connecting these 1st 1st have these wafer source surface; forming a package material, packaging material covering these 1st wafer, conducting these 1st, 2nd and 2nd conductive column these wafer; removed partially packaging material, in order to expose the various 1st conductive column; in the packaging material to form a integrate structure, wherein the integrate structure connecting these 1st conductive column.

Based on the above, in the present invention, face-to-face via a wafer is electrically connected to the at least two other wafer, can provide relatively high connecting path density and short connecting path length.

In order to enable the features and advantages of the invention can be more clearly understood, embodiment below, and cooperate with the attached schema as are detailed below.

Description of drawings

Figure 1 A to Figure 1H is the sectional schematic view of in accordance with one embodiment of the present invention a chip packaging method.

Figure 2 is the three-dimensional view of Figure 1 C support structure includes a plurality of openings.

Figure 3A is the top view of the invention in accordance with another embodiment of 1st and 2nd wafer of the wafer.

Figure 3B is the top view of the invention in accordance with another embodiment of 1st and 2nd wafer of the wafer.

Figure 4 is the sectional schematic view of the invention in accordance with another embodiment of a chip package structure.

Figure 5 is the sectional schematic view of the invention in accordance with another embodiment of a chip package structure.

Figure 6 is the sectional schematic view of the invention in accordance with another embodiment of a chip package structure.

Wherein the symbols in the Figure simple as follows:

50: Chip package structure array; 100: chip package structure; 102: carrier plate; 102 a: side; 110, 110 - 1, 110 - 2, 110 - 3, 110 - 4: 1st wafer; 110 a: 1st has a source surface; 110 b: the back of the 1st; 112: 1st conductive column; 120: 2nd wafer; 120 a: 2nd a source surface; 120 b: the back of the 2nd; 122: 2nd conductive column; 130: support structure; 130 a: opening; 140: packaging material; 140 a: side; 150: integrate structure; 150 a: integrate pad; 152: patterned conductive layer; 154: dielectric layer; 156: conductive channel; 160: conductive contact; L: cut; G: wafer group.

Mode of execution

Please reference view 1 A, according to the embodiment of the wafer packaging method, first of all, a plurality of 1st wafer 110 (for example: 110 - 1, 110 - 2) is disposed in a carrier plate 102 on. Each of the 1st wafer 110 has a 1st a source surface 110 a, and a plurality of 1st conductive column 112 is allocated in 1st has a source surface 110 a on. Specifically, these 1st conductive column 112 are positioned respectively on the corresponding 1st wafer 110 of a 1st source surface 110 a of a plurality of connection pads (not ) on.

Please reference view 1 B, via a plurality of 2nd conductive column 122 a 2nd wafer 120 has a source surface of the 2nd 120 a is electrically connected these 1st wafer 110 with these 1st source surface 110 a. Specifically, through these 2nd conductive column 122 will be 2nd wafer 120 of a 2nd source surface 120 a of a plurality of connection pads (not ) electrically connected these 1st wafer 110 with these 1st source surface 110 a of a plurality of connection pads (not ). The embodiment of the invention, 1st wafer 110 - 1 is part of the 1st source surface 110 a with the 2nd wafer 120 is part of the 2nd source surface 120 a are opposite to each other, and the 1st wafer 110 - 1 is part of the 1st source surface 110 a in the carrier plate 102 with the orthographic projection of the 2nd wafer 120 is part of the 2nd source surface 120 a in the carrier plate 102 the orthographic projection of the overlap. The embodiment of the invention, 1st wafer 110 - 2 is part of the 1st source surface 110 a with the 2nd wafer 120 is part of the 2nd source surface 120 a are opposite to each other, and the 1st wafer 110 - 1 is part of the 1st source surface 110 a in the carrier plate 102 with the orthographic projection of the 2nd wafer 120 is part of the 2nd source surface 120 a in the carrier plate 102 the orthographic projection of the overlap. Therefore, 1st wafer 110 - 1 via the 1st wafer 110 - 1 of these 2nd conductive column 122, 2nd wafer 120, 1st wafer 110 - 2 of these on the 2nd conductive column 122, with the 1st wafer 110 - 2 electrically connected with each other, in order to provide a larger connecting path density and short connecting path length. The embodiment of the invention, these 2nd conductive column 122 of these 1st can be greater than the distribution density of the conductive column 112 distribution density. In addition, these 2nd conductive column 122 in the carrier plate 102 of the orthographic projection area may be not greater than these 1st conductive column 112 in the carrier plate 102 of the orthographic projection area. In addition, these 2nd conductive column 122 with respect to the 1st source surface 110 a is not greater than the height of these 1st conductive column 112 with respect to the 1st source surface 110 a of the height.

Please reference view 1 C, a support structure 130 is disposed in the carrier plate 102 and around these 1st on the wafer 110. In this embodiment, the support structure 130 has an opening 130 a, it surrounds these 1st wafer 110. The support structure 130 help to improve the structural strength and reduce the intensity of curling.

Please reference view 1 D, forming a packaging material 140 (encapsulated material), such as the molding compound (molding compound). Encapsulation material 140 partially covering these 1st wafer 110, these 1st conductive column 112, 2nd wafer 120, these 2nd conductive column 122 and support structure 130.

Please reference view 1 E, removed partially encapsulating material 140, in order to expose the various 1st conductive column 112. The embodiment of the invention, removed partially encapsulating material 140 means including grinding (polishing). Encapsulation material 140 covering the 2nd maintain the wafer 120.

Please reference view 1 F, form a integrate structure 150 in the encapsulation material 140 on, in order to re-distribution signal output or input of the position. The embodiment of the invention, integrate structure 150 includes a plurality of patterned conductive layer 152, a plurality of dielectric layer 154 and a plurality of conductive channel 156, these dielectric layer 154 with the patterned conductive layer 152 are alternately laminated, and every conductive channel 156 is positioned in the corresponding dielectric layer 154 and is electrically connected to the corresponding in these patterned conducting layer 152. These 1st wafer 110 in addition to the wafer via the 2nd 120 electrically connected with each other outside, will also be accessible via integrate structure 150 electrically connected with each other. Specifically, 1st wafer 110 - 1 via the 1st wafer 110 - 1 of these 1st on the conductive column 112, integrate structure 150 of the patterned conductive layer 152, 1st wafer 110 - 2 these 1st on the conductive column 112, with the 1st wafer 110 - 2 electrically connected with each other. And, 1st wafer 110 - 1 can also be via the 1st wafer 110 - 1 of these 2nd conductive column 122, 2nd wafer 120, 1st wafer 110 - 2 of these on the 2nd conductive column 122 with the 1st wafer 110 - 2 electrically connected with each other. In other words, 1st wafer 110 - 1 with the 1st wafer 110 - 2 the path of connection between at least the two lines of the connecting path.

Please reference view 1 G, forming the integrate structure 150 after, removing the carrier plate 102, thus exposes these 1st wafer 110 a of the back surface of the 1st 110 b. At this moment, these 1st wafer 110 a of the back surface of the 1st 110 b, exposed packaging material 140, support structure 130 of the common plane.

Please reference view 1 H, integrate structure 150 has a plurality of integrate pad 150 a, it can be driven by the outermost patterned conductive layer 152 is formed. In Figure 1 G remove the carrier plate 102 after, in the integrate structure 150 of each integrate the pad 150 a is formed on the conductive contact 160, such as solder balls, is used to connect the next level of electronic element, such as a circuit board.

In order to batch way when the production of a plurality of chip package structure 100 when, by a plurality of 1st wafer 110 and at least one 2nd wafer 120 is formed by a plurality of wafer group G (Figure 1 B only these wafer group G of a group) is disposed in the carrier plate 102 on. Therefore, please reference view 1 G, in forming these conductive contact 160 before, can first perform a singulation step, namely along line L to the cutting integrate structure 150, encapsulation material 140 and support structure 130, to separate these wafer group G. At this time, the support structure 130 is exposed in the encapsulation material 140 to a side of the 140 a. Therefore, each of the chip package structure 100 includes a wafer group G, and comprises integrate structure 150 (i.e. after cutting of the integrate structure 150 of a portion of the) and encapsulation material 140 (i.e. after cutting the packaging material 140 of a part).

Similarly, when the in order to batch mode to produce a plurality of chip package structure 100 when, supporting structure 130 in order to array has a plurality of openings 130 a, as shown in Figure 2, and each opening 130 a around the corresponding one of the wafer group G, as shown in Figure 1 C shown. Therefore, as shown in Figure 1 H as shown, each of the chip package structure 100 includes a support structure 130 (i.e. after cutting the support structure 130 of a part).

In this embodiment, in order to array has not yet been cut and a plurality of chip package structure 100 can form a chip package structure array 50, as shown in Figure 1 G shown. In other words, chip package structure array 50 includes an array has not yet been cut and a plurality of chip package structure 100. Specifically, each of the chip package structure 100 includes a plurality of 1st wafer 110 (for example 110 - 1, 110 - 2), a plurality of 1st conductive column 112, a 2nd wafer 120, a plurality of 2nd conductive column 122, a packaging material 140 and a integrate structure 150. Each of the 1st wafer 110 (for example 110 - 1 or 110 - 2) is provided with a 1st a source surface 110 a. Each of the 1st conductive column 112 is disposed on the corresponding 1st wafer 110 of a 1st source surface 110 a on. 2nd wafer 120 has a 2nd a source surface 120 a. 2nd wafer 120 of a 2nd source surface 120 a through these 2nd conductive column 122 electrically connected these 1st wafer 110 with these 1st source surface 110 a. Encapsulation material 140 partially covering these 1st wafer 110, these 1st conductive column 112, 2nd wafer 120 and these 2nd conductive column 122. Integrate structure 150 is disposed in the package material 140 and connected these 1st conductive column 112.

When the chip package structure array 50 of the chip package structure 100 is configured with a peripheral region of the support structure 130 (see Figure 2) time, can reduce the chip package structure array 50 in the packaging process of warping, and can promote the chip package structure array 50 and reduce the structural strength of the production cost of the manufacturing process, and then increase the chip package structure 100 of the output.

In another embodiment, as shown in Figure 4, compared with Figure 1 A to Figure 1 H the illustrated embodiment, when the carrier plate 102 of the material of the heat radiating material, can retain the Figure 1 F carrier plate 102, so that the complete encapsulation of the chip package structure 100 can include Figure 1 H of the carrier plate 102 (i.e. after cutting of the carrier plate 102 and a portion of the) as a heat sink. At this time, the support structure 130 is exposed in the encapsulation material 140 to a side of the 140 a plate and a carrier plate 102 to a side of the 102 a.

In another embodiment, as shown in Figure 5, compared with Figure 1 A to Figure 1 H the illustrated embodiment, can be omitted Figure 1 C support structure 130, so that the completion of the final package of the chip package structure 100 not Figure 1 H of the support structure 130.

In another embodiment, as shown in Figure 6, compared with Figure 1 A to Figure 1 H the illustrated embodiment, can be omitted Figure 1 C support structure 130 while retaining Figure 1 F carrier plate 102, so that the completion of the final package of the chip package structure 100 does not support structure 130, but includes Figure 1 H of the carrier plate 102 (i.e. after cutting of the carrier plate 102 and a portion of the) as a heat sink.

Chip package structure 100 in fig. 4 to fig. 6 various changes can also be applied to Figure 1 G chip packaging structure shown in array 50. For example, has not yet been cutting chip packaging structure array 50 can also include the not yet cutting of the carrier plate 102, as shown in Figure 1 F, Figure 4 and Figure 6 is shown, and the carrier plate 102 has not yet been cut can be used as the heat sink. In addition, has not yet been cutting chip packaging structure array 50 can also does not include the not yet cutting support structure 130, as shown in Figure 5.

In fig. 1 H in the embodiment of the, chip package structure 100 includes a plurality of 1st wafer 110 (for example: 110 - 1, 110 - 2), a plurality of 1st conductive column 112, a 2nd wafer 120, a plurality of 2nd conductive column 122, a packaging material 140 and a integrate structure 150. Each of the 1st wafer 110 has a 1st a source surface 110 a, while the 1st conductive column 112 is disposed on the corresponding 1st wafer 110 of a 1st source surface 110 a on. 2nd wafer 120 has a 2nd a source surface 120 a. The embodiment of the invention, 1st wafer 110 - 1 is part of the 1st source surface 110 a with the 2nd wafer 120 is part of the 2nd source surface 120 a are opposite to each other, and the 1st wafer 110 - 1 is part of the 1st source surface 110 a in the 1st wafer 110 - 1 of the back of the 1st 110 b with the orthographic projection of the 2nd wafer 120 is part of the 2nd source surface 120 a in the 1st wafer 110 - 1 of the back of the 1st 110 b the orthographic projection of the overlap. The embodiment of the invention, 1st wafer 110 - 2 is part of the 1st source surface 110 a with the 2nd wafer 120 is part of the 2nd source surface 120 a are opposite to each other, and the 1st wafer 110 - 1 is part of the 1st source surface 110 a in the 1st wafer 110 - 2 of the back of the 1st 110 b with the orthographic projection of the 2nd wafer 120 is part of the 2nd source surface 120 a in the 1st wafer 110 - 2 of the back of the 1st 110 b the orthographic projection of the overlap.

2nd wafer 120 of a 2nd source surface 120 a through these 2nd conductive column 122 electrically connected these 1st wafer 110 (for example: 110 - 1, 110 - 2) have these 1st source surface 110 a. Encapsulation material 140 partially covering these 1st wafer 110, these 1st conductive column 112, 2nd wafer 120 and these 2nd conductive column 122. Integrate structure 150 is disposed in the package material 140 and connected these 1st conductive column 112.

In fig. 1 H in the embodiment of, these 2nd conductive column 122 is greater than the distribution density of these 1st conductive column 112 distribution density. In addition, these 2nd conductive column 122 in these 1st wafer 110 the orthographic projection of the area may be not greater than these 1st conductive column 112 in these 1st wafer 110 the orthographic projection of the area. In addition, these 2nd conductive column 122 with respect to the 1st source surface 110 a is not greater than the height of these 1st conductive column 112 with respect to the 1st source surface 110 a of the height. Encapsulation material 140 a portion of the 2nd wafer 120 with the integrate structure 150 between, and covers the 2nd wafer 120 a of the back surface of the 2nd 120 b. Integrate structure 150 includes a plurality of patterned conductive layer 152, a plurality of dielectric layer 154 and a plurality of conductive channel 156, these dielectric layer 154 with the patterned conductive layer 152 are alternately laminated, and every conductive channel 156 is positioned in the corresponding dielectric layer 154 and is electrically connected to the corresponding in these patterned conducting layer 152.

In fig. 1 H in the embodiment of the, chip package structure 100 also includes a support structure 130. The support structure 130 around these 1st wafer 110 and with the packaging material 140 phase chimeric. The support structure 130 is exposed in the encapsulation material 140 to a side of the 140 a.

In fig. 1 H in the embodiment of the, chip package structure 100 also includes a plurality of conducting contact points 160, such as solder balls. Integrate structure 150 has a plurality of integrate pad 150 a, and these conductive contact 160 are respectively configured in these integrate pad 150 a on.

Worthy of note is, 1st wafer 110 - 1 via the 1st wafer 110 - 1 of these 1st on the conductive column 112, integrate structure 150 of the patterned conductive layer 152, 1st wafer 110 - 2 these 1st on the conductive column 112, with the 1st wafer 110 - 2 electrically connected with each other. And, 1st wafer 110 - 1 can also be via the 1st wafer 110 - 1 of these 2nd conductive column 122, 2nd wafer 120, 1st wafer 110 - 2 of these on the 2nd conductive column 122 with the 1st wafer 110 - 2 electrically connected with each other. In other words, 1st wafer 110 - 1 with the 1st wafer 110 - 2 the path of connection between at least the two lines of the connecting path.

In addition, although the above embodiment is to a 2nd wafer 120 face-to-face and connected with two 1st wafer 110 - 1, 110 - 2, but not limited to this. In other embodiments, a 2nd wafer 120 also can be connected with three 1st wafer (as shown in Figure 3 A of 110 - 1, 110 - 2, 110 - 3), four 1st wafer (as shown in Figure 3 B of 110 - 1, 110 - 2, 110 - 3, 110 - 4) or even more 1st wafer 110, its visual use demand for the.

In fig. 4 embodiment, compared with the Figure 1 H embodiment, chip package structure 100 also includes a carrier plate 102. The carrier plate 102 is made of heat dissipating material, so that the carrier plate 102 can be used as a heat sink. These 1st wafer 110, encapsulation material 140 and support structure 130 is disposed on the carrier plate 102 on. The support structure 130 is exposed in the encapsulation material 140 to a side of the 140 a plate and a carrier plate 102 to a side of the 102 a.

In the Figure 5 embodiment, compared with the Figure 1 H embodiment, chip package structure 100 does not have the Figure 1 H of the support structure 130.

In fig. 6 in the embodiment of the, compared with the fig. 5 embodiment, chip package structure 100 also includes a carrier plate 102. The carrier plate 102 is made of heat dissipating material, so that the carrier plate 102 can be used as a heat sink. These 1st wafer 110 and encapsulating material 140 is disposed on the carrier plate 102 on.

To sum up, in the present invention, face-to-face via a wafer is electrically connected to the at least two other wafer, can provide relatively high connecting path density and short connecting path length. In addition, the support structure can be increased to improve the structural strength and reduce the intensity of curling. In addition, when the carrier plate of the material of the heat radiating material, to retain the carrier plate as a heat sink.

Is nothing less than the preferred embodiment of the invention, however its and non-is used to limit the scope of the invention, anyone who is familiar with the technical personnel, in without departing from the spirit of this invention and within the scope, can be in this on the basis of the further improvement and change, therefore the scope of protection of this invention when the to the claims of this application as defined by the scope of the prevail.