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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 8337. Отображено 100.
09-02-2012 дата публикации

Semiconductor Device and Power Supply Unit Utilizing the Same

Номер: US20120032713A1
Автор: Atsushi Kitagawa
Принадлежит: ROHM CO LTD

A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals.

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Номер записи: 1
23-02-2012 дата публикации

Mechanisms for forming copper pillar bumps using patterned anodes

Номер: US20120043654A1
Автор: Chih-Wei Lin, Chung-Shi Liu, Ming-Da Cheng, Wen-Hsiung LU
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

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Номер записи: 2
22-03-2012 дата публикации

Micro-structure phosphor coating

Номер: US20120068208A1
Автор: Chi Xiang Tseng, Hsiao-Wen Lee
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An optical emitter includes micro-structure phosphor coating on a light-emitting diode die mounted on a package substrate. The micro-structures are transferred onto a micro-structure phosphor coating precursor by patterning and curing the precursor or by curing the precursor through a mold. The micro-structures are half spheroids, three-sided pyramids, or six-sided pyramids.

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Номер записи: 3
22-03-2012 дата публикации

Massively Parallel Interconnect Fabric for Complex Semiconductor Devices

Номер: US20120068229A1
Автор: Farhang Yazdani, Majid Bemanian
Принадлежит: Individual

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

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Номер записи: 4
22-03-2012 дата публикации

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

Номер: US20120068328A1
Автор: Hin Hwa Goh, KANG Chen, Rui Huang, Xusheng Bao, Yung Kuan Hsiao
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

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Номер записи: 5
29-03-2012 дата публикации

Methods of fabricating package stack structure and method of mounting package stack structure on system board

Номер: US20120074586A1
Автор: Eun-Jin Choi, Sun-Kyoung SEO
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

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Номер записи: 6
12-04-2012 дата публикации

Semiconductor assembly and semiconductor package including a solder channel

Номер: US20120086123A1
Автор: Jeong-Woo Park, Moon-Gi Cho, Sun-Hee Park, Ui-Hyoung Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

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Номер записи: 7
19-04-2012 дата публикации

Semiconductor device, method for forming the same, and data processing system

Номер: US20120091520A1
Автор: Nobuyuki Nakamura
Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate, a first interlayer insulating film over the semiconductor substrate, a first interconnect over the first interlayer insulating film, and a via plug penetrating the semiconductor substrate and the first interlayer insulating film. The via plug is coupled to the first interconnect.

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Номер записи: 8
10-05-2012 дата публикации

Electronic element unit and reinforcing adhesive agent

Номер: US20120111617A1
Автор: Koji Motomura, Seiichi Yoshinaga, Tadahiko Sakai
Принадлежит: Panasonic Corp

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

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Номер записи: 9
31-05-2012 дата публикации

Semiconductor device comprising a capacitor and an electrical connection via, and fabrication method

Номер: US20120133021A1
Автор: Alexy Farcy, Jean-François Carpentier, Pierre Bar, Sylvain Joblot
Принадлежит: STMicroelectronics Crolles 2 SAS, STMICROELECTRONICS SA

A main blind hole is formed in a front face of a wafer having a rear face. A through capacitor is formed in the main blind hole including a conductive outer electrode, a dielectric intermediate layer, and a filling conductive material forming an inner electrode. Cylindrical portions of the outer electrode, the dielectric intermediate layer and the inner electrode have front ends situated in a plane of the front face of the wafer. A secondary rear hole is formed in the rear face of the wafer to reveal a bottom of the outer electrode. A rear electrical connection is made to contact the bottom of the outer electrode through the secondary rear hole. A through hole via filled with a conductive material is provided adjacent the through capacitor. An electrical connection is made on the rear face between the rear electrical connection and the through hole via.

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Номер записи: 10
31-05-2012 дата публикации

Semiconductor device

Номер: US20120133058A1
Автор: Kunihiro Komiya
Принадлежит: ROHM CO LTD

The semiconductor device has the CSP structure, and includes: a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps are arranged in two rows along the periphery of the semiconductor device. The electrode pads are arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring is extended from an electrode pad, and is connected to any one of the outermost solder bumps or any one of the inner solder bumps.

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Номер записи: 11
31-05-2012 дата публикации

Mechanisms for resistivity measurement of bump structures

Номер: US20120133379A1
Автор: Feynmann CHU, Jeff Wang, Mill-Jer Wang, Pi-Huang Lee, You-Hua Chou
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

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Номер записи: 12
14-06-2012 дата публикации

Semiconductor light emitting device

Номер: US20120146086A1
Автор: SATOSHI Tanaka, Tatsuma Saito, Yusuke Yokobayashi
Принадлежит: Stanley Electric Co Ltd

A semiconductor light emitting device having an n-electrode and a p-electrode provided on the same surface side of a semiconductor film, wherein current spread in the semiconductor film is promoted, so that the improvements in luminous efficiency and reliability, the emission intensity uniformalization across the surface, and a reduction in the forward voltage, can be achieved. The semiconductor light emitting device includes a semiconductor film including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer; the n-electrode formed on an exposed surface of the n-type semiconductor layer exposed by removing parts of the p-type semiconductor layer, of the active layer, and of the n-type semiconductor layer with accessing from the surface side of the p-type semiconductor layer; and the p-electrode. A current guide portion having conductivity higher than that of the n-type semiconductor layer is provided on or in the n-type semiconductor layer over the p-type electrode.

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Номер записи: 13
28-06-2012 дата публикации

Semiconductor device and assembling method thereof

Номер: US20120161336A1
Автор: Chau-Jie Zhan, Su-Tsai Lu, Yu-Min Lin
Принадлежит: Industrial Technology Research Institute ITRI

A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.

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Номер записи: 14
28-06-2012 дата публикации

Method of manufacturing semiconductor device including plural semiconductor chips stacked together

Номер: US20120164788A1
Автор: Akira Ide
Принадлежит: Elpida Memory Inc

Such a method is disclosed that includes preparing first and second semiconductor chips, the first semiconductor chip including a first electrode formed on one surface thereof and a second electrode formed on the other surface thereof so as to overlap the first electrode as viewed from a stacking direction, and the second semiconductor chip including a third electrode formed on one surface thereof and a fourth electrode formed on the other surface thereof so as not to overlap the third electrode as viewed from the stacking direction, and stacking the first and second semiconductor chips in the stacking direction so that the second electrode is connected to the third electrode by using a bonding tool including a concave at a position corresponding to the fourth electrode.

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Номер записи: 15
05-07-2012 дата публикации

Solid element device and method for manufacturing the same

Номер: US20120171789A1
Автор: Hideaki Kato, Hiroki Watanabe, Kazuya Aida, Koichi Ota, Kunihiro Hadame, Masaaki Ohtsuka, Mitsuhiro Inoue, Naruhito Sawanobori, Ryoichi Tohmon, Satoshi Wada, Yoshinobu Suehiro, Yoshinori Yamamoto
Принадлежит: Sumita Optical Glass Manufacturing Co Ltd, Toyoda Gosei Co Ltd

A method of making a solid element device that includes a solid element, an element mount part on which the solid element is mounted and which has a thermal conductivity of not less than 100 W/mK, an external terminal provided separately from the element mount part and electrically connected to the solid element, and a glass sealing part directly contacting and covering the solid element for sealing the solid element, includes pressing a glass material at a temperature higher than a yield point of the glass material for forming the glass sealing part.

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Номер записи: 16
26-07-2012 дата публикации

Semiconductor chip module, semiconductor package having the same and package module

Номер: US20120187560A1
Автор: Hyeon Ji BAEK, Hyung Ju CHOI, Jong Hyun Kim, Mun Aun HYUN
Принадлежит: Hynix Semiconductor Inc

A semiconductor module comprising a plurality of semiconductor chips where at least one semiconductor chip is laterally offset with respect to a second semiconductor chip, and substantially aligned with a third semiconductor chip such that an electrical connection can be made between an electrical contact in the first semiconductor chip and an electrical contact in the third semiconductor chip.

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Номер записи: 17
02-08-2012 дата публикации

Ohmic connection using widened connection zones in a portable electronic object

Номер: US20120193804A1
Автор: Yannick Grasset
Принадлежит: RFIDEAL

The invention relates to portable electronic objects comprising an integrated circuit chip, and a mounting having two connection terminals for a circuit, as well as to a method for manufacturing such objects. The invention is characterized in that the chip is provided, on the active surface thereof, with two widened connection zones, in particular connection plates, said connection plates being positioned opposite said terminals and electrically connected, by ohmic contact, to the latter, and in that the surface defined by the connection plates, at the surface of the active integrated circuit having said plates, is greater than ½ of the surface of said surface. The invention can be used, in particular, for RFID objects.

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Номер записи: 18
23-08-2012 дата публикации

Chip package with plank stack of semiconductor dies

Номер: US20120211878A1
Автор: Bruce M. Guenin, Darko R. Popovic, David C. Douglas, Ivan Shubin, Jing Shi, John A. Harada, Matthew D. Giere, Theresa Y. Sze
Принадлежит: Oracle International Corp

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

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Номер записи: 19
30-08-2012 дата публикации

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

Номер: US20120217629A1
Автор: Daesik Choi, Joonyoung Choi, SungWon Cho
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

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Номер записи: 20
30-08-2012 дата публикации

Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive TOV in Peripheral Area Around Semiconductor Die

Номер: US20120217643A1
Автор: Byung Tai Do, Dioscoro A. Merilo, Reza A. Pagaila
Принадлежит: Stats Chippac Pte Ltd

A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV.

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Номер записи: 21
06-09-2012 дата публикации

Etching liquid for etching silicon substrate rear surface in through silicon via process and method for manufacturing semiconductor chip having through silicon via using the etching liquid

Номер: US20120225563A1
Автор: Ryuji Sotoaka, Yoshiko Fujioto
Принадлежит: Mitsubishi Gas Chemical Co Inc

Disclosed are an etching liquid which is used for etching a silicon substrate rear surface in a through silicon via process, etches only a silicon substrate without etching a connecting plug composed of a metal such as copper, tungsten, etc., or polysilicon or the like, and has an excellent etching rate; and a method for manufacturing a semiconductor chip having a through silicon via using the same. The etching liquid is an etching liquid for etching a silicon substrate rear surface in a through silicon via process containing potassium hydroxide, hydroxylamine, and water; and the method for manufacturing a semiconductor chip includes a silicon substrate rear surface etching step using the etching liquid.

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Номер записи: 22
13-09-2012 дата публикации

Semiconductor device and manufacturing method of the same

Номер: US20120228762A1
Автор: Hiroshi Watabe, Masatoshi Fukuda
Принадлежит: Toshiba Corp

A semiconductor device, includes: a wiring substrate, a stacked body mounted on the wiring substrate, an underfill layer filled into gaps between respective semiconductor chips of the stacked body; and a molding body made up of a molding resin covered and formed at outside of the stacked body and so on. The underfill layer is made up of a cured product of a resin material containing an amine-based curing agent, and the cured product has a Tg of 65° C. or more and 100° C. or less.

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Номер записи: 23
04-10-2012 дата публикации

Heat conduction for chip stacks and 3-d circuits

Номер: US20120248627A1
Автор: Francois Hebert, Stephen Joseph Gaul
Принадлежит: INTERSIL AMERICAS LLC

A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.

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Номер записи: 24
01-11-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120276736A1
Автор: Naoki Idani
Принадлежит: Fujitsu Semiconductor Ltd

An oxide film is formed on an inner surface of a via hole in which a through electrode is to be formed, and thereafter a Cu film is embedded in the via hole. When an excess Cu film formed on a first interlayer insulating film is removed by a CMP method, the oxide film is also polished and reduced in thickness. Using the oxide film reduced in thickness as a hard mask, a wiring trench is formed in the first interlayer insulating film. At this time, the oxide film is further reduced in thickness. After a conductive material is embedded in the wiring trench, an excess conductive material is removed by polishing. At this time, the remaining oxide film is removed entirely by the polishing.

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Номер записи: 25
22-11-2012 дата публикации

Stacked semiconductor package

Номер: US20120292787A1
Автор: Jong Hyun Nam
Принадлежит: Hynix Semiconductor Inc

A stacked semiconductor package includes a substrate having an upper surface and a lower surface, and divided into a first region and a second region that adjoins the first region; a support member formed in the second region on the upper surface of the substrate; and a semiconductor chip module including a plurality of semiconductor chips each of which has bonding pads near one edge of a first surface thereof and which are stacked on the support member in a step-like shape such that their bonding pads face the first region and are bent such that the bonding pads are electrically connected with the substrate.

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Номер записи: 26
20-12-2012 дата публикации

Enhanced Bump Pitch Scaling

Номер: US20120319269A1
Автор: Matthew Kaufmann, Mengzhi Pang
Принадлежит: Broadcom Corp

An integrated circuit (IC) device is provided. In an embodiment the IC device includes an IC die configured to be bonded onto an IC routing member and a first plurality of pads that is located on a surface of the IC die, each pad being configured to be coupled to a respective pad of a second plurality of pads that is located on a surface of the IC routing member. A pad of the first plurality of pads is offset relative to a respective pad of the second plurality of pads such that the pad of the first plurality of pads is substantially aligned with the respective pad of the second plurality of pads after the IC die is bonded to the IC routing member.

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Номер записи: 27
03-01-2013 дата публикации

Method of manufacturing semiconductor device

Номер: US20130001274A1
Автор: Jumpei Konno, Kazunori Hasegawa, Michiaki Sugiyama, Nobuhiro Kinoshita, Takafumi Nishita
Принадлежит: Renesas Electronics Corp

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

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Номер записи: 28
03-01-2013 дата публикации

Bump-on-trace (bot) structures

Номер: US20130001778A1
Автор: Han-Ping Pu, Tin-Hao Kuo, Yu-feng Chen, Yuh Chern Shieh
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

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Номер записи: 29
10-01-2013 дата публикации

Semiconductor chip and flip-chip package comprising the same

Номер: US20130009286A1
Автор: Hwan-Sik Lim, Jong-ho Lee, Moon-Gi Cho, Sun-Hee Park, Young-Lyong KIM
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.

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Номер записи: 30
17-01-2013 дата публикации

Interconnection and assembly of three-dimensional chip packages

Номер: US20130015578A1
Автор: Ashok V. Krishnamoorthy, Hiren D. Thacker, Ivan Shubin, John E. Cunningham
Принадлежит: Oracle International Corp

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.

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Номер записи: 31
14-02-2013 дата публикации

Fabrication method of packaging substrate having through-holed interposer embedded therein

Номер: US20130040427A1
Автор: Dyi-chung Hu, Tzyy-Jang Tseng, Yu-Shan Hu
Принадлежит: Unimicron Technology Corp

A packaging substrate having a through-holed interposer embedded therein and a fabrication method of the packaging substrate are provided, where the packaging substrate includes: a molding layer having opposite first and second surfaces; a through-holed interposer embedded in the molding layer and flush with the second surface; a redistribution-layer structure embedded in the molding layer and disposed on the through-holed interposer and having a plurality of electrode pads exposed from the first surface of the molding layer; and a built-up structure disposed on the second surface of the molding layer and electrically connected to the through-holed interposer.

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Номер записи: 32
21-02-2013 дата публикации

Package-on-package structures

Номер: US20130043587A1
Автор: Huahung Kao, Shiann-Ming Liou
Принадлежит: MARVELL WORLD TRADE LTD

Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

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Номер записи: 33
14-03-2013 дата публикации

Semiconductor Devices and Methods of Manufacturing and Packaging Thereof

Номер: US20130062741A1
Автор: Chen-Shien Chen, Ming-Da Cheng, Sheng-Yu Wu, Tin-Hao Kuo
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation.

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Номер записи: 34
04-04-2013 дата публикации

Zener Diode Structure and Process

Номер: US20130082330A1
Автор: WEI Xia, Xiangdong Chen
Принадлежит: Broadcom Corp

A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

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Номер записи: 35
04-04-2013 дата публикации

Semiconductor package including an integrated waveguide

Номер: US20130082379A1
Автор: Ahmadreza Rofougaran, Arya Reza Behzad, Jesus Alfonso Castaneda, Michael BOERS, Sam Ziqun Zhao
Принадлежит: Broadcom Corp

Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.

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Номер записи: 36
11-04-2013 дата публикации

Power management applications of interconnect substrates

Номер: US20130087366A1
Автор: Anthony Stratakos, Chiteh Chiang, Ilija Jergovic, Kwang Hong Tan, Mihalis Michael
Принадлежит: Volterra Semiconductor LLC

Various applications of interconnect substrates in power management systems are described.

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Номер записи: 37
11-04-2013 дата публикации

Semiconductor device having multiple bump heights and multiple bump diameters

Номер: US20130087910A1
Автор: Ramlah Binte Abdul Razak
Принадлежит: Texas Instruments Inc

A semiconductor die includes a first contact stack including a first UBM pad on a first die pad, a second contact stack including a second UBM pad on a second die pad, and a third contact stack including a third UBM pad on a third die pad. The second UBM pad perimeter is shorter than the first UBM pad perimeter, and the third UBM pad perimeter is longer than the second UBM pad perimeter. A first solder bump is on the first UBM pad, a second solder bump is on the second UBM pad, and a third solder bump is on the third UBM pad. The first solder bump, second solder bump and third solder bump all have different sizes.

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Номер записи: 38
25-04-2013 дата публикации

Semiconductor package and stacked semiconductor package

Номер: US20130099359A1
Автор: Sung Min Kim
Принадлежит: SK hynix Inc

A semiconductor package includes a semiconductor chip having a plurality of bonding pads, dielectric members formed over the semiconductor chip in such a way as to expose portions of respective bonding pads and having a trapezoidal sectional shape, and bumps formed to cover the exposed portions of the respective bonding pads and portions of the dielectric members and having a step-like sectional shape.

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Номер записи: 39
09-05-2013 дата публикации

Semiconductor light emitting device and fabrication method thereof

Номер: US20130113005A1
Автор: Jong Rak Sohn, Sang Yeob Song, Seung Woo Choi, Wan Ho Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor light emitting device and a fabrication method thereof are provided. The semiconductor light emitting device includes a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. A reflective structure is formed on the light emitting structure and includes a nano-rod layer comprised of a plurality of nano-rods and air filling space between the plurality of nano-rods and a reflective metal layer formed on the nano-rod layer.

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Номер записи: 40
09-05-2013 дата публикации

System in package process flow

Номер: US20130113115A1
Автор: Chien-Hsiun Lee, Tsung-Ding Wang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

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Номер записи: 41
16-05-2013 дата публикации

Method for Forming Chip-on-Wafer Assembly

Номер: US20130119552A1
Автор: Chen-Hua Yu, Cheng-Lin Huang, Jing-Cheng Lin, Jui-Pin Hung, Shin-puu Jeng, Szu Wei Lu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

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Номер записи: 42
23-05-2013 дата публикации

Adjusting Sizes of Connectors of Package Components

Номер: US20130127059A1
Автор: Chia-Tung Chang, Chien Rhone Wang, Chih-Wei Lai, Chung-Shi Liu, Hung-Jui Kuo, Ming-Che Ho, Tzong-Hann Yang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

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Номер записи: 43
30-05-2013 дата публикации

Interposer and semiconductor package with noise suppression features

Номер: US20130134553A1
Автор: Chewn-Pu Jou, Feng Wei KUO, Huan-Neng CHEN, Hui Yu Lee, Yen-Jen Chen, Yu-Ling Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.

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Номер записи: 44
30-05-2013 дата публикации

Semiconductor Device and Method of Forming RDL Under Bump for Electrical Connection to Enclosed Bump

Номер: US20130134580A1
Автор: Jian Zuo, Ma Phoo Pwint Hlaing, Xusheng Bao
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.

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Номер записи: 45
06-06-2013 дата публикации

Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices

Номер: US20130143361A1
Автор: Chih-Wei Lin, Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Ming-Da Cheng, Wei-Hung Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

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Номер записи: 46
20-06-2013 дата публикации

System With Recessed Sensing Or Processing Elements

Номер: US20130154032A1
Автор: Alan J. O'Donnell, Garrett A. Griffin, Michael J. Cusack, Rigan F. McGeehan
Принадлежит: Analog Devices Inc

Backside recesses in a base member host components, such as sensors or circuits, to allow closer proximity and efficient use of the surface space and internal volume of the base member. Recesses may include covers, caps, filters and lenses, and may be in communication with circuits on the frontside of the base member, or with circuits on an active backside cap. An array of recessed components may a form complete, compact sensor system.

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Номер записи: 47
20-06-2013 дата публикации

Electrical Contact Alignment Posts

Номер: US20130157455A1
Автор: David John Russell, David Justin West
Принадлежит: International Business Machines Corp

An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

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Номер записи: 48
04-07-2013 дата публикации

Semiconductor device having a through-substrate via

Номер: US20130168850A1
Автор: Arkadii V. Samoilov, Larry Y. Wang, Tyler Parent
Принадлежит: Maxim Integrated Products Inc

Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

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Номер записи: 49
18-07-2013 дата публикации

Semiconductor Interposer Having a Cavity for Intra-Interposer Die

Номер: US20130181354A1
Автор: Kevin Kunzhong Hu, Pieter Vorenkamp, Rezaur Rahman Khan, Sam Ziqun Zhao, Sampath K.V. Karikalan, Xiangdong Chen
Принадлежит: Broadcom Corp

A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.

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Номер записи: 50
25-07-2013 дата публикации

Backside integration of rf filters for rf front end modules and design structure

Номер: US20130187246A1
Автор: Anthony K. Stamper, James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Panglijen Candra, Randy L. Wolf, Thomas J. DUNBAR
Принадлежит: International Business Machines Corp

A design structure for an integrated radio frequency (RF) filter on a backside of a semiconductor substrate includes: a device on a first side of a substrate; a radio frequency (RF) filter on a backside of the substrate; and at least one substrate conductor extending from the front side of the substrate to the backside of the substrate and electrically coupling the RF filter to the device.

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Номер записи: 51
25-07-2013 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20130187271A1
Автор: Hiromichi Watanabe, Motoaki Tani, Shinichi Sugiura, Shinya Iijima
Принадлежит: Denso Ten Ltd, Fujitsu Ltd

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

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Номер записи: 52
08-08-2013 дата публикации

Semiconductor Device Packaging Methods and Structures Thereof

Номер: US20130200529A1
Автор: I-Hsuan Peng, Jing-Cheng Lin, Szu Wei Lu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Semiconductor device packaging methods and structures thereof are disclosed. In one embodiment, a method of packaging semiconductor devices includes coupling a plurality of second dies to a top surface of a first die, and determining a distance between each of the plurality of second dies and the first die. The method also includes determining an amount of underfill material to dispose between the first die and each of the plurality of second dies based on the determined distance, and disposing the determined amount of the underfill material under each of the plurality of second dies.

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Номер записи: 53
15-08-2013 дата публикации

Methods of of improving bump allocation for semiconductor devices and semiconductor devices with improved bump allocation

Номер: US20130207107A1
Автор: Yung-Hsin Kuo
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In a method of improving bump allocation for a semiconductor device and a semiconductor device with improved bump allocation, a predetermined signal bump is surrounded with at least three bumps, each being a ground bump or a paired differential signal bump.

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Номер записи: 54
22-08-2013 дата публикации

Package-in-Package Using Through-Hole Via Die on Saw Streets

Номер: US20130214385A1
Автор: Byung Tai Do, Heap Hoe Kuan, Seng Guan Chow
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

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Номер записи: 55
19-09-2013 дата публикации

Contact Test Structure and Method

Номер: US20130240883A1
Автор: Hsien-Wei Chen, Jie Chen, Tsung-Yuan Yu, Ying-Ju Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

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Номер записи: 56
26-09-2013 дата публикации

Gallium nitride based semiconductor light-emitting element, light source, and method for forming unevenness structure

Номер: US20130248877A1
Автор: Akira Inoue, Masaki Fujikane, Toshiya Yokogawa
Принадлежит: Panasonic Corp

The light extraction surface of a nitride semiconductor light-emitting element, including a crystal plane other than a c plane, is subjected to a surface modification process to control its wettability, and then covered with a layer of fine particles. By etching that layer of fine particles after that, an unevenness structure, in which roughness curve elements have an average length (RSm) of 150 nm to 800 nm, is formed on the light extraction surface.

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Номер записи: 57
26-09-2013 дата публикации

Probing Chips during Package Formation

Номер: US20130249532A1
Автор: Jing-Cheng Lin, Szu Wei Lu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.

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Номер записи: 58
03-10-2013 дата публикации

Method and apparatus for reducing package warpage

Номер: US20130260535A1
Автор: Chih-Chun Chiu, Chun-Cheng Lin, Chung-Shi Liu, Hui-min Huang, Meng-Tse Chen, Ming-Da Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Embodiments of mechanisms for flattening a packaged structure are provided. The mechanisms involve a flattening apparatus and the utilization of protection layer(s) between the packaged structure and the surface(s) of the flattening apparatus. The protection layer(s) is made of a soft and non-sticking material to allow protecting exposed fragile elements of the packaged structure and easy separation after processing. The embodiments of flattening process involve flattening the warped packaged structure by pressure under elevated processing temperature. Processing under elevated temperature allows the package structure to be flattened within a reasonable processing time.

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Номер записи: 59
31-10-2013 дата публикации

Production method for polyamide acid particles, production method for polyimide particles, polyimide particles and bonding material for electronic component

Номер: US20130289156A1
Автор: Satoshi Hayashi
Принадлежит: Sekisui Chemical Co Ltd

An object of the present invention is to provide a method for producing polyamide acid particles which is used as a raw material for polyimide particles with a small average particle diameter having high heat resistance. Other objects of the present invention are to provide a method for producing polyimide particles using the method for producing polyamide acid particles, and polyimide particles produced by the method for producing polyimide particles. Yet another object of the present invention is to provide a bonding material for an electronic component, which has a low linear expansion coefficient and a low elastic modulus after being cured in the temperature range equal to or less than the glass transition temperature, so that a joined body with high reliability can be produced. The present invention is a method for producing polyamide acid particles having a step of preparing a solution having a diamine compound dissolved, and a step of precipitating polyamide acid particles by adding a tetracarboxylic anhydride in a non-solution state to the solution having a diamine compound dissolved while applying a physical impact thereto.

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Номер записи: 60
14-11-2013 дата публикации

Semiconductor device

Номер: US20130299970A1
Автор: Kozo Harada, Masaki Watanabe, Satoshi Yamada, Shinji Baba
Принадлежит: Renesas Electronics Corp

To provide a semiconductor device characterized in that lands for mounting thereon solder balls placed in an inner area of a chip mounting area have an NSMD structure. This means that lands for mounting thereon solder balls placed in an area of the back surface of a through-hole wiring board overlapping with a chip mounting area in a plan view have an NSMD structure. According to the invention, a semiconductor device to be mounted on a mounting substrate with balls has improved reliability.

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Номер записи: 61
14-11-2013 дата публикации

Semiconductor Die Connection System and Method

Номер: US20130299976A1
Автор: Chen-Hua Yu, Ming-Fa Chen, Sen-Bor Jan
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.

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Номер записи: 62
21-11-2013 дата публикации

Semiconductor device, method of manufacturing the same, and electronic component

Номер: US20130307155A1
Автор: Toshiro Mitsuhashi
Принадлежит: ROHM CO LTD

A semiconductor device according to the present invention includes a semiconductor substrate, a surface electrode provided on a front surface of the semiconductor substrate through an insulating film, a via, passing through the semiconductor substrate from a rear surface thereof up to the front surface to reach the surface electrode, having a wall including a flange portion inwardly projecting on a front surface portion of the semiconductor substrate, a via insulating film formed on the wall of the via, and a through-electrode embedded inside the via insulating film and electrically connected to the surface electrode, while the via insulating film has portions having different thickness compensating for a step between the flange portion and the remaining portion of the wall, to planarize a contact surface with the through-electrode.

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Номер записи: 63
28-11-2013 дата публикации

Low-temperature flip chip die attach

Номер: US20130313726A1
Автор: Trent S. Uehling
Принадлежит: Individual

A mechanism for electrically coupling a semiconductor device die to a semiconductor device package substrate that avoids introduction of excessive temperature induced stresses to the semiconductor device die interconnect is provided. In one embodiment, the semiconductor device die is mechanically attached to the package substrate (or another semiconductor device die) at room temperature through the use of a plug-in socket or wedge connection having corresponding mating features formed on the die and substrate. The mechanical interconnect features can be formed on the die and substrate interconnects using an electroplating process. The surfaces of the semiconductor device die and package substrate can then be coupled using an underfill material. A low-temperature solid state bonding process can then be used to diffuse the materials forming the plug and socket features in order to form the electrical connection.

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Номер записи: 64
05-12-2013 дата публикации

Sapphire substrate configured to form light emitting diode chip providing light in multi-directions, light emitting diode chip, and illumination device

Номер: US20130320363A1
Автор: Chen-Hong Lee, Cheng-Kuang Yang, Chi-Chih Pu, Chih-Shu Huang, Shih-Chieh Tang, Shih-Yu Yeh, Shyi-Ming Pan, Siang-Fu Hong, Tzu-Hsiang Wang, Wei-Kang Cheng
Принадлежит: Formosa Epitaxy Inc

A sapphire substrate configured to form a light emitting diode (LED) chip providing light in multi-directions, a LED chip and an illumination device are provided in the present invention. The sapphire substrate includes a growth surface and a second main surface opposite to each other. A thickness of the sapphire substrate is thicker than or equal to 200 micrometers. The LED chip includes the sapphire substrate and at least one LED structure. The LED structure is disposed on the growth surface and forms a first main surface where light emitted from with a part of the growth surface without the LED structures. At least a part of light beams emitted from the LED structure pass through the sapphire substrate and emerge from the second main surface. The illumination device includes at least one LED chip and a supporting base. The LED chip is disposed on the supporting base.

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Номер записи: 65
12-12-2013 дата публикации

Semiconductor package and method for manufacturing the same

Номер: US20130328192A1
Автор: Dai Hyun JUNG, In Tae Kim, Jae Sik Park, Jeong Seok Lee
Принадлежит: Amkor Technology Inc

One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers.

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Номер записи: 66
19-12-2013 дата публикации

Shaped and oriented solder joints

Номер: US20130335939A1
Автор: Aleksandar Aleksov, Sanka Ganesan
Принадлежит: Intel Corp

The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic substrate with a plurality of shaped and oriented solder joints. The shaped and oriented solder joints may be substantially oval, wherein the major axis of the substantially oval solder joints may be substantially oriented toward a neutral point or center of the microelectronic device. Embodiments of the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stresses between the microelectronic device and the microelectronic substrate.

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Номер записи: 67
26-12-2013 дата публикации

Semiconductor Device Apparatus and Assembly with Opposite Die Orientations

Номер: US20130341776A1
Автор: Josef C. Drobnik
Принадлежит: FREESCALE SEMICONDUCTOR INC

An electronic apparatus includes a base substrate, the base substrate including an interconnect. The electronic apparatus further includes a first die including a first semiconductor device, the first semiconductor device being coupled to the interconnect, and further includes a second die including a second semiconductor device, the second semiconductor device being coupled to the interconnect. The first and second die are attached to the base substrate in opposite orientations.

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Номер записи: 68
26-12-2013 дата публикации

Method for manufacturing semiconductor device

Номер: US20130344658A1
Автор: Shinichi Sakurada
Принадлежит: Longitude Semiconductor SARL

A method for manufacturing a semiconductor device includes: preparing a semiconductor wafer including a plurality of semiconductor chips arranged in the shape of a matrix, the semiconductor wafer having a first bump electrode formed on one face thereof; forming a depressed portion on a first face of the semiconductor wafer, the depressed portion partitioning the semiconductor wafer into respective semiconductor chips; placing the first face of the semiconductor wafer onto a support tape; and cutting the semiconductor wafer along the depressed portion from a second face opposite to the first face of the semiconductor wafer by the use of a dicing blade having a width smaller than the width of the depressed portion to thereby divide the semiconductor wafer into a plurality of semiconductor chips.

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Номер записи: 69
02-01-2014 дата публикации

Heterostructure containing ic and led and method for fabricating the same

Номер: US20140004630A1
Автор: Cheng-Ta Ko, Kuan-Neng Chen, Wei-Chung Lo
Принадлежит: National Chiao Tung University NCTU

A heterostructure containing IC and LED and a method of fabricating. An IC and an LED are established with the IC having a first electric-conduction block and a first connection block. The IC electrically connects to the first electric-conduction block. A first face of the LED has a second electric-conduction block and a second connection block. The LED is electrically connected to the second electric-conduction block. The first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block, and the first electric-conduction block are electrically connected with the second electric-conduction block to form a heterostructure. The heterostructure provides functions of heat radiation and electric communication for IC and LED.

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Номер записи: 70
02-01-2014 дата публикации

Method of manufacturing semiconductor device

Номер: US20140004661A1
Автор: Jumpei Konno, Kazunori Hasegawa, Michiaki Sugiyama, Nobuhiro Kinoshita, Takafumi Nishita
Принадлежит: Renesas Electronics Corp

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2 . When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

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Номер записи: 71
23-01-2014 дата публикации

Semiconductor package with single sided substrate design and manufacturing methods thereof

Номер: US20140021636A1
Автор: Bernd Karl Appelt, Chia-Cheng Chen, Kuang-Hsiung Chen, Ming Chiang LEE, Pao-Ming Hsieh, Shih-Fu Huang, Tzu-Hui Chen, Yuan-Chang Su
Принадлежит: Advanced Semiconductor Engineering Inc

A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

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Номер записи: 72
30-01-2014 дата публикации

Integrated circuit and display device including the same

Номер: US20140027861A1
Автор: Ho Seok HAN, Ho Suk Maeng
Принадлежит: Samsung Display Co Ltd

An integrated circuit that includes a substrate, a semiconductor layer arranged on the substrate and an insulating layer arranged on an upper portion of the semiconductor layer and including a bump provided on an upper surface thereof, wherein the semiconductor layer includes a main semiconductor area and an including an internal alignment mark including a p-type semiconductor that is overlapped by a metallic external alignment mark arranged on the upper surface of the insulating layer. The p-type semiconductor internal alignment mark can be viewed by an infrared camera during a mounting process of the integrated circuit.

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Номер записи: 73
06-02-2014 дата публикации

Interface Substrate with Interposer

Номер: US20140035162A1
Автор: Rezaur Rahman Khan, Sam Ziqun Zhao
Принадлежит: Broadcom Corp

An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

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Номер записи: 74
20-02-2014 дата публикации

Multi-Chip Module with Multiple Interposers

Номер: US20140048928A1
Автор: Li Li, Lin Shen, Subbarao Arumilli
Принадлежит: Cisco Technology Inc

A Multi-Chip Module is presented herein that comprises a package substrate, at least two integrated circuit devices, each of which is electrically coupled to the package substrate, and an interposer. Formed in the interposer are electrical connections which are predominantly horizontal interconnects. The first interposer is arranged to electrically couple the two integrated circuit devices to each other. Methods for manufacturing a Multi-Chip Module are also presented herein.

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Номер записи: 75
06-03-2014 дата публикации

Method of manufacturing semiconductor device

Номер: US20140065767A1
Автор: Michiaki Sugiyama, Nobuhiro Kinoshita
Принадлежит: Renesas Electronics Corp

In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

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Номер записи: 76
20-03-2014 дата публикации

Passive Devices in Package-on-Package Structures and Methods for Forming the Same

Номер: US20140076617A1
Автор: Chen-Shien Chen, Chih-Hua Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A device includes a polymer. A device die is disposed in the polymer. A passive device includes three Through Assembly Vias (TAVs) penetrating through the polymer, wherein the TAVs are coupled in series. A Redistribution Line (RDL) is underlying the polymer. The RDL electrically couples a first one of the TAVs to a second one of the TAVs.

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Номер записи: 77
20-03-2014 дата публикации

Bump Structure and Method of Forming Same

Номер: US20140077358A1
Автор: Chen-Shien Chen, Guan-Yu Chen, Tin-Hao Kuo, Yu-Jen Tseng, Yu-Wei Lin
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

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Номер записи: 78
20-03-2014 дата публикации

Metal Bump and Method of Manufacturing Same

Номер: US20140077365A1
Автор: Chang-Chia HUANG, Chen-Shien Chen, Tin-Hao Kuo, Yen-Liang Lin, Yu-Jen Tseng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

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Номер записи: 79
03-04-2014 дата публикации

Through silicon via and method of fabricating same

Номер: US20140094007A1
Автор: Cornelia Kang-I Tsang, Edmund Juris Sprogis, Paul Stephen Andry
Принадлежит: Ultratech Inc

A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closest to the substrate contacting a top surface of the conductive core.

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Номер записи: 80
01-01-2015 дата публикации

DE-POP ON-DEVICE DECOUPLING FOR BGA

Номер: US20150001716A1
Автор: BROWN Paul James, Chan Alex
Принадлежит:

Embodiments of the invention place surface-mount devices such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, in place of de-populated BGA pads. 1. An electronic integrated circuit (EIC) package comprising:an EIC substrate;an array of ball grid array (BGA) pads on a first side of said EIC substrate, arranged in a grid pattern of rows and columns; andcontact pads on said first side of said EIC substrate to accommodate electrical connection of a surface-mount device, wherein said surface-mount device occupies a grid location of said grid pattern in place of one or more BGA pads.2. The EIC package of claim 1 , wherein said contact pads comprise at least two adjacent contact pads.3. The EIC package of claim 2 , wherein each of the contact pads is connected to an adjacent BGA pad by a conductor on said first side of said EIC substrate.4. The EIC package of claim 1 , wherein said surface-mount device comprises a two-port device.5. The EIC package of claim 4 , wherein said surface-mount device comprises a decoupling capacitor.6. The EIC package of claim 1 , wherein said surface-mount device is selected from a set of a capacitor claim 1 , a resistor claim 1 , an inductor claim 1 , a diode claim 1 , a transistor claim 1 , a capacitor array claim 1 , and a resistor-capacitor circuit.7. The EIC package of claim 1 , wherein said BGA grid comprises a pitch of between about 0.4 mm×0.4 mm and about 1.27 mm×1.27 mm.8. The EIC package of claim 7 , wherein said BGA grid comprises an irregular pitch.9. A computer-aided design tool for accommodating a surface-mount device on a first surface of a ball grid array (BGA) electronic integrated circuit (EIC) package claim 7 , said tool comprising:a design tool configured to identify, in an EIC configuration of BGA pads in a grid pattern on said first side of said EIC package, at least two contact pads for forming directly on said first ...

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Номер записи: 81
05-01-2017 дата публикации

Stacked Semiconductor Devices and Methods of Forming Same

Номер: US20170005035A1
Автор: Chen Hsien-Wei, HUANG Li-Hsien, Yeh Der-Chyang
Принадлежит:

Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure. 113-. (canceled)14. A method comprising:forming contact pads on a die;blanket depositing a passivation layer over the contact pads;patterning the passivation layer to form first openings, the first openings exposing the contact pads;blanket depositing a buffer layer over the passivation layer and the contact pads;patterning the buffer layer to form second openings, the second openings exposing a first set of the contact pads;forming first conductive pillars in the second openings, topmost surfaces of the first conductive pillars being above a topmost surface of the buffer layer;simultaneously with forming the first conductive pillars, forming conductive lines over the buffer layer, ends of the conductive lines terminating with the first conductive pillars; andforming an external connector structure over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.15. The method of claim 14 , wherein forming the external connector structure ...

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Номер записи: 82
05-01-2017 дата публикации

SYSTEMS AND METHODS FOR HIGH-SPEED, LOW-PROFILE MEMORY PACKAGES AND PINOUT DESIGNS

Номер: US20170005056A1
Автор: Boyle Evan R., Fai Anthony, Wu Zhonghua, Yang Zhiping
Принадлежит:

Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides. 125.-. (canceled)26. An integrated circuit (“IC”) package substrate , comprising a bottom surface comprising an array of contacts , the array of contacts comprising a plurality of data I/O contacts , wherein:a first subset of the plurality of data I/O contacts forms a first C-shaped layout arranged on a first portion of the bottom surface;a second subset of the plurality of data I/O contacts forms a second C-shaped layout arranged on a second portion of the bottom surface; andthe first portion and the second portion are reflectively symmetrical about a central axis.27. The IC package substrate of claim 26 , the array of contacts further comprising a plurality of ground (“GND”) contacts claim 26 , wherein at least one GND contact of the plurality of GND contacts is surrounded by the data I/O contacts of each of the first and second subsets of the plurality of data I/O contacts.28. The IC package substrate of claim 26 , the array of contacts further comprising a plurality of data queue stroke (“DQS”) contacts claim 26 , wherein at least one DQS contact of the plurality of DQS contacts is surrounded by the data I/O contacts of each of the first and second subsets of the plurality of data I/O contacts.29. The IC package substrate of claim 26 , wherein the first subset of the plurality of data I/O contacts comprises a first communications channel claim 26 , and the second subset of the plurality of data I/O contacts comprises a second communications channel.30. The IC package of claim 29 , the array of contacts further comprising a plurality of chip enable (“CE”) contacts claim ...

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Номер записи: 83
05-01-2017 дата публикации

Packages for Semiconductor Devices, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices

Номер: US20170005067A1
Автор: Wang Yen-Ping, Yang Ching-Jung
Принадлежит:

Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon. 1. A package for a semiconductor device , comprising:an integrated circuit die mounting region;a molding material disposed around the integrated circuit die mounting region;an interconnect structure disposed over the molding material and the integrated circuit die mounting region, the interconnect structure comprising a plurality of contact pads; anda connector coupled to each of the plurality of contact pads, wherein two or more of the connectors comprise an alignment feature disposed thereon.2. The package according to claim 1 , wherein the two or more of the connectors comprising the alignment feature disposed thereon are disposed in corners of the package.3. The package according to claim 1 , wherein the connectors comprise a eutectic material.4. The package according to claim 1 , wherein the alignment features comprise a shape selected from the group consisting essentially of: a cross claim 1 , a line claim 1 , a plurality of lines claim 1 , a square claim 1 , a rectangle claim 1 , a triangle claim 1 , a polygon claim 1 , a ring claim 1 , a circle claim 1 , an oval claim 1 , a numeral claim 1 , a letter claim 1 , and combinations thereof.5. A packaged semiconductor device claim 1 , comprising:a molding material;an integrated circuit die disposed within the molding material;a plurality of through-vias disposed within the molding material;an interconnect structure disposed over the molding ...

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Номер записи: 84
05-01-2017 дата публикации

3DIC Stacking Device and Method of Manufacture

Номер: US20170005073A1
Автор: Lin Jing-Cheng, Yu Chen-Hua
Принадлежит:

A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position. 1. A semiconductor device comprising:a first semiconductor die encapsulated by a first encapsulant;at least one through substrate via extending through at least a portion of the first semiconductor die and being exposed on a first side of the first semiconductor die;first external connectors located on a second side of the first semiconductor die;a first redistribution layer in electrical connection with the first external connectors, the first redistribution layer extending over the first encapsulant; anda second semiconductor die in electrical connection with the at least one through substrate via, the second semiconductor die extending over the first encapsulant.2. The semiconductor device of claim 1 , further comprising;a third semiconductor die encapsulated by the first encapsulant; anda fourth semiconductor die in electrical connection with the third semiconductor die, the fourth semiconductor die extending over the first encapsulant.3. The semiconductor device of claim 2 , wherein the second semiconductor die and the fourth semiconductor die are encapsulated by a second encapsulant.4. The semiconductor device of claim 1 , further comprising a second redistribution layer in electrical connection with the at least one through substrate via claim 1 , the second redistribution layer extending over the first encapsulant.5. The semiconductor device of claim 1 , wherein the second semiconductor die is offset from the first semiconductor die.6. The semiconductor device of claim 5 , wherein the offset is between about 100 um and about 3 mm.7. ...

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Номер записи: 85
13-01-2022 дата публикации

SEMICONDUCTOR PACKAGE

Номер: US20220013419A1
Автор: SEO Hyun Chul
Принадлежит: SK HYNIX INC.

A semiconductor package includes a semiconductor chip with a normal connection electrode and a measurement connection electrode, formed on a first surface, and a substrate with a normal substrate pad, connected to the normal connection electrode, and a measurement substrate pad, connected to the measurement connection electrode. The normal substrate pad and the measurement substrate pad are formed on a surface that faces the first surface. The measurement connection electrode includes first and second edge measurement connection electrodes and first and second center measurement connection electrodes. The measurement substrate pad includes a center measurement substrate pad, a first edge measurement substrate pad, and a second edge measurement substrate pad. The first edge measurement connection electrode and the first center measurement connection electrode are electrically connected to each other, and the second edge measurement connection electrode and the second center measurement connection electrode are electrically connected to each other. 1. A semiconductor package , comprising:a semiconductor chip including a normal connection electrode and a measurement connection electrode that are formed on a first surface; anda substrate including a normal substrate pad that is connected to the normal connection electrode and a measurement substrate pad that is connected to the measurement connection electrode, the normal substrate pad and the measurement substrate pad being formed on a surface that faces the first surface,wherein the measurement connection electrode includes first and second edge measurement connection electrodes that are formed at both side edge regions of the semiconductor chip, respectively, the side edge regions running along a first direction, and first and second center measurement connection electrodes that are arranged in a center region of the semiconductor chip to be spaced apart from each other, the center region disposed between the both ...

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Номер записи: 86
07-01-2016 дата публикации

Semiconductor devices having through electrodes, methods of manufacturing the same, and semiconductor packages including the same

Номер: US20160005706A1
Автор: Wan Choon PARK
Принадлежит: SK hynix Inc

A semiconductor device includes a semiconductor layer having a first surface and a second surface, a through electrode penetrating the semiconductor layer and having a protruding portion that protrudes over the second surface of the semiconductor layer, a front-side bump disposed on the first surface of the semiconductor layer and electrically coupled to the through electrode, a passivation pattern including a first insulation pattern that surrounds a sidewall of the protruding portion of the through electrode and extends onto the second surface of the semiconductor layer and a second insulation pattern that covers the first insulation pattern and has an etch selectivity with respect to the first insulation pattern, and a back-side bump covering an end surface of the protruding portion of the through electrode and extending onto the passivation pattern.

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Номер записи: 87
04-01-2018 дата публикации

STUD BUMP STRUCTURE FOR SEMICONDUCTOR PACKAGE ASSEMBLIES

Номер: US20180005973A1
Автор: Chen Cheng-Ting, Chen Meng-Tse, Cheng Ming-Da, Lin Chih-Wei, Lin Hsiu-Jen, Liu Chung-Shi
Принадлежит:

A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure. 116.-. (canceled)17. A method of forming a stud bump structure in a package structure , comprising:providing a conductive wire;pressing one end of the conductive wire to a bond pad and melting the conductive wire end to form a stud bump on the bond pad;severing the other end of the conductive wire close above the stud bump; andsoldering a solder ball to a top surface of the stud bump, the solder ball encapsulating the stud bump.18. The method of forming a stud bump structure of claim 17 , wherein the conductive wire comprises aluminum claim 17 , aluminum alloy claim 17 , copper claim 17 , copper alloy claim 17 , gold claim 17 , or gold alloy.19. The method of forming a stud bump structure of claim 17 , wherein the pressing and melting the conductive wire to form a stud bump on the bond pad is performed by wire bonding tool.20. The method of forming a stud bump structure of claim 17 , wherein the pressing and melting the conductive wire to form a stud bump on the bond pad is performed by a stud bump bonder.21. The method of forming a stud bump structure of claim 17 , wherein the severing the other end of the conductive wire leaves a tail extending from the bond pad.22. The method of forming a stud bump structure of claim 17 , further comprising applying ultrasonic energy to form the stud bump.23. The method of forming a stud bump structure of claim 17 , wherein the stud bump is disposed at a corner of a die.24. A method for forming a package structure claim 17 , the method comprising:providing a die wherein the die has a first periphery region adjacent a first edge of the die and a second ...

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Номер записи: 88
07-01-2021 дата публикации

Method and apparatus for manufacturing array device

Номер: US20210005520A1
Автор: Hitoshi Aoki, Toshiya Ishio
Принадлежит: Sharp Corp

A method for manufacturing an array device includes a placing step of providing a plurality of elements in an array on a first surface of a substrate, an element separating step of separating a plurality of element chips from one another so that each element chip includes one or more elements, an inspecting step of inspecting the plurality of elements, a removing step of removing any element chip of the plurality of element chips from the surface of the substrate on the basis of a result of the inspecting step, and a mounting step of, after the removing step, mounting an element of at least the elements other than an element of the element chip thus removed onto a mounting substrate by transfer from the substrate, the mounting substrate being different from the substrate.

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Номер записи: 89
04-01-2018 дата публикации

SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF

Номер: US20180005987A1
Автор: Hiner David, Huemoeller Ronald, KELLY MICHAEL
Принадлежит:

A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die. 1. A method of making an electronic device , the method comprising:receiving a first portion of a signal redistribution structure;forming a first functional die interconnection structure on the signal redistribution structure;forming a second functional die interconnection structure on the signal redistribution structure;coupling a back side of a connect die to the signal redistribution structure, the connect die comprising a first connect die interconnection structure coupled to a front side of the connect die and a second connect die interconnection structure coupled to the front side of the connect die;coupling a first interconnection structure of a first functional die to the first functional die interconnection structure; andcoupling a second interconnection structure of the first functional die to the first connect die interconnection structure.2. The method of claim 1 , wherein:said receiving the first portion of the signal redistribution structure comprises receiving the first portion of the signal distribution structure on a carrier; andthe method further comprises removing the carrier.3. The method of claim 1 , comprising:coupling a third interconnection structure of a second functional die to the second functional die interconnection structure; andcoupling a fourth interconnection structure of the second functional die to the second connect die interconnection structure.4. The method of claim 2 , comprising after said removing the carrier claim 2 , adding at least one dielectric layer and at least one conductive layer to the signal redistribution structure.5. The method of claim 1 , comprising before said coupling the first and ...

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Номер записи: 90
07-01-2021 дата публикации

Semiconductor package

Номер: US20210005576A1
Автор: Ho Geon Song, Kyoungsoo Kim, Kyung Suk Oh, Seungduk Baek, SunWon Kang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package includes a first die including a signal region and a peripheral region bordering the signal region and having first vias in the peripheral region, a second die stacked on the first die and having second vias at positions corresponding to the first vias in the peripheral region, and first connection terminals between the first die and the second die that are configured to connect the second vias to the first vias, respectively. The peripheral region includes first regions and second regions configured to transmit different signals, which are alternately arranged in a first direction. The first vias are arranged in at least two rows along a second direction intersecting the first direction in each of the first and second regions.

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Номер записи: 91
04-01-2018 дата публикации

SEMICONDUCTOR LIGHT EMITTING ELEMENT WITH DISPERSIVE OPTICAL UNIT AND ILLUMINATION DEVICE COMPRISING THE SAME

Номер: US20180006199A9
Автор: Chien Fen-Ren, PAN SHYI-MING, Ye Zhi-Ting
Принадлежит:

A semiconductor light emitting element includes a transparent substrate and a plurality of light emitting diode (LED) chips. The transparent substrate has a support surface and a second main surface disposed opposite to each other. At least some of the LED structures are disposed on the support surface and form a first main surface where light emitted from with a part of the support surface without the LED structures. Each of the LED structures includes a first electrode and a second electrode. Light emitted from at least one of the LED structures passes through the transparent substrate and emerges from the second main surface. An illumination device includes the semiconductor light emitting element and a supporting base. The semiconductor light emitting element is disposed on the supporting base, and an angle is formed between the semiconductor light emitting element and the supporting base. 1. A semiconductor light emitting element , comprising:a transparent substrate, having a support surface and a second main surface disposed opposite to each other;a light emitting diode (LED) structure disposed on the support surface, a first main surface, where light emitted from, being formed by the LED structure and at least a part of the support surface without the LED structure, and at least a part of the light emitted from the LED structure may pass through the transparent substrate and emerge from the second main surface; andan optical unit disposed on the first main surface, the optical unit comprising a covering side facing the transparent substrate, and a light dispersion side corresponding to the covering surface;wherein the optical unit further comprises at least one optical structure disposed on the light dispersion side to disperse light received from the covering side to different directions corresponding to wavelength of the light.2. The semiconductor light emitting element of claim 1 , further comprising:a wavelength conversion layer sandwiched by the optical ...

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Номер записи: 92
02-01-2020 дата публикации

RF DEVICES WITH ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME

Номер: US20200006193A1
Автор: Carroll Michael, Costa Julio C.
Принадлежит:

The present disclosure relates to a radio frequency device that includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion, first bump structures, a first mold compound, and a second mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The BEOL portion is formed underneath the FEOL portion, and the first bump structures and the first mold compound are formed underneath the BEOL portion. Each first bump structure is partially encapsulated by the first mold compound, and electrically coupled to the FEOL portion via connecting layers within the BEOL portion. The second mold compound resides over the active layer without a silicon material, which has a resistivity between 5 Ohm-cm and 30000 Ohm-cm, in between. 1. An apparatus comprising: the BEOL portion comprises a plurality of connecting layers;', 'the FEOL portion comprises an active layer, a contact layer, and isolation sections;', 'the active layer and the isolation sections reside over the contact layer, and the isolation sections surround the active layer;', 'the active layer does not extend vertically beyond the isolation sections;, 'a device region including a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion residing over the BEOL portion, whereina plurality of first bump structures formed at a bottom surface of the BEOL portion, wherein the plurality of first bump structures is electrically coupled to the FEOL portion via the plurality of connecting layers;a first mold compound formed over the bottom surface of the BEOL portion and partially encapsulating each of the plurality of first bump structures, wherein a bottom portion of each of the plurality of first bump structures is not covered by the first mold compound; anda second mold compound residing over ...

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Номер записи: 93
02-01-2020 дата публикации

Stress Reduction Apparatus and Method

Номер: US20200006311A1
Автор: Chen Chen-Shien, Chuang Chita, Chuang Yao-Chun, HSU Yu-Chen, Kuo Chen-Cheng, Liu Haochun
Принадлежит:

A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region. 1. A method comprising:depositing a polymer layer over a substrate of a first semiconductor die;forming an under bump metallization structure over the polymer layer;forming a connector over the under bump metallization structure; andforming a first dummy conductive plane over the polymer layer, wherein a topmost surface of the first dummy conductive plane is below a topmost surface of the connector, and wherein a long edge of the first dummy conductive plane is collinear with an edge of the first semiconductor die in a plan view.2. The method of claim 1 , further comprising forming a second dummy conductive plane over the polymer layer and in physical contact with the first dummy conductive plane claim 1 , wherein the first dummy conductive plane and the second dummy conductive plane form an L-shaped dummy region at a corner of the first semiconductor die.3. The method of claim 2 , further comprising forming a third dummy conductive plane between the first dummy conductive plane and the connector.4. The method of claim 1 , further comprising bonding a second semiconductor die to the first semiconductor die through a reflow process claim 1 , wherein the second semiconductor die is electrically coupled to the first semiconductor die through the connector.5. The method of claim 4 , further comprising forming an underfill layer between the first semiconductor die and the second semiconductor die claim 4 , wherein a topmost ...

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Номер записи: 94
03-01-2019 дата публикации

SEMICONDUCTOR CHIP

Номер: US20190006306A1
Автор: KUROKAWA Atsushi, Shibata Masahiro, TOKUDA Daisuke, TOKUYA Hiroaki, UMEMOTO Yasunari
Принадлежит: MURATA MANUFACTURING CO., LTD.

A semiconductor chip includes a semiconductor substrate having a main surface, first and second electrodes, a first insulating layer, and first and second bumps. The first and second electrodes are formed above the main surface of the semiconductor substrate. The first insulating layer is formed above a first portion of the first electrode. The first bump is formed above a second portion of the first electrode and above the first insulating layer and is electrically connected to the first electrode. The second bump is formed above the second electrode. The area of the second bump is larger than that of the first bump in a plan view of the main surface of the semiconductor substrate. The first insulating layer adjusts the distance from the main surface of the semiconductor substrate to the top surface of the first bump in a direction normal to the main surface. 1. A semiconductor chip comprising:a semiconductor substrate having a main surface;a first electrode formed above the main surface of the semiconductor substrate;a second electrode formed above the main surface of the semiconductor substrate;a first insulating layer formed above a first portion of the first electrode;a first bump that is formed above a second portion of the first electrode and above the first insulating layer, and that is electrically connected to the first electrode; anda second bump formed above the second electrode, an area of the second bump being larger than an area of the first bump in a plan view of the main surface of the semiconductor substrate,wherein a level on which the first bump is formed is higher than a level on which the second bump is formed.2. The semiconductor chip according to claim 1 , wherein a longest distance from the main surface of the semiconductor substrate to a top surface of the first bump in a direction normal to the main surface of the semiconductor substrate is substantially equal to a longest distance from the main surface of the semiconductor substrate to a ...

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Номер записи: 95
03-01-2019 дата публикации

THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS

Номер: US20190006323A1
Автор: Gandhi Jaspreet S., Koopmans Michel
Принадлежит:

Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures. 1. A semiconductor die , comprising:a semiconductor substrate having a first surface and a second surface angled relative to the first surface, wherein the second surface at least partially defines an opening in the first surface;an interconnect extending at least partially through the semiconductor substrate, wherein the interconnect includes an end portion projecting from the opening, and wherein the end portion has a sidewall exposed from the semiconductor substrate in the opening;a metallization structure extending at least partially around the sidewall of the end portion of the interconnect, wherein the metallization structure is laterally spaced apart from the second surface of the semiconductor substrate; anda thermal pad on the first surface of the semiconductor substrate, wherein the thermal pad and the metallization structure project to generally the same vertical height above the first surface of the semiconductor substrate.2. The semiconductor die of claim 1 , further comprising a passivation material at least partially on the first surface of the semiconductor substrate.3. The semiconductor die of claim 1 , further comprising a passivation material in the opening between the metallization structure and the semiconductor substrate.4. The ...

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Номер записи: 96
03-01-2019 дата публикации

SEMICONDUCTOR PACKAGE HAVING SPACER LAYER

Номер: US20190006325A1
Автор: Guzek John S., TEH Weng Hong, Zhong Shan
Принадлежит:

Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies. 1. (canceled)2. A device comprising:a packaging substrate having a surface wherein the surface has a recess formed therein;a first integrated circuit die disposed in the recess of the packaging substrate wherein the first integrated circuit die has a surface;a raised patterned layer disposed on the surface of the packaging substrate; anda second integrated circuit die disposed on the raised patterned layer creating a cavity that is bordered by an inner surface of the raised patterned layer and a surface of the second integrated circuit die that faces the first surface of the first integrated circuit die.3. The device of wherein the first integrated circuit die also comprises a spacer layer disposed on the surface of the first integrated circuit die.4. The device of wherein the packaging substrate is a coreless packaging substrate.5. The device of wherein the packaging substrate is comprised of built-up layers of dielectric and conducting materials.6. The device of wherein the cavity is a region having an airtight seal.7. The device of wherein the first die is fully embedded in the packaging substrate.8. The device of wherein the cavity comprises sensors or actuators that are electrically coupled to the package substrate.9. The device of wherein the sensors or actuators are selected from the group consisting of mems RE switches claim 8 , cantilever-based sensors claim 8 , accelerometers claim 8 , gyroscopes claim 8 , oscillators claim 8 , pizeoresistive ...

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Номер записи: 97
27-01-2022 дата публикации

SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE

Номер: US20220028828A1
Автор: Naruse Takanobu
Принадлежит: AISIN CORPORATION

Connection terminals of a semiconductor module are disposed appropriately in accordance with the connection destination of the semiconductor module. A semiconductor module which includes at least one semiconductor element is mounted on a first surface of a main substrate, which has the first surface on which a first circuit element is mounted and a second surface on which a second circuit element is mounted. A plurality of connection terminals include a first connection terminal group composed of a plurality of first connection terminals to be connected to the first circuit element via the main substrate, and a second connection terminal group composed of a plurality of second connection terminals to be connected to the second circuit element via the main substrate. The first connection terminal group is disposed on the outer peripheral side with respect to the second connection terminal group. 1. A semiconductor module mounted on a first surface of a main substrate and including at least one semiconductor element , with a first circuit element mounted on the first surface and with a second circuit element mounted on a second surface on an opposite side from the first surface , the semiconductor module comprising:a plurality of connection terminals disposed in a shape of a plurality of rectangular rings on a side of a facing surface that faces the main substrate to be connected to the main substrate, wherein:the plurality of connection terminals include a first connection terminal group composed of a plurality of first connection terminals to be connected to the first circuit element via the main substrate, and a second connection terminal group composed of a plurality of second connection terminals to be connected to the second circuit element via the main substrate; andthe first connection terminal group is disposed on an outer peripheral side with respect to the second connection terminal group.2. The semiconductor module according to claim 1 , wherein when ...

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Номер записи: 98
12-01-2017 дата публикации

Chip Scale Package

Номер: US20170011979A1
Автор: Wilcoxen Duane Thomas
Принадлежит:

A novel semiconductor chip scale package encapsulates semiconductor chip on the device side, the non-device side, and the four edges with a mold compound. One process to fabricate such a semiconductor chip scale package involves forming trenches on the surface of a wafer around the chips and filling the trenches and covering the device side of the chips with a first mold compound. The wafer is subsequently thinned from the non-device side until the bottom portion of the trenches and the mold compound in the portion are also removed. The thinning process creates a plane that contains the back side of the chips and the mold compound exposed in the trench. This plane is subsequently covered with a second mold compound. 1. A semiconductor device package , comprising:a semiconductor chip having a device side with metallic contact bumps thereon, a non-device side opposite the device side, and four edges;a first layer of mold compound covering the four edges and the device side of the chip;a second layer of mold compound covering the non-device side of the chip;the first layer of mold compound joining the second layer of mold compound at a plane that is coplanar to the non-device side of the chip.2. The semiconductor device package of claim 1 , in which a top portion of the contact bumps on the device side of the semiconductor chip protrude from the first layer of mold compound.3. The semiconductor device package of claim 2 , in which the protruding portion of the contact burns is covered with a metallic film containing gold.4. The semiconductor device package of claim 3 , in which the contact bumps contain nickel.5. The semiconductor device package of claim 1 , in which the first layer of mold compound contains filler particles.6. The semiconductor device package of claim 5 , further comprising partially ground filler particles near the plane where the first layer and the second layer of mold compound meet.7. The semiconductor device of claim 6 , in which the partially ...

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Номер записи: 99
12-01-2017 дата публикации

Chip package and manufacturing method thereof

Номер: US20170012081A1
Автор: Chia-Lun SHEN, Hsiao-Lan Yeh, Yen-Shih Ho, Yi-Ming Chang
Принадлежит: XinTec Inc

A manufacturing method of a chip package includes the following steps. A patterned solder paste layer is printed on a patterned conductive layer of a wafer. Plural solder balls are disposed on the solder paste layer that is on a first portion of the conductive layer. A reflow process is performed on the solder balls and the solder paste layer. A flux layer converted from a surface of the solder paste layer is cleaned.

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Номер записи: 100