СПОСОБ ВСТРАИВАНИЯ КОМПОНЕНТА В ОСНОВАНИЕ

Изобретение относится к способу, согласно которому полупроводниковые компоненты, образующие часть электронной схемы, или по меньшей мере некоторые из таких компонентов, встраивают в основание, например, в печатную плату в процессе ее изготовления. Технический результат - создание способа, посредством которого бескорпусные микросхемы могут быть встроены в основание надежным, но экономичным образом. Достигается тем, что в основании выполняют сквозные отверстия для полупроводниковых компонентов, причем отверстия проходят между первой и второй поверхностями основания. После выполнения отверстий на вторую поверхность структуры основания наносят полимерную пленку, причем полимерная пленка закрывает сквозные отверстия для полупроводниковых компонентов со стороны второй поверхности структуры основания. Перед отверждением полимерной пленки или после ее частичного отверждения в отверстия вводят полупроводниковые компоненты со стороны первой поверхности. Полупроводниковые компоненты прижимают к полимерной ...

СПОСОБ 2D-МОНТАЖА (ВНУТРЕННЕГО МОНТАЖА) ИНТЕГРАЛЬНЫХ МИКРОСХЕМ

Изобретение относится к радиоэлектронике и может быть использовано при изготовлении печатных плат, применяемых при конструировании радиоэлектронной техники. Технический результат - повышение степени интеграции и снижение массогабаритных показателей ИМС. Достигается тем, что используется технология монтажа бескорпусной элементной базы в тело подложки посредством создания на подложке прямоугольных отверстий, соответствующих с допустимым увеличением размерам кристаллов ИС, монтируемых в данные отверстия. Разводка топологических связей между кристаллами осуществляется методом вакуумного напыления, когда на подложке с уложенными кристаллами через маску формируют токоведущие дорожки из меди и никеля - защитного слоя, причем, не используя пайку и сварку, образуется соединение контактных площадок ИС с токоведущими дорожками платы. 7 ил.

АРХИТЕКТУРА СОЗДАНИЯ ГИБКИХ КОРПУСОВ

Anordnung mit drei Halbleiterchips und Herstellung einer solchen Anordnung

Anordnung, umfassend:einen ersten Halbleiterchip, der eine erste Kontaktstelle auf einer ersten Seite umfasst;einen zweiten Halbleiterchip, der eine erste Kontaktstelle auf einer ersten Seite umfasst, wobei der zweite Halbleiterchip über dem ersten Halbleiterchip platziert ist und die erste Seite des ersten Halbleiterchips der ersten Seite des zweiten Halbleiterchips zugewandt ist; genau eine Schicht aus einem elektrisch leitfähigen Material, die zwischen dem ersten Halbleiterchip und dem zweiten Halbleiterchip angeordnet ist, wobei die genau eine Schicht aus einem elektrisch leitfähigen Material die erste Kontaktstelle des ersten Halbleiterchips elektrisch mit der ersten Kontaktstelle des zweiten Halbleiterchips koppelt;eine Passivierungsschicht, die einen Teil der ersten Seite des ersten Halbleiterchips außerhalb der ersten Kontaktstelle überdeckt; undeinen auf der Passivierungsschicht angebrachten dritten Halbleiterchip,wobei der erste und der zweite Halbleiterchip jeweils Leistungs-Halbleiterchips ...

Multichip-Montageeinheit mit einem Substrat mit mehreren vertikal eingebetteten Plättchen und Verfahren zur Herstellung derselben

Eine Vorrichtung umfasst ein Substrat, welches eine Anschlussfleckseite mit mehreren Kontaktflecken und eine Plättchenseite gegenüber der Anschlussfleckseite aufweist. Die Vorrichtung umfasst ein erstes Plättchen und ein zweites Plättchen, wobei das erste Plättchen und das zweite Plättchen derart in das Substrat eingebettet sind, dass das zweite Plättchen zwischen dem ersten Plättchen und der Anschlussfleckseite des Substrats angeordnet ist.

Integration von Silicium-Photonik-IC für hohe Datenrate

Integrierte Komponentenbaugruppe, die umfasst:eine Leiterplatte (PCB);eine integrierte Photonikschaltung (PIC), die mit der PCB auf einer ersten Seite der PIC mechanisch gekoppelt ist; undeine Treiber-IC mit einer ersten Seite, wobei die erste Seite der Treiber-IC(i) mit einer zweiten Seite der PIC über einen ersten Satz von Höcker-Bondverbindungen direkt mechanisch und elektrisch gekoppelt ist, und(ii) mit der PCB über einen zweiten Satz von Höcker-Bondverbindungen elektrisch gekoppelt ist.

Parallelchip-Eingebettete gedruckte Schaltungsplatine und Herstellungsverfahren dafür

Eine Parallelchip-eingebettete Schaltungsplatine und ein Herstellungsverfahren dafür sind offenbart. Mit einem Verfahren zum Herstellen einer Parallelchip-eingebetteten, gedruckten Schaltungsplatine, welches umfasst: a) Bilden eines Parallelchips durch ein Verbinden einer Mehrzahl von Einheitschips, die Elektroden oder elektrisch verbundene Elemente aufweisen, die auf den oberen und unteren Flächen davon gebildet sind, parallel unter Verwendung von zumindest einem leitfähigen Element; (b) Verbinden einer Elektrode auf einer Seite des Parallelchips mit einer ersten Platine; und (c) Verbinden einer Elektrode auf der anderen Seite des Parallelchips mit einer zweiten Platine, können Chips in einer Schaltungsplatine zu geringe Kosten eingebettet werden, da eine Mehrzahl von Einheitschips auf einmal eingebettet und ein mechanischer Bohrer oder Fräser anstelle eines Laserbohrers beim Ausstanzen der Kavität oder von Durchlöchern verwendet werden kann.

Verfahren zur Herstellung eines Solarmoduls

Die Erfindung betrifft ein Verfahren zur Herstellung eines Solarmoduls aus einer Vielzahl von Solarzellen vom kristallinen Rückseitenkontakt-Typ, die über rückseitige Verbindungsleitungen kontaktiert und miteinander verschaltet sind.

HALBLEITERBAUELEMENT UND HERSTELLUNGSVERFAHREN

Ein integriertes Fan-Out-Package wird eingesetzt, wobei die dielektrischen Materialien unterschiedlicher Umverteilungsschichten eingesetzt werden, um die integrierten Fan-Out-Package-Prozessflüsse mit anderen Package-Anwendungen zu integrieren. Bei einigen Ausführungsformen wird eine Ajinomoto-Aufbaufolie oder ein Prepreg-Material als das Dielektrikum in mindestens einigen der überlagerten Umverteilungsschichten eingesetzt.

Leistungshalbleitermodul und Verfahren zum Herstellen eines Leistungshalbleitermoduls

Ein Leistungshalbleitermodul umfasst ein erstes Substrat, wobei das erste Substrat Aluminium umfasst, eine auf dem ersten Substrat angeordnete erste Aluminiumoxidschicht, eine auf der ersten Aluminiumoxidschicht angeordnete leitende Schicht, einen ersten Halbleiterchip, wobei der erste Halbleiterchip auf der leitenden Schicht angeordnet und mit dieser elektrisch verbunden ist und ein elektrisches Isolationsmaterial, das den ersten Halbleiterchip umschließt, wobei die erste Aluminiumoxidschicht dazu ausgebildet ist, den ersten Halbleiterchip von dem ersten Substrat elektrisch zu isolieren.

Reconstituted device including die and functional material

Dies from a wafer are reassembled with passive components and encapsulated to form a reconstituted electronic device 10 comprising a die 11, a passive, functioning component 13 and a metallic redistribution layer 15 which defines an electronic component in an area at least partially above the functioning material. The electronic component may be a metal-oxide-metal capacitor, an inductor or an antenna. The functioning material may be ceramic or it may be a ferrite. The functioning material may surround the die. In one embodiment the functioning material is a ceramic body with a metallic coating 110 (figure 10) on a face opposite that of the surface of the substrate on which the die and functioning material are embedded, a metallic via 102 (figure 9) is included through the ceramic body to contact the metal coating, the redistribution layer/ceramic body/metal coating structure forms a capacitor. In another embodiment the functioning material may be a metal carrier 120 (figure 11) with an ...

PROCEDURE FOR THE PRODUCTION OF HYBRID INTEGRATED CIRCUITS WITH AN ARRAY FROM RESEMBLING ELECTRONIC ELEMENTS.

VERFAHREN ZUR INTEGRATION WENIGSTENS EINES ELEKTRONISCHEN BAUTEILS IN EINE LEITERPLATTE SOWIE LEITERPLATTE

PROCEDURE FOR EMBEDDING A COMPONENT INTO A BASIS AND FOR THE FORMATION OF A CONTACT

METHOD FOR CONTACT BONDING ELECTRONIC COMPONENTS ON AN INSULATING SUBSTRATE AND COMPONENT MODULE PRODUCED ACCORDING TO SAID METHOD

THREE-DIMENSIONAL MULTICHIP MODULE SYSTEMS AND METHODS OF FABRICATION

MULTICHIP INTEGRATED CIRCUIT MODULE AND METHOD OF FABRICATION

MULTIPLE SEMICONDUCTOR CHIP ASSEMBLY AND MANUFACTURE

THREE-DIMENSIONAL MULTICHIP MODULE SYSTEMS AND METHODS OF FABRICATION

... 2106873 9217903 PCTABS00016 Multichip integrated circuit packages and methods of fabrication, along with systems for stacking such packages, are disclosed. In one embodiment, the multichip package has an array of contact pads on an upper surface thereof and an array of contact pads on a lower surface thereof. Connection means are provided for electrically coupling at least some of the contact pads on each package surface with selected ones of the contact pads on the other surface, or selected interconnection metallization which is disposed between integrated circuits located within the package. The contact pads of each surface array are preferably equal in number and vertically aligned such that multiple multichip packages may be readily stacked, with a conductive means disposed therebetween for electrically coupling the contact pads of one package to the pads of another package. In addition, various internal and external heat sink structures are provided which facilitate dissipation of ...

Verfahren zur Herstellung eines aus einem Isolierteil und einem mit diesem fest verbundenen elektrisch leitenden Teil bestehenden Gegenstandes

Verfahren zur Herstellung einer Halbleitervorrichtung und nach diesem Verfahren hergestellte Vorrichtung

Halbleitervorrichtung

Chip Carriers And Semiconductor Devices Including Redistribution Structures With Improved Thermal And Electrical Performance

Modularized MOSFET packaging structure

Wafer packaging method

Power module package

The invention provides a power module package. The integrated power module includes a substantially planar insulated metal substrate having at least one cut-out region; at least one substantially planar ceramic substrate disposed within the cut-out region, wherein the ceramic substrate is framed on at least two sides by the insulated metal substrate, the ceramic substrate including a first metal layer on a first side and a second metal layer on a second side; at least one power semiconductor device coupled to the first side of the ceramic substrate; at least one control device coupled to a first surface of the insulated metal substrate; a power overlay electrically connecting the at least one semiconductor power device and the at least one control device; and a cooling fluid reservoir operatively connected to the second metal layer of the at least one ceramic substrate, wherein a plurality of cooling fluid passages are provided in the cooling fluid reservoir.

Wavelength converted semiconductor light emitting device

Manufacturing method of semiconductor device and semiconductor device

Processes of welding

ELECTRICAL DISTRIBUTION DEVICE WITH BURIED CAPACITORS.

Electronic device including electrical connections on an encapsulation block

팬-아웃 반도체 패키지

... 본 개시는 관통홀을 갖는 제1연결부재, 제1연결부재의 관통홀에 배치되며 접속패드가 배치된 활성면 및 활성면의 반대측에 배치된 비활성면을 갖는 프로세서칩, 제1연결부재의 관통홀에 배치되며 접속패드가 배치된 활성면을 가지며 복수의 다이가 적층된 형태의 메모리칩, 제1연결부재와 메모리칩과 프로세서칩의 비활성면의 적어도 일부를 봉합하는 봉합재, 및 제1연결부재와 메모리칩의 활성면과 프로세서칩의 활성면 상에 배치된 제2연결부재를 포함하며, 제1 및 제2연결부재는 프로세서칩의 접속패드 및 메모리칩의 접속패드와 전기적으로 연결된 재배선층을 각각 포함하며, 프로세서칩의 접속패드 및 메모리칩의 접속패드는 제2연결부재의 재배선층을 통하여 서로 전기적으로 연결된 팬-아웃 반도체 패키지에 관한 것이다.

DUAL MOLDED MULTI-CHIP PACKAGE SYSTEM

SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF USING A HIGH POLYMER MATERIAL

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent a substrate, an insulating layer, a contact plug, and a metal line from breaking by forming them with a high polymer material. CONSTITUTION: A substrate(1) includes plural device modules(3). The substrate is comprised of a first insulating polymer material. A first dielectric is formed on the substrate and has a via hole. The first dielectric is comprised of a second insulating polymer material. A contact plug(7) is formed on the via hole. The contact plug is comprised of a first conductive polymer material. A metal line(9) is formed on the first dielectric to be electrically connected to the contact plug. The metal line is comprised of the second conductive polymer material. A second dielectric is formed on the metal line. The second dielectric is comprised of a third insulating polymer material. The first to third insulating polymer materials are polyimide. © KIPO 2008 ...

SEMICONDUCTOR PACKAGE, SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE

SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT, MULTI-LAYER PRINTED CIRCUIT BOARD, AND METHOD OF MANUFACTURING MULTI- LAYER PRINTED CIRCUIT BOARD

A semiconductor element, wherein copper transition layers (38) disposed on die pads (22) of an IC chip (20) are incorporated in a multi-layer printed circuit board (10), whereby the IC chip (20) can be connected electrically to the multi-layer printed circuit board (10) without using lead parts and sealing resin, the resin is prevented from remaining on an aluminum pad (24) by providing the copper transition layers (38) on the aluminum pad (24), and the connectability between the die pads (22) and via holes (60) and the reliability thereof can be increased. © KIPO & WIPO 2007 ...

집적된 고전압 디바이스들을 갖는 실리콘 다이

... 기판 상에 복수의 제1 디바이스들 및 복수의 제1 인터커넥트들을 형성하는 단계; 복수의 제2 디바이스들을 포함하는 제2 디바이스 층을 상기 복수의 제1 인터커넥트들 중의 인터커넥트들에 연결하는 단계, 및 상기 제2 디바이스 층 상에 복수의 제2 인터커넥트들을 형성하는 단계를 포함하는 방법. 복수의 제1 인터커넥트들과 복수의 제2 인터커넥트들 사이에 배치된 복수의 제1 회로 디바이스들을 포함하는 제1 디바이스 층, 및 상기 복수의 제1 인터커넥트들 및 상기 복수의 제2 인터커넥트들 중의 하나에 병치되어 연결된 복수의 제2 디바이스들을 포함하는 제2 디바이스 층을 포함하고, 상기 복수의 제1 디바이스들 및 상기 복수의 제2 디바이스들 중의 하나는 상기 복수의 제1 디바이스들 및 상기 복수의 제2 디바이스들 중의 다른 하나보다 더 고전압 범위를 갖는 디바이스들을 포함하는 장치.

SEMICONDUCTOR DEVICE WHICH FORMS A RE-DISTRIBUTION LAYER AND A MANUFACTURING METHOD THEREOF

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to prevent the imbalance of the top height of a conductive member by forming a second conductive layer when eliminating a first conductive layer. CONSTITUTION: Insulating layers(32,34) are formed on the top of a substrate. A first opening is formed on the insulating layer. The first opening exposes a concave part(33). second opening is arranged at the exterior of the first opening and does not expose the concave part. A first conductive and a second conductive member are formed inside the first opening and the second opening by depositing conductive materials. The first conductive member is left within the concave part. COPYRIGHT KIPO 2013 ...

Multi-die package comprising unit specific alignment? and unit specific routing

Light-emitting device

This invention discloses a light-emitting device capable of being applied with an alternative current directly, comprising a submount; at least one electronic element located on the submount; at least one light-emitting diode array chips located on the submount; at least one bonding pad located on the submount, and a conductive trace on the submount, wherein the conductive trace is electrically connected with the electronic element, the light-emitting diode array chip, and bonding pad.

Chip package and method for fabricating the same

A method for fabricating chip package includes providing a semiconductor chip with a metal bump, next adhering the semiconductor chip to a substrate using a glue material, next forming a polymer material on the substrate, on the semiconductor chip, and on the metal bump, next polishing the polymer material, next forming a patterned circuit layer over the polymer material and connected to the metal bump, and then forming a tin-containing ball over the patterned circuit layer and connected to the patterned circuit layer.

Semiconductor module containing circuit elements, method for manufacture thereof, and application thereof

A plurality of semiconductor elements (142) and passive elements (144) are fixed on a substrate (140). An insulation resin film (123) with a conductive film, respectively formed with an insulation resin film (122) and a conductive film (130), is pressed onto the substrate (140), so as to force the semiconductor elements (142) and passive elements (144) to be buried in the insulation resin film (122), and fixed under vacuum or a reduced pressure. Thereafter the substrate (140) is peeled off from the insulation resin film (122) and the formation of vias (121) and the patterning of the conductive film (120) are performed. A structural body (125) having semiconductor elements (142) and passive elements (144) sealed by the insulation resin film (122) on respective one side and another side being exposed is obtained.

Semiconductor package and method of manufacture

Disclosed is a method of manufacturing a semiconductor package, comprising disposing a semiconductor component in a recessed part of a carrier member, forming an adhesive material in the recessed part and the circumference of the semiconductor component, forming a dielectric layer on the adhesive material and the semiconductor component, forming a circuit layer on the dielectric layer to electrically connect the semiconductor component, and removing the lower part of the recessed part of the carrier member to retain the part on the sidewall of the recessed part as a support portion. The invention eliminates the need to form the conventional medium board and can thus reduce manufacturing costs and further provides the semiconductor package as described above.

Semiconductor package structure and semiconductor packaging method

The disclosure provides a semiconductor package structure, including a substrate, a first insulating layer disposed on the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer spaced apart by a second insulating layer.

Light-emitting device and method for manufacturing light-emitting device by means of light-emitting part towards surface of resin molding body, and anode and cathode exposed out of backside of resin molding body

The invention implements a miniature and compact light-emitting device. In light-emitting device (1), LED device (3~6) is embedded in resin molding body (2) by means of light-emitting part (32, 42, 52, 62) towards surface (21) of resin molding body (2), and anode (33, 43, 53, 63) and cathode (34, 44, 54, 64) exposed out of backside (23) of resin molding body (2).

Power overlay structure and method of making same

Multi-chip package

METHOD OF FORMING MONOLITHIC CMOS-MEMS HYBRID INTEGRATED, PACKAGED STRUCTURES

A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access ...

ELECTRONICS PACKAGE AND MANUFACTURING METHOD THEREOF

A method for manufacturing an electronics package is provided that comprises forming at least one module block by providing a carrier substrate having a recess, placing at least one electronic component die in said recess, filling said recess with a molding material, and depositing a circuit layer connected with said at least one component die. It further provides an electronics package, comprising a carrier substrate having a recess, at least one electronic component die placed in said recess, a molding material filling said recess, and a circuit layer connected with said at least one component die.

ASSEMBLAGE OF RADIOFREQUENCY CHIPS

The invention relates to the fabrication of radiofrequency transmission/reception devices (2). The invention makes provision for: the making of radiofrequency transmission/reception chips devoid of antennas; the connecting in series of the chips by at least two conducting wire elements whose respective lengths between two neighbouring chips are chosen as a function of the transmission/reception frequency, each element contacting electrically at least one terminal of a chip (3) and ensuring an at least temporary function of mechanical holding of the chips chainwise; and the cutting at regular intervals of the serial connection to form, for each chip, two strands (41', 42') of an antenna of the device.

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation. 1. A package structure , comprising:a circuit element;a first semiconductor die and a second semiconductor die, located on the circuit element;a heat dissipating element, connecting to the first semiconductor die, the first semiconductor die being between the circuit element and the heat dissipating element, wherein a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die; andan insulating encapsulation, encapsulating the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with a surface of the insulating encapsulation.2. The package structure of claim 1 , wherein in a cross-sectional view claim 1 , a sidewall of the heat dissipating element is substantially aligned with a sidewall of the first semiconductor die.3. The package structure of claim 1 , wherein the heat dissipating element comprising an adhesive base layer claim 1 , and a thermal conductivity coefficient of the ...

Method for embedding a component in a base

This publication discloses a method, in which the semiconductor components forming part of an electronic circuit, or at least some of them, are embedded in a base, such as a circuit board, during the manufacture of the base, when part of the base structure is, as it were, manufactured around the semiconductor components. According to the invention, through-holes for the semiconductor components are made in the base, in such a way that the holes extend between the first and second surface of the base. After the making of the holes, a polymer film is spread over the second surface of the base structure, in such a way that the polymer film also covers the through-holes made for the semiconductor components from the side of the second surface of the base structure. Before the hardening, or after the partial hardening of the polymer film, the semiconductor components are placed in the holes made in the base, from the direction of the first surface of the base. The semiconductor components are ...

Chip burn-in and test structure and method

A burn-in frame having at least one window and including resistors having resistor pads is situated on a flexible layer, and at least one integrated circuit chip having chip pads is situated in the at least one window. Via openings are formed in the flexible layer to extend to the chip pads and the resistor pads. A pattern of electrical conductors is applied over the flexible layer and extending into the vias. The at least one integrated circuit chip is burned in. The burn-in frame may further include fuses, frame contacts, and voltage bias tracks. After burning in the at least one integrated circuit chip, the chip pads can be electrically isolated and the at least one integrated circuit chip can be tested. This method can also be used to burn-in and test multichip modules.

Connection pad for embedded components in PCB packaging

Described herein are printed circuit boards (PCBs), PCB assemblies, and methods of manufacture thereof, which allow free placement of electrical components. The PCBs may have electrical pads that may couple to components through via-based connections and without the use of solder. The electrical components may be physically attached to the PCBs through tight fitting, lamination, and/or the use of adhesives. The distance between adjacent vias may be reduced, as accidental short-circuit risks due to solder bridging and similar effects are mitigated when the soldering process is bypassed. The PCB design and component placement may be flexible as to allow the use of electrical components with custom shape and/or customized terminal placement.

Semiconductor device, manufacturing method of semiconductor device, and RFID tag

The present invention provides a semiconductor device which is formed at low cost and has a great versatility, a manufacturing method thereof, and further a semiconductor device with an improved yield, and a manufacturing method thereof. A structure, which has a base including a plurality of depressions having different shapes or sizes, and a plurality of IC chips which are disposed in the depressions and which fit the depressions, is formed. A semiconductor device which selectively includes a function in accordance with an application, by using the base including the plurality of depressions and the IC chips which fit the depressions, can be manufactured at low cost.

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.

Chip package structure having at least one chip and at least one thermally conductive element and manufacturing method thereof

A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.

Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process

The present disclosure relates to a bulk complementary-metal-oxide-semiconductor (CMOS) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the thinned device die. Herein, a silicon material with a resistivity between 5 Ohm-cm and 30000 Ohm-cm does not exist between the second mold compound and the thinned device die.

METHOD FOR EMBEDDING A COMPONENT IN A BASE

A method, in which the semiconductor components forming part of an electronic circuit, or at least some of them, are embedded in a base, such as a circuit board, during the manufacture of the base, when part of the base structure is, as it were, manufactured around the semiconductor components. Through-holes for the semiconductor components are made in the base, in such a way that the holes extend between the first and second surface of the base. After the making of the holes, a polymer film is spread over the second surface of the base structure, in such a way that the polymer film also covers the through-holes made for the semiconductor components from the side of the second surface of the base structure. Before the hardening, or after the partial hardening of the polymer film, the semiconductor components are placed in the holes made in the base, from the direction of the first surface of the base. The semiconductor components are pressed against the polymer film in such a way that they ...

Package structure and method of manufacturing the same

Provided is a package structure includes a die having a first connector, a RDL structure disposed on the die, and a second connector. The RDL structure includes at least one elongated via located on and connected to the first connector. The second connector is disposed on and connected to the RDL structure.

Wafer-level package with enhanced performance

The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.

Package structure and method for forming the same

A package structure and method for forming the same are provided. The package structure includes a substrate and a package layer formed over the substrate. The package structure further includes an alignment structure formed over the package layer, and the alignment structure includes a first alignment mark formed in a trench, and the trench has a step-shaped structure.

Antenna substrate and antenna module including the same

An antenna substrate includes: a first substrate including an antenna pattern disposed on an upper surface of the first substrate; a second substrate having a first planar surface, an area of which is smaller than an area of a planar surface of the first substrate; and a flexible substrate connecting the first and second substrates to each other and bent to allow the first planar surface of the second substrate to face a side surface of the first substrate, which is perpendicular to the upper surface of the first substrate.

FILP CHIP PACKAGE

A flip chip package includes a substrate, a chip body bonding on the substrate and bumps connected between the chip body and the substrate. The substrate includes input wires and output wires. The chip body includes a first package unit including a first seal ring and first pads and a second package unit including a second seal ring and second pads. The chip body extends continuously between the first seal ring and the second seal ring. Each of the input wires has one end overlapping the chip body and the other end positioned at a first bonding region of the substrate. Each of the output wires has one end overlapping the chip body and the other end positioned at a second bonding region of the substrate. The first bonding region and the second bonding region are located at opposite sides of the chip body.

FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member.

Wireless Charging Package with Chip Integrated in Coil Center

A package includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die. A coil extends from the top surface to a bottom surface of the encapsulating material, and the device die is in the region encircled by the coil. At least one dielectric layer is formed over the encapsulating material and the coil. A plurality of redistribution lines is in the at least one dielectric layer. The coil is electrically coupled to the device die through the plurality of redistribution lines.

III nitride semiconductor device and method of manufacturing the same

Provided is a high quality III nitride semiconductor device in which, not only X-shaped cracks extending from the vicinity of the corners of semiconductor structures to the center portion thereof, but also crack spots at the center portion can be prevented from being formed and can provide a method of efficiently manufacturing the III nitride semiconductor device. The III nitride semiconductor device of the present invention includes a support and two semiconductor structures having a nearly quadrangular transverse cross-sectional shape that are provided on the support. The two semiconductor structures are situated such that one side surface of one of the two semiconductor structures is placed to face one side surface of the other of them. The support covers the other three side surfaces and of the four sides of the semiconductor structures.

Semiconductor Package

A semiconductor device is disclosed. The semiconductor device comprises a first die, a second die, and a redistribution structure. The first die and the second die are electrically connected to the redistribution structure. There are no solder bumps between the first die and the redistribution structure. There are no solder bumps between the second die and the redistribution structure. The first die and the second die have a shift with regard to each other from a top view.

CHIP PACKAGE STRUCTURE

A chip package structure is provided. The chip package structure includes a first redistribution structure including a dielectric structure and wiring layers in the dielectric structure. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive pillar over the first surface and electrically connected to the wiring layers. The chip package structure includes a second chip over the second surface. The second chip includes a second substrate and a second conductive pad over the second substrate, and the second conductive pad is between the second substrate and the first redistribution structure. The chip package structure includes a second conductive pillar over the second surface and electrically connected to the wiring layers.

Use of device assembly for a generalization of three-dimensional metal interconnect technologies

An assembly process properly positions and align a plurality of first die within a carrier substrate. The first die are positioned within cavities formed in the carrier substrate. The carrier substrate is then aligned with a second substrate having a plurality of second die fabricated therein. The first die and the second die are fabricated using different technologies. Aligning the carrier substrate and the second substrate aligns the first die with the second die. One or more first die can be aligned with each second die. Once aligned, a wafer bonding process is performed to bond the first die to the second die. In some cases, the carrier substrate is removed, leaving behind the first die bonded to the second die of the second substrate. In other cases, the carrier substrate is left in place as a cap. The second substrate is then cut to form die stacks.

Sеmiсоnduсtоr dеviсе аnd mеthоd оf fоrming а vеrtiсаl intеrсоnnесt struсturе fоr 3-D FО-WLСSР

А sеmiсоnduсtоr dеviсе is mаdе bу fоrming а first соnduсtivе lауеr оvеr а саrriеr. Тhе first соnduсtivе lауеr hаs а first аrеа еlесtriсаllу isоlаtеd frоm а sесоnd аrеа оf thе first соnduсtivе lауеr. А соnduсtivе pillаr is fоrmеd оvеr thе first аrеа оf thе first соnduсtivе lауеr. А sеmiсоnduсtоr diе оr соmpоnеnt is mоuntеd tо thе sесоnd аrеа оf thе first соnduсtivе lауеr. А first еnсаpsulаnt is dеpоsitеd оvеr thе sеmiсоnduсtоr diе аnd аrоund thе соnduсtivе pillаr. А first intеrсоnnесt struсturе is fоrmеd оvеr thе first еnсаpsulаnt. Тhе first intеrсоnnесt struсturе is еlесtriсаllу соnnесtеd tо thе соnduсtivе pillаr. Тhе саrriеr is rеmоvеd. А pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd. Тhе rеmаining pоrtiоn оf thе first соnduсtivе lауеr inсludеs аn intеrсоnnесt linе аnd UВМ pаd. А sесоnd intеrсоnnесt struсturе is fоrmеd оvеr а rеmаining pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd.

Sеmiсоnduсtоr dеviсе аnd mеthоd оf fоrming а vеrtiсаl intеrсоnnесt struсturе fоr 3-D FО-WLСSР

А sеmiсоnduсtоr dеviсе is mаdе bу fоrming а first соnduсtivе lауеr оvеr а саrriеr. Тhе first соnduсtivе lауеr hаs а first аrеа еlесtriсаllу isоlаtеd frоm а sесоnd аrеа оf thе first соnduсtivе lауеr. А соnduсtivе pillаr is fоrmеd оvеr thе first аrеа оf thе first соnduсtivе lауеr. А sеmiсоnduсtоr diе оr соmpоnеnt is mоuntеd tо thе sесоnd аrеа оf thе first соnduсtivе lауеr. А first еnсаpsulаnt is dеpоsitеd оvеr thе sеmiсоnduсtоr diе аnd аrоund thе соnduсtivе pillаr. А first intеrсоnnесt struсturе is fоrmеd оvеr thе first еnсаpsulаnt. Тhе first intеrсоnnесt struсturе is еlесtriсаllу соnnесtеd tо thе соnduсtivе pillаr. Тhе саrriеr is rеmоvеd. А pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd. Тhе rеmаining pоrtiоn оf thе first соnduсtivе lауеr inсludеs аn intеrсоnnесt linе аnd UВМ pаd. А sесоnd intеrсоnnесt struсturе is fоrmеd оvеr а rеmаining pоrtiоn оf thе first соnduсtivе lауеr is rеmоvеd.

POWER ROUTING FOR 2.5D OR 3D INTEGRATED CIRCUITS

Embodiments relate to an electronic circuit implemented using a first integrated circuit die, a second integrated circuit die, and an interposer connecting the first integrated circuit die to the second integrated circuit die. The first integrated circuit die implements a first electronic circuit. The first integrated circuit die includes a first set of contacts on a bottom surface, a buried power rail (BPR), and a plurality of through-silicon vias (TSV) for connecting the BPR to the first set of contacts. The interposer includes a second set of contacts and a power delivery network (PDN). Each contact of the second set of contact corresponds to a contact of the first set of contacts of the first integrated circuit die. The PDN is configured to route a power supply voltage to the second set of contacts.

MEMORY CIRCUITS

A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.

Method for producing an electrically conductive connection on a substrate, microelectronic device and method for the production thereof

The invention relates to a method (110) for producing an electrically conductive connection (112, 112′) on a substrate (114), comprising the following steps: a) providing a substrate (114), wherein the substrate (114) is configured for receiving an electrically conductive connection (112, 112′); b) providing a reservoir of an electrically conductive liquid alloy, wherein the reservoir has a surface at which the alloy has an insulating layer; c) providing a capillary (120) configured for taking up the electrically conductive liquid alloy; d) penetrating of a tip (122) of the capillary (120) under the surface of the reservoir and taking up of a portion of the alloy from the reservoir; and e) applying the portion of the alloy at least partly to the substrate (114) in such a manner that an electrically conductive connection (112, 112′) is formed from the alloy on the substrate (114), wherein the alloy remains on the substrate (114) by adhesion. The invention furthermore relates to a method ...

MULTICHIP MODULE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A metal base substrate for mounting a plurality of bare semiconductor chip devices thereon has first and second main surfaces. The first main surface has formed thereon at least one projection, and at least two recesses in which the bare semiconductor chip devices are to be mounted. The depth of these recesses is smaller than the length of said projection, and the recesses have a higher surface smoothness than said main surfaces of said metal substrate. The metal base substrate is partially chemically etched to form the projection, and the first main surface of the substrate is mechanically worked to form at least the recesses. The conductive projection is isolated from the portion on which the bare semiconductor chip devices are mounted, of the base substrate, and the conductive projection acts as a terminal that can be electrically connected to the outside on the first and second main surfaces of the base substrate.

METHOD FOR MANUFACTURING SOLDERLESS HIGH DENSITY ELECTRONIC MODULES

The invention relates to a fabrication method and technique for producing functional devices where active and/or passive components are embedded and interconnected during the substrate fabrication process. It is characteristic for the invention that the active and passive components are embedded into low-cost polymer substrates, preferably flexible, and interconnected using photodefinable dielectrics and the electroless copper deposition. Besides embedding passive components they can be fabricated using dielectrics and electroless deposition processes. The fabrication is carried out at ambient temperatures without vacuum-based processes like evaporation or sputtering. It is also an important advantage of the invention that wire bonding or soldering are not needed, since the latter interconnection techniques will meet increasing difficulties with higher frequencies and smaller interconnection volumes. The interconnections of active components produced with a technique according to the present ...

A MULTI-LAYER PACKAGE INCORPORATING A RECESSED CAVITY FOR A SEMICONDUCTOR CHIP

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To provide a semiconductor device allowed to be highly integrated and miniaturized and having a function equivalent to a system on-chip. SOLUTION: A plurality of semiconductor element chips 1a-1d are aligned at a narrow pitch so that the surfaces of respective chips 1a-1d are on the same plane and arranged like an array and gaps between respective semiconductor element chips 1a-1d are sealed by insulating seal resin 4, a reinforcing material 5 is stuck to the rear faces of these chips 1a-1d, and a stress buffering layer 6 is formed on the surfaces of the chips 1a-1d. Via-holes 7 are formed on the stress buffering layer 6 and metallic wires 2 are formed so as to electrically connect respective semiconductor element chips 1a-1d to constitute a semiconductor device. COPYRIGHT: (C)2004,JPO ...

СПОСОБ ИЗГОТОВЛЕНИЯ МИКРОЭЛЕКТРОННОГО УЗЛА НА ПЛАСТИЧНОМ ОСНОВАНИИ

Изобретение относится к технологии производства многокристальных модулей, микросборок с внутренним монтажом компонентов. Технический результат - уменьшение трудоемкости изготовления, расширение функциональных возможностей и повышение надежности микроэлектронных узлов. Достигается тем, что в способе изготовления микроэлектронного узла на пластичном основании перед установкой бескорпусных кристаллов и чип-компонентов соединяют круглую пластину по внешней ее части с опорным металлическим кольцом, наносят тонкий слой кремнийорганического полимера. Устанавливают бескорпусные кристаллы чип-компоненты, ориентируясь на ранее сформированный топологический рисунок, герметизируют кремнийорганическим полимером, достигая толщины полимера равной высоте кольца. Удаляют основание - круглую металлическую пластину, закрепляют дополнительную круглую металлическую пластину с обратной стороны микроэлектронного узла. Проводят коммутацию методом вакуумного напыления металлов или фотолитографией. Наносят слой ...

СПОСОБ ВСТРАИВАНИЯ КОМПОНЕНТА В ОСНОВАНИЕ И ФОРМИРОВАНИЯ ЭЛЕКТРИЧЕСКОГО КОНТАКТА С КОМПОНЕНТОМ

... 1. Способ встраивания компонента в основание и формирования электрических контактов с компонентом, включающий обеспечение базовой пластины в качестве основания, выполнение отверстия в базовой пластине, установку в отверстие компонента, имеющего на своей первой поверхности контактные площадки или контактные выступы для создания электрических контактов, закрепление компонента в отверстии, выполненном в базовой пластине, создание изолирующего слоя по меньшей мере на одной поверхности основания с возможностью закрытия компонента указанным изолирующим слоем, выполнение в изолирующем слое контактных отверстий для компонента, и создание проводников в контактных отверстиях и поверх изолирующего слоя для формирования электрических контактов с компонентом, отличающийся тем, что создают проводящие рисунки на базовой пластине, выбирают положение отверстия и совмещают компонент с проводящими рисунками, выполненными на базовой пластине, причем после выполнения отверстия наносят ленту или пленку в форме ...

Halbleiteranordnung und Verfahren zur Herstellung derselben

Leistungselektronisches Submodul mit Gleich- und Wechselspannungsanschlusselementen und Anordnung hiermit

Vorgestellt wird ein Submodul und eine Anordnung hiermit, wobei das Submodul eine Schalteinrichtung mit einem Substrat und hierauf angeordneten Leiterbahnen aufweist. Das Submodul weist eine erste und eine zweite Gleichspannungsleiterbahn und hiermit elektrisch leitend verbunden ein erstes und ein zweites Gleichspannungsanschlusselement, sowie eine Wechselspannungsleiterbahn und hiermit elektrisch leitend verbunden ein Wechselspannungsanschlusselement auf. Das Submodul weist weiterhin einem Isolierstoffformkörper auf, der die Schalteinrichtung rahmenartig umschließ. Hierbei liegt das erste Gleichspannungsanschlusselemente mit einem ersten Kontaktabschnitt auf einem ersten Auflagekörper des Isolierstoffformkörpers auf, das Wechselspannungsanschlusselement liegt mit einem zweiten Kontaktabschnitt auf einem zweiten Auflagekörper des Isolierstoffformkörpers auf. Eine erste Klemmeinrichtung ist dazu ausgebildet elektrisch isoliert durch eine erste Ausnehmung des erste Auflagekörpers hindurchzureichen ...

Verfahren und Herstellung eines Elektronikmoduls und Elektronikmodul

KURZDARSTELLUNG DER OFFENBARUNG Eine Anzahl von Halbleiterchips beinhaltet jeweils eine erste Hauptseite und eine der ersten Hauptseite gegenüberliegende zweite Hauptseite. Die zweite Hauptseite beinhaltet mindestens ein elektrisches Kontaktelement. Die Halbleiterchips werden auf einen Träger platziert. Eine Materialschicht wird in die Zwischenräume zwischen benachbarten Halbleiterchips eingebracht. Der Träger wird entfernt, und eine erste elektrische Kontaktschicht wird auf die ersten Hauptseiten der Halbleiterchips aufgebracht, so dass die elektrische Kontaktschicht elektrisch mit jedem der elektrischen Kontaktelemente verbunden ist.

Halbleiterbauelemente und Verfahren zur Herstellung von Halbleiterbauelementen

Bauelement, umfassend:ein Halbleitermaterial (1), das eine erste Hauptoberfläche (2), eine gegenüberliegende Oberfläche (3), die der ersten Hauptoberfläche gegenüberliegt, und eine seitliche Oberfläche (4), die sich von der ersten Hauptoberfläche zur gegenüberliegenden Oberfläche erstreckt, umfasst, wobei das Halbleitermaterial eine Funktionsfläche umfasst, die in einem Hochfrequenzbereich betrieben wird;ein erstes elektrisches Kontaktelement (5), das auf der ersten Hauptoberfläche (2) des Halbleitermaterials angeordnet ist;ein Glasmaterial (6), das eine zweite Hauptoberfläche (7) umfasst, wobei das Glasmaterial die seitliche Oberfläche (4) des Halbleitermaterials kontaktiert und wobei die erste Hauptoberfläche (2) des Halbleitermaterials und die zweite Hauptoberfläche des Glasmaterials in einer gemeinsamen Ebene angeordnet sind; undeine Metallschicht (11), die über der ersten Hauptoberfläche (2) des Halbleitermaterials und über dem Glasmaterial angeordnet ist, wobei eine passive elektronische ...

Ein Halbleitermodul und ein Verfahren zu dessen Fabrikation durch erweiterte Einbettungstechnologien

Halbleitermodul (100), das Folgendes umfasst:einen einzelnen zusammenhängenden Träger (20);mehrere auf dem einzelnen zusammenhängenden Träger (20) angeordnete Halbleiter-Transistorchips (30);mehrere auf dem einzelnen zusammenhängenden Träger angeordnete Halbleiter-Diodenchips (40);eine Kapselungsschicht (70), die über den Halbleiter-Transistorchips (30) und den Halbleiter-Diodenchips (40) angeordnet ist, wobei die Kapselungsschicht (70) Via-Verbindungen (71) zu den Halbleiter-Transistorchips (30) und den Halbleiter-Diodenchips (40) umfasst; undeine Metallisierungsschicht, die mehrere, mit den Via-Verbindungen (71) verbundene metallische Bereiche (72) umfasst,wobei der einzelne zusammenhängende Träger (20) ein DCB-Substrat (Direct Copper Bonded), ein DAB-Substrat (Direct Aluminium Bonded) oder ein AMB-Substrat (Active Metal Brazing) umfasst und wobei das DCB-, DAB- oder AMB-Substrat eine Keramikschicht (21) oder eine Dielektrikumsschicht umfasst.

VERFAHREN ZUM HERSTELLEN EINER INTEGRIERTEN SCHALTUNGSPACKUNGSSTRUKTUR.

HALBLEITERBAUELEMENTE UND VERFAHREN ZUR HERSTELLUNG

... ein Halbleiterbauelement und Verfahren zur Herstellung sind bereitgestellt, wobei das Halbleiterbauelement ein erstes System-auf-einem-Chip-Bauelement an ein erstes Speicherbauelement gebondet, ein zweites System-auf-einem-Chip-Bauelement an das erste Speicherbauelement gebondet, ein erstes Verkapselungsmaterial, das das erste System-auf-einem-Chip-Bauelement und das zweite System-auf-einem-Chip-Bauelement umgibt, ein zweites Verkapselungsmaterial, das das erste System-auf-einem-Chip-Bauelement, das zweite System-auf-einem-Chip-Bauelement und das erste Speicherbauelement umgibt, und eine Durchkontaktierung, die sich von einer ersten Seite des zweiten Verkapselungsmaterials zu einer zweiten Seite des ersten Verkapselungsmaterials erstreckt, aufweist, wobei die Durchkontaktierung außerhalb des ersten Verkapselungsmaterials liegt.

Verfahren zum Herstellen eines optoelektronischen Halbleiterbauelements und derartiges Halbleiterbauelement

HALBLEITERANORDNUNG.

Modulanordnung mit eingebetteten Komponenten und einer integrierten Antenne, Vorrichtung mit Modulanordnungen und Verfahren zur Herstellung

Die Erfindung bezieht sich auf eine Modulanordnung (1) mit einer Antennenschicht (2), einer Abschirmschicht (3), einer Verteilungsschicht (4) und einer Komponentenschicht (5). Die Antennenschicht (2) trägt eine integrierte Antennenvorrichtung (7). Die Abschirmschicht (3) hat eine abschirmende Wirkung gegenüber elektromagnetischen Signalen. Die Verteilungsschicht (4) weist Strukturen (8) zum Verteilen von Signalen und/oder elektrischer Energie auf. Schließlich trägt die Komponentenschicht (5) eingebettete elektronische Komponenten (9, 9', 9"). Weiterhin bezieht sich die Erfindung auf eine Vorrichtung mit Modulanordnungen sowie auf ein Verfahren zur Herstellung einer Modulanordnung (1).

Integration of silicon photonics IC for high data rate

Circuit module and method of manufacturing the same

Supercomputer using wafer scale integration

PROCEDURE FOR THE PRODUCTION OF AN ELECTRONIC MODULE

FLEXIBLE BUILDING GROUP OF STACKED CHIPS

MICROELECTRONIC SUBSTRATE WITH INTEGRATED DEVICES

PROCEDURE FOR THE INTEGRATION AT LEAST AN ELECTRONIC CONSTRUCTION UNIT IN A PRINTED CIRCUIT BOARD AS WELL AS PRINTED CIRCUIT BOARD

Power semiconductor module and fabrication method

A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

Method of forming a packaged semiconductor device

A method is used to form a packaged semiconductor device. A semiconductor device, which has an active surface, is placed in an opening of a circuit board. The circuit board has a first major surface and a second major surface having the opening, first vias that extend between the first major surface and the second major surface, first contact pads terminating the vias at the first major surface, and second contact pads terminating the vias at the second major surface. A dielectric layer is applied over the semiconductor device and the second major surface of the circuit board. An interconnect layer is formed over the dielectric layer. The interconnect layer has second vias electrically connected to the second contact pads, third vias that are electrically connected to the active surface of the semiconductor device, an exposed surface, and third contact pads at the exposed surface.

Serially interconnected vertical-cavity surface emitting laser arrays

Vertical Cavity Surface Emitting Laser (VCSEL) arrays with vias for electrical connection are disclosed. A Vertical Cavity Surface Emitting Laser (VCSEL) array in accordance with one or more embodiments of the present invention comprises a plurality of first mirrors, a plurality of second mirrors, a plurality of active regions, coupled between the plurality of first mirrors and the plurality of second mirrors, and a heatsink, thermally and mechanically coupled to the second mirror opposite the plurality of active regions, wherein an electrical path to at least one of the plurality of second mirrors is made through a via formed through a depth of the plurality of second mirrors, and a plurality of VCSELs in the VCSEL array are connected in series.

Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer

A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier

A semiconductor device includes a first semiconductor die or component having a plurality of bumps, and a plurality of first and second contact pads. In one embodiment, the first and second contact pads include wettable contact pads. The bumps are mounted directly to a first surface of the first contact pads to align the first semiconductor die or component. An encapsulant is deposited over the first semiconductor die or component. An interconnect structure is formed over the encapsulant and is connected to a second surface of the first and second contact pads opposite the first surface of the first contact pads. A plurality of vias is formed through the encapsulant and extends to a first surface of the second contact pads. A conductive material is deposited in the vias to form a plurality of conductive vias that are aligned by the second contact pads to reduce interconnect pitch.

Light-emitting diode die packages and illumination apparatuses using same

The present invention relates to an LED die package, which has a light-emitting diode die having a sapphire layer, a first doped layer doped with a p- or n-type dopant, and a second doped layer doped with a different dopant from that doped in the first doped layer. A surface of the sapphire layer opposite to the surface on which the first doped layer is disposed is formed with generally inverted-pyramidal-shaped recesses and overlaid with a phosphor powder layer. Each of the first and the second doped layers has an electrode-forming surface formed with an electrode, on which an insulation layer is disposed and formed with exposure holes for exposing the electrodes. The exposure holes are each filled with an electrically conductive linker.

Semiconductor device and its manufacture method

A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.

Method and system for ultra miniaturized packages for transient voltage suppressors

A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The transient voltage suppressor (TVS) assembly includes a semiconductor die including a contact surface on a single side of the die, the die further including a substrate comprising a layer of at least one of an electrical insulator material, a semi-insulating material, and a first wide band gap semiconductor having a conductivity of a first polarity, at least a TVS device including a plurality of wide band gap semiconductor layers formed on the substrate; a first electrode coupled in electrical contact with the TVS device and extending to the contact surface, and a second electrode electrically coupled to the substrate extending to the contact surface.

Semiconductor package, semiconductor apparatus and method for manufacturing semiconductor package

A semiconductor package includes: a metal plate including a first surface, a second surface and a side surface; a semiconductor chip on the first surface of the metal plate, the semiconductor chip comprising a first surface, a second surface and a side surface; a first insulating layer that covers the second surface of the metal plate; a second insulating layer that covers the first surface of the metal plate, and the first surface and the side surface of the semiconductor chip; and a wiring structure on the second insulating layer and including: a wiring layer electrically connected to the semiconductor chip; and an interlayer insulating layer on the wiring layer. A thickness of the metal plate is thinner than that of the semiconductor chip, and the side surface of the metal plate is covered by the first insulating layer or the second insulating layer.

Chip embedded packages and methods for forming a chip embedded package

A chip embedded package is provided, the chip embedded package including: a plurality of dies; wherein a first die of the plurality of dies is a chip implementing a first sensor technology, and wherein a second die of the plurality of dies is a chip implementing a second sensor technology; and wherein the plurality of dies are molded with an encapsulation material; wherein at least one of the first die and the second die includes a film interconnect.

Methods and applications of non-planar imaging arrays

System, devices and methods are presented that provide an imaging array fabrication process method, comprising fabricating an array of semiconductor imaging elements, interconnecting the elements with stretchable interconnections, and transfer printing the array with a pre-strained elastomeric stamp to a secondary non-planar surface.

TWO-SIDED-ACCESS EXTENDED WAFER-LEVEL BALL GRID ARRAY (eWLB) PACKAGE, ASSEMBLY AND METHOD

A two-sided-access (TSA) eWLB is provided that makes it possible to easily access electrical contact pads disposed on both the front and rear faces of the die(s) of the eWLB package. When fabricating the IC die wafer, metal stamps are formed in the IC die wafer in contact with the rear faces of the IC dies. When the IC dies are subsequently reconstituted in an artificial wafer, portions of the metal stamps are exposed through the mold of the artificial wafer. When the artificial wafer is sawed to singulate the TSA eWLB packages and the packages are mounted on PCBs, any electrical contact pad that is disposed on the rear face of the IC die can be accessed via the respective metal stamp of the IC die.

Multi-Stacked Package-on-Package Structures

A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

Method of packaging chip and chip package structure

A method of packaging a chip includes laminating a first substrate with a second substrate, the first substrate being capable of withstanding a greater stress than the second substrate; applying an adhesive layer on the second substrate; bonding the chip on the adhesive layer; and forming an encapsulation layer that covers at least the chip.

PACKAGE METHOD AND PACKAGE STRUCTURE OF FAN-OUT CHIP

A packaging method and a package structure of a fan-out chip are disclosed. The package structure comprises a first chip with bumps and a second chip without bumps, a first dielectric layer formed on a surface of the second chip and through-holes fabricated in the first dielectric layer; a plastic package material; a second dielectric layer; a metal redistribution layer for interconnecting within and between the first chip and the second chip; under bump metallization layers and micro-bumps. By fabricating the dielectric layers with the through-holes on the surfaces of the first chip and the second chip, exposing the bumps of the first chip and metal pads of the second chip and subsequently fabricating the metal redistribution layer, the interconnections within and between the first chip and the second chip are achieved and thereby the integrated package of the first chip and the second chip is achieved. 1. A packaging method of a fan-out chip , comprising:step 1): providing a first chip with bumps and a second chip without bumps, forming a first dielectric layer on a surface of the second chip, and fabricating through-holes in the first dielectric layer;step 2): providing a carrier with a bonding layer formed on a surface, and bonding the first chip and the second chip to the bonding layer side by side;step 3): packing the first chip and the second chip, wherein the bumps of the first chip and the through-holes of the first dielectric layer on the surface of the second chip are exposed after the packing.step 4): depositing a second dielectric layer covering the first chip and the second chip, patterning a plurality of windows each aligned to one bump of the first chip and one through-hole of the second chip;step 5): fabricating a metal redistribution layer to fill the plurality of windows, wherein the metal redistribution layer provides electrical connection within the first chip and the second chip, wherein the metal redistribution layer interconnects between the ...

Semiconductor package and method for manufacturing a semiconductor package

A semiconductor package includes at least one semiconductor element, an encapsulant, a first circuitry, a second circuitry and at least one first stud bump. The encapsulant covers at least a portion of the semiconductor element. The encapsulant has a first surface and a second surface opposite to the first surface. The first circuitry is disposed adjacent to the first surface of the encapsulant. The second circuitry is disposed adjacent to the second surface of the encapsulant. The first stud bump is disposed in the encapsulant, and electrically connects the first circuitry and the second circuitry. The first stud bump contacts the second circuitry directly.

Package Structures and Methods of Forming

Methods of forming and structures of packages are discussed herein. In an embodiment, a method includes forming a back side redistribution structure, and after forming the back side redistribution structure, adhering a first integrated circuit die to the back side redistribution structure. The method further includes encapsulating the first integrated circuit die on the back side redistribution structure with an encapsulant, forming a front side redistribution structure on the encapsulant, and electrically coupling a second integrated circuit die to the first integrated circuit die. The second integrated circuit die is electrically coupled to the first integrated circuit die through first external electrical connectors mechanically attached to the front side redistribution structure. 1. A structure comprising: a first integrated circuit die having an active side and a back side opposite from the active side,', 'an encapsulant laterally encapsulating the first integrated circuit die, a first surface of the encapsulant being coplanar with a surface of a die connector on an active side of the first integrated circuit die, a second surface of the encapsulant being opposite from the first surface of the encapsulant,', 'a first redistribution structure on the first surface of the of the encapsulant,', 'a second redistribution structure on the second surface of the encapsulant, and', 'a through via extending through the encapsulant, a first end of the through via extending into the second redistribution structure, the through via extending over a surface of the second redistribution structure facing the first redistribution structure; and, 'a first package comprisinga second integrated circuit die electrically coupled to the first integrated circuit die through first external electrical connectors, the first external electrical connectors being mechanically attached to the first redistribution structure.2. The structure of claim 1 , further comprising second external ...

Electronic apparatus and method for fabricating the same

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

Light emitting device reflective bank structure

Reflective bank structures for light emitting devices are described. The reflective bank structure may include a substrate, an insulating layer on the substrate, and an array of bank openings in the insulating layer with each bank opening including a bottom surface and sidewalls. A reflective layer spans sidewalls of each of the bank openings in the insulating layer.

Microelectronic packages and methods for the fabrication thereof

Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method comprises encapsulating a first semiconductor die having one or more core redistribution layers formed thereover in an outer molded body. The outer molded body has a portion, which circumscribes the core redistribution layer. One or more topside redistribution layers are produced over the core redistribution layer. A contact array is formed over the topside redistribution layer and electrically coupled to the first semiconductor die encapsulated in the outer molded body through the topside redistribution layers and the core redistribution layers.

Light emitting device and method for manufacturing the same

A light emitting device in an embodiment includes first and second light transmissive insulators and a light emitting diode arranged between them. First and second electrodes of the light emitting diode are electrically connected to a conductive circuit layer provided on a surface of at least one of the first and second light transmissive insulators. Between the first light transmissive insulator and the second light transmissive insulator, a third light transmissive insulator is embedded which has at least one of a Vicat softening temperature of 80° C. or higher and 160° C. or lower and a tensile storage elastic modulus of 0.01 GPa or more and 10 GPa or less.

Embedded die package multichip module

An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.

Semiconductor Structure and Method of Forming the Same

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region. 1. A structure comprising:a device die;an encapsulant encapsulating the device die therein;a first plurality of Redistribution Lines (RDLs) overlying and electrically coupling to the device die, wherein the first plurality of RDLs have a first pitch, and the first plurality of RDLs are substantially free from undercuts; anda second plurality of RDLs overlying and electrically coupling to the device die, wherein the second plurality of RDLs have a second pitch greater than the first pitch, and the second plurality of RDLs have undercuts.2. The structure of claim 1 , wherein each of the first plurality of RDLs and the second plurality of RDLs comprises an adhesion layer and a metal region over the adhesion layer claim 1 , wherein the adhesion layers in the first plurality of RDLs are free from undercuts claim 1 , and the adhesion layers in the second plurality of RDLs have undercuts.3. The structure of claim 1 , wherein all RDLs at a same level as the first plurality of RDLs are substantially free from undercuts claim 1 , and all RDLs at a same level as the second plurality of RDLs have undercuts.4. The structure of claim 1 , wherein all RDLs at levels underlying the first plurality of RDLs and over the device die are substantially free from ...

METHODS AND SYSTEMS FOR PACKAGING AN INTEGRATED CIRCUIT

A method for packaging an integrated circuit including a first semiconductor device and a second semiconductor device arranged on a substrate includes calculating parameters of a forming gas based on each of a curing temperature and an estimate of a surface trap density associated with the integrated circuit, dispensing a molding compound over the first semiconductor device, the second semiconductor device, and the substrate, and curing the molding compound in accordance with the curing temperature while flowing the forming gas in accordance with the calculated parameters. 1. A method for packaging an integrated circuit including a first semiconductor device and a second semiconductor device arranged on a substrate , the method comprising:calculating parameters of a forming gas based on (i) a curing temperature and (ii) an estimate of a surface trap density associated with the integrated circuit;dispensing a molding compound over the first semiconductor device, the second semiconductor device, and the substrate; andcuring the molding compound in accordance with the curing temperature while flowing the forming gas in accordance with the calculated parameters.2. The method of claim 1 , wherein flowing the forming gas includes flowing a reactive gas configured to react with the first semiconductor device and the second semiconductor device during curing.3. The method of claim 1 , further comprising selecting the forming gas in accordance with the calculated parameters to reform broken bonds of the first semiconductor device and the second semiconductor device resulting from the curing.4. The method of claim 3 , wherein the broken bonds are silicon-to-hydrogen bonds and the forming gas comprises H2.5. The method of claim 4 , wherein the forming gas further comprises N2.6. The method of claim 1 , wherein calculating the parameters includes determining at least one of (i) a mole ratio of the forming gas and (ii) a pressure of the forming gas.7. The method of claim 6 , ...

ANTENNA SUBSTRATE AND ANTENNA MODULE INCLUDING THE SAME

An antenna substrate includes: a first substrate including an antenna pattern disposed on an upper surface of the first substrate; a second substrate having a first planar surface, an area of which is smaller than an area of a planar surface of the first substrate; and a flexible substrate connecting the first and second substrates to each other and bent to allow the first planar surface of the second substrate to face a side surface of the first substrate, which is perpendicular to the upper surface of the first substrate. 1. An antenna substrate comprising:a first substrate including an antenna pattern, and having an upper surface, a lower surface opposing the upper surface and a side surface disposed between the upper and lower surfaces;a second substrate having a first planar surface, a second planar surface opposing the first planar surface and a side edge surface disposed between the first and second planar surfaces, wherein an area of each of the first and second planar surfaces is smaller than an area of each of the upper and lower surfaces of the first substrate; anda flexible substrate connecting the side surface of the first substrate and the side edge surface of the second substrate to each other, such that the second substrate is rotatable to allow the first planar surface of the second substrate to face the side surface of the first substrate.24-. (canceled)5. An antenna module comprising: a first substrate including an antenna pattern, and having an upper surface, a lower surface opposing the upper surface and a side surface disposed between the upper and lower surfaces,', 'a second substrate having a first planar surface, a second planar surface opposing the first planar surface and a side edge surface disposed between the first and second planar surfaces, wherein an area of each of the first and second planar surfaces is smaller than an area of each of the upper and lower surfaces of the first substrate, and', 'a flexible substrate connecting the ...

FLEXIBLE CIRCUITS ON SOFT SUBSTRATES

An article includes a solid circuit die on a first major surface of a substrate, wherein the solid circuit die includes an arrangement of contact pads, and wherein at least a portion of the contact pads in the arrangement of contact pads are at least partially exposed on the first major surface of the substrate to provide an arrangement of exposed contact pads; a guide layer including an arrangement of microchannels, wherein the guide layer contacts the first major surface of the substrate such that at least some microchannels in the arrangement of microchannels overlie the at least some exposed contact pads in the arrangement of exposed contact pads; and a conductive particle-containing liquid in at least some of the microchannels. Other articles and methods of manufacturing the articles are described. 1. An article , comprising:a solid circuit die on a first major surface of a substrate, wherein the solid circuit die comprises an arrangement of contact pads, and wherein at least a portion of the contact pads in the arrangement of contact pads are at least partially exposed on the first major surface of the substrate to provide an arrangement of exposed contact pads;a guide layer comprising an arrangement of microchannels, wherein the guide layer contacts the first major surface of the substrate such that at least some microchannels in the arrangement of microchannels overlie the at least some exposed contact pads in the arrangement of exposed contact pads; anda conductive particle-containing liquid in at least some of the microchannels.2. The article of claim 1 , wherein the solid circuit die is at least partially embedded in the first major surface of the substrate.3. The article of claim 1 , wherein the solid circuit die is embedded in the first major surface of the substrate.4. The article of claim 1 , wherein the substrate comprises a flexible polymeric material.5. The article of claim 1 , wherein the guide layer comprises a layer of a polymeric material and a ...

Chip packaging and composite system board

A chip packaging includes a substrate, a first chip, a molding material, a first circuit, and a second circuit. The substrate includes a bottom surface, a first top surface disposed above the bottom surface with a first height, and a second top surface disposed above the bottom surface with a second height. The first height is smaller than the second height. The first chip is disposed on the first top surface. The molding material is disposed on the substrate and covers the first chip. The first and second circuits are disposed on the molding material, and are respectively and electrically connected to the first chip and the second top surface of the substrate. The substrate is made of copper material with huge area and has the properties of high current withstand capacity and high thermal efficiency. The second top surface protects the first chip from damage.

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

Semiconductor package device and method of manufacturing the same

A semiconductor package device includes a first die, an adhesive layer, and an encapsulant layer. The first die comprises a first electrode at a first surface of the first die and a second electrode at a second surface of the first die opposite to the first surface of the first die. The adhesive layer is disposed on the first surface of the first die. The encapsulant layer encapsulates the first die and the adhesive layer, wherein substantially an entire surface of the second electrode is exposed from the encapsulant layer.

Three Terminal Solid State Plasma Monolithic Microwave Integrated Circuit

A solid state plasma monolithic microwave integrated circuit having single or multiple elemental devices with at least three terminals operating within the microwave, millimetre wave or terahertz bands, that can be configured within a parallel plate structure, which solid state plasma monolithic microwave integrated circuit comprises: (i) a semiconductor dielectric substrate ( 3 ); (ii) parallel plates ( 1, 2 ) which comprise an upper conducting parallel plate ( 1 ) and a lower conducting parallel plate ( 2 ) and which parallel plates ( 1, 2 ) are used to guide an electromagnetic wave; (iii) an isolating trench which is between the parallel plates ( 1, 2 ), and which is used to contain a solid state plasma; (iv) a distinct p-doped region and a distinct n-doped region which are within a first semiconductor region defined by the isolating trench below the upper conducting parallel plate ( 1 ), and which are connected to two electrical bias terminals, where at least one electrical bias terminal forms a radio frequency short to the upper parallel plate ( 1 ); and a p or n doped region within a second semiconductor region defined by the isolating trench above the lower conducting parallel plate ( 2 ) and connected to a third electrical bias terminal, where the third electrical bias terminal forms a radio frequency short to the lower conducting parallel plate ( 2 ), and wherein; a solid state plasma is able to be controlled by voltage biasing of the three electrical bias terminals to either reflect, absorb or transmit an electromagnetic wave.

Integrated fan-out packages and methods of forming the same

Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side. 1. A package structure , comprising:a semiconductor die, having an active side and an opposite side opposite to the active side;a redistribution circuit structure, disposed on the active side and electrically coupled to the semiconductor die; anda metallization element, having a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.2. The package structure of claim 1 , wherein the plate portion of the metallization element is in physical contact with the opposite side of the semiconductor die.3. The package structure of claim 1 , wherein the plate portion of the metallization element is sandwiched between the semiconductor die and the branch portion.4. The package structure of claim 1 , wherein the metallization element is thermally coupled to the semiconductor die.5. The package structure of claim 1 , further comprising:an insulating encapsulation, laterally encapsulating the semiconductor die and sandwiched between the redistribution circuit structure and the metallization element; andconductive terminals, disposed on and electrically connected to the redistribution circuit structure, wherein the redistribution circuit structure is sandwiched between the conductive terminals and the ...

Semiconductor device package and method of manufacturing the same

A semiconductor device package includes a substrate and an electronic component disposed on the substrate. The electronic component has an active surface facing away from the substrate. The substrate has a first conductive pad and a second conductive pad disposed thereon. The electronic component has a first electrical contact and a second electrical contact disposed on the active surface. The semiconductor device package further includes a first metal layer connecting the first electrical contact with the first conductive pad, a second metal layer connecting the second electrical contact with the second conductive pad, a first seed layer disposed below the first metal layer; and a first isolation layer disposed between the first metal layer and the second metal layer. A method of manufacturing a semiconductor device package is also disclosed.

Apparatus with Light Emitting or Absorbing Diodes

An exemplary printable composition of a liquid or gel suspension of diodes generally includes a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary apparatus may include: a plurality of diodes; at least a trace amount of a first solvent; and a polymeric or resin film at least partially surrounding each diode of the plurality of diodes. Various exemplary diodes have a lateral dimension between about 10 to 50 microns and about 5 to 25 microns in height. Other embodiments may also include a plurality of substantially chemically inert particles having a range of sizes between about 10 to about 50 microns.

Semiconductor Package with Conductive Carrier Integrated Heat Spreader

In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

Chip arrangement and a method for forming a chip arrangement

A chip arrangement is provided. The chip arrangement includes: a first chip electrically connected to the first chip carrier top side; a second chip electrically connected to the second chip carrier top side; and electrically insulating material configured to at least partially surround the first chip carrier and the second chip carrier; at least one electrical interconnect configured to electrically contact the first chip to the second chip through the electrically insulating material; one or more first electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier top side and second chip carrier top side, and one or more second electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier bottom side and second chip carrier bottom side.

Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

WIRING SUBSTRATE, SEMICONDUCTOR PACKAGE HAVING THE WIRING SUBSTRATE, AND MANUFACTURING METHOD THEREOF

Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via 1. A semiconductor package , comprising:a first power device having a first surface, a second surface opposite to the first surface, and a first terminal adjacent to the first surface of the first power device;a second power device having a first surface, a second surface opposite to the first surface, and a second terminal adjacent to the first surface of the second power device;a control device having a first surface, a second surface opposite to the first surface, and control device terminals adjacent to the first surface of the control device;a first lower wiring adjacent to the second surface of the first power device;a second lower wiring adjacent to the second surface of the second power device;a third lower wiring adjacent to the second surface of the control device;a first insulating layer covering the first power device, the second power device, the control device, the first lower wiring, the second lower wiring, and third lower wiring, the first insulating layer comprising first openings extending from a first surface of the first insulating layer to the first terminal, the second terminal, and the control device terminals;a first conductive layer over the first terminal and the second terminal but not over the control device terminals; the second conductive layer is ...

Manufacturing method of semiconductor package

A manufacturing method of a semiconductor package is provided as follows. A semiconductor die is provided, wherein the semiconductor die comprises a semiconductor substrate, an interconnection layer and a through semiconductor via, the interconnection layer is disposed on an active surface of the semiconductor substrate, the through semiconductor via penetrates the semiconductor substrate from a back surface of the semiconductor substrate to the active surface of the semiconductor substrate. An encapsulant is provided to laterally encapsulate the semiconductor die. A through encapsulant via penetrating through the encapsulant is formed.

Substrateless device and the method to fabricate thereof

A substrateless device comprises a plurality of first conductive elements and an encapsulant. The encapsulant encapsulates the plurality of first conductive elements, wherein the locations of the plurality of first conductive elements are fixed by the encapsulant; and a plurality of terminals of the plurality of first conductive elements are exposed outside the encapsulant, wherein the plurality of first conductive elements are not supported by a substrate.

Interconnect Chips

A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die. 1. A package comprisinga first device die and a second device die;an interconnect die bonded to the first device die and the second device die, wherein the interconnect die electrically connects the first device die to the second device die;an encapsulating material encapsulating the interconnect die therein; anda through-via penetrating through the encapsulating material to connect to the first device die.2. The package of further comprising an integrated passive device bonded to one of the first device die or the second device die.3. The package of further comprising an underfill comprisinga first portion between the first device die and the interconnect die; anda second portion between the first device die and the second device die.4. The package of claim 1 , wherein a first surface of the encapsulating material is coplanar with a second surface of the interconnect die.5. The package of further comprising a die-attach film underlying and contact a bottom surface of the interconnect die claim 1 , wherein the die-attach film is in the encapsulating material.6. The package of further comprising:a dielectric layer; anda first redistribution line comprising a via portion extending into the dielectric layer, and a line portion over the dielectric layer, wherein the die-attach film is over and contacting the line portion.7. The package of further comprising:a second redistribution line extending into the dielectric layer, wherein the through-via overlies and contacts a top ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a connection member having first and second surfaces opposing each other and including a redistribution layer, an integrated circuit chip disposed on the first surface of the connection member, and including a plurality of units, at least one capacitor on the first surface of the connection member and in proximity to the integrated circuit chip, and an encapsulant on the first surface of the connection member and encapsulating the integrated circuit chip and the at least one capacitor, wherein the plurality of units include core power units selected from the group consisting of a central processing unit, a graphics processing unit, and an artificial intelligence unit, at least one of the core power units is disposed adjacent to one edge of the integrated circuit chip, and the at least one capacitor is disposed adjacent to the one edge of the integrated circuit chip. 1. A semiconductor package , comprising:a connection member having first and second surfaces opposing each other, and including a redistribution layer;an integrated circuit chip disposed on the first surface of the connection member, having a connection electrode connected to the redistribution layer, and including a plurality of units;at least one capacitor disposed on the first surface of the connection member and disposed adjacent to the integrated circuit chip; andan encapsulant disposed on the first surface of the connection member, and encapsulating the integrated circuit chip and the at least one capacitor,wherein at least one of the core power units is disposed adjacent to a first edge of the integrate circuit chip, andthe at least one capacitor is disposed adjacent to the first edge of the integrated circuit chip.2. The semiconductor package of claim 1 , wherein the redistribution layer includes a wiring line directly connecting the core power units and the at least one capacitor.3. The semiconductor package of claim 1 , wherein the at least one capacitor ...

LIGHT EMITTING DEVICE REFLECTIVE BANK STRUCTURE

Reflective bank structures for light emitting devices are described. The reflective bank structure may include a substrate, an insulating layer on the substrate, and an array of bank openings in the insulating layer with each bank opening including a bottom surface and sidewalls. A reflective layer spans sidewalls of each of the bank openings in the insulating layer. 1. A light emitting structure comprising:a substrate;an insulating layer on the substrate;an array of bank openings extending completely through a thickness of the insulating layer, each bank opening including sidewalls;an array of laterally separate reflective bank layers within an array of bank openings in the insulating layer, wherein each reflective bank layer spans the sidewalls of a corresponding bank opening and is on the substrate within the bank opening;a corresponding array of vertical light emitting diode devices on the array of reflective bank layers within the array of bank openings.2. The light emitting structure of claim 1 , further comprising an array of sidewall passivation layers claim 1 , each sidewall passivation layer around the sidewalls of a corresponding light emitting diode device within a reflective bank layer.3. The light emitting structure of claim 2 , wherein each reflective bank layer is electrically connected to circuitry within the substrate.4. The light emitting structure of claim 3 , wherein a bottom surface of each reflective bank layer is on a conductive contact pad electrically connected to the circuitry within the substrate.5. The light emitting structure of claim 2 , wherein each vertical light emitting diode device in the array of vertical light emitting diode devices includes a micro p-n diode that includes a top p-doped or n-doped layer claim 2 , a lower p-doped or n-doped layer claim 2 , and one or more quantum well layers between the top and lower p-doped or n-doped layers claim 2 , and wherein the micro p-n diode includes one or more layers based on II-VI ...

Light-emitting device

A light-emitting device comprises a substrate; a first semiconductor stack formed on the substrate; a connecting part formed on the first semiconductor stack; and a plurality of droplets formed near the connecting part, wherein the plurality of droplets comprises a material same as that of the connecting part.

Method for forming a package arrangement and package arrangement

A method for forming a package arrangement is provided, which may include: arranging at least one chip over a carrier; at least partially encapsulating the at least one chip with encapsulation material, wherein the encapsulation material is formed such that at least a portion of the carrier is uncovered by the encapsulation material; forming an electrically conductive structure over the encapsulation material and on the portion of the carrier uncovered by the encapsulation material; removing the carrier; and then forming a redistribution structure over the chip and the electrically conductive structure, wherein the redistribution structure electrically couples the electrically conductive structure and the chip.

Fan-Out Package and Methods of Forming Thereof

An embodiment is a structure including a molding compound laterally encapsulating a chip with a contact pad. A first dielectric layer is formed overlying the molding compound. A first metallization layer is formed overlying the first dielectric layer, in which the first metallization layer extends through the first dielectric layer to contact the contact pad. A second dielectric layer is formed overlying the first metallization layer and the first dielectric layer. A second metallization layer is formed overlying the second dielectric layer and extends through the second dielectric layer to contact the first metallization layer. 1. A structure comprising:a chip comprising a substrate and a contact pad on the substrate;a molding compound laterally encapsulating the chip, none of the molding compound being vertically aligned with the chip;a first dielectric layer overlying the molding compound and the chip;a first metallization layer having a first portion and a second portion, the first portion of the first metallization layer overlying the first dielectric layer, the second portion of the first metallization layer extending through the first dielectric layer electrically coupled to the contact pad, wherein the second portion of the first metallization layer has a flat top;a second dielectric layer overlying the first metallization layer and the first dielectric layer; anda second metallization layer having a first portion and second portion, the first portion of the second metallization layer overlying the second dielectric layer, the second portion of the second metallization layer extending through the second dielectric layer electrically coupled to the first metallization layer, the second portion of the second metallization layer being vertically aligned with the second portion of the first metallization layer.2. The structure of claim 1 , wherein the second metallization layer physically contacts the first metallization layer.3. The structure of claim 1 , ...

Ultra-thin embedded semiconductor device package and method of manufacturing thereof

A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

LIGHT-EMITTING DEVICE

A light-emitting device of an embodiment of the present application comprises light-emitting units; a transparent structure having cavities configured to accommodate at least one of the light-emitting units; and a conductive element connecting at least two of the light-emitting units. 1. A light-emitting device , comprising:a flexible substrate comprising a connecting structure;a first optoelectronic unit arranged on the flexible substrate and comprising:a light-emitting structure which comprises a top surface, a first outmost side surface, a first semiconductor layer, a second semiconductor layer, and a light-emitting layer formed between the first semiconductor layer and the second semiconductor layer;a first bonding pad which comprises a second outmost side surface, covers the top surface and the first outmost side surface, and electrically connects to the first semiconductor layer and the connecting structure; anda passivation layer which comprises a third outmost side surface, locates on the first bonding pad, and covers the second outmost side surface; anda supporting structure arranged under the first optoelectronic unit and covering the third outmost side surface.2. The light-emitting device of claim 1 , further comprising a reflective layer arranged between the supporting structure and the flexible substrate.3. The light-emitting device of claim 2 , wherein the reflective layer comprises titanium dioxide or other white substance.4. The light-emitting device of claim 1 , wherein the supporting structure is pervious to light.5. The light-emitting device of claim 1 , wherein the flexible substrate and the supporting structure are arranged on opposite sides of the first optoelectronic unit.6. The light-emitting device of claim 1 , wherein the supporting structure has a first width claim 1 , the first optoelectronic unit has a second width claim 1 , and the first width is larger than the second width.7. The light-emitting device of claim 1 , further comprising a ...

WAFER-LEVEL CHIP SCALE PACKAGING STRUCTURE AND METHOD FOR MANUFACTURING SAME

The present disclosure provides a wafer-level chip scale packaging structure and a method for manufacturing the same. The method includes the following steps: 1) providing a first supporting substrate; 2) placing a first chip on the first supporting substrate, and forming a first packaging layer on the first chip; 3) separating the first chip and the surface of the first packaging layer in contact with the first chip from the first supporting substrate, and attaching the other surface of the first packaging layer to a second supporting substrate; 4) disposing a second packaging layer on the surface of the first packaging layer which is in contact with the first chip; 5) forming a rewiring layer on the second packing layer, the rewiring layer is electrically connected to the first chip; and 6) electrically connecting a second chip to the rewiring layer. 1. A method for preparing a wafer-level chip scale packaging structure , comprising:placing a first chip on a first supporting substrate;forming a first packaging layer on the first chip, wherein the first packaging layer comprises a first surface and a second surface opposing to each other, wherein the first chip is in contact of the first surface;separating the first packaging layer and the first chip from the first supporting substrate at the first surface of the first packaging layer;attaching the second surface of the first packaging layer to a second supporting substrate;disposing a second packaging layer on the first surface of the first packaging layer;forming a rewiring layer on the second packing layer, wherein the rewiring layer is electrically connected to the first chip; andattaching a second chip to the rewiring layer, wherein the second chip is electrically connected to the rewiring layer.2. The method for preparing a wafer-level chip scale packaging structure according to claim 1 , further comprising:before placing the first chip on the first supporting substrate, coating a release layer on the first ...

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

A semiconductor package has at least one die, a first redistribution layer and a second redistribution layer. The first redistribution layer includes a first dual damascene redistribution pattern having a first via portion and a first routing portion. The second redistribution layer is disposed on the first redistribution layer and over the first die and electrically connected with the first redistribution layer and the first die. The second redistribution layer includes a second dual damascene redistribution pattern having a second via portion and a second routing portion. A location of the second via portion is aligned with a location of first via portion. 1. A semiconductor package , comprising:a first die;a first redistribution layer, disposed over the first die and electrically connected with the first die, wherein the first redistribution layer includes a first dual damascene redistribution pattern and a first seed metallic pattern, the first dual damascene redistribution pattern includes a first via portion and a first routing portion located directly on the first via portion, and the first seed metallic pattern covers sidewalls of the first routing portion and covers sidewalls and a bottom surface of the first via portion; anda second redistribution layer, disposed on the first redistribution layer and over the first die and electrically connected with the first redistribution layer and the first die, wherein the second redistribution layer includes a second dual damascene redistribution pattern and a second seed metallic pattern, the second dual damascene redistribution pattern includes a second via portion and a second routing portion located directly on the second via portion, and the second seed metallic pattern covers sidewalls of the second routing portion and covers sidewalls and a bottom surface of the second via portion,wherein a location of the second via portion is aligned with a location of first via portion.2. The package according to claim 1 , ...

MULTI-RDL STRUCTURE PACKAGES AND METHODS OF FABRICATING THE SAME

Various arrangements of multi-RDL structure devices are disclosed. In one aspect, an apparatus is provided that includes a first redistribution layer structure and a second redistribution layer structure mounted on the first redistribution layer structure. A first semiconductor chip is mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure. 1. An apparatus , comprising:a first redistribution layer structure;a second redistribution layer structure mounted on the first redistribution layer structure, there being a gap between the first redistribution layer structure and the second redistribution layer structure; anda first semiconductor chip mounted on the second redistribution layer structure and electrically connected to both the second redistribution layer structure and the first redistribution layer structure.2. The apparatus of claim 1 , wherein the first redistribution layer structure comprises a first plurality of I/Os to electrically interface with a circuit board.3. The apparatus of claim 1 , comprising a second plurality of I/Os to electrically interface the second redistribution layer structure and the first redistribution layer structure.4. The apparatus of claim 1 , comprising plural bumpless interconnects to electrically connect the first semiconductor chip to the second redistribution layer structure.5. The apparatus of claim 1 , comprising plural surface components mounted on the first redistribution layer structure in spaced-apart relation to the first semiconductor chip.6. The apparatus of claim 1 , comprising a first molding material at least partially encasing the first semiconductor chip.7. The apparatus of claim 1 , comprising a second semiconductor chip mounted on the second redistribution layer structure in spaced-apart relation to the first semiconductor chip claim 1 , the second redistribution layer structure electrically ...

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package includes a chip, a redistribution structure, and first under-ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads. 1. A semiconductor package , comprising:a chip comprising conductive posts exposed at an active surface of the chip; a first dielectric layer, including first openings exposing the conductive posts of the chip;', 'a topmost metallization layer, disposed over the first dielectric layer and electrically connected to the conductive posts, wherein the topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads; and', 'a second dielectric layer, disposed on the topmost metallization layer and including second openings exposing the first contact pads; and, 'a redistribution layer disposed on the active surface of the chip, comprisingfirst under-ball metallurgies patterns disposed on the first contact pads, wherein the first under-ball metallurgy patterns extend on and contact sidewalls and top surfaces of the first contact pads.2. The semiconductor package of claim 1 , wherein the topmost metallization layer further comprises ...

Vertical Memory Module Enabled by Fan-Out Redistribution Layer

Vertical memory modules enabled by fan-out redistribution layer(s) (RDLs) are provided. Memory dies may be stacked with each die having a signal pad directed to a sidewall of the die. A redistribution layer (RDL) is built on sidewalls of the stacked dies and coupled with the signal pads. The RDL may fan-out to UBM and solder balls, for example. An alternative process reconstitutes dies on a carrier with a first RDL on a front side of the dies. The dies and first RDL are encapsulated, and the modules vertically disposed for a second reconstitution on a second carrier. A second RDL is applied to exposed contacts of the vertically disposed modules and first RDLs. The vertical modules and second RDL are encapsulated in turn with a second mold material. The assembly may be singulated into individual memory modules, each with a fan-out RDL on the sidewalls of the vertically disposed dies. 1. A method , comprising:disposing multiple memory dies to make a vertical stack, each memory die having a respective signal pad directed to an edge of the memory die in a common direction with the signal pads of the multiple memory dies; andbuilding a redistribution layer (RDL) on a sidewall of the stack of memory dies, the redistribution layer (RDL) perpendicular to the vertical stack and communicatively coupled with the signal pads.2. The method of claim 1 , wherein building the RDL on the sidewall includes communicatively coupling the RDL to the signal pads with solderless connections claim 1 , or includes applying a solderless process to communicatively couple the RDL to the signal pads.3. The method of claim 1 , further comprising building the RDL as a fan-out of conductive lines from the signal pads.4. The method of claim 1 , further comprising building the RDL to fan-out conductive lines from the signal pads to under ball metallization or to solder balls.5. The method of claim 1 , further comprising building multiple redistribution layers (RDLs) on the sidewall.6. The method of ...

WAFER-LEVEL PACKAGE WITH ENHANCED PERFORMANCE

The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die resides over a top surface of the multilayer redistribution structure. The multilayer redistribution structure includes at least one support pad that is on a bottom surface of the multilayer redistribution structure and vertically aligned with the first thinned die. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die. 1. An apparatus comprising:a first thinned die comprising a first device layer and a first dielectric layer over the first device layer, wherein the first device layer comprises a plurality of first die contacts at a bottom surface of the first device layer; the first thinned die resides over a top surface of the multilayer redistribution structure;', 'the at least one first support pad is on a bottom surface of the multilayer redistribution structure and vertically aligned with the first thinned die, such that the at least one first support pad is placed vertically below the first thinned die;', 'the plurality of package contacts are on the bottom surface of the multilayer redistribution structure and electrically isolated from the at least one first support pad; and', 'the redistribution interconnects connect the plurality of package contacts to certain ones of the plurality of first die contacts;, 'a multilayer redistribution structure comprising at least one first support pad, a plurality of package contacts, and redistribution interconnects, whereina first mold compound residing over the multilayer redistribution structure and around the first ...

LOGIC DRIVE BASED ON STANDARD COMMODITY FPGA IC CHIPS

A chip package used as a logic drive, includes: multiple semiconductor chips, a polymer layer horizontally between the semiconductor chips; multiple metal layers over the semiconductor chips and polymer layer, wherein the metal layers are connected to the semiconductor chips and extend across edges of the semiconductor chips, wherein one of the metal layers has a thickness between 0.5 and 5 micrometers and a trace width between 0.5 and 5 micrometers; multiple dielectric layers each between neighboring two of the metal layers and over the semiconductor chips and polymer layer, wherein the dielectric layers extend across the edges of the semiconductor chips, wherein one of the dielectric layers has a thickness between 0.5 and 5 micrometers; and multiple metal bumps on a top one of the metal layers, wherein one of the semiconductor chips is a FPGA IC chip, and another one of the semiconductor chips is a NVMIC chip. 1. A chip package comprising:a first semiconductor chip;a polymer layer on a same plane as the first semiconductor chip;a metal via in the polymer layer;a first interconnection scheme over the first semiconductor chip, polymer layer and metal via and across over an edge of the first semiconductor chip, wherein the first interconnection scheme comprises a first interconnection metal layer over the first semiconductor chip, polymer layer and metal via and across over the edge of the first semiconductor chip, a second interconnection metal layer over the first interconnection metal layer and a first insulating dielectric layer between the first and second interconnection metal layers, wherein the first semiconductor chip couples to the metal via through the first interconnection metal layer; anda second semiconductor chip over the first interconnection scheme and the first semiconductor chip, wherein the second semiconductor chip couples to the first semiconductor chip through the first and second interconnection metal layers.2. The chip package of further ...

Semiconductor package including lid structure with opening and recess

A semiconductor package structure including a package substrate, at least one semiconductor die, a lid structure, a first electronic component and a heat sink is provided. The package substrate has a first surface and a second surface opposite to the first surface. The semiconductor die is on the first surface of the package substrate and is surrounded by an encapsulating layer. The lid structure surrounds and is spaced apart from the encapsulating layer. The lid structure includes a first opening that is covered by the first surface of the package substrate. The first electronic component is over the first surface of the package substrate and arranged within the first opening of the lid structure. The heat sink covers the lid structure and the semiconductor die.

Electronics package including integrated structure with backside functionality and method of manufacturing thereof

An electronics package includes a support substrate, an electrical component having an active surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and at least one side wall of the electrical component. A functional layer comprising at least one functional component is formed on at least one of a sloped side wall of the insulating structure and a backside surface of the electrical component. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is electrically coupled to the functional layer through at least one via in the support substrate.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method are provided. The semiconductor package includes a die, a dummy cube, a stress relaxation layer, an encapsulant and a redistribution structure. The dummy cube is disposed beside the die. The stress relaxation layer covers a top surface of the dummy cube. The encapsulant encapsulates the die and the dummy cube. The redistribution structure is disposed over the encapsulant and is electrically connected to the die. The stress relaxation layer is interposed between the dummy cube and the redistribution structure. 1. A semiconductor package , comprising:a die;a dummy cube, disposed beside the die;a stress relaxation layer, covering a top surface of the dummy cube;an encapsulant encapsulating the die and the dummy cube; anda redistribution structure disposed over the encapsulant and electrically connected to the die,wherein the stress relaxation layer is interposed between the dummy cube and the redistribution structure.2. The semiconductor package of claim 1 , wherein the dummy cube is electrically isolated from the redistribution structure.3. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a portion of the encapsulant.4. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a polymeric layer claim 1 , and the polymeric layer is not in physical contact with the redistribution structure.5. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a first polymeric layer and a second polymeric layer claim 1 , and a material of the first polymeric layer is different from a material of the second polymeric layer.6. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a polymeric layer extending from the top surface of the dummy cube to the redistribution structure.7. The semiconductor package of claim 6 , wherein a material of the polymeric layer comprises polyimide claim 6 , polybenzooxazole claim 6 ...

Power semiconductor module and method for cooling power semiconductor module

The present disclosure relates to a power semiconductor module comprising a printed circuit board (PCB), and to method of cooling such a power semiconductor module. The module comprises a power semiconductor device and an island of thermally conducting foam embedded into the printed circuit board. The power semiconductor device and the island of thermally conducting foam are positioned on top of each other, and the island is arranged to form a path for a flowing coolant cooling the power semiconductor device.

Method of fabricating an optical module that includes an electronic package

Some forms include an electronic package that includes a photo-detecting receiver IC and a receiver IC. The electronic package includes a mold that encloses the photo-detecting receiver IC and the receiver IC. The photo-detecting receiver IC and the receiver IC are adjacent to one another without touching one another. Other forms include an optical module that includes a substrate and an electronic package mounted on the substrate. The electronic package includes a photo-detecting receiver IC and a receiver IC that are enclosed within a mold. The photo-detecting receiver IC and the receiver IC are adjacent to one another without touching. Other forms include a method that includes forming a mold that includes a photo-detecting receiver IC and a receiver IC that are adjacent to one another without touching. The photo-detecting receiver IC includes optical components that are exposed on a surface of the mold.

Semiconductor Module and a Method for Fabrication Thereof By Extended Embedding Technologies

The semiconductor module includes a carrier, a plurality of semiconductor transistor chips disposed on the carrier, a plurality of semiconductor diode chips disposed on the carrier, an encapsulation layer disposed above the semiconductor transistor chips and the semiconductor diode chips, and a metallization layer disposed above the encapsulation layer. The metallization layer includes a plurality of metallic areas forming electrical connections between selected ones of the semiconductor transistor chips and the semiconductor diode chips.

Semiconductor Packages and Methods of Forming the Same

Semiconductor packages and methods of forming the same are disclosed. Embodiments include forming a first recess in a first substrate, wherein a first area of an opening of the first recess is larger than a second area of a bottom of the first recess. The embodiments also include forming a first device, wherein a third area of a top end of the first device is larger than a fourth area of a bottom end of the first device. The embodiments also include placing the first device into the first recess, wherein the bottom end of the first device faces the bottom of the first recess, and bonding a sidewall of the first device to a sidewall of the first recess.

SYSTEM AND METHOD FOR A TRANSDUCER IN AN EWLB PACKAGE

According to an embodiment, a sensor package includes an electrically insulating substrate including a cavity in the electrically insulating substrate, an ambient sensor, an integrated circuit die embedded in the electrically insulating substrate, and a plurality of conductive interconnect structures coupling the ambient sensor to the integrated circuit die. The ambient sensor is supported by the electrically insulating substrate and arranged adjacent the cavity. 1. A method of forming a sensor package , the method comprising:forming an ambient sensor on a first surface of a dummy patterning structure;arranging the dummy patterning structure on a carrier substrate;arranging an integrated circuit die on the carrier substrate;embedding the dummy patterning structure and the integrated circuit die in electrically insulating material;removing the carrier substrate;exposing a second surface of the dummy patterning structure by thinning the electrically insulating material, the second surface opposite the first surface; andforming a cavity in the electrically insulating material by etching the dummy patterning structure.2. The method of claim 1 , further comprising forming a lid layer covering the cavity in the electrically insulating material claim 1 , the lid layer comprising an opening connected to the cavity.3. The method of claim 1 , wherein forming the ambient sensor comprises forming a gas sensor.4. The method of claim 3 , whereinthe dummy patterning structure comprises a plurality of dummy patterning structures;forming the gas sensor comprises forming a plurality of gas sensors, each gas sensor of the plurality of gas sensors being formed on a first surface of at least one dummy patterning structure of the plurality of dummy patterning structures;arranging the dummy patterning structure on the carrier substrate comprises arranging the plurality of dummy patterning structures on the carrier substrate; andforming the cavity in the electrically insulating material ...

Semiconductor Structure and Method of Forming the Same

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region. 1. A method comprising:encapsulating a device die in an encapsulating material;planarizing the encapsulating material and the device die; an adhesion layer; and', 'a metal region over the adhesion layer; and, 'forming a conductive feature over and electrically coupling to the device die, wherein the conductive feature comprisesafter the conductive feature is formed, performing a re-etching process, wherein in the re-etching process, the metal region is etched faster than the adhesion layer.2. The method of claim 1 , wherein before the re-etching process claim 1 , a first edge of the adhesion layer is laterally recessed more than a corresponding second edge of the metal region to form an undercut claim 1 , and the undercut is at least reduced in size by the re-etching process.3. The method of claim 2 , wherein the undercut is eliminated by the re-etching process.4. The method of claim 2 , wherein after the re-etching process claim 2 , the adhesion layer extends laterally beyond the corresponding second edge of the metal region.5. The method of claim 1 , wherein the forming the conductive feature comprises:depositing a first conductive material to form a first seed layer;depositing a second conductive material different from the first conductive ...

MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE

A manufacturing method of a semiconductor structure includes covering first and second semiconductor dies with an insulating encapsulant. The first semiconductor die includes an active surface accessibly exposed by the insulating encapsulant and a first conductive terminal distributed at the active surface. The second semiconductor die includes an active surface accessibly exposed by the insulating encapsulant and a second conductive terminal distributed at the active surface. A redistribution circuit layer is formed on the insulating encapsulant and the active surfaces of the first and second semiconductor dies. A conductive trace of the redistribution circuit layer is electrically connected from the first semiconductor die and meanderingly extends to the second semiconductor die, and a ratio of a total length of the conductive trace to a top width of the insulating encapsulant between the first and second semiconductor dies ranges from about 3 to about 10. 1. A manufacturing method of a semiconductor structure , comprising: the first semiconductor die comprises a first active surface accessibly exposed by the insulating encapsulant and a first conductive terminal distributed at the first active surface, and', 'the second semiconductor die comprises a second active surface accessibly exposed by the insulating encapsulant and a second conductive terminal distributed at the second active surface; and, 'covering a first semiconductor die and a second semiconductor die with an insulating encapsulant, wherein a conductive trace of the redistribution circuit layer is electrically connected from the first semiconductor die and meanderingly extends to the second semiconductor die, and', 'a ratio of a total length of the conductive trace to a top width of the insulating encapsulant between the first semiconductor die and the second semiconductor die ranges from about 3 to about 10., 'forming a redistribution circuit layer on the insulating encapsulant, the first active ...

Wafer-level package with enhanced performance

The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.

Diode for a Printable Composition

An exemplary printable composition of a liquid or gel suspension of diodes comprises a plurality of diodes, a first solvent and/or a viscosity modifier. An exemplary diode comprises: a light emitting or absorbing region having a diameter between about 20 and 30 microns and a height between about 2.5 to 7 microns; a first terminal coupled to the light emitting region on a first side, the first terminal having a height between about 1 to 6 microns; and a second terminal coupled to the light emitting region on a second side opposite the first side, the second terminal having a height between about 1 to 6 microns.

Redistribution Layers in Semiconductor Packages and Methods of Forming Same

An embodiment package includes a first integrated circuit die, an encapsulent around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant. 1. A method comprising:forming a first semiconductor die surrounded by a molding compound; a first bend in the area directly over the first semiconductor die;', 'a second bend outside of the area directly over the first semiconductor die; and', 'a first linear segment between the first bend and the second bend, the first linear segment extending directly over a boundary between the first semiconductor die and the molding compound., 'electrically connecting, with a metal line, a first conductive via in an area directly over the first semiconductor die to a second conductive via, the second conductive via is outside of the area directly over the first semiconductor die, wherein the metal line comprises2. The method of claim 1 , wherein the metal line further comprises a second linear segment extending from the first bend to the first conductive via.3. The method of claim 1 , wherein the metal line further comprises a third bend between the second bend and the second conductive via.4. The method of claim 1 , wherein an angle of the first bend is in a range of 120° to 150° claim 1 , and wherein an angle of the second bend is in a range of 120° to 150°.5. The method of claim 4 , wherein the angle of the first bend is equal to the angle of the second bend.6. The method of further comprising:forming a polymer layer over the first semiconductor die and the molding compound, wherein ...

Electronic circuit device

An electronic circuit device according to the present invention includes a plane-shaped shield member having conductivity, at least one electronic circuit element having a first surface opposed to a second surface on which a connecting part is formed, the first surface arranged on the plane-shaped shield member, a rewiring layer comprises an insulating photosensitive resin layer enclosing the electronic circuit element on the plane-shaped shield member, a plurality of wiring photo vias having a plurality of first conductors electrically connected to a connecting part of the electronic element, a wiring having a second conductor electrically connected to each of the plurality of wiring photo vias on the same surface parallel to the plane-shaped shield member, and a wall-shaped shield groove having a third conductor for a sealing arranged to surround a thickness direction of the electronic circuit element.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate; a first die disposed over the substrate; a second die disposed over the substrate; a molding disposed over the substrate and surrounding the first die and the second die; an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed over the first die, the second die and the molding, and the conductive member is surrounded by the dielectric layer; and a via extended within the second die and between the dielectric layer and the substrate. 1. A semiconductor structure , comprising:a substrate;a first die disposed over the substrate;a second die disposed over the substrate;a molding disposed over the substrate and surrounding the first die and the second die;an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed over the first die, the second die and the molding, and the conductive member is surrounded by the dielectric layer; anda via disposed between the dielectric layer and the substrate, the via extended within the second die.2. The semiconductor structure of claim 1 , wherein the substrate is electrically connected with the conductive member through the via.3. The semiconductor structure of claim 1 , wherein a thickness of the first die is substantially different from or same as a thickness of the second die.4. The semiconductor structure of claim 1 , wherein the molding is disposed between the first die and the dielectric layer.5. The semiconductor structure of claim 1 , wherein the second die is a functional or dummy die.6. The semiconductor structure of claim 1 , wherein the first die is electrically connected with the conductive member through the substrate and the via.7. The semiconductor structure of claim 1 , further comprising a conductive bump disposed over the dielectric layer and electrically connected with the conductive member.8. A semiconductor structure claim 1 , comprising:a ...

WIRING SUBSTRATE, SEMICONDUCTOR PACKAGE HAVING THE WIRING SUBSTRATE, AND MANUFACTURING METHOD THEREOF

Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via. 1. A semiconductor package comprising:a semiconductor device comprising a first wiring having a first terminal and a second terminal;an insulating film over the first wiring;a first layer over the insulating film and over the second terminal but not over the first terminal;an opening in the first layer over the second terminal;a first via that extends through the insulating film to expose at least a portion of the first terminal;a second via that extends from the opening through the insulating film to expose at least a portion of the second terminal; anda second layer having a first portion within the first via and having a second portion over the first layer and within the opening and the second via, wherein:the first portion of the second layer comprises a first wiring route;the second portion of the second layer and the first layer comprises a second wiring route; andthe first wiring route is devoid of the first layer.2. The semiconductor package according to claim 1 , wherein:the second portion of the second layer overlaps an upper surface of the first layer;the second portion of the second layer has a first thickness overlapping the upper surface of the first layer and a second thickness in the second via; andthe first thickness is less than the second thickness.3. The wiring ...

Multi-Stacked Package-on-Package Structures

A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure. 1. A device comprising:a first redistribution structure;a passive device disposed on the first redistribution structure, the passive device comprising a substrate and a through via (TV) extending through the substrate, the TV electrically connected to the first redistribution structure;a first encapsulant at least partially surrounding the passive device;a second redistribution structure disposed on the first encapsulant and the passive device, the second redistribution structure electrically connected to the TV of the passive device;integrated circuit dies disposed on the second redistribution structure, each of the integrated circuit dies electrically connected to the second redistribution structure; anda second encapsulant at least partially surrounding each of the integrated circuit dies.2. The device of claim 1 , wherein the passive device is an integrated voltage regulator.3. The device of claim 1 , wherein the integrated circuit dies comprise:a system-on-chip die; anda memory die adjacent the system-on-chip die.4. The device of further comprising:first conductive vias extending through the first encapsulant, the first conductive vias connecting the first redistribution structure to the second redistribution structure.5. The device of further comprising:a reflowable connector connecting the passive device to the second redistribution structure; andan underfill disposed around the reflowable connector, ...

Cross-Wafer RDLs in Constructed Wafers

A method includes placing a plurality of package components over a carrier, encapsulating the plurality of package components in an encapsulant, forming a light-sensitive dielectric layer over the plurality of package components and the encapsulant, exposing the light-sensitive dielectric layer using a lithography mask, and developing the light-sensitive dielectric layer to form a plurality of openings. Conductive features of the plurality of package components are exposed through the plurality of openings. The method further includes forming redistribution lines extending into the openings. One of the redistribution lines has a length greater than about 26 mm. The redistribution lines, the plurality of package components, the encapsulant in combination form a reconstructed wafer.

SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

A semiconductor structure includes an insulating encapsulant, a semiconductor element, a redistribution layer and an insulating layer. The semiconductor element is embedded in the insulating encapsulant. The redistribution layer is disposed over the insulating encapsulant and electrically connected to the semiconductor element. The insulating layer is disposed in between the insulating encapsulant and the redistribution layer, wherein an uneven interface exists between the insulating layer and the insulating encapsulant, and a planar interface exists between the insulating layer and the redistribution layer. 1. A semiconductor structure , comprising:an insulating encapsulant;a semiconductor element embedded in the insulating encapsulant;a redistribution layer disposed over the insulating encapsulant and electrically connected to the semiconductor element; andan insulating layer disposed in between the insulating encapsulant and the redistribution layer, wherein an uneven interface exists between the insulating layer and the insulating encapsulant, and a planar interface exists between the insulating layer and the redistribution layer.2. The semiconductor structure according to claim 1 , further comprising:a patterned first seed layer and a plurality of conductive pillars embedded in the insulating layer in between the uneven interface and the planar interface, wherein the patterned first seed layer is located at a first surface of the insulating layer having the uneven interface, and the plurality of conductive pillars is located at a second surface of the insulating layer having the planar interface.3. The semiconductor structure according to claim 2 , further comprising:a patterned second seed layer disposed on the insulating layer over the planar interface, wherein the patterned second seed layer is surrounded by a dielectric layer of the redistribution layer, and the patterned second seed layer is physically separated from the patterned first seed layer.4. The ...

ANTENNA SUBSTRATE AND ANTENNA MODULE INCLUDING THE SAME

An antenna substrate includes: a first substrate including an antenna pattern disposed on an upper surface of the first substrate; a second substrate having a first planar surface, an area of which is smaller than an area of a planar surface of the first substrate; and a flexible substrate connecting the first and second substrates to each other and bent to allow the first planar surface of the second substrate to face a side surface of the first substrate, which is perpendicular to the upper surface of the first substrate. 1. A module comprising:a first substrate having a lower surface;a semiconductor package disposed on the lower surface of the first substrate and including a radio frequency integrated circuit (RFIC);a second substrate having a first planar surface, a second planar surface opposing the first planar surface and a side edge surface disposed between the first and second planar surfaces, wherein an area of each of the first and second planar surfaces is smaller than an area of the lower surface of the first substrate;a flexible substrate connecting a side surface of the first substrate and the side edge surface of the second substrate to each other, and more flexible than the first and second substrates; andan electronic component disposed on the second planar surface of the second substrate and having electrodes which are respectively connected to the second substrate.2. The module of claim 1 , wherein the electronic component has a thickness greater than that of the RFIC.3. The module of claim 2 , wherein the electronic component is a power inductor (PI).4. The module of claim 1 , wherein the semiconductor package further includes at least one passive component disposed on the lower surface of the first substrate claim 1 , andwherein the electronic component has a thickness greater than that of the at least one passive component.5. The module of claim 4 , wherein the RFIC is surface-mounted on the lower surface of the first substrate claim 4 , ...

Semiconductor Device and Method of Manufacture

A method of manufacturing a semiconductor device includes applying a polymer mixture over a substrate, exposing and developing at least a portion of the polymer mixture to form a developed dielectric, and curing the developed dielectric to form a dielectric layer. The polymer mixture includes a polymer precursor, a photosensitizer, and a solvent. The polymer precursor may be a polyamic acid ester.

Fan-out semiconductor package

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a processor chip disposed in the through-hole; a memory chip disposed in the through-hole and including a plurality of dies stacked on each other; an encapsulant encapsulating at least portions of the first interconnection member, the memory chip, and the processor chip; and a second interconnection member disposed on the first interconnection member, an active surface of the memory chip, and an active surface of the processor chip. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to connection pads of the processor chip and connection pads of the memory chip, and the connection pads of the processor chip and the connection pads of the memory chip are electrically connected to each other by the redistribution layer of the second interconnection member.

Logic drive based on multichip package comprising standard commodity fpga ic chip with cooperating or supporting circuits

A multichip package includes: a chip package comprising a first IC chip, a polymer layer in a space beyond and extending from a sidewall of the first IC chip, a through package via in the polymer layer, an interconnection scheme under the first IC chip, polymer layer and through package via, and a metal bump under the interconnection scheme and at a bottom of the chip package, wherein the first IC chip comprises memory cells for storing data therein associated with resulting values for a look-up table (LUT) and a selection circuit comprising a first input data set for a logic operation and a second input data set associated with the data stored in the memory cells, wherein the selection circuit selects, in accordance with the first input data set, data from the second input data set as an output data for the logic operation; and a second IC chip over the chip package, wherein the second IC chip couples to the first IC chip through, in sequence, the through package via and interconnection scheme, wherein the second IC chip comprises a hard macro having an input data associated with the output data for the logic operation.

Semiconductor package with redistribution structure and manufacturing method thereof

A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

LIGHT EMITTING ARRAY STRUCTURE AND DISPLAY

Disclosed is a light-emitting array structure having a substrate, a plurality of light-emitting pixel units, a plurality of first and second signal wires, and an encapsulating layer. The light-emitting pixel units are arranged in array on the substrate. Each light-emitting pixel unit includes a driving chip, a first flat layer, a first redistribution layer, a second flat layer, a second redistribution layer, and a light-emitting diode. Each first signal wire is electrically connected to a corresponding one of the first redistribution layers and extends in a first direction. The second signal wires extend in a level different from the first signal wires. Each second signal wire is electrically connected to a corresponding one of the second redistribution layers and extends in a second direction different from the first direction. The encapsulating layer covers the light-emitting pixel units, the first and second signal wires, and the substrate. 1. A light-emitting array structure , comprising:a substrate; a driver chip disposed on the substrate;', 'a first flat layer disposed on the substrate and covers the driver chip;', 'a first redistribution layer disposed on the first flat layer and electrically connected to the driver chip;', 'a second flat layer disposed on the first flat layer and covers the first redistribution layer;', 'a second redistribution layer disposed on the second flat layer and electrically connected to the first redistribution layer; and', 'a light-emitting diode, flip-chip bonded to and in contact with the second redistribution layer;, 'a plurality of light-emitting pixel units arranged in array on the substrate, each of the light-emitting pixel units comprisinga plurality of first signal wires, wherein each of the first signal wires is electrically connected to a corresponding one of the first redistribution layers and extends in a first direction;a plurality of second signal wires extending in a level different from the first signal wires, ...

Embedded semiconductor device package and method of manufacturing thereof

A package structure includes a dielectric layer, at least one semiconductor device attached to the dielectric layer, one or more dielectric sheets applied to the dielectric layer and about the semiconductor device(s) to embed the semiconductor device(s) therein, and a plurality of vias formed to the semiconductor device(s) that are formed in at least one of the dielectric layer and the one or more dielectric sheets. The package structure also includes metal interconnects formed in the vias and on one or more outward facing surfaces of the package structure to form electrical interconnections to the semiconductor device(s). The dielectric layer is composed of a material that does not flow during a lamination process and each of the one or more dielectric sheets is composed of a curable material configured to melt and flow when cured during the lamination process so as to fill-in any air gaps around the semiconductor device(s).

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Provided are a package structure and a method of manufacturing the same. The method includes the following processes. A die is provided. An encapsulant is formed laterally aside the die. A first dielectric layer is formed on the encapsulant and the die. A first redistribution layer is formed to penetrate through the first dielectric layer to connect to the die, the first redistribution layer includes a first via embedded in the first dielectric layer and a first trace on the first dielectric layer and connected to the first via. The first via and the first trace of the first redistribution layer are formed separately. 1. A method of manufacturing a package structure , comprising:providing a die;forming an encapsulant laterally aside the die;forming a first dielectric layer on the encapsulant and the die; andforming a first redistribution layer penetrating through the first dielectric layer to connect to the die, the first redistribution layer comprises a first via embedded in the first dielectric layer and a first trace on the first dielectric layer and connected to the first via,wherein the first via and the first trace of the first redistribution layer are formed separately.2. The method of claim 1 , wherein the first via is formed before forming the first dielectric layer claim 1 , and the first trace is formed after forming the first dielectric layer.3. The method of claim 2 , further comprising performing a treatment process on the first via before forming the first dielectric layer claim 2 , such that the first via is tapered away from the die.4. The method of claim 3 , wherein the treatment process comprises an isotropic etch process.5. The method of claim 2 , wherein forming the first via comprises:forming a seed material layer on the encapsulant and the die;forming a first patterned mask layer on the seed material layer;removing a portion of the seed material layer exposed by the first patterned mask layer, and the first seed layer is formed;removing the ...

METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE

A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals. 1. A method of fabricating a semiconductor package , the method comprising:providing a semiconductor chip;forming a redistribution substrate having a first surface and a second surface opposite to each other, the redistribution substrate including a plurality of first pads and a plurality of second pads on the first surface thereof; andfabricating a package including a plurality of conductive structures, the redistribution substrate, the semiconductor chip, and a plurality of external connection terminals,wherein the semiconductor chip and the plurality of conductive structures are disposed on the second surface of the redistribution substrate, the plurality of conductive structures spaced apart from the semiconductor chip,wherein the plurality of external connection terminals are provided on the plurality of conductive structures and electrically connected to the plurality of conductive structures,wherein the redistribution substrate has a first region and a second region spaced apart from each other in a plan view,wherein the plurality of first pads are provided on the first region of the redistribution substrate,wherein the plurality of second pads are provided on the second region of the redistribution ...

Wireless transmission module and manufacturing method

A wireless transmission module, chips, a passive component, and a coil are integrated into an integral structure, so that an integration level of the wireless transmission module is improved. In addition, the integral structure can effectively implement independence of the module, and the independent module can be flexibly arranged inside structural design of an electronic device, and does not need to be disposed on a mainboard of the electronic device. Only an input terminal of the wireless transmission module needs to be retained on the mainboard of the electronic device. In addition, the integral structure can further effectively increase a capability of a product for working continuously and normally in an extremely harsh scenario, and improve product reliability. In addition, in the structure of the wireless transmission module, the chips and the coil are integrated, and signal transmission paths between the chips and the coil are relatively short.

IPD Modules with Flexible Connection Scheme in Packaging

A package includes a first package and a second package over and bonded to the first package. The first package includes a first device die, and a first encapsulant encapsulating the first device die therein. The second package includes an Independent Passive Device (IPD) die, and a second encapsulant encapsulating the IPD die therein. The package further includes a power module over and bonded to the second package. 1. A package comprising: a first device die; and', 'a first encapsulant encapsulating the first device die therein;, 'a first package comprising an Independent Passive Device (IPD) module comprising a plurality of IPD dies identical to each other, wherein each of the plurality of IPD dies is physically joined to respective neighboring IPD dies in the plurality of IPD dies; and', 'a second encapsulant encapsulating the IPD die therein; and, 'a second package over and bonded to the first package, the second package comprisinga power module over and bonded to the second package.2. (canceled)3. The package of claim 1 , wherein the plurality of IPD dies are electrically interconnected.4. The package of claim 1 , wherein each of the plurality of IPD dies comprises a passive device claim 1 , and the IPD die is free from active devices and additional passive devices.5. The package of claim 1 , wherein the second package and the power module form a package stack claim 1 , and the package further comprises a plurality of package stacks identical to the package stack over and bonded to the first package.6. The package of claim 5 , wherein the package stack and the plurality of package stacks in combination form an array.7. The package of further comprising:a metallic brace over and contacting the second package;a screw penetrating through the first package; anda bolt, wherein the bolt and the screw secure the metallic brace on the first package.8. The package of further comprising:a first plurality of solder regions bonding the first package to the second package; ...

HYBRID BRIDGED FANOUT CHIPLET CONNECTIVITY

A chip for hybrid bridged fanout chiplet connectivity, the chip comprising: a central chiplet; one or more first chiplets each coupled to the central chiplet using a plurality of fanout traces; and one or more second chiplets each coupled to the central chiplet using one or more interconnect dies (ICDs). 1. A chip for hybrid bridged fanout chiplet connectivity , the chip comprising:a central chiplet;one or more first chiplets each coupled to the central chiplet using a plurality of fanout traces; andone or more second chiplets each coupled to the central chiplet using one or more interconnect dies (ICDs).2. The chip of claim 1 , wherein each of the one or more second chiplets are positioned nearer to the central chiplet relative to the one or more first chiplets.3. The chip of claim 1 , wherein the one or more first chiplets are positioned in a first column of chiplets and the one or more second chiplets are positioned in a second column of chiplets.4. The chip of claim 1 , wherein the one or more first chiplets are positioned in a first row of chiplets and the one or more second chiplets are positioned in a second row of chiplets.5. The chip of claim 1 , wherein the one or more first chiplets are coupled to the central chiplet by a plurality of fanout trace layers layered on a wafer comprising the central chiplet claim 1 , the one or more first chiplets claim 1 , and the one or more second chiplets.6. The chip of claim 5 , wherein the one or more interconnect dies are bonded to a layer of the chip layered on the plurality of fanout trace layers.7. The chip of claim 1 , further comprising one or more conductive pillars.8. The chip of claim 7 , further comprising a plurality of caps for the one or more conductive pillars and the one or more interconnect dies (ICDs).9. The chip of claim 8 , wherein the one or more second chiplets include a plurality of second chiplets claim 8 , the one or more interconnecting dies include a plurality of interconnecting dies claim 8 , ...

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A package structure includes a semiconductor die and a redistribution circuit structure. The redistribution circuit structure is disposed on and electrically connected to the semiconductor die and includes a patterned conductive layer, a dielectric layer, and an inter-layer film. The dielectric layer is disposed on the patterned conductive layer. The inter-layer film is sandwiched between the dielectric layer and the patterned conductive layer, and the patterned conductive layer is separated from the dielectric layer through the inter-layer film. 1. A package structure , comprising:a semiconductor die; and a patterned conductive layer;', 'a dielectric layer, disposed on the patterned conductive layer; and', 'an inter-layer film, sandwiched between the dielectric layer and the patterned conductive layer, wherein the patterned conductive layer is separated from the dielectric layer through the inter-layer film., 'a redistribution circuit structure, disposed on and electrically connected to the semiconductor die, and comprising2. The package structure of claim 1 , further comprising:a seed layer, wherein the patterned conductive layer is disposed on the seed layer, and the patterned conductive layer is wrapped by the seed layer and the inter-layer film.3. The package structure of claim 1 , wherein a first surface of the inter-layer film is in physical contact with the patterned conductive layer claim 1 , a second surface of the inter-layer film is in physical contact with the dielectric layer claim 1 , and the first surface is opposite to the second surface.5. The package structure of claim 4 , wherein a thickness of the inter-layer film is greater than or substantially equal to 50 nm and is less than or substantially equal to 350 nm.6. The package structure of claim 1 , wherein the inter-layer film comprises a nanostructure layer claim 1 , and the nanostructure layer comprises a nanostructure layer of poly-crystalline CuO.7. The package structure of claim 6 , wherein ...

DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE

A display device includes a first electrode disposed on a substrate, a second electrode disposed on the substrate, and spaced apart from and facing the first electrode, at least one light emitting element disposed between the first electrode and the second electrode, a first conductive contact pattern disposed on the first electrode and electrically contacting the first electrode and an end of the at least one light emitting element, and a second conductive contact pattern disposed on the second electrode and electrically contacting the second electrode and another end of the at least one light emitting element. 1. A display device comprising:a first electrode disposed on a substrate;a second electrode disposed on the substrate, and spaced apart from and facing the first electrode;at least one light emitting element disposed between the first electrode and the second electrode;a first conductive contact pattern disposed on the first electrode and electrically contacting the first electrode and an end of the at least one light emitting element; anda second conductive contact pattern disposed on the second electrode and electrically contacting the second electrode and another end of the at least one light emitting element.2. The display device of claim 1 , whereinthe first conductive contact pattern and the second conductive contact pattern overlap the first electrode and the second electrode, respectively, in a plan view,the first conductive contact pattern and the second conductive contact pattern are directly connected to the first electrode and the second electrode, respectively, andan insulating material layer is not disposed in a region in which the first conductive contact pattern and the first electrode overlap in a plan view and a region in which the second conductive contact pattern and the second electrode overlap in a plan view.3. The display device of claim 2 , wherein the first electrode claim 2 , the second electrode claim 2 , the first conductive ...

PLANAR WAFER LEVEL FAN-OUT OF MULTI-CHIP MODULES HAVING DIFFERENT SIZE CHIPS

Package structures and methods are provided for constructing multi-chip package structures using semiconductor wafer-level-fan-out techniques in conjunction with back-end-of-line fabrication methods to integrate different size chips (e.g., different thicknesses) into a planar package structure. The packaging techniques take into account intra-chip thickness variations and inter-chip thickness differences, and utilize standard back-end-of-line fabrication methods and materials to account for such thickness variations and differences. In addition, the back-end-of-line techniques allow for the formation of multiple layers of wiring and inter-layer vias which provide high density chip-to-chip interconnect wiring for high-bandwidth I/O communication between the package chips, as well as redistribution layers to route power/ground connections between active-side connections of the semiconductor chips to an area array of solder bump interconnects on a bottom side of the multi-chip package structure. 1. A package structure , comprising:a semiconductor substrate carrier comprising a first trench and a second trench disposed in a surface of the semiconductor substrate carrier;a first semiconductor integrated circuit chip comprising a first array of contact pads disposed on an active surface of the first semiconductor integrated circuit chip, wherein the first semiconductor integrated circuit chip is disposed in the first trench with the active surface of the first semiconductor integrated circuit chip facing outward from the first trench;a second semiconductor integrated circuit chip comprising a second array of contact pads disposed on an active surface of the second semiconductor integrated circuit chip, wherein the second semiconductor integrated circuit chip is disposed in the second trench with the active surface of the second semiconductor integrated circuit chip facing outward from the second trench;wherein the active surface of at least one of the first and second ...

Wireless Charging Package with Chip Integrated in Coil Center

A package includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die. A coil extends from the top surface to a bottom surface of the encapsulating material, and the device die is in the region encircled by the coil. At least one dielectric layer is formed over the encapsulating material and the coil. A plurality of redistribution lines is in the at least one dielectric layer. The coil is electrically coupled to the device die through the plurality of redistribution lines.

Fan-out semiconductor package

A fan-out semiconductor package includes: a first connection member having a through-hole; a first component disposed in the through-hole; a second component disposed in the through-hole and attached to the first component; an encapsulant filling at least portions of spaces between walls of the through-hole and side surfaces of the first component and side surfaces of the second component; a second connection member disposed on the first connection member and the first component; and a third connection member disposed on the first connection member and the second component. A number of at least one of the first or second components is plural, the second and third connection members are connected to each other through the first connection member, and the first connection member includes a redistribution layer electrically connected to a redistribution layer of the second connection member and a redistribution layer of the third connection member.

INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF

An integrated fan-out package includes a first and second dies, an encapsulant, and a redistribution structure. The first and second dies respectively has an active surface, a rear surface opposite to the active surface, and conductive posts on the active surface. The first and second dies are different types of dies. The active and rear surfaces of the first die are respectively levelled with the active and rear surfaces of the second die. Top surfaces of the conductive posts of the first and second dies are levelled. The conductive posts of the first and second dies are wrapped by same material. The encapsulant encapsulates sidewalls of the first and second dies. A first surface of the encapsulant is levelled with the active surfaces. The second surface of the encapsulant is levelled with the rear surfaces. The redistribution structure is disposed over the first die, the second die, and the encapsulant. 15-. (canceled)6. A manufacturing method of an integrated fan-out package , comprising:providing a carrier having an adhesive layer formed thereon;providing a first die and a second die on the adhesive layer, wherein a height of the first die is different from a height of the second die, the first die has first conductive posts and the second die has second conductive posts, the first conductive posts have substantially a same height, and the second conductive posts have substantially a same height;pressing the first die and the second die against the adhesive layer to make the active surfaces of the first die and the second die be in direct contact with the adhesive layer and the first and second conductive posts be submerged into the adhesive layer;curing the adhesive layer;forming an encapsulant to encapsulate the first die and the second die;removing the carrier from the adhesive layer;reducing heights of the first and second conductive posts and removing at least a portion of the adhesive layer such that the first and second conductive posts are laterally ...

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Provided is a package structure includes a die having a first connector, a RDL structure disposed on the die, and a second connector. The RDL structure includes at least one elongated via located on and connected to the first connector. The second connector is disposed on and connected to the RDL structure. 1. A package structure , comprising:a die having a first connector;a RDL structure disposed on the die, the RDL structure comprises at least one elongated via located on and connected to the first connector; anda second connector disposed on and connected to the RDL structure.2. The package structure of claim 1 , wherein the at least one elongated via comprises a first elongated via and a second elongated via arranged in parallel.3. The package structure of claim 2 , wherein the RDL structure further comprises a first trace and a second trace arranged in parallel and connected to the first elongated via and the second elongated via respectively.4. The package structure of claim 1 , wherein a shape of a top surface of the at least one elongated via is configured as a rectangle claim 1 , an oval claim 1 , a racetrack shape claim 1 , a combination of a square and an arc claim 1 , or a combination thereof.5. The package structure of claim 1 , wherein the elongated via includes a bottom surface and a side wall claim 1 , and a base angle of the elongated via defined by the sidewall and the bottom surface is equal to or less than 90°.6. The package structure of claim 1 , wherein the elongated via has a top surface claim 1 , and a bottom surface opposite to the top surface and connected to the first connector claim 1 , and wherein the bottom surface has an area larger than an area of the top surface.7. The package structure of claim 6 , wherein a shape of the elongated via is configured as a truncated cone.8. The package structure of claim 6 , wherein the elongated via comprises a seed layer and a conductive layer on the seed layer claim 6 , wherein the seed layer has an ...

SEMICONDUCTOR COMPONENT, PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package manufacturing having a semiconductor substrate, a bonding layer, at least one semiconductor device, a redistribution circuit structure and an insulating encapsulation. The bonding layer is disposed on the semiconductor substrate. The at least one semiconductor device is disposed on and in contact with a portion of the bonding layer, wherein the bonding layer is located between the semiconductor substrate and the at least one semiconductor device and adheres the at least one semiconductor device onto the semiconductor substrate. The redistribution circuit structure is disposed on and electrically connected to the at least one semiconductor device, wherein the at least one semiconductor device is located between the redistribution circuit structure and the bonding layer. The insulating encapsulation wraps a sidewall of the at least one semiconductor device, wherein a sidewall of the bonding layer is aligned with a sidewall of the insulating encapsulation and a sidewall of the redistribution circuit structure. 18-. (canceled)9. A method for manufacturing a package structure , comprising:providing a semiconductor substrate;forming a first bonding layer on the semiconductor substrate;disposing at least one semiconductor device on the semiconductor substrate;fusion bonding the at least one semiconductor device to the semiconductor substrate through a portion of the first bonding layer;forming an insulating encapsulation to at least wrap a sidewall of the at least one semiconductor device;performing a first planarizing step to planarize the insulating encapsulation;forming a redistribution circuit structure on the at least one semiconductor device and on the insulating encapsulation; anddisposing conductive elements on the redistribution circuit structure.10. The method as claimed in claim 9 , wherein the first bonding layer is formed in a blanket manner to cover on the semiconductor substrate.11. The method as claimed in claim 9 , wherein forming the insulating ...

SEMICONDUCTOR CHIP PACKAGE HAVING OPTICAL INTERFACE

A semiconductor package including: a chip including a pad; an optical device including a pad; a mold configured to encapsulate the optical device and the chip; a wiring pattern configured to electrically connect the optical device and the chip; and an external connection terminal configured to electrically connect the semiconductor package to the outside. The chip includes at least one of: an amplifier circuit configured to process an electrical signal supplied from the optical device; and a driver circuit configured to supply the electrical signal to the optical device. 1. A semiconductor package comprising:a chip including a pad;an optical device including a pad;a mold configured to encapsulate the optical device and the chip;a wiring pattern configured to electrically connect the optical device and the chip; andan external connection terminal configured to electrically connect the semiconductor package to the outside.2. The semiconductor package of claim 1 , wherein the mold is a transparent mold claim 1 ,wherein the outside of the semiconductor package and the optical device communicate with each other using an optical signal passing through the transparent mold.3. The semiconductor package of claim 1 , wherein an opening into which an optical cable for supplying an optical signal is inserted is formed in the mold.4. The semiconductor package of claim 1 , wherein the chip comprises at least one of:an amplifier circuit configured to process an electrical signal supplied from the optical device; anda driver circuit configured to supply the electrical signal to the optical device.5. The semiconductor package of claim 1 , wherein the semiconductor package comprises a plurality of chips claim 1 ,wherein the plurality of chips comprise at least one of:a chip including an amplifier circuit; anda chip including a driver circuit.6. The semiconductor package of claim 1 , wherein the semiconductor package further comprises a chip configured to perform at least one signal ...

Three-dimensional structure in which wiring is provided on its surface

One aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, the three-dimensional structure having an insulating resin layer that contains a filler formed from at least one element selected from typical non-metal elements and typical metal elements, wherein a recessed gutter for wiring is formed on a surface of the insulating resin layer, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

Apparatus and method for chip placement and molding

An approach is provided for placing and securing a chip package portion in an aligned position during a curing process. The approach involves providing an apparatus having a first reservoir configured to receive a first chip package, a second reservoir, and a third reservoir. The approach also involves placing the first chip package portion into the first reservoir, the second chip package portion into the second reservoir, and the third chip package portion into the third reservoir. The approach further involves causing the first chip package portion to be secured in a first curing position, the second chip package portion to be secured in a second curing position and the third chip package portion to be secured in a third curing position.

SEMICONDUCTOR PACKAGE WITH IMPROVED BANDWIDTH

A semiconductor chip package includes a first die and a second die. The first die and second die are coplanar and disposed in proximity to each other in a side-by-side fashion. A non-straight line shaped interface gap is disposed between the first die and second die. A molding compound surrounds the first die and second die. A redistribution layer (RDL) structure is disposed on the first die, the second die and on the molding compound. The first semiconductor die is electrically connected to the second semiconductor die through the RDL structure. 1. A semiconductor chip package , comprising:a first semiconductor die and a second semiconductor die, wherein the first semiconductor die and second semiconductor die are coplanar and disposed in proximity to each other in a side-by-side fashion;a non-straight line shaped interface gap between the first semiconductor die and second semiconductor die;a molding compound surrounding the first semiconductor die and second semiconductor die; anda redistribution layer (RDL) structure on the first semiconductor die, the second semiconductor die and on the molding compound, wherein the first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.2. The semiconductor chip package according to claim 1 , wherein the first semiconductor die and the second semiconductor die have identical circuit module design.3. The semiconductor chip package according to claim 1 , wherein the first semiconductor die has a first inter-die cut edge and the second semiconductor die has a second inter-die cut edge along the non-straight line shaped interface gap claim 1 , wherein the first inter-die cut edge and the second inter-die cut edge are complementary to each other.4. The semiconductor chip package according to claim 3 , wherein the first semiconductor die comprises a plurality of first input/output (I/O) pads disposed along the first inter-die cut edge and the second semiconductor die comprises a ...

LIGHT EMITTING DIODE DISPLAY WITH REDUNDANCY SCHEME

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities. 1. A display panel with redundancy scheme comprising:a display substrate including a pixel area that includes an array of subpixels, each subpixel including a pair of landing areas;an array of redundant LED bonding site pairs, each landing area including a corresponding LED bonding site;wherein the array of subpixels includes a first subpixel array, a second subpixel array, and a third subpixel array, wherein the first, second, and third subpixel arrays are designed to emit different primary color emissions;circuitry to switch and drive the array of subpixels; andone or more LED device irregularities among the array of redundant LED bonding site pairs, wherein each corresponding landing area containing a micro LED device irregularity is electrically disconnected from the circuitry.2. The display panel of claim 2 , wherein each corresponding landing area is cut to electrically disconnect the corresponding landing area from the circuitry.3. The display panel of claim 3 , wherein the circuitry is contained within an array of micro controller chips.4. The display panel of claim 3 , wherein the array of micro controller chips is bonded to the display substrate.5. The display panel of claim 4 , wherein each micro controller chip is bonded to the display substrate within the pixel area.6. The display panel of claim 5 , wherein each micro controller chip is connected to a scan driver ...