Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год
Применить Всего найдено 73779. Отображено 100.
05-01-2012 дата публикации

Semiconductor device

Номер: US20120001341A1
Автор: Akihiro Niimi, Shigeo Ide
Принадлежит: Denso Corp

The semiconductor device has a unit stack body including a plurality of units stacked on one another. Each unit includes a power terminal constituted of a lead part and a connection part. The connection part is formed with a projection and a recess. When the units are stacked on one another, the projection of one unit is fitted to the recess of the adjacent unit, so that the power terminals of the respective unit are connected to one another.

Подробнее
Номер записи: 1
12-01-2012 дата публикации

Light emitting module

Номер: US20120007076A1
Автор: Yun Min CHO
Принадлежит: LG Innotek Co Ltd

Disclosed is a light emitting module capable of representing improved heat radiation and improved light collection. there is provided a light emitting module. The light emitting module includes a metallic circuit board formed therein with a cavity, and a light emitting device package including a nitride insulating substrate attached in the cavity of the metallic circuit board, at least one pad part on the nitride insulating substrate, and at least one light emitting device attached on the pad part.

Подробнее
Номер записи: 2
12-01-2012 дата публикации

Light emitting apparatus, and method for manufacturing the same, and lighting system

Номер: US20120007123A1
Автор: Bum Chul Cho
Принадлежит: Bum Chul Cho

A light emitting apparatus includes: a substrate including a first conductive type impurity; a first heatsink and a second heatsink on a first region and a second region of the substrate; second conductive type impurity regions on the substrate and electrically connected to the first heatsink and the second heatsink, respectively; a first electrode electrically connected to the first heatsink on the substrate; a second electrode electrically connected to the second heatsink on the substrate; and a light emitting device electrically connected to the first electrode and the second electrode on the substrate.

Подробнее
Номер записи: 3
12-01-2012 дата публикации

System-in-a-package based flash memory card

Номер: US20120007226A1
Автор: Hem Takiar, Michael W. Patterson, Robert C. Miller, Shrikar Bhagath, Warren Middlekauff
Принадлежит: SanDisk Technologies LLC

A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.

Подробнее
Номер записи: 4
12-01-2012 дата публикации

Microelectronic packages with dual or multiple-etched flip-chip connectors

Номер: US20120007232A1
Автор: Belgacem Haba
Принадлежит: TESSERA RESEARCH LLC

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Подробнее
Номер записи: 5
12-01-2012 дата публикации

Redistribution layers for microfeature workpieces, and associated systems and methods

Номер: US20120007256A1
Автор: David Pratt
Принадлежит: Micron Technology Inc

Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device.

Подробнее
Номер записи: 6
12-01-2012 дата публикации

Power semiconductor module and fabrication method

Номер: US20120009733A1
Автор: Eladio Clemente Delgado, Ernest Wayne Balch, Kevin Matthew Durocher, Paul Alan McConnelee, Raymond Albert Fillion, Richard Alfred Beaupre, Stephen Daley Arthur
Принадлежит: General Electric Co

A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

Подробнее
Номер записи: 7
19-01-2012 дата публикации

Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another

Номер: US20120013028A1
Автор: Belgacem Haba, Ilyas Mohammed
Принадлежит: Tessera LLC

A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element.

Подробнее
Номер записи: 8
26-01-2012 дата публикации

Integrated lighting apparatus and method of manufacturing the same

Номер: US20120018745A1
Автор: Cheng Nan Han, Chih-Chiang Lu, Hsin-Mao Liu, Meng-Yuan Hong, Min-Hsun Hsieh, Ta-Cheng Hsu, Tsung-Xian Lee, Tzer-Perng Chen
Принадлежит: Epistar Corp

An integrated lighting apparatus includes at least a lighting device, a control device comprising an integrated circuit, and a connector that is used to electrically connect the lighting device and the control device. With the combination, the integrated circuit drives the lighting device in accordance with its various designed functionality, thus expands applications of the integrated lighting apparatus.

Подробнее
Номер записи: 9
26-01-2012 дата публикации

Stack package and method for manufacturing the same

Номер: US20120018879A1
Автор: Cheol-Ho JOH, Eun-Hye DO, Hee-Min SHIN, Ji-Eun Kim, Kyu-Won Lee
Принадлежит: Hynix Semiconductor Inc

A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

Подробнее
Номер записи: 10
02-02-2012 дата публикации

Integrated circuit combination of a target integrated circuit and a plurality of cells connected thereto using the top conductive layer

Номер: US20120025342A1
Автор: Ofer Navon, Ram Friedlander, Reuven Holzer, Shani Keysar
Принадлежит: SOL CHIP Ltd

A target integrated circuit (TIC) having a top conductive layer (TCL) that may be connected to a plurality of cells that are further integrated over the TIC. Each of the plurality of cells comprises two conductive layers, a lower conductive layer (LCL) below the cell and an upper conductive layer (UCL) above the cell. Both conductive layers may connect to the TCL of the TIC to form a super IC structure combined of the TIC and the plurality of cells connected thereto. Accordingly, conductivity between the TIC as well as auxiliary circuitry to the TIC maybe achieved.

Подробнее
Номер записи: 11
02-02-2012 дата публикации

Semiconductor device comprising a passive component of capacitors and process for fabrication

Номер: US20120025348A1
Автор: Laurent Marechal, Romain Coffy, Yvon Imbs
Принадлежит: STMicroelectronics Grenoble 2 SAS

A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.

Подробнее
Номер записи: 12
16-02-2012 дата публикации

Composite Electronic Circuit Assembly

Номер: US20120039004A1
Автор: Alain Artieri
Принадлежит: ST Ericsson Grenoble SAS, St Ericsson SA

A composite electronic circuit assembly comprises two MOS or CMOS circuit dice ( 100, 200 ) superimposed inside a package. Different modules of the circuit assembly are distributed between the two dice based on the digital, analog, or hybrid nature of said modules. Such a distribution makes it possible to group together the digital modules of the circuit assembly in one of the die and the analog or hybrid modules in the other die. The production cost, development time, and electrical energy consumption of the circuit assembly may thus be reduced.

Подробнее
Номер записи: 13
01-03-2012 дата публикации

Bumpless build-up layer package with pre-stacked microelectronic devices

Номер: US20120049382A1
Автор: Pramod Malatkar
Принадлежит: Intel Corp

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

Подробнее
Номер записи: 14
08-03-2012 дата публикации

Light emitting diode package

Номер: US20120056217A1
Автор: Do Hyung Kim, HeeTak Oh, Jung Hwa Jung, Oh Sug Kim, You Jin KWON
Принадлежит: Seoul Semiconductor Co Ltd

Disclosed herein is a light emitting diode package including a package body having a cavity, a light emitting diode chip having a plurality of light emitting cells connected in series to one another, a phosphor converting a frequency of light emitted from the light emitting diode chip, and a pair of lead electrodes. The light emitting cells are connected in series between the pair of lead electrodes.

Подробнее
Номер записи: 15
15-03-2012 дата публикации

Light emitting device and manufacturing method of light emitting device

Номер: US20120061703A1
Автор: Mitsuhiro Kobayashi
Принадлежит: Toshiba Corp

A light emitting device may include a base provided with a recess portion in a side surface thereof, a light emitting element mounted on a main surface of the base, a first resin body filled in an inside of the recess portion, and covering at least the main surface and the light emitting element, a second resin body covering an outside of the first resin body from the main surface side to at least a position of the lowermost end of the recess portion in a direction orthogonal to the main surface, and phosphor, provided in the second resin body, for absorbing light emitted from the light emitting element and then emitting light having a different wavelength.

Подробнее
Номер записи: 16
15-03-2012 дата публикации

Control device of semiconductor device

Номер: US20120061722A1
Автор: Masahiro MASUNAGA, Takayuki Hashimoto
Принадлежит: Renesas Electronics Corp

A control device of a semiconductor device is provided. The control device of a semiconductor device is capable of reducing both ON resistance and feedback capacitance in a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided. In the control device controlling driving of a hollow-gate type planar MOSFET to which a second gate electrode is provided or a trench MOSFET to which a second gate electrode is provided, a signal of tuning ON or OFF is outputted to a gate electrode in a state of outputting a signal of turning OFF to the second gate electrode.

Подробнее
Номер записи: 17
15-03-2012 дата публикации

Semiconductor package integrated with conformal shield and antenna

Номер: US20120062439A1
Автор: Chi-Hong Chan, Kuo-Hsien Liao, Shih Fuyu
Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor package integrated with conformal shield and antenna is provided. The semiconductor package includes a semiconductor element, an electromagnetic interference shielding element, a dielectric structure, an antenna element and an antenna signal feeding element. The electromagnetic interference shielding element includes an electromagnetic interference shielding film and a grounding element, wherein the electromagnetic interference shielding film covers the semiconductor element and the grounding element is electrically connected to the electromagnetic interference shielding layer and a grounding segment of the semiconductor element. The dielectric structure covers a part of the electromagnetic interference shielding element and has an upper surface. The antenna element is formed adjacent to the upper surface of the dielectric structure. The antenna signal feeding element passing through the dielectric structure electrically connects the antenna element and the semiconductor element.

Подробнее
Номер записи: 18
15-03-2012 дата публикации

Method of manufacture of integrated circuit packaging system with stacked integrated circuit

Номер: US20120064668A1
Автор: Henry Descalzo Bathan, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

Подробнее
Номер записи: 19
15-03-2012 дата публикации

Semiconductor device including coupling conductive pattern

Номер: US20120064827A1
Автор: Hee-Seok Lee, Jong-Joo Lee, Sang-Youb Lee, Yong-Hoon Kim, Young-don Choi
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

Подробнее
Номер записи: 20
22-03-2012 дата публикации

Massively Parallel Interconnect Fabric for Complex Semiconductor Devices

Номер: US20120068229A1
Автор: Farhang Yazdani, Majid Bemanian
Принадлежит: Individual

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

Подробнее
Номер записи: 21
22-03-2012 дата публикации

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

Номер: US20120068319A1
Автор: Daesik Choi, Oh Han Kim, SangMi Park
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

Подробнее
Номер записи: 22
22-03-2012 дата публикации

High speed digital interconnect and method

Номер: US20120068890A1
Автор: Baher S. Haroun, Marco Corsi, Nirmal C. Warke, Siraj Akhtar
Принадлежит: Texas Instruments Inc

In some developing interconnect technologies, such as chip-to-chip optical interconnect or metal waveguide interconnects, misalignment can be a serious issue. Here, however, a interconnect that uses an on-chip directional antenna (which operates in the sub-millimeter range) to form a radio frequency (RF) interconnect through a dielectric waveguide is provided. This system allows for misalignment while providing the increased communication bandwidth.

Подробнее
Номер записи: 23
29-03-2012 дата публикации

Re-emitting semiconductor construction with enhanced extraction efficiency

Номер: US20120074381A1
Автор: Catherine A. Leatherdale, Michael A. Haase, Terry L. Smith, Yasha Yi, Zhaohui Yang
Принадлежит: 3M Innovative Properties Co

A stack of semiconductor layers ( 310 ) forms a re-emitting semiconductor construction (RSC). The stack ( 310 ) includes an active region ( 316 ) that converts light at a first wavelength to light at a second wavelength, the active region ( 316 ) including at least one potential well. The stack ( 310 ) also includes an inactive region ( 318 ) extending from an outer surface of the stack to the active region. Depressions ( 326 ) are formed in the stack ( 310 ) that extend from the outer surface into the inactive region ( 318 ). An average depression depth is at least 50% of a thickness of the inactive region. Alternatively, the average depression depth is at least 50% of a nearest potential well distance. Still other alternative characterizations of the depressions ( 326 ) are also disclosed. The depressions ( 326 ) may have at least a 40% packing density in plan view. The depressions ( 326 ) may also have a substantial portion of their projected surface area associated with obliquely inclined surfaces.

Подробнее
Номер записи: 24
29-03-2012 дата публикации

Semiconductor module including a switch and non-central diode

Номер: US20120074428A1
Автор: Gourab Majumdar, Kiyoshi Arai
Принадлежит: Mitsubishi Electric Corp

A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Подробнее
Номер записи: 25
29-03-2012 дата публикации

Semiconductor device

Номер: US20120074542A1
Автор: Shin Soyano
Принадлежит: Fuji Electric Co Ltd

A semiconductor device, in which a control circuit board is mountable outside a sheath case and a power semiconductor element is placeable inside the sheath case, includes a metal step support, a shield plate and a metal ring. The support includes a base portion implanted in the sheath case, a connection portion which extends from an end of the base portion, and a step portion formed at a boundary between the base portion and the connection portion. The shield plate is disposed over the step portion such that the connection portion of the support pierces the shield plate. An end of the metal ring protrudes from an end of the connection portion over the shield plate. The semiconductor device is adapted such that the control circuit board is mounted over the protruded end of the metal ring and is fixed onto the connection portion by an engagement member.

Подробнее
Номер записи: 26
29-03-2012 дата публикации

Methods of fabricating package stack structure and method of mounting package stack structure on system board

Номер: US20120074586A1
Автор: Eun-Jin Choi, Sun-Kyoung SEO
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Подробнее
Номер записи: 27
29-03-2012 дата публикации

Source Driver, An Image Display Assembly And An Image Display Apparatus

Номер: US20120075268A1
Автор: Hee-Seok Lee, Keung-Beum Kim, Ye-Chung Chung, Yun-seok Choi
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An image display panel assembly includes a flexible printed circuit (FPC), an image display panel, a gate driver integrated circuit (IC) package, and a source driver IC package. The FPC is configured to receive gate and source driving signals. The image display panel is electrically connected to the FPC, and includes a gate driving signal transfer pattern along a first edge of the image display panel, a source driving signal transfer pattern along a second edge adjacent to the first end, and a plurality of pixels. The gate driver integrated circuit (IC) package is configured to receive the gate driving signal through the gate driving signal transfer pattern and provide the gate driving signal to the plurality of pixels. The source driver IC package is configured to receive the source driving signal through the source driving signal transfer pattern and provide the source driving signal to the plurality of pixels.

Подробнее
Номер записи: 28
12-04-2012 дата публикации

Integrated Circuits with Magnetic Core Inductors and Methods of Fabrications Thereof

Номер: US20120086102A1
Автор: Alexander Glas, Carsten Ahrens, Renate Hofmann, Wolfgang Klein
Принадлежит: INFINEON TECHNOLOGIES AG

In one embodiment, a method of forming a semiconductor device includes forming a first inductor coil within and/or over a substrate. The first inductor coil is formed adjacent a top side of the substrate. First trenches are formed within the substrate adjacent the first inductor coil. The first trenches are filled at least partially with a magnetic fill material. At least a first portion of the substrate underlying the first inductor coil is thinned. A backside magnetic layer is formed under the first portion of the substrate. The backside magnetic layer and the magnetic fill material form at least a part of a magnetic core region of the first inductor coil.

Подробнее
Номер записи: 29
12-04-2012 дата публикации

Integrated circuit packaging system with interposer interconnections and method of manufacture thereof

Номер: US20120086115A1
Автор: A Leam Choi, HanGil Shin, In Sang Yoon, Kenny Lee
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.

Подробнее
Номер записи: 30
12-04-2012 дата публикации

Package with embedded chip and method of fabricating the same

Номер: US20120086117A1
Автор: Chiang-Cheng Chang, Hsin-Yi Liao, Shih-Kuang Chiu
Принадлежит: Siliconware Precision Industries Co Ltd

A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.

Подробнее
Номер записи: 31
19-04-2012 дата публикации

Pass-through 3d interconnect for microelectronic dies and associated systems and methods

Номер: US20120094443A1
Автор: David S. Pratt, Dewali Ray, Kyle K. Kirby
Принадлежит: Micron Technology Inc

Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.

Подробнее
Номер записи: 32
19-04-2012 дата публикации

Semiconductor package

Номер: US20120096322A1
Автор: Kwi-Dong Kim, Tae-Hyoung HUH
Принадлежит: Hynix Semiconductor Inc

A semiconductor package includes a memory controller chip, a plurality of first memory chips configured to store normal data, a second memory chip configured to store error information for correcting or detecting error of the normal data, and an interface unit configured to interface the memory controller chip, the plurality of first memory chips, and the second memory chip.

Подробнее
Номер записи: 33
03-05-2012 дата публикации

Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product

Номер: US20120104588A1
Автор: Hong-Chin Lin, Nan-Jang Chen
Принадлежит: MediaTek Inc

A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads.

Подробнее
Номер записи: 34
03-05-2012 дата публикации

Thermal Power Plane for Integrated Circuits

Номер: US20120105145A1
Автор: Andreas Huber, Bruno Michel, Harry Barowski, Hubert Harrer, Jochen Supper, Stephan Paredes, Thomas Brunschwiler, Tim Niggemeier
Принадлежит: International Business Machines Corp

A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Подробнее
Номер записи: 35
03-05-2012 дата публикации

Method for Producing an Electrical Circuit and Electrical Circuit

Номер: US20120106112A1
Автор: Ricardo Ehrenpfordt, Sonja Knies
Принадлежит: ROBERT BOSCH GMBH

A method for producing an electrical circuit includes providing a main printed circuit board having a plurality of metalized plated-through holes through the main printed circuit board along at least one separating line between adjacent printed circuit board regions of the main printed circuit board. Each printed circuit board region has electrical contact connection pads on at least the main surface of the printed circuit board region that is to be populated, electrical lines for connection between the plurality of plated-through holes and the contact connection pads, and at least one semiconductor chip electrically contact-connected by means of the contact connection pads. The main printed circuit board is covered with a potting compound across the printed circuit board regions with the semiconductor chips.

Подробнее
Номер записи: 36
03-05-2012 дата публикации

Method for Producing Lamps

Номер: US20120107973A1
Автор: Klaus Müller, Stefan Grötsch
Принадлежит: OSRAM Opto Semiconductors GmbH

A method for producing luminous means proposes providing a carrier serving as a heat sink, said carrier comprising a planar chip mounting region. The planar chip mounting region is structured for the purpose of producing a first partial region and at least one second partial region. In this case, the first partial region has a solder-repellent property after structuring. Afterward, a solder is applied to the planar chip mounting region, such that said solder wets the at least one second partial region. At least one optoelectronic body is fixed into the at least one second partial region with the solder at the carrier. Finally, contact-connections are formed for the purpose of feeding electrical energy to the optoelectronic luminous body.

Подробнее
Номер записи: 37
10-05-2012 дата публикации

Semiconductor light emitting device

Номер: US20120112227A1
Автор: Tomoichiro Toyama
Принадлежит: ROHM CO LTD

A semiconductor light emitting device includes an LED chip, which includes an n-type semiconductor layer, active layer, and p-type semiconductor layer stacked on a substrate. The LED chip further includes an anode electrode connected to the p-type semiconductor, and a cathode connected to the n-type semiconductor. The anode and cathode electrodes face a case with the LED chip mounted thereon. The case includes a base member including front and rear surfaces, and wirings including a front surface layer having anode and cathode pads formed at the front surface, a rear surface layer having anode and cathode mounting electrodes formed at the rear surface, an anode through wiring connecting the anode pad and the anode mounting electrode and passing through a portion of the base member, and a cathode through wirings connecting the cathode pad and the cathode mounting electrode and passing through a portion of the base member.

Подробнее
Номер записи: 38
10-05-2012 дата публикации

Led package structure

Номер: US20120112237A1
Автор: Chechang Hu, Weiwei Zheng
Принадлежит: Shenzhen China Star Optoelectronics Technology Co Ltd

The present invention provides an LED package structure which has a housing, a first electrode plate, a second electrode plate, a LED chip and a Zener diode. The LED chip is mounted in the recess, and a first electrode and a second electrode of the LED chip are electrically connected to the first electrode plate and the second electrode plate, respectively. The Zener diode is embedded in the housing, and a second electrode and a first electrode of the Zener diode is electrically connected to the first electrode plate and the second electrode plate, respectively. The Zener diode of the present invention is embedded in the housing, so that it can prevent from affecting the luminous flux of the LED chip.

Подробнее
Номер записи: 39
17-05-2012 дата публикации

Integrated circuit packaging system with connection structure and method of manufacture thereof

Номер: US20120119360A1
Автор: DeokKyung Yang, In Sang Yoon, Jaehyun Lee, Ki Youn Jang, KyungHoon Lee, Seong Won Park, Sungeun Park, YoungChul KIM
Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

Подробнее
Номер записи: 40
17-05-2012 дата публикации

Electric part package and manufacturing method thereof

Номер: US20120119379A1
Автор: Kenta Uchiyama, Masahiro Kyozuka, Naoyuki Koizumi
Принадлежит: Shinko Electric Industries Co Ltd

A disclosed electric part package includes a supporting member that includes a first area in which an electric part is arranged, and a second area in which a first opening is positioned, the second area being isolated from the first area; a resin part provided on the supporting member thereby to cover the electric part arranged in the first area, the resin part including an electric terminal exposed in the first opening of the supporting member; and a wiring structure provided on the resin part, the wiring structure being electrically connected to the electric part and the electric terminal of the resin part.

Подробнее
Номер записи: 41
17-05-2012 дата публикации

3d optoelectronic packaging

Номер: US20120120978A1
Автор: Frank R. Libsch, Paul Fortier, Russell A. Budd
Принадлежит: International Business Machines Corp

An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with a wiring layer. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. One or more first OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the first OE elements positioned in optical alignment with the optical via for receiving the light. A second OE element embedded within the wiring layer. A carrier may be interposed between electrical interconnect elements and positioned between the wiring layer and a circuit board.

Подробнее
Номер записи: 42
24-05-2012 дата публикации

Light emitting devices and methods

Номер: US20120127720A1
Автор: Christopher P. Hussell, David T. Emerson, Jeffrey C. Britt
Принадлежит: Individual

Light emitting devices and methods such as light emitting diodes (LEDs) are disclosed for use in higher voltage applications. Variable arrangements of LEDs are disclosed herein. Arrangements can include one or more LED chips connected in series, parallel, and/or a combination thereof. LED chips can be disposed in a package body having at least one thermal element and one or more electrical components.

Подробнее
Номер записи: 43
07-06-2012 дата публикации

Semiconductor Device

Номер: US20120139130A1
Автор: Masaki Shiraishi, Nobuyoshi Matsuura, Tomoaki Uno, Yukihiro Satou
Принадлежит: Renesas Electronics Corp

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Подробнее
Номер записи: 44
21-06-2012 дата публикации

Packaged semiconductor chips with array

Номер: US20120153443A1
Автор: Andrey Grinman, Charles Rosenstein, David Ovrutsky, Vage Oganesian
Принадлежит: Tessera LLC

A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

Подробнее
Номер записи: 45
28-06-2012 дата публикации

Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer

Номер: US20120161279A1
Автор: Kai Liu, KANG Chen, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.

Подробнее
Номер записи: 46
12-07-2012 дата публикации

Method And System For A Photonic Interposer

Номер: US20120177381A1
Автор: Greg Young, Mark Peterson, Peter De Dobbelaere
Принадлежит: Luxtera LLC

Methods and systems for a photonic interposer are disclosed and may include receiving one or more continuous wave (CW) optical signals in a silicon photonic interposer from an external optical source, either from an optical source assembly or from optical fibers coupled to the silicon photonic interposer. The received CW optical signals may be processed based on electrical signals received from the electronics die. The modulated optical signals may be received in the silicon photonic interposer from optical fibers coupled to the silicon photonic interposer. Electrical signals may be generated in the silicon photonic interposer based on the received modulated optical signals, and may then be communicated to the electronics die via copper pillars. Optical signals may be communicated into and/or out of the silicon photonic interposer utilizing grating couplers. The electronics die may comprise one or more of: a processor core, a switch core, or router.

Подробнее
Номер записи: 47
19-07-2012 дата публикации

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

Номер: US20120181689A1
Автор: Byung Tai Do, Linda Pei Ee CHUA, Reza A. Pagaila
Принадлежит: Stats Chippac Pte Ltd

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

Подробнее
Номер записи: 48
19-07-2012 дата публикации

Dram device with built-in self-test circuitry

Номер: US20120182776A1
Автор: Ming Li, Scott C. Best
Принадлежит: RAMBUS INC

A dynamic random access memory (DRAM) device includes a first and second integrated circuit (IC) die. The first integrated circuit die has test circuitry to generate redundancy information. The second integrated circuit die is coupled to the first integrated circuit die in a packaged configuration including primary storage cells and redundant storage cells. The second integrated circuit die further includes redundancy circuitry responsive to the redundancy information to substitute one or more of the primary storage cells with one or more redundant storage cells.

Подробнее
Номер записи: 49
19-07-2012 дата публикации

Semiconductor device including plural chips stacked to each other

Номер: US20120182778A1
Автор: Homare Sato
Принадлежит: Elpida Memory Inc

Such a device is disclosed that includes a first semiconductor chip including a plurality of first terminals, a plurality of second terminals, and a first circuit coupled between the first and second terminals and configured to control combinations of the first terminals to be electrically connected to the second terminals, and a second semiconductor chip including a plurality of third terminals coupled respectively to the second terminals, an internal circuit, and a second circuit coupled between the third terminals and the internal circuit and configured to activate the internal circuit when a combination of signals appearing at the third terminals indicates a chip selection.

Подробнее
Номер записи: 50
26-07-2012 дата публикации

Semiconductor Device and Method of Forming Shielding Layer Around Back Surface and Sides of Semiconductor Wafer Containing IPD Structure

Номер: US20120187531A1
Автор: ByungHoon Ahn, Gwang Kim, HyunTai Kim, YongTaek Lee
Принадлежит: Stats Chippac Pte Ltd

A semiconductor wafer has an insulating layer over a first surface of the substrate. An IPD structure is formed over the insulating layer. The IPD structure includes a MIM capacitor and inductor. A conductive via is formed through a portion of the IPD structure and partially through the substrate. The conductive via can be formed in first and second portions. The first portion is formed partially through the substrate and second portion is formed through a portion of the IPD structure. A first via is formed through a second surface of the substrate to the conductive via. A shielding layer is formed over the second surface of the substrate wafer. The shielding layer extends into the first via to the conductive via. The shielding layer is electrically connected through the conductive via to an external ground point. The semiconductor wafer is singulated through the conductive via.

Подробнее
Номер записи: 51
26-07-2012 дата публикации

Semiconductor package and method for manufacturing semiconductor package

Номер: US20120187557A1
Автор: Akihiko Tateiwa, Masahiro Kyozuka, Masato Tanaka
Принадлежит: Shinko Electric Industries Co Ltd

A semiconductor package includes a semiconductor chip including a circuit forming surface and a side surface, and a sealing insulation layer that seals the circuit forming surface and the side surface of the semiconductor chip, the sealing insulation layer having a first surface on a side of the circuit forming surface. At least one wiring layer and at least one insulation layer are formed one on top of the other on the first surface. The wiring layer formed on the first surface is electrically connected to the semiconductor chip. The insulation layer has a reinforcement member installed therein.

Подробнее
Номер записи: 52
26-07-2012 дата публикации

Semiconductor chip module, semiconductor package having the same and package module

Номер: US20120187560A1
Автор: Hyeon Ji BAEK, Hyung Ju CHOI, Jong Hyun Kim, Mun Aun HYUN
Принадлежит: Hynix Semiconductor Inc

A semiconductor module comprising a plurality of semiconductor chips where at least one semiconductor chip is laterally offset with respect to a second semiconductor chip, and substantially aligned with a third semiconductor chip such that an electrical connection can be made between an electrical contact in the first semiconductor chip and an electrical contact in the third semiconductor chip.

Подробнее
Номер записи: 53
26-07-2012 дата публикации

Packaged semiconductor device for high performance memory and logic

Номер: US20120187578A1
Автор: Ming Li
Принадлежит: Individual

A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.

Подробнее
Номер записи: 54
26-07-2012 дата публикации

Integrated structures of high performance active devices and passive devices

Номер: US20120192139A1
Автор: Anthony K. Stamper, Daniel S. Vanslette, Robert M. Rassel
Принадлежит: International Business Machines Corp

Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip.

Подробнее
Номер записи: 55
02-08-2012 дата публикации

Semiconductor device and method of fabricating the same

Номер: US20120193779A1
Автор: Chung-Sun Lee, Hyun-jung SONG, Jung-Hwan Kim, Sun-pil Youn, Tae-Hong Min
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.

Подробнее
Номер записи: 56
02-08-2012 дата публикации

Power module and the method of packaging the same

Номер: US20120194148A1
Автор: Bai-Yao Lou, Chien-Hung Liu, Ho-Yin Yiu, Wei-Chung Yang
Принадлежит: XinTec Inc

A power module includes a substrate; a conductive path layer formed on the substrate with a specific pattern as an inductor; a connection layer being formed on the substrate and electrically connected to a first terminal of the inductor; and a first transistor, electrically mounted on the substrate through the connection layer.

Подробнее
Номер записи: 57
02-08-2012 дата публикации

Semiconductor Package with Embedded Die

Номер: US20120196406A1
Автор: Rajendra D. Pendse
Принадлежит: Stats Chippac Pte Ltd

A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

Подробнее
Номер записи: 58
16-08-2012 дата публикации

Heat exchanger

Номер: US20120205086A1
Автор: Masaya Nakamura, Naoki Sugimoto, Takao Ikeda
Принадлежит: Denso Corp

An inner fin is provided in a fluid pipe for dividing a fluid passage for heating medium into multiple small fluid passages, so as to facilitate heat exchange between the heating medium and an electronic part. The inner fin is formed in a wave shape in a cross section perpendicular to a flow direction of the heating medium, wherein the inner fin has projecting portions alternately projecting in one direction and in the other direction. The inner fin is composed of multiple fin portions, wherein a fin pitch of a first fin portion is made to be smaller than a fin pitch of a second fin portion, which faces to the electronic part.

Подробнее
Номер записи: 59
30-08-2012 дата публикации

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

Номер: US20120217629A1
Автор: Daesik Choi, Joonyoung Choi, SungWon Cho
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Подробнее
Номер записи: 60
30-08-2012 дата публикации

Semiconductor device and noise suppressing method

Номер: US20120217653A1
Автор: Hisashi Ishida, Koichi Takemura
Принадлежит: NEC Corp

A first semiconductor chip ( 200 ) is mounted on a second semiconductor chip ( 100 ). The first semiconductor chip ( 200 ) has a first conductor pattern ( 222 ). The second semiconductor chip ( 100 ) has a second conductor pattern ( 122 ). The second conductor pattern ( 122 ) is formed at a region overlapping the first conductor pattern ( 222 ) in a plan view. At least one element selected from a group consisting of the first conductor pattern ( 222 ) and the second conductor pattern ( 122 ) has a repetitive structure.

Подробнее
Номер записи: 61
30-08-2012 дата публикации

Multi-chip module package

Номер: US20120217657A1
Автор: Chih-Feng Huang, Chiu-Chih Chiang, Lih-Ming Doong, You-Kuo Wu
Принадлежит: Individual

A multi-chip module package is provided, which includes a first chip mounted on via a first conductive adhesive and electrically connected to a first chip carrier, a second chip mounted on via a second conductive adhesive and electrically connected to a second chip carrier which is spaced apart from the first chip carrier, wherein the second conductive adhesive is made of an adhesive material the same as that of the first conductive material, a plurality of conductive elements to electrically connect the first chip to the second chip and an encapsulant encapsulating the first chip, the first chip carrier, the second chip, the second chip carrier and the plurality of conductive elements, allowing a portion of both chip carriers to be exposed to the encapsulant, so that the first chip and second chip are able to be insulated by the separation of the first and second chip carriers.

Подробнее
Номер записи: 62
30-08-2012 дата публикации

Integrated circuit package with molded cavity

Номер: US20120217659A1
Автор: Byung Joon Han, Il Kwon Shim, Seng Guan Chow
Принадлежит: Individual

An integrated circuit package system includes a base substrate, attaching a base die over the base substrate, attaching an integrated interposer having interposer circuit devices, over the base die, and forming a package system encapsulant having an encapsulant cavity over the integrated interposer.

Подробнее
Номер записи: 63
06-09-2012 дата публикации

Light emitting diode package

Номер: US20120223343A1
Автор: Do Hyoung KANG, Oh Sug Kim
Принадлежит: Seoul Semiconductor Co Ltd

A light emitting diode package includes a first lead frame comprising a first hole cup, a second lead frame comprising a second hole cup and disposed to face the first lead frame with a gap disposed between the first lead frame and the second lead frame, a first light emitting diode chip disposed on the first hole cup, and a second light emitting diode chip disposed on the second hole cup, the first lead frame comprising a first enlarged region formed between the gap and the first hole cup, and the second lead frame comprising a second enlarged region formed between the gap and the second hole cup.

Подробнее
Номер записи: 64
06-09-2012 дата публикации

Package 3D Interconnection and Method of Making Same

Номер: US20120225522A1
Автор: Rezaur Rahman Khan, Sam Ziqun Zhao
Принадлежит: Broadcom Corp

A method of manufacturing an integrated circuit (IC) package is provided. The method includes stacking an interposer substrate and a device structure, the interposer substrate having a first plurality of contact members formed on a first surface of the interposer substrate and the device structure having a second plurality of contact members that are exposed at a surface of the device structure, and laminating the interposer substrate and the device structure such that the first plurality of contact members are physically and electrically coupled to the second plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the second plurality of contact members.

Подробнее
Номер записи: 65
06-09-2012 дата публикации

Method for Attaching Wide Bus Memory and Serial Memory to a Processor within a Chip Scale Package Footprint

Номер: US20120225523A1
Автор: Kurt Wachtler, Margaret Rose Simmons-Matthews
Принадлежит: Texas Instruments Inc

A method for forming a semiconductor device includes physically attaching a first semiconductor die to front surface of a first substrate. The first die is electrically connected to routings on front surface of the first substrate. The routings are electrically connected with conductive pads on back surface of the first substrate. A second semiconductor die is physically attached to front surface of a second substrate. The die is electrically connected to routings on front surface of second substrate. These routings are electrically connected with conductive pads on front surface of the second substrate. A third semiconductor die is physically attached to the second die. The third die is electrically attached to the second die through a plurality of through substrate vias (TSVs) within the second die. The conductive pads on back surface of first substrate are electrically connected to the conductive pads on front surface of second substrate.

Подробнее
Номер записи: 66
13-09-2012 дата публикации

Chip-last embedded interconnect structures and methods of making the same

Номер: US20120228754A1
Автор: Fuhan Liu, Nitesh Kumbhat, Rao Tummala, Venkatesh Sundaram
Принадлежит: Georgia Tech Research Corp

The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.

Подробнее
Номер записи: 67
20-09-2012 дата публикации

Semiconductor light emitting diode chip, method of manufacturing thereof and method for quality control thereof

Номер: US20120235142A1
Автор: Seong Deok HWANG, Seong Jae Hong, Young Hee Song
Принадлежит: SAMSUNG ELECTRONICS CO LTD

There are provided a semiconductor light emitting diode chip, a method of manufacturing thereof, and a method for quality control using the same. The semiconductor light emitting diode chip includes a substrate; a light emitting diode in one area of the substrate and at least one fuse signature circuit formed in the other area of substrate so as to be electrically insulated from the light emitting diode. The fuse signature circuit includes a circuit unit having unique electrical characteristic value corresponding to wafer based process information and a plurality of electrode pads connected to the circuit unit. The semiconductor light emitting diode chip may include chip information marking representing information.

Подробнее
Номер записи: 68
20-09-2012 дата публикации

Electronic device and method for producing a device

Номер: US20120235298A1
Автор: Harry Hedler, Markus Brunnbauer, Thorsten Meyer
Принадлежит: INFINEON TECHNOLOGIES AG

An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body.

Подробнее
Номер записи: 69
27-09-2012 дата публикации

Semiconductor memory card

Номер: US20120241933A1
Автор: Katsuyoshi Watanabe, Kazuhide Doi, Naohisa Okumura, Takeshi Ikuta, Taku Nishiyama
Принадлежит: Toshiba Corp

In an embodiment, a semiconductor memory card includes a lead frame including external connection terminals, a lead portion, a chip component mounting portion and a semiconductor chip mounting portion, a chip component mounted on the chip component mounting portion, a memory chip disposed on the semiconductor chip mounting portion, and a controller chip. A rewiring layer is formed on a surface of the memory chip. The lead frame is resin-sealed. An electric circuit of the controller chip and the memory chip on the lead frame is formed by the lead portion, the rewiring layer and a metal wire connected to electrode pad of the chips, the lead portion, and the rewiring layer.

Подробнее
Номер записи: 70
27-09-2012 дата публикации

Integrated circuit packaging system with collapsed multi-integration package and method of manufacture thereof

Номер: US20120241980A1
Автор: Hye Ran Lee, JaEun Yun, Jong Wook Ju, Sungmin Song, WonJun Ko
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a central integrated circuit over the base substrate; mounting a side package having a side package substrate along a peripheral region of the base substrate and laterally peripheral to the central integrated circuit with the side package substrate coplanar with the central integrated circuit; and encapsulating the central integrated circuit and the side package above the base substrate with a base encapsulation to form a planar surface over the central integrated circuit and the side package facing away from the base substrate.

Подробнее
Номер записи: 71
27-09-2012 дата публикации

Methods of fabricating light emitting diode devices

Номер: US20120244652A1
Автор: Ching-Wen Hsiao, Chyi Shyuan Chern, Fu-Wen LIU, Hsin-Hsien Wu, Kuang-Huan Hsu, Yung-Chang Chen
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An embodiment of the disclosure includes a method of fabricating a plurality of light emitting diode devices. A plurality of LED dies is provided. The LED dies are bonded to a carrier substrate. A patterned mask layer comprising a plurality of openings is formed on the carrier substrate. Each one of the plurality of LED dies is exposed through one of the plurality of the openings respectively. Each of the plurality of openings is filled with a phosphor. The phosphor is cured. The phosphor and the patterned mask layer are polished to thin the phosphor covering each of the plurality of LED dies. The patterned mask layer is removed after polishing the phosphor.

Подробнее
Номер записи: 72
04-10-2012 дата публикации

Integrated circuit package including miniature antenna

Номер: US20120249380A1
Автор: Carles Puente Baliarda, Carmen Borja Borau, Jaume Anguera Pros, Jordi Soler Castany
Принадлежит: Fractus SA

The present invention relates to an integrated circuit package comprising at least one substrate, each substrate including at least one layer, at least one semiconductor die, at least one terminal, and an antenna located in the integrated circuit package, but not on said at least one semiconductor die. The conducting pattern comprises a curve having at least five sections or segments, at least three of the sections or segments being shorter than one-tenth of the longest free-space operating wavelength of the antenna.

Подробнее
Номер записи: 73
04-10-2012 дата публикации

Energy Efficient Power Distribution for 3D INTEGRATED CIRCUIT Stack

Номер: US20120250443A1
Автор: Andre Schaefer, Ruchir Saraswat, SUPRIYANTO SUPRIYANTO
Принадлежит: Individual

Multiple dies can be stacked in what are commonly referred to as three-dimensional modules (or “stacks”) with interconnections between the dies, resulting in an IC module with increased circuit component capacity. Such structures can result in lower parasitics for charge transport to different components throughout the various different layers. In some embodiments, the present invention provides efficient power distribution approaches for supplying power to components in the different layers. For example, voltage levels for global supply rails may be increased to reduce required current densities for a given power objective.

Подробнее
Номер записи: 74
11-10-2012 дата публикации

Stacked Composite Device Including a Group III-V Transistor and a Group IV Diode

Номер: US20120256190A1
Автор: Michael A. Briere, Tim Mcdonald
Принадлежит: International Rectifier Corp USA

In one implementation, a stacked composite device comprises a group IV diode and a group III-V transistor stacked over the group IV diode. A cathode of the group IV diode is in contact with a source of the group III-V transistor, an anode of the group IV diode is coupled to a gate of the group III-V transistor to provide a composite anode on a bottom side of the stacked composite device, and a drain of the group III-V transistor provides a composite cathode on a top side of the stacked composite device.

Подробнее
Номер записи: 75
11-10-2012 дата публикации

Semiconductor device

Номер: US20120256322A1
Автор: Fumito Itou, Hiroshige Hirano, Yukitoshi Ota
Принадлежит: Panasonic Corp

A semiconductor device includes a first semiconductor chip provided with a first semiconductor element including a plurality of element electrodes; and a first substrate having an element mounting surface on which the first semiconductor chip is mounted. The first substrate includes a plurality of first electrodes, each formed on the element mounting surface; a plurality of first interconnects connected to the first electrodes; a plurality of second electrodes formed on a surface opposite to the element mounting surface; a plurality of second interconnects connected to the second electrodes; a plurality of through-hole interconnects penetrating the first substrate and connecting the first interconnects to the second interconnects; and a third semiconductor element. The first side of the first substrate is shorter than the first side of the first semiconductor chip.

Подробнее
Номер записи: 76
18-10-2012 дата публикации

Uv irradiation apparatus

Номер: US20120261595A1
Автор: Hideo Kado, Tsuyoshi INUI
Принадлежит: Panasonic Electric Works SUNX Co Ltd

In a memory unit 6, there is stored a correction table for each candidate value of an output set value of each of LED units 2. If UV rays have ever been emitted so far by the LED units 2, each of which is formed of a plurality of LED chips 8, then a PLC 5 acquires, upon setting of a output set value by an operation unit 53, a correction value corresponding to a cumulative emission time up to a previous emission, from the correction table of the output set value. Thereafter, the PLC 5 sets the magnitude of the power supplied to each of the LED units 2 using the acquired correction value. If an output set value different from a previous output set value is set, the PLC 5 obtains the correction value starting from the cumulative emission time upon modification. As a result, the UV irradiation apparatus enables power consumption necessary for emission of UV rays to be reduced, and UV ray output to be kept constant regardless of the cumulative emission time, even if the output set value is modified.

Подробнее
Номер записи: 77
18-10-2012 дата публикации

Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof

Номер: US20120261808A1
Автор: Dioscoro A. Merilo, Henry Descalzo Bathan, Lionel Chien Hui Tay, Zigmund Ramirez Camacho
Принадлежит: Individual

A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

Подробнее
Номер записи: 78
18-10-2012 дата публикации

Through-silicon vias for semicondcutor substrate and method of manufacture

Номер: US20120261827A1
Автор: Chen-Hua Yu, Cheng-Hung Chang, Chia-Lin Yu, Chun Hua CHANG, Darryl KUO, Ebin Liao, Hsiang-Yi Wang, Li-Hsien HUANG, Tsang-Jiuh Wu, Wen-Chih Chiou
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor component includes a semiconductor substrate having a top surface. An opening extends from the top surface into the semiconductor substrate. The opening includes an interior surface. A first dielectric liner having a first compressive stress is disposed on the interior surface of the opening. A second dielectric liner having a tensile stress is disposed on the first dielectric liner. A third dielectric liner having a second compressive stress disposed on the second dielectric liner. A metal barrier layer is disposed on the third dielectric liner. A conductive material is disposed on the metal barrier layer and fills the opening.

Подробнее
Номер записи: 79
18-10-2012 дата публикации

Method and system for template assisted wafer bonding

Номер: US20120264256A1
Автор: John Dallesasse, Stephen B. Krasulick
Принадлежит: Skorpios Technologies Inc

A method of fabricating a composite semiconductor structure includes providing a substrate including a plurality of devices and providing a compound semiconductor substrate including a plurality of photonic devices. The method also includes dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method further includes providing an assembly substrate, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, aligning the substrate and the assembly substrate, joining the substrate and the assembly substrate to form a composite substrate structure, and removing at least a portion of the assembly substrate from the composite substrate structure.

Подробнее
Номер записи: 80
25-10-2012 дата публикации

Enhanced Modularity in Heterogeneous 3D Stacks

Номер: US20120272040A1
Автор: Eren Kursun, Jude A. Rivers, Philip G. Emma
Принадлежит: International Business Machines Corp

A computer program product for generating and implementing a three-dimensional (3D) computer processing chip stack plan. The computer readable program code includes computer readable program code configured for receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to at least one layer in the 3D computer processing chip stack plan. The computer readable program code is also configured for identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The computer readable program code is further configured for determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment forms the 3D computer processing chip stack.

Подробнее
Номер записи: 81
01-11-2012 дата публикации

Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP

Номер: US20120273959A1
Автор: Dongsam Park, Yongduk Lee
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.

Подробнее
Номер записи: 82
01-11-2012 дата публикации

Semiconductor device

Номер: US20120273970A1
Автор: Hiroshi Kuroda
Принадлежит: Renesas Electronics Corp

Miniaturization and acceleration of the operating speed of a System In Package (SIP) type semiconductor device in which a memory chip and a microcomputer chip are mounted over a wiring board are promoted. When mounting a microcomputer chip and a memory chip over an upper surface of a wiring board, the memory chip is disposed such that second conductive pads of the wiring board arranged along a first chip side (a side along which data system electrode pads are arranged) of the memory chip are positioned, in the plan view, in a region between an extended line of a third chip side of the microcomputer chip and an extended line of a fourth chip side of the microcomputer chip. Thus, a length of a data system wiring for coupling a data system electrode pad of the microcomputer chip with the data system electrode pad of the memory chip is minimized.

Подробнее
Номер записи: 83
01-11-2012 дата публикации

Light emitting device and display device including the same

Номер: US20120275181A1
Автор: Bong Kul MIN
Принадлежит: LG Innotek Co Ltd

A light emitting device package is disclosed. The light emitting device package includes a body, first and second reflection cups spaced apart from each other in a top surface of the body, a first connection pad disposed in the top surface of the body, spaced apart from the first and second reflection cups, a first light emitting diode mounted in the first reflection cup, a second light emitting diode mounted in the second reflection cup, and a partition wall disposed between the first reflection cup and the second reflection cup, the partition wall extended from the top surface of the body upwardly.

Подробнее
Номер записи: 84
08-11-2012 дата публикации

Method of manufacturing chip-stacked semiconductor package

Номер: US20120282735A1
Автор: Chang-seong Jeon, Dong-Hyeon Jang, Ho-geon Song, Jung-seok Ahn, Sang-sick Park, Sung-Jun IM, Teak-Hoon LEE
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Подробнее
Номер записи: 85
29-11-2012 дата публикации

Power Semiconductor Module with Embedded Chip Package

Номер: US20120299150A1
Автор: Benjamin Tang, Frank Daeche, Kenneth Ostrom, Laura Carpenter
Принадлежит: INFINEON TECHNOLOGIES AG, Primarion Inc

A power semiconductor module includes a power semiconductor die, a metal substrate, a patterned metallization layer, a plurality of padless electrical connections, a plurality of vias and an inductor. The power semiconductor die has a top surface, an opposing bottom surface and a plurality of sides extending between the top and bottom surfaces. The metal substrate is attached to the bottom surface of the die. The patterned metallization layer is disposed above the top surface of the die. The plurality of padless electrical connections are at the top surface of the die and connect the patterned metallization layer to the die. The plurality of vias are disposed adjacent one or more of the sides of the die and electrically connected to the patterned metallization layer at a first end of the plurality of vias and to the metal substrate at a second end of the plurality of vias.

Подробнее
Номер записи: 86
29-11-2012 дата публикации

Stacked wafer level package having a reduced size

Номер: US20120299169A1
Автор: Jong Hoon Kim, Min Suk Suh, Seung Hyun Lee, Seung Taek Yang, Tae Min Kang
Принадлежит: SK hynix Inc

A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

Подробнее
Номер записи: 87
29-11-2012 дата публикации

Electronic control device

Номер: US20120300405A1
Автор: Heinrich Barth, Ralph Schertlen, Volker Weeber
Принадлежит: ROBERT BOSCH GMBH

The invention relates to an electronic control device ( 10 ) having electronic components ( 160, 162 ) on a circuit board ( 110 ) which are shielded from electrical and/or magnetic interference fields. According to the invention, an electrically conductive sheet metal part ( 170 ) is arranged on the circuit board ( 110 ) which forms a Faraday cage for the electronic components ( 160, 162 ) with the circuit board. The electrically conductive sheet metal part ( 170 ) is furthermore in thermal contact to the electronic components ( 160, 162 ) and in thermal contact to the housing ( 100 ) of the control device ( 10 ) and thereby deflects heat from the electronic components ( 160, 162 ) into the housing ( 100 ).

Подробнее
Номер записи: 88
29-11-2012 дата публикации

Distributed semiconductor device methods, apparatus, and systems

Номер: US20120302006A1
Автор: Hussein I. Hanafi, Paul A. Farrar
Принадлежит: Individual

Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.

Подробнее
Номер записи: 89
06-12-2012 дата публикации

Exposed interconnect for a package on package system

Номер: US20120306078A1
Автор: Byung Tai Do, Linda Pei Ee CHUA, Reza Argenty Pagaila
Принадлежит: Stats Chippac Pte Ltd

An integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit above the substrate; connecting an interposer to the integrated circuit with a wire-in-film adhesive; connecting an exposed interconnect having an upper surface to the substrate; and encapsulating the integrated circuit with an encapsulation.

Подробнее
Номер записи: 90
13-12-2012 дата публикации

Semiconductor package

Номер: US20120313265A1
Автор: Norio Yamanishi
Принадлежит: Shinko Electric Industries Co Ltd

A semiconductor package includes a plurality of connection pads, which are electrically connected to connection terminals of a mounted component that is mounted on the semiconductor package, and recognition marks. The recognition marks are formed respectively within the area of each of at least two of the connection pads. Each recognition mark has an area that is smaller than the area of the connection mark in which it is formed.

Подробнее
Номер записи: 91
20-12-2012 дата публикации

Flip chip assembly process for ultra thin substrate and package on package assembly

Номер: US20120319276A1
Автор: A. Vethanayagam Rudge, Bok Sim Lim, Kang Eu Ong, Mun Leong Loke, Sih Fei Lim, Tean Wee One, Weng Khoon Mong
Принадлежит: Individual

In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed.

Подробнее
Номер записи: 92
20-12-2012 дата публикации

Module substrate, module-substrate manufacturing method, and terminal connection substrate

Номер: US20120320536A1
Автор: Issei Yamamoto
Принадлежит: Murata Manufacturing Co Ltd

In a module substrate, a plurality of terminal connection substrates each including an insulator and a plurality of columnar terminal electrodes arranged on a single lateral surface or both lateral surfaces of the insulator is mounted on a single side of a composite substrate such that at least one of the terminal connection substrates extends over a border between a plurality of neighboring module substrates. The composite substrate, in which the plurality of terminal connection substrates is mounted on the single side and a plurality of electronic components is mounted on at least the single side, is divided at a location where the module substrates are to be cut from the composite substrate.

Подробнее
Номер записи: 93
27-12-2012 дата публикации

Led module and manufacturing method thereof

Номер: US20120326195A1
Автор: Won Sang Lee, Young Keun Kim
Принадлежит: Daewon Innost Co Ltd

There is provided a manufacturing method of an LED module including: forming an insulating film on a substrate; forming a first ground pad and a second ground pad separated from each other on the insulating film; forming a first division film that fills a space between the first and second ground pads, a second division film deposited on a surface of the first ground pad, and a third division film deposited on a surface of the second ground pad; forming a first partition layer of a predetermined height on each of the division films; sputtering seed metal to the substrate on which the first partition layer is formed; forming a second partition layer of a predetermined height on the first partition layer; forming a first mirror connected with the first ground pad and a second mirror connected with the second ground pad by performing a metal plating process to the substrate on which the second partition layer is formed; removing the first and second partition layers; connecting a zener diode to the first mirror and connecting an LED to the second mirror; and depositing a fluorescent material so as to fill a space formed by the first mirror and the second mirror.

Подробнее
Номер записи: 94
27-12-2012 дата публикации

Integrated circuit packaging system with interconnects and method of manufacture thereof

Номер: US20120326281A1
Автор: Reza Argenty Pagaila
Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit to the substrate; attaching a vertical interconnect over the substrate; forming an encapsulation on the substrate and covering the vertical interconnect; and forming a rounded cavity, having a curved side, in the encapsulation with the vertical interconnect exposed in the rounded cavity.

Подробнее
Номер записи: 95
03-01-2013 дата публикации

Electronic control unit and method of manufacturing the same

Номер: US20130003306A1
Автор: Mitsuhiro Saitou, Shinsuke Oota, Yutaka Oohashi
Принадлежит: Denso Corp

An electronic control unit is disclosed. The electronic control unit includes: a resin board; a power device that is surface-mounted on the resin board; a microcomputer that is configured to control the power device; first heat radiation means for radiating heat, the first heat radiation means being disposed on an opposite side of the resin board from the power device; and first heat conduction means for conducting the heat generated by the power device to the first heat radiation means.

Подробнее
Номер записи: 96
17-01-2013 дата публикации

System and Method for Wafer Level Packaging

Номер: US20130015467A1
Автор: Alfons Dehe, Gerhard Lohninger, Ulrich Krumbein
Принадлежит: INFINEON TECHNOLOGIES AG

In an embodiment, a semiconductor device includes a semiconductor substrate. The semiconductor substrate has a first cavity disposed through it, and conductive material covers at least the bottom portion of the first cavity. An integrated circuit is disposed on the top surface of the conductive material. The device further includes a cap disposed on the top surface of the substrate, such that a cavity disposed on a surface of the cap overlies the first cavity in the substrate.

Подробнее
Номер записи: 97
17-01-2013 дата публикации

Interconnection and assembly of three-dimensional chip packages

Номер: US20130015578A1
Автор: Ashok V. Krishnamoorthy, Hiren D. Thacker, Ivan Shubin, John E. Cunningham
Принадлежит: Oracle International Corp

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.

Подробнее
Номер записи: 98
17-01-2013 дата публикации

Memory module in a package

Номер: US20130015590A1
Автор: Belgacem Haba, Ilyas Mohammed, Richard DeWitt Crisp, Wael Zohni
Принадлежит: Invensas LLC

A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals.

Подробнее
Номер записи: 99
24-01-2013 дата публикации

Power Semiconductor Module with Asymmetrical Lead Spacing

Номер: US20130021759A1
Автор: Andreas Laschek-Enders, Olaf Zschieschang
Принадлежит: IXYS Semiconductor GmbH

A power semiconductor has power terminals arranged in a row at one side of the housing, with control terminals arranged in a row at the other side of the housing. The spacing between adjacent power terminals is greater than the spacing between adjacent control terminals.

Подробнее
Номер записи: 100