Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год
Применить Всего найдено 71769. Отображено 100.
05-01-2012 дата публикации

Double molded chip scale package

Номер: US20120001322A1
Автор: Luke England, Yong Liu
Принадлежит: Fairchild Semiconductor Corp

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

Подробнее
Номер записи: 1
05-01-2012 дата публикации

Semiconductor package having a stacked structure

Номер: US20120001347A1
Автор: Chan-Min Han, Jin-yang Lee, Kil-Soo Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor package includes a substrate, a first semiconductor chip stacked on the substrate and a second semiconductor chip stacked on the first semiconductor chip. In the semiconductor package, the second semiconductor chip is rotated to be stacked on the first semiconductor chip. The semiconductor package is used in an electronic system.

Подробнее
Номер записи: 2
05-01-2012 дата публикации

Active energy ray-curable pressure-sensitive adhesive for re-release and dicing die-bonding film

Номер: US20120003470A1
Автор: Chie Kitano, Hironao OTAKE, Katsuhiko Kamiya, Masatsugu KOSO, Mika Okada, Shuhei Murata, Takeshi Matsumura, Tomokazu Takahashi
Принадлежит: Nitto Denko Corp

Provided is an active energy ray-curable pressure-sensitive adhesive for re-release, which has a small influence on an environment or a human body, can be easily handled, can largely change its pressure-sensitive adhesiveness before and after irradiation with an active energy ray, and can express high pressure-sensitive adhesiveness before the irradiation with the active energy ray and express high releasability after the irradiation with the active energy ray. The active energy ray-curable pressure-sensitive adhesive for re-release includes an active energy ray-curable polymer (P), in which the polymer (P) includes one of a polymer obtained by causing a carboxyl group-containing polymer (P3) and an oxazoline group-containing monomer (m3) to react with each other, and a polymer obtained by causing an oxazoline group-containing polymer (P4) and a carboxyl group-containing monomer (m2) to react with each other.

Подробнее
Номер записи: 3
11-07-2017 дата публикации

Выводная рамка мощной интегральной микросхемы

Номер: RU0000172495U1
Автор: Александр Владимирович Минин, Евгений Викторович Абашин, Константин Львович Афанасьев, Николай Александрович Брюхно
Принадлежит: Закрытое акционерное общество "ГРУППА КРЕМНИЙ ЭЛ"

Использование: для создания выводных рамок мощных интегральных схем. Сущность полезной модели заключается в том, что выводная рамка мощной интегральной микросхемы содержит теплорастекатель с участком присоединения кристалла с рифлением, и траверсы для присоединения гибких выводов, рифление теплорастекателя выполено виде сетки из канавок, расположенных в двух взаимоперпендикулярных направлениях с шагомпричем:где- наибольший диаметр гибкого вывода, соединяющий контактную площадку с теплорастекателем,наименьший линейный размер кристалла. Технический результат: обеспечение возможности повышения качества мощной микросхемы. 2 ил. Ц 1 172495 ко РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ 27; 22, 7 р», 77 8? аа) ил < < $ >< оо п РЦ ‘’ (50) МПК НО. 23/495 (2006.01) (12) ОПИСАНИЕ ПОЛЕЗНОЙ МОДЕЛИ К ПАТЕНТУ (21)(22) Заявка: 2017109009, 17.03.2017 (24) Дата начала отсчета срока действия патента: 17.03.2017 Дата регистрации: 11.07.2017 Приоритет(ы): (22) Дата подачи заявки: 17.03.2017 (45) Опубликовано: 11.07.2017 Бюл. № 20 Адрес для переписки: 241037, г. Брянск, ул. Красноармейская, 103, ЗАО "ГРУППА КРЕМНИЙ ЭЛ", Технический отдел (72) Автор(ы): Абашин Евгений Викторович (КО), Афанасьев Константин Львович (КО), Брюхно Николай Александрович (КО), Минин Александр Владимирович (КО) (73) Патентообладатель(и): Закрытое акционерное общество "ГРУ1ИТА КРЕМНИЙ ЭЛ" (ВО) (56) Список документов, цитированных в отчете о поиске: ВО 2040075 С1, 20.07.1995. ВЧ 2222074 СТ, 20.01.2004. ВО 2193260 СТ, 20.11.2002. 05 5299091 АТ, 29.03.1994. 05 5633528 А1, 27.05.1997 . (54) ВЫВОДНАЯ РАМКА МОЩНОЙ ИНТЕГРАЛЬНОЙ МИКРОСХЕМЫ (57) Реферат: Использование: для создания выводных рамок мощных интегральных схем. Сущность полезной модели заключается в том, что выводная рамка мощной интегральной микросхемы содержит теплорастекатель с участком присоединения кристалла с рифлением, и траверсы для присоединения гибких выводов, рифление теплорастекателя выполено виде сетки из канавок, ...

Подробнее
Номер записи: 4
12-01-2012 дата публикации

Heat dissipating material and semiconductor device using same

Номер: US20120007017A1
Автор: Chisato Hoshino, Shingo Tabei
Принадлежит: MOMENTIVE PERFORMANCE MATERIALS JAPAN LLC

Disclosed is a heat dissipating material which is interposed between a heat-generating electronic component and a heat dissipating body. This heat dissipating material contains (A) 100 parts by weight of a silicone gel cured by an addition reaction having a penetration of not less than 100 (according to ASTM D 1403), and (B) 500-2000 parts by weight of a heat conductive filler. Also disclosed is a semiconductor device comprising a heat-generating electronic component and a heat dissipating body, wherein the heat dissipating material is interposed between the heat-generating electronic component and the heat dissipating body.

Подробнее
Номер записи: 5
12-01-2012 дата публикации

Semiconductor device

Номер: US20120007224A1
Автор: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
Принадлежит: Hitachi Hokkai Semiconductor Ltd, Renesas Electronics Corp

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Подробнее
Номер записи: 6
12-01-2012 дата публикации

System-in-a-package based flash memory card

Номер: US20120007226A1
Автор: Hem Takiar, Michael W. Patterson, Robert C. Miller, Shrikar Bhagath, Warren Middlekauff
Принадлежит: SanDisk Technologies LLC

A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.

Подробнее
Номер записи: 7
12-01-2012 дата публикации

Semiconductor device and package

Номер: US20120007236A1
Автор: Jin Ho Bae
Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate.

Подробнее
Номер записи: 8
12-01-2012 дата публикации

Resin-Encapsulated Semiconductor Device

Номер: US20120007247A1
Автор: Motoharu Haga, Shoji Yasunaga, Yasumasa Kasuya
Принадлежит: ROHM CO LTD

A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more.

Подробнее
Номер записи: 9
19-01-2012 дата публикации

Methods of forming semiconductor chip underfill anchors

Номер: US20120012987A1
Автор: Neil McLellan, Roden R. Topacio
Принадлежит: Individual

Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

Подробнее
Номер записи: 10
19-01-2012 дата публикации

Stacked semiconductor package and method of fabricating the same

Номер: US20120013026A1
Автор: Won-Gil HAN
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A stacked semiconductor package and an electronic system, the stacked semiconductor package including a plurality of semiconductor chips, a set of the semiconductor chips being stacked such that an extension region of a top surface of each semiconductor chip of the set extends beyond an end of a semiconductor chip stacked thereon to form a plurality of extension regions; and a plurality of protection layers on the extension regions and on an uppermost semiconductor chip of the plurality of semiconductor chips.

Подробнее
Номер записи: 11
26-01-2012 дата публикации

Substrate for semiconductor element, method for manufacturing substrate for semiconductor element, and semiconductor device

Номер: US20120018867A1
Автор: Junko Toda, Susumu Maniwa, Takehito Tsukamoto
Принадлежит: Toppan Printing Co Ltd

Provided is a manufacturing method of a semiconductor element substrate including: a step of forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; a step of forming a second photoresist pattern on the second surface of the metallic plate; a step of forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; a step of forming a plurality of concaved parts on the second surface of the metallic plate; a step of forming a resin layer by injecting a resin to the plurality of concaved parts; and a step of etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.

Подробнее
Номер записи: 12
26-01-2012 дата публикации

Electronic module with vertical connector between conductor patterns

Номер: US20120020044A1
Автор: Antti Iihola, Petteri Palm
Принадлежит: IMBERA ELECTRONICS OY

The present invention generally relates to a new structure to be used with electronic modules such as printed circuit boards and semiconductor package substrates. Furthermore there are presented herein methods for manufacturing the same. According to an aspect of the invention, the aspect ratio of through holes is significantly improved. Aspect ratio measures a relationship of a through hole or a micro via conductor in the direction of height divided width. According to the aspect of the invention, the aspect ratio can be increased over that of the prior art solution by a factor of ten or more.

Подробнее
Номер записи: 13
02-02-2012 дата публикации

Surface mounted led structure and packaging method of integrating functional circuits on a silicon

Номер: US20120025242A1
Автор: Guowei David Xiao, Haiying Chen, YU Hou, Yugang Zhou, Zhaoming Zeng
Принадлежит: Apt Electronics Co ltd

The present invention relates to a surface mounted LED structure of integrating functional circuits on a silicon substrate, comprising the silicon substrate and an LED chip. Said silicon substrate has an upper surface of planar structure without grooves. An oxide layer covers the upper surface of the silicon substrate, and metal electrode layers are arranged in the upper surface of the oxide layer. The upper surfaces of said metal electrode layers are arranged with metal bumps, and the LED chip is flip-chip mounted to the silicon substrate. Two conductive metal pads are arranged on the lower surface of said silicon substrate, said conductive metal pads are electrically connected to the metal electrode layers on the upper surface of the silicon substrate by a metal lead arranged on the side wall of the silicon substrate. A heat conduction metal pad is arranged on the corresponding lower, surface of the silicon substrate just below the LED chip. Peripheral functional circuits required by LED are integrated on the upper surface of said silicon substrate. The structure of the present invention has advantages of good heat dissipation effect and small volume, and direct integration of functional circuits such as protection and drive circuits etc. in the silicon substrate achieves large-scale production package of wafer level, reducing the cost of packaging and lighting fixture.

Подробнее
Номер записи: 14
02-02-2012 дата публикации

Laminated semiconductor substrate, laminated chip package and method of manufacturing the same

Номер: US20120025354A1
Автор: Atsushi Iijima, Hiroyuki Ito, Yoshitaka Sasaki
Принадлежит: Headway Technologies Inc, SAE Magnetics HK Ltd

In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have an electromagnetic shielding layer formed using a ferromagnetic body. The electromagnetic shielding layer is formed in a shielding region except the extending zone. The extending zone is set a part which the wiring electrode crosses, in a peripheral edge part of the device region.

Подробнее
Номер записи: 15
02-02-2012 дата публикации

Semiconductor device

Номер: US20120025367A1
Автор: Akio Katsumata, Goshi Kawazu, Isao Kudo, Yoichi Hiruta, Yukari Imaizumi
Принадлежит: J Devices Corp, Toshiba Corp

A semiconductor device which includes a substrate, a semiconductor element arranged on the substrate, a heat dissipation component arranged on the semiconductor element, and a mold component covering an upper part of the substrate, the semiconductor element and the heat dissipation component, wherein an area of a surface on the semiconductor element of the heat dissipation component is larger than an area of a surface on which the heat dissipation component of the semiconductor element is arranged.

Подробнее
Номер записи: 16
02-02-2012 дата публикации

Chip package and fabricating method thereof

Номер: US20120025387A1
Автор: Kuo-Ching Chang, Tzu-Han Lin, Wu-Cheng Kuo
Принадлежит: Individual

A chip package and a fabrication method thereof are provided. The chip package includes a substrate and a chip disposed over the substrate. A solder layer is disposed between the chip and the substrate. A conductive pad is disposed between the solder layer and the substrate, wherein the conductive pad includes a first portion disposed under the solder layer, a second portion disposed away from the first portion and a connective portion disposed between the first portion and the second portion. The connective portion has a width which is narrower than a width of the first portion along a first direction perpendicular to a second direction extending from the first portion to the connective portion.

Подробнее
Номер записи: 17
02-02-2012 дата публикации

Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module

Номер: US20120025393A1
Автор: Andre Roehrig, Olaf Kirsch, Peter Kanschat, Thilo Stolze
Принадлежит: INFINEON TECHNOLOGIES AG

A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

Подробнее
Номер записи: 18
02-02-2012 дата публикации

Methods of operating electronic devices, and methods of providing electronic devices

Номер: US20120028582A1
Автор: Patrick W. Tandy
Принадлежит: Round Rock Research LLC

Some embodiments include a method disposing an integrated circuit die within a housing, the integrated circuit die having integrated circuitry formed thereon, the integrated circuitry including first transponder circuitry configured to transmit and receive radio frequency signals, wherein the integrated circuit die is void of external electrical connections for anything except power supply external connections; and disposing second transponder circuitry, discrete from the first transponder circuitry, within the housing, the second transponder circuitry being configured to transmit and receive radio frequency signals, wherein the first and second transponder circuitry are configured to establish wireless communication between one another within the housing, the second transponder circuitry being disposed within 24 inches of the first transponder circuitry within the housing.

Подробнее
Номер записи: 19
09-02-2012 дата публикации

Method for fabrication of a semiconductor device and structure

Номер: US20120032294A1
Автор: Brian Cronquist, Deepak C. Sekar, Israel Beinglass, Jan Lodewijk de Jong, Zvi Or-Bach
Принадлежит: Monolithic 3D Inc

A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

Подробнее
Номер записи: 20
09-02-2012 дата публикации

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

Номер: US20120032298A1
Автор: Hideki Fujii, Kenji Furuya, Yuichi Miyagawa
Принадлежит: Renesas Electronics Corp

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Подробнее
Номер записи: 21
09-02-2012 дата публикации

Integrated circuit packaging system with die paddle and method of manufacture thereof

Номер: US20120032315A1
Автор: Arnel Senosa Trasporto, Byung Tai Do, Linda Pei Ee CHUA
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing a package paddle having a single integral structure with a paddle central portion surrounded by a paddle peripheral portion; forming a terminal adjacent the package paddle; mounting an integrated circuit over the paddle central portion; and forming an encapsulation over the integrated circuit and the terminal, the encapsulation free of delamination with the encapsulation directly on the paddle peripheral portion.

Подробнее
Номер записи: 22
09-02-2012 дата публикации

High-voltage packaged device

Номер: US20120032319A1
Автор: Richard A. Dunipace
Принадлежит: Individual

Packaged devices and methods for making and using the same are described. The packaged devices contain one or more circuit components, such as a die, that is attached to a leadframe having a first lead, a second lead, and a third lead (although, higher lead counts may be employed in some implementations). A portion of the circuit component and the leadframe are encapsulated in a molded housing so that the first lead is exposed from a first end of the housing while the second and third leads are exposed from a second end of the housing. In some configurations, the packaged device does not contain a fourth lead that is both electrically connected to the first lead and that is exposed from the second end of the molded housing. In other configurations, an area extending from the second lead to the third lead in the molded housing comprises an insulating material having a substantially uniform conductivity. Thus, the packaged devices have relatively large creepage and clearance distances between the first lead and the second and third leads. As a result, the packaged devices are able to operate at relatively high operating voltages without experiencing voltage breakdown. Other embodiments are described.

Подробнее
Номер записи: 23
09-02-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120032323A1
Автор: Akihiro Osaki, Atsushi Ishii, Masahiko Fujisawa, Masahiro Matsumoto
Принадлежит: Renesas Electronics Corp

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

Подробнее
Номер записи: 24
09-02-2012 дата публикации

Systems and Methods for Heat Dissipation Using Thermal Conduits

Номер: US20120032350A1
Автор: Jianjun Li, Nic Rossi, Robert W. Warren
Принадлежит: Conexant Systems LLC

The addition of thermal conduits by bonding bond wires to bond pads either in a wire loop configuration or a pillar configuration can improve thermal dissipation of a fabricated die. The thermal conduits can be added as part of the normal packaging process of a semiconductor die and are electrically decoupled from the circuitry fabricated on the fabricated die. In an alternative, a dummy die is affixed to the fabricated die and the thermal conduits are affixed to the dummy die. Additionally, thermal conduits can be used in conjunction with a heat spreader.

Подробнее
Номер записи: 25
09-02-2012 дата публикации

Phosphor, production method thereof and light emitting instrument

Номер: US20120032579A1
Автор: Naoto Hirosaki
Принадлежит: NATIONAL INSTITUTE FOR MATERIALS SCIENCE

A light emitting element includes a light-emitting source for emitting light at a wavelength of 330 to 500 nm and a constituent phosphor. The constituent phosphor includes a compound including M, A, Al, O, and N, where M is at least one kind of element selected from Mn, Ce, Nd, Sm, Eu, Tb, Dy, Ho, Er, Tm, and Yb, and A is at least one kind of element selected from C, Si, Ge, Sn, B, Ga, In, Mg, Ca, Sr, Ba, Sc, Y, La, Gd, Lu, Ti, Zr, Hf, Ta, and W.

Подробнее
Номер записи: 26
16-02-2012 дата публикации

Semiconductor device

Номер: US20120038033A1
Автор: Akira Oga, Masanori Minamio, YOSHIHIRO Tomita
Принадлежит: Panasonic Corp

A semiconductor device includes a first semiconductor chip 1 , a second semiconductor chip 4 , a first lead frame 3 including a first die pad 9 on which the first semiconductor chip 1 is mounted, and a second lead frame 5 including a second die pad 11 on which the second semiconductor chip 4 is mounted. A sealing structure 6 covers the first semiconductor chip 1 and the second semiconductor chip 4 . A noise shield 7 is disposed between the first semiconductor chip 1 and the second semiconductor chip 4.

Подробнее
Номер записи: 27
16-02-2012 дата публикации

Structure for Multi-Row Leadframe and Semiconductor Package Thereof and Manufacture Method Thereof

Номер: US20120038036A1
Автор: Hyuk Soo Lee, Hyun A. Chun, Jae Bong Choi, Sai Ran Eom, Sung Won Lee, Sung Wuk Ryu
Принадлежит: LG Innotek Co Ltd

The present invention relates to a multi-row leadframe for semiconductor packaging, characterized by: forming a plating pattern on a leadframe material (first step); forming a protective pattern on the plating pattern (second step); and forming a nano pattern by using the protective pattern as a mask (third step), whereby a protective pattern is formed on an upper surface of a plating pattern to increase reliability of a product by preventing damage to a plating layer caused by etching solution during pattern formation of leadframe and to thereby solve the problem of using the plating layer as an etching mask.

Подробнее
Номер записи: 28
16-02-2012 дата публикации

Stitch bump stacking design for overall package size reduction for multiple stack

Номер: US20120038059A1
Автор: Foong Yue Ho, Kevin Guan, Koo Eng LUON, Lai Nguk Chin, Sally Foong, Wong Kwet Nam
Принадлежит: Individual

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Подробнее
Номер записи: 29
23-02-2012 дата публикации

Packaging Integrated Circuits

Номер: US20120043650A1
Автор: Liang Kng Ian Koh, Richard Mangapul Sinaga
Принадлежит: INFINEON TECHNOLOGIES AG

An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Подробнее
Номер записи: 30
01-03-2012 дата публикации

Semiconductor structure having conductive vias and method for manufacturing the same

Номер: US20120049347A1
Автор: Meng-Jen Wang
Принадлежит: Advanced Semiconductor Engineering Inc

A semiconductor structure includes a plurality of thermal vias and a heat dissipation layer disposed at a periphery of a back surface of a lower chip in a stacked-chip package. This arrangement improves solderability of a subsequently-bonded heat sink. Additionally, the thermal vias and the heat dissipation layer provide an improved thermal conduction path for enhancing heat dissipation efficiency of the semiconductor structure. A method for manufacturing the semiconductor structure is also provided.

Подробнее
Номер записи: 31
01-03-2012 дата публикации

Bumpless build-up layer package with pre-stacked microelectronic devices

Номер: US20120049382A1
Автор: Pramod Malatkar
Принадлежит: Intel Corp

The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL) designs. Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package.

Подробнее
Номер записи: 32
01-03-2012 дата публикации

Process for assembling two parts of a circuit

Номер: US20120052629A1
Автор: Patrick Lamontagne, Perceval Coudrain, Yacine Felk
Принадлежит: STMICROELECTRONICS SA

A three-dimensional integrated structure is fabricated by assembling at least two parts together, wherein each part contains at least one metallic line covered with a covering region and having a free side. A cavity is formed in the covering region of each part, that cavity opening onto the metallic line. The two parts are joined together with the free sides facing each other and the cavities in each covering region aligned with each other. The metallic lines are then electrically joined to each other through an electromigration of the metal within at least one of the metallic lines, the electromigrated material filling the aligned cavities.

Подробнее
Номер записи: 33
08-03-2012 дата публикации

Semiconductor package

Номер: US20120056313A1
Автор: Jun Morimoto, Masashi AIZAWA, Masayuki Kato
Принадлежит: Individual

A semiconductor package includes a radiator plate including a stress alleviation section, a resin sheet arranged on the radiator plate, a pair of bus bars joined to the radiator plate through the resin sheet at positions at which the stress alleviation section is interposed between the bus bars, and a semiconductor device joined to the pair of bus bars by being sandwiched between the bus bars, and energized from outside through the pair of bus bars.

Подробнее
Номер записи: 34
08-03-2012 дата публикации

Multi-chip package with offset die stacking

Номер: US20120056335A1
Автор: Peter B. Gillingham
Принадлежит: Mosaid Technologies Inc

A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

Подробнее
Номер записи: 35
15-03-2012 дата публикации

Light emitting device and manufacturing method of light emitting device

Номер: US20120061703A1
Автор: Mitsuhiro Kobayashi
Принадлежит: Toshiba Corp

A light emitting device may include a base provided with a recess portion in a side surface thereof, a light emitting element mounted on a main surface of the base, a first resin body filled in an inside of the recess portion, and covering at least the main surface and the light emitting element, a second resin body covering an outside of the first resin body from the main surface side to at least a position of the lowermost end of the recess portion in a direction orthogonal to the main surface, and phosphor, provided in the second resin body, for absorbing light emitted from the light emitting element and then emitting light having a different wavelength.

Подробнее
Номер записи: 36
15-03-2012 дата публикации

Power Semiconductor Chip Package

Номер: US20120061812A1
Автор: Ralf Otremba
Принадлежит: INFINEON TECHNOLOGIES AG

A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad.

Подробнее
Номер записи: 37
15-03-2012 дата публикации

Semiconductor device and manufacturing method of the same

Номер: US20120061817A1
Автор: Mamoru SHISHIDO, Noriyuki Takahashi
Принадлежит: Renesas Electronics Corp

A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

Подробнее
Номер записи: 38
15-03-2012 дата публикации

Semiconductor chip device with polymeric filler trench

Номер: US20120061852A1
Автор: Bryan Black, Gamal Refai-Ahmed, Michael Z. Su
Принадлежит: Advanced Micro Devices Inc, ATI TECHNOLOGIES ULC

A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Подробнее
Номер записи: 39
15-03-2012 дата публикации

Electronic Packaging With A Variable Thickness Mold Cap

Номер: US20120061857A1
Автор: Christopher J. Healy, Gopal C. Jha, Vivek Ramadoss
Принадлежит: Qualcomm Inc

An electronic package with improved warpage compensation. The electronic package includes a mold cap having a variable thickness. The variable thickness can have a mound or dimple design. In another embodiment, a method is provided for reducing unit warpage of an electronic package by designing the topography of a mold cap to compensate for warpage.

Подробнее
Номер записи: 40
15-03-2012 дата публикации

Method of manufacture of integrated circuit packaging system with stacked integrated circuit

Номер: US20120064668A1
Автор: Henry Descalzo Bathan, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

Подробнее
Номер записи: 41
15-03-2012 дата публикации

Method of making a semiconductor chip assembly with a post/base heat spreader and a substrate using grinding

Номер: US20120064672A1
Автор: Charles W.C. Lin, Chia-Chung Wang
Принадлежит: Individual

A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in the substrate, then flowing the adhesive between the post and the substrate in the aperture, solidifying the adhesive, then grinding the post and the adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader.

Подробнее
Номер записи: 42
15-03-2012 дата публикации

Semiconductor device including coupling conductive pattern

Номер: US20120064827A1
Автор: Hee-Seok Lee, Jong-Joo Lee, Sang-Youb Lee, Yong-Hoon Kim, Young-don Choi
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device is disclosed including a through electrode. The semiconductor device may include a first semiconductor chip including a transceiver circuit formed on a first surface, a first coupling conductive pattern which is formed on a second surface opposite the first surface, and a through electrode which connects the transceiver circuit and the first coupling conductive pattern. There may be a transceiver located on a second semiconductor chip and including a second coupling conductive pattern facing the first coupling conductive pattern which communicates wirelessly with the first coupling conductive pattern.

Подробнее
Номер записи: 43
22-03-2012 дата публикации

Tsop with impedance control

Номер: US20120068317A1
Автор: Belgacem Haba, Brian Marcucci
Принадлежит: TESSERA RESEARCH LLC

A semiconductor device of an illustrative embodiment includes a die, a lead frame including a plurality of leads having substantial portions arranged in a lead plane and electrically connected to the die. Most preferably, the package includes at least a substantial portion of one conductive element arranged in a plane positioned adjacent the lead frame and substantially parallel to the lead plane, the conductive element being capacitively coupled to the leads such that the conductive element and at least one of the leads cooperatively define a controlled-impedance conduction path, and an encapsulant which encapsulates the leads and the conductive element. The leads and, desirably, the conductive element have respective connection regions which are not covered by the encapsulant.

Подробнее
Номер записи: 44
22-03-2012 дата публикации

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

Номер: US20120068319A1
Автор: Daesik Choi, Oh Han Kim, SangMi Park
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

Подробнее
Номер записи: 45
22-03-2012 дата публикации

Substrate bonding with metal germanium silicon material

Номер: US20120068325A1
Автор: Alex P. Pamatat, Ruben B. Montez
Принадлежит: FREESCALE SEMICONDUCTOR INC

In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

Подробнее
Номер записи: 46
22-03-2012 дата публикации

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

Номер: US20120068328A1
Автор: Hin Hwa Goh, KANG Chen, Rui Huang, Xusheng Bao, Yung Kuan Hsiao
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

Подробнее
Номер записи: 47
22-03-2012 дата публикации

Semiconductor device having semiconductor member and mounting member

Номер: US20120068362A1
Автор: Syuuichi Kariyazaki
Принадлежит: Renesas Electronics Corp

A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.

Подробнее
Номер записи: 48
29-03-2012 дата публикации

Semiconductor module including a switch and non-central diode

Номер: US20120074428A1
Автор: Gourab Majumdar, Kiyoshi Arai
Принадлежит: Mitsubishi Electric Corp

A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Подробнее
Номер записи: 49
29-03-2012 дата публикации

Semiconductor package with through electrodes and method for manufacturing the same

Номер: US20120074529A1
Автор: Jin-Ho Bae, Ki-Young Kim, Myung-Geun PARK
Принадлежит: Hynix Semiconductor Inc

A semiconductor package may include a substrate with a first surface over which bond fingers are formed. At least two semiconductor chips may be stacked on the first surface of the substrate and each chip may have via holes. The semiconductor chips may be stacked such that the respective via holes expose the respective bond fingers of the substrate. Through electrodes may be formed in the via holes. The through electrodes may comprise carbon nanotubes grown from the exposed bond fingers of the substrate, where the through electrodes may be electrically connected with the semiconductor chips.

Подробнее
Номер записи: 50
29-03-2012 дата публикации

Semiconductor device with exposed pad

Номер: US20120074549A1
Автор: Kai Yun Yow, Poh Leng EU
Принадлежит: FREESCALE SEMICONDUCTOR INC

A semiconductor device has a die attached to a die pad and electrically connected to lead fingers. The die, a top surface of the die pad, and a first portion of the lead fingers are covered with a mold compound. A second portion of the lead fingers project from the mold compound and allow for external electrical connection to the die. The mold compound around the die and lead fingers is extended such that a cavity is formed below the die pad. The die pad is exposed via the cavity. A heat sink may be inserted into the cavity and attached to the bottom surface of the die pad.

Подробнее
Номер записи: 51
29-03-2012 дата публикации

Circuit Board Packaged with Die through Surface Mount Technology

Номер: US20120074558A1
Автор: Hsuan Yu LU, Kuei-Wu Chu, Tse Ming Chu
Принадлежит: Mao Bang Electronic Co Ltd

A package of a circuit board and a die are packed through surface mount technology (SMT). The shortest circuit is formed with at a low cost. Thus, the package can work in high speed and high frequency applications.

Подробнее
Номер записи: 52
29-03-2012 дата публикации

Methods of fabricating package stack structure and method of mounting package stack structure on system board

Номер: US20120074586A1
Автор: Eun-Jin Choi, Sun-Kyoung SEO
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Подробнее
Номер записи: 53
29-03-2012 дата публикации

Integrated circuit packaging system with warpage control and method of manufacture thereof

Номер: US20120074588A1
Автор: Hin Hwa Goh, KANG Chen, Rui Huang, Xusheng Bao, Yung Kuan Hsiao
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.

Подробнее
Номер записи: 54
29-03-2012 дата публикации

Corner structure for ic die

Номер: US20120074589A1
Автор: David M. Mahoney, Mohsen H. Mardi
Принадлежит: Xilinx Inc

One or more integrated circuit chips are flip-chip bonded to a first surface of a substrate. A contact array is fabricated on a second surface of the substrate. Corner structures attached to the integrated circuit chip cover at least two corners of the IC chip.

Подробнее
Номер записи: 55
29-03-2012 дата публикации

Integrated circuit packaging system with a shield and method of manufacture thereof

Номер: US20120075821A1
Автор: Reza Argenty Pagaila
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a first integrated circuit over the substrate; forming an encapsulant around the first integrated circuit and over the substrate; and forming a shield structure within and over the encapsulant while simultaneously forming a vertical interconnect structure.

Подробнее
Номер записи: 56
05-04-2012 дата публикации

Chip Capacitor Precursors

Номер: US20120081832A1
Автор: Azuma Chikara
Принадлежит: Texas Instruments Inc

A capacitive precursor includes electrically conductive material layers stacked on a substrate. The electrically conductive layers provide first and second patterns. The patterns each include overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. Dielectric layers are interposed between neighboring electrically conductive material layers for electrical isolation. One or more capacitive precursors can be dropped onto or into a board and during assembly of a packaged semiconductor device and have electrically conducting layers associated with its respective plates connected together to form a capacitor during assembly using conventional assembly steps.

Подробнее
Номер записи: 57
05-04-2012 дата публикации

Semiconductor die package including low stress configuration

Номер: US20120083071A1
Автор: Maria Clemens Y. Quinones, Maria Cristina B. Estacio
Принадлежит: Individual

A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.

Подробнее
Номер записи: 58
12-04-2012 дата публикации

Electrode connection method, electrode connection structure, conductive adhesive used therefor, and electronic device

Номер: US20120085580A1
Автор: Kyouichirou Nakatsugi, Masamichi Yamamoto, Yasuhiro Okuda
Принадлежит: Sumitomo Electric Industries Ltd

By connecting together connecting electrodes having an organic film serving as an oxidation-preventing film using a conductive adhesive, the manufacturing process can be simplified, and a highly reliable connection structure can be constructed at low cost. An electrode connection method, in which a first connecting electrode 2 and a second connecting electrode 10 are connected together through a conductive adhesive 9 that is interposed between the electrodes, includes an organic film formation step in which an organic film 6 is formed on at least a surface of the first connecting electrode, and an electrode connection step in which the first connecting electrode and the second connecting electrode are connected together through the conductive adhesive. In the electrode connection step, by allowing an organic film decomposing component mixed in the conductive adhesive to act on the organic film, the organic film is decomposed, and thus connection between the connecting electrodes is performed.

Подробнее
Номер записи: 59
12-04-2012 дата публикации

Integrated circuit packaging system with interposer interconnections and method of manufacture thereof

Номер: US20120086115A1
Автор: A Leam Choi, HanGil Shin, In Sang Yoon, Kenny Lee
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit; mounting a routing structure having a functional side above the integrated circuit; mounting a vertical interconnect to the functional side of the routing structure and the vertical interconnect extending vertically away from the routing structure; forming an encapsulation covering the integrated circuit, the routing structure, and sides of the vertical interconnect above the routing structure, and leaves a surface of the routing structure exposed from the encapsulation, and a portion of the vertical interconnect exposed from the encapsulation above the surface of the routing structure; mounting a first-external-package-component to the routing structure; and forming a first-external-package-encapsulation covering the first-external-package-component.

Подробнее
Номер записи: 60
12-04-2012 дата публикации

Package with embedded chip and method of fabricating the same

Номер: US20120086117A1
Автор: Chiang-Cheng Chang, Hsin-Yi Liao, Shih-Kuang Chiu
Принадлежит: Siliconware Precision Industries Co Ltd

A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.

Подробнее
Номер записи: 61
12-04-2012 дата публикации

Semiconductor assembly and semiconductor package including a solder channel

Номер: US20120086123A1
Автор: Jeong-Woo Park, Moon-Gi Cho, Sun-Hee Park, Ui-Hyoung Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Подробнее
Номер записи: 62
12-04-2012 дата публикации

Package systems and manufacturing methods thereof

Номер: US20120086126A1
Автор: Chia-Pao SHU, Chun-Wen Cheng, Kuei-Sung CHANG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

Подробнее
Номер записи: 63
12-04-2012 дата публикации

Package systems and manufacturing methods thereof

Номер: US20120086127A1
Автор: Chia-Pao SHU, Chun-Wen Cheng, Hsin-Ting HUANG, Jung-Huei Peng, Kuei-Sung CHANG, Shang-Ying Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

Подробнее
Номер записи: 64
12-04-2012 дата публикации

Integrated circuit tampering protection and reverse engineering prevention coatings and methods

Номер: US20120088338A1
Автор: Alan P. Boone, Nathan P. Lower, Ross K. Wilcoxon
Принадлежит: ROCKWELL COLLINS INC

A method of protecting an electronics package is discussed along with devices formed by the method. The method involves providing at least one electronic component that requires protecting from tampering and/or reverse engineering. Further, the method includes mixing into a liquid glass material at least one of high durability micro-particles or high-durability nano-particles, to form a coating material. Further still, the method includes depositing the coating material onto the electronic component and curing the coating material deposited.

Подробнее
Номер записи: 65
19-04-2012 дата публикации

Semiconductor chip assembly with bump/base/ledge heat spreader, dual adhesives and cavity in bump

Номер: US20120091493A1
Автор: Charles W.C. Lin, Chia-Chung Wang
Принадлежит: Bridge Semiconductor Corp

A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and dual adhesives. The heat spreader includes a bump, a base and a ledge. The conductive trace includes a pad and a terminal. The semiconductor device is mounted on the bump in a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The bump extends into an opening in the first adhesive and is aligned with and spaced from an opening in the second adhesive. The base and the ledge extend laterally from the bump. The first adhesive is sandwiched between the base and the ledge, the second adhesive is sandwiched between the conductive trace and the ledge and the ledge is sandwiched between the adhesives. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.

Подробнее
Номер записи: 66
26-04-2012 дата публикации

Thermosetting resin composition for sealing packing of semiconductor, and semiconductor device

Номер: US20120101191A1
Автор: Akira Nagai, Emi Miyazawa, Kazutaka Honda, Keisuke Ookubo, Tetsuya Enomoto
Принадлежит: Hitachi Chemical Co Ltd

A thermosetting resin composition for an underfilling of a semiconductor comprising, as essential components, a thermosetting resin, a curing agent, a flux agent and two or more inorganic fillers with different mean particle sizes, wherein the inorganic fillers include an inorganic filler with a mean particle size of no greater than 100 nm and an inorganic filler with a mean particle size of greater than 100 nm.

Подробнее
Номер записи: 67
03-05-2012 дата публикации

Integrated circuit package system with encapsulation lock

Номер: US20120104579A1
Автор: Byung Tai Do, Sung Uk Yang
Принадлежит: Individual

An integrated circuit package system includes an external interconnect having a lead tip and a lead body, including a recess in the lead body including a first recess segment, having an orientation substantially parallel to the lengthwise dimension of the lead body, and a second recess segment intersecting and perpendicular to the first recess segment along a lead body top surface of the lead body, the first recess segment at a bottom portion of the second recess segment; an internal interconnect between an integrated circuit die and the external interconnect; and an encapsulation to cover the external interconnect with the recess filled.

Подробнее
Номер записи: 68
03-05-2012 дата публикации

Semiconductor package device with a heat dissipation structure and the packaging method thereof

Номер: US20120104581A1
Автор: Chia-Feng Yeh, Chung-Hwa Wu, Shao-Kang Hung
Принадлежит: Global Unichip Corp

The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

Подробнее
Номер записи: 69
03-05-2012 дата публикации

Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product

Номер: US20120104588A1
Автор: Hong-Chin Lin, Nan-Jang Chen
Принадлежит: MediaTek Inc

A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads.

Подробнее
Номер записи: 70
03-05-2012 дата публикации

Chip-on-chip structure and manufacturing method therof

Номер: US20120104597A1
Автор: Junji Yoshikawa, Tatsuji Ishiduka, Tsutomu Kojima
Принадлежит: Toshiba Corp

According to an embodiment, a chip-on-chip structure includes a first chip, a second chip, the first chip and the second chip being opposite to each other, a first electrode terminal, a second electrode terminal, a bump and a protecting material. The first electrode terminal is provided on the surface of the first chip at the side of the second chip. The second electrode terminal is provided on the surface of the second chip at the side of the first chip. The bump electrically connects the first electrode terminal and the second electrode terminal. The protecting material is formed around the bump between the first chip and the second chip. The protecting material includes a layer made of a material having heat-sensitive adhesive property.

Подробнее
Номер записи: 71
03-05-2012 дата публикации

Base plate

Номер: US20120106087A1
Автор: Lydia Feller, Samuel Hartmann
Принадлежит: ABB TECHNOLOGY AG

The present disclosure relates to a base plate, for example, for a power module, including a matrix formed of metal, for example, aluminium, wherein at least two reinforcements are provided in the matrix next to each other, and wherein the reinforcements are spaced apart from each other.

Подробнее
Номер записи: 72
03-05-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120108013A1
Автор: Atsushi Fujisawa, Hiroshi Fujii
Принадлежит: Renesas Electronics Corp

In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads. This method includes a step of removing a sealing resin filled between the circumference of a mold cavity and the dam bar by using laser and then carrying out surface treatment, for example, solder plating.

Подробнее
Номер записи: 73
10-05-2012 дата публикации

Electronic element unit and reinforcing adhesive agent

Номер: US20120111617A1
Автор: Koji Motomura, Seiichi Yoshinaga, Tadahiko Sakai
Принадлежит: Panasonic Corp

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

Подробнее
Номер записи: 74
10-05-2012 дата публикации

Semiconductor Device and Method of Forming Prefabricated EMI Shielding Frame with Cavities Containing Penetrable Material Over Semiconductor Die

Номер: US20120112327A1
Автор: Reza A. Pagaila, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.

Подробнее
Номер записи: 75
10-05-2012 дата публикации

Semiconductor device with nested rows of contacts

Номер: US20120112333A1
Автор: Qiang Liu, Qingchun He, Zhaojun Tian
Принадлежит: FREESCALE SEMICONDUCTOR INC

A molded surface mount semiconductor device has electrical contact elements disposed in a set of pairs of zigzag rows extending adjacent and generally parallel to opposite edges of an active face of a semiconductor die. Each of the pairs of rows includes an inner zigzag row of electrical contact elements nested inside an outer zigzag row of electrical contact elements. The electrical contact elements of the inner and outer zigzag rows are partially inter-digitated. A lead frame used in making the device also has a die pad located inside the set of pairs of zigzag rows, and an outer frame element located outside the set of pairs of zigzag rows, and which support the electrical contact elements of the inner and outer zigzag rows respectively.

Подробнее
Номер записи: 76
10-05-2012 дата публикации

Methods of manufacturing semiconductor chips

Номер: US20120115307A1
Автор: Ho Geon Song, Sang Wook Park, Tae Gyeong Chung, Won Chul Lim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing semiconductor chips includes providing a semiconductor substrate including circuit regions, irradiating the semiconductor substrate with a laser beam onto to form a frangible layer, and polishing the semiconductor substrate to separate the circuit regions of the semiconductor substrate from one another into semiconductor chips. The frangible layer may be removed completely during the polishing of the semiconductor substrate.

Подробнее
Номер записи: 77
17-05-2012 дата публикации

Microelectronic devices and methods for manufacturing microelectronic devices

Номер: US20120119344A1
Автор: Teck Kheng Lee
Принадлежит: Micron Technology Inc

Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in a substrate with the apertures arranged in an array, and, after forming the apertures, attaching the substrate to a lead frame having a plurality of pads with the apertures in the substrate aligned with corresponding pads in the lead frame. Another method includes providing a partially cured substrate, coupling the partially cured substrate to a plurality of leads, attaching a microelectronic die to the leads, and electrically connecting the microelectronic die to the leads.

Подробнее
Номер записи: 78
17-05-2012 дата публикации

Underfill method and chip package

Номер: US20120119353A1
Автор: Michael A. Gaynes, Rajneesh Kumar, Steve Ostrander, Thomas E. Lombardi
Принадлежит: International Business Machines Corp

A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.

Подробнее
Номер записи: 79
17-05-2012 дата публикации

Integrated circuit packaging system with connection structure and method of manufacture thereof

Номер: US20120119360A1
Автор: DeokKyung Yang, In Sang Yoon, Jaehyun Lee, Ki Youn Jang, KyungHoon Lee, Seong Won Park, Sungeun Park, YoungChul KIM
Принадлежит: Stats Chippac Pte Ltd

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

Подробнее
Номер записи: 80
17-05-2012 дата публикации

Semiconductor package and semiconductor system including the same

Номер: US20120119370A1
Автор: Jae-Wook Yoo
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided are a semiconductor package and a semiconductor system including the semiconductor package. The semiconductor package includes a semiconductor device and an interconnect structure electrically connected to the semiconductor device and delivering a signal from the semiconductor device, wherein the interconnect structure includes an anodized insulation region and an interconnect adjacent to and defined by the anodized insulation region.

Подробнее
Номер записи: 81
17-05-2012 дата публикации

Electric part package and manufacturing method thereof

Номер: US20120119379A1
Автор: Kenta Uchiyama, Masahiro Kyozuka, Naoyuki Koizumi
Принадлежит: Shinko Electric Industries Co Ltd

A disclosed electric part package includes a supporting member that includes a first area in which an electric part is arranged, and a second area in which a first opening is positioned, the second area being isolated from the first area; a resin part provided on the supporting member thereby to cover the electric part arranged in the first area, the resin part including an electric terminal exposed in the first opening of the supporting member; and a wiring structure provided on the resin part, the wiring structure being electrically connected to the electric part and the electric terminal of the resin part.

Подробнее
Номер записи: 82
24-05-2012 дата публикации

Connecting and Bonding Adjacent Layers with Nanostructures

Номер: US20120125537A1
Автор: Andrzej Brud, Mohammad Shafiqul Kabir
Принадлежит: Smoltek AB

An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.

Подробнее
Номер записи: 83
24-05-2012 дата публикации

Thermal Gradient Reflow for Forming Columnar Grain Structures for Solder Bumps

Номер: US20120125981A1
Автор: Chih-Hang Tung, Chih-Horng Chang, Tsung-Fu Tsai, Yian-Liang Kuo
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method includes heating a package structure including a first work piece and a second work piece to melt a plurality of solder bumps between the first and the second work pieces; and after the step of heating, allowing the plurality of solder bumps to solidify. During the step of solidifying, a first side of the package structure is maintained at a first temperature higher than a melting temperature of the plurality of solder bumps by using a heating source. During the step of solidifying, a second side of the package structure is maintained at a second temperature lower than the melting temperature by using a cooling source, wherein the second side is opposite the first side.

Подробнее
Номер записи: 84
24-05-2012 дата публикации

Illumination apparatus

Номер: US20120126266A1
Автор: Gen Watari, Kazuhiro Inoue
Принадлежит: Toshiba Corp

According to one embodiment, an illumination apparatus includes an LED (Light Emitting Diode) module, a light guide plate, and a support body. The support body supports the LED module and the light guide plate. A reflective surface of the support body is provided between a portion supporting the LED module and a portion supporting the light guide plate. The reflective surface is reflective with respect to the light emitted from the LED package. The LED module is tilted relative to the reflective surface with the LED package mounting surface being toward the reflective surface. An angle between the LED module and the reflective surface is less than 90°.

Подробнее
Номер записи: 85
24-05-2012 дата публикации

Light emitting device, manufacturing method thereof, and optical device

Номер: US20120126269A1
Автор: Yuki Tanuma
Принадлежит: ROHM CO LTD

The present invention provides a light emitting device which is capable of enhancing the radiant intensity on a single direction. The light emitting device comprises a substrate, a lens bonded to the substrate, and an LED chip bonded to the substrate and exposed in a gap clipped between the substrate and the lens, wherein the lens has a light output surface which bulges in a direction that is defined from the substrate toward the LED chip and is contained in a thickness direction of the substrate to transmit the light emitted from the LED chip.

Подробнее
Номер записи: 86
24-05-2012 дата публикации

Semiconductor device package with electromagnetic shielding

Номер: US20120126378A1
Автор: Allan C. Toriaga, Anang Subagio, Michael H. McKerreghan, Romarico S. San Antonio
Принадлежит: Unisem (Mauritius) Holdings Ltd

A package for a semiconductor device includes shielding from RF interference. The package has a lead frame with a lead and a connecting bar. The lead has an inner end for connecting to the device and an outer end having an exposed surface at the package side face. The connecting bar also has an end with an exposed surface at the package side face. A molding compound overlying the leadframe forms a portion of the side face. Electrically conductive shielding forms a top surface of the package, and extends downward therefrom to form an upper portion of the package side face. The exposed surface at the connecting bar end has an upper edge higher than the upper edge of the exposed surface of lead end. Accordingly, the shielding makes electrical contact with the connecting bar adjacent to its exposed surface, while being electrically isolated from the lead.

Подробнее
Номер записи: 87
24-05-2012 дата публикации

Method for semiconductor leadframes in low volume and rapid turnaround

Номер: US20120126385A1
Автор: Sreenivasan K. Koduri
Принадлежит: Texas Instruments Inc

A leadframe for a QFN/SON semiconductor device comprising a strip of a first metal as the leadframe core with a plurality of leads and a pad. a layer of a second metal over both surfaces of the strip. There are sidewalls normal to the surfaces. The first metal exposed at the sidewalls and at portions of a surface of the pad.

Подробнее
Номер записи: 88
24-05-2012 дата публикации

Resin composition, multilayer body containing the same, semiconductor device, and film

Номер: US20120126393A1
Автор: Kenji Iida
Принадлежит: Mitsui Chemicals Inc

Disclosed is a resin composition which has high heat dissipation properties and high electrical insulation properties at the same time, while having low-temperature bondability to a conductor circuit or the like. The resin composition contains (A) a thermoplastic polyimide resin having a glass transition temperature of 160 DEG C or less and (B) an inorganic filler. The aspect ratio, that is the value of length/thickness, of the inorganic filler (B) is 9 or more, and the content of the inorganic filler (B) is 40-70 weight % relative to the total weight of the resin composition. The resin composition has a melt viscoelasticity of 10-300 MPa (inclusive) at 170 DEG C.

Подробнее
Номер записи: 89
24-05-2012 дата публикации

Semiconductor device and method of forming the same

Номер: US20120126402A1
Автор: Keiyo Kusanagi, Koichi Hatakeyama, Mitsuhisa Watanabe
Принадлежит: Elpida Memory Inc

A semiconductor device includes a wiring board; a stack of semiconductor chips disposed over the wiring board, each of the semiconductor chip comprising via electrodes, the semiconductor chips being electrically coupled through the via electrodes to each other, the semiconductor chips being electrically coupled through the via electrodes to the wiring board; a first seal that seals the stack of semiconductor chips; and a second seal that covers the first seal. The first seal is smaller in elastic modulus than the second seal.

Подробнее
Номер записи: 90
24-05-2012 дата публикации

System comprising a semiconductor device and structure

Номер: US20120129301A1
Автор: Brian Cronquist, Deepak C. Sekar, Israel Beinglass, Paul Lim, Ze&#39;ev Wurman, Zvi Or-Bach
Принадлежит: Monolithic 3D Inc

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

Подробнее
Номер записи: 91
31-05-2012 дата публикации

Cerium and Europium Doped Phosphor Compositions and Light Emitting Devices Including the Same

Номер: US20120132857A1
Автор: Ronan P. Le Toquin
Принадлежит: Individual

Compounds of Formula I, which include both cerium and europium, may be useful as phosphors in solid state light emitting devices. Light emitting devices including such phosphors may emit warm white light.

Подробнее
Номер записи: 92
07-06-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120138946A1
Автор: Masao Kikuchi, Osamu Usui
Принадлежит: Mitsubishi Electric Corp

A semiconductor device includes a cooler having a main surface constructed of a metal base, joined layers fixed on the metal base through joining layers, insulating layers fixed on the joined layers and which contain an organic resin as a base material, metal layers provided on the insulating layers, and semiconductor elements provided on the metal layers. A stacked structure with the joined layers, the insulating layers, and the metal layers is divided into parts containing one or the plurality of semiconductor elements, and is fixed through the joining layers on the metal base.

Подробнее
Номер записи: 93
07-06-2012 дата публикации

Wafer mold material and method for manufacturing semiconductor apparatus

Номер: US20120139131A1
Автор: Hideto Kato, Kazunori Kondo, Michihiro Sugo
Принадлежит: Shin Etsu Chemical Co Ltd

The invention provides a wafer mold material for collectively subjecting a wafer having semiconductor devices on a surface thereof to resin molding, wherein the wafer mold material has a resin layer containing a filler and at least any one of an acrylic resin, a silicone resin having an epoxy group, an urethane resin, and a polyimide silicone resin, and the wafer mold material is formed into a film-like shape. There can be a wafer mold material that enables collective molding (wafer molding) with respect to a wafer having semiconductor devices formed thereon, has excellent transference performance with respect to a large-diameter thin-film wafer, can provide a flexible hardened material with low-stress properties, and can be preferably used as a mold material in a wafer level package with less warp of a formed (molded) wafer.

Подробнее
Номер записи: 94
07-06-2012 дата публикации

Electronic paper display device and method for manufacturing the same

Номер: US20120139884A1
Автор: Changsoo LIM, Haksun Kim, Hyunhak KIM, Jaechan LEE, Unghan MOON
Принадлежит: Samsung Electro Mechanics Co Ltd

Disclosed herein are an electronic paper display device and a method for manufacturing the same. The electronic paper display device including an electronic paper panel and various components, includes: a substrate made of an insulating material and being provided with wirings on a surface thereof and therein; and a driving IC bonded to the substrate and controlling the electronic paper panel to display an image, whereby it be manufactured by a more simplified process as compared to that of the related art and can remarkably reduce product costs by using more inexpensive components that are necessary as compared to those of the related art.

Подробнее
Номер записи: 95
07-06-2012 дата публикации

Wafer Level Structures and Methods for Fabricating and Packaging MEMS

Номер: US20120142144A1
Автор: Babak Taheri
Принадлежит: Babak Taheri

Methods of fabricating a Micro-Electromechanical System (MEMS) in a hermetically sealed cavity formed at a substrate level are provided. Generally, the method comprises: (i) forming a number of first open cavities in a surface of a first substrate and a number of second open cavities in a surface of a second substrate corresponding to the first open cavities; (ii) forming an actuator/sensor layer including a number of MEMS devices with electrically conductive regions therein; (iii) bonding the first substrate and the second substrate to the actuator/sensor layer so that at least one of the number of the first and second open cavities align with at least one of the number of MEMS devices to form a sealed cavity around the MEMS; and (iv) electrically connecting the electrically conductive regions of the MEMS device to a pad outside of the sealed cavity through an electrical interconnect. Other embodiments are also described.

Подробнее
Номер записи: 96
14-06-2012 дата публикации

Integrated circuit mounting system with paddle interlock and method of manufacture thereof

Номер: US20120146192A1
Автор: Arnel Senosa Trasporto, Byung Joon Han, Byung Tai Do, Henry Descalzo Bathan
Принадлежит: Individual

A method of manufacture of an integrated circuit mounting system includes: providing a die paddle with a component side having a die mount area and a recess with more than one geometric shape; applying an adhesive on the die mount area and in a portion of the recess; and mounting an integrated circuit device with an inactive side directly on the adhesive.

Подробнее
Номер записи: 97
14-06-2012 дата публикации

Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures

Номер: US20120146215A1
Автор: Chih-Hung Lu, Yu-Ju Yang
Принадлежит: ILI Techonology Corp

A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.

Подробнее
Номер записи: 98
21-06-2012 дата публикации

Semiconductor component, semiconductor wafer component, manufacturing method of semiconductor component, and manufacturing method of joining structure

Номер: US20120153461A1
Автор: Akio Furusawa, Hidetoshi Kitaura, Shigeaki Sakatani, Taichi Nakamura, Takahiro Matsuo
Принадлежит: Panasonic Corp

A semiconductor component of the present invention includes a semiconductor element and a joining layer formed on one surface of the semiconductor element and consisting of a joining material containing Bi as an essential ingredient, and projecting sections are formed on a surface of the joining layer on a side opposite to a surface in contact with the semiconductor element. By joining the semiconductor component to an electrode arranged so as to face the joining layer, the generation of a void can be suppressed.

Подробнее
Номер записи: 99
21-06-2012 дата публикации

Microelectronic package and method of manufacturing same

Номер: US20120153504A1
Автор: Edward R. Prack, Leonel R. Arana, Robert M. Nickerson
Принадлежит: Intel Corp

A microelectronic package includes a substrate ( 110, 210 ), an interposer ( 120, 220 ) having a first surface ( 121 ) and an opposing second surface ( 122 ), a microelectronic die ( 130, 230 ) attached to the substrate, and a mold compound ( 140 ) over the substrate. The interposer is electrically connected to the substrate using a wirebond ( 150 ). The first surface of the interposer is physically connected to the substrate with an adhesive ( 160 ), and the second surface has an electrically conductive contact ( 126 ) formed therein. The mold compound completely encapsulates the wirebond and partially encapsulates the interposer such that the electrically conductive contact in the second surface of the interposer remains uncovered by the mold compound.

Подробнее
Номер записи: 100