СБОРНЫЙ КОРПУС МИКРОСХЕМЫ И СПОСОБ ЕГО ИСПОЛЬЗОВАНИЯ

HALBLEITERBAUTEIL

Ein Halbleiterbauteil A1 der vorliegenden Offenbarung beinhaltet: ein Halbleiterelement 10 (Halbleiterelemente 10A und 10B), das eine Elementvorderfläche und eine Elementrückfläche hat, die in einer z-Richtung in einander entgegengesetzte Richtungen weisen; ein Trägersubstrat 20, das das Halbleiterelement 10 lagert; einen leitfähigen Block 60 (erster Block 61 und zweiter Block 62), der über ein erstes leitfähiges Bond-Material (Block-Bond-Materialien 610 und 620) an die Elementvorderfläche gebondet ist; und ein Metallelement (Anschlusselement 40 und Eingangs-Terminal 32), das über den leitfähigen Block 60 elektrisch mit dem Halbleiterelement 10 verbunden ist. Der leitfähige Block 60 weist einen Wärmeausdehnungskoeffizienten auf, der kleiner ist als jener des Metallelementes. Der leitfähige Block 60 und das Metallelement sind durch einen Schweißabschnitt (Schweißabschnitte M4 und M2), bei dem ein Abschnitt des leitfähigen Blocks 60 und ein Abschnitt des Metallelementes aneinander geschweißt ...

Package-Struktur und Verfahren

In einer Ausführungsform umfasst eine Vorrichtung: ein Substrat mit einer ersten Seite und einer zweiten Seite gegenüber der ersten Seite; eine Verbindungsstruktur benachbart zu der ersten Seite des Substrats; und eine IC-Vorrichtung, welche an der Verbindungsstruktur befestigt ist; eine Durchkontaktierung, welche sich von der ersten Seite des Substrats bis zu der zweiten Seite des Substrats erstreckt, wobei die Durchkontaktierung mit der IC-Vorrichtung elektrisch verbunden ist; eine Under-Bump-Metallurgie (UBM) benachbart zu der zweiten Seite des Substrats und die Durchkontaktierung kontaktierend; einen leitfähigen Höcker auf der UBM, wobei es sich bei dem leitfähigen Höcker und der UBM um ein durchgängiges leitfähiges Material handelt, wobei der leitfähige Höcker von der Durchkontaktierung seitlich versetzt ist; und eine Unterfüllung, welche die UBM und den leitfähigen Höcker umgibt.

Leiterplatte für Plastikhalbleitergehäuse

Substrat-Bondingstruktur und Substrat-Bondingverfahren

Eine Vorrichtung (2) ist auf einer Hauptoberfläche eines Substrats (1) ausgebildet. Die Hauptoberfläche des Substrats (1) ist über das Bonding-Bauteil (11, 12, 13) in einem hohlen Zustand an die Unterseite des Gegensubstrats (14) gebondet. Eine Schaltung (17) und eine Höckerstruktur (26) sind auf der Oberseite des Gegensubstrats (14) ausgebildet. Die Höckerstruktur (26) ist in einem Bereich positioniert, der zumindest dem Bonding-Bauteil (11, 12, 13) entspricht, und weist eine größere Höhe als diejenige der Schaltungsstruktur (17) auf.

Konzept zur spannungsarmen mechanischen Verbindung eines Halbleiterbauelements mit einem Substrat

Verfahren zur spannungsarmen, mechanischen Verbindung eines Halbleiterbauelements (100BE) mit einem Substrat (100Sub), wobei zumindest eines aus dem Halbleiterbauelement (100BE) und dem Substrat (100Sub) eine Verbindungsstruktur (102) mit zumindest drei symmetrisch zueinander angeordneten Verbindungselementen (104_1 bis 104_n) aufweist, und wobei das andere aus dem Halbleiterbauelement (100BE) und dem Substrat (100Sub) eine Verbindungsgegenstruktur (108) mit zumindest einem Verbindungsgegenelement (106_1 bis 106_m) aufweist, wobei die Verbindungsstruktur (102) und die Verbindungsgegenstruktur (108) Metalle oder Werkstoffe aufweisen, die sich unter Einwirkung von Ultraschall verbinden lassen, wobei das Verfahren folgende Schritte umfasst: Aufnehmen des Verbindungsgegenelements (106_1 bis 106_m) der Verbindungsgegenstruktur (108) zwischen den zumindest drei symmetrisch zueinander angeordneten Verbindungselementen (104_1 bis 104_n) der Verbindungsstruktur (102), so dass bei der Aufnahme der ...

MODUL-AUFBAU MIT INTEGRIERTEM HALBLEITERCHIP UND CHIPTRAEGER

Halbleitervorrichtung und Verfahren zu deren Herstellung

Halbleitervorrichtung, aufweisend:- ein isolierendes Substrat (1) mit einem ersten Schaltungsmuster (3);- ein Halbleiterelement (5), das an das erste Schaltungsmuster (3) mit einem ersten Lötmaterial (13) gebondet ist; und- einen Verdrahtungsanschluss (8), der mit einem zweiten Lötmaterial (14) an eine Elektrode gebondet ist, die am Halbleiterelement (5) auf einer gegenüberliegenden Seite des ersten Schaltungsmusters (3) ausgebildet ist, wobei:- ein Teil des Verdrahtungsanschlusses (8) an zwei vorstehenden Abschnitten in einer Draufsicht an gegenüberliegenden Seiten des Halbleiterelements (5) in Kontakt mit dem isolierenden Substrat (1) steht und vom ersten Schaltungsmuster (3) isoliert ist,- ein Harzgehäuse (7) auf dem isolierenden Substrat (1) und um das isolierende Substrat (1) herum angeordnet ist,- eine Endseite des Verdrahtungsanschlusses (8) in einer ersten Erstreckungsrichtung im Harzgehäuse (7) eingebettet ist und- der Teil des Verdrahtungsanschlusses (8), welcher die vorstehenden ...

Integriertes Passivvorrichtungs-Package und Verfahren zum Ausbilden von diesem

Ein Vorrichtungs-Package umfasst einen ersten Die, einen zweiten Die und eine Moldmasse, die sich entlang von Seitenwänden des ersten Die und des zweiten Die erstreckt. Das Package umfasst ferner Umverteilungsschichten (RDLs), die sich seitlich über Kanten des ersten Die und des zweiten Die hinaus erstrecken. Die RDLs umfassen einen Eingabe-/Ausgabekontakt (I/O-Kontakt), der mit dem ersten Die und dem zweiten Die elektrisch verbunden ist, und der I/O-Kontakt ist an einer Seitenwand des Vorrichtungs-Package freigelegt, die im Wesentlichen senkrecht zu einer den RDLs entgegengesetzten Fläche der Moldmasse ist.

INTEGRIERTES SCHALTUNGSPACKAGE UND VERFAHREN

In einer Ausführungsform weist eine Struktur Folgendes auf: einen ersten integrierten Schaltungsdie, der erste Die-Anschlüsse aufweist; eine erste Dielektrikumsschicht auf den ersten Die-Anschlüssen; erste leitfähige Durchkontaktierungen, die sich durch die erste Dielektrikumsschicht hindurch erstrecken, wobei die ersten leitfähigen Durchkontaktierungen an eine erste Untergruppe der ersten Die-Anschlüsse angeschlossen sind; einen zweiten integrierten Schaltungsdie, der an eine zweite Untergruppe der ersten Die-Anschlüsse mit ersten aufschmelzbaren Anschlüssen gebondet ist; ein erstes Verkapselungsmaterial, das den zweiten integrierten Schaltungsdie und die ersten leitfähigen Durchkontaktierungen umgibt, wobei das erste Verkapselungsmaterial und der erste integrierte Schaltungsdie seitlich angrenzend sind; zweite leitfähige Durchkontaktierungen benachbart zu dem ersten integrierten Schaltungsdie; ein zweites Verkapselungsmaterial, das die zweiten leitfähigen Durchkontaktierungen, das erste ...

Leistungshalbleitervorrichtung

Leistungshalbleitervorrichtung, bei der folgende Elemente in Spritzharz eingeschlossen sind: ein Schaltungssubstrat, das eine metallische Wärmeabführeinrichtung beinhaltet und das eine Isolierschicht mit hoher Wärmeleitfähigkeit beinhaltet, die mit der einen Oberfläche der metallischen Wärmeabführeinrichtung verbunden ist und ein Verdrahtungsmuster aufweist, das auf einer Oberfläche der Isolierschicht mit hoher Wärmeleitfähigkeit vorgesehen ist, die zu der mit der metallischen Wärmeabführeinrichtung verbundenen Oberfläche der Isolierschicht mit hoher Wärmeleitfähigkeit entgegengesetzt ist; ein Leistungshalbleiterelement, das mit einem Element-Montagebereich des Verdrahtungsmusters verbunden ist; und eine Seitenfläche eines zylindrischen Verbindungsbereichs für den externen Anschluß, der auf dem Verdrahtungsmuster in elektrischer Verbindung mit dem Leistungshalbleiterelement vorgesehen ist und in den ein externer Anschluß einsetzbar und mit diesem verbindbar ist, wobei: der zylindrische ...

Halbleitermoduleinheit und Halbleitermodul

Halbleitermodul, enthaltend:ein Halbleiterelement;eine isolierende Schaltungsplatine (11), welche auf einer der Hauptoberflächen eines Isoliersubstrats (2) ein mit dem Halbleiterelement elektrisch verbundenes Schaltungselement und ein auf der anderen Hauptoberfläche des Isoliersubstrats (2) angeordnetes erstes Metallelement (7) hat;ein zweites Metallelement (10a-f), das auf der Seite eines äußeren Randes des ersten Metallelements (7) angeordnet ist und zumindest teilweise weiter zu einer Außenseite hin als das Isoliersubstrat (2) angeordnet ist;einen Vergussharzabschnitt (9), der das Halbleiterelement, die isolierende Schaltungsplatine (11) und das zweite Metallelement (10a-f) in einem Zustand, in welchem ein Teil des ersten Metallelements (7) und ein Teil des zweiten Metallelements (10a-f) freiliegen, versiegelt;einen Kühler (1);ein erstes Bonding-Element (8a), welches den Kühler (1) und das erste Metallelement (7) verbindet; undein zweites Bonding-Element (8b-c), welches den Kühler (1 ...

System-in-Package für eine LED-Antriebs- und LED-Beleuchtungsvorrichtung einschließlich derselben

Lichtemittierende Dioden (LED) Beleuchtungsvorrichtung, umfassend:- mindestens eine LED-Gruppe, die eine Vielzahl von LEDs umfasst;- einen Gleichrichter, der konfiguriert ist, um eine Wechselstrom(AC)-Spannung gleichzurichten und eine Antriebsspannung für die mindestens eine LED-Gruppe zu erzeugen; und- ein System-in-Package (SIP), das konfiguriert ist, um die mindestens eine LED-Gruppe anzutreiben und zu steuern, wobei das SIP mit der mindestens einen LED-Gruppe und dem Gleichrichter verbunden ist, wobei das SIP ein Antriebsmodul, ein Funktionsmodul und einen ersten Widerstand umfasst, der auf einem einzelnen Substrat angeordnet ist.

STRUKTUR UND FERTIGUNGSVERFAHREN EINES DREIDIMENSIONALEN SYSTEMS EINER METALL-LEITERPLATTE, DIE VOR DEM HORIZONTALEN BESTÜCKEN GEÄTZT WIRD

Gegenstand ist eine horizontal bestückte, dreidimensionale, vor dem Bestücken geätzte System-Level-Metall-Leiterplatte, charakterisiert durch einen Metallsubstrat-Rahmen (1). Dieser Metallsubstrat-Rahmen (1) weist Basisbereiche (2) und Stifte (3) auf. Die Frontseiten der Basisbereiche (2) werden mit Chips (5) bestückt, die Frontseiten der Chips (5) sind über Metalldrähte (6) mit den Frontseiten der Stifte (3) verbunden. Auf den Front- oder den Rückseiten der Stifte (3) befinden sich Leitungspunkte (7). Die peripheren Bereiche der Basisbereiche (2), die Bereiche zwischen den Basisbereichen (2) und den Stiften (3), die Bereiche zwischen den Stiften (3), über den Basisbereichen (2) und den Stiften (3) und den Außenbereichen der Chips (5), die Metalldrähte (6) und die Leitungspunkte (7) sind mit Formmasse (8) vergossen und die Oberflächen des Rahmens aus Metall-Substrat (1), der Stifte (3) und der Leitungspunkte (7), die aus der Formmasse (8) herausragen, sind mit einer oxidationsbeständigen ...

Halbleitermodul

Es wird eine Technik zur Verbesserung der Kühlkapazität eines Halbleitermoduls, welches Pin-Bonding verwendet, vorgesehen. Das Halbleitermodul enthält: einen Pin (4), der mit einem Halbleiterelement (1) verbunden ist; ein Pin-Verdrahtungssubstrat (5), das einen zweiten Metallfilm (5c) und einen ersten Metallfilm (5b) auf der oberen bzw. unteren Oberfläche hat, wobei der erste Metallfilm (5b) und der zweite Metallfilm (5c) mit dem Pin (4) elektrisch verbunden sind; Lot (3c), das den Pin (4) und das Halbleiterelement (1) verbindet; ein DCB-Substrat (2), das einen dritten Metallfilm (2b) und einen vierten Metallfilm (2c) auf der oberen bzw. unteren Oberfläche hat, wobei der dritte Metallfilm (2b) an eine untere Oberfläche des Halbleiterelements (1) gebondet ist; und einen ersten Kühler (6), der mit dem vierten Metallfilm (2c) verbunden ist. Das Verhältnis (H/T) einer Höhe (H) des Lots zu einem Abstand (T) von dem Halbleiterelement (1) zu dem ersten Metallfilm (5b) ist gleich oder größer als ...

Leistungshalbleitermodul

Ein Leistungshalbleitermodul wird bereitgestellt, das eine Induktivität zwischen Verdrahtungsleitungen im Leistungshalbleitermodul reduziert, um eine Unterbindung eines Bruchs des Leistungshalbleiterelements durch eine Stoßspannung zu ermöglichen. Das Leistungshalbleitermodul: einen positiven Zweig und einen negativen Zweig, die durch eine Reihenschaltung von Halbleiterelementen (6) des lichtbogenselbstlöschenden Typs gebildet sind, und die an einer Reihenanschlussstelle zwischen den Halbleiterelementen (6) des lichtbogenselbstlöschenden Typs angeschlossen sind; eine positivseitige Gleichstromelektrode (10), eine negativseitige Gleichstromelektrode (11) und eine Wechselstromelektrode (12), die an den positiven Zweig und den negativen Zweig angeschlossen sind; und ein Substrat (2), auf dem ein Verdrahtungsmuster (3, 4) ausgebildet ist, wobei das Verdrahtungsmuster (3, 4) die Halbleiterelemente (6) des lichtbogenselbstlöschenden Typs des positiven Zweigs und des negativen Zweigs an die positivseitige ...

Semiconductor circuit arrangement has contact pin element that is formed between semiconductor module and circuit board

The semiconductor circuit arrangement has a contact pin element (16) that is formed between a semiconductor module (12) and a circuit board (14). The contact pin element is made of a metallic-shaped memory alloy. A contact head portion (22) is formed in the contact pin element and is designed as a hollow cylinder (24). A metal layer (26) is formed on the contact head portion.

Halbleitervorrichtung und Halbleitervorrichtungs-Herstellverfahren

Es wird eine Halbleitervorrichtung bereitgestellt, um ein Knicken eines Anschlussstifts in der Halbleitervorrichtung mit einer Leiterplatte, in der der Anschlussstift eingepresst wird, zu verhindern, wobei die Halbleitervorrichtung eine Leiterplatte, mehrere in die Leiterplatte eingepresste Stifte, einen Harzblock, in dem mehrere Durchgangslöcher ausgebildet sind, wobei die mehreren Stifte jeweils in die mehreren Durchgangslöcher eingepresst sind, und ein Harzgehäuse, das mindestens einen Teil der Leiterplatte und des Harzblocks abdeckt, umfasst.

Halbleiter-Bauelement und Verfahren

Ein Halbleiter-Bauelement weist Folgendes auf: ein Substrat; eine erste Umverteilungsschicht (RDL) über einer ersten Seite des Substrats; eine oder mehrere Halbleiter-Dies, die über der ersten RDL angeordnet sind und mit dieser elektrisch verbunden sind; und ein Verkapselungsmaterial über der ersten RDL und um den einen oder die mehreren Halbleiter-Dies. Das Halbleiter-Bauelement weist weiterhin Anschlüsse auf, die an einer zweiten Seite des Substrats befestigt sind, die der ersten Seite gegenüberliegt, wobei die Anschlüsse elektrisch mit der ersten RDL verbunden sind. Das Halbleiter-Bauelement weist weiterhin eine Polymerschicht auf der zweiten Seite des Substrats auf, wobei die Anschlüsse von der Polymerschicht her über eine erste Oberfläche der Polymerschicht überstehen, die von dem Substrat entfernt ist. Ein erster Teil der Polymerschicht, der die Anschlüsse kontaktiert, hat eine erste Dicke, und ein zweiter Teil der Polymerschicht zwischen benachbarten Anschlüssen hat eine zweite Dicke ...

Halbleitermodul

Ein Leistungsmodul (1), das eine Halbbrücke bereitstellt, wobei das Leistungsmodul umfasst: mindestens ein Substrat (2), das eine innere Lastbahn (3), zwei dazwischenliegende Lastbahnen (4) und zwei äußere Lastbahnen (5) umfasst, wobei jede der Lastbahnen länglich ist und sich im Wesentlichen über das mindestens eine Substrat (2) in einer ersten Richtung (6) erstreckt; wobei die beiden dazwischenliegenden Lastbahnen (4) bei der inneren Lastbahn (3) angeordnet sind und jede äußere Lastbahn (5) auf der gegenüberliegenden Seite eine der beiden dazwischenliegenden Lastbahnen (4) bezüglich einer zweiten Richtung (7) im Wesentlichen orthogonal zu der ersten Richtung (6) angeordnet ist.

Gehäuse eines integrierten Schaltkreises und Verfahren zum Bilden desselben

Eine Ausführungsform einer Gehäuse-auf-Gehäuse(PoP)-Vorrichtung umfasst eine Gehäusestruktur, einen Gehäuseträger und eine Vielzahl von Anschlüssen, die die Gehäusestruktur mit dem Gehäuseträger verbinden. Die Gehäusestruktur umfasst einen Logikchip, der mit einem Speicherchip verbunden ist, eine Formmasse, die den Speicherchip umschließt und eine Vielzahl leitfähiger Stifte, die sich durch die Formmasse hindurch erstrecken. Die Vielzahl der leitfähigen Stifte ist an Kontaktpolstern auf dem Logikchip befestigt.

VERFAHREN ZUR HERSTELLUNG EINER EINE KONTAKTHÜLSE AUFWEISENDEN ELEKTRONIKBAUGRUPPE

Verfahren zur Herstellung einer Elektronikbaugruppe (400), das aufweist: Bereitstellen einer ersten Metallisierungsschicht (51) mit einer Oberseite (51t) und einer Vertiefung (511), die sich ausgehend von der Oberseite (51t) in die erste Metallisierungsschicht (51) hinein erstreckt; und Bereitstellen einer elektrisch leitenden Kontakthülse (100), die sich in einer Längsrichtung (z) erstreckt, die eine erstes Ende (11) und ein dem ersten Ende (11) entgegengesetztes zweites Ende (12) aufweist, sowie einen Schaft (13), der sich zwischen dem ersten Ende (11) und dem zweiten Ende (12) erstreckt, wobei an dem ersten Ende (11) ein erster Kragen (111) ausgebildet ist, sowie eine Vorsprungsstruktur (112), die sich ausgehend von dem ersten Kragen (111) vom zweiten Ende (12) weg erstreckt; Anordnen der Kontakthülse (100) auf der Metallisierungsschicht (51) derart, dass die Vorsprungsstruktur (112) in die Vertiefung (511) eingreift; und Verlöten der Kontakthülse (100) und der ersten Metallisierungsschicht ...

Leistungshalbleitermodul und Verfahren zur Herstellung eines Leistungshalbleitermoduls

Ein Leistungshalbleitermodul kann einen Träger, einen Leistungshalbleiterchip, der so über dem Träger angeordnet ist, dass eine erste Hauptseite des Leistungshalbleiterchips dem Träger zugewandt ist, einen Kontaktclip, der so über dem Leistungshalbleiterchip angeordnet ist, dass eine zweite, der ersten Hauptseite gegenüberliegende Hauptseite des Leistungshalbleiterchips; dem Kontaktclip zugewandt ist, und ein zwischen der zweiten Hauptseite und dem Kontaktclip angeordnetes Abstandshalterelement umfassen, wobei eine erste Lötverbindung die zweite Hauptseite und das Abstandshalterelement verbindet und wobei eine zweite Lötverbindung das Abstandshalterelement und den Kontaktclip verbindet.

HALBLEITER-BAUELEMENT UND VERFAHREN ZU DESSEN HERSTELLUNG

Ein Verfahren weist die folgenden Schritte auf: Herstellen einer Vorrichtungsstruktur, wobei das Herstellen der Vorrichtungsstruktur das Herstellen einer ersten Umverteilungsstruktur über und in elektrischer Verbindung mit einer Halbleitervorrichtung und das Herstellen eines Formmaterials um die erste Umverteilungsstruktur und die Halbleitervorrichtung umfasst; Herstellen einer zweiten Umverteilungsstruktur über dem Formmaterial und der ersten Umverteilungsstruktur, wobei die zweite Umverteilungsstruktur mit der ersten Umverteilungsstruktur elektrisch verbunden ist; Befestigen einer Verbindungsstruktur an der zweiten Umverteilungsstruktur, wobei die Verbindungsstruktur ein Kernsubstrat aufweist und mit der zweiten Umverteilungsstruktur elektrisch verbunden ist; und Abscheiden eines Unterfüllungsmaterials auf Seitenwänden der Verbindungsstruktur und zwischen der zweiten Umverteilungsstruktur und der Verbindungsstruktur.

Leiterplatte mit verbesserten Positionierungsmitteln

Semiconductor system comprises substrate with contact pad connected to e.g. solder beads, system being encapsulated on at least five sides and mechanical decoupling system mounted between encapsulation and semiconductor

Semiconductor system comprises a substrate (10) with a contact pad (11) which is connected by conductors (12) to connectors, e.g. solder beads (13). The system is encapsulated (14) on at least five sides and a mechanical decoupling system (15) is mounted between the encapsulation and the semiconductor. An independent claim is included for a method for making the semiconductor system.

Fastener for mechanical fastening and electrical contacting of electronic component has carrier element and multitude of fastening elements wherein fastening elements are arranged on carrier element and comprises in each case oblong body

Fastener (1) has a carrier element (2) and multitude of fastening elements (3). The fastening elements are arranged on the carrier element and comprises in each case an oblong body, which protrudes from carrier element and possesses a suitable form between further fastening elements for engaging and/or hooking. Fastening elements and carrier element are electrically conductive on their surface. Independent claims are also included for the following: (A) Electronic component; (B) Arrangement with an electronic conductor board and a semiconductor unit; and (C) Procedure for fastening semiconductor unit on an electronic conductor board.

Elektrische Baugruppe mit Abstandshaltern zwischen mehreren Schaltungsträgern

Elektrische Baugruppe (1), aufweisend einen Schaltungsträger (2, 23) mit mindestens einem elektrischen Stromkreis (21), der mindestens ein auf einem Oberflächenabschnitt (237) des Schaltungsträgers (2, 23) angeordnetes elektrischen Bauelement (22, 221) aufweist, und mindestens einen weiteren Schaltungsträger (3, 33) mit mindestens einem weiteren elektrischen Stromkreis (31), wobei der Schaltungsträger (2, 23) und der weitere Schaltungsträger (3, 33) derart aneinander angeordnet sind, dass ein Zwischenraum (6) zwischen dem Schaltungsträger (2) und dem weiteren Schaltungsträger (3) vorhanden ist und sich das Leistungshalbleiterbauelement (221) in dem Zwischenraum (6) befindet, der Stromkreis (21) und der weitere Stromkreis (31) über mindestens eine elektrische Verbindungsleitung (5) elektrisch leitend miteinander verbunden sind, das auf dem Oberflächenabschnitt (237) des Schaltungsträgers (2, 21) angeordnete Bauelement (22, 21) dem weiteren Schaltungsträger (3, 33) gegenüberliegend angeordnet ...

Lötverfahren und Schaltung

Vorgeschlagen wird ein Lötverfahren zum Verbinden eines Halbleiterchips (1) mit einer Leiterplatte (2) über wenigstens einen Lötkontakt (7) und zum Herstellen einer Schaltung (14), wobei der Halbleiterchip wenigstens ein elektrisch leitendes Pad (5) aufweist und die Leiterplatte wenigstens einen Leiterbahnabschnitt (9) zur Kontaktierung mit wenigstens einem der Pads des Halbleiterchips umfasst, umfassend: eine Auftragung von Lötpaste (10) auf den wenigstens einen Leiterbahnabschnitt, einen Bondingprozess, bei dem ein Höcker (7) auf wenigstens einem Materialabschnitt (6) auf wenigstens eines der Pads gebondet wird, einen Bestückungsvorgang, bei dem die Leiterplatte so mit wenigstens einem der Halbleiterchips bestückt wird, dass wenigstens einer der Lötkontakte mit der Lötpaste in Berührung kommt, einen Heizprozess, bei dem eine elektrisch leitende Verbindung zwischen dem Leiterbahnabschnitt und dem Pad hergestellt wird. Zur Verbesserung des Lötverfahrens wird als Lötkontakt ausschließlich ...

An apparatus and associated methods for flexible carrier substrates

An apparatus comprising: a flexible carrier substrate 102 comprising a substrate contact pad 104, 106 configured to allow electrical connection of a carried electronic component to one or more other carried electronic components 112; an electronic component 112 carried on the flexible carrier substrate, the electronic component comprising a component contact pad 114, 116 configured to allow electrical connection to the electronic component; and a curved interconnection 126 electrically interconnecting the respective substrate and component contact pads, wherein the curved interconnection is configured such that its curvature allows the interconnection to maintain its connection to the respective contact pads with operational flexing of the flexible carrier substrate. The curved interconnection removes the stress caused by flexing of the substrate.

Semiconductor device

A semiconductor device 1 according to an embodiment of the present invention is a semiconductor device to be attached to a heat dissipating body. The semiconductor device is provided with: a heat generating electronic component 20; a sealing section 30 that seals the heat generating electronic component 20; a lead member 40 having an inner lead section 41 sealed by means of the sealing section 30, and an outer lead section 42 exposed from the sealing section 30; and a lead member 50, which has an inner lead section 51 sealed by means of the sealing section 30, and an outer lead section 52 exposed from the sealing section 30. The inner lead section 41 has: a heat dissipating end portion 41c that dissipates heat to the heat dissipating body, said heat having been propagated from the outer lead section 42; and an electrically connecting portion 41d, which is positioned between the heat dissipating end portion 41c and the outer lead section 42, and which is electrically connected to a main ...

Cast solder leads for leadless semiconductor circuits

The attachment of leadless chip carriers to printed wiring boards by means of soldering techniques must provide for a spacing between the chip carrier and the board. Such spacing is required for cleaning the area under the chip carrier, protecting the underlying circuitry, and accounting for stresses which may develop due to thermal mismatch between the chip carrier and the board, and to board flexure. Herein disclosed is a lead (15) for semiconductor chip carriers comprising an elongated body of high melting point electrically conductive material, e.g., solder material. Also disclosed is a method for casting such a solder lead, and a method for attaching a plurality of cast solder leads (38) to a leadless chip carrier (20).

Ceramic module for power semiconductor integrated packaging and preparation method thereof

METALLIC LEADS FOR ELECTRONIC DEVICES

... 1331901 Component assemblies; semi-conductor devices E I DU PONT DE NEMOURS & CO 4 Feb 1972 [5 Feb 1971] 5408/72 Headings H1K and H1R [Also in Division H2] In a semi-conductor device package, the thick film material substrate 8 is connected to metallic leads 2, by means of a clamp portion 3. Bifurcated fingers 4 and 5 clamp the lead to the terminal 9, and are soldered thereto, and laterally disposed offset tab 7 is adapted to abut the clamp 3 at a predetermined distance from the substrate. In Fig. 3, an adaptation with only two of the described leads 11 is shown. The nature of the clamp is to maintain a rigid bond at the high temperatures required for the use of thick film materials in the insulating dielectric, 13, substrate 8, metallurgical seal ring 12, conducting fingers 14 semi-conductor die attachment region 15, and terminal pads 9, the assembly may then be hermetically sealed. An elongated shorting or tie bar 1 is provided to maintain the leads 2 in proper relationship to each other ...

CIRCUIT ASSEMBLIES

... 1498637 Electrical connectors SIEMENS AG 24 Oct 1975 [6 Dec 1974] 43722/75 Heading H2E [Also in Division H1] Wire bridges 11 are soldered between the contact arms 8a and 8c, or 8b and 8d, extending from the contact elements 5 which are soldered to the electrodes 6, to switch off, or switch on, the attenuation T-element formed by film circuit resistances 2a, 2b, 2c on the glass or ceramic substrate 3. Contact arm 8 and resistance 2 are part of the next attenuation element on the substrate. Cross pieces 13, 15, which facilitate connection of the contact elements to the substrate, are removed after soldering of the latter, the rods 7 then being inserted through holes in a carrier plate for soldering to printed circuit paths thereon.

SELECTIVE CONNECTION DURING THE IC PACKAGING

COMPOUND CERAMIC SUBSTRATE

IC-SOCKEL UND ELEKTRONISCHES BAUELEMENT

PROCEDURE FOR THE PRODUCTION OF AN ELECTRONIC BUILDING GROUP WITH AN ELECTRONIC CONSTRUCTION UNIT WITH HIGH-DENSITY ONE, ECONOMICAL MOUNTING

HYBRID INTEGRATED CIRCUIT WITH A SYSTEM FOR HEAT DISSIPATION

TO CIRCUIT ASSEMBLIES

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SEMI-CONDUCTOR DEVICE

Electrical contact structures from flexible wire

A thin multichip module

CARRIER STRIP FOR ROUND LEAD PINS AND METHOD FOR MAKING SAME

TERMINAL LEAD CONSTRUCTION FOR ELECTRICAL CIRCUIT SUBSTRATE

AREA-ARRAY WITH LOW INDUCTANCE CONNECTING DEVICE

An area-array integrated circuit package assembly are provided with a plurality of electrically conductive connectors attached to the package I.O. pads, that are used to connect the package to a printed circuit card or other component. The connectors comprise at least two parallel conductors flexing together in the same direction, electrically insulated from each other for a portion of their length between the package and printed circuit card to provide for reduced interconnection inductance. The connection with the component contact pads can be achieved by mechanically pressing the package and circuit card together or with the use of bonding material.

HIGH DENSITY AREA ARRAY SOLDER MICROJOINING INTERCONNECT STRUCTURE AND FABRICATION METHOD

A system for interconnecting a set of device chips by means of an array of microjoints disposed on an interconnect carrier is taught. The carrier is provided with a dense array of microjoint receptacles with an adhesion layer, barrier layer and a noble metal layer; the device wafers are fabricated with an array of microjoining pads comprising an adhesion layer, barrier layer and a fusible solder layer with pads being located at matching locations in reference to the barrier receptacles; said device chips are joined to said carrier through the microjoint arrays resulting in interconnections capable of very high input/output density and inter-chip wiring density.

PLOT DE REPORT DE CONNEXION POUR LA FIXATION D'UNE BROCHE A GRIFFES SUR LA TRANCHE D'UN SUBSTRAT DE CIRCUIT HYBRIDE

... : Plot de report de connexion pour la fixation d'une broche à griffes sur la tranche d'un substrat de circuit hybride. Ce plot de report de connexion de bord est destiné à la fixation d'une broche de connexion (30). Il présente deux plages étamables (17, 18) placées en vis à vis sur les côtés opposés d'un bord de substrat (10), aux endroits de préhension des griffes (33, 34, 35) de la broche (30) qui forment les mâchoires d'une pince élastique. Ces plages étamables (17, 18) sont entaillées de rainures (19, 20) aux emplacements des chemins de coulissement suivis par les griffes (33, 34, 35) lors de la mise emplace de la broche (30). Elles ont, dans le cas d'une broche (30) à trois griffes de même largeur totale qu'elles, l'une (17) la forme générale d'un U et l'autre (18) celle d'un T. Leur intérêt est de restreindre l'amplitude de l'ouverture de la pince de la broche et de lui assurer un centrage automatique sur le plot lorsque les plages (17, 18) sont déjà étamées. FIGURE A PUBLIER : Figure ...

SEMICONDUCTOR DEVICE PACKAGE

LEAD FRAME CONNECTOR AND ELECTRONIC PACKAGES CONTAINING SAME

R.F. POWER TRANSISTOR DEVICE WITH CONTROLLED COMMON LEAD INDUCTANCE

METHOD OF FORMING AN INTEGRATED CIRCUIT ASSEMBLY

PACKAGE-ON-PACKAGE (POP) DEVICE COMPRISING BI-DIRECTIONAL THERMAL ELECTRIC COOLER

A package-on-package (PoP) device includes a first package, a second package, and a bi-directional thermal electric cooler (TEC). The first package includes a first substrate and a first die coupled to the first substrate. The second package is coupled to the first package. The second package includes a second substrate and a second die coupled to the second substrate. The TEC is located between the first die and the second substrate. The TEC is adapted to dynamically dissipate heat back and forth between the first package and the second package. The TEC is adapted to dissipate heat from the first die to the second die in a first time period. The TEC is further adapted to dissipate heat from the second die to the first die in a second time period. The TEC is adapted to dissipate heat from the first die to the second die through the second substrate.

APPLICANT SCREENING

Systems (100, 2700) and methods (3400) for screening applicants (102, 2702) are disclosed herein. A method (3400) of screening applicants (102, 2702) is performed by a screening server (112, 2712). The server (112, 2712) begins by receiving (3402) a selection of screening services and an applicant profile that identifies an applicant (102, 2702). The screening continues by generating (3404) screening results specified by the selection of screening services based on the applicant profile. A property manager (120, 2720) is then notified (3406) that the screening results are available for the applicant (102, 2702) based upon the applicant profile. The screening results are then provided (3410) to the property manager (120, 2720) based upon the applicant profile. Based on these screening results, the screener or property manager (120, 2720) can make a decision about the applicant (102, 2702) and communicate a decision action to the applicant (102, 2702).

CONTACT BUMP CONNECTION AND CONTACT BUMP AND METHOD FOR PRODUCING A CONTACT BUMP CONNECTION

The invention relates to a contact bump connection (24) and to a method for producing a contact bump connection between an electronic component provided with at least one terminal face (11) and a contact substrate (26) contacted with the component and having at least one second terminal face (25), wherein the first terminal face is provided with a contact bump (10) which has a raised edge (15) and has at least one displacement pin (16) in a displacement compartment (18) which is surrounded by the raised edge and is open towards a head end of the contact bump, and in a contact region (31) with the first terminal face the second terminal face has a contact bead (30) which is formed by displacement of a contact material (29) of the second terminal face into the displacement compartment and surrounds the displacement pin, wherein said contact bead has a bead crown (33) which is directed to a base (17) of the displacement compartment and is raised relative to a level contact surface (32) of ...

CONNECTING DEVICES AND METHOD FOR INTERCONNECTING CIRCUIT COMPONENTS

An integrated circuit package having metallized contact pads is provided wit h flexible or resilient connecting devices permanently attached onto each contact pad. The connectin g devices are flexed when so attached, and are aligned and assembled onto corresponding pa ds of a printed circuit board, and provide electrical interconnection between the integrated circuit package and a printed circuit board. Electrically conducting connecting devices and method of attaching the devices to the package are described.

HIGH DENSITY ELECTRICAL CONNECTORS

The present invention relates to self-aligned, flexible high density and impedance adjusted electrical connectors used in microelectronic systems. This invention solves the problem of having electrical connection and alignment at the same time. One connector (200) having a first part (204) consists of two metal layer structures, a first signal path (212) and a first ground path (210), covering the V-groove (202). The connector also has a second part (208) consisting of corresponding metal layers, a second signal path (224) covering the elastic bump (206) and a second signal ground plane (226), which fits into the V-groove (202). The first and the second signal path (212, 224) are in contact with each other when the first and the second part (204, 208) are brought together. The contact is self-aligned when put together. The electrical contact will remain even if displaced due to the thermal expansion.

Halbleiteranordnung

Halbleiteranordnung

Preparation of semiconductor switches using

Preparation of semiconductor switches using micromodular methods of construction, in which a number of semiconducting plates or wafers, each of which contains at least a single building unit, is soldered to a thin insulated plate e.g. of copper plated ceramic, glass or the like having a metallised switch pattern on at least one side, and fixed to a support by a plurality of wire connections which is characterised by the following (partly known) features (a) all the electrodes, e.g. (1), (2), (3), (7), (10) are arranged on a surface of the semiconducting plate (1a) or (1b), and each carries a coating of a solder material on a large surface of contact (4), (5), (6), (9), (11). (b) the semiconducting plates and the electrodes are inserted in the opening of a template and then placed on the insulating plate in such a way that the large contact surfaces, e.g. (4), (5), etc. are in contact with the switch pattern, and are then soldered by heating, and after cooling the template is removed. (c ...

Procedimento di montaggio di uno o più circuiti elettronici integrati in un contenitore

Intermediate semiconductor chip substrate for lead frame - provides wire connections between integrated circuit chip and conductor paths and between latter and lead frame fingers

The substrate supporting at least one chip (106) on one side (105) comprises a plastics material carrier (109) coated with adhesive on both sides for attaching it to the connection fingers (108) of the lead frame (101) and providing the electrical connections between the latter and the connection terminals (107) of the IC chip(s) (106). Metal elements (110,111) provide the connections between the IC chip terminals (107) and conductor path terminals (104) of the substrate (102) and the corresponding conductor path terminals (104) and the lead frame fingers. ADVANTAGE - Prevents overheating.

CONTACTING ARRANGEMENT AT A THICK-FILM CIRCUIT.

Chip Carriers And Semiconductor Devices Including Redistribution Structures With Improved Thermal And Electrical Performance

Power semiconductor module and power unit

Method for producing contact areas on a semiconductor substrate

The invention relates to a method for producing contact areas on a semiconductor substrate. The present invention is related to a method for producing hollow contact areas suitable for insertion bonding, formed on a semiconductor substrate (1) comprising a stack of one or more metallization layers on its surface. Openings are etched in a dielectric layer by plasma etching, using a resist layer as a mask. The resist material and the plasma etch parameters are chosen so as to obtain openings with sloped sidewalls that have a predefined slope, due to the controlled formation of a polymer layer forming on the sidewalls of the resist hole and the hollow contact opening formed during the etch step. According to a preferred embodiment, metal deposited in the hollow contact areas and on top of the dielectric is planarized using Chemical Mechanical Polishing, leading to mutually isolated contact areas. An array of such areas can be produced having smaller pitch compared to prior art arrays. The ...

Wafer level system packaging method and packaging structure

Method of manufacturing semiconductor device and semiconductor device

Electric component part having lead terminals

Semiconductor device free from short-circuit between bump electrodes and separation from circuit board and process of fabrication thereof

Microelectronic packages and methods therefor

A microelectronic package (90) includes a microelectronic element (62) having faces and contacts, the microelectronic element (62) having an outer perimeter, and a flexible substrate (42) overlying and spaced from a first face of the microelectronic element (62), whereby an outer region of the flexible substrate (42) extends beyond the outer perimeter of the microelectronic element (62). The microelectronic package (90) includes a plurality of etched conductive posts (40a-40f) exposed at a surface of the flexible substrate (42) and being electrically interconnected with the microelectronic element (62), whereby at least one of the etched conductive posts (40a-40f) is disposed in the outer region (86) of the flexible substrate (42), and an adaptation layer (74) is disposed between first surface of the microelectronic element (62) and the flexible substrate (42), wherein, the adaptation layer (74) is covered on at least one of conductive posts disposed in the outer region (86) of the flexible ...

Electrical interconnection device for connecting power supply electricity with at least one electronic component and related electronic system

An electrical interconnection device includes a first terminal, a second terminal, an insulation substrate, a first conduction layer and a current conduction loop. The insulation substrate includes parallel top and bottom surfaces. The first conduction layer is set to contact with the top surface, and includes a bonding pad and current traces for connecting the electronic components. The first conduction layer forms a first current conduction plane. The current conduction loop is arranged between the first terminal and the second terminal, includes the traces and has an inductance. The device includes a component for reducing loop inductance. The component comprises a second conduction layer and an electrical connection piece. The second conduction layer is set to contact with the bottom surface. The second layer forms with a second conduction plane parallel to the first plane. The electrical connection piece is between the two planes. The first terminal is connected to the first plane ...

Electrolytic depositon and via filling in coreless substrate processing

Electronic assemblies including coreless substrates and their manufacture using electrolytic plating are described. One method includes providing a core comprising a metal, and forming a dielectric material on the core. The method also includes forming vias in the dielectric material, the vias positioned to expose metal regions. The method also performs an electrolytic plating of metal into the vias and on the metal regions, wherein the core is electrically coupled to a power supply during the electrolytic plating of metal into the vias and delivers current to the metal regions. The method also includes removing the metal core after the electrolytic plating of metal into the vias. Other embodiments are described and claimed.

Welding remedial method and the use of the method for semiconductor device

A flip chip film and display device

The electric component and is used in the method of manufacturing the electric component

Printed wiring board

A printed wiring board comprises a wiring substrate provided with at least one conductor circuit, a solder resist layer formed on the surface of the wiring substrate, covering the at least one conductor circuit, conductor pads formed on a part of the at least one conductor circuit exposed from respective openings provided in the solder resist layer for mounting electronic parts, and solder bumps formed on the respective conductor pads. Connection reliability and insulation reliability are easily improved by making the ratio (H/D) of a height H from solder resist layer surface the solder bump to an opening diameter of the opening about 0.55 to about 1.0 even in narrow pitch structure under the pitch of the opening provided in the solder resist layer of about 200 mum or less.

Encapsulation of pin solder for maintaining accuracy in pin position

Structure for reducing integrated circuit corner peeling

A crack prevention structure that reduces integrated circuit corner peeling and reduces cracking is disclosed. The crack prevention structure comprises a semiconductor substrate; a first plurality ofdielectric layers of a first material disposed over the semiconductor substrate; a second plurality of dielectric layers of a second material different than the first material, disposed on the first plurality of dielectric layers, wherein the first plurality of dielectric layers and the second plurality of dielectric layers meet at an interface; and a plurality of metal structures and a pluralityof via structures formed through the interface of the first plurality of dielectric layers and the second plurality of dielectric layers.

Semiconductor device and manufacture method therefor

MODULATE ELECTRONIC

SEMICONDUCTOR DEVICE PACKAGE

ASSEMBLING AN INTEGRATED CIRCUIT DIE AND A PLATE

LSI electronic circuit support assembly

Assemblage de dispositifs électroniques comprenant un boîtier de support de bande (1) supportant un circuit LSI (2) et ayant des trous traversants (8) disposés bidimensionnellement dans un film et connectés électriquement au circuit LSI par un motif de câblage, et un substrat isolant (3) ayant des broches d'entrée/sortie (4) connectées à des pastilles (9) fournies sur un substrat de montage (6), s'étendant dans et en contact avec les trous (8). Le boîtier de support de bande peut être fabriqué de façon aussi peu coûteuse que le boîtier TBGA de l'état de l'art, à un coût inférieur à celui d'un câblage similaire utilisant un substrat stratifié céramique. La constante diélectrique et d'autres facteurs du matériau du substrat isolant (3) n'ont pas à être pris en compte, et on peut utiliser le matériau le moins coûteux.

ELECTRONIC POWER MODULE

METHOD FOR REALIZATION Of ELEMENTS CHIP HAS PROVIDED WITH GROOVES Of INSERTION OF WIRE

L'invention concerne un procédé de réalisation d'éléments à puce (10) munis d'une rainure (14), comprenant les étapes suivantes : prévoir, sur un substrat d'interconnexion (22), une piste conductrice (26) agencée pour relier une plage de contact d'une face active d'une puce (20) à une zone correspondant à une première paroi de la rainure ; faire croître par électrodéposition un plot de contact (16) sur la piste conductrice au niveau de la zone correspondant à la première paroi de la rainure ; assembler la puce (20) sur le substrat par sa face active de manière qu'une paroi latérale de la puce forme le fond de la rainure ; usiner la puce par sa face arrière parallèlement au substrat en mesurant la distance entre la face arrière de la puce et le plot de contact ; arrêter l'usinage lorsque la distance mesurée atteint une valeur souhaitée ; et assembler par collage une plaque (24) sur la face arrière de la puce de manière à former une deuxième paroi de la rainure.

METHODS OF FORMING A MICROELECTRONIC DEVICE STRUCTURE, AND RELATED MICROELECTRONIC DEVICE STRUCTURES AND MICROELECTRONIC DEVICES

Procédé de formation d'une structure de dispositif micro-électronique qui comprend l'enroulement d'une portion d'un câble électrique autour d'au moins une paroi Latérale d'une structure qui fait saillie depuis un substrat. Au moins une interface entre une région supérieure de la structure et une région supérieure de la portion enroulée du câble électrique est soudée pour former une région de fusion entre la structure et le câble électrique.

Hybridization method of electronic component e.g. x-ray or infrared radiation sensors, involves forming protrusions of larger size on pads of electronic component

Ce procédé d'hybridation consiste : - à munir un premier composant 1 de premiers plots 3 de réception de protubérances, - à munir un deuxième composant 2 de deuxièmes plots 5 de réception de protubérances, - les premiers 3 et deuxièmes 5 plots étant respectivement destinés à être associés deux à deux pour former des paires de plots, - puis, à munir les premiers plots et/ou les deuxièmes plots de protubérances 4 réalisées en un matériau fusible, - puis à reporter l'un sur l'autre les premier et deuxième composants, - puis à porter l'ensemble des premier et deuxième composants et corollairement les protubérances de soudure à une température de soudure pour interconnecter les premiers et deuxièmes plots de chaque paire de plots par soudage des protubérances sur ces plots, - et enfin, à faire refroidir la soudure ainsi obtenue. Parmi les protubérances 4 de matériau fusible équipant les premiers 3 et/ou les deuxièmes 5 plots, sont réalisées au moins trois protubérances 6 de plus grandes dimensions ...

반도체 디바이스 및 제조 방법

... 반도체 디바이스 및 제조 방법이 제공된다. 리플로우 가능 물질이 관통 비아와 전기 접속하고, 관통 비아는 봉지재를 통해 연장된다. 보호층이 리플로우 가능 물질 위에 형성된다. 실시예에서, 개구부는 리플로우 가능 물질을 노출하기 위해 보호층 내에 형성된다. 다른 실시예에서, 보호층은 리플로우 가능 물질이 보호층으로부터 멀리 연장되도록 형성된다.

팬-아웃 반도체 패키지

... 본 개시는 관통홀을 갖는 제1연결부재, 제1연결부재의 관통홀에 배치되며 접속패드가 배치된 활성면 및 활성면의 반대측에 배치된 비활성면을 갖는 프로세서칩, 제1연결부재의 관통홀에 배치되며 접속패드가 배치된 활성면을 가지며 복수의 다이가 적층된 형태의 메모리칩, 제1연결부재와 메모리칩과 프로세서칩의 비활성면의 적어도 일부를 봉합하는 봉합재, 및 제1연결부재와 메모리칩의 활성면과 프로세서칩의 활성면 상에 배치된 제2연결부재를 포함하며, 제1 및 제2연결부재는 프로세서칩의 접속패드 및 메모리칩의 접속패드와 전기적으로 연결된 재배선층을 각각 포함하며, 프로세서칩의 접속패드 및 메모리칩의 접속패드는 제2연결부재의 재배선층을 통하여 서로 전기적으로 연결된 팬-아웃 반도체 패키지에 관한 것이다.

범프-온-트레이스 칩 패키징용 디바이스 및 그 형성 방법

... 제1 기판을 제2 기판에 부착하기 위한 방법 및 장치가 제공된다. 몇몇 실시예에서, 제1 기판은 제2 기판이 부착되어 있는 다이 부착 영역 주위에 땜납 마스크와 같은 보호층을 갖는다. 제한 영역(예를 들어, 제2 기판과 보호층 사이의 영역)은 보호층이 형성되지 않거나 제거되어 있는 제2 기판 주위의 영역이다. 제한 영역은 공극을 감소시키거나 방지하면서 그리고 제한 영역 내의 트레이스가 언더필에 의해 덮여지게 하면서 제1 기판과 제2 기판 사이에 언더필을 배치하기 위해 충분한 간극이 제2 기판과 보호층 사이에 존재하도록 치수 설정된다.

CANTILEVER BEAMS AND MANUFACTURING METHOD OF INTERCONNECTS FACTOR USING SACRIFICIAL SUBSTRATES

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

The present invention relates to a semiconductor package and a manufacturing method, and is to provide a manufacturing method of a semiconductor package, in which a greater number of leads are secured in a space with a predetermined size, a half-sewing process is more easily performed through a semiconductor package including a lead frame configured such that a structure design of the lead is freely variable, and the design can be variously changed by the structure of the lead frame. For example, the semiconductor package comprises: a lead frame; a semiconductor die which is disposed on the lead frame and is connected to the lead frame; and an encapsulant which covers the upsides of the semiconductor die and the lead frame and is formed to be interposed in the lead frame, wherein the lead frame includes a die pad on which the semiconductor die is placed, and a plurality of leads which extend in an outward direction parallel to the die pad from each side of the die pad, and the lead includes ...

SEMICONDUCTOR INTERPOSER, INTEGRATED CIRCUIT PACKAGE, AND METHOD FOR IMPROVING THE RELIABILITY OF A CONNECTION TO A VIA IN A SUBSTRATE

마주보는（ＦＡＣＥ­ＴＯ­ＦＡＣＥ, Ｆ2Ｆ） 하이브리드 구조를 갖는 집적 회로(ＩＣ), ＩＣ 조립체, ＩＣ 제품 및 이들을 제조하는 방법, 그리고 이를 위한 컴퓨터-판독가능 매체

... 재분배 층(RDL)을 포함하는 집적 회로(IC) 제품이 제공되며, 재분배 층(RDL)은 IC 내에서 전기적 정보를 하나의 위치로부터 또 하나의 위치로 분배하도록 구성된 적어도 하나의 전도성 층을 갖는다. RDL은 또한 복수의 와이어 본드 패드들 및 복수의 솔더 패드들을 포함한다. 복수의 솔더 패드들 각각은 RDL과 직접적으로 전기적 통신을 하는 솔더 가용성 물질을 포함한다.

METHOD FOR FORMING A CORELESS SUBSTRATE

... 전해 도금을 이용하는 코어리스 기판, 및 그들의 제품을 포함하는 전자 어셈블리가 기술된다. 한 방법은 금속을 포함하는 코어를 제공하는 단계, 및 코어 위에 유전 재료를 형성하는 단계를 포함한다. 이 방법은 또한 금속 영역을 노출하도록 배치되는 비아를 유전 재료에 형성하는 단계를 포함한다. 이 방법은 또한 비아 내에 그리고 금속 영역 위에 금속의 전해 도금을 수행하는 단계를 포함하고, 코어는 비아 내에의 전해 도금 동안에 전원에 전기적으로 결합되어 금속 영역에 전류를 전달한다. 이 방법은 또한 비아 내에의 금속의 전해 도금 이후에 금속 코어를 제거하는 단계를 포함한다. 다른 실시예들이 기술되고 청구된다.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Stacked semiconductor device package

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Methods of forming semiconductor chip underfill anchors

Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side.

Method of fabricating film circuit substrate and method of fabricating chip package including the same

A method of fabricating a film circuit substrate and a method of fabricating a chip package. The method of fabricating a film circuit substrate can include providing a base film including a chip packaging area to package a chip and a separation area to separate the two chip packaging areas from each other, the separation area including a cut area and an uncut area; forming a reserve interconnection pattern having a first height on the base film; and forming an interconnection pattern having a second height that is lower than the first height on the out area by selectively etching the reserve interconnection pattern of the cut area.

Semiconductor device, electronic apparatus, and method of manufacturing semiconductor device

A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin.

Semiconductor structure having conductive vias and method for manufacturing the same

A semiconductor structure includes a plurality of thermal vias and a heat dissipation layer disposed at a periphery of a back surface of a lower chip in a stacked-chip package. This arrangement improves solderability of a subsequently-bonded heat sink. Additionally, the thermal vias and the heat dissipation layer provide an improved thermal conduction path for enhancing heat dissipation efficiency of the semiconductor structure. A method for manufacturing the semiconductor structure is also provided.

Electronic component mounting method and electronic component mount structure

A challenge to be met by the present invention is to provide an electronic component mounting method and an electronic component mount structure that make it possible to assure bonding strength for an electronic component whose underside is provided with bumps. In electronic component mounting operation during which an electronic component ( 6 ) whose underside is provided with bumps ( 7 ) with solder is mounted on a substrate ( 1 ), a solder bonding material ( 3 ) including solder particles contained in a first thermosetting resin is used for bonding the bumps ( 7 ) to an electrode ( 2 ) formed on the substrate ( 1 ), thereby forming a solder bonding area ( 7 *) where the solder particles and the bumps ( 7 ) are fused and solidified and a first resin reinforcement area ( 3 a *) that reinforces the solder bonding area ( 7 *). Further, an adhesive ( 4 ) containing as a principal component a second thermosetting resin not including solder particles is used for fixing an outer edge ( 6 a ) of the electronic component ( 6 ) to reinforcement points set on the substrate ( 1 ). Even when the solder bonding material ( 3 ) and the bonding agent ( 4 ) are blended together, normal thermal curing of the thermosetting resin is not hindered. Bonding strength can thereby be assured for the electronic component ( 6 ) whose underside is provided with the bumps ( 7 ).

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

Package substrate unit and method for manufacturing package substrate unit

A semiconductor chip mounting layer of a package substrate unit includes an insulation layer, a conductive seed metal layer formed on the top surface of the insulation layer, conductive pads formed on the top surface of the conductive seed metal layer, metal posts formed substantially in the central portion on the top surface of the conductive pads, and a solder resist layer that is formed to surround the conductive pads and the metal posts.

Microsprings Partially Embedded In A Laminate Structure And Methods For Producing Same

At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.

Pass-through 3d interconnect for microelectronic dies and associated systems and methods

Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a substrate, a metal substrate pad, and a first integrated circuit electrically coupled to the substrate pad. A pass-through 3D interconnect extends between front and back sides of the substrate, including through the substrate pad. The pass-through interconnect is electrically isolated from the substrate pad and electrically coupled to a second integrated circuit of a second microelectronic die attached to the back side of the substrate. In another embodiment, the first integrated circuit is a first memory device and the second integrated circuit is a second memory device, and the system uses the pass-through interconnect as part of an independent communication path to the second memory device.

Integrated circuit packaging system with connection structure and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a connection post to the substrate, the connection post having a post top and a post side; mounting an integrated circuit die on the substrate, the integrated circuit die having a top die surface; and forming a package body on the substrate, the connection post, and the integrated circuit die.

Connecting and Bonding Adjacent Layers with Nanostructures

An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.

Lead pin for package substrate and semiconductor package printed circuit board including the same

Disclosed herein is a lead pin for a package substrate including a connection pin, and a head part including a flange part formed at one end of the connection pin and having one surface bonded to the connection pin and a flat part formed at the other surface of the flange part and having at least one groove formed along an outer circumference thereof. According to the present invention, the grooves are formed along the outer circumference of the flat part of the head part of the lead pin to increase a bonding area, thereby making it possible to increase bonding strength of the lead pin.

Semiconductor chip assembly and method for making same

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Semiconductor package and method of fabricating the same

A semiconductor package and a method of manufacturing the same, and more particularly, to a package of a power module semiconductor and a method of manufacturing the same. The semiconductor package includes a substrate including a plurality of conductive patterns spaced apart from one another; a plurality of semiconductor chips disposed on the conductive patterns; a connecting member for electrically connecting the conductive patterns to each other, for electrically connecting the semiconductor chips to each other, or for electrically connecting the conductive pattern and the semiconductor chip; and a sealing member for covering the substrate, the semiconductor chips, and the connecting member, wherein a lower surface of the substrate and an upper surface of the connecting member are exposed to the outside by the sealing member.

Packaging substrate with conductive structure

A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

Interposer

An interposer includes a substrate having a first surface and a second surface with vias extending between the first and second surfaces. The interposer also includes a contact array mounted to the first surface that has a plurality of coil-shaped contacts. The contacts have heels terminated to corresponding vias. The contacts have beams defining a mating interface of the interposer configured for mating with an electronic component. The contacts may be conic helix shaped. The beams may include at least one turn. The beams may be free standing from the heel and may be compressible along contact axes toward the first surface of the substrate.

Heatsink for led array light

A heatsink that includes a plurality of thermally conductive plates coupled to each other in a stacked configuration. Each plate includes a core section and a plurality of protrusions extending radially outwardly from the core section in a direction substantially parallel to the core section. The core section of each plate is in direct contact with the core section of an adjacent plate.

Compliant spring interposer for wafer level three dimensional (3d) integration and method of manufacturing

The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.

Semiconductor Package with Embedded Die

A semiconductor package having an embedded die and solid vertical interconnections, such as stud bump interconnections, for increased integration in the direction of the z-axis (i.e., in a direction normal to the circuit side of the die). The semiconductor package can include a die mounted in a face-up configuration (similar to a wire bond package) or in a face-down or flip chip configuration.

Electroconductive bonding material, method for bonding conductor, and method for manufacturing semiconductor device

An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

Wiring substrate and method of manufacturing the same

A wiring substrate includes a structure in which a plurality of wiring layers are stacked through insulating layers intervening therebetween, and which has a first surface side and a second surface side, the first surface side where a semiconductor element is to be mounted, the second surface side being located at an opposite side to the first surface side, an interposer buried in an outermost one of the insulating layers located at the first surface side, and electrically connected to the semiconductor element to be mounted, and a sheet-shaped member buried in an outermost one of the insulating layers located at the second surface side, wherein, the interposer and the sheet-shaped member are disposed at symmetrical positions symmetrical each other.

Pad structure, circuit carrier and integrated circuit chip

A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad.

Semiconductor package

A semiconductor package includes a plurality of connection pads, which are electrically connected to connection terminals of a mounted component that is mounted on the semiconductor package, and recognition marks. The recognition marks are formed respectively within the area of each of at least two of the connection pads. Each recognition mark has an area that is smaller than the area of the connection mark in which it is formed.

Module substrate, module-substrate manufacturing method, and terminal connection substrate

In a module substrate, a plurality of terminal connection substrates each including an insulator and a plurality of columnar terminal electrodes arranged on a single lateral surface or both lateral surfaces of the insulator is mounted on a single side of a composite substrate such that at least one of the terminal connection substrates extends over a border between a plurality of neighboring module substrates. The composite substrate, in which the plurality of terminal connection substrates is mounted on the single side and a plurality of electronic components is mounted on at least the single side, is divided at a location where the module substrates are to be cut from the composite substrate.

Method of manufacturing semiconductor device

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Bump-on-trace (bot) structures

A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

Circuit board, semiconductor device, process for manufacturing circuit board and process for manufacturing semiconductor device

A circuit board ( 1 ) exhibits an average coefficient of thermal expansion (A) of the first insulating layer ( 21 ) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point of equal to or higher than 3 ppm/degrees C. and equal to or lower than 30 ppm/degrees C. Further, an average coefficient of thermal expansion (B) of the second insulating layer ( 23 ) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point is equivalent to an average coefficient of thermal expansion (C) of the third insulating layer ( 25 ) in the direction along the substrate surface in a temperature range from 25 degrees C. to its glass transition point. (B) and (C) are larger than (A), and a difference between (A) and (B) and a difference between (A) and (C) are equal to or higher than 5 ppm/degrees C. and equal to or lower than 35 ppm/degrees C.

Power Module and Manufacturing Method Thereof

A power module includes a substrate having a surface on which a plurality of wiring patterns are formed, a semiconductor device mounted on the substrate and electrically connected to a part of the plurality of wiring patterns, and a terminal portion with a lead electrically connected to the other part of the plurality of wiring patterns, and is configured that the lead of the terminal portion is formed by laminating a plurality of metal members which contain a material substantially the same as or softer than the material for forming the other part of wiring patterns, and the material of the plurality of metal members, which is the same as or softer than the material for forming the other part of wiring patterns is electrically connected to the other part of wiring patterns through ultrasonic bonding.

Surface acoustic wave device and production method therefor

A surface acoustic wave device includes a surface acoustic wave element including a plurality of electrode pads, and a mount substrate. The surface acoustic wave element is flip-chip mounted on a die-attach surface of the mount substrate by bumps made of Au. The mount substrate includes at least one resin layer including via-holes, a plurality of mount electrodes provided on the die-attach surface of the mount substrate, and via-hole conductors. The mount electrodes are bonded to the electrode pads via the bumps. The via-hole conductors are provided in the via-holes. At least one of each of the electrode pads and each of the mount electrodes includes a front layer made of Au. At least one of the via-hole conductors is located below the corresponding bump.

Semiconductor Package and Method of Forming Z-Direction Conductive Posts Embedded in Structurally Protective Encapsulant

A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and temporary carrier are pressed together to embed the semiconductor die in the film encapsulant. The semiconductor die is disposed between the conductive posts in the film encapsulant. The temporary carrier and base plate of the post carrier are removed. A first circuit build-up layer is formed over a first side of the film encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. A second circuit build-up layer is formed over a second side of the film encapsulant opposite the first side. The second circuit build-up layer is electrically connected to the conductive posts. 1. A method of making a semiconductor device , comprising:providing a base plate including a plurality of conductive posts extending from the base plate;depositing a film encapsulant over the base plate and around the conductive posts;embedding a semiconductor die within the film encapsulant with major surfaces of the semiconductor die disposed within a height of the conductive posts;removing the base plate; andforming a first interconnect structure over a first surface of the film encapsulant, the first interconnect structure being electrically connected to the conductive posts.2. The method of claim 1 , further including forming a second interconnect structure over a second surface of the film encapsulant opposite the first surface of the film encapsulant.3. The method of claim 1 , further including planarizing the film encapsulant to the semiconductor die.4. The method of claim 1 , wherein depositing the film encapsulant includes:depositing a first film encapsulant over the base plate and around the conductive posts; anddepositing a second film encapsulant ...

Semiconductor Device and Method of Forming Conductive Posts Embedded in Photosensitive Encapsulant

A semiconductor package includes a post carrier having a base plate and plurality of conductive posts. A photosensitive encapsulant is deposited over the base plate of the post carrier and around the conductive posts. The photosensitive encapsulant is etched to expose a portion of the base plate of the post carrier. A semiconductor die is mounted to the base plate of the post carrier within the etched portions of the photosensitive encapsulant. A second encapsulant is deposited over the semiconductor die. A first circuit build-up layer is formed over the second encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. The base plate of the post carrier is removed and a second circuit build-up layer is formed over the semiconductor die and the photosensitive encapsulant opposite the first circuit build-up layer. The second circuit build-up layer is electrically connected to the conductive posts. 1. A method of making a semiconductor device , comprising:providing a substrate including a plurality of conductive posts extending from the substrate;disposing a photosensitive material over the substrate and around the conductive posts;forming an opening in the photosensitive material to expose a portion of the substrate between the conductive posts;disposing a semiconductor die over the substrate within the opening in the photosensitive material; anddepositing an encapsulant over the semiconductor die within the opening in the photosensitive material.2. The method of claim 1 , further including forming a first interconnect structure over the photosensitive material and encapsulant claim 1 , the first interconnect structure being electrically connected to the conductive posts.3. The method of claim 2 , further including forming a second interconnect structure over the photosensitive material and encapsulant opposite the first interconnect structure.4. The method of claim 1 , further including planarizing the photosensitive material and ...

Semiconductor Device and Method of Forming Different Height Conductive Pillars to Electrically Interconnect Stacked Laterally Offset Semiconductor Die

A semiconductor device has a first semiconductor die mounted over a carrier. Wettable contact pads can be formed over the carrier. A second semiconductor die is mounted over the first semiconductor die. The second die is laterally offset with respect to the first die. An electrical interconnect is formed between an overlapping portion of the first die and second die. A plurality of first conductive pillars is disposed over the first die. A plurality of second conductive pillars is disposed over the second die. An encapsulant is deposited over the first and second die and first and second conductive pillars. A first interconnect structure is formed over the encapsulant, first conductive pillars, and second die. The carrier is removed. A second interconnect structure is formed over the encapsulant, second conductive pillars, and first die. A third conductive pillar is formed between the first and second build-up interconnect structures. 1. A semiconductor device , comprising:a first semiconductor die;a second semiconductor die disposed over a portion of the first semiconductor die and laterally offset from the first semiconductor die;a plurality of first conductive pillars disposed over the first semiconductor die or second semiconductor die; andan encapsulant deposited around the first semiconductor die and second semiconductor die and first conductive pillars.2. The semiconductor device of claim 1 , further including an electrical interconnect formed between an overlapping portion of the first semiconductor die and second semiconductor die.3. The semiconductor device of claim 2 , wherein the electrical interconnect includes a bump claim 2 , stud bump claim 2 , or second conductive pillar.4. The semiconductor device of claim 1 , further including a plurality of second conductive pillars disposed around the first semiconductor die or second semiconductor die.5. The semiconductor device of claim 1 , further including an interconnect structure formed over the ...

Integrated circuit packaging system with external wire connection and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a package carrier; mounting an integrated circuit to the package carrier; forming an external wire on the package carrier and adjacent to the integrated circuit; forming an encapsulation on the package carrier over the external wire; and forming a hole in the encapsulation with the external wire and a portion of the package carrier exposed from the encapsulation.

Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

Integrated circuit packaging system with encapsulation and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base integrated circuit on the base substrate; forming a base encapsulation, having a base encapsulation top side, on the base substrate and around the base integrated circuit; forming a base conductive via, having a base via head, through the base encapsulation and attached to the base substrate adjacent to the base integrated circuit, the base via head exposed from and coplanar with the base encapsulation top side; mounting an interposer structure over the base encapsulation with the interposer structure connected to the base via head; and forming an upper encapsulation on the base encapsulation top side and partially surrounding the interposer structure with a side of the interposer structure facing away from the base encapsulation exposed.

Semiconductor package including an integrated waveguide

Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.

Power semiconductor arrangement and method for producing a power semiconductor arrangement

In a method for producing a power semiconductor arrangement, an insulation carrier with a top side, a metallization, and a contact pin with a first end are provided. The metallization is attached to the top side and a target section of the metallization is determined. After the metallization is attached to the top side of the insulation carrier, the first end of the contact pin is pressed into the target section such that the first end is inserted in the target section. Thereby, an interference fit and an electrical connection are established between the first end of the contact pin and the target section of the metallization.

Interposer, circuit board module, and method for manufacturing interposer

An interposer includes a substrate having first and second opposing surfaces, the substrate having a sheet shape; and a plurality of spring electrodes fixed to the substrate in a certain arrangement, each of the plurality of the spring electrodes including a first pad disposed opposite the first surface of the mesh and extending in a first direction, a second pad disposed opposite the second surface of the mesh and extending in the first direction, and a post extending through the substrate between the first and second surfaces and connecting an end of the first pad to an end of the second pad.

Semiconductor Device and Method of Forming Bump on Substrate to Prevent ELK ILD Delamination During Reflow Process

A semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer. 1. A semiconductor device , comprising:a substrate;a first insulating layer formed over the substrate including an opening extending through the first insulating layer to the substrate;a first bump material disposed in the opening and electrically connected to the substrate; anda semiconductor die disposed over the substrate and electrically connected to the first bump material.2. The semiconductor device of claim 1 , further including:a second insulating layer formed over the first insulating layer including an opening extending through the second insulating layer to the first bump material; anda second bump material disposed within the opening in the second insulating layer over the first bump material.3. The semiconductor device of claim 1 , further including a second bump material disposed over the first bump material.4. The semiconductor device of claim 3 , wherein the first bump material includes a non-fusible material and the second bump material includes a fusible material.5. The semiconductor device of claim 1 , wherein the first bump material includes a conductive pillar or stacked ...

SEMICONDUCTOR DEVICE, ELECTRODE MEMBER, AND ELECTRODE MEMBER FABRICATION METHOD

A semiconductor device that improves the heat cycle resistance and power cycle resistance of a power module. An electrode member in which copper posts are formed in a plurality of perforations cut in a support made of a ceramic material is soldered onto a side of an IGBT where an emitter electrode is formed. By soldering the copper posts onto the electrode, heat generated in the IGBT is transferred to the electrode member and is radiated. In addition, even if a material of which the IGBT is made and copper differ in thermal expansivity, stress on a soldered interface is reduced and distortion is reduced. This suppresses the appearance of a crack. As a result, the heat cycle resistance and power cycle resistance of a power module can be improved. 1. A semiconductor device having a semiconductor element with an electrode on a surface , the device comprising an electrode member including:a plurality of first holes made in one principal plane of an insulating support;first metal posts located in the plurality of first holes;a plurality of second holes made in another principal of the insulating support; andsecond metal posts which are located in the plurality of second holes and which are electrically insulated from the first metal posts,wherein at least one of the first metal posts and the second metal posts are joined to the electrode.2. The semiconductor device according to claim 1 , wherein a conductor layer is formed on a principal plane of the electrode member joined to the electrode.3. The semiconductor device according to claim 1 , wherein in the electrode member claim 1 , end portions of the first and second metal posts protrude from at least one principal plane of the insulating support.4. The semiconductor device according to claim 3 , wherein a cooling medium is configured to be passed between the first and second metal posts which protrude from the insulating support and a surface in which the first and second metal posts are joined to the electrode.5. An ...

SEMICONDUCTOR DEVICE AND STACKED SEMICONDUCTOR DEVICE

A semiconductor device according to one embodiment has a wiring circuit board, a semiconductor chip, a die attach material and bumps. The semiconductor chip is mounted on the wiring circuit board. The die attach material is provided between the wiring circuit board and the semiconductor chip. A wiring layer is provided on one surface of the wiring circuit board. Leads are extended from the wiring layer and connected to the semiconductor chip. The bumps are provided at outer positions relative to the region where the semiconductor chip of the wiring circuit board is mounted. The wiring layer in the wiring circuit board is formed on the surface opposite from the surface on which the semiconductor chip is mounted. 1. A semiconductor device comprising:a first core member including a first surface and a second surface opposite to the first surface;a first semiconductor chip mounted over the first surface of the first core member;a plurality of first bumps provided on the second surface of the first core member;a second core member including a third surface and a fourth surface opposite to the third surface, the second core member being stacked over the first semiconductor chip so that the fourth surface faces the first semiconductor chip;a second semiconductor chip mounted over the third surface of the second core member; anda plurality of second bumps provided on the fourth surface of the second core member, the plurality of second bumps being arranged at positions that are outside of a region overlapping the first semiconductor chip, and the plurality of second bumps are smaller in diameter than the plurality of first bumps.2. The semiconductor device as claimed in claim 1 , wherein the second semiconductor chip is electrically coupled to the first bumps via the second bumps.3. The semiconductor device as claimed in claim 1 , wherein the second bumps are arranged at positions that are overlapped to the first bumps in plan view.4. The semiconductor device as claimed in ...

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

SEMICONDUCTOR DEVICE

A semiconductor device suitable for preventing malfunction is provided. 1. A semiconductor device comprising:a semiconductor chip;a first electrode pad laminated on the semiconductor chip;an intermediate layer having a rectangular shape defined by a first edge and a second edge; anda plurality of bumps arranged to sandwich the intermediate layer by cooperating with the semiconductor chip;wherein the first edge extends in a first direction crossing a thickness direction of the semiconductor chip, the second edge extends in a second direction crossing both of the thickness direction and the first direction, the plurality of bumps include a first bump electrically connected to the first electrode pad, the plurality of bumps include a second bump electrically connected to the first electrode pad, and the first bump is arranged at one end in the first direction and one end in the second direction.2. The semiconductor device according to claim 1 , further comprising a second electrode pad laminated on the semiconductor chip claim 1 ,wherein the semiconductor chip includes a wiring layer for electrically connecting the first electrode pad and the second electrode pad to each other, and the second bump is electrically connected to the first electrode pad via the second electrode pad.3. The semiconductor device according to claim 2 , further comprising a coating film that exposes the first electrode pad and the second electrode pad claim 2 ,wherein the intermediate layer includes a stress buffer layer laminated on the coating film, a first re-distribution layer laminated on the stress buffer layer and a second re-distribution layer laminated on the stress buffer layer, the first re-distribution layer includes a portion that overlaps the first bump as viewed in the thickness direction, the second re-distribution layer includes a portion that overlaps the second bump as viewed in the thickness direction, and the first re-distribution layer and the second re-distribution layer ...

FLIP CHIP PACKAGES WITH IMPROVED THERMAL PERFORMANCE

Systems and methods for improving thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity. 1. A package comprising:a substrate configured to support a flip chip die, the flip chip die including a first surface mounted on the substrate and a second surface; anda thermal collection layer formed on the second surface of the flip chip die, the thermal collection layer configured to dissipate heat generated by the flip chip die.2. The package of further comprising a plurality of bump connections interposed between the substrate and the first surface of the flip chip die.3. The package of wherein the plurality of bump connections include copper.4. The package of wherein the second surface of the flip chip die is opposite the first surface of the flip chip die.5. The package of further comprising a second die interposed between the flip chip die and the substrate.6. The package of further comprising a mold configured to protect the flip chip die and enclose a plurality of exposed surfaces of the flip chip die.7. The package of wherein the thermal collection layer includes copper.8. A multi-chip package comprising:a substrate configured to support a plurality of flip chip dies, each flip chip die from the plurality of flip chip dies including a first surface mounted on the substrate and a second surface; anda thermal collection layer formed on the second surface of each flip chip die from the plurality of flip chip dies, the thermal collection layer configured to dissipate heat generated by the plurality of flip chip dies.9. The package of further comprising a plurality of bump connections interposed ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a wiring board, a semiconductor chip mounted on the wiring board, the semiconductor chip including a bump formation surface, a plurality of first bumps provided within a first region of the bump formation surface, the first bumps being arranged in a first area density, a plurality of second bumps provided within a second region of the bump formation surface, the second bumps being arranged in a second area density, and a plurality of third bumps arranged between the first region and the second region of the bump formation surface in a two-dimensional array. The plurality of third bumps are arranged in a third area density being higher than the second area density and being lower than the first area density. 1. A semiconductor device comprising:a wiring board;a semiconductor chip mounted on the wiring board, the semiconductor chip including a bump formation surface;a plurality of first bumps provided within a first region of the bump formation surface, the first bumps being arranged in a first area density;a plurality of second bumps provided within a second region of the bump formation surface, the second bumps being arranged in a second area density; anda plurality of third bumps arranged between the first region and the second region of the bump formation surface in a two-dimensional array,wherein the plurality of third bumps are arranged in a third area density being higher than the second area density and being lower than the first area density.2. The semiconductor device according to claim 1 , wherein said wiring board includes an electrode terminal group claim 1 , and said semiconductor chip is mounted on said wiring board so that a bump group faces said electrode terminal group.3. The semiconductor device according to claims 1 , wherein a number of the bumps formed per unit area in said third region is larger than a number of the bumps formed per unit area in said second region claims 1 , and is smaller than a number of the ...

Method for Stacking Devices and Structure Thereof

A semiconductor device that has a first device that includes a first through-silicon via (TSV) structure, a first coating material disposed over the first device, the first coating material continuously extending over the first device and covering the first TSV structure, a second device disposed over the first device and within the first coating material, the second device includes a second TSV structure and a plurality of conductive bumps, the plurality of conductive bumps are positioned within the first coating material, a second coating material disposed over the second device, the second coating material continuously extends over the second device and covers the second TSV structure, and a third device disposed over the second coating material, the third device includes a third TSV structure. 1. A semiconductor device comprising:a first device including a first plurality of conductive bumps;a second device including a second plurality of conductive bumps, the second device overlying the first device and electrically coupled to the first device;a third device including a third plurality of conductive bumps, the third device overlying the second device and electrically coupled to the second device;a first coating material disposed between the first and second devices, wherein the first coating material continuously covers a surface area between and surrounding the second plurality of conductive bumps, and wherein a wall of the first coating material is in direct contact with a wall of the second plurality of conductive bumps; anda second coating material disposed between the second and third devices, wherein the second coating material continuously covers a surface area between and surrounding the third plurality of conductive bumps, and wherein a wall of the second coating material is in direct contact with a wall of the third plurality of conductive bumps.2. The semiconductor device of claim 1 , wherein the first and second coating materials are configured with ...

Semiconductor device and manufacturing method therefor

A semiconductor device includes a substrate having a main surface and a back surface opposite to the main surface, a first semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the first semiconductor chip being mounted on the main surface of the substrate, a plurality of bumps provided between the main surface of the substrate and the lower surface of the first semiconductor chip, a second semiconductor chip having an upper surface and a lower surface opposite to the first surface with a side surface provided therebetween, the second semiconductor chip being mounted on the upper surface of the first semiconductor chip such that the side surface of the second semiconductor chip is positioned outward from the side surface of the first semiconductor chip.

WINDOW BALL GRID ARRAY (BGA) SEMICONDUCTOR PACKAGES

A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate. 1a substrate having (i) a first surface, (ii) a second surface that is opposite to the first surface, and (iii) an opening formed between the first surface of the substrate and the second surface of the substrate;a semiconductor die having (i) a first surface and (ii) a second surface that is opposite to the first surface, the first surface of the semiconductor die being electrically coupled to the second surface of the substrate by one or more interconnect bumps;one or more bonding wires that electrically couple the first surface of the semiconductor die to the first surface of the substrate through the opening of the substrate; anda first electrically insulative structure disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and the one or more interconnect bumps, wherein the first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate.. A semiconductor package comprising: The present disclosure is a continuation of and claims priority to U.S. patent application ...

Stacked Seminconductor Package

Provided is a stacked semiconductor package. The stacked semiconductor package of the present invention comprises: a substrate including at least one contact pad; an external chip laminate which includes a plurality of semiconductor chips mounted on the substrate, and which is stacked in multi-steps such that the ends at one side of the plurality of semiconductor chips alternately protrude in opposite directions to expose bonding pads which are formed on the up-face surface; at least one internal chip which is disposed in a mounting space formed between the external chip laminate and substrate so as to be electrically connected to the substrate; and a conductive wire electrically connecting the bonding pad of the semiconductor chip and the contact pad of the substrate. 1. A stacked semiconductor package , comprising:a substrate having at least one contact pad;an external chip laminate comprising a plurality of semiconductor chips stacked on the substrate, in which one end of each of the plurality of semiconductor chips is alternately protruded in opposite directions so that bonding pads formed on face-up surfaces thereof are externally exposed;at least one internal chip disposed in a mounting space formed between the external chip laminate and the substrate so that the internal chip is electrically connected to the substrate; anda conductive wire which electrically connects the bonding pads of the semiconductor chips and the contact pad of the substrate.2. The stacked semiconductor package of claim 1 , wherein the external chip laminate is provided in a stack structure in which an overlapping region between the semiconductor chips which are vertically stacked gradually increases upwards and a width thereof gradually decreases upwards.3. The stacked semiconductor package of claim 1 , wherein the external chip laminate includes a support member so as to support free ends of the semiconductor chips having the bonding pads which are wire-bonded with the conductive wire. ...

Semiconductor package

Disclosed herein is a semiconductor package. The semiconductor package includes: a substrate having a semiconductor device mounted on a top portion thereof; a housing surrounding the semiconductor device and the substrate so as to isolate them from the outside; at least one lead frame disposed on the top portion of the substrate while being spaced apart from one another; and a clip electrically connecting the substrate with at least one lead frame.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

In one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first and second semiconductor chips are electrically connected via first bump connection parts. Stopper projections and bonding projections are provided at least one of the first and second semiconductor chips. The stopper projections are in contact with the other of the first and second semiconductor chips in an unbonded state. The bonding projections are bonded to the first and second semiconductor chips. 1. A semiconductor device , comprising:a first semiconductor chip having a first surface including a first connection region and a first non-connection region excluding the first connection region;a second semiconductor chip having a second surface including a second connection region facing the first connection region and a second non-connection region excluding the second connection region, and stacked on the first semiconductor chip;first bump connection parts provided the first connection region of the first surface and the second connection region of the second surface to electrically connect between the first semiconductor chip and the second semiconductor chip;first stopper projections locally provided at least one region of the first non-connection region of the first surface and the second non-connection region of the second surface, and being in contact with the other region of the first non-connection region and the second non-connection region in an unbonded state;first bonding projections locally provided between the first non-connection region of the first surface and the second non-connection region of the second surface, and bonded to the first and second surfaces; anda first resin filled into a gap between the first surface of the first semiconductor chip and the second surface of the second semiconductor chip.2. The semiconductor device according to claim 1 , further comprising:a third ...

Semiconductor Device Having Vertically Offset Bond on Trace Interconnects on Recessed and Raised Bond Fingers

A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer. 1. A semiconductor device , comprising:a substrate;a first conductive layer embedded in a first surface of the substrate;a second conductive layer extending above the first surface of the substrate to create a vertical offset between the first conductive layer and second conductive layer; anda first interconnect structure formed over the first conductive layer and second conductive layer.2. The semiconductor device of claim 1 , wherein the first interconnect structure includes a bump or conductive post.3. The semiconductor device of claim 1 , further including:a third conductive layer embedded in a second surface of the substrate opposite the first surface of the substrate;a fourth conductive layer extending above the second surface of the substrate; anda second interconnect structure formed over the third conductive layer and fourth conductive layer.4. The semiconductor device of claim 1 , wherein the vertical offset between the first conductive layer and second conductive layer is about 20 micrometers.5. The semiconductor device of claim 1 , ...

MICROELECTRONIC PACKAGE WITH SELF-HEATING INTERCONNECT

A microelectronic package is provided. The microelectronic package includes a substrate having a plurality of solder bumps disposed on a top side of the substrate anda die disposed adjacent to the top side of the substrate. The die includes a plurality of glassy metal bumps disposed on a bottom side of the die wherein the plurality of glassy metal bumps are to melt the plurality of solder bumps to form a liquid solder layer. The liquid solder layer is to attach the die with the substrate. 1. A microelectronic package , comprising:a substrate having a plurality of solder bumps disposed on a top side of the substrate; anda die disposed adjacent to the top side of the substrate, wherein the die comprises a plurality of glassy metal bumps disposed on a bottom side of the die and wherein the plurality of glassy metal bumps are to melt the plurality of solder bumps to form a liquid solder layer, wherein the liquid solder layer is to attach the die with the substrate.2. The microelectronic package of claim 1 , wherein the plurality of glassy metal bumps are to generate heat through exothermic crystallization to melt the plurality of solder bumps.3. The microelectronic package of claim 1 , wherein the die is attached to the substrate at a temperature greater than a glass transition temperature of the plurality of glassy metal bumps.4. The microelectronic package of claim 1 , further comprising an insulating layer disposed between adjacent glassy metal bumps.5. The microelectronic package of claim 1 , further comprising a wettable metal disposed on each of the plurality of glassy metal bumps.6. The microelectronic package of claim 5 , wherein the wettable metal comprises copper.7. The microelectronic package of claim 5 , wherein the wettable metal comprises nickel.8. The microelectronic package of claim 1 , wherein each of the plurality of glassy metal bumps has a glass transition temperature of less than about 200° C.9. The microelectronic package of claim 1 , wherein each ...

WIRING SUBSTRATE, MANUFACTURING METHOD OF WIRING SUBSTRATE, AND SEMICONDUCTOR PACKAGE INCLUDING WIRING SUBSTRATE

A wiring substrate includes an insulating layer having a first surface on which a projecting part is formed, and an electrode pad being formed on the projecting part and including a first electrode pad surface and a second electrode pad surface on a side opposite to the first electrode pad surface. The first electrode pad surface is exposed from the projecting part of the insulating layer. The second electrode pad surface is covered by the insulating layer. A cross-section of the projecting part is a tapered shape. One side of the cross-section toward the first electrode pad surface is narrower than another side of the cross-section toward the first surface of the insulating layer. 1. A wiring substrate comprising:an insulating layer having a first surface on which a projecting part is formed; andan electrode pad being formed on the projecting part and including a first electrode pad surface and a second electrode pad surface on a side opposite to the first electrode pad surface;wherein the first electrode pad surface is exposed from the projecting part of the insulating layer,wherein the second electrode pad surface is covered by the insulating layer,wherein a cross-section of the projecting part is a tapered shape,wherein one side of the cross-section toward the first electrode pad surface is narrower than another side of the cross-section toward the first surface of the insulating layer.2. The wiring substrate as claimed in claim 1 , wherein a via wiring is connected to the second electrode pad surface.3. The wiring substrate as claimed in claim 2 , further comprising:a through-hole formed in the insulating layer, the through-hole penetrating the insulating layer, exposing the second electrode pad surface, and having the via wiring formed therein;a metal layer extending from the through-hole to a second surface of the insulating layer opposite to the first surface of the insulating layer;wherein the metal layer includes the via wiring formed in the through-hole ...

METHOD FOR FORMING AN INTEGRATED CIRCUIT

A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 μm, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material. 1. A method for forming an integrated circuit having a surface capable of being placed on another integrated circuit , on a printed circuit , or on a package , and having its other surface capable of receiving an additional integrated circuit , the method comprising the steps of:a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 μm, and filling them with a conductive material;b) forming doped areas of components in active areas of the front surface, forming interconnection levels) on said front surface and leveling said surface supporting the interconnection levels;c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling said surface coated with an insulator;d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers;e) forming vias from the rear surface of the second wafer, to reach the ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a first substrate; a plurality of first electrodes formed on the first substrate; and a first insulating film formed on sidewalls of the plurality of first electrodes. The first insulating film is formed not to fill spaces between the plurality of first electrodes. 1. A semiconductor device , comprising:a first substrate;a plurality of first electrodes formed on the first substrate, and including a solder bump as an upper layer; anda first insulating film formed on sidewalls of the plurality of first electrodes, whereinthe first insulating film is formed not to fill spaces between the plurality of first electrodes.2. The semiconductor device of claim 1 , wherein a first conductive layer containing a first metal, and', 'a second conductive layer formed on the first conductive layer, and containing a second metal different from the first metal., 'the plurality of first electrodes include'}3. The semiconductor device of claim 2 , whereinthe first metal is copper, andthe second metal is tin.4. The semiconductor device of claim 2 , whereinthe plurality of first electrodes further include a barrier layer under the first conductive layer.5. The semiconductor device of claim 4 , whereinthe barrier layer contains titanium.6. The semiconductor device of claim 1 , whereinthe first insulating film is an oxide film or an organic film.7. The semiconductor device of claim 1 , further comprising:a second substrate;a plurality of second electrodes formed on the second substrate in positions corresponding to the plurality of first electrodes on the first substrate; anda second insulating film formed on sidewalls of the plurality of second electrodes, whereinthe second insulating film is formed not to fill spaces between the plurality of second electrodes,the first substrate and the second substrate are arranged so that the plurality of first electrodes face the corresponding plurality of second electrodes, andthe plurality of first electrodes are ...

Structure for Reducing Integrated Circuit Corner Peeling

A crack prevention structure that reduces integrated circuit corner peeling and reduces cracking is disclosed. The crack prevention structure comprises a semiconductor substrate; a first plurality of dielectric layers of a first material disposed over the semiconductor substrate; a second plurality of dielectric layers of a second material different than the first material, disposed on the first plurality of dielectric layers, wherein the first plurality of dielectric layers and the second plurality of dielectric layers meet at an interface; and a plurality of metal structures and a plurality of via structures formed through the interface of the first plurality of dielectric layers and the second plurality of dielectric layers. 1. A device comprising: a first plurality of dielectric layers of a first material disposed over the semiconductor substrate;', 'a second plurality of dielectric layers of a second material different than the first material disposed over the first plurality of dielectric layers, wherein the first plurality of dielectric layers and the second plurality of dielectric layers meet at an interface;', 'a plurality of metal structures and a plurality of via structures formed through the interface of the first plurality of dielectric layers and the second plurality of dielectric layers; and', 'a bond/bump pad structure disposed in a passivation layer overlying the first and second plurality of dielectric layers, the bond/bump pad structure being coupled with a topmost metal structure of the plurality of metal structures., 'a plurality of semiconductor dies disposed between scribe lines, wherein the scribe lines include at least one crack prevention structure disposed over a semiconductor substrate, the at least one crack prevention structure comprising2. The device of claim 1 , further comprising a seal ring disposed between one of the semiconductor dies and the at least one crack prevention structure.3. The device of claim 1 , wherein the at least ...

SEMICONDUCTOR DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS WITHOUT OCCURRING OF CRACK

A device includes first and second semiconductor chips. The first semiconductor chip includes an edge defining a periphery of the first semiconductor chip. The second semiconductor chip is greater in size than the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip so that the second semiconductor chip hangs over from the edge of the first semiconductor chip. The second semiconductor chip includes a plurality of wiring patterns including a first wiring pattern that positions over the edge of the first semiconductor chip, an insulating film which covers the wiring patterns and which includes on or more holes that expose one or more the wiring patterns, and one or more bump electrodes formed on the one or more the wiring patterns. Remaining one or ones of the wiring patterns is kept covered by the insulating layer and includes the first wiring pattern. 1. A device comprising:a first semiconductor chip including an edge defining a periphery of the first semiconductor chip; anda second semiconductor chip that is greater in size than the first semiconductor chip, the second semiconductor chip being stacked over the first semiconductor chip so that the second semiconductor chip hangs over from the edge of the first semiconductor chip; a plurality of upper layer wiring patterns including a first wiring pattern that positions over the edge of the first semiconductor chip;', 'a first insulating film covering the upper layer wiring patterns, the first insulating film including one or more holes that expose at least a part of one or more the upper layer wiring patterns; and', 'one or more main surface bump electrodes formed on the one or more the upper layer wiring patterns, remaining one or ones of the upper layer wiring patterns being kept covered by the first insulating layer, the remaining one or ones of the upper layer wiring patterns including the first wiring pattern., 'the second semiconductor chip comprising;'}2. The ...

MULTI-CHIP PACKAGE HAVING A STACKED PLURALITY OF DIFFERENT SIZED SEMICONDUCTOR CHIPS, AND METHOD OF MANUFACTURING THE SAME

Provided is a multi-chip package in which a plurality of semiconductor chips having different sizes are stacked. A multi-chip package may include a substrate, and a plurality of semiconductor chips stacked on the substrate, each of the plurality of semiconductor chips having a different size. Each of the plurality of semiconductor chips including a pad group and a reference region associated with the pad group, each pad group having a plurality of pads, and the plurality of pads in each pad group located at same coordinates with respect to the associated reference region, and each of the plurality of semiconductor chips having their reference regions vertically aligned. 1. A semiconductor device comprising:a first chip; andat least one chip stacked on the first chip, the at least one chip having a different size from the first chip,wherein each of the first chip and the at least one chip has a plurality of pads at center portion, and the first chip and the at least one chip are electrically connected to each other using the pads vertically aligned.2. The semiconductor device of claim 1 , wherein the plurality of pads are formed in a through via hole.3. The semiconductor device of claim 1 , wherein the at least one chip comprises a plurality of chips claim 1 , and the plurality of chips have a different size from each other.4. The semiconductor device of claim 1 , wherein at least a portion of the plurality of pads is arranged at a same distance from each other.5. The semiconductor device of claim 1 , wherein the plurality of pads are arranged in the same arrangement order in each of the first chip and the at least one chip.6. The semiconductor device of claim 1 , wherein the first chip and the at least one chip are electrically connected to each other by bumps disposed on the plurality of pads.7. The semiconductor device of claim 1 , further comprising:a substrate on which the first chip and the at least one chip are stacked.8. The semiconductor device of claim 7 , ...

Semiconductor Device and Method of Forming Adjacent Channel and Dam Material Around Die Attach Area of Substrate to Control Outward Flow of Underfill Material

A semiconductor device has a flipchip or PoP semiconductor die mounted to a die attach area interior to a substrate. The substrate has a contact pad area around the die attach area and flow control area between the die attach area and contact pad area. A first channel is formed in a surface of the substrate within the flow control area. The first channel extends around a periphery of the die attach area. A first dam material is formed adjacent to the first channel within the flow control area. An underfill material is deposited between the die and substrate. The first channel and first dam material control outward flow of the underfill material to prevent excess underfill material from covering the contact pad area. A second channel can be formed adjacent to the first dam material. A second dam material can be formed adjacent to the first channel. 1. A method of making a semiconductor device , comprising:providing a substrate including a die attach area;forming a first channel in the substrate;forming a first dam material over the substrate;disposing a semiconductor die over the die attach area of the substrate; anddepositing an underfill material between the semiconductor die and substrate, wherein the first channel and first dam material control outward flow of excess underfill material.2. The method of claim 1 , further including forming the first dam material between the first channel and a contact pad area of the substrate.3. The method of claim 2 , further including forming a second channel between the first dam material and the contact pad area of the substrate.4. The method of claim 1 , further including forming the first dam material between the first channel and die attach area.5. The method of claim 4 , further including forming a second dam material between the first channel and a contact pad area of the substrate.6. The method of claim 1 , wherein the semiconductor die is a flipchip type semiconductor die or package-on-package semiconductor device.7. A ...

BUMP INCLUDING DIFFUSION BARRIER BI-LAYER AND MANUFACTURING METHOD THEREOF

Provided herein is a bump including a diffusion barrier bi-layer, the bump having: a conductive layer; a first diffusion barrier layer formed on or above the conductive layer, and comprising an alloy of nickel and phosphorus; a second diffusion barrier formed on or above the first diffusion barrier layer, and comprising copper; and a solder layer formed on or above the second diffusion barrier layer. A manufacturing method for producing a bump is also provided. 1. A bump including a diffusion bather bi-layer , the bump comprising:a conductive layer;a first diffusion barrier layer formed on or above the conductive layer, and comprising an alloy of nickel and phosphorus;a second diffusion barrier formed on or above the first diffusion barrier layer, and comprising copper; anda solder layer formed on or above the second diffusion barrier layer.2. The bump according to claim 1 , wherein the bump is formed in a semiconductor 3D stacking process.3. The bump according to claim 1 , wherein a thickness ratio of the first diffusion barrier layer and the second diffusion barrier layer ranges from 1.2:1 to 2.5:1.4. The bump according to claim 1 , wherein a thickness of the first diffusion barrier layer ranges from 0.8 μm to 1.6 μm claim 1 , and a thickness of the second diffusion barrier layer ranges from 0.4 μm to 0.8 μm.5. The bump according to claim 3 , wherein a thickness of the first diffusion barrier layer ranges from 0.8 μm to 1.6 μm claim 3 , and a thickness of the second diffusion barrier layer ranges from 0.4 μm to 0.8 μm.6. The bump according to claim 1 , wherein the conductive layer comprises copper (Cu) claim 1 , and the solder layer comprises tin (Sn).7. The bump according to claim 3 , wherein the conductive layer comprises copper (Cu) claim 3 , and the solder layer comprises tin (Sn).8. The bump according to claim 1 , wherein a thickness of the conductive layer ranges from 20 μm to 60 μm claim 1 , and a thickness of the solder layer ranges from 3 μm to 10 μm.9. ...

Semiconductor Device and Method of Forming Interconnect Structure with Conductive Pads Having Expanded Interconnect Surface Area for Enhanced Interconnection Properties

A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a plurality of conductive pads over the substrate; andexpanding an interconnect surface area of the conductive pads by forming a plurality of recesses partially into the conductive pads while retaining a portion of the conductive pads under the recesses.2. The method of claim 1 , further including:forming an insulating layer with patterned openings disposed over the conductive pads; andforming the recesses through a surface of the conductive pads within the patterned openings of the insulating layer.3. The method of claim 2 , wherein the patterned openings include ring openings claim 2 , circular openings claim 2 , or linear openings.4. The method of claim 1 , further including:forming a first conductive layer over the substrate;forming an insulating layer over the substrate;forming a second conductive layer over the first conductive layer; andforming the conductive pads over the second conductive layer.5. The method of claim 1 , further ...

SEMICONDUCTOR CHIP WITH UNDERFILL ANCHORS

Various semiconductor chips and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in an insulating layer applied to a side of a semiconductor chip. The first opening does not extend through to the side. A second opening is formed in the insulating layer that exposes a portion of the side. 1. An apparatus , comprising:a semiconductor chip including a side and plural solder structures to enable semiconductor the semiconductor chip to flip-chip mounted to a circuit board;a first insulating layer on the side;a second insulating layer on the first insulating layer and including a first opening that does not extend through to the first insulating layer and a second opening that extends at least to the first insulating layer.2. The apparatus of claim 1 , comprising an underfill on the second insulating layer including a projection positioned in the first opening.3. The apparatus of claim 1 , comprising plural second openings that extend at least to the first insulating layer and wherein each of the solder structures includes a portion positioned in corresponding of the second openings.4. The apparatus of claim 3 , wherein the semiconductor chip includes plural conductor pads claim 3 , each of the second openings extending to one of the conductor pads.5. The apparatus of claim 1 , comprising a circuit board coupled to the semiconductor chip.6. The apparatus of claim 4 , comprising an underfill positioned between the semiconductor chip and the circuit board and including a projection positioned in the first opening.7. The apparatus of claim 4 , wherein the circuit board comprises a package substrate.8. The apparatus of claim 6 , wherein the circuit board includes a solder resist layer facing the semiconductor chip.9. The apparatus of claim 1 , wherein the second insulating layer comprises a photoactive compound.10. The apparatus of claim 1 , comprising a conductor pad claim 1 , the second ...

Semiconductor device, semiconductor package, and method for manufacturing semiconductor device

A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first surface, a second surface, and a through hole that extends through the semiconductor substrate from the first surface to the second surface. An insulating layer covers the first surface and includes an opening at a location facing the through hole. An insulating film covers an inner wall of the through hole and an inner wall of the opening. A through electrode is formed in the through hole and the opening that are covered by the insulating film. A first connecting terminal is formed integrally with the through electrode to cover one end of the through electrode exposed from the insulating layer. The first connecting terminal has a larger size than the through electrode as viewed from above.

SEMICONDUCTOR CHIP WITH OFFSET PADS

A semiconductor chip device includes a first semiconductor chip adapted to be stacked with a second semiconductor chip wherein the second semiconductor chip includes a side and first and second conductor structures projecting from the side. The first semiconductor chip includes a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and that has a first lateral dimension and is adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and that has a second lateral dimension larger than the first lateral dimension and is adapted to couple to the other of the first and second conductor structures. 1. An apparatus , comprising:a first semiconductor chip adapted to be stacked with a second semiconductor chip, the second semiconductor chip including a side and first and second conductor structures projecting from the side; andthe first semiconductor chip including a first edge, a first conductor pad, a first conductor pillar positioned on but laterally offset from the first conductor pad toward the first edge and having a first lateral dimension and being adapted to couple to one of the first and second conductor structures, a second conductor pad positioned nearer the first edge than the first conductor pad, and a second conductor pillar positioned on but laterally offset from the second conductor pad and having a second lateral dimension larger than the first lateral dimension and being adapted to couple to the other of the first and second conductor structures.2. The apparatus of claim 1 , wherein the first semiconductor chip comprises an interposer.3. The apparatus of claim 1 , comprising a solder structure positioned each of the first and second conductor pillars.4. The apparatus of ...

Semiconductor device having a through-substrate via

Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME

Disclosed herein are a package substrate and a method of fabricating the same. The method of fabricating the package substrate includes preparing a base substrate, forming a metal material layer surrounding an entire surface of the base substrate, forming sacrificial patterns on partial regions of the base substrate on which the metal material layer is formed, forming pads contacting lateral surfaces of the sacrificial patterns, forming a gold plating layer on upper surfaces of the pads, and removing the sacrificial patterns and removing portions of the metal material layer to form a conductive layer that remains on partial regions so as to contact lower surfaces of the pads. 1. A method of fabricating a package substrate , comprising:preparing a base substrate;forming a metal material layer surrounding an entire surface of the base substrate;forming sacrificial patterns on partial regions of the base substrate on which the metal material layer is formed;forming pads contacting lateral surfaces of the sacrificial patterns;forming a gold plating layer on upper surfaces of the pads; andremoving the sacrificial patterns and removing portions of the metal material layer to form a conductive layer that remains on partial regions so as to contact lower surfaces of the pads.2. The method according to claim 1 , wherein the pads are each formed to have a smaller height than that of each of the sacrificial patterns.3. The method according to claim 1 , wherein the gold plating layer is formed to have a smaller height than that of each of the sacrificial patterns.4. The method according to claim 1 , further comprising forming an insulating layer on the base substrate claim 1 , except for the partial regions.5. A package substrate comprising:a base substrate;a conductive layer formed on partial regions of the base substrate;pads formed on the conductive layer; anda gold plating layer that is formed to contact upper surfaces of the pads.6. The package substrate according to claim ...

SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME

A semiconductor device includes a semiconductor substrate, first and second penetration electrodes each penetrating the semiconductor substrate, a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure including a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring, a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode, a second wiring pad formed as the upper-level wiring, a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads, a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode, a fourth wiring pad formed as the upper-level wiring, and a plurality of second through electrodes each formed in the interlayer insulating film. 1. A semiconductor device comprising:a semiconductor substrate;first and second penetration electrodes each penetrating the semiconductor substrate;a multi-level wiring structure formed on the semiconductor substrate, the multi-level wiring structure comprising a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level wiring and the upper-level wiring;a first wiring pad formed as the lower-level wiring and electrically connected to the first penetration electrode;a second wiring pad formed as the upper-level wiring;a plurality of first through electrodes each formed in the interlayer insulating film to form an electrical connection between the first and second wiring pads;a third wiring pad formed as the lower-level wiring and electrically connected to the second penetration electrode;a fourth wiring pad formed as the upper-level wiring; anda plurality of second through electrodes each formed in the interlayer insulating film to form an electrical ...

Semiconductor Device And Bump Formation Process

A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump. 1. A semiconductor device , comprising:a semiconductor substrate;a pad region on the semiconductor substrate;a solder bump overlying and connected to the pad region; anda metal cap layer formed over at least a portion of the solder bump while exposing a top portion of the solder bump;wherein the metal cap layer has a melting temperature greater than a melting temperature of the solder bump.2. The semiconductor device of claim 1 , wherein the metal cap layer comprises nickel.3. The semiconductor device of claim 1 , wherein the metal cap layer comprises palladium.4. The semiconductor device of claim 1 , wherein the metal cap layer comprises gold.5. The semiconductor device of claim 1 , wherein the metal cap layer comprises copper.6. The semiconductor device of claim 1 , wherein the solder bump comprise a lead-free solder material.7. The semiconductor device of claim 1 , wherein the metal cap layer is formed on a middle sidewall surface of the solder bump.8. The semiconductor device of claim 7 , wherein the solder bump comprises a bottom portion that laterally spreads outside the metal cap layer.9. The semiconductor device of claim 1 , wherein the metal cap layer is formed on a lower sidewall surface of the solder bump and extends to a bottom portion of the solder bump.10. A packaging assembly claim 1 , comprising:a semiconductor substrate;a package substrate; anda bump structure disposed between and electrically connecting the semiconductor substrate and the package substrate;wherein the bump structure comprises a solder bump and a metal cap layer covering at least a portion of the solder bump while a top portion of the solder bump remains exposed, and the metal cap layer has a melting temperature ...

SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING THE SEMICONDUCTOR MODULE, AND MOBILE APPARATUS

Bump electrodes and wiring layers are formed by selectively removing a copper sheet while the copper sheet is being held on a supporting base by an adhesion layer. Subsequently, a device mounting board is formed by laminating an insulating resin layer in such a manner that Au/Ni layers are exposed on the bump electrodes and the adhesion layer. The device mounting board and a semiconductor device held on the supporting base are temporarily press-bonded to each other and then the supporting base and the adhesion layer are removed. Then the device mounting board and the semiconductor device are finally and permanently press-bonded together. 1. A semiconductor module , comprising:an insulating resin layer;a wiring layer disposed on one main surface of said insulating resin layer;a bump electrode protruding on a side of said insulating resin layer from said wiring layer; anda semiconductor device where a device electrode is disposed counter to said bump electrode,wherein said wiring layer has an end surface formed in a tapered shape such that the end surface of said wiring layer enters inside a wiring layer forming region as the end surface thereof approaches the semiconductor device, andthe bump electrode runs through the insulating resin layer, and the bump electrode and the device electrode are electrically connected to each other.2. A semiconductor module according to claim 1 , wherein the bump electrode is tapered in the same direction as a tapered direction of the end surface of the wiring layer.3. A method claim 1 , for fabricating a semiconductor module claim 1 , including:forming a wiring layer, where a substrate electrode is provided, by selectively removing a metallic sheet held on a supporting base; andforming a device mounting board, which includes the wiring layer, the substrate electrode, and an insulating resin layer, by forming the insulating resin layer on the supporting base in a manner such that a top face itself of the substrate electrode or a ...

BUMPING PROCESS AND STRUCTURE THEREOF

A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots, forming a plurality of bottom coverage layers at the opening slots, proceeding a heat procedure, forming a plurality of external coverage layers to make each of the external coverage layers connect with each of the bottom coverage layers, wherein said external coverage layer and said bottom coverage layer form a wrap layer and completely surround the copper bump, forming a plurality of connective layers on the external coverage layers, removing the photoresist layer, removing the second areas and enabling each of the first areas to form an under bump metallurgy layer. 1. A bump structure at least includes:a silicon substrate having a surface, a plurality of bond pads disposed on the surface, and a protective layer disposed on the surface, wherein the protective layer comprisesa plurality of openings, and the bond pads are revealed by the openings;a plurality of under bump metallurgy layers formed on the bond pads;a plurality of copper bumps formed on top of the under bump metallurgy layers, and each of the copper bumps comprises a first top surface, a ring surface, and a bottom surface;a plurality of wrap layers, each of the copper bumps is completely surrounded by each of the wrap layers, wherein the wrap layer comprises a bottom coverage layer and an external coverage layer in connection with the bottom coverage layer, each of the bottom coverage layers is formed on each of the under bump metallurgy layers, each of the external coverage layers is formed on the first top surface of each of the copper bumps and the ring surface, the bottom surface of each of the copper bumps is located on each ...

Methods and Apparatus for Thinner Package on Package Structures

Methods and apparatus for thinner package on package (“PoP”) structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate and a plurality of package on package connectors extending from a bottom surface; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface; wherein at least the second substrate is formed of a plurality of layers of laminated dielectric and conductors. In another embodiment a cavity is formed on the bottom surface of the first substrate and a portion of the another integrated circuit extends partially into the cavity. Methods for making the PoP structures are disclosed.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

SEMICONDUCTOR PACKAGE AND METHOD AND SYSTEM FOR FABRICATING THE SAME

A fabrication method of a semiconductor package includes: disposing a first wafer on a substrate having at least a conductive pad; stacking a second wafer on the first wafer, wherein the second wafer has a pre-open area corresponding in position to the conductive pad of the substrate; forming a protection layer on the second wafer; embrittling the protection layer on the pre-open area of the second wafer; and removing the embrittled portion of the protection layer and portions of the second and first wafers so as to form an opening to expose the conductive pad, thereby preventing an adhesive layer from being attached to a cutting tool as in the prior art. 1. A semiconductor package , comprising:a substrate having a die attach area and at least a conductive pad disposed at an outer periphery of the die attach area;a first chip disposed on the die attach area of the substrate;a second chip disposed on the first chip and having a side surface corresponding in position to the die attach area so as to expose the conductive pad of the substrate;a first protection layer formed on a portion of the second chip and extending to an upper edge of the side surface of the second chip; anda second protection layer formed on a portion of the second chip and connecting the first protection layer, wherein the first protection layer is greater in brittleness than the second protection layer.2. The package of claim 1 , wherein the substrate has a chip structure.3. The package of claim 1 , wherein the first chip or the second chip has a MEMS (Micro Electro Mechanical System).4. The package of claim 1 , wherein the first chip is disposed on the substrate through a plurality of bumps.5. The package of claim 1 , wherein the second chip has a cavity for exposing a portion of the first chip.6. The package of claim 5 , wherein the second protection layer covers the cavity.7. The package of claim 1 , wherein the first protection layer is made of a brittle material.8. The package of claim 1 , ...

Semiconductor package

A semiconductor package includes a substrate including a mounting surface having a plurality of ground pads, a semiconductor chip disposed on the mounting surface, a conductive connection part connected to at least one of the plurality of ground pads and having a greater width at a center than at an end, a molding member exposing a top surface of the conductive connection part while wrapping the mounting surface, the conductive connection part and the semiconductor chip, and a heat slug disposed on the molding member and connected to the top surface of the conductive connection part.

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME

A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal. 1. A semiconductor package comprising:a package substrate;a first semiconductor chip on the package substrate; anda chip package on the first semiconductor chip, the chip package including a silicon substrate and a second semiconductor chip on the silicon substrate, the silicon substrate electrically connecting the second semiconductor chip to the first semiconductor chip,wherein the silicon substrate includes first through hole vias disposed in the silicon substrate, andwherein a first conductive terminal is disposed on an upper surface of the first semiconductor chip, a second conductive terminal is disposed on a lower surface of the silicon substrate, and the first conductive terminal is also disposed on the second conductive terminal.2. The semiconductor package of claim 1 , whereinthe first conductive terminal includes first bump pads on an upper surface of the first semiconductor chip; andthe second conductive terminal includes first bumps on a lower surface of the silicon substrate, the first bumps electrically connected to the first through-hole vias and the first bump pads.3. The semiconductor package of claim 1 , wherein the chip package includes the second semiconductor chip having bumps connected to the first through-hole vias claim 1 , the second semiconductor chip being disposed on the silicon substrate as a flip chip.4. The ...

HYBRID SUBSTRATE, PRODUCTION METHOD THEREFOR, AND SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE

A hybrid substrate according to the present invention comprises a core layer composed of a glass woven cloth as a reinforcing material, and a glass-ceramic sintered body which at least comprises a glass component and a metal oxide component. The glass woven cloth and the glass-ceramic sintered body formed by an impregnation with respect to the glass woven cloth are in a form of sintering integration with each other. 119-. (canceled)20. A hybrid substrate comprising:a core layer composed of a glass woven cloth as a reinforcing material, and a glass-ceramic sintered body which at least comprises a glass component and a metal oxide component;at least one through-hole which passes through the core layer;a wiring layer provided on each of opposing both sides of the core layer,wherein the hybrid substrate further comprises at least one build-up layer on at least one side of the hybrid substrate,wherein the build-up layer is composed at least of a build-up resin layer, a via hole provided in the build-up resin layer, and a wiring layer provided on the build-up resin layer, andwherein the glass woven cloth and the glass-ceramic sintered body formed by an impregnation with respect to the glass woven cloth are in a form of sintering integration with each other in the core layer, and thereby the glass woven cloth is contained in the whole interior of the core layer.21. The hybrid substrate according to claim 20 , wherein the glass component of the glass-ceramic sintered body has a softening point which is lower than that of the glass woven cloth.22. The hybrid substrate according to claim 20 , wherein the glass woven cloth has a glass fiber whose diameter is in the range of 15 μm to 105 μm.23. The hybrid substrate according to claim 20 , wherein the hybrid substrate is in a form of a single substrate whose principal surface has a size of 255-600 mm×255-600 mm.24. The hybrid substrate according to claim 20 , further comprising:a thermoset insulating resin layer provided on each ...

Package-on-package type semiconductor packages and methods for fabricating the same

A method of forming a semiconductor package may include providing a first package including a first semiconductor chip mounted on a first package substrate having a via-hole and molded by a first mold layer, providing a second package including a second semiconductor chip mounted on a second package substrate having a connection pad and molded by a second mold layer, stacking the first package on the second package to vertically align the via-hole with the connection pad, forming a through-hole penetrating the first and second packages and exposing the connection pad, and forming an electrical connection part in the through-hole. The electrical connection part may electrically connect the first package and the second package to each other.

PRINTED WIRING BOARD

A printed wiring board includes a core substrate, a first buildup layer laminated on a first surface of the core substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the first buildup layer, and a second buildup layer laminated on a second surface of the core substrate and including the outermost interlayer resin insulation layer and the outermost conductive layer formed on the outermost interlayer resin insulation layer of the second buildup layer. The outermost conductive layer of the first buildup layer includes pads positioned to mount a semiconductor device on a surface of the first buildup layer, and the outermost interlayer resin insulation layer of the first buildup layer has a thermal expansion coefficient which is set lower than a thermal expansion coefficient of the outermost interlayer resin insulation layer of the second buildup layer. 1. A printed wiring board , comprising:a core substrate having a first surface and a second surface on an opposite side of the first surface;a first buildup layer laminated on the first surface of the core substrate and comprising an outermost interlayer resin insulation layer and an outermost conductive layer formed on the outermost interlayer resin insulation layer of the first buildup layer; anda second buildup layer laminated on the second surface of the core substrate and comprising an outermost interlayer resin insulation layer and an outermost conductive layer formed on the outermost interlayer resin insulation layer of the second buildup layer,wherein the outermost conductive layer of the first buildup layer includes a plurality of pads positioned to mount a semiconductor device on a surface of the first buildup layer, and the outermost interlayer resin insulation layer of the first buildup layer has a thermal expansion coefficient which is set lower than a thermal expansion coefficient of the ...

SEMICONDUCTOR DEVICES INCLUDING DUMMY SOLDER BUMPS

A semiconductor device includes a substrate on which integrated circuit units are formed, main solder bumps that are electrically connected to the integrated circuit units on the substrate and dummy solder bumps that are not electrically connected to the integrated circuit units on the substrate. The dummy solder bumps are narrower than wiring patterns immediately below the dummy solder bumps. 1. A semiconductor device comprising:a substrate;a plurality of integrated circuit units on the substrate;a plurality of main solder bumps on the substrate, the plurality of main solder bumps being electrically connected to the integrated circuit units; anda plurality of dummy solder bumps on the substrate, the plurality of dummy solder bumps not being electrically connected to the integrated circuit units, the dummy solder bumps being narrower than wiring patterns directly therebelow.2. The semiconductor device of claim 1 , wherein bottom surfaces of the dummy solder bumps are flat.3. The semiconductor device of claim 1 , wherein each of the dummy solder bumps comprises a pillar adjacent the substrate and a reflow solder layer remote from the substrate claim 1 , and sidewalls of the pillar have a vertical profile.4. The semiconductor device of claim 1 , wherein the dummy solder bumps vertically overlap with the wiring patterns.5. The semiconductor device of claim 1 , further comprising:an insulating interlayer on the integrated circuit units; anda plurality of pads on the insulating interlayer,wherein the wiring patterns are in the insulating interlayer.6. The semiconductor device of claim 5 , further comprising a passivation layer on the insulating interlayer to cover a portion of the pads and the wiring patterns.7. The semiconductor device of claim 6 , wherein the passivation layer completely covers the wiring patterns and the dummy solder bumps are on the passivation layer.8. The semiconductor device of claim 7 , wherein portions of an outer surface of the passivation ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 μm. 1. A semiconductor device comprising:a semiconductor chip; andan interconnect substrate over which the semiconductor chip is mounted in a flip-chip,wherein the semiconductor chip includesan electrode pad, anda Cu pillar formed over the electrode pad,the interconnect substrate includes a connection terminal made of a metal containing Cu,the Cu pillar and the connection terminal are connected to each other through a solder layer containing Sn,a Ni layer is formed either between the Cu pillar and the solder layer or between the solder layer and the connection terminal, anda minimum value of a thickness of the solder layer is equal to or less than 20 μm.2. The semiconductor device according to claim 1 , wherein the solder layer includes an alloy layer of Cu and Sn claim 1 , and at least a portion of the Cu pillar and at least a portion of the connection terminal are connected to each other through the alloy layer.3. The semiconductor device according to claim 1 , wherein the solder layer includes an alloy layer of Cu and Sn claim 1 , and the alloy layer grows as a current is caused to flow between the electrode pad and the connection terminal claim 1 , so that at least a portion of the Cu pillar and at least a portion of the connection terminal are connected to ...

SOLDER BUMP STRETCHING METHOD FOR FORMING A SOLDER BUMP JOINT IN A DEVICE

A method includes heating a solder bump above a melting temperature of the solder bump. The solder bump is stretched to increase a height of the solder bump. The solder bump is cooled down to form a solder bump joint in an electrical device. 1. A method of producing a solder bump joint , comprising:heating a solder bump comprising tin above a melting temperature of the solder bump;stretching the solder bump to increase a height of the solder bump; andcooling down the solder bump.2. The method of claim 1 , wherein the solder bump is predominantly a eutectic Sn—Bi compound.3. The method of claim 1 , wherein the solder bump is predominantly a eutectic Sn—Pb compound.4. The method of claim 1 , wherein the solder bump further comprises copper.5. The method of claim 1 , wherein the solder bump further comprises silver.6. The method of claim 1 , wherein a contact angle is less than 90° after the stretching.7. The method of claim 1 , wherein a ratio of an average center width spacing to an average top contact width spacing is between 0.5 and 1.0.8. The method of claim 1 , wherein the solder bump contains lamellar structure claim 1 , the lamellar structure being predominantly orthogonal to an axis of stretching claim 1 , after the stretching.9. The method of claim 1 , wherein the solder bump contains lamellar structure claim 1 , the lamellar structure being predominantly parallel to an axis of stretching claim 1 , after the stretching.10. The method of claim 1 , wherein the solder bump contains lamellar structure claim 1 , the lamellar structure having a first portion and a second portion claim 1 , the first portion being predominantly parallel to an axis of stretching and the second portion being predominantly orthogonal to the axis of stretching claim 1 , after the stretching.11. The method of claim 1 , wherein the solder bump contains lamellar structure claim 1 , the lamellar structure including a Sn-rich phase having greater than 90% Sn plus an IMC phase where the IMC ...

Semiconductor Device and Method for Forming a Low Profile Embedded Wafer Level Ball Grid Array Molded Laser Package (EWLP-MLP)

A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;depositing an encapsulant over and around the semiconductor die;forming an interconnect structure over a first surface of the encapsulant;forming an opening from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure; andforming a bump recessed within the opening and disposed over the surface of the interconnect structure.2. The method of claim 1 , further including:providing a semiconductor package; anddisposing the semiconductor package over the second surface of the encapsulant and electrically connecting the semiconductor package to the bump.3. The method of claim 2 , further including forming a plurality of interconnect structures over the semiconductor package to electrically connect the semiconductor package to the bump.4. The method of claim 2 , wherein the semiconductor package includes a memory device.5. The method of claim 2 , wherein the semiconductor device includes a ...

THREE-DIMENSIONAL INTEGRATED CIRCUIT WHICH INCORPORATES A GLASS INTERPOSER AND METHOD FOR FABRICATING THE SAME

A three-dimensional integrated circuit (3D-IC) which incorporates a glass interposer and a method for fabricating the three-dimensional integrated circuit (3D-IC) with the glass interposer are described herein. In one embodiment, the 3D-IC incorporates a glass interposer which has vias formed therein which are not filled with a conductor that allow for precision metal-to-metal interconnects (for example) between redistribution layers. In another embodiment, the 3D-IC incorporates a glass interposer which has vias and has a coefficient of thermal expansion (CTE) that is different than the CTE of silicon which is 3.2 ppm/° C. 1. A three-dimensional integrated circuit comprising:a first circuit component;one or more first redistribution layers, where one of the first redistribution layers has a plurality of first conductive pillars extending therefrom;a glass interposer having a body including a first surface and a second surface which are substantially parallel to each other, and where the body has a plurality of vias extending there through from the first surface to the second surface;one or more second redistribution layers, where one of the second redistribution layers has a plurality of second conductive pillars extending therefrom;a second circuit component;the one or more first redistribution layers are positioned between the first circuit component and the first surface of the glass interposer;the one or more second redistribution layers are positioned between the second circuit component and the second surface of the glass interposer; andthe glass interposer is positioned between the one first distribution layer and the one second distribution layer such that each one of the first conductive pillars contacts a corresponding one of the second conductive pillars, and where each pair of the first and second conductive pillars contact one another within one of the vias located in the glass interposer.2. The three-dimensional integrated circuit of claim 1 , wherein ...

PROTECTION LAYER FOR ADHESIVE MATERIAL AT WAFER EDGE

A three-dimensional integrated circuit (3DIC) including a first substrate having a first surface and a second surface opposite to the first surface and a second substrate attached to the first surface of the first substrate. The 3DIC further includes an interconnect between attached to the first surface of the first substrate and the second substrate and a plurality of through vias formed in the first substrate and electrically coupled to the interconnect. The 3DIC further includes a protection layer over the second surface of the first substrate, wherein each of the plurality of through vias protrudes through the protection layer and a plurality of dies, each die of the plurality of dies attached to at least one through via of the plurality of through vias. 1. A three-dimensional integrated circuit , comprising:a first substrate having a first surface and a second surface opposite to the first surface;a second substrate attached to the first surface of the first substrate;an interconnect between attached to the first surface of the first substrate and the second substrate;a plurality of through vias formed in the first substrate and electrically coupled to the interconnect;a protection layer over the second surface of the first substrate, wherein each of the plurality of through vias protrudes through the protection layer; anda plurality of dies, each die of the plurality of dies attached to at least one through via of the plurality of through vias.2. The 3DIC of claim 1 , wherein the protection layer comprises at least one of an oxide film claim 1 , a nitride film claim 1 , a carbide film claim 1 , a polymer-based material claim 1 , a resin-based material claim 1 , polyimide claim 1 , or a spin-on material.3. The 3DIC of claim 1 , further comprising at least one conductive structure configured to attach each of the plurality of dies to at least one of the plurality of through vias.4. The 3DIC of claim 3 , wherein the at least one conductive structure comprises at ...

Thin 3D Fan-Out Embedded Wafer Level Package (EWLB) for Application Processor and Memory Integration

A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die. 1. A method of making a semiconductor device , comprising:providing a plurality of first semiconductor die;depositing an encapsulant over a first surface of the first semiconductor die and around the first semiconductor die;forming an insulating layer over the encapsulant and over a second surface of the first semiconductor die opposite the first surface;forming a first conductive layer over the insulating layer; anddisposing a second semiconductor die over the first semiconductor die and electrically connected to the first conductive layer.2. The method of claim 1 , further including forming a second conductive layer over the first conductive layer to form vertical conductive vias.3. The method of claim 2 , wherein a pitch between vertical conductive vias is less than 50 micrometers.4. The method of claim 1 , further including forming a bump over the first conductive layer and overlapping a footprint of the first semiconductor die.5. The method of claim 1 , further including forming a bump over the first conductive layer outside a footprint of the ...

FILLED THROUGH-SILICON VIA AND THE FABRICATION METHOD THEREOF

By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased. 1. A through via , comprising:at least one through-via hole disposed between a first surface and a second surface opposite to the first surface of an isolative substrate and penetrating the isolative substrate; anda conductive material filled within the at least one through-via hole and filled up the at least one through-via hole, the conductive material being a composite material at least comprising a metal material and particles of a supplementary material having a coefficient of thermal expansion lower than a coefficient of thermal expansion of the metal material and having a thermal conductivity higher than a thermal conductivity of the metal material, wherein the metal material is selected from copper, tungsten or aluminum, and the supplementary material is selected from silicon carbide, chemical-vapor deposition silicon carbide, diamond, chemical-vapor deposition diamond, beryllium oxide, aluminum nitride, aluminum oxide, molybdenum or carbon nanotubes.2. The through via as claimed in claim 1 , wherein a diameter of the particles of the supplementary material substantially ranges from tens of nanometers to tens of micrometers.3. The through via as claimed in claim 1 , wherein an addition ratio of the particles of the supplementary material is less than or equal to 50%.4. The through via as claimed in claim 1 , wherein an addition ratio of the particles of the supplementary material substantially ranges from 5% to 50%.5. The through via as claimed in claim 1 , further comprising a first wiring pattern located on the first surface and covering the conductive material filled in the at least one ...

Flip-chip packaging techniques and configurations

Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.

SEMICONDUCTOR APPARATUS AND METHOD OF FABRICATING THE SAME

In a semiconductor apparatus, a plurality of semiconductor chips including through-silicon vias are stacked in a vertical direction, wherein the through-silicon via formed in each semiconductor chip protrudes beyond heights of each semiconductor chip. 1. A semiconductor apparatus in which a plurality of semiconductor chips including through-silicon vias are stacked in a vertical direction , wherein the through-silicon via formed in each semiconductor chip protrudes beyond heights of each semiconductor chip.2. The semiconductor apparatus according to claim 1 , wherein each semiconductor chip comprises:the through-silicon via; anda bump formed for signal exchange with another semiconductor chip to be stacked through the through-silicon via.3. The semiconductor apparatus according to claim 2 , wherein the plurality of semiconductor chips are stacked through a conductive connection member.4. The semiconductor apparatus according to claim 3 , wherein the conductive connection member is interposed between a bump of a first semiconductor chip and a through-silicon via of a second semiconductor chip to surround the through-silicon via protruding from the second semiconductor chip.5. The semiconductor apparatus according to claim 4 , wherein the conductive connection member includes a solder ball.6. A semiconductor apparatus comprising:a first semiconductor chip including a first through-silicon via;a second semiconductor chip including a second through-silicon via; anda conductive connection member interposed between the first semiconductor chip and the second semiconductor chip in order to stack the first semiconductor chip and the second semiconductor chip,wherein the first semiconductor chip and the second semiconductor chip are formed with concave-convex sections, respectively.7. The semiconductor apparatus according to claim 6 , wherein the concave-convex sections are formed by allowing the first through-silicon via formed in the first semiconductor chip and the second ...

Multi-Chip Packages and Methods of Manufacturing the Same

Multi-chip packages are provided having a first semiconductor chip arranged on a package substrate. The first semiconductor chip includes a first bonding pad connected to the package substrate. A second semiconductor chip is arranged on the first semiconductor chip. The second semiconductor chip has an overhang that protrudes from a side surface of the first semiconductor chip, and a second bonding pad arranged on the overhang. A third semiconductor chip is arranged on the second semiconductor chip to expose the overhang. The third semiconductor chip has a third bonding pad. A first conductive wire may be connected between the second bonding pad and the third bonding pad. A second conductive wire may be connected between the third bonding pad and the package substrate. 1. A multi-chip package comprising:a package substrate;a first semiconductor chip on a first surface of the package substrate, the first semiconductor chip having a first bonding pad that is electrically coupled to the package substrate;a second semiconductor chip arranged on a first surface of the first semiconductor chip, the second semiconductor chip having an overhang that protrudes from a side surface of the first semiconductor chip and a second bonding pad on the overhang;a third semiconductor chip arranged on a first surface of the second semiconductor chip to expose the overhang, the third semiconductor chip having a third bonding pad;a first conductive wire that electrically connects the second bonding pad and the third bonding pad; anda second conductive wire that electrically connects the third bonding pad and the package substrate.2. The multi-chip package of claim 1 , further comprising:a fourth semiconductor chip between the package substrate and the first semiconductor chip, the fourth semiconductor chip having a fourth bonding pad;a third conductive wire that electrically connects the first bonding pad and the fourth bonding pad; anda fourth conductive wire that electrically connects ...

Semiconductor device and method for manufacturing the same

An ultrasonic welding tool is used to bond end portions of an external connection terminal to circuit patterns of an insulating substrate, with a Vickers hardness not lower than 90. Bonding end portions are provided integrally with a bar in the external connection terminal. A bonding end portion located substantially in the lengthwise center of the bar is bonded first, then others are bonded alternately in order toward either end. Hardness of the bonding end portions is increased so that strength of the ultrasonic welding portions is increased, and displacement of the bonding end portion in either end from its regular position is suppressed to keep bonding strength high. Bonding strength of the ultrasonic welding portions between the external connection terminal and the circuit patterns of the insulating substrate can be increased so that long-term reliability can be secured in a semiconductor device.

PACKAGING SUBSTRATE

A packaging substrate is provided, wherein a plurality of conductive posts together with a conductive bonding layer formed thereon form a plurality of external connection structures with the same height, thereby preventing tilted stack structures and poor coplanarity in a subsequent stacking process. 1. A packaging substrate , comprising:a substrate body having two opposite surfaces respectively provided with a circuit layer, wherein the circuit layer on at least one of the surfaces of the substrate body has a plurality of first conductive pads and a plurality of second conductive pads;an insulating protective layer formed on the substrate body and the circuit layer and having a plurality of openings for exposing the first and second conductive pads;a plurality of first conductive posts respectively formed on the first conductive pads in the openings;a plurality of second conductive posts respectively formed on the second conductive pads in the openings and having a height greater than a height of the first conductive posts;a first conductive bonding layer formed on each of the first conductive posts so as for the first conductive posts and the first conductive bonding layer to form first external connection structures; anda second conductive bonding layer formed on each of the second conductive posts so as for the second conductive posts and the second conductive bonding layer to form second external connection structures, wherein the first external connection structures have a height equal to a height of the second external connection structures.2. The packaging substrate of claim 1 , wherein the circuit layer further has a plurality of bonding pads.3. The packaging substrate of claim 1 , wherein the first and second conductive posts are metal posts.4. The packaging substrate of claim 3 , wherein the metal posts are copper posts.5. The packaging substrate of claim 1 , wherein the first and second conductive bonding layers are made of a conductive paste.6. The ...

SEMICONDUCTOR DEVICE HAVING PENETRATING ELECTRODES EACH PENETRATING THROUGH SEMICONDUCTOR CHIP

Disclosed herein is a device that includes: a semiconductor substrate; plurality of first through-substrate vias each penetrating through the semiconductor substrate, a plurality of second through-substrate vias each penetrating through the semiconductor substrate, an insulating film formed over the semiconductor substrate, the insulating film including a first opening and a plurality of second openings, the first opening being located over the first through-substrate vias, and each of the second openings being located over a corresponding one of the second through-substrate vias. 1. A semiconductor device comprising:a semiconductor substrate including a first surface and a second surface opposite to each other; anda plurality of first through-substrate vias each penetrating through the semiconductor substrate from the first surface to the second surface, each of the first through-substrate vias including a first bump that protrudes from the first surface of the semiconductor substrate,wherein the first bumps serve as a first surface alignment mark on the first surface of the semiconductor substrate.2. The semiconductor device as claimed in claim 1 , further comprising a plurality of second through-substrate vias each penetrating through the semiconductor substrate from the first surface to the second surface claim 1 , whereinthe second through-substrate vias transmit corresponding signals, andthe first through-substrate vias are arranged narrower in pitch than the second through-substrate vias.3. The semiconductor device as claimed in claim 2 , further comprising:a plurality of second bumps provided over the second surface of the semiconductor substrate,wherein each of the second bumps is vertically aligned with an associated one of the second through-substrate vias.4. The semiconductor device as claimed in claim 1 , further comprising:a first wiring layer provided over the second surface of the semiconductor substrate; anda second surface alignment mark provided ...

CHIP STRUCTURE, CHIP BONDING STRUCTURE USING THE SAME, AND MANUFACTURING METHOD THEREOF

A chip structure, a chip bonding structure, and manufacturing methods thereof are provided. The chip structure includes a chip, a plurality of bumps, and an insulation layer. The bumps are disposed on the chip. Each bump has a first bump portion and a second bump portion connected to each other, wherein the first bump portion and the second bump portion have different activities. The bumps are subjected to chemical reaction to form an insulation layer on the surface of one of the first bump portion and the second bump portion which has higher activity, so as to avoid short-circuit between the adjacent bumps. 1. A chip structure , comprising:a chip;at least one bump disposed on the chip, wherein the bump includes a first bump portion and a second bump portion connected to each other, wherein the first bump portion and the second bump portion have different activities; andan insulation layer having an element identical to the element in a higher activity one of the first bump portion and the second bump portion, wherein the insulation layer is formed on the surface of the higher activity one of the first bump portion and the second bump portion.2. A chip bonding structure , comprising:a substrate including a plurality of conducting films spaced apart from each other;a chip including a plurality of bumps respectively aligned to the plurality of conducting films; anda conducting layer disposed between the substrate and the chip, wherein the conducting layer includes a plurality of conducting particles electrically connecting the bump and the aligned conducting film;wherein a portion of at least one of the plurality of bumps reacts with a reactant to form an insulation layer on the surface of the portion.3. The chip bonding structure of claim 2 , wherein the bump includes a first bump portion and a second bump portion connected to each other claim 2 , wherein the first bump portion and the second bump portion have different activities claim 2 , wherein the insulation ...

ELECTRONIC COMPONENT AND MANUFACTURE METHOD THEREOF

An electronic component includes a package substrate, a plurality of conductive pads, an insulating material and a semiconductor device. The plurality of conductive pads is disposed on the package substrate. The insulating material is disposed between the plurality of conductive pads. The insulating material includes a top surface located on an identical plane to an upper surface of the plurality of conductive pads. The semiconductor device includes a conductive bump aligned on a corresponding conductive pad of the plurality of conductive pads. 1. (canceled)2. (canceled)3. An electronic component manufacture method , comprising:disposing a plurality of conductive pads on a package substrate;disposing an insulating material between the plurality of conductive pads such that a top surface of the insulating material is located on an identical plane to an upper surface of the plurality of conductive pads; andaligning a conductive bump of a semiconductor device on a corresponding conductive pad of the plurality of conductive pads.4. The electronic component manufacture method according to claim 3 , further comprising forming a depression in the package substrate so as to face the semiconductor device claim 3 , wherein the plurality of conductive pads are disposed outside the depression.59-. (canceled)10. An electronic component manufacture method claim 3 , comprising:forming a depression in a package substrate;disposing a plurality of conductive pads outside the depression; andaligning a conductive bump of a semiconductor device on a corresponding conductive pad of the plurality of conductive pads.11. The electronic component manufacture method according to claim 10 , further comprising forming a protrusion portion on the plurality of conductive pads claim 10 , the protrusion portion having a narrower width than each of the plurality of conductive pads.12. The electronic component manufacture method according to claim 11 , further comprising disposing an insulating ...

METHOD FOR MANUFACTURING FINE-PITCH BUMPS AND STRUCTURE THEREOF

A method for manufacturing fine-pitch bumps comprises the steps of providing a silicon substrate; forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first zones and a plurality of second zones; forming a photoresist layer on the titanium-containing metal layer; patterning the photoresist layer to form a plurality of opening slots; forming a plurality of copper bumps at the opening slots, wherein each of the copper bumps comprises a first top surface and a ring surface; heating the photoresist layer to form a plurality of body portions and a plurality of removable portions; etching the photoresist layer; and removing the second zones to enable each of the first zones to form an under bump metallurgy layer having a bearing portion and an extending portion. 1. A fine-pitch bump structure at least comprising:a silicon substrate having a surface, a plurality of bond pads disposed at the surface and a protective layer disposed at the surface, wherein the protective layer comprised a plurality of openings, and the bond pads are revealed by the openings;a plurality of under bump metallurgy layers formed on the bond pads, each of the under bump metallurgy layers comprises a bearing portion and an extending portion;a plurality of copper bumps formed on the under bump metallurgy layers, each of the copper bumps comprises a first top surface and a ring surface, the bearing portion of each of the under bump metallurgy layers is located under each of the copper bumps, and the extending portion of each of the under bump metallurgy layers is protruded to the ring surface of each of the copper bumps;a plurality of bump protection layers formed on the extending portions of the under bump metallurgy layers, the first top surface and the ring surface of each of the copper bumps, each of the bump protection layers comprises a metallic coverage portion and a bump coverage portion having a second top ...

Multi-Direction Design for Bump Pad Structures

An integrated circuit structure includes a semiconductor chip having a first region and a second region; a dielectric layer formed on the first region and the second region of the semiconductor chip; a first elongated under-bump metallization (UBM) connector formed in the dielectric layer and on the first region of the semiconductor chip and having a first longer axis extending in a first direction; and a second elongated UBM connector formed in the dielectric layer on the second region of the semiconductor chip and having a second longer axis extending in a second direction. The first direction is different from the second direction. 1. An integrated circuit structure comprising:a semiconductor chip having a first region and a second region;a dielectric layer formed on the first region and the second region of the semiconductor chip;a first under-bump metallization (UBM) connector formed in the dielectric layer on the first region of the semiconductor chip and having a first shape in a top view; anda second UBM connector formed in the dielectric layer on the second region of the semiconductor chip and having a second shape in a top view, wherein the first shape is different from the second shape.2. The integrated circuit structure of claim 1 , further comprising a metal pad directly under the first UBM connector.3. The integrated circuit structure of claim 1 , wherein the first UBM connector comprises a longer axis with a first length and a shorter axis with a second length perpendicular to the longer axis claim 1 , and wherein a ratio of the first length to the second length is greater than about 1.5.4. The integrated circuit structure of claim 1 , wherein the second UBM connector is not elongated claim 1 , and wherein the second region is a center chip region comprising a center of the semiconductor chip.5. The integrated circuit structure of claim 4 , wherein the first region is adjacent a first edge of the semiconductor chip claim 4 , and wherein a longer axis ...

Semiconductor Device and Method of Forming a Robust Fan-Out Package including Vertical Interconnects and Mechanical Support Layer

A semiconductor device has a semiconductor die. An encapsulant is deposited around the semiconductor die. An interconnect structure having a conductive bump is formed over the encapsulant and semiconductor die. A mechanical support layer is formed over the interconnect structure and around the conductive bump. The mechanical support layer is formed over a corner of the semiconductor die and over a corner of the interconnect structure. An opening is formed through the encapsulant that extends to the interconnect structure. A conductive material is deposited within the opening to form a conductive through encapsulant via (TEV) that is electrically connected to the interconnect structure. A semiconductor device is mounted to the TEV and over the semiconductor die to form a package-on-package (PoP) device. A warpage balance layer is formed over the encapsulant opposite the interconnect structure.

Wiring substrate and method of manufacturing the same

There is provided a wiring substrate. The wiring substrate includes: an insulating layer; first electrode pads having first exposed surfaces, the first exposed surfaces being exposed from the insulating layer; and second electrode pads having second exposed surfaces, the second exposed surfaces being exposed from the insulating layer. There is a level difference between the first exposed surfaces and the second exposed surfaces.