ПРИВЕДЕНИЕ В КОНТАКТ УСТРОЙСТВА С ПРОВОДНИКОМ

Изобретение относится к области приведения в контакт ОСИД с проводником. В способе для приведения в контакт ОСИД с проводником, ОСИД содержит подложку, по меньшей мере, с одной ячейкой, область контакта и инкапсулирующую оболочку, содержащую тонкую пленку, которая содержит нитрид кремния, карбид кремния или оксид алюминия, причем инкапсулирующая оболочка инкапсулирует, по меньшей мере, область контакта, а способ содержит этапы компоновки проводника на инкапсулирующей оболочке и взаимного соединения проводника с областью контакта, без предварительного удаления инкапсулирующей оболочки между проводником и областью контакта. Это изобретение обладает преимуществом в том, что инкапсулирующую оболочку между проводником и областью контакта не надо предварительно удалять. 2 н. и 7 з.п. ф-лы, 4 ил.

Mounting for at least one semiconductor component

The invention relates to a low-capacitance mounting, in particular for lossy semiconductor components, for example IMPATT diodes, which can be manufactured inexpensively. This is achieved with the aid of a diamond body (heat sink) having a trench-like recess containing the connected semiconductor component.

Verfahren zum Herstellen einer harzumhüllte Halbleiteranordnung

ELEKTRONISCHES BAUELEMENTGEHÄUSE

Die Technologie eines elektronischen Bauelementgehäuses ist offenbart. Ein elektronisches Bauelementgehäuse gemäß der vorliegenden Offenbarung kann ein Gehäusesubstrat, eine elektronische Komponente, eine Formmasse, die die elektronische Komponente einkapselt, und eine Redistributionsschicht umfassen, die derart angeordnet ist, dass die Formmasse zwischen dem Gehäusesubstrat und der Redistributionsschicht ist. Die Redistributionsschicht und das Gehäusesubstrat können elektrisch gekoppelt sein. Außerdem können die Redistributionsschicht und die elektronische Komponente elektrisch gekoppelt sein, um die elektronische Komponente und das Gehäusesubstrat elektrisch zu koppeln. Zugeordnete Systeme und Verfahren sind auch offenbart.

Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche

Ein Halbleiterchip beinhaltet eine Leistungstransistorschaltung mit mehreren aktiven Transistorzellen. Eine erste Lastelektrode und eine Steuerelektrode sind auf einer ersten Fläche des Halbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht beinhaltet. Eine zweite Lastelektrode ist auf einer zweiten Fläche des Halbleiterchips angeordnet. Eine zweite Metallschicht ist über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht elektrisch gegenüber der Leistungstransistorschaltung isoliert ist und die zweite Metallschicht über einen Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst.

Chip-size package production

Production of a semiconductor chip-size housing (CSP) involves (a) bonding conductive wires (45) onto bond pads on a chip (41); (b) placing the chip in an electrolysis cell (55) such that the wire ends are outside the electrolyte solution (50) of the cell; (c) fitting an electroplating electrode (60) on an inner wall of the cell; (d) placing a conductive plate (65) as common electrode on the exposed wire ends; and (e) connecting the conductive plate (65) and the outer wall of the cell (55) to a current source (70). Preferably, the wires (45) consist of gold, the conductive plate (65) consists of copper and the electroplating electrode (60) consists of nickel or gold.

Bond wire clamping and/or motion unit for semiconductor module

The unit includes a clamp (1) with axially protruding jaws (3) and a hollow base body (2). The unit is fitted to a bonding head of a wire bonding set. The jaws (3) are joined by solid hinges (6). A bonding wire (5) is led through the surrounding clamp. The clamp actuation is carried out by piezoelectric or electromagnetic force transmission in the elastic region. The clamp is movable in the longitudinal direction of the bonding wire.

Verfahren zur Bildung einer Drahtbondelektrode auf einer Dickschichtleiterplatte

Verfahren zum Herstellen einer Drahtbondelektrode auf einer Dickschichtleiterplatte, bei welcher eine Kupfer-Dickschicht (2) als Verdrahtungsschicht auf einem isolierenden Substrat (1) gebildet ist und ein auf dem isolierenden Substrat angebrachtes Teil (7) elektrisch mit der Kupfer-Dickschicht (2) über einen Golddraht (8) verbunden ist, mit: einem Schritt des Druckens der Kupfer-Dickschicht (2) auf das isolierende Substrat und des Sinterns der Kupfer-Dickschicht zur Bildung der Verdrahtungsschicht; und einem Schritt des Druckens einer Gold-Dickschicht, welcher vor dem Drucken Kupfer hinzugefügt worden ist, auf das isolierende Substrat und des Sinterns der Gold-Dickschicht als Drahtbondelektrode, um wenigstens partiell die Kupfer-Dickschicht zu überlappen, welche auf dem isolierenden Substrat gebildet ist.

Chip size semiconductor component

The semiconductor chip (21) carries several beads (22) bonded to the inner ends of the conductive wires (16), in a vertical manner. The entire chip is embedded in synthetic resin (23) such that the outer ends of the conductive wires protrude outwards. Preferably the inner end of the bonded wires, in contact with the chip beads, are shaped as irregular, oval; bonding spheres (25). Typically the outer ends of the protruding conductive vires are bent, directed against the middle of the chip, such as to form L-shaped external conductors.

Semiconductor module, has bonding wire bonded at load terminal and connected with upper contact piece, and explosion protection unit arranged between load terminals and upper contact piece and embedded in bonding wire at specific length

The module (100) has an electrically conductive lower contact piece (31) and an electrically conductive upper contact piece (32) spaced in a vertical direction (v). Multiple semiconductor chips comprise load terminals. One of the load terminals is electrical conductively connected with the lower contact piece. A bonding wire (4) is bonded at the load terminal and connected with the upper contact piece. An explosion protection unit is arranged between the load terminals and the upper contact piece and embedded in the bonding wire over 80% or 90% of length. The semiconductor chips are designed as unipolar and bipolar transistors such as IGBTs and MOSFETs. The bonding wire is designed as a flat small strip.

Wire bonding method for semiconductor device manufacture

The method involves using a capillary driven by a wire bonding apparatus, the capillary having an opening. A distal end of a bonding wire which enters a bonding circuit through the capillary is ultrasonically bonded. The opening forms a substantial part of a nail head bonding point during nail-head bonding.

Halbleitervorrichtung und Verfahren zu deren Herstellung

Halbleitervorrichtung, aufweisend:- ein isolierendes Substrat (1) mit einem ersten Schaltungsmuster (3);- ein Halbleiterelement (5), das an das erste Schaltungsmuster (3) mit einem ersten Lötmaterial (13) gebondet ist; und- einen Verdrahtungsanschluss (8), der mit einem zweiten Lötmaterial (14) an eine Elektrode gebondet ist, die am Halbleiterelement (5) auf einer gegenüberliegenden Seite des ersten Schaltungsmusters (3) ausgebildet ist, wobei:- ein Teil des Verdrahtungsanschlusses (8) an zwei vorstehenden Abschnitten in einer Draufsicht an gegenüberliegenden Seiten des Halbleiterelements (5) in Kontakt mit dem isolierenden Substrat (1) steht und vom ersten Schaltungsmuster (3) isoliert ist,- ein Harzgehäuse (7) auf dem isolierenden Substrat (1) und um das isolierende Substrat (1) herum angeordnet ist,- eine Endseite des Verdrahtungsanschlusses (8) in einer ersten Erstreckungsrichtung im Harzgehäuse (7) eingebettet ist und- der Teil des Verdrahtungsanschlusses (8), welcher die vorstehenden ...

Halbleitervorrichtung, Substrat zum Herstellen einer Halbleitervorrichtung und Verfahren zum Herstellen derselben

Halbleitervorrichtung, umfassend: eine Chipkontaktstelle; ein Halbleiterelement, das auf die Chipkontaktstelle geladen ist, das Elektroden aufweist; eine Mehrzahl von elektrisch leitfähigen bzw. leitenden Abschnitten, die um die Chipkontaktstelle angeordnet sind; Drähte zum Verbinden der Elektroden des Halbleiterelements und der elektrisch leitfähigen Abschnitte; und ein Dichtharz zum Dichten von wenigstens dem Halbleiterelement, den elektrisch leitfähigen Abschnitten und Drähten; wobei jeder der elektrisch leitfähigen Abschnitte eine Metallfolie enthält, wobei den elektrisch leitfähigen Abschnitt plattierende Schichten bzw. Lagen sowohl am oberen als auch unteren Ende der Metallfolie zur Verfügung gestellt sind; wobei die Chipkontaktstelle eine Chipkontaktstellen-Plattierschicht beinhaltet, die in derselben Ebene wie untere, den elektrisch leitfähigen Abschnitt plattierende Schichten der elektrisch leitfähigen Abschnitte vorgesehen ist; und wobei die unteren, den elektrisch leitfähigen ...

HALBLEITEREINHEIT UND VERFAHREN ZUR HERSTELLUNG DERSELBEN

Eine Elektrode (1) ist auf einer Halbleiterschicht (11) angeordnet. Eine Polyimid-Schicht (12) weist eine Öffnung auf, die auf der Elektrode (1) angeordnet ist, bedeckt den Rand der Elektrode (1) und erstreckt sich bis auf die Elektrode (1). Eine Kupfer-Schicht (13) ist innerhalb der Öffnung (OP) auf der Elektrode (1) angeordnet und befindet sich entfernt von der Polyimid-Schicht (12) auf der Elektrode (1). Das eine Ende eines Kupfer-Drahts (14) ist mit der Oberfläche der Kupfer-Schicht (13) verbunden.

Connection between sensor terminal and conductor path applied to glass plate uses conductive connection element ultrasonically welded to conductor path

Connection is provided by electrically conductive connection element (11), e.g. bonding wire, which is ultrasonically welded to conductor path (5) applied to surface of glass plate (1) and which is coupled to sensor terminal (13) mounted on glass plate. Surface (3) of glass plate is ridged at point of connection between conductor path and connection element, ultrasonic welding position lying in furrow between 2 ridges (4). An Independent claim for an application of a sensor terminal connection for a ceramic glass cooking hob surface is also included.

Dickdraht-Bondanordnung und Verfahren zum Herstellen

Die Erfindung betrifft eine Dickdraht-Bondanordnung, mit einem Substrat (2), einem Dickdraht (1) und einer Hochstrom-Dickdrahtbondverbindung, bei der ein endseitiger Bondabschnitt (4) des Dickdrahtes (1), welcher sich zum Drahtende (7) des Dickdrahtes (1) hin erstreckt, auf das Substrat (2) gebondet ist, derart, dass im Bereich des Bondabschnitts (4) ein Bondkontakt (5) zwischen dem Dickdraht (1) und dem Substrat (2) gebildet ist, wobei der Dickdraht (1) einen Verjüngungsabschnitt (6) aufweist, welcher sich an das Drahtende (7) anschließt und in welchem sich der Drahtquerschnitt zum Drahtende (7) hin verjüngt. Weiterhin betrifft die Anmeldung ein Verfahren zum Herstellen einer Dickdraht-Bondanordnung.

Verfahren zum elektrischen Verbinden eines Kontaktfeldes eines Halbleiterchips mit zumindest einer Kontaktfläche sowie danach hergestellte Chipkarte

Vorrichtung zum Anschweissen von duennen Draehten an Halbleiterbauteile mit Hilfe der Pressschweissung (Kalt- und Warmschweissung), mit einer Zufuhr fuer den Draht an einem den Pressdruck auf den Draht uebertragenden Schweisskopf

Packung mit aufgerauter verkapselter Oberfläche zur Förderung einer Haftung

Eine Packung (100), die mindestens einen elektronischen Chip (102), einen ersten wärmeabführenden Körper (104), der thermisch mit einer Hauptoberfläche des mindestens einen elektronischen Chips (102) gekoppelt ist und dafür ausgelegt ist, Wärmeenergie von dem mindestens einen elektronischen Chip (102) abzuführen, ein Kapselungsmittel (108), das mindestens einen Teil des mindestens einen elektronischen Chips (102) und einen Teil des ersten wärmeabführenden Körpers (104) verkapselt, wobei mindestens ein Teil einer Oberfläche des ersten wärmeabführenden Körpers (104) aufgeraut ist.

Leistungshalbleiterchip und Verfahren zur Herstellung eines Leistungshalbleiterchips und Leistungshalbleitereinrichtung

Leistungshalbleiterchip mit einem Halbleiterbauelementkörper (2) und mit einer auf dem Halbleiterbauelementkörper (2) angeordneten mehrschichtigen Metallisierung (10), die eine über dem Halbleiterbauelementkörper (2) angeordnete Nickelschicht (6) aufweist, wobei die Metallisierung (10) eine auf dem Halbleiterbauelementkörper (2) angeordnete, Aluminium aufweisende erste Metallschicht (3) aufweist, wobei die Nickelschicht (6) über der ersten Metallschicht (3) angeordnet ist, wobei die Metallisierung (10) eine zweite Metallschicht (4), die als Chromschicht ausgebildet ist und eine auf der zweiten Metallschicht (4) angeordnete Zwischenschicht (13), die aus Nickel besteht und eine auf der Zwischenschicht (13) angeordnete dritte Metallschicht (5), die als Silberschicht ausgebildet ist, aufweist, wobei die zweite Metallschicht (4) auf der ersten Metallschicht (3) angeordnet ist, wobei die Nickelschicht (6) auf der dritten Metallschicht (5) angeordnet ist, wobei die Nickelschicht (6) eine Dicke ...

Die-Struktur, Die-Anordnung und Verfahren zum Prozessieren eines Dies

Eine Die-Struktur weist einen Die und eine Metallisierungsschicht, die auf oder über der Vorderseite des Dies angeordnet ist, auf. Die Metallisierungsschicht weist Kupfer auf. Zumindest ein Teil der Metallisierungsschicht weist ein raues Oberflächenprofil auf. Der Teil mit dem rauen Oberflächenprofil weist einen Drahtbondbereich auf, an den eine Drahtbondstruktur gebondet werden soll.

PCB-BASIERTER FENSTERRAHMEN FÜR HF-LEISTUNGSPACKAGE, Halbleiterpackage und Verfahren zum Herstellen eines Halbleiterpackage

Halbleiterpackage, umfassend:eine kupferhaltige Grundplatte (100), die einen Chip-Befestigungsbereich (102; 103) und einen peripheren Bereich (101; 104) aufweist;einen Transistorchip (110), der einen ersten Anschluss, der am Chip-Befestigungsbereich (102; 103) der Grundplatte (100) angebracht ist, und einen zweiten Anschluss und einen dritten Anschluss abgewandt von der Grundplatte (100) aufweist; undeinen Rahmen (120), der ein elektrisch isolierendes Glied (122) umfasst, das eine am peripheren Bereich (101; 104) der Grundplatte (100) angebrachte erste Seite (128), eine von der Grundplatte (100) abgewandte zweite Seite (126), eine erste kupferhaltige Metallisierung (138) an der ersten Seite (128) des isolierenden Glieds (122) und eine zweite kupferhaltige Metallisierung (130) an der zweiten Seite (126) des isolierenden Glieds (122) umfasst, wobei jede Rahmenmetallisierung eine Schicht von Ni (250) auf Kupfer und eine Schicht von Au (252) auf dem Ni (250) umfasst,wobei das isolierende Glied ...

Halbleiterbauteil mit Korrosionsschutzschicht und Verfahren zur Herstellung desselben

Halbleiterbauteil (1; 23), das die folgenden Merkmale aufweist: - ein Schaltungsträger (2) mit mehreren Innenkontaktflächen (5), die ein erstes Material mit einem ersten elektrochemischen Potential aufweisen, - ein Halbleiterchip (3) mit einer aktiven Oberfläche (13) und einer Rückseite (11), wobei die aktive Oberfläche (13) mehrere Chipkontaktflächen (14) aufweist, die ein zweites Material mit einem zweiten elektrochemischen Potential aufweisen, und - Bonddrahtverbindungen (15) zwischen den Chipkontaktflächen (14) und den Innenkontaktflächen (5) des Schaltungsträgers (2), wobei die Bonddrähte (15) ein drittes Material mit einem dritten elektrochemischen Potential aufweisen, wobei die Verbindungsstellen (16) zwischen den Chipkontaktflächen (14) und den Bonddrähten (15) und die Verbindungsstellen (17) zwischen den Innenkontaktflächen (5) und den Bonddrähten (15) mit einer Korrosionsschutzschicht (20; 24) beschichtet sind, wobei Mittelbereiche (21) der Bonddrähte (15) frei von der Korrosionsschutzschicht ...

Leistungstransistor und Leistungshalbleiterbauteil

Die Erfindung betrifft einen Leistungstransistor und ein Leistungshalbleiterbauteil. Der vertikal leitende Leistungstransistor weist an seiner Vorderseite (11) eine Sourcezone (14) und einen Steuereingang (16) auf. Eine Durchführung für den Steuereingang weist eine Elektrode auf der Vorderseite (11) und eine Elektrode auf der Rückseite (12) auf, sodass der Steuereingang sowohl von der Vorderseite (11) als auch von der Rückseite (12) kontaktiert werden kann.

Verfahren zur Herstellung einer Chipkarte

Verfahren zur Herstellung einer Chipkarte, umfassend ein Chipmodul (3) mit mindestens einer Kontaktierungsfläche (4.1, 4.2), wobei das Chipmodul (3) in eine Aufnahmeposition (6) eines Substrats (1) einsetzbar ist, wobei für zumindest eine der Kontaktierungsflächen (4.1, 4.2) aus einem mittels einer Drahtführungseinheit zugeführten Drahtleiter (5) jeweils eine Kontaktierungsöse gebildet wird, indem ein erster Abschnitt (7) des Drahtleiters (5) auf einer Oberfläche des Substrats (1) außerhalb der Aufnahmeposition (6) angeheftet wird, wobei ein dem ersten Abschnitt (7) benachbarter zweiter Abschnitt (8) des Drahtleiters (5) so geführt wird, dass er zusammen mit der Oberfläche und aus dieser herausragend die Kontaktierungsöse bildet, wobei ein sich anschließender dritter Abschnitt (9) des Drahtleiters (5) auf der Oberfläche außerhalb der Aufnahmeposition (6) angeheftet wird, wobei das Chipmodul (3) in die Aufnahmeposition (6) eingesetzt wird und wobei der zweite Abschnitt (8) zur Kontaktierungsfläche ...

Mehrfach-Bonddrahtverbund und simultanes Bonden

Verbund, enthaltend eine Isolierung und einen Bonddraht, dadurch gekennzeichnet, dass die Isolierung eine den Bonddraht teilweise einbettende Rinne aufweist, so dass eine Seite des Verbunds aus Isolation besteht und eine Seite des Verbunds eine freiliegende Bonddrahtoberfläche aufweist.

Bondvorrichtung und Verfahren zur Herstellung elektrisch leitfähiger Verbindungen

Die vorliegende Erfindung betrifft eine Bondvorrichtung, aufweisend zumindest ein Bondwerkzeug und aufweisend eine Schneideinrichtung zum teilweisen oder vollständigen Zertrennen des Leiterquerschnittes und schlägt zur vorteilhaften Weiterbildung vor, dass auf der Schneideinrichtung (9) zumindest ein Piezoelement (17) montiert ist, da es bei Erregung mittels elektrischer Wechselspannung, vorzugsweise im Ultraschall-Frequenzbereich, zumindest einen Teilbereich der Schneideinrichtung (9), vorzugsweise zumindest eine Schneide (10) der Schneideinrichtung (9), in Schwingungen versetzt. Die Erfindung betrifft weiterhin ein Verfahren zur Herstellung elektrisch leitfähiger Verbindungen zwischen Verbindungspartnern mittels Befestigung von elektrischem Leiter an den miteinander elektrisch leitfähig zu verbindenden Verbindungspartnern durch Bondverbindungen, vorzugsweise Ultraschall-Bondverbindungen, wobei nach dem Herstellen einer gewünschten Anzahl von Bondverbindungen zum Abtrennen eines Längenabschnittes ...

AUTOMATIC THERMOCOMPRESSION WIRE BONDING APPARATUS

... 1433198 Welding by pressure HITACHI Ltd 18 July 1973 [26 July 1972] 34263/73 Heading B3R An automatic thermocompression bonding apparatus comprises an arm 3 carrying a wire bonding tool 2 and means for causing a pedestal 9 carrying the arm to move in two directions horizontally and for causing the tool to move upwardly and downwardly, the means including first and second cam mechanisms including two cams 11, 12 on a first shaft 10 for causing the arm movement in two horizontal directions, a further mechanism including a cam 16 on a second shaft 15 for causing the tool to move upwardly and downwardly and a driving mechanism for causing the first and second shafts to rotate with a predetermined speed ratio. In an embodiment the arm 3 carries at one end a tool 2 having a small wire receiving bore and the arm is carried in a member secured to a shaft 4 rotatably mounted in the pedestal 9. The pedestal 9 is slidable in the X direction on rods 8 mounted on a slide 35 which is in turn slidable ...

METHOD FOR BONDING A WIRE TO A METAL LAYER

... 1294770 Soldering HITACHI Ltd 22 Dec 1970 [29 Dec 1969] 60892/70 Heading B3R [Also in Division H1] In connecting a wire to a metal layer on a substrate the wire is guided through the passage of a capillary tube and a portion of the wire extending from the tube is pressed against the layer by the tube, the tube is heated to a temperature not lower than the melting point of the layer but lower than the melting point of the wire whereby the portion of the wire is pressed into the metal layer while metal of the layer is melted and the layer is then cooled to bond the wire to the layer, the tool being then moved away. An electrode 2, Fig. la, printed on a ceramic substrate 1 of a semi-conductor device carries a lead-tin solder layer 3 and a silver wire 5 is guided through the passage of a capillary tube 4. A head 6 is formed on the wire by burning in a hydrogen flame. The tube 4 is heated by resistance means to a temperature not lower than the melting point of the solder 3, e.g. to 300‹ C. and ...

Method of producing a semiconductor device

Electrical connection to an A1 electrode of a semiconductor is made by the attachment of a copper wire. A copper ball 8a formed by flaming out one end of a copper wire 8 is moved downward to an A1 electrode pad 5 on a semiconductor chip and brought into contact for less than 150 ms. Plastic deformation then occurs so that the copper ball is pressed to the aluminium electrode pad in such a manner that the height of the copper ball (h, Fig. 8) is 25 mu m or less. It is therefore possible to decrease the work hardening property of the Cu ball and prevent A1 exclusion when the Cu ball is bonded to the A1 electrode pad. ...

Improvements in and relating to the manufacture of semiconductor devices

... 1,086,254. Semi-conductor devices. PHILCOFORD CORPORATION. Feb. 25, 1965 [Feb. 28, 1964], No. 8244/65. Heading H1K. A connection is made to the surface of a semi-conductor body by attaching a fusible wire connector to the surface of the body, enlarging the free end of the wire by thermally fusing the wire and making connection to the enlarged end of the wire. A series of gold wires 30 are joined to the surface 31 of silicon body 29 by thermocompression bonding at "nailheads" 32. When joined initially, the wires 30 are upstanding and each has a blob on the upper end thereof formed by the process of flamecutting the wire from its supply reel after bonding the other end to the body 29. The blobs are brought into contiguity and then melted by a flame to give a single blob 34 which is enlarged and displaced towards the body 29 by the action of the flame. The body 29 which is mounted on a stud 27 is placed within a holder together with stud 26 having thereon solder 59 which solder is brought ...

COPPER PLATED LEAD FRAME FOR SEMICONDUCTOR PLASTIC PACKAGES

WIRE BONDING APPARATUS

METHOD AND MEANS FOR FORMING ELECTRICAL JOINTS

... 1338159 Soldering WELLS ELECTRONICS Inc 30 July 1971 35919/71 Heading B3R A method of soldering spaced parts of an elongated, flexible, wire or ribbon, conductor (e.g. of copper, silver, nickel) to selected spaced conductive elements of an electrical assembly (e.g. a circuit board) wherein solder is carried by either or both of the conductor or conductive elements, comprises the steps (a) mounting the electrical assembly on a support and threading the conductor through an apertured tip part, (b) bringing the tip part and support together to press a first conductor part against a first selected conductive element, (c) heating the first conductor part to melt the solder, (d) cooling; and thereby solidifying, the solder, (e) moving the tip part and support apart and shifting them relatively so that the conductor is drawn through the tip part, and repeating as required, steps (b)-(e) in respect of second and subsequent conductor parts and selected conductor elements. Where the conductor is ...

Method of manufacturing semiconductor devices

... 1,113,217. Semi-conductor devices. MATSUSHITA ELECTRONICS CORPORATION. 20 Oct., 1965 [26 Oct., 1964], No. 44440/65. Heading H1K. Connections are made to electrodes on a semiconductor device using a transparent flat insulator plate having conductive patterns coated thereon. A silicon body 1 having base 2 and emitter 3 regions therein is joined to metal base 16 by gold alloy 17. Metal pins 19 and 20 are mounted in glass holders 18 and are joined to metallic leads 10 and 11 by solder 21. The leads 10 and 11 are formed on a glass slide 9 which has notches 14 and 15 to fit around pins 19 and 20. The base 5 and emitter 6 electrodes are led out through oxide film 4 and joined to the leads 10 and 11 at 7 and 8. The transparent substrate 9 enables the leads to be positioned over the electrodes using a microscope and then pressure bonded. In another embodiment (Fig. 4, not shown) a P-type germanium mesa has leads on transparent substrate joined to it. The mass production of planar transistor units ...

Improved qfn package

METHOD OF TERMINATING A LAMP FILAMENT

... 1,222,905. Welding by pressure. CHICAGO MINIATURE LAMP WORKS. 25 Sept., 1969 [4 Oct., 1968], No. 47285/69. Heading B3R. [Also in Division H1] A method of securing a tungsten lamp filament 10 to a metal lead-in wire 12 comprises the following steps:- (1) Coating the end of the lead-in wire with gold; (2) Placing the filament across the coated end of the lead-in wire; (3) Placing a body 14 of gold on the filament and over the coated end of the lead-in wire; (4) Heating the body to a temperature below the melting point of gold but above the point at which diffusion of gold begins; and (5) Applying pressure to the body to cause the gold to surround the filament and form a diffusion bond with the coating on the lead-in wire. The body 14 is preferably formed as a ball 6-8 mils in diameter on the end of a 1À5 mil diameter wire 16, and the pressure is applied by a member 18 having a 2 mil diameter bore through which the wire passes. The lead-in wire 12 may be made of copper or dumet, and the temperature ...

Substrate for interconnecting electronic integrated circuit components, which is provided with a repair arrangement

An interconnecting substrate according to the invention comprises an insulating base on which rests a set of alternating, superimposed conductive and insulating layers. Contacts are formed on the uppermost insulating layer which border at least one site or zone intended for an integrated circuit chip device whose output conductors are to be connected to the said contacts. Through-connections enable the contacts to be coupled to one of the inner conductive layers. The through-connections include at least one through-connection on the inside of the site relative to at least a predetermined one of the said contacts. A shunt conductor means connected to the predetermined contact has a part outside the site which is connected to an additional contact which serves as a substitute or replaces the said predetermined contact for the connection to the associated output conductor of the chip device. The repair arrangement according to the invention allows one to substitute for a connection inside ...

PROVISION OF WIRE CONNECTIONS FOR SEMICONDUCTOR DEVICES

... 1502965 Welding by pressure; welding electrical contact PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 16 May 1975 [21 May 1974] 20840/75 Headings B3R and B3A In a method of welding a wire 9 (e.g. gold) to a semi-conductor body 1, an electric spark discharge between an electrode 10 and the end of the wire 9 melts the wire to form a ball 11 below a recess 8 in the welding surface 6 of a welding tool 5, preferably an ultrasonic sonotrode, whereupon the tool 5 presses the ball 11 on to a contact place 2 of the semi-conductor body 1 to produce the weld. The welding tool 5 also produces a weld between the wire 9 and a supply conductor, without the formation of a ball 11 (Fig. 6, not shown). The electric spark discharge may be provided by way of a transformer fed by a discharge capacitor, the discharge time being less than 5 msec. and the energy of the discharge (hence the size of the ball) determined by the capacitor voltage. The recess 8 can either be a groove transverse to the wire 9, which ...

Improvements in or relating to methods of soldering

... 821,551. Soldering; welding by pressure. GENERAL ELECTRIC CO. Ltd. May 3, 1957 [May 4, 1956; March 22, 1957], Nos. 13954/56 and 9417/57. Class 83 (4). [Also in Group XXXVI] In soldering two members together, both of metal or one of metal and the other a semiconductor, a metal member has bonded to it, prior to the heating operation, solder, in the solid state, to be used in the soldering operation, the bond being brought about by pressing together clean mating surfaces on the solder and the member. In making a transistor a plate 1, Fig. 3, of N-type germanium is provided with an indium emitter electrode 2 and an indium collector electrode 3 by cold bonding. The face of the plate on which is bonded the electrode 2 is soldered to one side of an annular dished nickel mount 4 having an indium bead 10 cold-bonded to the other side. The mount is cleaned by heating in dry hydrogen to 1000‹ C., a solder washer 11 of 60% tin, 40% lead, by volume, is scraped on each face and fitted into the mount ...

Bonding of metallic leads to semiconductor elements

... 881,834. Semi-conductor devices. WESTERN ELECTRIC CO. Inc. Oct. 29, 1957 [Oct. 31, 1956], No. 14256/61. Divided out of 881,832. Class 37. A lead of gold, silver, aluminium, copper or gold-plated or tinned copper is bonded to a strip of gold or aluminium 1 mil. wide on a semi-conductor body by pressing the parts together at a temperature above 100‹ C. but below the lowest eutectic temperature of any combination of the materials in contact, and the dislocation forming and displacing temperatures of the semiconductor, and maintaining the pressure and temperature long enough to make a strong low resistance bond. In an example, 1 mil. wide strips 44, 46 of aluminium and gold respectively are first alloyed to a mesa 52 formed on a germanium or silicon block. Leads 48, 50 of gold and aluminium respectively are then pressed against the alloyed strips in a press for 5 seconds to 15 minutes under a pressure sufficient to deform the leads by from 10 to 20%. The electrodes thus formed constitute the ...

Siliconized heterogeneous optical engine

Production method of semiconductor devices

... 1,070,303. Semi-conductor devices. HITACHI Ltd. Dec. 9, 1965 [Dec. 17, 1964]. No. 52349/65. Heading H1K. Metal is deposited from the vapour phase through a photo-sensitive resist mask on to a semi-conductor in two stages, the second stage at a lower temperature than the first. To bond a deposited metal to a semi-conductor the temperature of deposition must be in the neighbourhood of the metal-semi-conductor eutectic. But to prevent contamination of the surface of the deposited metal by carbonized resist, deposition should occur at a temperature below that at which the resist volatilizes or carbonizes. These considerations define the temperatures of the two stages, which for deposition of aluminium on silicone are 550‹ and 200‹ C. respectively for periods sufficient to deposit 0.2 to 1.0Á in the first stage and up to 0.2Á in the second. The clean deposit of the second stage provides for ready attachment of wire terminals, e.g. of aluminium or gold, which may be attached to it by thermocompression ...

DRAHTUND SOLDER JOINT MANUFACTURING PROCESS

PLAKSTIKVERKAPSELTE SEMICONDUCTOR DEVICES WITH IMPROVED CORROSION RESISTANCE

PROCEDURE FOR THE WIRE BONDING WITH A CUPREOUS BONDING WIRE USING AT LEAST TWO PLASMA NOZZLES

PROCEDURE FOR THE WIRE BONDING OF A MICROELECTRONIC SEMICONDUCTOR CHIP

PROCEDURE FOR FASTENING THE VERBINDUNGSDRAHTE ELECTRICAL MICRO CONSTRUCTION UNITS

AIR-COOLED BUILDING GROUP FOR A LSI (LARGE SCALE INTEGRATION) - PANEL AND PROCEDURE FOR THE PRODUCTION THE SAME

PROCEDURE AND DEVICE FOR THE EXAMINATION OF A WIRE BOND

CONTROL SYSTEM

PROCEDURE FOR ATTACHING A DUENNEN ELECTRICAL OF LEADING WIRE AT ELECTRONIC CONSTRUCTION UNITS, IN PARTICULAR SEMICONDUCTOR COMPONENTS.

WEAK POINT OF A WIRE PRODUCES BY A WIRE LINK.

BALL BOND PROCEDURE AND DEVICE FOR THE EXECUTION OF THE SAME

MONITORING OF BOND PARAMETERS DURING THE BOND PROCEDURE.

DEVICE FOR THE EXAMINATION OF WIRE FEED AND - CONSUMPTION

EFFICIENT ENERGY-TRANSFERRING CAPILLARY

Procedure for connecting a metal pus with a semiconductor body

Procedure for the production of a semiconductor device

Light receiving or light emitting modular sheet and process for producing the same

Electronic power circuit with heat dissipating radiator

Method for the wafer-level integration of shape memory alloy wires

The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.

WIRE BONDED INTEGRATED CIRCUIT DEVICES

Improved integrated circuit structures and methods to facilitate accurate measurement of the ic devices

INTEGRATED CIRCUIT WITH BUILT-IN REPAIR DEVICE

INTEGRATED CIRCUIT WITH BUILT-IN REPAIR DEVICE

L'invention se rapporte à un substrat d'interconnexion, du type comprenant un support isolant sur lequel repose un ensemble de couches conductrices et isolantes alternées et superposées; des plots formés sur la couche isolante supérieure et bordant au moins un domaine destiné à un composant dont les conducteurs de sortie sont à connecter auxdits plots; et des traversées permettant le couplage des plots, par l'intermédiaire de la couche conductrice supérieure, à l'une des couches conductrices intérieures et comprenant au moins une traversée intérieure au domaine relative à au moins un plot donné desdits plots, ledit substrat étant caractérisé en ce qu'il comporte un dispositif de réparation comprenant un moyen conducteur de dérivation relié audit plot donne et présentant une partie extérieure au domaine connectée à un plot additionnel se substituant audit plot donné pour la connexion audit composant.

METHOD OF WELDING OF CONNECTION WIRES TO MICROCIRCUIT CONTACTS

PHN.9872 10 27.4.81 "Method of forming a wire bond" A method of forming a wire bond between a contact place on an electronic microcircuit (17) and a connection conductor (18), in which a wire (6) of aluminium or an aluminium alloy is used which is passed through a capillary (5) in which a ball is formed at the end of the wire by means of a spark discharge between the wire (6) and an electrode (11), which spark discharge takes place in a protective gas atmosphere in which a first electric spark discharge is produced between two auxiliary electrodes (12, 13) as a result of which the protective gas is ionised and a plasma is formed, after which due to the low resistance in the plasma an electric spark discharge takes place between the electrode (11) and the wire (6) at a voltage between 25 V and 200 V, by which spark discharge a ball is formed at the end of the wire, while the wire is then bonded to a contact place on the electronic microcircuit and then to the connection conductor by means ...

FLAT PACKAGE FOR INTEGRATED CIRCUITS

L'invention se rapporte à un boîtier plat pour au moins un dispositif à circuits intégrés pourvu de plots de sortie, du type comprenant un élément de support dudit dispositif, une pluralité de bornes de sortie extérieures au boîtier, un réseau de conducteurs reliant lesdites bornes de sortie auxdits plots de sortie du dispositif, et des éléments de renforcement, caractérisé en ce que: ledit élément de support est une plaquette et lesdites bornes de sortie du boîtier sont des plages de contact disposées sur cette plaquette, au moins les conducteurs dudit réseau qui sont rattachés auxdites plages de contact reposent sur ladite plaquette de support; et ledit moyen de protection comprend un enrobage électriquement isolant, enrobant partiellement la plaquette de support et laissant dégagées au moins lesdites plages de contact.

WIRE BONDING TECHNIQUE FOR INTEGRATED CIRCUIT CHIPS

Title of the Invention LEAD FRAME WIRE BONDING BY PREHEATING In a method for welding a lead wire or bonding wire from a microcircuit chip mounted on a lead frame to a lead frame finger, the lead frame finger is preheated prior to any substantial electrical or thermal coupling between the lead frame finger and chip. Intense but controlled energy is applied to the lead frame finger at levels which might otherwise damage the IC chip. In one embodiment the lead frame finger is preheated to a temperature below the melting point of the metal comprising the lead frame. Enhanced bonding is thereafter effected by thermocompression bonding or the like. In another embodiment the preheating step comprises melting a portion of the surface of the lead frame finger and forming a molten pool or puddle in the surface. Bonding of the lead wire is affected by immersing a section of the wire in the molten pool or puddle. In order to preheat the lead frame finger a controlled pulse train is delivered for arc ...

LEAD WIRE BOND ATTEMPT DETECTION

Title of the Invention LEAD WIRE BOND ATTEMPT DETECTION A method and circuits are described for sensing and detecting bond attempts and weld attempts during bonding and welding-of lead wire. The method and circuitry are particularly applicable for detecting missed ball bonds and missed wedge bonds during bonding of lead wire between the die pad of a microcircuit chip and the lead frame on which the chip is mounted. A sensor (30) or sensing circuit (42) senses the different characteristic electrical condition of the lead wire (11) following a ball bond attempt and following a wedge bond attempt. A bond attempt indicator (45). indicates high resistance in the lead wire following a missed ball bond while weld attempt indicator (46) indicates low resistance in the lead wire (11) following a missed wedge bond. The lead wire (11) is isolated from uncontrolled contacts with ground potential while the lead wire is held in the bonding tool and bonding machine. Switching circuit (38) electrically ...

UHF BAND SEMICONDUCTOR PACKAGE

LSI CHIP PACKAGE AND METHOD

SEMICONDUCTOR PACKAGE

PULSE-WIDTH CONTROL OF BONDING BALL FORMATION

PACKAGE FOR INTEGRATED CIRCUIT DIE

A circuit package for housing semiconductor or other integrated circuit devices ("die") includes a high-copper flange, one or more high-copper leads and a liquid crystal polymer frame molded to the flange and the leads. The flange includes a dovetail-shaped groove or other frame retention feature that mechanically interlocks with the molded frame. During molding, a portion of the frame forms a key that freezes in or around the frame retention feature. The leads include one or more lead retention features to mechanically interlock with the frame. During molding, a portion of the frame freezes in or adjacent these lead retention features. The frame includes compounds to prevent moisture infiltration and match its coefficient of thermal expansion (CTE) to the CTE of the leads and flange. The frame is formulated to withstand die-attach temperatures. A lid is ultrasonically welded to the frame after a die is attached to the flange.

LEAD WIRE BOND ATTEMPT DETECTION

MIXED IMPEDANCE BOND WIRE CONNECTIONS AND METHOD OF MAKING THE SAME

A die package having mixed impedance leads where a first lead has a first metal core (130), and a dielectric layer surrounding the first metal core (130), and a second lead has a second metal core, and a second dielectric layer (132) surrounding the second metal core, with the dielectric thicknesses differing from each other. A method of making a die package having leads with different impedances formed by cleaning die substrate connection pads (162), connecting the die package to the die substrate connection pads via a first wirebond having a first diameter metal core (164), depositing at least one layer of dielectric on the wirebond metal core (170), metalizing the at least one layer of dielectric (174), connecting the die package to the die substrate connection pads via a second wirebond having a second diameter metal core, depositing at least one layer of dielectric on the second wirebond second diameter metal core, and metalizing the at least one layer of dielectric on the second diameter ...

MIXED IMPEDANCE BOND WIRE CONNECTIONS AND METHOD OF MAKING THE SAME

A die package having mixed impedance leads where a first lead has a first metal core (130), and a dielectric layer surrounding the first metal core (130), and a second lead has a second metal core, and a second dielectric layer (132) surrounding the second metal core, with the dielectric thicknesses differing from each other. A method of making a die package having leads with different impedances formed by cleaning die substrate connection pads (162), connecting the die package to the die substrate connection pads via a first wirebond having a first diameter metal core (164), depositing at least one layer of dielectric on the wirebond metal core (170), metalizing the at least one layer of dielectric (174), connecting the die package to the die substrate connection pads via a second wirebond having a second diameter metal core, depositing at least one layer of dielectric on the second wirebond second diameter metal core, and metalizing the at least one layer of dielectric on the second diameter ...

HALO-HYDROCARBON POLYMER COATING

In some embodiments, a printed circuit board (PCB) comprises a substrate comprising an insulating material. The PCB further comprises a plurality of conductive tracks attached to at least one surface of the substrate. The PCB further comprises a multi-layer coating deposited on the at least one surface of the substrate. The multi-layer coating (i) covers at least a portion of the plurality of conductive tracks and (ii) comprises at least one layer formed of a halo-hydrocarbon polymer. The PCB further comprises at least one electrical component connected by a solder joint to at least one conductive track, wherein the solder joint is soldered through the multi-layer coating such that the solder joint abuts the multilayer coating.

METHOD FOR THE WAFER-LEVEL INTEGRATION OF SHAPE MEMORY ALLOY WIRES

The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.

METHOD FOR PRODUCING AN ELECTRONIC CIRCUIT ASSEMBLY

There is disclosed herein a method for producing a wirebonded electronic circuit assembly which obviates the need for soldering aluminum-copper wirebond pads to substrate mounting pads and other copper bonding surfaces.

POLYGON REPRESENTATION IN AN INTEGRATED CIRCUIT LAYOUT

An approach for representing polygons in an integrated circuit (IC) layout i s provided. Polygons are represented by one or more wires, which in turn are each represented by one or more wire segments. Each wire segment is represented by a pair of directed line segments. A data structure hierarchy includes polygon data, wire data, wire segment data and branch data. The polygon data represents a set of IC devices to be represented in the IC layout. The wire data represents the wires that represent the polygons and specifies the associated wire segments and associated polygons. The wire segment data represents the wire segments and specifies the associated directed line segments for each wire segment that represent the wires and references the wire data. The branch data specifies connections between wires by specifying the connecting wire segments in the wires. A spacing che ck between a first polygon and a second polygon involves determining the canonical direction from the first polygon ...

Verfahren zum Anschluss eines elektrischen Zuführungsleiters an einen Teil eines elektrischen Gerätes, insbesondere eines Sperrschichtgleichrichters.

Procédé d'établissement d'une liaison entre un conducteur métallique et un élément semi-conducteur

Werkzeug zum permanenten Befestigen eines Drahtes an einer Fläche

Verfahren zum Herstellen einer in einem Schutzgehäuse untergebrachten, mindestens zwei nebeneinander einlegierte Metallelektroden aufweisenden Halbleiterkristallanordnung

Verfahren zum Kontaktieren von Halbleiteranordnungen oder anderen elektrischen Bauelementen mit mindestens zwei eng nebeneinanderliegenden, kleinflächigen Kontaktstellen

Outil pour fixer un fil conducteur d'électricité à la surface d'un semi-conducteur

Vorrichtung zum Kontaktieren einer Halbleiteranordnung mittels Thermokompression

Träger mit mindestens einer Mikroschaltanordnung und Verfahren zu seiner Herstellung

Verfahren zur Herstellung eines Halbleiterbauelementes, wobei das Anbringen elektrischer Verbindungen zwischen Kontaktstellen des Halbleiterbauelementes einerseits und Zuführungsleitern andererseits ein Werkzeug verwendet wird

Vorrichtung zur Positionierung eines Werkzeugs

Procédé d'établissement de liaisons électriques des parties espacées d'un conducteur flexible allonge et des éléments conducteurs espacés d'un dispositif électrique, et appareil pour la mise en oeuvre de ce procédé

VERFAHREN ZUM BEFESTIGEN EINES DRAHTES AN EINEM HALBLEITERKOERPER.

VERFAHREN ZUM FORTLAUFENDEN HERSTELLEN MINDESTENS EINER DRAHTVERBINDUNG IN HALBLEITER-BAUTEILEN UND VORRICHTUNG ZUR AUSFUEHRUNG DES VERFAHRENS.

Welding of contact blobs to semiconductor lead wires - uses electric DC light arc of preset current strength for melting lead wire end

Contact blobs are formed at the ends of lead wires for electric, preferably semiconductor, components in a process using a direct current light arc, whose current has been stabilised to a desired current strength, while the duration of the light arc has been limited to a certain time period. The equipment contains a high voltage storage capacitor (2) whose discharge circuit incorporates the arc spark gap (b) between the lead wire (3) and a counter-electrode (7). The capacitor discharge circuit contains an electron tube in grid-base connection and a current stabiliser, both in line with the arc spark gap.

In ein Gehäuse eingebaute Halbleiteranordnung

Active energy ray-curable pressure-sensitive adhesive for re-release and dicing die-bonding film

Provided is an active energy ray-curable pressure-sensitive adhesive for re-release, which has a small influence on an environment or a human body, can be easily handled, can largely change its pressure-sensitive adhesiveness before and after irradiation with an active energy ray, and can express high pressure-sensitive adhesiveness before the irradiation with the active energy ray and express high releasability after the irradiation with the active energy ray. The active energy ray-curable pressure-sensitive adhesive for re-release includes an active energy ray-curable polymer (P), in which the polymer (P) includes one of a polymer obtained by causing a carboxyl group-containing polymer (P3) and an oxazoline group-containing monomer (m3) to react with each other, and a polymer obtained by causing an oxazoline group-containing polymer (P4) and a carboxyl group-containing monomer (m2) to react with each other.

Power Semiconductor Module, Method for Producing a Power Semiconductor Module and a Housing Element for a Power Semiconductor Module

A power semiconductor module includes a housing element into which one or more connecting lugs are inserted. Each connecting lug has a foot region on the topside of which one or more bonding connections can be produced. In order to fix the foot regions, press-on elements are provided, which press against the end of the connecting lug.

Gas delivery system for reducing oxidation in wire bonding operations

A wire bonding machine is provided. The wire bonding machine includes a bonding tool and an electrode for forming a free air ball on an end of a wire extending through the bonding tool where the free air ball is formed at a free air ball formation area of the wire bonding machine. The wire bonding machine also includes a bond site area for holding a semiconductor device during a wire bonding operation. The wire bonding machine also includes a gas delivery mechanism configured to provide a cover gas to: (1) the bond site area whereby the cover gas is ejected through at least one aperture of the gas delivery mechanism to the bond site area, and (2) the free air ball formation area.

Stitch bump stacking design for overall package size reduction for multiple stack

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Packaging Integrated Circuits

An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

Power/ground layout for chips

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

Semiconductor package device with a heat dissipation structure and the packaging method thereof

The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

Method for manufacturing semiconductor device

In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads. This method includes a step of removing a sealing resin filled between the circumference of a mold cavity and the dam bar by using laser and then carrying out surface treatment, for example, solder plating.

Semiconductor Device

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Semiconductor device

A semiconductor device is configured that two or more semiconductor elements are stacked and mount on a lead frame, the aforementioned lead frame is electrically joined to the semiconductor element with a wire, and the semiconductor element, the wire and an electric junction are encapsulated with a cured product of an epoxy resin composition for encapsulating semiconductor device, and that the epoxy resin composition for encapsulating semiconductor device contains (A) an epoxy resin; (B) a curing agent; and (C) an inorganic filler, and that the (C) inorganic filler contains particles having particle diameter of equal to or smaller than two-thirds of a thinnest filled thickness at a rate of equal to or higher than 99.9% by mass.

Semiconductor device and method of manufacturing the semiconductor device

Disclosed are: a semiconductor device that comprises a semiconductor element to which a plurality of wires are bonded, wherein bonding strength of the wires is high and sufficient bonding reliability is achieved; and a method for manufacturing the semiconductor device. Specifically disclosed is a semiconductor device which is characterized by comprising a first wire that has one end bonded onto an electrode and the other end bonded to a second bonding point that is out of the electrode, and a second wire that has one end bonded onto the first wire on the electrode and the other end bonded to a third bonding point that is out of the electrode. The semiconductor device is also characterized in that the bonded portion of the first-mentioned end of the second wire covers at least apart of the upper surface and the lateral surface of the first wire.

Method of manufacturing film for semiconductor device

The present invention aims to provides a method of manufacturing a film for a semiconductor device in which a dicing film, a die bond film, and a protecting film are laminated in this order, including the steps of: irradiating the die bond film with a light ray having a wavelength of 400 to 800 nm to detect the position of the die bond film based on the obtained light transmittance and punching the dicing film out based on the detected position of the die bond film, and in which T 2 /T 1 is 0.04 or more, wherein T 1 is the light transmittance of the portion where the dicing film and the protecting film are laminated and T 2 is the light transmittance of the portion where the dicing film, the die bond film, and the protecting film are laminated.

Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer

When forming complex metallization systems on the basis of copper, the very last metallization layer may receive contact regions on the basis of copper, the surface of which may be passivated on the basis of a dedicated protection layer, which may thus allow the patterning of the passivation layer stack prior to shipping the device to a remote manufacturing site. Hence, the protected contact surface may be efficiently re-exposed in the remote manufacturing site on the basis of an efficient non-masked wet chemical etch process.

Manufacturing method of semiconductor device, and semiconductor device

To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

Unpackaged and packaged IC stacked in a system-in-package module

There is provided a system and method for unpackaged and packaged IC stacked in a system-in-package module. There is provided a system-in-package module comprising a substrate including a first contact pad and a second contact pad disposed thereon, a packaged device disposed on the substrate, and an unpackaged device stacked atop the packaged device, wherein a first electrode of the packaged device is electrically and mechanically coupled to the first contact pad, and wherein a second electrode of the unpackaged device is electrically coupled to the second contact pad. The structure of the disclosed system-in-package module provides several advantages over conventional designs including increased yields, facilitated die substitution, enhanced thermal and grounding performance through direct connect vias, stacking of wider devices without a spacer, and a simplified single package structure for reduced fabrication time and cost.

Integrated circuit packaging system with lead frame etching and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a pre-plated leadframe having a contact pad and a die paddle pad; forming an isolated contact from the pre-plated leadframe and the contact pad; mounting an integrated circuit die over the die paddle pad; and encapsulating with an encapsulation the integrated circuit die and the isolated contact, the encapsulation having a bottom surface which is planar and exposing in the bottom surface only the contact pad and the die paddle pad.

Method for making circuit board

A method for making the same is disclosed. First, a first substrate and a second substrate are provided. The first substrate includes a release film attached to a carrier. The second substrate includes a copper film covered with a solder mask. Second, the solder masked is patterned. Next, the release film and the patterned solder mask are pressed together so that the first substrate is attached to the second substrate. Then, the copper film is patterned to form a first pattern and a second pattern. The first pattern is in direct contact with the release film and the second pattern is in direct contact with the patterned solder mask. Later, a passivation is formed to cover the first pattern and the second pattern to form a circuit board structure. Afterwards, a package is formed on the carrier to form a packaging structure.

Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof

A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

Die attach film

Provided are a die attach film, a semiconductor wafer, and a semiconductor packaging method. The die attach film can prevent generation of burrs or scattering of chips in a dicing process, and exhibits excellent expandability and pick-up characteristics in a die pressure-sensitive adhesive process. Further, the die attach film can prevent release, shifting, or deflection of a chip in a wire pressure-sensitive adhesive or molding process. Thus, it is possible to improve embeddability, inhibit warpage of a wafer or wiring substrate, and enhance productivity in a semiconductor packaging process.

Support structures and clamping systems for semiconductor devices during wire and ribbon bonding operations

A support structure for supporting a semiconductor device during a bonding operation is provided. The support structure comprises a body portion defining an upper surface configured to support a semiconductor device during a bonding operation. The upper surface defines a constraining feature for constraining at least a portion of the semiconductor device during the bonding operation.

Method for Producing a Metal Layer on a Substrate and Device

A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.

Method of manufacturing semiconductor device

Provided is a technology of suppressing, in forming an initial ball by using an easily oxidizable conductive wire and pressing the initial ball onto a pad to form a press-bonded ball, an initial ball from having a shape defect, thereby reducing damage to the pad. To achieve this, a ball formation unit is equipped with a gas outlet portion for discharging an antioxidant gas and a discharging path through this gas outlet portion is placed in a direction different from a direction of introducing the antioxidant gas into a ball formation portion. Such a structure widens a region for discharging the antioxidant gas, making it possible to prevent a gas flow supplied from the side of one side surface of the ball formation portion from being reflected by the other side surface facing with the one side surface and thereby forming a turbulent flow.

Saw Type Package without Exposed Pad

In one embodiment, a method for manufacturing a saw type pad is provided. The method includes performing a first molding process to form a first molded layer beneath a pad of a lead frame. A semiconductor device is placed on the pad. A second molding process is performed to form a second molded layer. The first molded layer and the second molded layer form an encapsulation to enclose the semiconductor device and the pad. The lead frame is singulated to form an individualized semiconductor package. The pad is not exposed from a bottom surface of the semiconductor package.

Method of manufacturing semiconductor device

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Semiconductor device and method for manufacturing same

A dug portion ( 50 ) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle ( 42 ) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion ( 50 ) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion ( 50 ) is smaller than a thickness of the chip. When the thickness of the chip is 100 μm or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle ( 42 ).

Semiconductor device and method of packaging same

A Quad Flat Pack (QFP) device includes a semiconductor die attached to a flag of a lead frame. Bonding pads of the die are electrically connected to inner and outer rows of leads of the lead frame with bond wires. The die, die flag, bond wires and portions of the inner and outer leads are covered with a mold compound, which defines a package body. The outer leads are similar to the gull-wing leads of a conventional QFP device while the inner leads form contact points at a bottom surface of the package body. A cut is performed on an inner side of the inner leads to separate the inner leads from the die pad.

Package-on-package structures

Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

Semiconductor device including cladded base plate

A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.

Low loop wire bonding

A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads positioned thereon. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires includes a first portion extending upward from one of the second plurality of bond pads substantially along a z-axis and curving outward substantially along x and y axes in a direction towards the first semiconductor die. The bonding wire also includes a second portion coupled to the first portion and extending from the first portion downward to one of the first plurality of bond pads on the upper surface of the first semiconductor die.

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Semiconductor device and fabrication method therefore

Various embodiments of the present invention include a semiconductor device and a fabrication method therefore, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device and a fabrication method therefore, in which downsizing and cost reduction can be realized.

METHOD OF FABRICATING A SEMICONDUCTOR DEVICE HAVING AN INTERPOSER

The method of fabricating a semiconductor device may include forming a semiconductor die on a substrate, forming an interposer including at least one integrated circuit connected to the semiconductor die on the substrate or on the semiconductor die, and performing encapsulation to surround the semiconductor die and the interposer. 1. A method of fabricating a semiconductor device , the method comprising:forming a semiconductor die on a substrate;forming an interposer including at least one integrated circuit connected to the semiconductor die therein on the substrate or on the semiconductor die; andperforming encapsulation to surround the semiconductor die and the interposer.2. The method of claim 1 , wherein the interposer comprises a plurality of integrated circuits to be selectively connected to the semiconductor die.3. The method of claim 1 , wherein the interposer is selectively connected to the semiconductor die through conductive wires or is selectively connected to the semiconductor die by removing parts of fuse that constituting wiring lines by laser.4. The method of claim 1 , further comprising:forming side interposers electrically connected to the semiconductor die and/or interposers on the sides of the semiconductor die and/or interposer between forming the interposer and performing encapsulation. The present application is a divisional of U.S. patent application Ser. No. 12/535,316, entitled SEMICONDUCTOR DEVICE HAVING AN INTERPOSER, filed on Aug. 4, 2009, and incorporated herein by reference in its entirety.1. Field of the InventionThe present invention relates to a semiconductor device including an interposer and a method of fabricating the same.2. Description of the Related ArtSince recent semiconductor devices are required to have high capacities and high performance, in constituting one semiconductor device, a plurality of semiconductor dies are stacked in many cases. When the semiconductor dies are stacked, it is difficult to supply electric power ...

Large panel leadframe

A method of manufacturing an integrated circuit package includes mounting a large panel leadframe having a substantially square shape to a ring. The large panel leadframe includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern. An integrated circuit chip is attached to each of the die pads. An encapsulant material is applied over the integrated circuit chips and at least a part of the large panel leadframe. Each of the die pads and its corresponding leads are separated from the large panel leadframe to form individual integrated circuit packages. The steps of attaching the integrated circuit chips and applying the encapsulant material are performed while the large panel leadframe is mounted to a taped ring.

Ribbon bonding tools and methods of using the same

A ribbon bonding tool including a body portion is provided. The body portion includes a tip portion. The tip portion includes a working surface between a front edge of the tip portion and a back edge of the tip portion. The working surface includes a region defining at least one of a plurality of recesses and a plurality of protrusions. The working surface also defines at least one of ( 1 ) a first planar portion between the region and the front edge of the tip portion, and ( 2 ) a second planar portion between the region and the back edge of the tip portion.

Wire loops, methods of forming wire loops, and related processes

A method of forming a wire loop is provided. The method includes the steps of: ( 1 ) forming a conductive bump on a bonding location using a wire bonding tool; ( 2 ) bonding a portion of wire to another bonding location using the wire bonding tool; ( 3 ) extending a length of wire from the bonded portion of wire toward the bonding location; ( 4 ) lowering the bonding tool toward the bonding location while detecting a height of a tip of the wire bonding tool; and ( 5 ) interrupting the lowering of the wire bonding tool during step ( 4 ) if the wire bonding tool reaches a predetermined height.

Integrated circuit including a differential power amplifier with a single ended output and an integrated balun

An integrated circuit, including, a die with an electronic circuit embedded thereon; wherein the electronic circuit includes a differential power amplifier and pads to electronically interface with the electronic circuit; a packaging encasing the die with contact pins to connect between the integrated circuit and external elements; wires connecting between the pads and the contact pins; a converter that includes capacitors and inductors to combine the outputs from the differential power amplifier to form a single ended output at one of the contact pins; wherein inherent inductance of some of the wires serve as the inductors of the converter.

Integrated Circuit Having Stress Tuning Layer and Methods of Manufacturing Same

Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Resin Sealed Semiconductor Device And Manufacturing Method Therefor

A semiconductor device includes a thermoplastic resin case, a semiconductor chip mounted within the thermoplastic resin case, a metal terminal having a wire bonding surface and an opposing contact surface, and a wire connected between the wire bonding surface and the semiconductor chip. The contact surface of the metal terminal is thermoplastically bonded at an area to the inside of the thermoplastic resin case.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device permitting the reduction of cost is disclosed. In a semiconductor package wherein electrode pads of a semiconductor chip and corresponding inner leads are electrically coupled with each other through a plurality of bonding wires, sensing wires (second and fourth bonding wires) are made thinner than other bonding wires (first and third bonding wires) coupled to inner leads same as those with the sensing wires coupled thereto, thereby reducing the cost of gold wires to attain the reduction in cost of the semiconductor package. 114-. (canceled)15. A method for manufacturing a semiconductor device , comprising the steps of:providing a lead frame having a chip mounting area and a plurality of leads arranged around the chip mounting area; mounting a semiconductor chip having a plurality of electrode pads over the chip mounting area of the lead frame; coupling the leads and the electrode pads of the semiconductor chip electrically with each other through a plurality of bonding wires; and forming a resinous sealing body to seal the semiconductor chip, the bonding wires and a portion of the leads, wherein the bonding wires include: a first bonding wire coupled at one end portion thereof to a first electrode pad out of the electrode pads and at an opposite end portion thereof to a first lead out of the leads; and a second bonding wire coupled at one end portion thereof to a second electrode pad out of the electrode pads and at an opposite end portion thereof to the first lead and being thinner than the first bonding wire, and wherein the second bonding wire is formed later than the first bonding wire.16. The method according to claim 15 , wherein the bonding wires including the first and second bonding wires are formed by a ball bonding method which forms a ball-like electrode at a tip of a capillary claim 15 , wherein the opposite end portions of the first and second bonding wires are portions located on a side opposite to the ball-like electrode claim ...

Processes and structures for IC fabrication

The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.

Wire bonding method in circuit device

A wire bonding method in a circuit device mounted on a lead frame, the wire bonding method including: counting a stop time if an operation of a capillary stops; removing a contaminated free air ball (FAB) formed on an end of the capillary if the stop time exceeds a reference time; forming a new FAB; and restarting a wire bonding process.

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer. 1. A microelectronic package comprising:a substrate having a first region and a second region, the substrate also having a first surface and a second surface remote from the first surface;at least one microelectronic element overlying the first surface within the first region;electrically conductive elements exposed at the first surface of the substrate within the second region, at least some of the conductive elements being electrically connected to the at least one microelectronic element;wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases, the ends of the wire bonds being defined on tips of the wire bonds, the wire bonds defining respective first diameters between the bases and the tips thereof, and the tips having at least one dimension that is smaller than the respective first diameters of the wire bonds; anda dielectric encapsulation layer extending from at least one of the first or second surfaces and covering portions of the wire bonds such that covered ...

SEMICONDUCTOR DEVICE

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other. 1. A semiconductor device comprising:a first chip mounting section, a second chip mounting section and a third chip mounting section respectively disposed at predetermined intervals;a plurality of external terminals disposed around the first, second and third chip mounting sections;a first semiconductor chip disposed over the first chip mounting section and having a first field effect transistor;a second semiconductor chip disposed over the second chip mounting section and having a second field effect transistor;a third semiconductor chip disposed over the third chip mounting section and including control circuits for controlling the operations of the first and second field effect transistors; anda resin body that encapsulates the first, second and third semiconductor chips, the first, second and third chip mounting sections and some of the plurality of external terminals,wherein the plurality of external terminals include a first power supply terminal that supplies an input power supply potential, a second power supply terminal that supplies a potential lower than the input power supply potential, signal terminals that control the control circuits of the third semiconductor chip, and an output terminal that outputs an output power supply potential to the outside,wherein the first field effect ...

PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES

Packaged microelectronic devices and methods of manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a stand-off layer over a plurality of microelectronic dies on a semiconductor workpiece, and removing selected portions of the stand-off layer to form a plurality of stand-offs with the individual stand-offs positioned on a backside of a corresponding die. The method further includes cutting the semiconductor workpiece to singulate the dies, and attaching the stand-off on a first singulated die to a second die. 1. A method of manufacturing a microelectronic device , the method comprising:molding a stand-off structure;forming an adhesive layer on the stand-off structure;cutting the stand-off structure to form a plurality of stand-offs;attaching a first microelectronic die to a support member;coupling a first singulated stand-off to the first die; andconnecting a second microelectronic die to the first singulated stand-off2. The method of wherein molding a stand-off structure comprises forming a stand-off structure having a first major surface and a second major surface opposite the first major surface claim 1 , and wherein the first and second major surfaces are exposed.3. The method of wherein:the stand-off structure comprises a first major surface and a second major surface opposite the first major surface;forming the adhesive layer comprises disposing a first adhesive layer on the first major surface; andthe method further comprises placing a second adhesive layer on the second major surface.4. The method of wherein:attaching the first die to the support member comprises connecting a backside of the first die to the support member; andcoupling the first singulated stand-off to the first die comprises attaching the first singulated stand-off to an active side of the first die.5. The method of wherein:coupling the first singulated stand-off to the first die ...

Heavy-wire bond arrangement and method for producing same

The invention relates to a heavy-wire bond arrangement, having a substrate ( 2 ), a heavy wire ( 1 ) and a high-voltage heavy-wire bond connection, in which an end bond section ( 4 ) of the heavy wire ( 1 ), which extends towards the end ( 7 ) of the heavy wire ( 1 ), is bonded to the substrate ( 2 ), such that in the area of the bond section ( 4 ) a bond contact ( 5 ) between the heavy wire ( 1 ) and the substrate ( 2 ) is formed, the heavy wire ( 1 ) having a tapering section ( 6 ) which adjoins the end of the wire ( 7 ) and in which the wire cross-section tapers towards the end of the wire ( 7 ). The application additionally relates to a method for producing a heavy-wire bond arrangement.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Terminal assembly portions, lying on a front surface side of a case, are aligned in a left-right direction in a portion raised from a bottom of the case so that opening faces of the terminal assembly portions are positioned above circuit formation regions. Wiring terminal plates are led out into the terminal assembly portions, and disposed adjacent to each other. After each wiring terminal plate is connected by a laser welding to one end of one external connection terminal plate formed integrally with a cover, these welded portions are sealed with a second mold resin portion made of gel or an insulating resin such as epoxy. By so doing, even when the terminal junction area and distance between terminal junctions in the terminal assembly portions are small, it is possible to increase the joint strength of the terminals, and also secure withstand voltage. 1. A semiconductor device comprising:a case;a circuit formation region disposed in the case and including a plurality of semiconductor elements,a plurality of wiring terminal plates, each of which is electrically connected to one of the plurality of semiconductor elements;a terminal assembly portion where the plurality of wiring terminal plates led out from the circuit formation region is gathered;a plurality of external connection terminal plates, each having one end connected to one of the plurality of wiring terminal plates in the terminal assembly portion, and another end extended to external terminal portions disposed on the case; anda mold resin portion which insulates and protects connections of the wiring terminal plates and external connection terminal plates with a resin with which the terminal assembly portion is filled.2. The semiconductor device according to claim 1 , wherein the external terminal portions are disposed to be spread claim 1 , on an. outer peripheral portion of the case.3. The semiconductor device according to claim 1 , wherein the plurality of wiring terminal plates has connections for ...

Manufacturing method of semiconductor device

A manufacturing yield of a semiconductor device including a power transistor is improved. When forming a tip portion LE 1 c of a first lead, a tip portion LE 2 c of a second lead, and a tip portion LE 3 c of a third lead by using a spanking die SDM 1 , the tip portion LE 1 c of the first lead, the tip portion LE 2 c of the second lead, and the tip portion LE 3 c of the third lead are pressed by an upper surface of a protrusion portion provided on a pressing surface of a lower die SD 1 and a bottom surface of a groove portion provided in a pressing surface of an upper die SU 1 , and a bent portion of the second lead and a bent portion of the third lead are pressed by a flat pressing surface of the lower die SD 1 and a flat pressing surface of the upper die SU 1.

Semiconductor devices including electromagnetic interference shield

Provided are a semiconductor device including an EMI shield, a method of manufacturing the same, a semiconductor module including the semiconductor device, and an electronic system including the semiconductor device. The semiconductor device includes a lower semiconductor package, an upper semiconductor package, a package bump, and an EMI shield. The lower semiconductor package includes a lower substrate, a lower semiconductor chip mounted on the lower substrate, and a ground wire separated from the lower semiconductor chip. The upper semiconductor package includes an upper substrate stacked on the lower semiconductor package, and an upper semiconductor chip stacked on the upper substrate. The package bump electrically connects the upper semiconductor package and the lower semiconductor package. The EMI shield covers the upper and lower semiconductor packages and is electrically connected to the ground wire.

Lead frame with grooved lead finger

A lead finger of a lead frame has a number of channels or grooves in a portion of its top surface that provide a locking mechanism for securing a bond wire to the lead finger. The bond wire may be attached to the lead finger by stitch bonding.

Methods of adjusting ultrasonic bonding energy on wire bonding machines

A method of adjusting ultrasonic bonding energy on a wire bonding machine, the method comprising the steps of: providing a reference relationship between free air ball squash and ultrasonic bonding energy; determining an actual relationship between free air ball squash and ultrasonic bonding energy on a subject wire bonding machine; and adjusting at least one ultrasonic bonding energy setting of the subject wire bonding machine such that the actual relationship of the subject wire bonding machine is closer to the reference relationship.

Semiconductor device

A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.

METHOD FOR THE WAFER-LEVEL INTEGRATION OF SHAPE MEMORY ALLOY WIRES

The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. 1. A method to attach a wire to a substrate , wherein said wire is mechanically attached into a 3D structure on said substrate , wherein said wire is mechanically fixated with the help of one anchor and one clamp structure on said substrate , and wherein each fixation pair is placed on opposite sides of a wafer edge.2. The method according to claim 1 , wherein claim 1 , while using a wirebonder claim 1 , a free air ball is generated at the end of said wire by an electrical discharge claim 1 , that said ball is anchored in said anchor structure claim 1 , wherein said wire is fed and guided over the entire wafer area to said clamp structure claim 1 , and wherein said wire is clamped in between silicon cantilevers and finally cut off by truncating the wire by the bond capillary and a high bond force.3. A device comprising a wire attached to a substrate claim 1 , wherein said wire has been mechanically attached into a 3D structure on said substrate claim 1 , wherein said substrate comprises at least one anchor and one clamp structure placed on opposite sides of a wafer edge forming a fixation pair claim 1 , and that wherein said wire has been mechanically fixated with the help of said anchor and said clamp structure. The present invention relates to a method to attach a shape memory alloy wire to a substrate, and a device comprising a shape memory alloy wire attached to a substrate.Shape memory alloy (SMA) is an attractive actuator material to use in microelectromechanical systems (MEMS) when high forces and work are needed. SMA outperforms most other actuation principles at the microscale by more than an order of ...

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

CHIP PACKAGE AND METHOD FOR FORMING THE SAME

An embodiment of the invention provides a chip package, which includes: a substrate having an upper surface and a lower surface; a passivation layer located overlying the upper surface of the substrate; a plurality of conducting pad structures disposed overlying the upper surface of the substrate, wherein at least portions of upper surfaces of the conducting pad structures are exposed; a plurality of openings extending from the upper surface towards the lower surface of the substrate; and a plurality of movable bulks located between the openings and connected with the substrate, respectively, wherein each of the movable bulks is electrically connected to one of the conducting pad structures. 1. A method for forming a chip package , comprising:providing a substrate having an upper surface and a lower surface;disposing a passivation layer and a package layer overlying the upper surface of the substrate;disposing a spacer layer between the upper surface of the substrate and the package layer;disposing a plurality of conducting pad structures overlying the upper surface of the substrate, wherein at least portions of upper surfaces of the conducting pad structures are exposed;forming a plurality of openings extending from the upper surface towards the lower surface of the substrate; anddisposing a plurality of movable bulks between the openings and connected with the substrate, respectively, wherein each of the movable bulks is electrically connected to one of the conducting pad structures, and wherein the substrate, the spacer layer, and the package layer together form a cavity, and the openings and the movable bulks are located underlying the cavity.2. The method for forming a chip package as claimed in claim 1 , wherein the openings connect with each other.3. The method for forming a chip package as claimed in claim 1 , further comprising forming a trench extending from the lower surface towards the upper surface of the substrate claim 1 , wherein a bottom portion of ...

SHORT AND LOW LOOP WIRE BONDING

A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads disposed thereon. The upper surface of the second semiconductor die may be substantially coextensive with the upper surface of the first semiconductor die and extend substantially along a plane. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires has a kink disposed at a height above the plane, a first hump disposed between the first semiconductor die and the kink, and a second hump disposed between the second semiconductor die and the kink. 120-. (canceled)21. A semiconductor package comprising:a first contact having an upper surface;a second contact having an upper surface, the upper surface of the first contact and the upper surface of the second contact being at substantially a same height and extending substantially along a plane; and a first length extending upward from the second contact to the first hump;', 'a second length coupled to the first length at the first hump, the second length extending downward from the first hump to the kink, the kink disposed at a height above the upper surface of the first contact and the upper surface of the second contact;', 'a third length coupled to the second length at the kink, the third length extending upward from the kink to the second hump; and', 'a fourth length coupled to the third length at the second hump, the fourth length extending from the second hump to the first contact, wherein the fourth length comprises an upper portion and a lower portion coupled at a second kink spaced from the second hump, the upper portion coupled to the third length at the second hump and extending to the second kink, and the lower portion extending ...

Package-on-package assembly with wire bond vias

A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.

Wedge bonder and a method of cleaning a wedge bonder

Disclosed is a wedge bonder, comprising a wedge for bonding a wire to surfaces to form an electrical interconnection therebetween, a cleaning device for cleaning the wedge, and a positioning device to which the wedge is mounted. In particular, the positioning device is operative to move the wedge to the cleaning device for cleaning. A method of cleaning a wedge of a wedge bonder is also disclosed.

Miniature Surface Mount Device

A surface mount LED package includes a lead frame carrying a plurality of LEDs and a plastic casing at least partially encasing the lead frame. The lead frame includes an electrically conductive chip carrier and first, second, and third electrically conductive connection parts separate from the electrically conductive chip carrier. Each of the first, second and third electrically conductive connection parts has an upper surface, a lower surface, and a connection pad on the upper surface. The plurality of LEDs are disposed on an upper surface of the electrically conductive chip carrier. Each LED has a first electrical terminal electrically coupled to the electrically conductive chip carrier. Each LED has a second electrical terminal electrically coupled to the connection pad of a corresponding one of the first, second, and third electrically conductive connection parts.

ADHESIVE FILM, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

The present invention aims to provide an adhesive film that enables manufacturing of a high quality semiconductor device with good yield ratio, a method of manufacturing a semiconductor device using the same, and a semiconductor device obtained by the manufacturing method. This object is achieved by an adhesive film for embedding a first semiconductor element fixed to an adherend and fixing a second semiconductor element that is different from the first semiconductor element to the adherend, wherein the adhesive film has a thickness T that is larger than a thickness Tof the first semiconductor element, and the adherend and the first semiconductor element are connected by wire bonding and a difference between the thickness T and the thickness Tis 40 μm or more and 260 μm or less, or the adherend and the first semiconductor element are connected by flip-chip bonding and a difference between the thickness T and the thickness Tis 10 μm or more and 200 μm or less. 1. An adhesive film for embedding a first semiconductor element fixed to an adherend and fixing a second semiconductor element that is different from the first semiconductor element to the adherend , wherein{'sub': '1', 'the adhesive film has a thickness T that is larger than a thickness Tof the first semiconductor element, and'}{'sub': '1', 'the adherend and the first semiconductor element are connected by wire bonding and a difference between the thickness T and the thickness Tis 40 μm or more and 260 μm or less, or'}{'sub': '1', 'the adherend and the first semiconductor element are connected by flip-chip bonding and a difference between the thickness T and the thickness Tis 10 μm or more and 200 μm or less.'}2. The adhesive film according to claim 1 , wherein the adherend and the first semiconductor element are connected by wire bonding claim 1 , and the thickness T is 80 μm or more and 300 μm or less.3. The adhesive film according to claim 1 , wherein the adherend and the first semiconductor element are ...

Method of manufacturing semiconductor device

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2 . When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Semiconductor chips having improved solidity, semiconductor packages including the same and methods of fabricating the same

Semiconductor chips are provided. The semiconductor chip includes a semiconductor chip body having an arch-shaped groove in a backside thereof and a non-conductive material pattern filling the arch-shaped groove. Related methods are also provided.

Very extremely thin semiconductor package

A package and method of making thereof. The package includes a first plated area, a second plated area, a die, a bond, and a molding. The die is attached to the first plated area, and the bond couples the die to the first and/or the second plated areas. The molding encapsulates the die, the bonding wire, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package.

Semiconductor package and method of fabricating the same

A semiconductor package includes a first semiconductor chip including a first chip pad located on an upper surface thereof, a second semiconductor chip offset-stacked on the upper surface of the first semiconductor chip and including a second chip pad located on an upper surface thereof, a chip coupling ball located on a first board pad of the first semiconductor chip, a chip coupling bump located on a second board pad of the second semiconductor chip, and a chip connection wire connecting the chip coupling ball and the chip coupling bump. The chip connection wire has a chip connection curve part with a reverse curve shape.

MICROELECTRONIC PACKAGES HAVING CAVITIES FOR RECEIVING MICROELECTRONIC ELEMENTS

Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts. 1. A packaged microelectronic element comprising:a package element having a top face, a bottom face, and an edge extending between said top and bottom faces, a plurality of chip contacts and package contacts exposed at said top face;a microelectronic element having a front face, a rear face, an edge extending between said top and bottom faces, and a plurality of bond pads exposed at said top face; andbond wires electrically connecting said bond pads to said chip contacts, said bond wires extending across said edges of said microelectronic element and said package element.2. The packaged microelectronic element as claimed in claim 1 , wherein said bond wires extend across a gap disposed between said edges of said microelectronic element and said package element.3. The packaged microelectronic element as claimed in claim 1 , wherein said package contacts are disposed adjacent to said chip contacts.4. The packaged microelectronic element as claimed in claim 1 , wherein each of said package contacts is connected to an adjacent one of said chip contacts.5. The packaged microelectronic element as claimed in claim 1 , wherein said package element is elongated in a first direction claim 1 , said chip contacts and said package contacts extending in said first direction.6. The packaged microelectronic element as claimed in claim 1 , as claimed in claim 1 , wherein said chip contacts are disposed in at least one row adjacent to and extending parallel to said edge of said package element.7. The packaged microelectronic element as claimed in claim 6 , wherein said edge of said package element is a first edge claim 6 , said package element including a second edge opposite said first edge claim 6 , wherein said chip contacts are ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes: at least one semiconductor element having electrode terminals; a metal plate supporting the semiconductor element; and a wiring board covering the semiconductor element and including a plurality of insulating layers and wiring layers alternately stacked and external connection terminals on a surface, the wiring layers being electrically connected to each other by vias. The electrode terminals and the external connection terminals are electrically connected via at least one of the wiring layers and the vias. At least one of the electrode terminals, the wiring layers, and the vias is electrically connected to the metal plate. 1. A semiconductor device manufacturing method comprising:mounting a semiconductor element on a metal plate, with a surface on which electrode terminals are arranged up;forming a first insulating layer covering the semiconductor element on the metal plate;forming a second via running through the first insulating layer on the metal plate;forming a first wiring layer on the first insulating layer including the second via; andforming a wiring board on the first insulating layer including the first wiring layer, thewiring board including a plurality of insulating layers and wiring layers alternately stacked, thewiring layers being connected to each other by vias.2. A semiconductor device manufacturing method comprising:forming a metal post on a metal plate;mounting a semiconductor element on a surface of the metal plate on which the metal post is arranged, with a surface on which electrode terminals are mounted up;forming a first insulating layer covering the semiconductor element and the metal post on the metal plate;removing part of the first insulating layer until a surface of the metal post is exposed;forming a first wiring layer on the first insulating layer including the metal post; andforming a wiring board on the first insulating layer including the first wiring layer, the wiring board including a plurality of ...

Low Stress Package For an Integrated Circuit

A package that electrically connects an integrated circuit to a printed circuit board includes a frame and a package body that encases a portion of the frame and the integrated circuit. The frame includes a mounting region that is connected to the printed circuit board, and a cantilevering region that cantilevers away from the mounting region. The cantilevering region retains the integrated circuit in a flexible fashion. 1. A package for electrically connecting an integrated circuit to a printed circuit board , the package comprising:a first frame that includes a first mounting region that is adapted to be connected to the printed circuit board, and a first cantilevering region that cantilevers away from the first mounting region;a first connector that connects the integrated circuit to the first cantilevering region; anda package body that encases at least a portion of the first frame and the integrated circuit.2. The package of further comprising (i) a second frame that includes a second cantilevering region claim 1 , and a second mounting region that is adapted to be electrically connected to the printed circuit board claim 1 , the second frame being spaced apart from the first frame; and (ii) a second connector that connects the integrated circuit to the second cantilevering region; wherein the package body encases at least a portion for the second frame.3. The package of further comprising (i) a third frame that includes a third cantilevering region claim 2 , and a third mounting region that is adapted to be electrically connected to the printed circuit board claim 2 , the third frame being spaced apart from the first frame and the second frame; and (ii) a third connector that connects the integrated circuit to the third cantilevering region; wherein the package body encases at least a portion for the third frame.4. The package of further comprising (i) a fourth frame that includes a fourth cantilevering region claim 3 , and a fourth mounting region that is ...

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

Double Solid Metal Pad with Reduced Area

An integrated circuit structure includes a bond pad; an Mtop pad located directly underlying the bond pad; an Mtop-1 pad having at least a portion directly underlying the Mtop pad, wherein at least one of the Mtop pad and the Mtop-1 pad has a horizontal dimension smaller than a horizontal dimension of the bond pad; a plurality of vias interconnecting the Mtop pad and the Mtop-1 pad; and a bond ball on the bond pad. Each of the Mtop pad and the Mtop-1 pad has positive enclosures to the bond ball in all horizontal directions. 1. A method comprising: a bond pad;', 'an Mtop pad located directly underlying the bond pad;', 'an Mtop-1 pad having at least a portion directly underlying the Mtop pad, wherein the Mtop pad and the Mtop-1 pad are solid conductive pads electrically coupled to the bond pad, and wherein at least one of the Mtop pad and the Mtop-1 pad has a horizontal dimension smaller than a horizontal dimension of the bond pad; and', 'a plurality of vias interconnecting the Mtop pad and the Mtop-1 pad, wherein the wire bonding forms a bond ball on the bond pad, and wherein each of the Mtop pad and the Mtop-1 pad extends beyond boundaries of the bond ball., 'performing a wire bonding on a bond pad of an integrated circuit structure, wherein the integrated circuit structure comprises2. The method of further comprising forming the integrated circuit structure comprising:forming the Mtop-1 pad;forming the plurality of vias over and connected to the Mtop-1 pad; andforming the Mtop pad over and connected to the plurality of vias.3. The method of claim 1 , wherein each of the Mtop pad and the Mtop-1 pad extends beyond the boundaries of the bond ball by a distance greater than about 2.4 μm.4. The method of claim 3 , wherein the distance is greater than about 4 μm.5. The method of claim 1 , wherein each of the Mtop pad and the Mtop-1 pad extends beyond the boundaries of the bond ball in opposite directions that are parallel to a top surface of the Mtop pad.6. The method of ...

Semiconductor device structures and methods for copper bond pads

A method of making a semiconductor device can comprise forming a copper bond pad on an integrated circuit device; forming a first passivation layer on the integrated circuit device and the copper bond pad; forming a second passivation layer on the first passivation layer; forming a mask over the first and second passivation layers around the copper bond pad; etching the second passivation layer over the copper bond pad; and cleaning the first passivation layer over the copper bond pad. At least a portion of the first passivation layer remains over the copper bond pad after the etching the second passivation layer. A thickness of the first passivation layer over the copper bond pad is selected to protect the copper bond pad from oxidation and to allow wire bonding to the copper bond pad through the first passivation layer.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition. 1. A method of manufacturing a semiconductor device , comprising the steps of:(a) providing a wiring board having a first main surface over which a plurality of wirings are placed and an insulating film covering some of the wirings is formed;(b) mounting a rectangular semiconductor chip having a surface in which a plurality of pads are arranged over the first main surface of the wiring board;(c) electrically coupling the pads of the semiconductor chip to the some of the wirings with a plurality of individual metal wires including a first metal wire; and(d) sealing a part of the wiring board, the semiconductor chip, and the metal wires to form a sealing body,wherein, in planar view, a first belt-like wiring included in the wirings is placed over the first main surface of the wiring board along an outer edge of the semiconductor chip,wherein a first opening is formed in the insulating film of the wiring board,wherein, from the first opening, a first area of the first belt-like wiring and a first mark area provided correspondingly to the first area are exposed, andwherein the step (c) includes the steps of:(c1) detecting the first mark area to thereby specify a position of the first area; and(c2) after the step (c1), electrically coupling the first metal wire to the first area based ...

METHOD FOR FABRICATING LEADFRAME-BASED SEMICONDUCTOR PACKAGE

A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier s greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant. 1. A manufacturing method of a semiconductor package , comprising the steps of:providing a leadframe and a carrier, with a plurality of connecting pads being formed on the carrier, wherein the leadframe comprises a die pad and a plurality of leads surrounding the die pad, and the die pad is attached to a top surface of the carrier, and wherein a planar size of the carrier is larger than that of the die pad, allowing the connecting pads on the top surface of the carrier to be exposed from the die pad;attaching at least a semiconductor chip to a side of an assembly comprising the die pad and the carrier;forming a plurality of bonding wires for electrically connecting the semiconductor chip to the connecting pads on the top surface of the carrier and the leads of the leadframe; andforming a package encapsulant for encapsulating the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.2. The manufacturing method of a semiconductor package of claim 1 , wherein the plurality of connecting pads are ...

Resin-encapsulated semiconductor device and method of manufacturing the same

A resin-encapsulated semiconductor device includes: a semiconductor element mounted on a die pad portion; a plurality of lead portions disposed so that distal end parts thereof are opposed to the die pad portion; a metal thin wire for connecting an electrode of the semiconductor element to the lead portion; and an encapsulating resin for partially encapsulating those components. A bottom surface part of the die pad portion, and a bottom surface part, an outer surface part, and an upper end part of the lead portion are exposed from the encapsulating resin. A plated layer is formed on the exposed lead bottom surface part and the exposed lead upper end part.

SEMICONDUCTOR DEVICE

Provided is a semiconductor device with a semiconductor chip mounted on a small-sized package substrate that includes a slot, a large number of external connection terminals, and bonding fingers. The bonding fingers are connected to the external connection terminals. The bonding fingers constitute a bonding finger arrangement in a central section and end sections of a bonding finger area along each longer side of the slot. The arrangement includes a first bonding finger array, which is located at a close distance from each longer side of the slot, and a second array, which is located at a farther distance than the distance of the first bonding finger array from each longer side of the slot. The central section of the bonding finger area includes the second bonding finger array, and the end sections of the bonding finger area include the first bonding finger array. 120-. (canceled)21. A method comprising:preparing a package substrate, the package substrate comprising:a substrate with a slot that is selectively formed in the substrate to penetrate therethrough, the substrate thereby including a first edge defining a first side of the slot, the substrate further including a first bonding finger formation area in an end section of the first edge and a second bonding finger formation area in a central section of the first edge that is adjacent to the end section;a first bonding finger array, wherein the first bonding finger formation area consists of the first bonding finger array that consists of a first line in which a plurality of first bonding fingers are arranged in line along the end section of the first edge at a first distance from the end section of the first edge; anda second bonding finger array, wherein the second bonding finger formation area comprises the second bonding finger array, the second bonding finger array including a second line in which a plurality of second bonding fingers are arranged in line along the central section of the first edge at a ...

PACKAGED SEMICONDUCTOR DEVICE

A packaged semiconductor device includes a lead frame having a plurality of leads; a semiconductor die mounted onto the lead frame; and an encapsulant surrounding the semiconductor die. At least a portion of each of the leads is surrounded by the encapsulant, wherein, each lead includes a thin portion external to the encapsulant and a thick portion that is surrounded by the encapsulant, wherein the thin portion is thinner than the thick portion. 1. A packaged semiconductor device , comprising:a lead frame having a plurality of leads;a semiconductor die mounted onto the lead frame; andan encapsulant surrounding the semiconductor die, wherein at least a portion of each of the leads is surrounded by the encapsulant, wherein, each lead comprises a thin portion external to the encapsulant and a thick portion that is surrounded by the encapsulant, wherein the thin portion is thinner than the thick portion.2. The packaged semiconductor device of claim 1 , wherein claim 1 , for each lead claim 1 , a knee region of the lead extends external to the encapsulant.3. The packaged semiconductor device of claim 2 , wherein claim 2 , for each lead claim 2 , the knee region comprises the thin portion of the lead.4. The packaged semiconductor device of claim 3 , wherein for each lead claim 3 , the thin portion extends an entire length of the knee region.5. The packaged semiconductor device of claim 2 , wherein claim 2 , for each lead claim 2 , the thin portion is located between the knee region and a foot portion.6. The packaged semiconductor device of claim 1 , wherein for each lead claim 1 , a thickness of the thin portion is approximately 50% of a thickness of the thick portion.7. The packaged semiconductor device of claim 1 , wherein claim 1 , for each lead claim 1 , a thickness of the thin portion is in a range of 50-90% of a thickness of the thick portion.8. A method for forming a packaged semiconductor device claim 1 , comprising:attaching a semiconductor die to a lead frame ...

SELECTIVE TREATMENT OF LEADFRAME WITH ANTI-WETTING AGENT

Embodiments of the present disclosure are directed to a leadframe packages that include a leadframe having a surface that is selectively treated with chemicals that reduce the wettability of the surface and thereby reduce adhesive flow on the surface and methods of forming a packing comprising same. In one embodiment there is provided a leadframe having an upper surface that includes a first portion that is treated with an anti-epoxy bleed out chemical and a second portion that was not treated with the anti-epoxy bleed out chemical. A semiconductor die is attached to the upper surface of the leadframe at the second portion via an epoxy adhesive. 1. A leadframe package comprising:a die pad having an upper surface that is treated at a first location with an anti-wetting agent, the anti-wetting agent configured to reduce adhesive bleed out on the treated upper surface of the die pad at the first location;at least one lead located proximate to the die pad;a die secured to the upper surface of the die pad at a second location via an adhesive, the second location being untreated with the anti-wetting agent; andencapsulation material located over the die and the upper surface of the die pad.2. The leadframe package of wherein first location is located outwardly of the second location.3. The leadframe package of wherein the first location has a rectangular or square shape and the second location being located in the center of the rectangular or square shape of the first location.4. The leadframe package of wherein the first location is outwardly bound a distance from a perimeter of the die pad.5. The leadframe package of wherein the first location has an edge that is equal to or slightly larger than the perimeter of the die pad.6. The leadframe package of the adhesive abuts an edge of the first location.7. A method of forming a leadframe package claim 1 , the method comprising:treating a first portion of an upper surface of a die pad with an anti-wetting agent without ...

EMBEDDED PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THEREOF

The disclosure provides an embedded package structure comprising a metal substrate, a chip module, an insulation material layer, and at least one patterned metal layer. The metal substrate has a first surface and a second surface. The chip module is disposed on the first surface of the metal substrate, and comprises at least two stacked chips being electrically connected to each. The insulation material layer covers the first surface of the metal substrate and the stacked chips and has an electrical interconnection formed therein. The patterned metal layer is positioned on the insulation material layer, and is electrically connected the chip module through the electrical interconnection. The method for manufacturing the embedded package structure also provides. 1. An embedded package structure comprising:a metal substrate having a first surface and a second surface;a chip module, disposed on the first surface of the metal substrate, comprising at least two stacked chips being electrically connected to each other;an insulation material layer covering the first surface of the metal substrate and the chip module and having an electrical interconnection formed therein; andat least one patterned metal layer, positioned on the insulation material layer, electrically connected the chip module through the electrical interconnection.2. The embedded package structure of claim 1 , further comprising another chip module disposed on the first surface of the metal substrate.3. The embedded package structure of claim 1 , wherein at least one of the chips is of vertical type or lateral type.4. The embedded package structure of claim 1 , further comprising an adhesive layer or a solder positioned between the stacked chips.5. The embedded package structure of claim 1 , wherein the stacked chips are electrically connected to each other through a conductive layer.6. The embedded package structure of claim 1 , wherein the material of the insulation material layer comprises ABF ( ...

Semiconductor package having wire bond wall to reduce coupling

A system and method for a package including a wire bond wall to reduce coupling is presented. The package includes a substrate, and a first circuit on the substrate. The first circuit includes a first electrical device, a second electrical device, and a first wire bond array interconnecting the first electrical device and the second electrical device. The package includes a second circuit on the substrate adjacent to the first circuit, the second circuit includes a second wire bond array interconnecting a third electrical device and a fourth electrical device. The package includes a wire bond wall including a plurality of wire bonds over the substrate between the first circuit and the second circuit. The wire bond wall is configured to reduce an electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.

SEMICONDUCTOR PACKAGES HAVING WIRE BOND WALL TO REDUCE COUPLING

A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals. 1. A device housed in an air cavity package , the device comprising:a substrate having a top surface;one or more isolation structures over the top surface of the substrate, wherein an area over the top surface of the substrate within sidewalls of the one or more isolation structures defines an active circuit area;a first circuit over the top surface of the substrate within the active circuit area;a second circuit over the top surface of the substrate within the active circuit area and adjacent to the first circuit;a first lead coupled to a portion of the one or more isolation structures that is proximate to a first side of the package, wherein the first lead is electrically coupled to the first circuit;a second lead coupled to a portion of the one or more isolation structures that is proximate to a second side of the package, wherein the second lead is electrically coupled to the first circuit;a third lead coupled to the portion of the one or more isolation structures that is proximate to the first side of the package, wherein the third lead is electrically ...

PACKAGING STRUCTURE, PACKAGING METHOD AND TEMPLATE USED IN PACKAGING METHOD

Disclosed are a packaging structure, a packaging method and a template used in packaging method. The packaging structure comprises: a substrate; a chip mounted on the substrate; bonding wires for electrically connecting the substrate to the chip; and a protective layer which is formed on the substrate and is used for covering the chip, the bonding wires and bonding pads connected to the bonding wires, the size of the protective layer being smaller than that of the substrate. The packaging structure, the packaging method and the template used in packaging method can solve the problems in the prior art of the great difficulty in designing a mold chase, a complicated molding process, a high manufacturing cost and a high molding material consumption. 1. (canceled)2. (canceled)3. A packaging method , comprising:providing a substrate;mounting a chip on the substrate;electrically connecting the substrate with the chip via bonding wires through a wire bonding process;placing a template on the substrate, the template has a cavity configured to expose entire chip, the bonding wires, and bonding pads connected with the bonding wires, and the height of the template is higher than the height of the bonding wires;forming a protective layer in the cavity; andremoving the template.4. The packaging method according to claim 3 , further comprising:coating a surface coating material on the bottom surface of the template, before the template is placed on the substrate; andcleaning the surface coating material with an organic solvent, before the template is removed.5. The packaging method according to claim 3 , wherein the protective layer is formed from an epoxy encapsulation material.6. The packaging method according to claim 5 , wherein forming a protective layer in the cavity comprises:filling the epoxy encapsulation material into the cavity; andforming the protective layer by executing a curing process of the epoxy encapsulation material.7. The packaging method according to claim 6 ...

Flat No-Leads Package With Improved Contact Pins

According to an embodiment of the present disclosure, a leadframe for an integrated circuit (IC) device may comprise a center support structure for mounting an IC chip, a plurality of pins extending from the center support structure, and a bar connecting the plurality of pins remote from the center support structure. Each pin of the plurality of pins may include a dimple. 19-. (canceled)10. A method for manufacturing an integrated circuit (IC) device in a flat no-leads package , the method comprising:mounting an IC chip onto a center support structure of a leadframe, the leadframe including:the center support structure;a plurality of pins extending from the center support structure; anda bar connecting the plurality of pins remote from the center support structure;wherein each pin of the plurality of pins includes a dimple;bonding the IC chip to at least some of the plurality of pins;encapsulating the leadframe and bonded IC chip creating an IC package; andcutting the IC package free from the bar by sawing through the encapsulated lead frame at a set of cutting lines intersecting the dimples of the plurality of pins, exposing an end face of each of the plurality of pins and leaving a portion of the dimples that extends from the bottom surface of the IC package to a side surface with the exposed end faces of the pins.11. A method according to claim 10 , further comprising:performing an isolation cut to isolate individual pins of the IC package without separating the IC package from the lead frame; andperforming a circuit test of the isolated individual pins after the isolation cut.12. A method according to claim 10 , further comprising bonding the IC chip to at least some of the plurality of pins using wire bonding.13. A method according to claim 10 , further comprising plating the exposed portion of the plurality of pins claim 10 , including the dimples claim 10 , on a bottom surface of the IC package before cutting the IC package free from the bar.14. A method for ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin. 1. A method of manufacturing a semiconductor device , comprising: a main surface on which a first pad and a second pad arranged next to the first pad are provided,', 'a passivation film formed on the main surface of the semiconductor chip such that a first part of the first pad and a second part of the second pad are exposed from the passivation film,', 'a first surface-metal layer provided over the first part of the first pad and a first part of the passivation film, and', 'a second surface-metal layer provided over the second part of the second pad and a second part of the passivation film,, '(a) providing a semiconductor chip havingwherein, in plan view, a width of the first surface-metal layer is less than a width of the first pad,wherein, in plan view, a width of the second surface-metal layer is less than a width of the second pad,wherein the width of each of the first surface-metal layer, the second surface-metal layer, the first pad and the second pad is a respective dimension along the main surface of the semiconductor chip and, in plan view, in a direction along which the first pad and the second pad are arranged,wherein the passivation film has a third part located between the first pad and the second pad in cross-section view, andwherein, in cross-section view, a surface of the third part is located closer to the main surface of the semiconductor chip than a surface of the first part ...

ULTRASONIC FINGERPRINT RECOGNITION MODULE AND MANUFACTURING METHOD THEREOF

An ultrasonic fingerprint recognition module and a manufacturing method thereof are provided. The ultrasonic fingerprint recognition module includes a substrate, an ultrasonic transmitter, a thin film transistor and an ultrasonic receiver. The method includes the following steps. In a step (a), the substrate, the ultrasonic transmitter, the thin film transistor and the ultrasonic receiver are provided. In a step (b), the ultrasonic transmitter is attached on a top surface of the substrate, and the ultrasonic transmitter is electrically connected with the substrate. In a step (c), the ultrasonic receiver is attached on the thin film transistor. In a step (d), the thin film transistor is attached on the ultrasonic transmitter. In a step (e), the ultrasonic receiver is electrically connected with the thin film transistor and the thin film transistor is electrically connected with the substrate through wires. 1. A method for manufacturing an ultrasonic fingerprint recognition module , the method comprising steps of:(a) providing a substrate, an ultrasonic transmitter, a thin film transistor and an ultrasonic receiver, wherein the thin film transistor comprises a first electric pad and a second electric pad;(b) attaching the ultrasonic transmitter on a top surface of the substrate and electrically connecting the ultrasonic transmitter with the substrate;(c) attaching the ultrasonic receiver on the thin film transistor;(d) attaching the thin film transistor on the ultrasonic transmitter; and(e) electrically connecting the ultrasonic receiver with the first electric pad of the thin film transistor through the first wire, and electrically connecting the second electric pad of the thin film transistor with the substrate through the second wire.20. The method according to claim 1 , wherein the step (b) comprises a sub-step (b) of performing a plasma cleaning process to clean the top surface of the substrate.301. The method according to claim 2 , wherein after the sub-step (b) ...

EXPOSED DIE QUAD FLAT NO-LEADS (QFN) PACKAGE

Consistent with an example embodiment, there is a method for packaging an integrated circuit (IC) device. The method comprises attaching a lead frame to the carrier tape; the lead frame has an array of device positions on the carrier tape and pad landings surround the device positions for making electrical connections to the plurality of active device die. A plurality of active device die are mounted on the carrier tape within the array of device positions; each said active device die has bond pads, each of said active device die has been subjected to back-grinding to a prescribed thickness and has a solderable conductive surface on its underside. On the bond pads, the plurality of active devices are wire bonded to the pad landings on the lead frame. The lead frame and wire bonded active devices are encapsulated, leaving the solderable die backside and lead frame backside exposed. 13-. (canceled)4. The method as recited in claim 8 , wherein the solderable conductive surface includes alloys of: NiAu claim 8 , Ni claim 8 , Cu claim 8 , Au claim 8 , NiPdAu claim 8 , AuSn claim 8 , NiSn claim 8 , CuSn claim 8 , Ag claim 8 , AgSn or combinations thereof.5. The method as recited in claim 4 , wherein the solderable conductive surface further includes an adhesion layer of Ti or Cr as a first layer on the under-side.67-. (canceled)8. A method for packaging an integrated circuit (IC) device from a semiconductor wafer substrate claim 4 , the wafer substrate having a top-side surface with a plurality active device die defined thereon claim 4 , and an under-side surface claim 4 , the method comprising:back-grinding the under-side surface of the wafer substrate to a prescribed thickness;applying a solderable conductive surface to the under-side surface of the wafer substrate;separating out the plurality active device die from the semiconductor wafer substrate, each of the active device die having bond pads, the bond pads providing electrical connection to circuit elements in the ...

RADIO FREQUENCY POWER DEVICE

An electronic RF power device includes a transistor chip, a device input terminal and a device output terminal. Further, the electronic RF power device includes an output impedance transformation circuit, an output contact clip bonded to the transistor chip and to the output device terminal and at least one bond wire bonded to the output impedance transformation circuit and to the transistor chip. 1. An electronic RF power device , comprising:a transistor chip;a device input terminal;a device output terminal;an output impedance transformation circuit;an output contact clip bonded to the transistor chip and to the output device terminal; andat least one bond wire bonded to the output impedance transformation circuit and to the transistor chip.2. The electronic RF power device of claim 1 , wherein the transistor chip is selected from the group consisting of a LDMOS chip claim 1 , a SiC chip claim 1 , a GaN chip claim 1 , a GaAs chip claim 1 , and a Si bipolar chip.3. The electronic RF power device of claim 1 , wherein the output impedance transformation circuit comprises a capacitor die.4. The electronic RF power device of claim 1 , further comprising:an input impedance transformation circuit; anda first input contact clip bonded to the device input terminal and to the input impedance transformation circuit.5. The electronic RF power device of claim 4 , further comprising:a second input contact clip bonded to the input impedance transformation circuit and to the transistor chip.6. The electronic RF power device of claim 4 , wherein the input impedance transformation circuit comprises a capacitor die.7. The electronic RF power device of claim 1 , further comprising:a carrier on which the transistor chip and the output impedance transformation circuit are mounted, wherein the carrier comprises a trench located between the transistor chip and the output impedance transformation circuit.8. An electronic RF power device claim 1 , comprising:a transistor chip;a device input ...

SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SEMICONDUCTOR DEVICE

A semiconductor device includes: a substrate including a base member having a main surface and a back surface facing opposite in a thickness direction; a semiconductor element mounted on the main surface of the substrate and having at least one element pad; a wire having a bonding portion bonded to the element pad; and a sealing resin formed on the main surface of the substrate for covering the wire and at least a portion of the semiconductor element. The semiconductor element has an element exposed side surface that faces in a direction crossing the thickness direction of the substrate and is exposed from the sealing resin. 1. A semiconductor device comprising:a substrate including a base member having a main surface and a back surface facing opposite in a thickness direction;a semiconductor element having at least one element pad and mounted on the main surface of the substrate;a wire having a bonding portion bonded to the element pad; anda sealing resin formed on the main surface of the substrate, and covering the wire and at least a portion of the semiconductor element,wherein the semiconductor element includes an element exposed surface that faces in a direction crossing the thickness direction of the substrate and is exposed from the sealing resin.2. The semiconductor device according to claim 1 , wherein the base member includes a substrate outer side surface that connects the main surface and the back surface to each other and is flush with the element exposed side surface of the semiconductor element.3. The semiconductor device according to claim 2 , wherein the sealing resin has a sealing resin outer surface flush with both the element exposed side surface of the semiconductor element and the substrate outer side surface of the base member.4. The semiconductor device according to claim 1 , wherein the element exposed side surface of the semiconductor element is perpendicular to the thickness direction of the substrate.5. The semiconductor device according ...

SEMICONDUCTOR PACKAGE HAVING AN ISOLATION WALL TO REDUCE ELECTROMAGNETIC COUPLING

A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented. 1. A semiconductor device comprising:a substrate with a surface;a first circuit on the substrate and comprising a plurality of electrical components, including a first transistor, and a first wire bond array electrically coupled between the first transistor and a first lead;a second circuit on the substrate and comprising a plurality of electrical components, including a second transistor, and a second wire bond array electrically coupled between the second transistor and a second lead; andan isolation wall formed of electrically conductive material and located between the first circuit and the second circuit in an air cavity above the surface of the substrate, the isolation wall formed of a body of material that is oriented perpendicular to the surface of the substrate and extending above a height of the first and second wire bond arrays, the isolation wall being configured to reduce electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit, wherein the isolation wall is formed by a section of a lead frame for the semiconductor device, and wherein the lead frame also includes the first lead and the second lead.2. The semiconductor device as recited in claim 1 , wherein the lead frame is formed by an electrically conductive sheet claim 1 , and the isolation wall is formed by a section of the lead frame that is ...

Repackaged integrated circuit assembly method

A method is provided. The method includes one or more of extracting a die from an original packaged integrated circuit, modifying the extracted die, reconditioning the modified extracted die, placing the reconditioned die into a cavity of a hermetic package base, bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base, and sealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit. Modifying the extracted die includes removing the one or more ball bonds on the one or more die pads. Reconditioning the modified extracted die includes adding a sequence of metallic layers to bare die pads of the modified extracted die. The extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die. 1. A method , comprising:extracting a die from an original packaged integrated circuit, wherein the extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die;modifying the extracted die, comprising removing the one or more ball bonds on the one or more die pads; 'adding a sequence of metallic layers to bare die pads of the modified extracted die;', 'reconditioning the modified extracted die, comprisingplacing the reconditioned die into a cavity of a hermetic package base;bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base; andsealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit.2. The method as recited in claim 1 , wherein bare die pads of the modified extracted die comprises all metallic and chemical residue claim 1 , all ball bonds claim 1 , and all bond wires removed from all die ...

METHODS FOR FORMING SHIELDED RADIO-FREQUENCY MODULES HAVING REDUCED AREA

Shielded radio-frequency (RF) module having reduced area. In some embodiments, a method for fabricating a radio-frequency module includes forming or providing a packaging substrate configured to receive a plurality of components. The method may include mounting one or more devices on the packaging substrate such that the packaging substrate includes a first area associated with mounting of each of the one or more devices. In some embodiments, the method further includes forming a plurality of shielding wirebonds on the packaging substrate to provide RF shielding functionality for one or more regions on the packaging substrate, such that the packaging substrate includes a second area associated with formation of each shielding wirebond, the mounting of each device implemented with respect to a corresponding shielding wirebond such that a portion of the first area associated with the device overlaps at least partially with a portion of the second area associated with the corresponding shielding wirebond. 1. A method for fabricating a radio-frequency module , the method comprising:forming or providing a packaging substrate configured to receive a plurality of components;mounting one or more devices on the packaging substrate such that the packaging substrate includes a first area associated with mounting of each of the one or more devices; andforming a plurality of shielding wirebonds on the packaging substrate to provide RF shielding functionality for one or more regions on the packaging substrate, such that the packaging substrate includes a second area associated with formation of each shielding wirebond, the mounting of each device implemented with respect to a corresponding shielding wirebond such that a portion of the first area associated with the device overlaps at least partially with a portion of the second area associated with the corresponding shielding wirebond.2. The method of further comprising forming each of the shielding wirebonds to have a loop shape ...

SIMULTANEOUS DOUBLE WIRE WEDGE BONDING METHOD, SYSTEM, KIT AND TOOL

A wedge bonding method for simultaneously connecting two wires to a first component and then to a second component includes a) feeding the two wires side by side through a guide channel located at a lower end of a bonding wedge tool, b) positioning the bonding wedge tool over the first component and performing a first bond connection thereon, c) positioning the bonding wedge tool over the second component and performing a second bond connection thereon; and d) breaking tails of the two wires near the second bond connection. 1. A wedge bonding method for simultaneously connecting two wires to a first component and then to a second component , comprising:a) feeding the two wires side by side through a guide channel located at a lower end of a bonding wedge tool;b) positioning the bonding wedge tool over the first component and performing a first bond connection thereon;c) positioning the bonding wedge tool over the second component and performing a second bond connection thereon; andd) breaking tails of the two wires near the second bond connection.2. The method according to claim 1 , further comprising providing first and second wire spools claim 1 , the second wire spool being located higher and offset relative to the first wire spool.3. The method according to claim 2 , further comprising:unwinding the two wires from the first and the second wire spools, respectively; andguiding the two wires side by side through the guide channel extending through the bonding wedge tool, prior to step a).4. The method according to claim 3 , wherein during the step of guiding the two wires claim 3 , the two wires are spaced apart.5. The method according to claim 1 , wherein during steps b) and c) claim 1 , the two wires are spaced apart by 8 to 13 micrometers.6. The method according to claim 1 , whereinthe two wires have the same diameter, andin step a), the guide channel has a cross-section of rectangular, oblong, oval or radius-cornered rectangle shape, with a width of 2.3 to 2.7 ...

Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops

A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.

SEMICONDUCTOR DEVICE

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film. 1. A semiconductor device comprising:an interlayer insulating film formed on a semiconductor substrate;an uppermost layer wiring made of copper and formed on the interlayer insulating film;a passivation film formed on the uppermost layer wiring and selectively exposing a top surface of the uppermost layer wiring as an electrode pad; anda bonding wire made of copper and bonded directly to the electrode pad.2. The semiconductor device according to claim 1 , wherein the bonding wire is stitch bonded directly to the electrode pad.3. The semiconductor device according to claim 1 , wherein the bonding wire is bonded to the electrode pad by a stud bump.4. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is no less than 10 μm.5. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is 10 μm to 15 μm.6. The semiconductor device according to claim 1 , further comprising a lower layer wiring covered with the interlayer insulating film claim 1 , whereinthe uppermost layer wiring includes a protrusion extending inside the interlayer insulating film,the lower layer wiring is electrically connected to the electrode pad via a pathway including the protrusion.7. The ...

Lead frames including lead posts in different planes

A lead frame includes a die pad having a surface, a first lead post, a first lead, a second lead post, and a second lead. The first lead post has a surface coplanar with the surface of the die pad and is in a first plane. The first lead is coupled to the first lead post. The second lead post is in a second plane different from the first plane. The second lead is coupled to the second lead post.

METHODS OF DETECTING BONDING BETWEEN A BONDING WIRE AND A BONDING LOCATION ON A WIRE BONDING MACHINE

A method of determining a bonding status between wire and at least one bonding location of a semiconductor device is provided. The method includes the steps of: (a) bonding a portion of wire to at least one bonding location of a semiconductor device using a bonding tool of a wire bonding machine; and (b) detecting whether another portion of wire engaged with the bonding tool, and separate from the portion of wire, contacts the portion of wire in a predetermined height range, thereby determining if the portion of wire is bonded to the at least one bonding location. 1. A method of determining a bonding status between wire and at least one bonding location of a semiconductor device , the method comprising the steps of:(a) bonding a portion of wire to the at least one bonding location of a semiconductor device using a bonding tool of a wire bonding machine; and(b) detecting whether another portion of wire engaged with the bonding tool, and separate from the portion of wire, contacts the portion of wire in a predetermined height range, thereby determining if the portion of wire is bonded to the at least one bonding location.2. The method of wherein the portion of wire is bonded to a single bonding location of the semiconductor device claim 1 , and wherein after step (a) the portion of wire is a conductive bump bonded to the single bonding location.3. The method of wherein the portion of wire is bonded to a plurality of bonding locations of the semiconductor device claim 1 , and wherein after step (a) the portion of wire is a wire loop providing electrical interconnection between the plurality of bonding locations.4. The method of claim 3 , wherein step (b) includes detecting whether the another portion of wire engaged with the bonding tool contacts each of a plurality of areas of the portion of wire within corresponding predetermined height ranges claim 3 , thereby determining if the portion of wire is bonded at each of the plurality of areas to corresponding bonding ...

SEMICONDUCTOR PRODUCT AND CORRESPONDING METHOD

A semiconductor product such as an integrated circuit includes a laminar plastic substrate having first and second opposed surfaces and through holes extending through the substrate, electrically and/or thermally conductive material balls inserted in the through holes at the first surface of the substrate, and one or more semiconductor chips mounted at the first surface of the substrate, the semiconductor chip(s) electrically and/or thermally coupled with electrically and/or thermally conductive material balls inserted in the through holes. 1. A product , comprising:a laminar plastic substrate having first and second opposed surfaces and through holes extending through the substrate between the first and second surfaces, the substrate including a laser direct structuring material that has been laser activated and forms conductive walls in the through holes;conductive material balls inserted in the through holes at the first surface of the substrate, the conductive material balls coupled to the conductive walls; andat least one semiconductor chip coupled to the first surface of the substrate and the conductive material balls.2. The product of claim 1 , further comprising conductive material on the second surface of the substrate and partially filling through holes in the substrate.3. The product of claim 2 , wherein the conductive material on the second surface of the substrate and partially filling the through holes is coupled to the conductive material balls inserted in the through holes at the first surface.4. The product of claim 1 , further comprising electrically-conductive formations at the first surface of the substrate claim 1 , the electrically-conductive formations in electrical contact with the conductive material balls inserted in through holes in the substrate at the first surface.5. The product of claim 1 , wherein the at least one semiconductor chip coupled to the first surface of the substrate is coupled to the conductive material balls by wire bonds ...

METHOD OF MANUFACTURING A CIRCUIT DEVICE

In one form, a method of manufacturing a circuit device comprises providing a lead frame comprising a plurality of leads, each comprising an island portion, a bonding portion elevated from the island portion, a slope portion extending obliquely so as to connect the island portion and the bonding portion, and a lead portion extending from the bonding portion. First and second transistors and first and second diodes are mounted upper surfaces of island portions of respective first and second leads, and are connected to the respective leads through wirings that connect the transistors and diodes to the bonding portions of the respective leads. Lower surfaces of the island portions are attached to an upper surface of a circuit board, and the circuit board, the transistors, the diodes, and the lead frame are encapsulated by a resin, so that the lead portions are not covered by the resin. 1. A method of manufacturing a circuit device , comprising:providing a lead frame comprising a plurality of leads, each comprising an island portion, a bonding portion elevated from the island portion, a slope portion extending obliquely so as to connect the island portion and the bonding portion, and a lead portion extending from the bonding portion;mounting a first transistor and a first diode of a first phase on an upper surface of the island portion of a first lead;connecting the first transistor and the first diode of the first phase to a bonding portion of a second lead by a first wiring;mounting a second transistor and a second diode of the first phase on the upper surface of the island portion of a third lead;connecting the second transistor and the second diode of the first phase to a bonding portion of the second lead by a second wiring;attaching lower surfaces of the island portion of each of the plurality of leads to an upper surface of a circuit board; andencapsulating by a resin the circuit board, the first and second transistors, the first and second diodes and the lead ...

HIGH-POWER AMPLIFIER PACKAGE

Package assemblies for improving heat dissipation of high-power components in microwave circuits are described. A laminate that includes microwave circuitry may have cut-outs that allow high-power components to be mounted directly on a heat slug below the laminate. Electrical connections to circuitry on the laminate may be made with wire bonds. The packaging allows more flexible design and tuning of packaged microwave circuitry. 1. A high-power amplifier circuit assembled in a package comprising:a microwave circuit formed on a laminate;a case supporting conductive leads that are connected to the microwave circuit;a heat slug connected to the case and extending from an interior region of the case to an exterior region of the case;a cut-out in the laminate; anda first power transistor mounted directly on the heat slug within the cut-out of the laminate and connected to the microwave circuit.2. The high-power amplifier circuit of claim 1 , wherein the first power transistor is capable of outputting power levels between 50 W and 100 W at duty cycles greater than 50% without significant degradation of the amplifier's performance.3. The high-power amplifier circuit of claim 1 , wherein the first power transistor is capable of outputting power levels between 100 W and 200 W at duty cycles greater than 50% without significant degradation of the amplifier's performance.4. The high-power amplifier circuit of claim 3 , wherein the first power transistor comprises GaN.5. The high-power amplifier circuit of claim 4 , further comprising a second power transistor mounted directly on the heat slug in a second cut-out in the laminate and having an output connected to an input of the first power transistor.6. The high-power amplifier circuit of claim 4 , further comprising a second power transistor mounted directly on the heat slug in a second cut-out in the laminate and connected in parallel with the first power transistor in a Doherty configuration.7. The high-power amplifier ...

Semiconductor package and method for manufacturing a semiconductor package

A semiconductor package includes at least one semiconductor element, an encapsulant, a first circuitry, a second circuitry and at least one first stud bump. The encapsulant covers at least a portion of the semiconductor element. The encapsulant has a first surface and a second surface opposite to the first surface. The first circuitry is disposed adjacent to the first surface of the encapsulant. The second circuitry is disposed adjacent to the second surface of the encapsulant. The first stud bump is disposed in the encapsulant, and electrically connects the first circuitry and the second circuitry. The first stud bump contacts the second circuitry directly.