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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 560. Отображено 100.
16-05-2013 дата публикации

Isolation structure for esd device

Номер: US20130119433A1
Автор: Chun-Kai Wang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Among other things, an electrostatic discharge (ESD) device is provided. The ESD device comprises a dielectric isolation structure that is formed between an emitter and a collector of the ESD device. During an ESD event, current flows from the emitter, substantially under the dielectric isolation structure, to the collector, to protect associated circuitry. The dielectric isolation structure is formed to a depth that is less than a depth of at least one of the emitter or the collector, or doped regions thereof, thereby decreasing a length of a current path from the emitter to the collector, because the current is not obstructed by the dielectric isolation structure. Accordingly, the ESD device can carry higher current during the ESD event because the shorter current path has less resistance than a longer path that would otherwise be traveled if the dielectric isolation structure was not formed at the shallower depth.

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Номер записи: 1
03-10-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130256746A1
Автор: MIYAZAWA Shigemi, Nakamura Hiroshi
Принадлежит: FUJI ELECTRIC CO., LTD.

Aspects of the invention can include a semiconductor device that includes an output stage IGBT and a Zener diode on the same semiconductor substrate. The IGBT can include a first p well layer, an n emitter region on the surface region of the first p well layer, a gate electrode deposited on a gate insulating film, and an emitter electrode on the emitter region. The Zener diode can include a player formed in the surface region of a second p well layer in the place different from the first p well layer and has a higher concentration than the second p well layer, an anode electrode in ohmic contact with the surface of the player, an nlayer having a lower concentration than the second p well layer, and a cathode electrode in Schottky contact with the surface of the nlayer. 1. A semiconductor device comprising: a first well layer of a second conductivity type formed in a surface region of a first conductivity type semiconductor layer on a first principal surface of a second conductivity type semiconductor layer;', 'an emitter layer of the first conductivity type selectively formed in a surface region of the first well layer;', 'a gate electrode covering a part of surface of the emitter layer and a part of surface of the first well layer through a gate insulating film;', 'an emitter electrode in contact commonly with the surface of the emitter layer that is not covered with the gate electrode and the surface of the first well layer; and', 'a collector electrode in contact with a second principal surface of the second conductivity semiconductor layer; and, 'an IGBT and a Zener diode that protects the IGBT from a surge voltage, the IGBT comprising a second well layer of the second conductivity type formed in the surface region of the first conductivity type semiconductor layer on the first principal surface of the second conductivity type semiconductor layer, the second well layer being disposed apart from the first well layer;', 'an anode electrode in ohmic contact with a ...

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Номер записи: 2
31-10-2013 дата публикации

FULL BRIDGE RECTIFIER MODULE

Номер: US20130285210A1
Автор: Seok Kyoung Wook
Принадлежит:

A full bridge rectifier includes four bipolar transistors, each of which has an associated parallel diode. A first pair of inductors provides inductive current splitting and thereby provides base current to/from one pair of the bipolar transistors so that the collector-to-emitter voltages of the bipolar transistors are low. A second pair of inductors similarly provides inductive current splitting to provide base current to/from the other pair of bipolar transistors. In one embodiment, all components are provided in a four terminal full bridge rectifier module. The module can be used as a drop-in replacement for a conventional four terminal full bridge diode rectifier. When current flows through the rectifier module, however, the voltage drop across the module is less than one volt. Due to the reduced low voltage drop, power loss in the rectifier module is reduced as compared to power loss in a conventional full bridge diode rectifier. 1. A packaged semiconductor device comprising:a first package terminal;a second package terminal;a third package terminal;a fourth package terminal;a first bipolar transistor BJT1, wherein an emitter of BJT1 is coupled to the first package terminal;a second bipolar transistor BJT2, wherein an emitter of BJT2 is coupled to the second package terminal;a third bipolar transistor BJT3, wherein an emitter of BJT3 is coupled to the first package terminal; anda fourth bipolar transistor BJT4, wherein an emitter of BJT4 is coupled to the second package terminal;a first inductor I1 having a first terminal and a second terminal, wherein the first terminal of I1 is coupled to a collector of BJT1 and to a collector of BJT2, wherein the second terminal of I1 is coupled to the third package terminal;a second inductor I2 having a first terminal and a second terminal, wherein the first terminal of the I2 is coupled to a collector of BJT3 and to a collector of BJT4, wherein the second terminal of I2 is coupled to the fourth package terminal;a third ...

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Номер записи: 3
05-01-2017 дата публикации

DETERMINING MECHANICAL STRESS

Номер: US20170003181A1
Автор: Ausserlechner Udo
Принадлежит: INFINEON TECHNOLOGIES AG

Embodiments relate to circuitry and methods for determining and providing a mechanical stress level signal, including at least one bipolar junction transistor, wherein the circuitry is arranged to determine a first mechanical stress level based on a current gain of the at least one bipolar junction transistor, to determine a second mechanical stress level based on the current gain of the at least one bipolar junction transistor, and to provide the mechanical stress level signal based on the first mechanical stress level and the second mechanical stress level. 1. A circuitry for providing a mechanical stress level signal , comprising:at least one bipolar junction transistor; anda processing unit configured to determine a first mechanical stress level based on a current gain of the at least one bipolar junction transistor, to determine a second mechanical stress level based on the current gain of the at least one bipolar junction transistor, and to provide the mechanical stress level signal based on the first mechanical stress level and the second mechanical stress level.2. The circuitry according to claim 1 , wherein the mechanical stress level signal is determined based on a comparison between the first mechanical stress level and the second mechanical stress level.3. The circuitry according to claim 1 , wherein the first mechanical stress level is determined via at least two of the three terminals of a first bipolar junction transistor and the second mechanical stress level is determined via the same two terminals or different two out of three terminals of the first bipolar junction transistor.4. The circuitry according to claim 1 , wherein the at least one bipolar junction transistor comprises a first bipolar junction transistor and a second bipolar junction transistor claim 1 , andwherein the first mechanical stress level is determined via at least two of the three terminals of the first bipolar junction transistor and the second mechanical stress level is ...

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Номер записи: 4
13-01-2022 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

Номер: US20220013635A1
Автор: ONOZAWA Yuichi, TAMURA Takahiro
Принадлежит:

Provided is a semiconductor device including: a semiconductor substrate including a bulk donor; and a first buffer region of a first conductivity type, the first buffer region being provided on a lower surface side of the semiconductor substrate and having one or more doping concentration peaks and one or more hydrogen concentration peaks in a depth direction of the semiconductor substrate, in which a doping concentration at a shallowest concentration peak, out of the doping concentration peaks of the first buffer region, closest to the lower surface of the semiconductor substrate is 50 times as high as a concentration of the bulk donor of the semiconductor substrate or lower. The doping concentration at the shallowest concentration peak may be lower than a reference carrier concentration obtained when current that is 1/10 of rated current flows between an upper surface and the lower surface of the semiconductor substrate. 1. A semiconductor device comprising:a semiconductor substrate including a bulk donor; anda first buffer region of a first conductivity type, the first buffer region being provided on a lower surface side of the semiconductor substrate and having one or more doping concentration peaks and one or more hydrogen concentration peaks in a depth direction of the semiconductor substrate, whereina doping concentration at a shallowest concentration peak, out of the doping concentration peaks of the first buffer region, closest to the lower surface of the semiconductor substrate is 50 times as high as a bulk donor concentration of the semiconductor substrate or lower.2. The semiconductor device according to claim 1 , wherein doping concentrations at all of the doping concentration peaks of the first buffer region are 50 times as high as the bulk donor concentration or lower.3. The semiconductor device according to claim 1 , wherein the first buffer region has two or more of the doping concentration peaks claim 1 , and a doping concentration at at least one ...

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Номер записи: 5
03-01-2019 дата публикации

High-Dielectric Constant Capacitor Structures on III-V Substrates

Номер: US20190006459A1
Автор: Jonathan Abrokwah, Phil Nikkel, Satish Yeldandi, Thomas Dungan
Принадлежит: Avago Technologies International Sales Pte Ltd

A semiconductor structure includes a III-V semiconductor structure; a first electrode; a first barrier layer disposed over the first electrode; a first adhesion layer disposed over the first electrode; a first passivation layer disposed over the first adhesion layer; a dielectric layer disposed over the first passivation layer; a second passivation layer disposed over the dielectric layer; a second adhesion layer disposed over the second passivation layer; a second barrier layer disposed over the second adhesion layer; and a second electrode disposed over the second barrier layer.

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Номер записи: 6
14-01-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210013164A1
Автор: KOBORI Tsutomu, Okabe Hiroshi, TAKAHASHI Yoshifumi, YANAGIHARA Shingo, Yoshida Shigeru
Принадлежит:

A ground pad is disposed on a substrate. A plurality of transistors, each grounded at an emitter thereof, are in a first direction on a surface of the substrate. An input line connected to bases of the transistors is on the substrate. At least two shunt inductors are each connected at one end thereof to the input line and connected at the other end thereof to the ground pad. In the first direction, the two shunt inductors are on opposite sides of a center of a region where the transistors are arranged. 1. A semiconductor device comprising:a ground pad on a substrate;a plurality of transistors arranged in a first direction on a surface of the substrate, an emitter of each transistor being grounded;an input line on the substrate, the input line being connected to a base of each transistor; andat least two shunt inductors, each shunt inductor being connected at a first end to the input line and at a second end to the ground pad,wherein a first of the at least two shunt inductors is on a first side of a region of the substrate in which the plurality of transistors are arranged, with respect to the first direction, andwherein a second of the at least two shunt inductors is on a second side of the region of the substrate in which the plurality of transistors are arranged, with respect to the first direction, the second side being opposite the first side.2. The semiconductor device according to claim 1 , wherein the emitter of each transistors is connected to the ground pad.3. The semiconductor device according to claim 1 , wherein the input line and the at least two shunt inductors are on the same side of the substrate with respect to a second direction claim 1 , the second direction being orthogonal to the first direction.4. The semiconductor device according to claim 1 , wherein at least one of the transistors is between the first shunt inductor and the second shunt inductor in the first direction.5. The semiconductor device according to claim 2 , wherein at least one ...

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Номер записи: 7
14-01-2021 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20210013165A1
Автор: GOTO Satoshi, NAMIE Hisanori, Tanaka Satoshi
Принадлежит:

A semiconductor device includes a semiconductor substrate, a transistor, and a first harmonic termination circuit. The transistor is formed at the semiconductor substrate. The transistor amplifies an input signal supplied to an input end and outputs an amplified signal through an output end. The first harmonic termination circuit attenuates a harmonic component included in the amplified signal. The first harmonic termination circuit is formed at the semiconductor substrate such that one end of the first harmonic termination circuit is connected to the output end of the transistor and the other end of the first harmonic termination circuit is connected to a ground end of the transistor. 1. A semiconductor device comprising:a semiconductor substrate;a transistor that amplifies an input signal supplied to an input end and outputs an amplified signal through an output end, the transistor being on or in the semiconductor substrate, and the transistor being a multi-finger transistor having a plurality of unit transistors;a first harmonic termination circuit that is configured to attenuate a harmonic component of an amplified signal output from an output end of a first unit transistor, the first harmonic termination circuit being on the semiconductor substrate such that a first end of the first harmonic termination circuit is connected to the output end of the first unit transistor and a second end of the first harmonic termination circuit is connected to a ground end of the first unit transistor; anda second harmonic termination circuit configured to attenuate a harmonic component of an amplified signal output from an output end of a second unit transistor, the second harmonic termination circuit being on the semiconductor substrate such that a first end of the second harmonic termination circuit is connected to the output end of the second unit transistor and a second end of the second harmonic termination circuit is connected to a ground end of the second unit ...

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Номер записи: 8
21-01-2016 дата публикации

IMPEDANCE MATCHING CIRCUIT, POWER AMPLIFIER AND MANUFACTURING METHOD FOR VARIABLE CAPACITOR

Номер: US20160020147A1
Автор: Kim Seong-il, LEE Jongmin, Min Byoung-Gue, MUN Jae Kyoung, Nam Eun Soo, Yoon Hyung Sup
Принадлежит: Electronics and Telecommunications Research Institute

A manufacturing method for a variable capacitor includes forming a first element of which a capacitance value depends on a voltage applied to both of two terminals of a first area on a substrate, forming a second element having a capacitance value fixed to a second area on the substrate adjacent to the first area, and forming metallic wires for connecting the first element and the second element and connecting the first element and the second element with the outside. The first element maybe a bipolar transistor that may include a diode. The second element maybe a capacitor that includes a dielectric.

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Номер записи: 9
19-01-2017 дата публикации

DUAL-SIDED SILICON INTEGRATED PASSIVE DEVICES

Номер: US20170018546A1
Автор: Hu Kunzhong, PANG Mengzhi, Ramachandran Vidhya, Zhai Jun, Zhong Chonghua
Принадлежит:

In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device. 1. An integrated circuit , comprising:a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface configured to electrically connect the integrated circuit to a circuit board;a semiconductor die coupled to the second surface of the first substrate using a second set of electrical conductors; anda passive device dimensioned to be integrated with the integrated circuit, wherein the passive device is positioned between the second surface and at least one of the first set of electrical conductors, wherein the passive device comprises at least a third electrical conductor positioned on a first side of the passive device, wherein the passive device comprises at least a fourth electrical conductor positioned on a second side of the passive device, and wherein the second side of the device is positioned opposite the first side of the device;wherein the die is electrically connected to the fourth electrical conductor using the second ...

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Номер записи: 10
17-04-2014 дата публикации

POWER RF AMPLIFIERS

Номер: US20140103447A1
Автор: Bouisse Gerard Jean-Louis
Принадлежит: NXP B.V.

A power transistor circuit uses first and second power transistors in differential mode. An inductor arrangement of inductors is formed by wire bonds between the drains. The transistors are in a mirrored configuration, and the inductor arrangement comprises wire bonds which extend between the drain connections across the space between the mirrored transistors. 1. A power transistor circuit , comprising:first and second power transistors, which each occupy an elongate rectangular area with gate connections on a gate side and drain connections on the opposite drain side, wherein the drain connections of each transistor connect to a respective output pad enabling use of the two power transistors in a differential amplifier configuration; andan inductor arrangement of inductors formed by wire bonds between the drain connections,wherein an elongate side of one transistor faces an elongate side of the other transistor in a mirrored arrangement, and the inductor arrangement comprises wire bonds which extend between the drain connections across the space between the transistors.2. A circuit as claimed in claim 1 , wherein the gate sides face each other.3. A circuit as claimed in claim 1 , comprising a separate input pad claim 1 , one for each gate side.4. A circuit as claimed in claim 1 , comprising a package having a quadrilateral shape claim 1 , wherein two input pads are provided at one side of the quadrilateral package claim 1 , and the output pads are provided at the two adjacent sides.5. A circuit as claimed in claim 1 , comprising inductor tracks between the input pads and the gates.6. A circuit as claimed in claim 1 , wherein each transistor provides a total gate periphery of at least 100 mm claim 1 , with a series of parallel fingers.7. A circuit as claimed in claim 6 , wherein the inductor arrangement wire bonds are provided every 5 to 10 fingers.8. A circuit as claimed in claim 1 , further comprising a connection line connecting the mid points of the inductor ...

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Номер записи: 11
17-04-2014 дата публикации

Impedance Matching Network with Improved Quality Factor and Method for Matching an Impedance

Номер: US20140104132A1
Автор: Anthony Thomas, Winfried Bakalski
Принадлежит: INFINEON TECHNOLOGIES AG

An impedance matching network comprises a first and a second signal terminal and a reference potential terminal. The network further comprises a first shunt branch between the first signal terminal and the reference potential terminal, the first shunt branch comprising a variable inductive element and a first capacitive element. The impedance matching network also comprises a second shunt branch between the second signal terminal and the reference potential terminal and comprising a second capacitive element. A series branch between the first signal terminal and the second signal terminal comprises a third capacitive element. Optionally, the first, second, and/or third capacitive element may be implemented as a variable capacitive element. The variable capacitive element comprises a plurality of transistors, wherein a combination of off-capacitances C off of the transistors provide an overall capacitance of the variable capacitive element as a function of at least two independent transistor control signals.

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Номер записи: 12
16-01-2020 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20200021255A1
Автор: GOTO Satoshi
Принадлежит: MURATA MANUFACTURING CO., LTD.

A semiconductor device includes a semiconductor substrate including a principal surface parallel to a plane defined by a first direction and a second direction substantially orthogonal to the first direction, and the principal surface having a first side parallel to the first direction; first unit transistors, each amplifying a first signal in a first frequency band to output a second signal; and second unit transistors, each amplifying the second signal to output a third signal and aligned in the second direction between the first side and a substrate center line in the first direction in plan view of the principal surface. A first center line in the first direction of a region in which the first unit transistors are aligned is farther from the first side than a second center line in the first direction of a region in which the second unit transistors are aligned. 1. A semiconductor device comprising:a semiconductor substrate including a principal surface that is parallel to a plane defined by a first direction and a second direction substantially orthogonal to the first direction, the principal surface including a first side that is parallel to the first direction;first unit transistors, each of which is configured to amplify a first signal in a first frequency band to output a second signal; andsecond unit transistors, each of which is configured to amplify the second signal to output a third signal,wherein, on the semiconductor substrate,the second unit transistors are aligned in the second direction between the first side and a substrate center line in the first direction of the semiconductor substrate in plan view of the principal surface, andthe first unit transistors are aligned such that a first center line in the first direction of a region in which the first unit transistors are aligned is farther from the first side than a second center line in the first direction of a region in which the second unit transistors are aligned.2. The semiconductor device ...

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Номер записи: 13
24-01-2019 дата публикации

DIRECT SUBSTRATE TO SOLDER BUMP CONNECTION FOR THERMAL MANAGEMENT IN FLIP CHIP AMPLIFIERS

Номер: US20190028067A1
Автор: Gill Bharatjeet Singh, Kovacic Stephen Joseph, McPartlin Michael Joseph
Принадлежит:

Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps. 1. A device comprising:an amplifier including at least one transistor formed over a silicon substrate; anda metal pillar formed with respect to the silicon substrate such that a portion of the metal pillar is in direct contact with the silicon substrate, heat generated during operation of the at least one transistor being transferred through the silicon substrate to the portion of the metal pillar.2. The device of further comprising a first resistor in communication with an emitter of the at least one transistor and with the metal pillar.3. The device of further comprising a second resistor in communication with a base of the at least one transistor.4. The device of wherein the metal pillar is formed within a cavity etched into the silicon substrate.5. The device of wherein the metal pillar protrudes outward and upward from the cavity.6. The device of wherein the portion of the metal pillar in direct contact with the silicon substrate is a bottom and at least a portion of sides of the metal pillar7. The device of wherein the portion of the metal pillar in direct contact with the silicon substrate is a bottom of the metal pillar.8. The device of wherein the metal pillar is configured to provide a flip chip interconnection for the amplifier.9. The device of wherein the metal pillar is adjacent to the at least one transistor.10. A method to implement an emitter-ballasted amplifier in a flip chip configuration claim 1 , the method comprising:forming an amplifier including at ...

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Номер записи: 14
30-01-2020 дата публикации

Semiconductor Package with Passive Electrical Component and Method for the Production Thereof

Номер: US20200035581A1
Автор: Haase Ordwin, HOEGERL Juergen, Kist Tobias
Принадлежит:

A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer with an outwardly exposed surface and an electrical insulating layer arranged between the upper and lower electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the power semiconductor chip, and a passive electrical component electrically connected to the upper electrically conductive layer of the lower carrier substrate. 1. A double-sided coolable semiconductor package , comprising:an upper electrically conductive element having an outwardly exposed metal surface;a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer with an outwardly exposed surface, and an electrical insulating layer arranged between the upper and lower electrically conductive layers;a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer;a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer;a second electrically conductive spacer arranged between the upper electrically conductive element and the power semiconductor chip; anda capacitor electrically connected to the upper electrically conductive layer of the lower carrier substrate,wherein the capacitor is arranged on a region of the upper electrically conductive layer that is formed for applying a positive supply voltage or a negative ...

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Номер записи: 15
08-02-2018 дата публикации

SCRs with Checker Board Layouts

Номер: US20180040603A1
Автор: CHENG Shui-Ming, Lin Wun-Jie, SONG Ming-Hsiang, SU YU-TI, Yang Han-Jen
Принадлежит:

An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips. 1. A device comprising:a first semiconductor strip in a first well, the first semiconductor strip extending along a first direction, the first semiconductor strip having a first p-doped portion and a first n-doped portion;a second semiconductor strip in a second well, the second semiconductor strip extending along a second direction parallel to the first direction, the second semiconductor strip having a second p-doped portion and a second n-doped portion, wherein the first semiconductor strip and the second semiconductor strip are positioned such that a first line extending in a third direction perpendicular to the first direction extends through the first p-doped portion and the second n-doped portion, and a second line extending in a fourth direction perpendicular to the second direction extends through the first n-doped portion and the second p-doped portion; anda conductor electrically connecting the first n-doped portion to the second p-doped portion.2. The device of claim 1 , further comprising a third well interposed between the first well and the second well claim 1 , the third well having an opposite conductivity from the first well and the second well.3. The device of claim 1 , wherein the first p-doped portion is electrically coupled to an input/output pad.4. The device ...

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Номер записи: 16
24-02-2022 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20220059527A1
Автор: KOYA Shigeki, MA Shaojun, SASAKI Kenji, UMEMOTO Yasunari
Принадлежит: MURATA MANUFACTURING CO., LTD.

Each of cells arranged on a substrate surface along a first direction includes at least one unit transistor. Collector electrodes are arranged between two adjacent cells. A first cell, which is at least one of the cells, includes unit transistors arranged along the first direction. The unit transistors are connected in parallel to each another. In the first cell, the base electrode and the emitter electrode in each unit transistor are arranged along the first direction, and the order of arrangement of the base electrode and the emitter electrode is the same among the unit transistors. When looking at one first cell, a maximum value of distances in the first direction between the emitter electrodes of two adjacent unit transistors in the first cell being looked at is shorter than of a shorter one of distances between the first cell being looked at and adjacent cells. 1. A semiconductor device comprising:a substrate;a plurality of transistor cells arranged side by side along a first direction on a surface of the substrate, each of the plurality of transistor cells including at least one unit transistor; anda collector electrode arranged between two of the plurality of transistor cells adjacent to one another, whereina first transistor cell of the plurality of transistor cells includes a plurality of unit transistors arranged side by side along the first direction, at least one of the plurality of transistor cells being the first transistor cell,the plurality of unit transistors are connected in parallel to one another,each of the plurality of unit transistors includes a collector layer, a base layer arranged on the collector layer, an emitter layer arranged on the base layer, a base electrode electrically connected to the base layer, and an emitter electrode electrically connected to the emitter layer,the collector electrode is electrically connected to the collector layer of the unit transistor included in the transistor cell adjacent to the collector electrode in ...

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Номер записи: 17
14-02-2019 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20190051645A1
Автор: OBU Isao, SASAKI Kenji
Принадлежит: MURATA MANUFACTURING CO., LTD.

A semiconductor device includes a sub-collector layer disposed on a substrate, a bipolar transistor including a collector layer formed of a semiconductor having a lower carrier concentration than the sub-collector layer, a base layer, and an emitter layer, and a protection diode including a Schottky electrode. The Schottky electrode forms, in a partial region of an upper surface of the collector layer, a Schottky junction to the collector layer and is connected to one of the base layer and the emitter layer. In the collector layer, a part that forms a junction to the base layer and a part that forms a junction to the Schottky electrode are electrically connected to each other via the collector layer. 1. A semiconductor device comprising:a sub-collector layer disposed on a substrate and formed of a semiconductor;a bipolar transistor including a collector layer disposed on the sub-collector layer and formed of a semiconductor having a lower carrier concentration than the sub-collector layer, a base layer disposed on the collector layer and formed of a semiconductor, and an emitter layer disposed on the base layer and formed of a semiconductor; anda first protection diode including a first Schottky electrode that forms, in a partial region of an upper surface of the collector layer, a Schottky junction to the collector layer and that is connected to one of the base layer and the emitter layer,wherein, in the collector layer, a part that forms a junction to the base layer and a part that forms a junction to the first Schottky electrode are electrically connected to each other via the collector layer.2. The semiconductor device according to claim 1 , wherein:at least a part of the collector layer forms a mesa-shaped first mesa portion disposed on the sub-collector layer,the base layer forms at least an upper layer portion of a second mesa portion disposed on the first mesa portion, andthe first Schottky electrode forms a Schottky junction to an upper surface of the first ...

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Номер записи: 18
13-02-2020 дата публикации

FLOATING BASE SILICON CONTROLLED RECTIFIER

Номер: US20200051971A1
Автор: Chuang Che-Hao, YEH Chih-Ting
Принадлежит:

A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced. 1. A floating base silicon controlled rectifier , comprising:a first conductivity type layer;a second conductivity type well formed in said first conductivity type layer;a first conductivity type heavily doped region formed in said second conductivity type well and coupled to a first node; anda second conductivity type heavily doped region formed in said first conductivity type layer and coupled to a second node, such that said floating base silicon controlled rectifier acts as a forward diode.2. The floating base silicon controlled rectifier according to claim 1 , wherein when said first conductivity type is P type claim 1 , said second conductivity type is N type.3. The floating base silicon controlled rectifier according to claim 2 , wherein said first conductivity type layer is a P type substrate.4. The floating base silicon controlled rectifier according to claim 1 , further comprises a first conductivity type well formed in said first conductivity type layer and said second conductivity type heavily doped region is formed in said first conductivity type well.5. The floating base silicon controlled rectifier ...

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Номер записи: 19
22-05-2014 дата публикации

Junction-isolated blocking voltage devices with integrated protection structures and methods of forming the same

Номер: US20140138735A1
Автор: Brian B. Moane, David J. Clarke, Gavin Patrick Cosgrave, Javier Alejandro Salcedo, John Twomey, Juan Luo, Kieran K. Heffernan, Seamus Murnane, Stephen Denis Heffernan
Принадлежит: Analog Devices Inc

Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.

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Номер записи: 20
20-02-2020 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20200058735A1
Автор: Naito Tatsuya
Принадлежит:

Provided is a semiconductor device comprising: a semiconductor substrate; an active section provided in the semiconductor substrate; an edge termination structure section provided between the active section and an outer peripheral edge of the semiconductor substrate on an upper surface of the semiconductor substrate; and an end lifetime control unit that is provided in the semiconductor substrate in the edge termination structure section and is continuous in a range facing at least two or more diode sections arranged in the first direction, wherein the active section includes: a transistor section and the diode sections alternately arranged with the transistor section in a predetermined first direction on the upper surface of the semiconductor substrate. 1. A semiconductor device comprising:a semiconductor substrate;an active section provided in the semiconductor substrate;an edge termination structure section provided between the active section and an outer peripheral edge of the semiconductor substrate on an upper surface of the semiconductor substrate; andan end lifetime control unit that is provided in the semiconductor substrate in the edge termination structure section facing the active section in a second direction perpendicular to a predetermined first direction and is continuous in a range facing at least two or more diode sections arranged in the first direction, whereinthe active section includes:a transistor section; andthe diode sections alternately arranged with the transistor section in the first direction on the upper surface of the semiconductor substrate.2. The semiconductor device according to claim 1 , whereinthe end lifetime control unit is provided in a circular pattern to surround the active section on a plane parallel to the upper surface of the semiconductor substrate.3. The semiconductor device according to claim 1 , further comprising:an active section lifetime control unit provided in the semiconductor substrate in the diode sections; ...

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Номер записи: 21
28-02-2019 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20190068142A1
Автор: Tanaka Satoshi, TSUTSUI Takayuki
Принадлежит:

A semiconductor device includes the following elements. A chip has a main surface substantially parallel with a plane defined by first and second directions intersecting with each other. A power amplifier amplifies an input signal and outputs an amplified signal from plural output terminals. First and second filter circuits attenuate harmonics of the amplified signal. The first filter circuit includes a first capacitor connected between the plural output terminals and a ground. The second filter circuit includes a second capacitor connected between the plural output terminals and a ground. On the main surface of the chip, the plural output terminals are disposed side by side in the first direction, and the first capacitor is disposed on a side in the first direction with respect to the plural output terminals, while the second capacitor is disposed on a side opposite the first direction with respect to the plural output terminals. 1. A semiconductor device comprising:a chip having a main surface in a plane defined by first and second orthogonal directions;a power amplifier configured to amplify an input signal and output an amplified signal from a plurality of output terminals; andfirst and second filter circuits configured to attenuate harmonics of the amplified signal, whereinthe first filter circuit comprises a first capacitor connected between the plurality of output terminals and ground,the second filter circuit comprises a second capacitor connected between the plurality of output terminals and ground,the plurality of output terminals are disposed adjacent to each other in the first direction along a first side of the main surface of the chip,the first capacitor is disposed at a first end of the plurality of output terminals along the first direction, and the second capacitor is disposed at a second end of the plurality of output terminals along the first direction, the first end being opposite the second end.2. The semiconductor device according to claim 1 , ...

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Номер записи: 22
19-03-2015 дата публикации

INTEGRATED CIRCUIT DEVICE AND A METHOD FOR PROVIDING ESD PROTECTION

Номер: US20150076556A1
Автор: BESSE PATRICE, Givelin Philippe, Rolland Eric
Принадлежит: Freescale Semiconductor, Inc.

An integrated circuit (IC) device including an electrostatic discharge (ESD) protection network for a high voltage application. The ESD protection network includes a common diode structure coupled between an external contact of the IC device and a substrate of the IC device, such that the common diode structure is forward biased towards the external contact, a Darlington transistor structure coupled between the external contact and the substrate of the IC device, and the Darlington transistor structure includes: an emitter node coupled to the external contact; a collector node coupled to the substrate; and a base node coupled between the emitter node of the Darlington transistor structure and the common diode structure. The at least one ESD protection network further comprises an isolation diode structure coupled between the emitter node and the base node of the Darlington transistor structure such that the isolation diode structure is forward biased towards the base node. 1. An integrated circuit (IC) device comprising at least one electrostatic discharge (ESD) protection network for a high voltage application , the at least one ESD protection network comprising:a common diode structure operably coupled between at least one external contact of the IC device for which ESD protection is to be provided and a substrate of the IC device such that the common diode structure is forward biased towards the at least one external contact; an emitter node operably coupled to the at least one external contact of the IC device;', 'a collector node operably coupled to the substrate of the IC device; and', 'a base node operably coupled between the emitter node of the Darlington transistor structure and the common diode structure; and, 'at least one Darlington transistor structure operably coupled between the at least one external contact of the IC device for which ESD protection is to be provided and the substrate of the IC device, the at least one Darlington transistor structure ...

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Номер записи: 23
17-03-2016 дата публикации

High Voltage Semiconductor Power Switching Device

Номер: US20160079237A1
Автор: Chi-keung Tang, Chiu-Sing Celement Tse, On-Bon Peter Chan
Принадлежит: Mosway Semiconductor Ltd

A three terminal high voltage Darlington bipolar transistor power switching device includes two high voltage bipolar transistors, with collectors connected together serving as the collector terminal. The base of the first high voltage bipolar transistor serves as the base terminal. The emitter of the first high voltage bipolar transistor connects to the base of the second high voltage bipolar transistor (inner base), and the emitter of the second high voltage bipolar transistor serves as the emitter terminal. A diode has its anode connected to the inner base (emitter of the first high voltage bipolar transistor, or base of the second high voltage bipolar transistor), and its cathode connected to the base terminal. Similarly, a three terminal hybrid MOSFET/bipolar high voltage switching device can be formed by replacing the first high voltage bipolar transistor of the previous switching device by a high voltage MOSFET.

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Номер записи: 24
16-03-2017 дата публикации

SYNCHRONOUS SWITCHING CIRCUIT

Номер: US20170079101A1
Автор: "OCONNOR Kevin Joseph", NILES Andrew
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

An electrical circuit, in some embodiments, comprises a control circuit having a plurality of switches and an electrical load having a plurality of load components. A first of the plurality of switches is configured to control a first of the plurality of load components. A second of the plurality of switches is configured to control a second of the plurality of load components synchronously with the first of the plurality of switches. 1. An electrical circuit , comprising:a control circuit having a plurality of switches; andan electrical load coupled to the control circuit and having a plurality of load components,wherein a first of the plurality of switches is configured to control a first of the plurality of load components, andwherein a second of the plurality of switches is configured to control a second of the plurality of load components synchronously with the first of the plurality of switches.2. The electrical circuit of claim 1 , wherein each of the plurality of switches comprises a transistor.3. The electrical circuit of claim 2 , wherein each of the plurality of switches comprises a n-type semiconductor (NPN) bipolar junction transistor (BJT) or a p-type semiconductor (PNP) BJT.4. The electrical circuit of claim 1 , wherein an input of the first of the plurality of switches is coupled to a power supply claim 1 , and wherein an input of the second of the plurality of switches is coupled to the input of the first of the plurality of switches via a diode.5. The electrical circuit of claim 4 , wherein the diode is a Zener diode claim 4 , wherein the input of the first of the plurality of switches is coupled to a cathode of the Zener diode claim 4 , and wherein the input of the second of the plurality of switches is coupled to an anode of the Zener diode.6. The electrical circuit of wherein the Zener diode compensates for a variation in performance of the plurality of switches caused by a change in temperature of at least one of the plurality of switches or ...

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Номер записи: 25
02-04-2015 дата публикации

SCRs with Checker Board Layouts

Номер: US20150091054A1
Автор: CHENG Shui-Ming, Lin Wun-Jie, SONG Ming-Hsiang, SU YU-TI, Yang Han-Jen
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips. 1. An Electro-Static Discharge (ESD) protection circuit comprising:a plurality of groups of p-type heavily doped semiconductor strips (p+ strips);a plurality of groups of n-type heavily doped semiconductor strips (n+ strips), wherein the plurality of groups of p+ strips and the plurality of groups of n+ strips form an array having a plurality of rows and columns, and wherein in each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout; a first edge aligned to an edge of a group in the plurality of groups of p+ strips; and', 'a second edge aligned to an edge of a group in the plurality of groups of n+ strips; and, 'a plurality of gate stacks, each comprisinga conductor electrically connecting a first one of the plurality of groups of p+ strips to a second one of the plurality of groups of n+ strips, wherein the first one and the second one are in a same column.2. The ESD protection circuit of further comprising:an input/output pad;a Vss node; anda plurality of conductors comprising the conductor, wherein each of the plurality of conductors electrically connects one of the plurality of groups of p+ strips in a column to one of the plurality of groups of n+ strips in the column.3. The ESD ...

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Номер записи: 26
02-04-2015 дата публикации

SEMICONDUCTOR DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION

Номер: US20150091056A1
Автор: Marichal Olivier, Sorgeloos Bart, Van Camp Benjamin
Принадлежит: Sofics BVBA

Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may include a silicon controller rectifier (SCR) which may be triggered via at least one of its first trigger gate or second trigger gate. The ESD protection circuit may further include a highly doped region coupled to either the anode or cathode of the SCR, wherein the highly doped region may provide additional carriers to facilitate triggering of the SCR during an ESD event, whereby the SCR may be triggered more quickly. 1. An ESD protection circuit , comprising:a lowly doped P region;a lowly doped N region formed in the first lowly doped P region;a first highly doped P region formed entirely within the lowly doped P region;a second highly doped N region formed entirely within the lowly doped P region;a third highly doped P region formed entirely within the lowly doped N region;a fourth highly doped N region formed entirely within the lowly doped N region;a fifth highly doped N region formed entirely within the lowly doped P region, wherein the fifth highly doped N region is coupled to the third highly doped P region; anda trigger circuit coupled to at least one of the first highly doped P region and the fourth highly doped N region; the lowly doped N region, the lowly doped P region, and the second highly doped N region form an NPN transistor;', 'the third highly doped P region, the lowly doped N region, and the lowly doped P form a PNP transistor;', 'the NPN transistor and PNP transistor form a silicon controller rectifier (SCR); and', 'the fifth highly doped N region provides additional carriers to facilitate triggering of the SCR during an ESD event., 'wherein2. The ESD protection circuit of further comprising a gate claim 1 , disposed above an area between the second highly doped N region and the fifth highly doped N region.3. The ESD protection circuit of claim 1 , wherein the trigger circuit comprises at least one of a transistor claim 1 , a resistor claim 1 , a ...

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Номер записи: 27
12-03-2020 дата публикации

APPARATUS FOR AUTOMOTIVE AND COMMUNICATION SYSTEMS TRANSCEIVER INTERFACES

Номер: US20200083212A1
Автор: Parthasarathy Srivatsan, Salcedo Javier Alejandro, Zhao James
Принадлежит:

A communication interface protection device includes a first electrical overstress (EOS) protection switch electrically connected to a first terminal and a second EOS protection switch electrically connected to a second terminal. Each of the first and second EOS protection switches includes a first semiconductor-controlled rectifier (SCR) and a second SCR and a first diode having a cathode electrically connected to an anode of the first SCR and a second diode having a cathode electrically connected to an anode of the second SCR. The first EOS protection device is configured to be activated in response to an EOS condition that causes a first bias between the first and second terminals, and wherein the second EOS protection device is configured to be activated in response to an EOS condition that causes a second bias between the first and second terminals. 1. A communication interface protection device , comprising:a first electrical overstress (EOS) protection switch electrically connected to a first terminal and a second EOS protection switch electrically connected to a second terminal, a first semiconductor-controlled rectifier (SCR) and a second SCR, and', 'a first diode having a cathode electrically connected to an anode of the first SCR and a second diode having a cathode electrically connected to an anode of the second SCR,, 'wherein each of the first and second EOS protection switches compriseswherein the first EOS protection device is configured to activate in response to an EOS condition that causes a first bias state between the first and second terminals, and wherein the second EOS protection device is configured to activate in response to an EOS condition that causes a second bias state of opposite polarity to the first bias state between the first and second terminals.2. The protection device of claim 1 , wherein the first EOS protection switch is formed in a first device region formed in a semiconductor substrate claim 1 , wherein the second EOS ...

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Номер записи: 28
29-03-2018 дата публикации

DEVICE AND METHOD FOR DETECTING SEMICONDUCTOR SUBSTRATE THICKNESS

Номер: US20180091147A1
Автор: Dinh Viet Thanh, Jansman Andreas Bernardus Maria, WIDDERSHOVEN Franciscus Petrus
Принадлежит: NXP B.V.

Embodiments of devices and method for detecting semiconductor substrate thickness are disclosed. In an embodiment, an IC device includes a semiconductor substrate, a charge emitter embedded in the semiconductor substrate and configured to produce an electrical charge in the semiconductor substrate and a charge sensor embedded in the semiconductor substrate and configured to generate a response signal in response to the electrical charge produced in the semiconductor substrate. The magnitude of the response signal depends on the thickness of the semiconductor substrate. 1. An Integrated Circuit (IC) device , the IC device comprising:a semiconductor substrate;a charge emitter embedded in the semiconductor substrate and configured to produce an electrical charge in the semiconductor substrate;a charge sensor embedded in the semiconductor substrate and configured to generate a response signal in response to the electrical charge produced in the semiconductor substrate, wherein a magnitude of the response signal depends on a thickness of the semiconductor substrate; andan emitter controller configured to control a magnitude of electrical charge produced by the charge emitter.2. The IC device of claim 1 , further comprising a response analysis unit configured to generate thickness information of the semiconductor substrate based on the magnitude of the response signal.3. The IC device of claim 2 , wherein the thickness information of the semiconductor substrate comprises information regarding a change in the thickness of the semiconductor substrate.4. (canceled)5. The IC device of claim 1 ,wherein the emitter controller is further configured to control the charge emitter to produce a second electrical charge in the semiconductor substrate.wherein the charge sensor generates a second response signal in response to the second electrical charge, andwherein the IC device further comprises a response analysis unit configured to compare the second response signal to the ...

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Номер записи: 29
26-06-2014 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20140175552A1
Автор: HIROSE Yoshitsugu, Sakurai Hitomi
Принадлежит: SEIKO INSTRUMENTS INC.

Provided is a semiconductor device capable of suppressing latch-up generation and formed within a small area. In a minority carrier capture region, a P-type diffusion region (), an N-type well (), and a P-type diffusion region () are formed on a surface of a P-type semiconductor substrate (). An N-type diffusion region () is formed on a surface of the N-type well (). And the N-type well () is located between the P-type diffusion region () and the P-type diffusion region (). The P-type diffusion region () and the P-type diffusion region () are each connected to a ground pad () not by the shortest distance but respectively through metal film wirings arranged in a diverted way. 1. A semiconductor device , comprising:a P-type semiconductor substrate including a pad, a ground pad, and a power supply pad;a first N-type diffusion region that is formed on the P-type semiconductor substrate and is connected to the pad;a region of an internal circuit that is formed on the P-type semiconductor substrate; and the minority carrier capture region including a triple guard ring including:', 'a first P-type diffusion region;', 'a second P-type diffusion region; and', 'a second N-type diffusion region that is located between the first P-type diffusion region and the second P-type diffusion region,, 'a minority carrier capture region formed between the first N-type diffusion region and the region of the internal circuit, for capturing minority carriers in the P-type semiconductor substrate caused by a surge to the pad,'}the first P-type diffusion region and the second P-type diffusion region each being connected to the ground pad respectively through metal film wirings that are separately formed,the second N-type diffusion region being connected to the power supply pad.2. A semiconductor device according to claim 1 , further comprising an NMOS transistor that functions as an ESD protection circuit claim 1 , the NMOS transistor including a source and a gate connected to the ground pad ...

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Номер записи: 30
06-04-2017 дата публикации

SCRS with Checker Board Layouts

Номер: US20170098645A1
Автор: Han-Jen Yang, Li-Wei Chu, Wun-Jie Lin, Yu-Ti Su
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.

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Номер записи: 31
06-04-2017 дата публикации

METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT

Номер: US20170098691A1
Автор: Tian Wenbo, WANG Zhao, Yin Hang
Принадлежит:

Techniques related to a method for manufacturing an integrated circuit is disclosed. According to one embodiment, a method for manufacturing an integrated circuit on a wafer comprises a first device of the integrated circuit is formed on the wafer and a second device of the integrated circuit is formed on the wafer to make a projection area of the second device overlap with a projection area of the first device partially or completely. In one embodiment, two or more devices are formed in different layers of the integrated circuit, or formed at different depths in a same layer of the integrated circuit, so the two or more devices may share an area on the same wafer in a certain manner. Thereby, the area of the chip is saved and the chip cost of the integrated circuit is significantly reduced. 1. A method for manufacturing an integrated circuit on a wafer , comprising:forming a first device of the integrated circuit on the wafer; andforming a second device of the integrated circuit on the wafer to make a projection area of the second device overlap with a projection area of the first device partially or completely.2. The method according to claim 1 , wherein the first device is one of an N+ resistor claim 1 , a P+ resistor claim 1 , an Nwell resistor claim 1 , a Pwell resistor claim 1 , a MOS transistor and a bipolar transistor claim 1 , and the second device is a Poly resistor.3. The method according to claim 1 , wherein the first device is one of a capacitor claim 1 , a Poly resistor claim 1 , a Pwell resistor claim 1 , an Nwell resistor claim 1 , a MOS transistor and a bipolar transistor claim 1 , and the second device is a trimming circuit or a metal resistor.4. The method according to claim 1 , wherein the integrated circuit comprises:a first layer, comprising any one or any combination of an N+ resistor area, a P+ resistor area, an Nwell resistor area, a Pwell resistor area, an N+ area of a MOS transistor, a P+ area of a MOS transistor and a bipolar transistor ...

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Номер записи: 32
21-04-2016 дата публикации

Insulated Gate Bipolar Transistor Comprising Negative Temperature Coefficient Thermistor

Номер: US20160111415A1
Автор: Daniel PEDONE, Erich Griebl, Joachim Mahler, Peter Tuerkes, Philipp Seng, Stephan Voss, Thomas Basler, Wolfgang Scholz
Принадлежит: INFINEON TECHNOLOGIES AG

An embodiment of an IGBT comprises an emitter terminal at a first surface of a semiconductor body. The IGBT further comprises a collector terminal at a second surface of the semiconductor body. A first zone of a first conductivity type is in the semiconductor body between the first and second surfaces. A collector injection structure adjoins the second surface, the collector injection structure being of a second conductivity type and comprising a first part and a second part at a first lateral distance from each other. The IGBT further comprises a negative temperature coefficient thermistor adjoining the first zone in an area between the first and second parts.

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Номер записи: 33
30-04-2015 дата публикации

High Voltage Semiconductor Power Switching Device

Номер: US20150115315A1
Автор: Chan On-Bon Peter, Tang Chi-Keung, Tse Chiu-Sing Celement
Принадлежит: Mosway Semiconductor Limited

A three terminal high voltage Darlington bipolar transistor power switching device includes two high voltage bipolar transistors, with collectors connected together serving as the collector terminal. The base of the first high voltage bipolar transistor serves as the base terminal. The emitter of the first high voltage bipolar transistor connects to the base of the second high voltage bipolar transistor (inner base), and the emitter of the second high voltage bipolar transistor serves as the emitter terminal. A diode has its anode connected to the inner base (emitter of the first high voltage bipolar transistor, or base of the second high voltage bipolar transistor), and its cathode connected to the base terminal. Similarly, a three terminal hybrid MOSFET/bipolar high voltage switching device can be formed by replacing the first high voltage bipolar transistor of the previous switching device by a high voltage MOSFET. 1. A three terminal high voltage Darlington bipolar transistor power switching device having a connector terminal , a base terminal , an emitter terminal and including the following components:a first and a second high voltage bipolar transistor, each with a collector, a base and an emitter with collectors connected together serving as the collector terminal for the power switching device, the base of the first high voltage bipolar transistor serving as the base terminal of the power switching device, the emitter of the first high voltage bipolar transistor connecting to the base of the second high voltage bipolar transistor, and the emitter of the second high voltage bipolar transistor serving as the emitter terminal of the power switching device; anda diode having an anode and a cathode with the anode connected to transistor, or the base of the second high voltage bipolar transistor, and the cathode connected to the base terminal of the power switching device.2. The power switching device of claim 1 , wherein the diode is a Schottky diode.3. The ...

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Номер записи: 34
27-04-2017 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20170117201A1
Автор: YAMADA Takafumi
Принадлежит: FUJI ELECTRIC CO., LTD.

A semiconductor device includes: a semiconductor element; a laminated substrate including an insulating plate and a circuit board which is arranged on the front surface of the insulating plate and on which the semiconductor element is arranged; a lead terminal provided via solder in a major electrode of the front surface of the semiconductor element; and a sealing resin for sealing the semiconductor element, the laminated substrate, and the lead terminal, wherein a value of “Young's modulus of the sealing resin×(linear expansion coefficient of the lead terminal−linear expansion coefficient of the sealing resin)” is equal to or greater than −26×10(Pa/° C.) and equal to or less than 50×10(Pa/° C.). 1. A semiconductor device comprising:a semiconductor element including a major electrode at a front surface of the semiconductor element; an insulating plate, and', 'a circuit board which is arranged on a front surface of the insulating plate, and on which the semiconductor element is arranged;, 'a laminated substrate including'}solder;a lead terminal provided via the solder on the major electrode of the semiconductor element; anda sealing resin for sealing the semiconductor element, the laminated substrate, and the lead terminal, wherein{'sup': 3', '3, "a value of “a Young's modulus of the sealing resin×(a linear expansion coefficient of the lead terminal−a linear expansion coefficient of the sealing resin)” is equal to or greater than −26×10(Pa/° C.) and equal to or less than 50×10(Pa/° C.)."}2. The semiconductor device according to claim 1 , wherein a value of “the Young's modulus of the sealing resin×(the linear expansion coefficient of the lead terminal−the linear expansion coefficient of the sealing resin)×a height of the sealing resin” is equal to or greater than −255×10(Pa·mm/° C.) and equal to or less than 515×10(Pa·mm/° C.).3. The semiconductor device according to claim 2 , wherein the height of the sealing resin is equal to or greater than 6 mm and equal to or ...

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Номер записи: 35
27-04-2017 дата публикации

SOLDER BUMP PLACEMENT FOR THERMAL MANAGEMENT IN FLIP CHIP AMPLIFIERS

Номер: US20170117204A1
Автор: Gill Bharatjeet Singh, McPartlin Michael Joseph
Принадлежит:

Metal pillars are placed adjacent to NPN transistor arrays that are used in the power amplifier for RF power generation. By placing the metal pillars in intimate contact with the silicon substrate, the heat generated by the NPN transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar also forms an electrical ground connection in close proximity to the NPN transistors to function as a grounding point for emitter ballast resistors, which form an optimum electrothermal configuration for a linear SiGe power amplifier. 1. An amplifier comprising:at least one transistor formed over a silicon substrate; anda metal pillar formed over the silicon substrate such that, as viewed from above and looking down onto the metal pillar, the silicon substrate, and the at least one transistor, a footprint defined by a periphery of the metal pillar does not substantially overlap with a footprint defined by a periphery of the at least one transistor, the silicon substrate, the metal pillar, and the at least one transistor being arranged with respect to each other such that heat generated during operation of the at least one transistor is transferred through the silicon substrate to the metal pillar.2. The amplifier of wherein the metal pillar is configured to provide a flip chip interconnection for the amplifier.3. The amplifier of wherein the metal pillar is configured to provide a thermal path for the heat generated by the at least one transistor when the amplifier is operating.4. The amplifier of wherein the heat is transferred through one or more layers disposed between the silicon substrate and the metal pillar before reaching the metal pillar.5. The amplifier of further comprising a first resistor in communication with an emitter of the at least one transistor and the metal pillar claim 1 , the first resistor providing emitter-ballasting to the amplifier.6. The amplifier of further comprising a second resistor in communication with a base of ...

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Номер записи: 36
05-05-2016 дата публикации

METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR

Номер: US20160126236A1
Автор: HEMINGER David M., KEENA Thomas
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

In one embodiment, a semiconductor device may include a first transistor having a first current carrying electrode, a second current carrying electrode, and a control electrode; a first bipolar transistor having a collector coupled to the first current carrying electrode of the first transistor, a base coupled to the second current carrying electrode of the first transistor, and an emitter of the first bipolar transistor coupled to a first node of the semiconductor device. In an embodiment, the first node is connected to a terminal of a semiconductor package. An embodiment may include a semiconductor component coupled between the base of the first bipolar transistor and the emitter of the second bipolar transistor. 1. A bias resistor transistor semiconductor device comprising:a base terminal;an emitter terminal;a collector terminal;a main bipolar transistor having a base, an emitter coupled to the emitter terminal, and a collector coupled to the collector terminal;a first resistor having a first terminal coupled to the base of the main bipolar transistor, and having a second terminal coupled to the base terminal; anda protection bipolar transistor having a collector coupled to the collector of the main bipolar transistor, a base coupled to the emitter of the main bipolar transistor, and an emitter coupled to the base terminal, the protection bipolar transistor having an emitter to collector region that is configured to operate in avalanche mode in response to an ESD event.2. The bias resistor transistor semiconductor device of wherein at least a portion of the emitter of the protection bipolar transistor and at least a portion of the base of the protection bipolar transistor is formed to underlie a base contact pad of the bias resistor transistor semiconductor device wherein the base contact pad is coupled to the base terminal.3. The bias resistor transistor semiconductor device of wherein an emitter-base junction of the protection bipolar transistor is formed to ...

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Номер записи: 37
25-04-2019 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20190123003A1
Автор: GOTO Satoshi, NAMIE Hisanori, Tanaka Satoshi
Принадлежит:

A semiconductor device includes a semiconductor substrate, a transistor, and a first harmonic termination circuit. The transistor is formed at the semiconductor substrate. The transistor amplifies an input signal supplied to an input end and outputs an amplified signal through an output end. The first harmonic termination circuit attenuates a harmonic component included in the amplified signal. The first harmonic termination circuit is formed at the semiconductor substrate such that one end of the first harmonic termination circuit is connected to the output end of the transistor and the other end of the first harmonic termination circuit is connected to a ground end of the transistor. 1. A semiconductor device comprising:a semiconductor substrate;a transistor that amplifies an input signal supplied to an input end and outputs an amplified signal through an output end, the transistor being formed at the semiconductor substrate; anda first harmonic termination circuit configured to attenuate a harmonic component of the amplified signal, the first harmonic termination circuit being formed on the semiconductor substrate such that a first end of the first harmonic termination circuit is connected to the output end of the transistor and a second end of the first harmonic termination circuit is connected to a ground end of the transistor.2. The semiconductor device according to claim 1 ,wherein the transistor is a multi-finger transistor having a plurality of unit transistors, the first harmonic termination circuit being configured to attenuate a harmonic component of an amplified signal output from an output end of a first unit transistor, and being connected between the output end and a ground end of the first unit transistor,wherein the semiconductor device further comprises a second harmonic termination circuit configured to attenuate a harmonic component of an amplified signal output from an output end of a second unit transistor, the second harmonic termination ...

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Номер записи: 38
25-04-2019 дата публикации

FLIP CHIP AMPLIFIER FOR WIRELESS DEVICE

Номер: US20190123693A1
Автор: Gill Bharatjeet Singh, McPartlin Michael Joseph
Принадлежит:

Metal pillars are placed adjacent to transistor arrays in the power amplifiers that can be used in wireless devices. By placing the metal pillars in intimate contact with the silicon substrate and not over a substantial portion of the transistor arrays, the heat generated by the transistor arrays flows down into the silicon substrate and out the metal pillar. The metal pillar forms a solder bump of a flip chip power amplifier die, which when soldered to a module, further conducts the heat away from the transistor array. 1. A wireless mobile device comprising:an antenna configured to receive and transmit radio frequency signals;a transmit/receive switch configured to pass an amplified radio frequency signal to the antenna for transmission; anda multi-chip module including a flip chip amplifier die that includes at least one emitter-ballasted amplifier configured to amplify a radio frequency input signal and to generate the amplified radio frequency signal, the at least one emitter-ballasted amplifier including at least one transistor formed over and in thermal communication with a silicon substrate, a first resistor in communication with an emitter of the at least one transistor to form at least one emitter-ballasted transistor of the emitter-ballasted amplifier, and a metal pillar formed adjacent to the at least one emitter-ballasted transistor, in electrical communication with the first resistor, and in thermal communication with the silicon substrate, and an output matching network die including an output matching network circuit configured to match an impedance of a fundamental frequency of the amplified radio frequency signal.2. The wireless mobile device of wherein the at least one emitter-ballasted amplifier further includes a second resistor in communication with a base of the at least one emitter-ballasted transistor to provide base resistance.3. The wireless mobile device of wherein claim 1 , when looking down onto the metal pillar and the at least one ...

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Номер записи: 39
17-05-2018 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Номер: US20180138122A1
Автор: KODAMA Eisuke
Принадлежит:

As means for preventing a leakage of a fuse element cut by laser trimming due to a conductive residue or the like, an insulating film which has a high thermal conductivity and a relatively low adhesion is formed between an element isolation region and the fuse element in the case of forming the fuse element on the element isolation region in a groove on a main surface of an epitaxial substrate. When the fuse element is cut by performing the laser trimming, both of a part of the fuse element and the insulating film below the part of the fuse element are removed. 110-. (canceled)11. A manufacturing method of a semiconductor device , comprising the steps of:(a) preparing a semiconductor substrate;(b) forming a first insulating film on the semiconductor substrate;(c) forming a second insulating film on the first insulating film; and(d) forming a conductive film containing silicon on the second insulating film,wherein the conductive film constitutes a fuse, andthe second insulating film has a thermal conductivity higher than that of the first insulating film.12. The manufacturing method of a semiconductor device according to claim 11 ,wherein adhesion of the second insulating film to the first insulating film is lower than adhesion of a silicon film to the first insulating film.13. The manufacturing method of a semiconductor device according to claim 11 , further comprising the step of:(b1) prior to the step (c), forming a groove on an upper surface of the first insulating film,wherein in the step (c), a part of the second insulating film is buried in the groove.14. The manufacturing method of a semiconductor device according to claim 13 ,wherein in the step (b1), the groove is formed by anisotropic etching.15. The manufacturing method of a semiconductor device according to claim 11 , further comprising the steps of:(e) forming a third insulating film on the conductive film; and(f) forming an opening, which penetrates through a stacked film made up of the second ...

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Номер записи: 40
17-05-2018 дата публикации

POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR

Номер: US20180138265A1
Автор: SONEDA Shinya
Принадлежит: Mitsubishi Electric Corporation

An RC-IGBT according to the invention includes a high electric field cell formed in a region surrounded by an IGBT cell or in a region surrounded by a diode cell, and an n+ diffusion layer formed at a position opposed to the high electric field cell, the position being on a second main surface of an n− type drift layer. The high electric field cell has a higher maximum electric field intensity generated when a voltage is applied between main terminals than maximum electric field intensities of the IGBT cell, the diode cell, and a withstand voltage holding structure. Additionally, a p+ type collector layer and the high electric field cell fail to overlap with each other in a direction vertical to a first main surface of the n− type drift layer in a plane view. 1. A power semiconductor device comprising:a first conductive type drift layer;an IGBT cell, a diode cell, and a withstand voltage holding structure which are formed on a first main surface of said drift layer;a high electric field cell formed in a region surrounded by said IGBT cell or in a region surrounded by said diode cell on said first main surface of said drift layer;a second conductive type collector layer formed at a position opposed to said IGBT cell and said withstand voltage holding structure, the position being on a second main surface opposite to said first main surface of said drift layer;a first conductive type cathode layer formed at a position opposed to said diode cell on said second main surface of said drift layer; anda first conductive type diffusion layer formed at a position opposed to said high electric field cell on said second main surface of said drift layer, whereinsaid high electric field cell has a higher maximum electric field intensity generated when a voltage is applied between main terminals than maximum electric field intensities of said IGBT cell, said diode cell and said withstand voltage holding structure, andsaid collector layer and said high electric field cell fail to ...

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Номер записи: 41
18-05-2017 дата публикации

TVS Structures for High Surge AND Low Capacitance

Номер: US20170141097A1
Автор: Limin Weng, Madhur Bobde, Wenjiang Zeng
Принадлежит: Individual

A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device further comprises a plurality of contact trenches opened and extended to a lower part of the epitaxial layer filled with a doped polysilicon layer of a second conductivity type wherein the trenches are further surrounded by a heavy dopant region of the second conductivity type. The TVS device further includes a metal contact layer disposed on a top surface of the epitaxial layer electrically connected to a Vcc electrode wherein the metal contact layer further directly contacting the doped polysilicon layer and the heavy dopant region of the second conductivity type.

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Номер записи: 42
26-05-2016 дата публикации

INTEGRATED CIRCUIT DEVICE

Номер: US20160148929A1
Автор: CHANG Yin-Ku, Lee Sheng-Yuan
Принадлежит:

The invention provides an integrated circuit device. The integrated circuit device includes a substrate. A first capacitor is disposed on the substrate. A first metal pattern is coupled to a first electrode of the first capacitor. A second metal pattern is coupled to a first electrode of the second capacitor. A third metal pattern is disposed over the first and second metal patterns. The third metal pattern covers the first capacitor, the first metal pattern, and the second metal pattern. The third metal pattern is electrically grounded. An inductor is disposed over the third metal pattern. 1. An integrated circuit device , comprising:a substrate;a first capacitor disposed on the substrate;a first metal pattern coupled to a first electrode of the first capacitor;a second metal pattern coupled to a second electrode of the first capacitor;a third metal pattern disposed over the first and second metal patterns and covering the first capacitor, the first metal pattern, and the second metal pattern, wherein the third metal pattern is coupled to ground; andan inductor disposed over the third metal pattern,wherein the first capacitor comprises:a first oxide layer disposed among the first, second, and third metal patterns, wherein the first metal pattern serves as the first electrode of the first capacitor, the second metal pattern serves as the second electrode of the first capacitor.2. The integrated circuit device as claimed in claim 1 , further comprising:a plurality of metal layers disposed on the substrate, wherein the third metal pattern and the first metal pattern respectively occupy different metal layers of the metal layers, and wherein the third metal pattern and the second metal pattern respectively occupy different metal layers of the metal layers.3. The integrated circuit device as claimed in claim 1 , wherein the third metal pattern is disposed directly under the inductor claim 1 , wherein the first metal pattern and the second metal pattern are disposed ...

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Номер записи: 43
30-04-2020 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20200135717A1
Автор: KANEDA Mitsuru, TAKAHASHI Tetsuo
Принадлежит: Mitsubishi Electric Corporation

A semiconductor device includes an IGBT as a switching element, and a diode. The IGBT includes: a p type channel doped layer formed in a surface layer part on a front side of a semiconductor substrate; a ptype diffusion layer and an ntype source layer individually selectively formed in a surface layer part of the p type channel doped layer; and an emitter electrode connected to the ntype source layer and the ptype diffusion layer. A part of the p type channel doped layer reaches a front-side surface of the semiconductor substrate and is connected to the emitter electrode. On the front-side surface of the semiconductor substrate, the ptype diffusion layer is interposed between the p type channel doped layer and an ntype source layer, and the p type channel doped layer and the ntype source layer are not adjacent to each other. 1. A semiconductor device comprising: a channel doped layer of a first conductivity type formed in a surface layer part on a front side of a semiconductor substrate,', 'a first diffusion layer of a first conductivity type selectively formed in a surface layer part of the channel doped layer and having a higher impurity concentration than that of the channel doped layer,', 'a source layer of a second conductivity type selectively formed in a surface layer part of the channel doped layer, and', 'an electrode formed on a front-side surface of the semiconductor substrate and connected to the source layer and the first diffusion layer; and, 'a switching element having'}a diode formed between the first diffusion layer and a second diffusion layer of a second conductivity type formed in a surface layer part on a back side of the semiconductor substrate,whereina part of the channel doped layer reaches a front-side surface of the semiconductor substrate and is connected to the electrode, andon a front-side surface of the semiconductor substrate, the first diffusion layer is interposed between the channel doped layer and the source layer, and the channel ...

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Номер записи: 44
25-05-2017 дата публикации

FACILITATION OF INCREASED LOCKING RANGE TRANSISTORS

Номер: US20170149438A1
Автор: Shum Kam Man, XUE Quan, Zhou Haifeng
Принадлежит:

Transistors can be used for a variety of electronic-based applications. Therefore, transistor efficiency and performance is of importance. An apparatus is presented herein to increase the locking range of transistors by leveraging cross-coupled injection transistors in conjunction with symmetry injection transistors. The transistor efficiency can also be increase by reducing a parasitic capacitance associated with the components of the transistor. 1. A method , comprising:forming a four-terminal transistor comprising a first injection transistor and a second injection transistor and a first symmetry injection transistor and a second symmetry injection transistor;connecting a first drain of the first injection transistor, a second drain of the first symmetry injection transistor, and a first gate of the second injection transistor to a first terminal;connecting a second gate of the first symmetry injection transistor and a third gate of the second symmetry injection to a second terminal;connecting a third drain of the second injection transistor, a fourth drain of the second symmetry injection transistor, and a fourth gate of the second injection transistor to a third terminal;cross-connecting the first drain of the first injection transistor with the first gate of the second injection transistor; andcross-connecting the third drain of the second injection transistor with the fourth gate of the first injection transistor.2. The method of claim 1 , further comprising:connecting a first source of the first symmetry injection transistor and a second source of the second symmetry injection transistor to a ground.3. The method of claim 2 , further comprising:connecting a third source of the first injection transistor and a fourth source of the second injection transistor to another ground.4. The method of claim 1 , further comprising:connecting a first source of the first injection transistor and a second source of the second injection transistor to a ground.5. The method ...

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Номер записи: 45
31-05-2018 дата публикации

SEMICONDUCTOR DEVICE, RC-IGBT, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20180151711A1
Автор: Yamada Kazuhiro
Принадлежит:

According to one embodiment, a semiconductor device includes a semiconductor substrate including a first principal surface and a second principal surface, an emitter electrode , a gate wiring , a collector electrode , a first unit cell region that is extended along one direction in a plane parallel to the first principal surface, and a second unit cell region that is extended along one direction, in which the semiconductor substrate of the first unit cell region and the second unit cell region includes an N− type drift layer , an N type hole barrier layer , a trench electrode , a P type body layer , an insulating film , an N type field stop layer , and a P+ type collector layer , and the second unit cell region includes an N type cathode layer that is fitted into the collector layer and is extended along one direction. 1. A semiconductor device comprising:a semiconductor substrate including a first principal surface and a second principal surface;an emitter electrode and a gate wiring provided in the first principal surface;a collector electrode provided in the second principal surface; and a drift layer of a first conductive type;', 'a hole barrier layer of a first conductive type that is provided to be closer to the first principal surface than the drift layer is and is extended in the one direction;', 'a pair of trench electrodes that are provided in such a way as to sandwich the hole barrier layer from both sides thereof in another direction perpendicular to the one direction and are extended in the one direction;', 'a body layer of a second conductive type that is provided to be closer to the first principal surface than the hole barrier layer is, is extended in the one direction, and is connected to the emitter electrode;', 'an insulating film that is provided between the trench electrode, and the drift layer, the hole barrier layer, and the body layer;', 'a field stop layer of a first conductive type provided to be closer to the second principal surface than ...

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Номер записи: 46
16-05-2019 дата публикации

INTEGRATED ELECTRONIC DEVICE INCLUDING AN EDGE TERMINATION STRUCTURE WITH A PLURALITY OF DIODE CHAINS

Номер: US20190148483A1
Автор: MENTA Fernando Giovanni, PISANO Salvatore
Принадлежит:

An integrated electronic device forming a power device and including: a semiconductor body; a first conductive region and a second conductive region, which extend over the semiconductor body, the second conductive region surrounding the first conductive region at a distance; and an edge termination structure, which is arranged between the first and second conductive regions and includes a dielectric region, which delimits an active area of the power device, and a semiconductive structure, which extends over the dielectric region and includes a plurality of diode chains, each diode chain including a plurality of first semiconductive regions of a first conductivity type and a plurality of second semiconductive regions of a second conductivity type, the first and second semiconductive regions being arranged in alternating fashion so as to form a series circuit including a plurality of first and second diodes, which are spaced apart from one another and have opposite orientations. 1. An integrated electronic device , comprising:a semiconductor body;a first conductive region and a second conductive region, which extend on top of the semiconductor body, the second conductive region surrounding, at a distance, the first conductive region; andan edge termination structure, arranged between the first and second conductive regions and including a dielectric region, which delimits an active area of the electronic device, said first conductive region extending at least in part on top of the active area;wherein the edge termination structure further comprises a semiconductive structure, which extends on top of the dielectric region and comprises a plurality of diode chains, each diode chain having a first end and a second end, which are electrically coupled, respectively, to the first and second conductive regions; and wherein each diode chain comprises a plurality of first semiconductive regions, which have a first conductivity type, and a plurality of second semiconductive ...

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Номер записи: 47
31-05-2018 дата публикации

INVERTER SWITCHING DEVICES WITH GATE COILS TO ENHANCE COMMON SOURCE INDUCTANCE

Номер: US20180152113A1
Автор: Chen Chingchi, Degner Michael W., XU ZHUXIAN
Принадлежит:

A selectable increase in the common source inductance is obtained by a layout for a power module used for a half-bridge phase leg in an inverter for an electrically-driven vehicle. The power module comprises a pair of transistor dies connected to positive, negative, and AC conductive tracks for carrying bridge currents. The module includes a pair of gate drive pins and a pair of gate drive coils connecting a respective pin and die. The gate drive coils are disposed in a region between the positive and negative tracks containing a flux generated by the currents having a locally greatest rate of change. The coils may preferably be comprised of traces on an auxiliary printed circuit board incorporated in the module. The gate drive pins can be on the gate side or the emitter side of the transistor dies. 1. A half-bridge power module comprising;a pair of transistor dies connected to positive, negative, and AC conductive tracks for carrying bridge currents;a pair of gate drive pins; anda pair of gate drive coils connecting a respective pin and die, wherein the gate drive coils are disposed in a region between the positive and negative tracks containing a flux generated by the currents having a locally greatest rate of change.2. The power module of further comprising an auxiliary printed circuit board claim 1 , wherein the gate drive coils are comprised of traces on the auxiliary printed circuit board.3. The power module of wherein the gate drive coils are disposed on opposite planar surfaces of the auxiliary printed circuit board.4. The power module of further comprising an encapsulating body retaining the dies and auxiliary printed circuit board.5. The power module of wherein the pair of gate drive pins are comprised of gate pins on a gate side of the transistor dies.6. The power module of wherein the gate pins are turn-on pins for turning on the transistors claim 5 , wherein the module further comprises a pair of gate turn-off pins for turning off the transistors claim ...

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Номер записи: 48
09-06-2016 дата публикации

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Номер: US20160163641A1
Автор: BAO XIAOYAN, GE HONGTAO
Принадлежит:

A method for forming a semiconductor device includes, sequentially, providing a substrate having a first region and a second region; forming a first dielectric layer on the substrate; forming a second dielectric layer having a plurality of first openings exposing portions of a top surface of the first dielectric layer; forming a first conductive layer in the first openings; etching the second dielectric layer and the first dielectric layer in the second region until the substrate is exposed to form a plurality of second openings; forming passivation regions in portions of the substrate exposed by the second openings; exposing the surface of the first dielectric layer in the second region; forming a third dielectric layer on the surface of the first dielectric layer and in the second openings; and forming a second conductive layer, a portion of which is configured as an inductor, over the third dielectric layer. 1. A method for fabricating a semiconductor device , comprising:providing a substrate having a first region and a second region;forming a first dielectric layer on a surface of the substrate;forming a second dielectric layer having a plurality of first openings exposing portion of a top surface of the first dielectric layer;forming a first conductive layer in the first openings;etching the second dielectric layer in the second region and the first dielectric layer in the second region until the surface of the substrate is exposed to form a plurality of second openings;forming passivation regions in portions of the substrate exposed by the second openings;exposing the surface of the first dielectric layer in the second region;forming a third dielectric layer on the surface of the first dielectric layer and in the second openings; andforming a second conductive layer, a portion of which is configured as an inductor, over the third dielectric layer in the second region.2. The method according to claim 1 , the substrate further comprises:a base substrate;an ...

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Номер записи: 49
04-09-2014 дата публикации

CIRCUIT INCLUDING A RESISTIVE ELEMENT, A DIODE, AND A SWITCH AND A METHOD OF USING THE SAME

Номер: US20140247527A1
Автор: MIYAMOTO Yuta, OTAKE Seiji, Takeda Yasuhiro
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

An ESD protection element can have a high ESD protection characteristic which has a desired breakdown voltage and flows a large discharge current. A junction diode is formed by an N+ type buried layer having a proper impurity concentration and a P+ type buried layer. The P+ type buried layer is combined with a P+ type drawing layer to penetrate an N− type epitaxial layer and be connected to an anode element. An N+ type diffusion layer and a P+ typed diffusion layer connected to an surrounding the N+ type diffusion layer are formed in the N− epitaxial layer surrounded by the P+ type buried layer etc. The N+ type diffusion layer and P+ type diffusion layer are connected to a cathode electrode. An ESD protection element is formed by the PN junction diode and a parasitic PNP bipolar transistor which uses the P+ type diffusion layer as an emitted, the N− type epitaxial layer as the base, and the P+ type drawing layer etc. as the collector. 1. An integrated circuit comprising:a resistive element having a first terminal and a second terminal, wherein the first terminal is coupled to a first power supply terminal;a diode having an anode and a cathode, wherein the cathode is coupled to the second terminal of the resistive element, and the anode is coupled to a second power supply terminal; anda switch having a first current terminal, a second current terminal, and a control electrode, wherein the control electrode is coupled to the second terminal of the resistive element and the cathode of the diode.2. The integrated circuit of claim 1 , further comprising an internal circuit coupled to the first power supply and the second power supply claim 1 , wherein a combination of the resistive element claim 1 , the diode claim 1 , and the switch is an electrostatic discharge protection element.3. The integrated circuit of claim 1 , wherein the first current terminal of the switch is coupled to the first power supply terminal claim 1 , and the second current terminal of the switch is ...

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Номер записи: 50
18-06-2015 дата публикации

Semiconductor Device and Switching Circuit

Номер: US20150171070A1
Автор: Hanaoka Masayuki
Принадлежит: Sanken Electric Co., Ltd.

A semiconductor device of the present invention includes: a main switching element, a current-sensing switching element and a surge protection element, which are formed on a single semiconductor substrate, wherein the surge protection element is a bidirectional diode connected between a first main electrode of the main switching element and a first main electrode of the current-sensing switching element. Also, a switching circuit of this disclosure includes above semiconductor device and a detection resistor connected to the first main electrode of the current-sensing switching element; and a driving device that drives the semiconductor device based on a voltage drop occurred in the detection resistor when the semiconductor device is turned on. 1. A semiconductor device comprisinga main switching element, a current-sensing switching element and a surge protection element, which are formed on a single semiconductor substrate,wherein the surge protection element is a bidirectional diode connected between a first main electrode of the main switching element and a first main electrode of the current-sensing switching element.2. The semiconductor device according to claim 1 ,wherein the surge protection element is formed by a poly-silicon layer arranged on the semiconductor substrate with interposing an insulation layer.3. The semiconductor device according to claim 1 , further comprisinga resistor connected in parallel with the surge protection element, between the first main electrode of the main switching element and the first main electrode of the current-sensing switching element.4. The semiconductor device according to claim 3 ,wherein the resistor is formed by a poly-silicon layer arranged on the semiconductor substrate with interposing an insulation layer.5. The semiconductor device according to claim 1 , further comprisinga detection resistor connected between the first main electrode of the current-sensing switching element and a ground,wherein a withstanding ...

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Номер записи: 51
14-06-2018 дата публикации

Insulated gate semiconductor device

Номер: US20180166436A1
Автор: Shigeki Sato
Принадлежит: Fuji Electric Co Ltd

An insulated gate semiconductor device includes a main insulated gate transistor having a gate electrode controlling a main current, a current-detecting insulated gate transistor, which is disposed in parallel to a main insulated gate transistor, outputting a current on a proportional basis in size between the transistors to the main current flowing through the main insulated gate transistor, a temperature detecting diode formed integrally with these insulated gate transistors in a semiconductor substrate. Interposing an ESD tolerance Zener diode between an emitter electrode of the current-detecting insulated gate transistor and an anode electrode of the temperature detecting diode leads to securing the ESD tolerance for the current-detecting insulated gate transistor by using the temperature detecting diode.

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Номер записи: 52
21-06-2018 дата публикации

POWER SEMICONDUCTOR DEVICE AND METHOD THEREFOR

Номер: US20180175142A1
Автор: SONEDA Shinya
Принадлежит: Mitsubishi Electric Corporation

An RC-IGBT according to the invention includes a high electric field cell formed in a region surrounded by an IGBT cell or in a region surrounded by a diode cell, and an n+ diffusion layer formed at a position opposed to the high electric field cell, the position being on a second main surface of an n− type drift layer. The high electric field cell has a higher maximum electric field intensity generated when a voltage is applied between main terminals than maximum electric field intensities of the IGBT cell, the diode cell, and a withstand voltage holding structure. Additionally, a p+ type collector layer and the high electric field cell fail to overlap with each other in a direction vertical to a first main surface of the n− type drift layer in a plane view. 1 a first conductive type drift layer,', 'an IGBT cell, a diode cell, and a withstand voltage holding structure which are formed on a first main surface of said drift layer,', 'a high electric field cell formed in a region surrounded by said IGBT cell or in a region surrounded by said diode cell on said first main surface of said drift layer,', 'a second conductive type collector layer formed at a position opposed to said IGBT cell and said withstand voltage holding structure, the position being on a second main surface opposite to said first main surface of said drift layer,', 'a first conductive type cathode layer formed at a position opposed to said diode cell on said second main surface of said drift layer, and', 'a first conductive type diffusion layer formed at a position opposed to said high electric field cell on said second main surface of said drift layer,', 'wherein said high electric field cell has a higher maximum electric field intensity generated when a voltage is applied between main terminals than maximum electric field intensities of said IGBT cell, said diode cell and said withstand voltage holding structure, and', 'wherein said collector layer and said high electric field cell fail to ...

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Номер записи: 53
22-06-2017 дата публикации

Adjustable Multi-Turn Magnetic Coupling Device

Номер: US20170179216A1
Автор: CHAN Hao-Chieh, Li Chao Chieh
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd

According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor. 1. An integrated circuit device , comprising:at least one inductor having at least one turn;a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, wherein the at least two magnetic coupling turns are disposed adjacent to the at least one inductor to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn; anda power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring.2. The integrated circuit device of claim 1 , wherein all of the at least two magnetic coupling turns are outside the at least one turns of the inductor.3. The integrated circuit device of claim 1 , wherein all of the at least two magnetic coupling turns are inside the at least one turns of the inductor.4. The ...

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Номер записи: 54
29-06-2017 дата публикации

Overvoltage protection device

Номер: US20170187182A1
Автор: Norihiko Tanaka
Принадлежит: Alpine Electronics Inc

An overvoltage protection device includes a resistor that is connected in series between an internal signal line connected to a communication terminal of a processor and a communication line, a diode of which a cathode is connected to the internal signal line and an anode is connected to a ground, and a PNP transistor of which a base is connected to a power supply terminal, an emitter is connected to the internal signal line, and a collector is connected to the ground. When a base-emitter voltage (a junction saturation voltage) of the transistor in operation is defined as VBE and a power source is turned on (a voltage V 1 ) by the operation of the transistor, a voltage of the internal signal line is limited to the source voltage V 1 +VBE. When the power source is turned off (a voltage 0 V), the voltage of the internal signal line is limited to the source voltage 0 V+VBE.

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Номер записи: 55
16-07-2015 дата публикации

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF FORMING

Номер: US20150200134A1
Автор: CHEN Chih-Kuan, YANG Zhuo-Cang
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Embodiments of a semiconductor device structure and a method of forming a semiconductor device structure are provided. The semiconductor device structure includes an insulating layer having a top surface, a bottom surface and a side surface. The semiconductor device structure also includes a first semiconductor substrate formed over the bottom surface of the first insulating layer. The semiconductor device structure further includes a conductive feature formed only adjacent to the side surface of the insulating layer on the first semiconductor substrate. In addition, the semiconductor device structure includes a second semiconductor substrate formed over the top surface of the insulating layer. The second semiconductor substrate includes a device-forming region formed directly over the insulating layer such that a projection region of the device-forming region is positioned inside the insulating layer. 1. A semiconductor device structure , comprising:a first semiconductor substrate;an insulating layer over the first semiconductor substrate;a second semiconductor substrate bonded to the insulating layer, wherein the second semiconductor substrate comprises a first device-forming region and a second device-forming region isolated from each other; 'a first well doped region, wherein a bottom of a boundary of the first well doped region is in direct contact with the insulating layer; and', 'a first semiconductor device in the first device-forming region, comprising 'a second well doped region, wherein a bottom of a boundary of the second well doped region is in direct contact with the insulating layer.', 'a second semiconductor device in the second device-forming region, comprising2. The semiconductor device structure as claimed in claim 1 , wherein the first semiconductor device or the second semiconductor device comprises a metal-oxide-semiconductor (MOS) transistor device claim 1 , a bipolar junction transistor (BJT) claim 1 , a diode claim 1 , a resistor or a ...

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Номер записи: 56
16-07-2015 дата публикации

Full Bridge Rectifier Module

Номер: US20150200184A1
Автор: Seok Kyoung Wook
Принадлежит:

A full bridge rectifier includes four bipolar transistors, each of which has an associated parallel diode. A first pair of inductors provides inductive current splitting and thereby provides base current to/from one pair of the bipolar transistors so that the collector-to-emitter voltages of the bipolar transistors are low. A second pair of inductors similarly provides inductive current splitting to provide base current to/from the other pair of bipolar transistors. In one embodiment, all components are provided in a four terminal full bridge rectifier module. The module can be used as a drop-in replacement for a conventional four terminal full bridge diode rectifier. When current flows through the rectifier module, however, the voltage drop across the module is less than one volt. Due to the reduced low voltage drop, power loss in the rectifier module is reduced as compared to power loss in a conventional full bridge diode rectifier. 124-. (canceled)25. A packaged semiconductor device , comprising:a first package terminal;a second package terminal;a third package terminal;a fourth package terminal;a fifth package terminal;a sixth package terminal;{'b': '1', 'a first bipolar transistor BJT having an emitter coupled to the first package terminal, having a collector coupled to the third package terminal, and having a base directly coupled to the fifth package terminal;'}{'b': '2', 'a second bipolar transistor BJT having an emitter coupled to the second package terminal, having a collector coupled to the third package terminal, and having a base directly coupled to the fifth package terminal;'}{'b': '3', 'a third bipolar transistor BJT having an emitter coupled to the first package terminal, having a collector coupled to the fourth package terminal, and having a base directly coupled to the sixth package terminal;'}{'b': '4', 'a fourth bipolar transistor BJT having an emitter coupled to the second package terminal, having a collector coupled to the fourth package ...

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Номер записи: 57
05-07-2018 дата публикации

Silicon-controlled rectifiers having a cathode coupled by a contact with a diode trigger

Номер: US20180190644A1
Автор: John B. Campi, JR., Manjunatha Prabu, Mujahid Muhammad, Robert J. Gauthier, Jr., Souvick Mitra, You Li
Принадлежит: Globalfoundries Inc

Silicon-controlled rectifiers, electrostatic discharge circuits, and methods of fabricating a silicon-controlled rectifier for use in an electrostatic discharge circuit. A device structure for the silicon controlled rectifier includes a first well of a first conductivity type in a semiconductor layer, a second well of a second conductivity type in the semiconductor layer, a cathode coupled with the first well, and an anode coupled with the second well. First and second body contacts are coupled with the first well, and the first and second body contacts each have the first conductivity type. A triggering device may be coupled with the first body contact.

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Номер записи: 58
22-07-2021 дата публикации

ADJUSTABLE MULTI-TURN MAGNETIC COUPLING DEVICE

Номер: US20210225999A1
Автор: CHAN Hao-Chieh, Li Chao Chieh
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor. 1. A method , comprising:conducting a first current through a transformer, wherein the transformer comprises a first inductor and a second inductor, wherein the first and second inductors each comprises at least one turn; andconducing a second current through a magnetic coupling ring, wherein the magnetic coupling ring comprises at least two magnetic coupling turns each disposed to be either surrounding or surrounded by the transformer in a top view to enable magnetic coupling between the magnetic coupling ring and the transformer,wherein the first current through the transformer is conducted in a first direction, andthe second current through the magnetic coupling ring is conducted in a second direction opposite the first direction.2. The method of claim 1 , wherein all of the at least two magnetic coupling turns are disposed surrounding the transformer.3. The method of claim 1 , wherein all of the at least two magnetic coupling turns are disposed surrounded by the transformer.4. The method of claim 1 , wherein at least one of the at least two ...

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Номер записи: 59
27-06-2019 дата публикации

Semiconductor device

Номер: US20190198464A1
Автор: Isao Obu, Takayuki Tsutsui
Принадлежит: Murata Manufacturing Co Ltd

A plurality of unit transistors that are connected in parallel to each other are formed on a substrate. In addition, a ground bump is provided on the substrate. A plurality of first capacitors are each provided for a corresponding one of the plurality of unit transistors and each connect an output electrode of the corresponding one of the plurality of unit transistors and the ground bump to each other.

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Номер записи: 60
27-06-2019 дата публикации

METHODS FOR THERMAL MANAGEMENT IN AMPLIFIERS

Номер: US20190199294A1
Автор: Gill Bharatjeet Singh, McPartlin Michael Joseph
Принадлежит:

Methods of managing heat generated by amplifiers are disclosed. A metal pillar, a plurality of resistors, and a transistor array are formed over a silicon substrate. The plurality of resistors provide emitter-ballasting for the amplifier. A footprint defined by a periphery of the metal pillar is adjacent to a footprint defined by a periphery of the transistor array and overlaps a footprint defined by a periphery of the plurality of resistors so that heat generated during operation of the amplifier is transferred through the silicon substrate to the metal pillar. 1. A method for thermal management of an amplifier , the method comprising:forming a transistor array over a silicon substrate; andforming a metal pillar over the silicon substrate such that a footprint defined by a periphery of the metal pillar is adjacent to a footprint defined by a periphery of the transistor array, heat generated during operation of the transistor array being transferred through the silicon substrate to the metal pillar.2. The method of wherein the footprint defined by the periphery of the metal pillar further overlaps a footprint defined by a periphery of a plurality of first resistors formed over the silicon substrate.3. The method of wherein a first end of a resistor of the plurality of first resistors is in communication with an emitter of a transistor of the transistor array.4. The method of wherein the resistor of the plurality of first resistors provides emitter-ballasting for the amplifier.5. The method of wherein a second end of the resistor of the plurality of first resistors in communication with the metal pillar.6. The method of wherein the metal pillar is configured to provide a flip chip interconnection for the amplifier.7. The method of wherein the metal pillar is configured to provide a ground connection.8. The method of further comprising forming one or more inter-level metal layers between the silicon substrate and the metal pillar.9. The method of wherein the heat is ...

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Номер записи: 61
06-08-2015 дата публикации

Surface Mountable Power Components

Номер: US20150221588A1
Автор: "ODell Clive", Burbidge Rupert, Cutler Daniel, Palmer Scott, Pavier Mark
Принадлежит:

According to an exemplary implementation, a power component includes a component substrate and a power semiconductor device electrically and mechanically coupled to the component substrate. The power component also includes at least one first peripheral contact and at least one second peripheral contact situated on the component substrate. A power semiconductor device is situated between the at least one first peripheral contact and the at least one second peripheral contact. The at least one first peripheral contact, the at least one second peripheral contact, and a surface electrode of the power semiconductor device are configured for surface mounting. The at least one first peripheral contact can be electrically coupled to the power semiconductor device. 120-. (canceled)21. A power component comprising:a component substrate;a power semiconductor device coupled to said component substrate;a diode coupled to said power semiconductor device through said component substrate;at least one first peripheral contact and at least one second peripheral contact situated on said component substrate, said power semiconductor device situated between said at least one first peripheral contact and said at least one second peripheral contact;said at least one first peripheral contact and said at least one second peripheral contact being configured for surface mounting.22. The power component of claim 21 , wherein said at least one first peripheral contact is electrically coupled to said power semiconductor device.23. The power component of claim 21 , wherein said at least one second peripheral contact is electrically coupled to said power semiconductor device.24. The power component of claim 21 , wherein said at least one first peripheral contact is electrically floating.25. The power component of claim 21 , wherein said at least one second peripheral contact is electrically floating.26. The power component of claim 21 , wherein said component substrate comprises a dielectric ...

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Номер записи: 62
11-07-2019 дата публикации

Semiconductor device

Номер: US20190214382A1
Автор: Kazuhito Nakai, Shigeki Koya, Takayuki Tsutsui, Yusuke Tanaka
Принадлежит: Murata Manufacturing Co Ltd

A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.

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Номер записи: 63
10-08-2017 дата публикации

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Номер: US20170229448A1
Автор: Tanaka Hiroyuki
Принадлежит:

To provide a semiconductor device with a high degree of flatness, provided is a semiconductor device including a semiconductor substrate; an element insulating film that is formed on a front surface side of the semiconductor substrate and includes a groove; and a semiconductor element provided in the groove of the element insulating film. The semiconductor device further comprises a withstand voltage structure farther to the outside than the active region, the withstand voltage structure includes a field insulating film formed on the front surface of the semiconductor substrate, and film thickness of a region of the element insulating film where the groove is not provided is the same as film thickness of the field insulating film. 1. A semiconductor device comprising:a semiconductor substrate;an element insulating film that is formed on a front surface side of the semiconductor substrate and includes a groove; anda semiconductor element provided in the groove of the element insulating film.2. The semiconductor device according to claim 1 , whereinthe semiconductor substrate includes an active region,the semiconductor device further comprises a withstand voltage structure farther to the outside than the active region,the semiconductor element is provided in the active region,the withstand voltage structure includes a field insulating film formed on the front surface of the semiconductor substrate, andfilm thickness of a region of the element insulating film where the groove is not provided is the same as film thickness of the field insulating film.3. The semiconductor device according to claim 2 , whereinthe semiconductor substrate includes one or more recessed portions in the front surface, andat least a portion of the element insulating film is provided in a recessed portion among the one or more recessed portions.4. The semiconductor device according to claim 3 , whereinthe entire element insulating film is provided in the recessed portion among the one or more ...

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Номер записи: 64
09-07-2020 дата публикации

Common-emitter and common-base heterojunction bipolar transistor

Номер: US20200219994A1
Автор: Honggang Liu, Zhipeng Yuan
Принадлежит: Waython Intelligent Technologies Suzhou Co ltd

Provided is a common-emitter and common-base heterojunction bipolar transistor disposed on a packaging substrate with a heat sink, including a common-base heterojunction bipolar transistor having a first base, a first emitter and a first collector, a common-emitter heterojunction bipolar transistor having a second base, a second emitter and a second collector, a heat shunt bridge for connecting the first emitter with the second collector, a first pad for being connected with the first base and a first copper pillar, a second pad for being connected with the first collector and a second copper pillar, a third pad for being connected with the second base and a third copper pillar, and a fourth copper pillar disposed above the second emitter; the common-emitter and common-base heterojunction bipolar transistor is flip-chip mounted on the packaging substrate, and the fourth copper pillar is soldered on the heat sink.

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Номер записи: 65
16-08-2018 дата публикации

Device and method for on-chip mechanical stress sensing

Номер: US20180231424A1
Автор: Baher Haroun, Ralf Peter Brederlow, Umidjon Nurmetov
Принадлежит: TEXAS INSTRUMENTS DEUTSCHLAND GMBH, Texas Instruments Inc

An integrated circuit (IC) chip includes a substrate of a piezo-electric material having a first resistivity coefficient associated with a first direction that is longitudinal to a first crystal axis and a second resistivity coefficient associated with a second direction that is transverse to the first crystal axis. The first and second resistivity coefficients have opposite signs. The IC chip also includes a first stress sensing element formed in the substrate and coupled to pass a first current therethrough. The first stress sensing element includes a first resistor aligned such that the major direction of current flow through the first resistor is in the first direction and a second resistor coupled in series with the first resistor and aligned such that the major direction of current flow through the second resistor is in the second direction. A ratio of the resistance of the second resistor to the resistance of the first resistor is equal to a value α, where α is equal to the ratio of the first resistivity coefficient to the second resistivity coefficient.

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Номер записи: 66
18-08-2016 дата публикации

Sensor Device

Номер: US20160241014A1
Автор: Hiroshi Nakano, Masahiro Matsumoto, Satoshi Asano, Shinobu Tashiro
Принадлежит: HITACHI AUTOMOTIVE SYSTEMS LTD

Provided is a sensor device that suppresses a malfunction caused by a negative surge or a voltage drop. A sensor device includes a sensor element having an electrical characteristic varying according to a physical amount, a signal processing circuit configured to process an output signal of the sensor element, a transistor element interposed between a power source terminal and the signal processing circuit, a resistive element configured to connect a drain and a gate of the transistor element, or a collector and a base of the transistor element, and an element having threshold voltage for connecting the gate or the base of the transistor element to a GND. The element regulates current flowing from the resistive element in a direction of the GND, in a case in which supply voltage to the signal processing circuit falls below the threshold voltage.

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Номер записи: 67
13-11-2014 дата публикации

JUNCTION-ISOLATED BLOCKING VOLTAGE STRUCTURES WITH INTEGRATED PROTECTION STRUCTURES

Номер: US20140332843A1
Автор: Clarke David J., Cosgrave Gavin Patrick, Heffernan Kieran K., Heffernan Stephen Denis, Luo Juan, Moane Brian B., Murnane Seamus, Salcedo Javier Alejandro, Twomey John
Принадлежит:

Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well. 1. (canceled)2. An apparatus comprising:a blocking voltage structure comprising:a first terminal;a second terminal, wherein the blocking voltage structure is configured to provide voltage blocking between the second terminal and the first terminal;a third terminal; and a silicon-controlled rectifier electrically connected between the first terminal and the second terminal, wherein the silicon-controlled rectifier is configured to protect the blocking voltage structure from overstress when a voltage of the second terminal increases relative to a voltage of the first terminal; and', 'a bidirectional silicon-controlled rectifier electrically connected between the third terminal and the second terminal, wherein the bidirectional silicon-controlled rectifier is configured to protect the blocking voltage structure from overstress when a voltage of the third terminal increases relative to the voltage of the second terminal, and wherein the bidirectional silicon-controlled rectifier is further configured to protect the blocking ...

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Номер записи: 68
24-08-2017 дата публикации

ELECTROSTATIC DISCHARGE PROTECTION DEVICE

Номер: US20170243864A1
Автор: Sorgeloos Bart, Van Camp Benjamin, Van Wijmeersch Sven, Vanhouteghem Wim
Принадлежит: Sofics BVBA

An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP. 1. An electrostatic discharge (ESD) protection device coupled between a first node and a second node , the ESD protection device comprising:a first lowly doped region of a P dopant type;a second lowly doped region of a N dopant type formed within the first lowly doped region;a third lowly doped region of a P dopant type formed within the second lowly doped region;a fourth region including a first highly doped region of the N dopant type, wherein the fourth region is formed directly within the third lowly doped region, the first highly doped region is coupled to the first node; anda fifth region including a second highly doped region of the P dopant type, wherein the fifth region is formed directly within the first lowly doped region, the second highly doped region is coupled to the second node;wherein a voltage at the first highly doped region is higher than a voltage at the second highly doped region, and further wherein a junction between the fourth region and the third lowly doped region is configured to enter into reverse breakdown in response to an ESD event, and a junction between the second lowly doped region and the first lowly doped region is configured to enter into a reverse breakdown in response to the ESD event, such that the ESD protection device is configured to sink current from the first node to the second node in response to an ESD event.2. The ESD protection device of claim 1 , ...

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Номер записи: 69
24-08-2017 дата публикации

Electrostatic protection circuit, semiconductor integrated circuit device, and electronic device

Номер: US20170244244A1
Автор: Masuhide Ikeda
Принадлежит: Seiko Epson Corp

This electrostatic protection circuit enables a high hold voltage to be set, and acts to accurately prevent breakdown of a protected circuit immediately after power on, and to prevent breakdown or deterioration of a protection device during prolonged normal operation, without connecting a resistance element in parallel to a plurality of circuit blocks connected in series. This electrostatic protection circuit is provided with a plurality of circuit blocks connected in series between a first node and a second node, at least one circuit block out of the plurality of circuit blocks including a thyristor having an anode connected to one end of the at least one circuit block and a cathode connected to the other end of the at least one circuit block. When the potential of the first node is higher than the potential of the second node during normal operation, the voltage between both ends of the other circuit blocks out of the plurality of circuit blocks is smaller than the voltage between the anode and the cathode of the thyristor.

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Номер записи: 70
31-08-2017 дата публикации

FIRE DETECTING DEVICE INCLUDING METAL-INSULATOR TRANSITION (MIT) DEVICE MOLDED BY CLEAR COMPOUND EPOXY

Номер: US20170249818A1
Автор: Kim Bongjun, Kim Hyun-Tak, Park Jong Chan
Принадлежит: Electronics and Telecommunications Research Institute

The inventive concept provides MIT devices molded by clear compound epoxy and fire detecting devices including the MIT device. The fire detecting device is supplied with a power source from a power control device. The fire detecting device includes a MIT device including a MIT chip molded by a clear compound epoxy, a diode bridge circuit supplied with the power source from the power control device for providing a non-polar power source, a notice circuit supplied with the non-polar power source from the diode bridge circuit for warning of a fire alarm in response to a detecting signal from the MIT device, and a stabilization circuit for maintaining the detecting signal for a certain period. 1. A fire detecting device supplied with a power source from a power control device , comprising:a MIT device including a MIT chip molded by a clear compound epoxy;a diode bridge circuit supplied with the power source from the power control device, the diode bridge circuit for providing a non-polar power source;a notice circuit supplied with the non-polar power source from the diode bridge circuit, the notice circuit for warning of a fire alarm in response to a detecting signal from the MIT device; anda stabilization circuit for maintaining the detecting signal for a certain period.2. The fire detecting device of claim 1 , wherein the diode bridge circuit includes an external electrostatic discharge (ESD) interruption device.3. The fire detecting device of claim 2 , wherein the ESD interruption device is realized by a zener diode.4. The fire detecting device of claim 1 , wherein the notice circuit includes a light emitting device warning of the fire alarm by light.5. The fire detecting device of claim 1 , wherein the stabilization circuit includes a PNP transistor and a NPN transistor;wherein an emitter of the PNP transistor is connected to a first terminal of the MIT device, a collector of the PNP transistor is connected to a second terminal of the MIT device, and a base of the ...

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Номер записи: 71
20-11-2014 дата публикации

Module and Assembly with Dual DC-Links for Three-Level NPC Applications

Номер: US20140342509A1
Автор: Laschek-Enders Andreas
Принадлежит:

A power semiconductor module has four power terminals. An IGBT has a collector connected to the first power terminal and an emitter coupled to the third power terminal. An anti-parallel diode is coupled in parallel with the IGBT. A DC-link is connected between the second and fourth power terminals. The DC-link may involve two diodes and two IGBTs, where the IGBTs are connected in a common collector configuration. The first and second power terminals are disposed in a first line along one side of the module, and the third and fourth power terminals are disposed in a second line along the opposite side of the module. Two identical instances of the module can be interconnected together to form a three-level NPC phase leg having low stray inductances, where the phase leg has two parallel DC-links. 115-. (canceled)16. A method of manufacture , comprising:coupling a collector of a first Insulated Gate Bipolar Transistor (IGBT) to a first power terminal;coupling an emitter of the first IGBT to a third power terminal;coupling an anode of a diode to the emitter of the first IGBT;coupling a cathode of the diode to the collector of the first IGBT;providing a DC-link between a second power terminal and a fourth power terminal, wherein the DC-link comprises a pair of IGBTs coupled together in a common collector configuration; andencapsulating the first IGBT, the diode, and the DC-link in a first power semiconductor module package, wherein the first, second, third and fourth power terminals are terminals of the first power semiconductor module package.17. The method of claim 16 , wherein each of the first claim 16 , second claim 16 , third and fourth power terminals has a fastening hole.18. The method of claim 17 , wherein the first and second power terminals are disposed along a first line claim 17 , wherein the third and fourth power terminals are disposed along a second line claim 17 , and wherein the first and second lines extend parallel to one another.19. The method of ...

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Номер записи: 72
08-09-2016 дата публикации

MAGNETIC MULTILAYER STRUCTURE

Номер: US20160260708A1
Автор: "OSullivan Eugene J.", Herget Philipp, Romankiw Lubomyr T., Wang Naigang, Webb Bucknell C.
Принадлежит:

A mechanism is provided for an integrated laminated magnetic device. A substrate and a multilayer stack structure form the device. The multilayer stack structure includes alternating magnetic layers and diode structures formed on the substrate. Each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by a diode structure.

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Номер записи: 73
15-09-2016 дата публикации

ELECTROSTATIC DISCHARGE PROTECTION DEVICE

Номер: US20160268250A1
Автор: Sorgeloos Bart, Van Camp Benjamin, Van Wijmeersch Sven, Vanhouteghem Wim
Принадлежит: Sofics BVBA

An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP. 1. An electrostatic discharge (ESD) protection device coupled between a first node and a second node , the ESD protection device comprising:a first region that is lowly doped with a P-type dopant;a second region that is lowly doped with an N-type dopant and formed directly within the first region;a third region that is highly doped with the P-type dopant and formed directly within the second region, wherein the third region is coupled to the first node;a fourth region that is lowly doped with the N-type dopant and formed directly within the first region; anda fifth region that is doped with the P-type dopant and formed directly within the fourth region, wherein the fifth region is coupled to the second node;wherein a voltage at the third region is higher than a voltage at the fifth region, and further wherein a junction between the second region and the first region is configured to enter into reverse breakdown in response to an ESD event, and a junction between the fourth region and the fifth region is configured to enter into a reverse breakdown in response to the ESD event, such that the ESD protection device is configured to sink current from the first node to the second node in response to the ESD event.2. The ESD protection device of claim 1 , wherein the fifth region is highly doped with the P-type dopant and the fifth region is directly connected to the second node.3. The ESD protection ...

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Номер записи: 74
15-08-2019 дата публикации

DRIVER FOR DRIVING A CAPACITIVE LOAD

Номер: US20190252373A1
Автор: Darwhekar Yogesh, Kumar Pranav
Принадлежит:

A circuit includes a first bipolar junction transistor (BJT) including a first base, a first collector, and a first emitter, the first collector connected to a first supply voltage node and a second BJT including a second base, a second collector, and a second emitter, the second collector connected to the first emitter at an output node. The circuit also includes a capacitor including a first capacitor terminal and a second capacitor terminal, the first capacitor terminal connected to the second emitter of the second BJT and the second capacitor terminal connected to a second supply voltage node. A current source device is also included that is connected in parallel with the capacitor. 1. A circuit , comprising:a first bipolar junction transistor (BJT) including a first base, a first collector, and a first emitter, the first collector connected to a first supply voltage node;a second BJT including a second base, a second collector, and a second emitter, the second collector connected to the first emitter at an output node;a capacitor including a first capacitor terminal and a second capacitor terminal, the first capacitor terminal connected to the second emitter of the second BJT and the second capacitor terminal connected to a second supply voltage node; anda current source device connected in parallel with the capacitor.2. The circuit of claim 1 , wherein the first BJT is an NPN BJT.3. The circuit of claim 1 , further comprising a control circuit coupled to receive a first periodic control signal to be provided to the first base and claim 1 , based on the received first periodic control signal claim 1 , to generate a second periodic control signal to be provided to the second base claim 1 , wherein the first and second periodic control signals are of the same frequency but are complementary to each other.4. The circuit of claim 3 , wherein the current source device is to produce a current that is of a magnitude which claim 3 , when the second BJT is off claim 3 , ...

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Номер записи: 75
29-09-2016 дата публикации

ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT

Номер: US20160285262A1
Автор: Chao Chuan-Chen
Принадлежит:

An ESD protection circuit includes an input port, a resistor, a BJT, and a diode. The BJT has an emitter, a base, and a collector. The emitter of the BJT is coupled to the input port. The base of the BJT is coupled through the resistor to the input port. The diode has a first terminal and a second terminal. The first terminal of the diode is the collector of the BJT. The second terminal of the diode is coupled to a supply voltage. 1. An ESD protection circuit , comprising:an input port;a resistor;a BJT, having an emitter, a base, and a collector, wherein the emitter of the BJT is coupled to the input port, and the base of the BJT is coupled through the resistor to the input port; anda diode, having a first terminal and a second terminal, wherein the first terminal of the diode is the collector of the BJT, and the second terminal of the diode is coupled to a supply voltage.2. The ESD protection circuit as claimed in claim 1 , wherein the emitter of the BJT is formed by a first type-I semiconductor claim 1 , the base of the BJT is formed by a first type-II semiconductor claim 1 , the collector of the BJT is formed by a second type-I semiconductor claim 1 , and the diode is formed by the second type-I semiconductor and a second type-II semiconductor.3. The ESD protection circuit as claimed in claim 2 , wherein:the first type-I semiconductor is a high-doped P-type semiconductor, the first type-II semiconductor is an N-type semiconductor, the second type-I semiconductor is a low-doped P-type semiconductor, and the second type-II semiconductor is an N-type semiconductor; orthe first type-I semiconductor is a high-doped N-type semiconductor, the first type-II semiconductor is a P-type semiconductor, the second type-I semiconductor is a low-doped N-type semiconductor, and the second type-II semiconductor is a P-type semiconductor.4. The ESD protection circuit as claimed in claim 1 , wherein the BJT is a HBT.5. The ESD protection circuit as claimed in claim 1 , wherein the ...

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Номер записи: 76
29-08-2019 дата публикации

THREE-LEVEL I-TYPE INVERTER AND SEMICONDUCTOR MODULE

Номер: US20190267912A1
Автор: ISHINO Masaaki, NISHIDA Nobuya
Принадлежит: Mitsubishi Electric Corporation

A three-level I-type inverter includes first to fourth switching devices between first and second potentials, first to fourth diodes, and fifth and sixth diodes. The first to fourth diodes are respectively connected to the first to fourth switching devices in anti-parallel. Between a connection node of the first and second switching devices and a connection node of the third and fourth switching devices, the fifth and sixth diodes are connected in series and in anti-parallel with series connection of the second and third switching devices. A connection node of the fifth and sixth diodes is connected to an input node having intermediate potential. A connection node of the second and third switching devices is connected to an output node. The second switching device and diode are formed of a first reverse conducting IGBT. The third switching device and diode are formed of a second reverse conducting IGBT. 1. A three-level I-type inverter , comprising:between a first main power-supply node supplied with first potential and a second main power-supply node supplied with second potential that is lower than the first potential, first, second, third, and fourth switching devices that are connected in series in mentioned order from the first potential side;first, second, third, and fourth diodes that are respectively connected to the first, second, third, and fourth switching devices in anti-parallel; andbetween a connection node of the first and second switching devices and a connection node of the third and fourth switching devices, fifth and sixth diodes that are connected in series and in anti-parallel with the series connection of the second and third switching devices, whereina connection node of the fifth and sixth diodes is connected to an input node that is supplied with intermediate potential between the first potential and the second potential,a connection node of the second and third switching devices is connected to an output node,the second switching device and ...

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Номер записи: 77
09-12-2021 дата публикации

POWER GENERATION ELEMENT

Номер: US20210384328A1
Автор: Kimura Shigeya, Miyazaki Hisao, YOSHIDA Hisashi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a power generation element includes a first conductive layer, a second conductive layer, and a first member. The first member is provided between the first conductive layer and the second conductive layer. The first member includes a first semiconductor having polarity. A gap is between the second conductive layer and the first member. A <000-1> direction of the first semiconductor is oblique to a first direction from the first conductive layer toward the second conductive layer. 1. A power generation element , comprising:a first conductive layer;a second conductive layer; anda first member provided between the first conductive layer and the second conductive layer, the first member including a first semiconductor having polarity,a gap being between the second conductive layer and the first member,a <000-1> direction of the first semiconductor being oblique to a first direction from the first conductive layer toward the second conductive layer.2. The element according to claim 1 , wherein{'sub': x1', '1-x1, 'the first semiconductor includes AlGaN (0≤x1≤1).'}3. The element according to claim 1 , whereinthe first semiconductor is of an n-type.4. The element according to claim 1 , whereinan angle between the first direction and the <000-1> direction of the first semiconductor is not less than 4° and not more than 32°.5. The element according to claim 1 , wherein a first surface; and', 'a second surface between the first surface and the first conductive layer, and, 'the first member includesthe first surface includes a first region along a (000-1) plane of the first semiconductor.6. The element according to claim 5 , whereinthe first surface further includes a second region,a direction from the first region toward the second region is along a second direction crossing the first direction, andthe second region crosses the first region.7. The element according to claim 6 , whereinan angle between the first region and the second region is 90°.8 ...

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Номер записи: 78
05-10-2017 дата публикации

Gate Driver That Drives With A Sequence Of Gate Resistances

Номер: US20170288661A1
Автор: Laschek-Enders Andreas
Принадлежит:

A gate driver integrated circuit for driving a gate of an IGBT or MOSFET receives an input signal. In response to a rising edge of the input signal, the integrated circuit causes the gate to be driven in a first sequence of time periods. In each period, the gate is driven high (pulled up) via a corresponding one of a plurality of different effective gate resistances. In response to a falling edge of the input signal, the integrated circuit causes the gate to be driven in a second sequence of time periods. In each period, the gate is driven low (pulled down) via a corresponding one of the different effective gate resistances. In one example, the duration of each time period is set by a corresponding external passive circuit component. The different effective gate resistances are set by external gate resistors disposed between the integrated circuit and the gate. 1. (canceled)2. An integrated circuit comprising:a first power transistor gate driver having an output lead;a second power transistor gate driver having an output lead;a third power transistor gate driver having an output lead;a signal node, wherein a gate driver control signal is present on the signal node, wherein the gate driver control signal has a rising edge that is followed by a falling edge; and a first delay line having a plurality of nodes;', 'a second delay line having a plurality of nodes; and', 'an amount of digital logic coupled to receive signals from the plurality of nodes of the first delay line and coupled to receive signals from the plurality of nodes of the second delay line, wherein the amount of digital logic supplies a first enable signal to the first power transistor gate driver, wherein the amount of digital logic supplies a second enable signal to the second power transistor gate driver, and wherein the amount of digital logic supplies a third enable signal to the third power transistor gate driver., 'a driver control circuit that receives the gate driver control signal and in ...

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Номер записи: 79
04-10-2018 дата публикации

Radio Frequency Resistor Element

Номер: US20180286941A1
Автор: Bartels Martin, Cattaneo Andrea, FEICK Henning, Kuehn Christian, Steltenpohl Anton, Taddiken Hans
Принадлежит:

A radio frequency resistor element comprises a resistive polysilicon trace, an isolation component and a semiconductor substrate. The resistive polysilicon trace is located above the isolation component. The isolation component is laterally at least partially surrounded by a modified semiconductor region located above the semiconductor substrate and having a higher charge carrier recombination rate than the semiconductor substrate. 1. A radio frequency resistor element , comprising:a resistive polysilicon trace;an isolation component; and wherein the resistive polysilicon trace is located above the isolation component,', 'wherein the isolation component is laterally at least partially surrounded by a modified semiconductor region,', 'wherein the modified semiconductor region is located above the semiconductor substrate, and', 'wherein the modified semiconductor region has a higher charge carrier recombination rate than the semiconductor substrate., 'a semiconductor substrate,'}2. The radio frequency resistor element of claim 1 , wherein the modified semiconductor region laterally surrounds at least a part of an axial extension of the isolation component.3. The radio frequency resistor element of claim 1 , wherein the modified semiconductor region comprises an active silicon that comprises a damage implantation.4. The radio frequency resistor element of claim 1 , wherein the modified semiconductor region comprises an argon implantation.5. The radio frequency resistor element of claim 1 , wherein the modified semiconductor region comprises a germanium implantation.6. The radio frequency resistor element of claim 1 , wherein the modified semiconductor region comprises damaged silicon.7. The radio frequency resistor element of claim 1 , wherein the modified semiconductor region comprises polysilicon.8. The radio frequency resistor element of claim 1 , wherein the modified semiconductor region comprises strained silicon nitride.9. The radio frequency resistor element of ...

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Номер записи: 80
29-10-2015 дата публикации

A SEMICONDUCTOR DEVICE COMPRISING AN ESD PROTECTION DEVICE, AN ESD PROTECTION CIRCUITRY, AN INTEGRATED CIRCUIT AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Номер: US20150311193A1
Автор: BESSE PATRICE, LAINE Jean Philippe
Принадлежит: Freescale Semiconductor, Inc.

A semiconductor device is provided which comprises an ESD protection device. The ESD protection device is being formed by one or more pnp transistors which are present in the structure of the semiconductor device. The semiconductor device comprises two portions, of an isolated p-doped region which are separated by an N-doped region. Two p-doped regions are provided within the two portions. The p-dopant concentration of the two-doped region is higher than the p-dopant concentration of the isolated p-doped region. A first electrical contact is connected only via a highly doped p-contact region to the first p-doped region and a second electrical contact is connected only via another highly doped p-contact region to the second p-doped region. 1. A semiconductor device comprising an ESD protection device for protecting an integrated circuit on the semiconductor device against ESD event received by the integrated circuit , the ESD protection device comprisinga semiconductor substrate, the semiconductor substrate having a first side, the semiconductor substrate having an N-buried region extending in a lateral direction in the interior of the semiconductor substrate,a p-doped isolated portion of the semiconductor substrate being isolated from a remaining part of the semiconductor substrate by an isolation structure, the isolation structure comprising the N-buried region,an N-doped region being arranged in the p-doped isolated portion and extending from the first side towards the N-buried region, the N-doped region subdividing the isolated portion in a first portion and a second portion,a first p-doped region and a second p-doped region extending from the first side into, respectively, the first portion and the second portion, the p-dopant concentration of the first p-doped region and of the second p-doped region being higher than the p-dopant concentration of the first portion and the second portion,a first contact region and a second contact region extending from the first ...

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Номер записи: 81
29-10-2015 дата публикации

Quantum Tunneling Devices and Circuits with Lattice-Mismatched Semiconductor Structures

Номер: US20150311911A1
Автор: Cheng Zhiyuan, Sheen Calvin
Принадлежит:

Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials. 1. A device comprising: a first voltage divider, an input node of the first voltage divider being electrically coupled to a circuit analog input node,', 'a first multi-state resonant tunneling bipolar transistor having a first base, a first collector, and a first emitter, a voltage-divided node of the first voltage divider being electrically coupled to the first base, the first collector being a first output and being electrically coupled to a first node of a first impedance element, a second node of the first impedance element being electrically coupled to a first power node, the first emitter being electrically coupled to a second power node,', 'a second voltage divider, an input node of the second voltage divider being electrically coupled to the circuit analog input node, and', 'a second multi-state resonant tunneling bipolar transistor having a second base, a second collector, and a second emitter, a voltage-divided node of the second voltage divider being electrically coupled to the second base, the second collector being a second output and being electrically coupled to a first node of a second impedance element, a second node of the second impedance element being electrically coupled to the first power node, the second emitter being electrically coupled to the second power node., 'an analog-to-digital converter comprising2. The device of claim 1 , wherein the first power node is a power supply node claim 1 , and the second power node is a ground node.3. The device of claim 1 , wherein:the first voltage divider comprises a first resistor and a second resistor, a first node of the first resistor being the input node of the first voltage divider, a second node of the first resistor being the voltage-divided node of the first voltage divider and being electrically ...

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Номер записи: 82
26-09-2019 дата публикации

ADJUSTABLE MULTI-TURN MAGNETIC COUPLING DEVICE

Номер: US20190296101A1
Автор: CHAN Hao-Chieh, Li Chao Chieh
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

According to some embodiments, an integrated circuit device is disclosed. The integrated circuit device include at least one inductor having at least one turn, a magnetic coupling ring positioned adjacent to the at least one inductor, the magnetic coupling ring comprising at least two magnetic coupling turns, the at least two magnetic coupling turns are disposed adjacent to the at least one turn to enable magnetic coupling between the at least two magnetic coupling turns and the at least one turn The integrated circuit device also includes a power electrode and a ground electrode, wherein the power electrode and the ground electrode are coupled to the at least one inductor and the magnetic coupling ring to provide a first current in the at least one inductor having a direction opposite to a second current in the magnetic coupling ring to cancel at least a portion of a magnetic field generated by the at least one inductor. 1. An integrated circuit device , comprising:a transformer comprising a first inductor and a second inductor, wherein the first and second inductors each comprises at least one turn; anda magnetic coupling ring comprising at least two magnetic coupling turns,wherein the at least two magnetic coupling turns are each disposed to be either surrounding or surrounded by the transformer in a top view to enable magnetic coupling between the magnetic coupling ring and the transformer, wherein the at least two magnetic coupling turns are in at least two different levels with respect to one another2. The integrated circuit device of claim 1 , wherein all of the at least two magnetic coupling turns are disposed surrounding the transformer.3. The integrated circuit device of claim 1 , wherein all of the at least two magnetic coupling turns are disposed surrounded by the transformer.4. The integrated circuit device of claim 1 , wherein at least one of the at least two magnetic coupling turns is disposed surrounding the transformer claim 1 , and at least one of ...

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Номер записи: 83
17-09-2020 дата публикации

Electronic Device Including a Semiconductor Body or an Isolation Structure Within a Trench

Номер: US20200295126A1
Автор: Agam Moshe, Janssens Johan Camiel Julia, Pjencak Jaroslav
Принадлежит: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

An electronic device can include a substrate defining a trench. In an embodiment, a semiconductor body can be within the trench, wherein the semiconductor body has a resistivity of at least 0.05 ohm-cm and is electrically isolated from the substrate. In an embodiment, an electronic component can be within the semiconductor body. The electronic component can be a resistor or a diode. In a particular embodiment, the semiconductor body has an upper surface, the electronic component is within and along an upper surface and spaced apart from a bottom of the semiconductor body. In a further embodiment, the electronic device can further include a first electronic component within an active region of the substrate, an isolation structure within the trench, and a second electronic component within the isolation structure.

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Номер записи: 84
03-10-2019 дата публикации

CO-PLACEMENT OF RESISTOR AND OTHER DEVICES TO IMPROVE AREA & PERFORMANCE

Номер: US20190304905A1
Автор: Loke Alvin Leng Sun, Schneider Jacob, Wee Tin Tin
Принадлежит:

Co-placement of resistor and other devices to improve area and performance is disclosed. In one implementation, a semiconductor circuit includes a resistor residing on a back end of line (BEOL) resistor layer, a plurality of interlevel metal vias coupling the BEOL resistor layer to one or more metal layers underneath the BEOL resistor layer, and a diode residing on a silicon substrate underneath the one or more metal layers, wherein a planar surface of the diode and a planar surface of the resistor at least partially overlap with each other, and the diode and the resistor are coupled to each other through the plurality of interlevel metal vias. 1. A semiconductor circuit , comprising:a resistor residing on a back end of line (BEOL) resistor layer;a plurality of multi-level metal wires and interlevel metal vias coupling the BEOL resistor layer to one or more metal layers underneath the BEOL resistor layer; anda diode residing on a silicon substrate underneath the one or more metal layers, wherein a planar surface of the diode and a planar surface of the resistor at least partially overlap with each other, and the diode and the resistor are coupled to each other through the plurality of multi-level metal wires and interlevel metal vias.2. The semiconductor circuit of claim 1 , further comprising an output driver and an electrostatic discharge (ESD) protection circuit coupled to an output of the output driver claim 1 , wherein the diode is configured as part of the ESD protection circuit and the resistor is configured as part of the output driver.3. The semiconductor circuit of claim 1 , further comprising:routing to couple the resistor to the diode, wherein the routing passes through the plurality of multi-level metal wires and interlevel metal vias.4. The semiconductor circuit of claim 1 , wherein the resistor and the diode are configured as part of a bandgap reference circuit.5. The semiconductor circuit of claim 1 , further comprising a first BEOL metal layer and a ...

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Номер записи: 85
02-11-2017 дата публикации

APPARATUSES FOR COMMUNICATION SYSTEMS TRANSCEIVER INTERFACES

Номер: US20170317070A1
Автор: Clarke David J., Salcedo Javier Alejandro
Принадлежит:

An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a semiconductor substrate having formed therein a bidirectional semiconductor rectifier (SCR) having a cathode/anode electrically connected to a first terminal and an anode/cathode electrically connected to a second terminal. The integrated circuit device additionally includes a plurality of metallization levels formed above the semiconductor substrate. The integrated circuit device further includes a triggering device formed in the semiconductor substrate on a first side and adjacent to the bidirectional SCR. The triggering device includes one or more of a bipolar junction transistor (BJT) or an avalanche PN diode, where a first device terminal of the triggering device is commonly connected to the T with the K/A, and where a second device terminal of the triggering device is electrically connected to a central region of the bidirectional SCR through one or more of the metallization levels. 1. An integrated circuit device , comprising:a semiconductor substrate having formed therein a bidirectional semiconductor-controlled rectifier (SCR) having a cathode/anode (K/A) electrically connected to a first terminal (T1) and an anode/cathode (A/K) electrically connected to a second terminal (T2), wherein the bidirectional SCR comprises a first bipolar transistor, a second bipolar transistor, and a bidirectional bipolar transistor comprising a base coupled to a central region of the bidirectional SCR;a plurality of metallization levels formed outside the semiconductor substrate; anda triggering device formed in the semiconductor substrate on a first side and adjacent to the bidirectional SCR and comprising one or more of a bipolar junction transistor (BJT) or an avalanche PN diode, wherein a first device terminal of the triggering device is commonly connected to the T1 with the K/A, and wherein a second device terminal of the triggering ...

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Номер записи: 86
09-11-2017 дата публикации

DUAL-SIDED SILICON INTEGRATED PASSIVE DEVICES

Номер: US20170323883A1
Автор: Hu Kunzhong, PANG Mengzhi, Ramachandran Vidhya, Zhai Jun, Zhong Chonghua
Принадлежит:

In some embodiments, a system may include an integrated circuit. The integrated circuit may include a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface. The first set of electrical conductors may function to electrically connect the integrated circuit to a circuit board. The integrated circuit may include a semiconductor die coupled to the second surface of the substrate using a second set of electrical conductors. The integrated circuit may include a passive device dimensioned to be integrated with the integrated circuit. The passive device may be positioned between the second surface and at least one of the first set of electrical conductors. The die may be electrically connected to a second side of the passive device. A first side of the passive device may be available to be electrically connected to a second device. 1. An integrated circuit , comprising:a substrate including a first surface, a second surface substantially opposite of the first surface, and a first set of electrical conductors coupled to the first surface configured to electrically connect the integrated circuit to a circuit board;a semiconductor die coupled to the second surface of the first substrate using a second set of electrical conductors; anda passive device integrated in the integrated circuit, wherein the passive device is positioned between the first surface and the second surface of the substrate.2. The integrated circuit of claim 1 , wherein the passive device is embedded in the substrate.3. The integrated circuit of claim 1 , wherein the passive device comprises at least a third electrical conductor positioned on a first side of the passive device claim 1 , wherein the passive device comprises at least a fourth electrical conductor positioned on a second side of the passive device claim 1 , and wherein the second side of the device is positioned opposite the first ...

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Номер записи: 87
26-11-2015 дата публикации

LATCH-UP ROBUST SCR-BASED DEVICES

Номер: US20150340481A1
Автор: LAI Da-Wei
Принадлежит:

An approach for providing a latch-up robust silicon control rectifier (SCR) is disclosed. Embodiments include providing a first N+ region and a first P+ region in a substrate for a SCR; providing first and second n-well regions in the substrate proximate the first N+ and P+ regions; providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region; and coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an I/O pad. 1. A device comprising:a first n-well region in a substrate for a silicon control rectifier (SCR);a first N+ region and a first P+ region in the substrate on a first side of the first n-well region;a second n-well on a second side of the first n-well region that is opposite the first side;a second N+ region in the first n-well region, and a second P+ region in the second n-well region, wherein the first N+ and P+ regions are coupled to a ground rail, the second N+ region is coupled to a power rail, the second P+ region is coupled to an I/O pad, and a holding voltage of the SCR that is greater than a maximum operating voltage of the SCR during a latch-up event is provided by turning on the power rail;a third P+ region between the second N+ and P+ regions;a resistor having first and second resistor terminals;a capacitor having first and second capacitor terminals; andthe third P+ region is coupled to the first resistor and capacitor terminals, the second resistor terminal is coupled to the ground rail, and the second capacitor terminal is coupled to the I/O pad.2. A device comprising:a first N+ region and a first P+ region in a substrate;first and second n-well regions in the substrate proximate the first N+ and P+ regions;a second N+ region in the first n-well region; anda second P+ region in the second n-well region, wherein the first N+ and P+ regions are coupled to a ground rail, the second N+ region is coupled to a power rail, and the second P ...

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Номер записи: 88
24-11-2016 дата публикации

ZENER TRIGGERED SILICON CONTROLLED RECTIFIER WITH SMALL SILICON AREA

Номер: US20160343701A1
Автор: CHENG Huijuan, LEI Wei, LI Hongwei, ZHONG Lei
Принадлежит:

A semiconductor device includes a P-type semiconductor substrate, an N-well and a P-well disposed adjacent to each other and extending along a first direction within the P-type semiconductor substrate, a first N+ doped region and a first P+ doped region extending along the first direction within the N-well and spaced away from each other along a second direction perpendicular to the first direction, a second N+ doped region and a second P+ doped region extending along the first direction within the P-well and spaced away from each other along the second direction, and a plurality of third N+ doped regions and a plurality of P+ doped regions alternatively disposed in a junction region formed between the N-well and P-well the third N+ doped regions. The third N+ doped regions and the third P+ doped regions form a Zener diode. 1. A semiconductor device comprising:a P-type semiconductor substrate;an N-well and a P-well disposed adjacent to each other and extending along a first direction within the P-type semiconductor substrate;a first N+ doped region and a first P+ doped region extending along the first direction within the N-well and spaced away from each other along a second direction perpendicular to the first direction;a second N+ doped region and a second P+ doped region extending along the first direction within the P-well and spaced away from each other along the second direction; anda plurality of third N+ doped regions and a plurality of P+ doped regions alternatively disposed in a junction region formed between the N-well and P-well and extending along the first direction, the third N+ doped regions and the third P+ doped regions being separated from the adjacent first P+ doped region and second N+ doped region,wherein the third N+ doped regions and the third P+ doped regions form a Zener diode.2. The semiconductor device of claim 1 , wherein the first N+ doped region and the first P+ doped region are connected to each other to form an anode of a silicon ...

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Номер записи: 89
08-10-2020 дата публикации

POWER AMPLIFIER APPARATUS

Номер: US20200321927A1
Автор: ARAYASHIKI Satoshi, HARIMA Fumio, ITOU Makoto, Tanaka Satoshi, TERASHIMA Toshikazu, WATANABE Kazuo, Yoshida Chikara
Принадлежит:

A power amplifier apparatus includes a semiconductor substrate, a plurality of first transistors on the semiconductor substrate, a plurality of second transistors, at least one collector terminal electrically connected to collectors of the plurality of first transistors, a first inductor having a first end electrically connected to the collector terminal and a second end electrically connected to a power supply potential, at least one emitter terminal electrically connected to emitters of the plurality of second transistors and adjacent to the collector terminal in a second direction, a second inductor having a first end electrically connected to the emitter terminal and a second end electrically connected to a reference potential, and at least one capacitor having a first end electrically connected to the collectors of the plurality of first transistors and a second end electrically connected to the emitters of the plurality of second transistors. 1. A power amplifier apparatus comprising:a semiconductor substrate;a plurality of first transistors along a first direction on the semiconductor substrate;a plurality of second transistors along the first direction on the semiconductor substrate, and separated from the plurality of first transistors in a second direction perpendicular to the first direction;at least one collector terminal electrically connected to collectors of the plurality of first transistors;a first inductor having a first end electrically connected to the at least one collector terminal and a second end electrically connected to a power supply potential;at least one emitter terminal electrically connected to emitters of the plurality of second transistors, the at least one emitter terminal being adjacent to a corresponding one of the at least one collector terminals in the second direction on the semiconductor substrate;a second inductor having a first end electrically connected to the at least one emitter terminal and a second end electrically ...

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Номер записи: 90
30-11-2017 дата публикации

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR AND SEMICONDUCTOR MODULE

Номер: US20170345817A1
Автор: MAMETUKA Masataka, NISHIMURA Kazuhiro, Ueno Makoto
Принадлежит: Mitsubishi Electric Corporation

A semiconductor device of the present invention achieves improved avoidance of a parasitic operation in a circuit region while achieving miniaturization of the semiconductor device and a reduction in the amount of time for manufacturing the semiconductor device. The semiconductor device according to the present invention includes an IGBT disposed on a first main surface of a semiconductor substrate provided with a drift layer of a first conductivity type; a thyristor disposed on the first main surface of the semiconductor substrate; a circuit region; a hole-current retrieval region separating the IGBT and the circuit region in a plan view; and a diffusion layer of a second conductivity type, the diffusion layer being disposed on a second main surface of the semiconductor substrate. The IGBT has an effective area equal to or less than an effective area of the thyristor in a plan view. 1. A semiconductor device comprising:an insulated-gate bipolar transistor disposed on a first main surface of a semiconductor substrate comprising a drift layer of a first conductivity type;a thyristor disposed on said first main surface of said semiconductor substrate;a circuit region disposed on said first main surface of said semiconductor substrate, said circuit region comprising a CMOS circuit element;a hole-current retrieval region disposed on said first main surface of said semiconductor substrate, said hole-current retrieval region separating said insulated-gate bipolar transistor and said circuit region in a plan view; anda diffusion layer of a second conductivity type, said diffusion layer being disposed on a second main surface of said semiconductor substrate, whereinsaid insulated-gate bipolar transistor has an effective area equal to or less than an effective area of said thyristor in a plan view.2. The semiconductor device according to claim 1 , wherein said diffusion layer is formed by doping said second main surface of said semiconductor substrate with a dopant claim 1 , ...

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Номер записи: 91
06-12-2018 дата публикации

E-FUSE CELLS AND METHODS FOR PROTECTING E-FUSES

Номер: US20180350796A1
Автор: LEE CHIEN-HSIN, LINEWIH Handoko
Принадлежит:

E-fuse cells and methods for protecting e-fuses are provided. An exemplary e-fuse cell includes an e-fuse having a first end coupled to a source node and a second end selectively coupled to a ground. Further, the exemplary e-fuse includes a selectively activated shunt path from the source node to the ground. Also, the exemplary e-fuse includes a device for activating the shunt path in response to an electrical overstress event. 1. An e-fuse cell comprising:an e-fuse having a first end coupled to a source node and a second end selectively coupled to a ground;a selectively activated shunt path from the source node to the ground; anda device for activating the shunt path in response to an electrical overstress event.2. The e-fuse cell of further comprising a transistor in the shunt path claim 1 , wherein the device for activating the shunt path in response to the electrical overstress event is coupled to the transistor.3. The e-fuse cell of further comprising an NMOS field effect transistor (NFET) in the shunt path claim 1 , wherein the device for activating the shunt path in response to the electrical overstress event is coupled to a gate of the NFET.4. The e-fuse cell of further comprising a transistor in the shunt path claim 1 , wherein the device for activating the shunt path in response to the electrical overstress event is a power clamp interconnected between the source node and the ground and having an output coupled to a gate of the transistor.5. The e-fuse cell of further comprising an NMOS field effect transistor (NFET) in the shunt path claim 1 , wherein the device for activating the shunt path in response to the electrical overstress event is a power clamp interconnected between the source node and the ground and having an output coupled to a gate of the NFET.6. The e-fuse cell of further comprising a bipolar junction transistor in the shunt path.7. The e-fuse cell of further comprising a PNP bipolar junction transistor in the shunt path and having an ...

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Номер записи: 92
21-12-2017 дата публикации

Transient Voltage Protection Circuits, Devices, and Methods

Номер: US20170366001A1
Автор: Cao Yiqun
Принадлежит:

A transient voltage protection circuit includes a first input/output pad, a second input/output pad, and a trigger circuit coupled between the first input/output pad and the second input/output pad. The trigger circuit includes a first trigger element which includes a first input/output node, a second input/output node, a third input/output node, and a first substrate diode coupled to the third input/output node of the first trigger element. The trigger circuit further includes a first resistor coupled between the first input/output node of the first trigger element and the second input/output node of the first trigger element. The trigger circuit further includes a second trigger element which includes a first input/output node, a second input/output node, a third input/output node, wherein the second input/output node of the first trigger element is coupled to the first input/output node of the second trigger element, and a second substrate diode coupled to the third input/output node of the second trigger element. The trigger circuit further includes a second resistor coupled between the first input/output node of the second trigger element and the second input/output node of the second trigger element. 1. A transient voltage protection circuit comprising:a first input/output pad;a second input/output pad; and [ a first input/output node,', 'a second input/output node,', 'a third input/output node, and', 'a first substrate diode coupled to the third input/output node of the first trigger element,, 'a first trigger element comprising'}, 'a first resistor coupled between the first input/output node of the first trigger element and the second input/output node of the first trigger element,', a first input/output node,', 'a second input/output node,', 'a third input/output node, wherein the second input/output node of the first trigger element is coupled to the first input/output node of the second trigger element, and', 'a second substrate diode coupled to the third ...

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Номер записи: 93
31-12-2015 дата публикации

SCRs with Checker Board Layouts

Номер: US20150380396A1
Автор: CHENG Shui-Ming, Lin Wun-Jie, SONG Ming-Hsiang, SU YU-TI, Yang Han-Jen
Принадлежит:

An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips. 1. An Electro-Static Discharge (ESD) protection circuit comprising:a first semiconductor strip in a first well on a substrate, the first semiconductor strip extending along a first row direction, the first semiconductor strip having a first p-doped portion and a first n-doped portion;a second semiconductor strip in a second well on the substrate, the first well and the second well being physically separated and having a same conductivity type, the first well and the second well being in a third well having a different conductivity type, the second semiconductor strip extending along a second row direction parallel to the first row direction, the second semiconductor strip having a second p-doped portion and a second n-doped portion, the first p-doped portion and the second n-doped portion being aligned along a first column direction, the first n-doped portion and the second p-doped portion being aligned along a second column direction parallel to the first column direction; anda conductor electrically connecting the first n-doped portion to the second p-doped portion.2. The ESD protection circuit of further comprising:a first gate stack on the first semiconductor strip and between first p-doped portion and the first n-doped portion; anda second gate stack on the first semiconductor ...

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Номер записи: 94
28-12-2017 дата публикации

ESD PROTECTION CIRCUIT, DIFFERENTIAL TRANSMISSION LINE, COMMON MODE FILTER CIRCUIT, ESD PROTECTION DEVICE, AND COMPOSITE DEVICE

Номер: US20170373492A1
Автор: UEKI Noriyuki
Принадлежит:

An ESD protection device includes a first terminal and a second terminal defining a first balanced port, a third terminal and a fourth terminal defining a second balanced port, and a ground terminal. A first coil and a third coil are provided between the first terminal and the third terminal to cancel an inductance component of a first ESD protection circuit. A second coil and a fourth coil are provided between the second terminal and the fourth terminal to cancel an inductance component of a second ESD protection circuit. 1. An ESD protection circuit comprising:a first terminal and a second terminal defining a first balanced port;a third terminal and a fourth terminal defining a second balanced port;a first ESD protection circuit that includes a first Zener diode and is connected between a ground and a first node between the first terminal and the third terminal;a second ESD protection circuit that includes a second Zener diode, is connected between the ground and a second node between the second terminal and the fourth terminal, and is symmetric with respect to the first ESD protection circuit;a first coil provided in series between the first terminal and the first node;a third coil that is cumulatively connected to the first coil and is provided in series between the third terminal and the first node;a second coil provided in series between the second terminal and the second node; anda fourth coil that is cumulatively connected to the second coil and is provided in series between the fourth terminal and the second node.2. The ESD protection circuit according to claim 1 , whereinthe first coil and the third coil are provided in a first region where coil openings of the first coil and the third coil at least partially overlap in plan view;the second coil and the fourth coil are provided in a second region where coil openings of the second coil and the fourth coil at least partially overlap in plan view; andthe first ESD protection circuit and the second ESD ...

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Номер записи: 95
28-12-2017 дата публикации

Gate Driver that Drives with a Sequence of Gate Resistances

Номер: US20170373682A1
Автор: Laschek-Enders Andreas
Принадлежит:

A gate driver integrated circuit for driving a gate of an IGBT or MOSFET receives an input signal. In response to a rising edge of the input signal, the integrated circuit causes the gate to be driven in a first sequence of time periods. In each period, the gate is driven high (pulled up) via a corresponding one of a plurality of different effective gate resistances. In response to a falling edge of the input signal, the integrated circuit causes the gate to be driven in a second sequence of time periods. In each period, the gate is driven low (pulled down) via a corresponding one of the different effective gate resistances. In one example, the duration of each time period is set by a corresponding external passive circuit component. The different effective gate resistances are set by external gate resistors disposed between the integrated circuit and the gate. 1. An integrated circuit comprising:a first power transistor gate driver having an output lead;a second power transistor gate driver having an output lead;a third power transistor gate driver having an output lead;a signal node, wherein a gate driver control signal is present on the signal node, wherein the gate driver control signal is a digital signal that has a rising edge that is followed by a falling edge; anda driver control circuit that receives the gate driver control signal and in response to the rising edge enables the first, second and third power transistor gate drivers sequentially in a first predetermined order, wherein each of the three power transistor gate drivers when enabled in response to the rising edge drives a high voltage onto its output lead, wherein the driver control circuit in response to the falling edge enables the first, second and third power transistor gate drivers sequentially in a second predetermined order, and wherein each of the three power transistor gate drivers when enabled in response to the falling edge drives a low voltage onto its output lead when it is enabled.2. ...

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Номер записи: 96
10-12-2020 дата публикации

Semiconductor Device and Semiconductor Arrangement Comprising Semiconductor Devices

Номер: US20200388612A1
Автор: Buschhorn Stefan, Laven Johannes Georg, MUELLER Christian Robert
Принадлежит:

An embodiment of a semiconductor device includes a plurality of transistor sections separated from each other and a plurality of diode sections separated from each other. Each transistor section includes an emitter electrode and a collector electrode. Each diode section includes an anode electrode and a cathode electrode. Each transistor section is electrically coupled to a common gate pad. A ratio between an active transistor part and an active diode part of the semiconductor device is adjustable by activating a first number of the transistor sections by selectively contacting the emitter electrodes and the collector electrodes of the first number of transistor sections, and by activating a second number of the diode sections by selectively contacting the anode electrodes and the cathode electrodes of the second number of diode sections. 1. A semiconductor device , comprising:a plurality of transistor sections that are separated from each other, wherein each of the plurality of transistor sections comprises an emitter electrode and a collector electrode; anda plurality of diode sections that are separated from each other, wherein each of the plurality of diode sections comprises an anode electrode and a cathode electrode,wherein each of the plurality of transistor sections is electrically coupled to a common gate pad,wherein a ratio between an active transistor part and an active diode part of the semiconductor device is adjustable by activating a first number of the transistor sections by selectively contacting the emitter electrodes and the collector electrodes of the first number of transistor sections, and by activating a second number of the diode sections by selectively contacting the anode electrodes and the cathode electrodes of the second number of diode sections.2. The semiconductor device of claim 1 , wherein the ratio between the active transistor part and the active diode part of the semiconductor device represents a ratio between a nominal current ...

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Номер записи: 97
15-05-2014 дата публикации

Semiconductor integrated circuit device and radio frequency module

Номер: KR101394699B1
Автор: 다까시 오가와, 도모유끼 이시까와, 신니찌로 다까따니, 신야 오사까베, 아끼시게 나까지마, 야스시 시게노
Принадлежит: 가부시키가이샤 무라타 세이사쿠쇼

고차 고조파 왜곡 또는 IMD를 저감 가능한 반도체 집적 회로 장치 및 고주파 모듈을 제공한다. 예를 들면, 안테나 단자 ANT와 복수의 신호 단자 Txa, Rxb, Rxc사이에 각각 복수의 트랜지스터 Qa, Qb, Qc를 구비한 소위 안테나 스위치에 대하여, 전압 공급 회로 VD_BK를 형성한다. 전압 공급 회로 VD_BK는, 전압 공급 단자 Vdd로부터 전술한 복수의 신호 단자 Txa, Rxb, Rxc 중 적어도 2개의 신호 단자(예를 들면 Rxb, Rxc)를 향하여 각각 저항 소자 Radd1, Radd2를 통하여 전압을 공급하는 회로이다. 이것에 의해, 리크 등에 의해 저하한 안테나 전압 Vant를 상승시키는 것이 가능해져서, 예를 들면 오프 상태로 되어 있는 트랜지스터 Qb, Qc를 깊은 오프 상태로 하는 것이 가능하게 된다. 고차 고조파 왜곡, IMD, 트랜지스터, 안테나, 신호 단자, 저항 소자, 안테나 전압, 오프 상태 A high-frequency module and a semiconductor integrated circuit device capable of reducing high-order harmonic distortion or IMD are provided. For example, a voltage supply circuit VD_BK is formed for a so-called antenna switch having a plurality of transistors Qa, Qb, and Qc between an antenna terminal ANT and a plurality of signal terminals Txa, Rxb, and Rxc. The voltage supply circuit VD_BK supplies voltage from the voltage supply terminal Vdd to at least two signal terminals (for example, Rxb and Rxc) among the above-mentioned plurality of signal terminals Txa, Rxb and Rxc through the resistance elements Radd1 and Radd2, respectively Circuit. As a result, it is possible to raise the antenna voltage Vant which has been lowered due to leak or the like, for example, to turn off the transistors Qb and Qc in the OFF state. High-order harmonic distortion, IMD, transistor, antenna, signal terminal, resistive element, antenna voltage, off state

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Номер записи: 98
14-12-2011 дата публикации

半导体集成电路器件和射频模块

Номер: CN101098135B
Автор: 中岛秋重, 小川贵史, 石川知之, 重野靖, 长壁伸也, 高谷信一郎
Принадлежит: Renesas Electronics Corp

半导体集成电路器件和射频模块，实现高阶谐波失真或IMD减小。例如，在天线端和多个信号端之间具有多个晶体管的所谓天线开关提供有电压供给电路。电压供给电路是用于从电压供给端经由电阻元件将电压供给到多个信号端中的至少两个信号端的电路。使用该配置，可以升高因泄漏等而降低的天线电压，并且例如可以将处于断态的晶体管设置成深的断态。

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Номер записи: 99
13-09-2017 дата публикации

MIT device molded by Clear compound epoxy and fire detecting device including the MIT device

Номер: KR101772588B1
Автор: 김봉준, 김현탁, 박종찬
Принадлежит: 한국전자통신연구원

본 발명은 클리어 컴파운드 에폭시로 몰딩한 MIT 소자 및 그것을 포함하는 화재 감지 장치에 관한 것이다. 본 발명의 실시 예에 따른 화재 감지 장치는 전원 제어 장치로부터 전원을 공급받는다. 상기 화재 감지 장치는 MIT 칩을 클리어 컴파운드 에폭시로 몰딩한 MIT 소자; 상기 전원 제어 장치로부터 전원을 공급받고, 무극성 전원을 제공하기 위한 다이오드 브릿지 회로; 상기 다이오드 브릿지 회로로부터 무극성 전원을 공급받고, 상기 MIT 소자로부터의 감지 신호에 응답하여 화재 경보를 알리기 위한 표시 회로; 및 상기 감지 신호를 일정 기간 동안 유지하기 위한 안정화 회로를 포함한다. The present invention relates to an MIT device molded with a clear compound epoxy and a fire detection device including the MIT device. A fire sensing apparatus according to an embodiment of the present invention receives power from a power control apparatus. The fire detection device includes an MIT device molded with a clear compound epoxy, an MIT chip, A diode bridge circuit for receiving power from the power supply control device and providing apolar power; A display circuit for receiving a nonpolar power from the diode bridge circuit and for informing a fire alarm in response to a sensing signal from the MIT device; And a stabilization circuit for maintaining the sensing signal for a predetermined period of time.

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Номер записи: 100