Integrierter elektronischer Stromkreis

Elektronische Vorrichtung mit wenigstens einem integrierten Stromkreis

STRUKTUR MIT EINGEBETTETER SPEICHERVORRICHTUNG UND KONTAKTISOLATIONSSCHEMA

Die vorliegende Offenbarung sieht ein Verfahren zum Herstellen einer integrierten Schaltung gemäß einigen Ausführungsformen vor. Das Verfahren umfasst das Ausbilden einer Source und eines Drain auf einem aktiven Finnenbereich eines Halbleitersubstrats; das Abscheiden einer Zwischenschicht-Dielektrikums- (ILD) - Schicht auf der Source und dem Drain; das Strukturieren der ILD-Schicht, um ein erstes Kontaktloch und ein zweites Kontaktloch auszubilden, die an der Source bzw. dem Drain ausgerichtet sind; das Ausbilden einer Dielektrikumsschicht in dem ersten Kontaktloch; und das Ausbilden eines ersten leitfähigen Elements und eines zweiten leitfähigen Elements in dem ersten bzw. dem zweiten Kontaktloch.

SEMICONDUCTOR DATA STORAGE ARRANGEMENTS

... 1502334 Integrated circuits INTERNATIONAL BUSINESS MACHINES CORP 21 May 1975 [28 June 1974] 21857/75 Heading H1K [Also in Division H3] A data store (see Division G4) is formed on a substrate 50 of P-silicon having bit lines B0, B1 formed of N-silicon and also forming the drain of FETs, the sources of which are formed of N-silicon at 51. The substrate is covered with arelatively thin layer 52 of SiO 2 /Si 3 N 4 which forms the gate dielectric of the FETs and the dielectric of the storage capacitors. A layer 54 of doped polycrystalline silicon has a resistivity of less than 1 kilohm/square and is connected to the substrate potential and serves as one of the capacitor electrodes over the source zone 51. Layer 54 also prevents undesirable inversion of the semiconductor surface. An intermediate insulating layer 56 of SiO 2 and gate metallization 55 are also applied extending as word lines WL orthogonally to the bit lines B0, B1.

MEMORY DEVICE

... 1525681 Semiconductor memory devices AMERICAN MICROSYSTEMS Inc 19 Jan 1977 [4 May 1976] 02191/77 Heading H1K A programmable read-only memory device comprises an array of insulated floating gates 40 on the walls of inverted-pyramid shaped recessess at intersections between diffused bit lines 28 and transverse word lines 26 insulated by thin dielectric material from the gates 40. As shown, the bit lines lie beneath a SiO 2 layer 44 but connect with surface bit line conductors 30 via contacts 32. The surface bit lines 30 are insulated from the word lines by a further SiO 2 layer 48. The s.c. substrate comprises (100) crystal Si and the recesses are anisotropically etched. The voltage on the floating gate determines the programmed condition of each cell depending on the hot electron injection across gate insulation 38 from the bit line 28 which forms the drain of a VMOS transistor together with the common source 22 of the substrate.

MEMORY CELL WITH ONE LATERALLY CONDENSER ARRANGED BY A TRANSISTOR

SEMICONDUCTOR ARRANGEMENT FOR STORING AND SELECTION OF INFORMATION

Semiconductor device with a field-effect transistor with insulating gate electrode and with such semiconductor device provided switching configuration

SINGLE IGFET MEMORY CELL WITH BURIED STORAGE ELEMENT

DUAL INJECTOR, FLOATING GATE MOS ELECTRICALLY ALTERABLE, NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

TI-6219 DUAL INJECTOR, FLOATING GATE MOS ELECTRICALLY ALTERABLE, NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, using process specifications and design rules of the same general character previously developed for single-level metal gate CMOS devices. An electron injector junction (p+/n) is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presense or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.

DYNAMIC MEMORY WITH NON-VOLATILE BACK-UP MODE

DYNAMIC MEMORY WITH NON-VOLATILE BACK-UP MODE A random access dynamic read-write FET memory system is provided with non-volatile storage of data in the event of a system power failure. The memory system includes an array of single device memory cells in which information is dynamically stored on a variable threshold nonvolatile capacitor. A memory protect circuit detects system power supply failures and causes data volatively stored directly in the storage capacitor dielectric of each memory cell. Upon restoration of power, the non-volatively stored data is read from the array into a small auxiliary memory and the variable threshold storage capacitors are restored to their original state. Data is then returned to the memory cells in a dynamic mode.

Speicherschaltung für Schieberegister

Dispositif électronique comprenant au moins un circuit électronique intégré

Feldeffekttransistor mit mindestens einer isolierten Torelektrode

Kapazitiver wortorientierter Speicher mit Feldeffekt-Transistoren

Dispositif électronique comprenant au moins un circuit électronique intégré

RESIDUAL SEMICONDUCTOR MEMORY HAS FLOATING GRID AND DOUBLE INJECTOR

METHOD FOR MANUFACTURING AN MOS INTEGRATED CIRCUIT

DEVICE SEMICONDUCTOR, BEING USED WITH STORAGE AND the READING As INFORMATION

Semiconductor device for high voltage, in particular of the bipolar type, and integrated circuit comprising such a device and method for producing the same

Electronic device including/understanding at least an integrated electronic circuit

DYNAMIC STORAGE HAS SEMICONDUCTOR COMPRISING ELEMENTS Of STORAGE HAS TWO DEVICES

METHOD FOR MANUFACTURING AN MOS INTEGRATED CIRCUIT

CELL AND PAIR OF STORAGE CELLS HAVE DIRECT ACCESS WITHOUT CONTACT

High density ball grid array (BGA) package capacitor design

A circuit package is provided that includes a substrate having a first side and a second side, an integrated circuit component coupled to the second side of the substrate, and a ball grid array formed on the first side of the substrate, the ball grid array including multiple contact balls arranged in a pattern. Each of a first subset of the contact balls is electrically coupled to a first voltage input of an integrated circuit component, and each of a second subset of the contact balls is electrically coupled to a second voltage input of the integrated circuit component. The package also includes a capacitor mounted to the first side and having a first terminal coupled to a first contact ball in the first subset of the contact balls and a second terminal coupled to a second contact ball in the second subset of the contact balls.

Decoupling Capacitor for FinFET Compatible Process

A decoupling capacitor formed from a fin field-effect transistor (FinFET) and method of using the same are provided. An embodiment decoupling capacitor includes a fin field-effect transistor (FinFET) having a semiconductor substrate supporting a gate stack, a source, and a drain, a first terminal coupled to the semiconductor substrate and to the gate stack, the first terminal configured to couple with a first power rail, and a second terminal coupled to the source and to the drain, the second terminal configured to couple with a second power rail having a higher potential than the first power rail. 1. A decoupling capacitor , comprising:a fin field-effect transistor (FinFET) having a semiconductor substrate supporting a fin disposed between isolation regions, the fin including a source and a drain on opposing sides of a channel region beneath a gate stack;a first terminal coupled to the semiconductor substrate and to the gate stack, the first terminal configured to couple with a first power rail; anda second terminal coupled to the source and to the drain, the second terminal configured to couple with a second power rail.2. The decoupling capacitor of claim 1 , wherein the second power rail has a higher potential than the first power rail.3. The decoupling capacitor of claim 1 , wherein the FinFET is configured to provide a total capacitance of greater than about 0.5 femtofarad per micrometer (fF/μm).4. The decoupling capacitor of claim 1 , wherein the FinFET is configured to provide a total capacitance of greater than about 0.8 femtofarad per micrometer (fF/μm).5. The decoupling capacitor of claim 1 , wherein the FinFET is configured to have a total capacitance of between about 4.0 femtofarad per square micrometer (A/μm) and about 2.0 femtofarad per square micrometer (A/μm) over a channel length of between about 0.02 μm and about 0.1 μm.6. The decoupling capacitor of claim 1 , wherein the FinFET is configured to have a leakage current of less than about 1.0×10amps ...

STRUCTURES FOR TESTING NANOSCALE DEVICES INCLUDING FERROELECTRIC CAPACITORS AND METHODS FOR FORMING THE SAME

A ferroelectric device structure includes an array of ferroelectric capacitors overlying a substrate, first metal interconnect structures electrically connecting each of first electrodes of the array of ferroelectric capacitors to a first metal pad embedded in a dielectric material layer, and second metal interconnect structures electrically connecting each of the second electrodes of the array of ferroelectric capacitors to a second metal pad embedded in the dielectric material layer. The second metal pad may be vertically spaced from the substrate by a same vertical separation distance as the first metal pad is from the substrate. First metal lines laterally extending along a first horizontal direction may electrically connect the first electrodes to the first metal pad, and second metal lines laterally extending along the first horizontal direction may electrically connect each of the second electrodes to the second metal pad.

POWER MOSFETS STRUCTURE

A semiconductor device is provided. The semiconductor device includes a substrate, a field plate, a gate electrode, and a first dielectric layer. The substrate has a top surface. The substrate includes a first drift region with a first conductivity type extending from the top surface of the substrate into the substrate, and includes a second drill region with the first conductivity type extending from the top surface of the substrate into the substrate and adjacent to the first drift region. The field plate is over the substrate. The gate electrode has a first portion and a second portion, wherein the first portion of the gate electrode is located over the field plate. The first dielectric layer is between the substrate and the field plate. The first portion of the gate electrode is overlapping with a boundary of the first drift region and the second drift region in the substrate. 1. A semiconductor device , comprising: a first drift region with a first conductivity type, extending from the top surface of the substrate into the substrate; and', 'a second drift region with the first conductivity type, extending from the top surface of the substrate into the substrate and adjacent to the first drift region;, 'a substrate having a top surface, comprisinga field plate over the substrate;a gate electrode having a first portion and a second portion, wherein the first portion of the gate electrode is located over the field plate; anda first dielectric layer sandwiched by the substrate and the field plate;wherein the first portion of the gate electrode is overlapping with a boundary of the first drift region and the second drift region in the substrate.2. The semiconductor device of claim 1 , further comprising a silicide layer on the gate electrode claim 1 , and each side of the silicide layer is substantially aligned with each side of the gate electrode.3. The semiconductor device of claim 1 , further comprising a second dielectric layer between the field plate and the ...

Semiconductor structures with deep trench capacitor and methods of manufacture

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

MEMORY HAS SEMICONDUCTOR

CELL AND PAIR OF STORAGE CELLS HAVE DIRECT ACCESS WITHOUT CONTACT

DIGITALLY CONTROLLABLE ENHANCED CAPACITOR

MANUFACTORING PROCESS OF JUST CIRCUITS AUTO-ALIGNES AND DEVICES WHILE RESULTING

FET ADDRESS DECODER

RESIDUAL SEMICONDUCTOR MEMORY HAS FLOATING GRID AND DOUBLE INJECTOR

METHOD FOR MANUFACTURING AN MOS INTEGRATED CIRCUIT

INTEGRATED CIRCUIT COMPRISING A CAPACITIVE ELEMENT, AND MANUFACTURING METHOD

A capacitive element of an integrated circuit includes first and second electrodes. The first electrode is formed by a first electrically conductive layer located above a semiconductor well doped with a first conductivity type. The second electrode is formed by a second electrically conductive layer located above the first electrically conductive layer of the semiconductor well. The second electrode is further formed by a doped surface region within the semiconductor well that is heavily doped with a second conductivity type opposite the first conductivity type, wherein the doped surface region is located under the first electrically conductive layer. An inter-electrode dielectric area electrically separates the first electrode and the second electrode.

Single IGFET memory cell with buried storage element

A semiconductor read/write memory comprised of an array of cells, each having a single active element that is a IGFET device formed in a recess with one source or drain region located directly above and its other source or drain region located within a buried storage capacitor. The gate of each device is connected to an address line in the array, and transverse diffused bit lines interconnect the drains of the devices in aligned and spaced apart cells. Voltage applied via an address line activates a gate to charge its buried capacitor and store a signal when its connected bit line is also activated. Readout of stored charges is controlled by the address line through the connected bit line in the conventional manner. A memory device with an array of such single element cells can be fabricated by forming an array of N-type buried layer diffusions in a P substrate, depositing an epitaxial layer of lightly doped P material that extends above the buried layer diffusions, forming a relatively ...

PACKAGED SEMICONDUCTOR DEVICE

A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals. 1. A packaged semiconductor device , comprising:a multi-layer molded interconnect substrate (MIS) having a signal layer including first and second traces for a first channel and first and second traces for a second channel on a dielectric layer with vias, and a bottom metal layer under the dielectric layer for providing a ground return path, the signal layer including contact pads, wherein the first and second traces of the first and second channel include narrowed trace regions and the bottom metal layer comprises a patterned layer including a plurality of ground cut regions;a first and a second direct current (DC) blocking capacitor in series within the first and second traces of the first channel for providing alternating current (AC) coupling, the first and second DC blocking capacitors each with one plate over one of the ground cuts;a third and a fourth DC blocking capacitor in series within the first and second traces of the second channel for providing AC coupling, the third and fourth DC blocking capacitors each with one plate over one of the ground cuts, andan integrated circuit (IC) including a first differential ...

METHOD FOR FORMING CAPACITOR, SEMICONDUCTOR DEVICE, MODULE, AND ELECTRONIC DEVICE

A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.

METHOD OF PRODUCING PARASITIC CAPACITY CONTROLLED SEMICONDUCTOR DEVICE

DYNAMISCHER HALBLEITERSPEICHER MIT ZWEI-TRANISTOR-SPEICHERELEMENTEN

Memory cell with read transistor, tunnelling capacitor and coupling capacitors in series

A memory cell structure for a memory device is provided, the memory cell structure comprising a read transistor (120) having a floating gate node (140), a tunneling capacitor (130), and a coupling capacitor stack (200). The tunnelling capacitor is connected to the floating gate node and has a first programming terminal (160), whilst the coupling capacitor stack is connected to the floating gate node and has a second programming terminal (150). The coupling capacitor stack has at least two coupling capacitors arranged in series between the floating gate node and the second programming terminal, with the coupling capacitor stack having a larger capacitance than the tunnelling capacitor. During aprogramming operation, a voltage difference is established between the first programming terminal and the second programming terminal to cause charge tunneling to occur through the tunnelling capacitor, such that after the programming operation a charge is stored in the floating gate node. During a ...

Drain extended mos transistors with multiple capacitors and method of fabrication

DYNAMIC DATA STORAGE CELL

... 1412132 Semi-conductor matrix stores TEXAS INSTRUMENTS Inc (P M Frandon) 10 Oct 1972 46587/72 Heading G4C [Also in Division H1] An integrated matrix of IGFET storage cells for use in a dynamic random access memory comprises a grounded wafer of P type silicon with parallel interleaved N + and P + strips 70, 74 (Fig. 5) formed by diffusion in one face and further N+ regions 76 individual to each cell each overlying part of a P + strip and having a portion 76a extending beyond the strip towards the adjacent N + strip. Strip 70 constitutes the drain regions of all the transistors in a column while regions 76 constitute the sources, the junction capacitances of which are enhanced by the heavy doping of strips 74. A layer of insulation 80 of silicon dioxide and/or nitride is 500 Š thick over the IGFET channels 78 and 10,000 Š thick elsewhere. Each row conductor 82 which may be of aluminium or silicon runs normal to the strips and forms the gate of all transistors in the row. One cycle of operation ...

SEMICONDUCTOR ARRANGEMENT FOR STORING AND SELECTION OF INFORMATION

METHOD OF MANUFACTURING PARALLEL GATE TYPE MATRIX CIRCUITS

FIELD EFFECT TRANSISTOR CIRCUIT

Memory including two transistors and one capacitor, apparatus for access to the memory and method

半导体器件及其制造方法

... 通过在高频用的MIM电容器中在相同的上下电极间具有不同的电容器绝缘膜结构，同时满足了减少漏泄电流的要求和缩小电容器形成用的面积这2个要求。通过在低漏泄电流为必要的电容器中插入能抑制漏泄电流的电容器绝缘膜层，实现了低漏泄电流的MIM电容器，通过在电容器面积的缩小为必要的电容器中将高介电常数电介质膜用作电容器绝缘膜，实现了电容器面积小的MIM电容器。通过使用相同的上下电极(13)、(17)同时形成具有这二种特性的电容器，减少了工艺成本的上升。 ...

Semiconductor device for high voltage, in particular of the bipolar type, and integrated circuit comprising such a device and method for producing the same

DIGITALLY CONTROLLABLE ENHANCED CAPACITOR

Field-Effect Transistor Memory

METHOD FOR MANUFACTURING AN MOS INTEGRATED CIRCUIT

반도체 소자

... 본 발명의 개념에 따른 반도체 소자는 연결 영역을 포함하는 반도체 기판, 상기 반도체 기판 상에 제공되는 한 쌍의 에피 패턴들, 상기 에피 패턴들 사이에 배치되는 커패시터, 상기 커패시터 상의 중간 연결 층, 상기 중간 연결 층 상의 배선 층, 및 상기 배선 층 아래에 제공되어, 상기 연결 영역의 반도체 기판을 관통하는 관통 비아를 포함한다. 상기 커패시터는 상기 한 쌍의 에피 패턴들 사이의 상기 반도체 기판의 상부, 상기 반도체 기판 상의 금속 전극, 및 상기 반도체 기판 및 상기 금속 전극 사이에 개재되는 유전 패턴을 포함한다. 상기 관통 비아는 상기 배선 층 및 상기 중간 연결 층을 통하여, 상기 커패시터와 연결될 수 있다.

Method to fabricate capacitance-matching FET and related device

Methods for producing FETs with negative capacitance and the resulting device are disclosed. Embodiments include forming a gate stack over a semiconductor substrate by: forming a gate oxide over the semiconductor substrate; forming a first metal gate electrode over the gate oxide; forming a dummy gate over the metal gate electrode; and forming sidewall spacers on first and second sides of the gate stack; forming an ILD over the substrate and gate stack; removing the dummy gate and at least a portion of sidewall spacers to form an opening; forming a ferro-electric (FE) layer in the opening; and forming a second metal gate electrode over the FE layer.

MONOLITHICALLY INTEGRATED ACTIVE SNUBBER

A semiconductor device (100) containing an extended drain MOS transistor (106) with an integrated snubber formed by forming a drain drift region (108) of the MOS transistor, forming a snubber capacitor including a capacitor dielectric layer (122) and capacitor plate (124) over the extended drain (108), and forming a snubber resistor (136) over a gate (114) of the MOS transistor so that the resistor is connected in series between the capacitor plate and a source (118) of the MOS transistor.

Epitaxial method of fabricating single IGFET memory cell with buried storage element

A semiconductor read/write memory comprised of an array of cells, each having a single active element that is a IGFET device formed in a recess with one source or drain region located directly above and its other source or drain region located within a buried storage capacitor. The gate of each device is connected to an address line in the array, and transverse diffused bit lines interconnect the drains of the devices in aligned and spaced apart cells. Voltage applied via an address line activates a gate to charge its buried capacitor and store a signal when its connected bit line is also activated. Readout of stored charges is controlled by the address line through the connected bit line in the conventional manner. A memory device with an array of such single element cells can be fabricated by forming an array of N-type buried layer diffusions in a P substrate, depositing an epitaxial layer of lightly doped P material that extends above the buried layer diffusions, forming a relatively ...

Integrated circuit device

An integrated circuit device comprising a semiconductor substrate of one conductivity type and provided with a circuit element capable of dynamically holding electric charges and another circuit element having p-n junctions, characterized in that at least one part of that region of the substrate which surrounds the circuit element capable of holding the above-mentioned charges is formed of an absorption region having an opposite conductivity type to that of the substrate; and that said absorption region is impressed with the highest or substantially highest level of voltage among those impressed on the circuits included in the integrated circuit device, thereby enabling the absorption region to catch minority carriers injected from said another circuit element into the substrate.

Self-refreshed capacitor memory cell

This invention involves a memory cell of, for example, the metal-oxide-semiconductor (MOS) capacitor type, which is accessed for reading and writing by means of an access network connected to the memory cell through a gating transistor, and which is provided with an independent refresh network for maintaining the memory state of the cell in the absence of an access writing signal. The refresh network includes a pair of IGFET (Insulated Gate Field-Effect Transistors) transistors connected between the MOS capacitor and an AC refresh line which is completely independent of the electrical access network. Either a "full" or "empty" capacitor memory state, binary digital 1 or 0, respectively, is maintained without the need for interrupting the reading and writing of the MOS capacitor through the gating transistor.

Bucket brigade device and process

The invention is the structure and process for making a bucket brigade device which comprises the merger of an MOS capacitor with an MOSFET device to form the charge transfer cell. A thin n-type region is implanted in a portion of the p-type channel region of an FET device adjacent to the drain diffusion. This structure increases the charge transfer efficiency for the cell and reduces its sensitivity of the threshold voltage to the source-drain voltage. The gate for the device has a substantial overlap over the drain and a minimal overlap over the source and the gate to drain capacitance per unit area is maximized by maintaining a uniformly thin oxide layer across the gate region.

SEMICONDUCTOR DEVICE

According to one embodiment, semiconductor device includes: a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type provided on the first semiconductor region; a third semiconductor region of the first conductive type provided on the second semiconductor region, the third semiconductor region having a higher impurity concentration than the impurity concentration of the first semiconductor region; a third electrode in contact with the third semiconductor region, the second semiconductor region, and the first semiconductor region via a first dielectric film; and a capacitance element unit having a fourth electrode provided above the second semiconductor region, a fifth electrode provided above the fourth electrode, and a second dielectric film provided between the fourth electrode and the fifth electrode. 1. A semiconductor device comprising:a first semiconductor region of a first conductive type;a second semiconductor region of a second conductive type provided on the first semiconductor region;a third semiconductor region of the first conductive type provided on the second semiconductor region, the third semiconductor region having a higher impurity concentration than the impurity concentration of the first semiconductor region;a third electrode in contact with the third semiconductor region, the second semiconductor region, and the first semiconductor region via a first dielectric film; anda capacitance element unit having a fourth electrode provided above the second semiconductor region, a fifth electrode provided above the fourth electrode, and a second dielectric film provided between the fourth electrode and the fifth electrode.2. The device according to claim 1 , further comprising:a first electrode; anda second electrode,the first semiconductor region being provided between the first electrode and the second electrode;the second semiconductor region being provided between the first semiconductor ...

ONE TRANSISTOR-ONE CAPACITOR MEMORY CELL

Halbleiterbauelement mit inhärenten Kapazitäten und Verfahren zur Herstellung desselben

Die Erfindung betrifft ein Halbleiterbauelement (1) mit inhärenten Kapazitäten (CGD, CDS) und ein Verfahren zur Herstellung desselben. Dazu weist das Halbleiterbauelement (1) eine inhärente Rückwirkungskapazität (CGD) zwischen einer Steuerelektrode (9) und einer ersten Elektrode (10) auf. Außerdem weist das Halbleiterbauelement (1) eine inhärente Drain-Source-Kapazität (CDS) zwischen der ersten Elektrode (10) und einer zweiten Elektrode (11) auf. Mindestens eine monolithisch integrierte Zusatzkapazität (CZ) ist parallel zu der inhärenten Rückwirkungskapazität (CGD) oder parallel zu der inhärenten Drain-Source-Kapazität (CDS) geschaltet. Die Zusatzkapazität (CZ) weist eine erste Kondensatorfläche (12) und eine der ersten Kondensatorfläche (12) gegenüberliegende zweite Kondensatorfläche (13) auf. Die Kondensatorflächen (12, 13) sind strukturierte leitende Schichten (14, 15) des Halbleiterbauelements (1) auf einer Oberseite (16) des Halbleiterkörpers (20), zwischen denen eine dielektrische ...

INTEGRATED SEMICONDUCTOR STRUCTURE

... 1496119 IC memory devices INTERNATIONAL BUSINESS MACHINES CORP 31 Aug 1976 [29 Sept 1975] 36053/76 Heading H1K An IC memory array is made by forming a pair of isolation strips 12, 14, Fig. 2A adjacent the surface of a semiconductor substrate, forming conductive lines 22-32, and forming doped semiconductor regions 34-46, Fig. 2C, in the areas between the isolation strips 12, 14 and the conductive lines 22-32. The device thus formed may be used as a chain of IGFETs. An alternative memory array includes IGFETs and MIS capacitors 54-60 and is formed by connecting selected lines 22, 26, 28, 32 to a word driver and bias source 64 and the remaining conductive lines 24, 30 to a reference potential 74, 76 so that they act as field shields. The doped regions 34, 40, 46 form drain regions and the regions 36, 38, 42, 44 form source regions as well as one plate of the respective MIS capacitors 54-60. The other capacitor plates 50, 52 are connected to potentials 61, 63 and the capacitors are addressed ...

A memory cell structure, a memory device employing such a memory cell structure,and an integrated circuit having such a memory device

SEMICONDUCTOR MEMORY DEVICES

METHOD FOR MANUFACTURING AN MOS INTEGRATED CIRCUIT

... 1357515 Semi-conductor devices MATSUSHITA ELECTRONICS CORP 6 March 1973 [10 March 1972] 10740/73 Heading H1K In a method of manufacturing a Si MOS integrated circuit in which the gate structure 2, 3 is used as a self-registering mask for diffusion of source and drain regions one pair of source and drain regions 4, 5 is interconnected by the earlier provision beneath the gate structure 2, 3 of a diffused region 9 of the same conductivity type as the regions 4, 5. The gate electrode 3 may be of Mo or polycrystalline Si.

BISTABLE STORAGE ELEMENTS

... 1379408 FET data storage circuits SIEMENS AG 30 Dec 1971 [5 Feb 1971] 60810/71 Heading H3T [Also in Division H1] A bi-stable has F.E.T.'s 11, 15, with capacitor loads 12, 16, cross-coupled by voltage-dependent resistors such as F.E.T.'s 13, 17; and input/ output F.E.T.'s 5, 6. Read-write bit lines and the F.E.T.'s 4, 6 charge and discharge C12, C16 so that for example C16 is positively charged, C12 is discharged. When a pulse power supply makes terminal 2 positive relatively to 1 and p-channel F.E.T.'s are used, F.E.T. 15 is held off by the positive potential on C16 applied through F.E.T. 17 which has been turned on thereby. The potentials at 112 (U1, Fig. 2, not shown), rises to a proportion of the pulse power amplitudes (U) determined by the potential divider formed by C12 and the circuit capacitances between 112 and 2. F.E.T. 13 is then turned on (by U1) and applies this potential (U1) to F.E.T. 11 gate to turn it on. Thus C14, C16 are kept charged by the pulse power supply, the state ...

HALBLEITERANORDNUNG ZUM SPEICHERN UND AUSLESEN VON INFORMATION

SELF-ALIGNED INTEGRATED CIRCUITS

DYNAMIC MEMORY WITH NON-VOLATILE BACK-UP MODE

METHOD OF MANUFACTURING AN MOS INTEGRATED CIRCUIT

INTEGRATED CELL PRECARACTERISEE

MANUFACTORING PROCESS OF THE DEVICES SEMICONDUCTORS WITH ORDERING OF THE STRAY CAPACITY PARTICULARLY ADAPT IN THE NETWORKS OF MEMORY HAS ONLY ONE FIELD-EFFECT TRANSISTOR

METHOD FOR MANUFACTURING AN MOS INTEGRATED CIRCUIT

DYNAMIC STORAGE HAS SEMICONDUCTOR COMPRISING ELEMENTS Of STORAGE HAS TWO DEVICES

FIELD EFFECT TRANSISTOR CIRCUIT

ELEMENT CIRCUIT FOR A SEMICONDUCTOR MEMORY

METAL CAPACITOR WITH INNER FIRST TERMINAL AND OUTER SECOND TERMINAL

A metal capacitor with an inner first terminal (e.g., a positive terminal) and an outer second terminal (e.g., a negative terminal) is disclosed herein. In an exemplary design, an apparatus (e.g., an IC chip) includes a first conductive line for a first terminal of a capacitor and at least one conductive line for a second terminal of the capacitor. The at least one conductive line is formed on opposing first and second sides of the first conductive line. Parallel conductive traces are formed transverse to, and on both the first and second sides of, the first conductive line. Additional parallel conductive traces are formed transverse to the at least one conductive line and are interlaced with the parallel conductive traces coupled to the first conductive line. The metal capacitor includes a plurality of unit capacitors formed by the parallel conductive traces coupled to the conductive lines.

Metal-oxide-metal (MOM) capacitor with enhanced capacitance

A particular metal-oxide-metal (MOM) capacitor device includes a conductive gate material coupled to a substrate. The MOM capacitor device further includes a first metal structure coupled to the conductive gate material. The MOM capacitor device further includes a second metal structure coupled to the substrate and proximate to the first metal structure.

FIELD-EFFECT INTEGRATED CIRCUIT AND METHOD OF FABRICATION

Dynamic single-transistor memory element for relatively permanent memories

The invention relates to a dynamic single-transistor memory element whereby the information may be stored for long periods of time without an energy supply. The invention also provides for a dynamic single-transistor memory element having the capability of storing two differing information pulses. The write-in process may be effectuated element-wise, line-wise, or matrix-wise. The invention further provides the capability to effectuate the erasure of the information line by line where the information is intermedially stored in the regenerator amplifiers or matrix by matrix where the intermediate storage occurs in the second matrix.

ANTI-FUSSE STRUCTURE AND METHOD OF FABRICATING THE SAME

An anti-fuse structure and a method of fabricating the same are described. The anti-fuse structure is disposed over a substrate having at least one device and a copper layer therein. The anti-fuse structure includes a bottom conductive layer, an insulating layer and a top conductive layer. The bottom conductive layer is disposed over and electrically connected with the copper layer. The insulating layer is conformally disposed over the bottom conductive layer covering a corner or a downward turning portion of the bottom conductive layer to form a turning portion of the insulating layer. The top conductive layer is conformally disposed over the insulting layer covering the turning portion of the insulating layer.

Method to fabricate capacitance-matching FET and related device

Methods for producing FETs with negative capacitance and the resulting device are disclosed. Embodiments include forming a gate stack over a semiconductor substrate by: forming a gate oxide over the semiconductor substrate; forming a first metal gate electrode over the gate oxide; forming a dummy gate over the metal gate electrode; and forming sidewall spacers on first and second sides of the gate stack; forming an ILD over the substrate and gate stack; removing the dummy gate and at least a portion of sidewall spacers to form an opening; forming a ferro-electric (FE) layer in the opening; and forming a second metal gate electrode over the FE layer.

MOS-Schalter zur Verminderung des Übersprechens eines Taktgebers in einem Schalter-Kondensator-Schaltkreis

SEMICONDUCTOR STORES

... 1530094 Integrated information store SIEMENS AG 11 Feb 1977 [4 May 1976] 5813/77 Heading H1K An information store comprises a heavily doped semiconductor substrate SU (Fig. 4) of one conductivity type carrying a lightly doped epitaxial layer of the same type, a buried layer of opposite type disposed beneath the epitaxial layer and a further layer of said opposite type located in the epitaxial layer surface above the buried layer, a V-groove extending from the surface to divide the surface and buried layers into zones BL1, BL2 and BU1, BU2 respectively and a conductive track WL extending in the groove but insulated from its walls. As described each pair of zones BL, BU defines the ends of the channel of an IGFET whose gate is formed by the track WL (of polysilicon or metal), each IGFET thus being in series with a storage capacitor formed by the PN junction between the respective zone BU and the substrate. The zones BL form part of respective bit lines running normal to word lines WL whereas ...

SEMI-CONDUCTOR MEMORY DEVICE

... 1531824 Semi-conductor devices AMERICAN MICROSYSTEMS Inc 19 May 1976 [23 Oct 1975] 20567/76 Heading H1K A semi-conductor memory cell comprises an IGFET having a buried source region 34 in a substrate 36, which region also constitutes a storage capacitor, an overlying drain region 40 in the surface of an epitaxial layer 50, and a gate oxide 58 and conductor 60 located between the regions 34, 40 on a wall of a recess 56 extending through the region 40 and reaching the region 34. The recess 56 is preferably of V-shaped cross-section, being formed by anisotropic etching. The gate conductor 60, which may be of metal or polysilicon, preferably extends as a memory address line 44 for an array of such cells, and similarly an extension 42 of the region 40 constitutes a bit line. Alternatively the bit line may comprise an extension of the buried source/capacitor region 34. The semi-conductor body may also contain planar surface IGFETs and implanted resistors. An outdiffused layer 52 of resistivity ...

INTEGRATED CIRCUIT FABRICATION PROCESS

INTEGRATED CIRCUIT

DYNAMIC STORAGE HAS SEMICONDUCTOR

METHOD FOR MANUFACTURING AN MOS INTEGRATED CIRCUIT

DEVICE SEMICONDUCTOR, BEING USED WITH STORAGE AND the READING As INFORMATION

INTEGRATED CIRCUIT FABRICATION PROCESSES

Semiconductor device

An object of the present invention is to provide a semiconductor device in which stored data can be held even when power is not supplied for a certain time. Another object is to increase the degree of integration of a semiconductor device and to increase the storage capacity per unit area. A semiconductor device is formed with a material capable of sufficiently reducing off-state current of a transistor, such as an oxide semiconductor material that is a wide-bandgap semiconductor. With the use of a semiconductor material capable of sufficiently reducing off-state current of a transistor, the semiconductor device can hold data for a long time. Furthermore, a wiring layer provided under a transistor, a high-resistance region in an oxide semiconductor film, and a source electrode are used to form a capacitor, thereby reducing the area occupied by the transistor and the capacitor.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A method for manufacturing a semiconductor device comprises: forming a lower electrode on a semiconductor substrate, sputtering a ferroelectric film on the lower electrode using a target, thermal treating the ferroelectric film in an atmosphere containing oxygen in accordance with an accumulated period of use of the target for fabricating the ferroelectric film, and forming an upper electrode on the ferroelectric film. 112-. (canceled)13. A semiconductor device comprising:a semiconductor substrate: anda ferroelectric capacitor formed on the semiconductor substrate, the ferroelectric capacitor comprising:a ferroelectric film; anda pair of electrodes wherein the ferroelectric film is disposed therebetween,wherein the ferroelectric film is formed using sputtering and thermal treatment in an atmosphere where the amount of oxygen varies in accordance with the accumulated period for a target.14. The semiconductor device according to claim 13 , wherein the oxygen amount used in thermal treating is changed from 40 sccm to 100 sccm in accordance with the accumulated period.15. The semiconductor device according to claim 13 , wherein the thermal treating is RTA (rapid thermal annealing).16. The semiconductor device according to claim 13 , wherein the temperature of the thermal treating is set from 545° C. to 565° C.17. The semiconductor device according to claim 13 , wherein during the first half of the lifetime of the target claim 13 , the oxygen amount is set from 40 sccm to 60 sccm claim 13 , andduring the first half of the lifetime of the target, the oxygen amount is set up from 70 sccm to 100 sccm.18. The semiconductor device according to claim 13 , further including:a gate dielectric film formed on the semiconductor substrate,a gate electrode formed on the gate dielectric film,an impurity region introduced on the semiconductor substrate, anda wiring layer formed on the ferroelectric capacitor.19. The semiconductor device according to claim 18 , wherein the gate ...

SEMICONDUCTOR DEVICE

A semiconductor device capable of high-speed operation. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is supplied with a first signal. One of a source and a drain of the second transistor is supplied with a first potential. A gate of the second transistor is supplied with a second signal. A first electrode of the capacitor is electrically connected to the other of the source and the drain of the first transistor. A second electrode of the capacitor is electrically connected to the other of the source and the drain of the second transistor. In a first period, the first signal is low and the second signal is high. In a second period, the first signal is high and the second signal is either low or high. 1. A semiconductor device comprising:a first transistor comprising a source and a drain one of which is supplied with a first signal;a second transistor comprising a source and a drain one of which is supplied with a first potential, and a gate supplied with a second signal; anda capacitor comprising a first electrode electrically connected to the other of the source and the drain of the first transistor, and a second electrode electrically connected to the other of the source and the drain of the second transistor,wherein in a first period, the first signal is low and the second signal is high, andwherein in a second period, the first signal is high and the second signal is either low or high.2. The semiconductor device according to claim 1 , further comprising:a fourth transistor comprising a source and a drain one of which is supplied with the first potential and the other of which is electrically connected to the other of the source and the drain of the first transistor, and a gate electrically connected to the other of the source and the drain of the second transistor;a fifth transistor comprising a source and a drain one of which is supplied with the first potential ...

Decoupling capacitor cell, cell-based ic, cell-based ic layout system and method, and portable device

A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal layers. The decoupling capacitor cell is arranged in an unused region not occupied by basic cells in a cell-based IC and is connected to a power wiring and a ground wiring.

ELECTRICALLY ERASABLE PROGRAMMABLE NON-VOLATILE MEMORY

In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation. 1. A method of fabricating a floating-gate p-type MOSFET comprising:forming a first and a second thick oxide region on a p-type substrate;implanting a first and a second Pwell region below the first and second thick oxide region respectively;implanting an Nwell region between the first and second thick oxide regions and the first and second Pwells;growing a gate insulation on the Nwell region;depositing poly-silicon on the gate insulation;etching the poly-silicon to form a poly-silicon gate;forming oxide side-walls on sides of the poly-silicon gate;forming nitride side-walls on the oxide side-walls;implanting an p-type dopant into the Nwell on both sides of the nitride side-walls forming a source and a drain;forming a silicide-blocking layer over the poly-silicon gate, the oxide side-walls, the nitride walls, a first portion of the source and a first portion of the drain;forming a silicide on a second portion of the source and on a second portion of the drain;forming a nitride layer over the silicide-blocking layer, the poly-silicon gate, the oxide side-walls, the nitride walls, the first portion of the source and the first portion of the drain;forming a conductive layer over the nitride layer;forming metal ...

SEMICONDUCTOR DEVICE

A semiconductor device including a capacitor with increased charge capacity and having a high aperture ratio and low power consumption is provided for a semiconductor device including a driver circuit. The semiconductor device includes a driver circuit which includes a first transistor including gate electrodes above and below a semiconductor film so as to overlap with the semiconductor film; a pixel which includes a second transistor including a semiconductor film; a capacitor which includes a dielectric film between a pair of electrodes in the pixel; and a capacitor line electrically connected to one of the pair of electrodes. In the semiconductor device, the gate electrode over the semiconductor film of the first transistor is electrically connected to the capacitor line. 1. A semiconductor device comprising:a driver circuit which includes a first transistor including a first semiconductor film;a pixel which includes a second transistor including a second semiconductor film;a capacitor which includes a dielectric film between a pair of electrodes in the pixel; anda capacitor line electrically connected to one of the pair of electrodes,wherein the first transistor includes a first gate electrode below the first semiconductor film and a second gate electrode above the first semiconductor film, andwherein the second gate electrode is electrically connected to the capacitor line.2. The semiconductor device according to claim 1 , wherein the capacitor comprises a third semiconductor film on the same surface as the second semiconductor film claim 1 , and wherein the third semiconductor film is in contact with the capacitor line.3. The semiconductor device according to claim 1 , wherein the capacitor line extends in a direction parallel to a signal line which is electrically connected to a source electrode and a drain electrode of the second transistor and is provided on the same surface as the source electrode or the drain electrode of the second transistor.4. A ...

SEMICONDUCTOR DEVICE

A semiconductor device comprises an isolation region, an active region, a first gate trench extending continuously from the active region to the isolation region, first and second insulating films, a first conductive layer, and a cap insulating film. The first insulating film covers an inner surface of the first gate trench. The second insulating film interposes between the first insulating film and the inner surface of the first gate trench at the active region. The first conductive layer buries a lower portion of the first gate trench so as to cover at least a part of the first insulating film. The cap insulating film covers the upper surface of the first conductive layer and buries an upper portion of the first gate trench 1. A semiconductor device comprising:an isolation region buried with a field insulator;an active region surrounded with the isolation region;a first gate trench extending continuously from the active region to the isolation region;a first insulating film covering an inner surface of the first gate trench in each of the active region and the isolation region;a second insulating film interposing between the first insulating film and the inner surface of the first gate trench at the active region;a first conductive layer burying a lower portion of the first gate trench so as to cover at least a part of the first insulating film and having an upper surface, the upper surface being placed below a surface of the active region; anda cap insulating film covering the upper surface of the first conductive layer and burying an upper portion of the first gate trench.2. The semiconductor device according to claim 1 , further comprising:a second gate trench extending continuously from the active region to the isolation region;a first diffusion layer placed in the active region which is located between the first gate trench and the second gate trench;second diffusion layers placed in the active region which are located on an opposite side of the first and ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A favorable semiconductor device for miniaturization and high integration is provided. One embodiment of the present invention includes a first oxide including a first region and second region adjacent to each other, a third region and a fourth region with the first region and the second region provided therebetween, a second oxide over the first region, a first insulator over the second oxide, a first conductor over the first insulator, a second insulator over the second oxide and on side surfaces of the first insulator and the first conductor, a third insulator over the second region and on a side surface of the second insulator, and a second conductor over the second region with the third insulator provided therebetween. A part of the third insulator is positioned between the second conductor and the side surface of the second insulator. 1. A semiconductor device comprising: a first region and a second region adjacent to each other; and', 'a third region and a fourth region with the first region and the second region provided between the third region and the fourth region;, 'a first oxide comprisinga second oxide over the first region;a first insulator over the second oxide;a first conductor over the first insulator;a second insulator over the second oxide, the second insulator being in contact with a side surface of the first insulator and a side surface of the first conductor;a third insulator over the second region, the third insulator being in contact with a side surface of the second insulator; anda second conductor over the second region with the third insulator provided between the second conductor and the second region,wherein a part of the third insulator is positioned between the second conductor and the side surface of the second insulator.2. The semiconductor device according to claim 1 ,wherein the first oxide is over a third conductor, andwherein a bottom surface of the fourth region is in contact with a top surface of the third conductor.3. The ...

Semiconductor Component Arrangement Comprising a Trench Transistor

A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps. 1. A method for producing a semiconductor component arrangement , the method comprising:producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench;producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode; andwherein the gate electrode and the at least one electrode of the electrode structure are produced by common process steps.2. The method of claim 1 , wherein the at least one trench of the transistor structure and the at least one further trench are produced by common process steps.3. The method of claim 1 , further comprising:producing at least one field electrode of the trench transistor structure in the at least one trench; andproducing the electrode structure to comprise at least two electrodes; andwherein the at least two electrodes of the electrode structure and the at least one gate electrode and the at least one field electrode are produced by common process steps.4. The method of claim 1 , wherein the at least one trench of the trench transistor structure and the at least one further trench are produced to have different trench widths.5. The method of claim 1 , wherein prior to producing the at least one gate electrode of the trench transistor structure and prior to producing the at least one electrode of the ...

STRUCTURES FOR TESTING NANOSCALE DEVICES INCLUDING FERROELECTRIC CAPACITORS AND METHODS FOR FORMING THE SAME

A ferroelectric device structure includes an array of ferroelectric capacitors overlying a substrate, first metal interconnect structures electrically connecting each of first electrodes of the array of ferroelectric capacitors to a first metal pad embedded in a dielectric material layer, and second metal interconnect structures electrically connecting each of the second electrodes of the array of ferroelectric capacitors to a second metal pad embedded in the dielectric material layer. The second metal pad may be vertically spaced from the substrate by a same vertical separation distance as the first metal pad is from the substrate. First metal lines laterally extending along a first horizontal direction may electrically connect the first electrodes to the first metal pad, and second metal lines laterally extending along the first horizontal direction may electrically connect each of the second electrodes to the second metal pad. 1. A method of forming a ferroelectric device , comprising:forming an array of ferroelectric capacitors and first metal lines over a substrate, wherein each ferroelectric capacitor in the array of ferroelectric capacitors comprises a vertical stack including a respective first electrode, a respective ferroelectric material plate, and a respective second electrode, and wherein each of the first metal lines is electrically connected to a respective row of first electrodes arranged along a first horizontal direction;forming second metal lines over the array of ferroelectric capacitors, wherein each of the second metal lines is electrically connected to a respective row of second electrodes arranged along the first horizontal direction; andforming a first metal pad and a second metal pad over the array of ferroelectric capacitors, wherein the first metal pad is electrically connected to the first metal lines and the second metal pad is electrically connected to the second metal lines.2. The method of claim 1 , further comprising forming an ...

Integrated device having multiple transistors

An integrated device includes a semiconductor well formed in an epitaxial layer, and a guard ring formed in the epitaxial layer and surrounding the semiconductor well. The semiconductor well and the guard ring include a type of semiconductor different from that of the epitaxial layer. The integrated device also includes an insulating layer formed atop the guard ring, and multiple gate electrodes formed on a top surface of the insulating layer, overlapping the guard ring and surrounding the semiconductor well. The gate electrodes include a first gate electrode and a second gate electrode separated by a gap. An intersecting line between the top surface of the insulating layer and a side wall of the first gate electrode partially overlaps an area that is defined based on an intersecting line between the top surface of the insulating layer and a side wall of the second gate electrode above the guard ring.

SEMICONDUCTOR INTEGRATED DEVICE INCLUDING CAPACITOR AND MEMORY CELL AND METHOD OF FORMING THE SAME

A semiconductor integrated device and a method of forming the same, the semiconductor integrated device includes a substrate, at least one shallow trench isolation, a memory cell device and a poly-insulator-poly capacitor. A capacitor region and a memory cell region are defined on the substrate. The at least one shallow trench isolation is formed in the substrate. The memory cell device is disposed on the at least one shallow trench isolation in the memory cell region and includes a double polysilicon gate. The poly-insulator-poly capacitor is disposed on the at least one shallow trench isolation in the capacitor region, wherein the poly-insulator-poly capacitor directly contacts the at least one shallow trench isolation. 1. A method of forming a semiconductor integrated device , comprising:providing a substrate having a capacitor region and a memory cell region;forming a first polysilicon layer on the substrate;patterning the first polysilicon layer to form a plurality of openings, within the capacitor region and the memory cell region respectively;forming an oxide-nitride-oxide layer on the first polysilicon layer, to fill in each opening in the capacitor region and the memory cell region;forming a second polysilicon layer covered on the oxide-nitride-oxide layer; andpatterning the first polysilicon layer, the oxide-nitride-oxide layer and the second polysilicon layer to simultaneously form a poly-insulator-poly (PIP) capacitor in the capacitor region and a memory cell device in the memory cell region.2. The method of forming the semiconductor integrated device of claim 1 , wherein each of the poly-insulator-poly capacitor and the memory cell device comprises a portion of the second polysilicon layer claim 1 , a portion of the oxide-nitride-oxide layer and a portion of the first polysilicon layer.3. The method of forming the semiconductor integrated device of claim 2 , further comprising:patterning the second polysilicon layer to partially expose the portion of ...

WIRE BONDING BETWEEN ISOLATION CAPACITORS FOR MULTICHIP MODULES

A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

Vertical memory devices

A vertical memory device includes lower circuit patterns, a second substrate, a capacitor, gate electrodes, and a channel. The lower circuit patterns are formed on a first substrate including first, second and third regions. Contact plugs are formed in the second region. Through vias are formed in the third region. The second substrate is formed on the lower circuit patterns. The capacitor is formed on the lower circuit patterns, and includes a first conductor, a dielectric layer structure, and a second conductor. The first conductor is spaced apart from the second substrate at the same height as the second substrate. The dielectric layer structure is formed on the first conductor. The second conductor is formed on the dielectric layer structure. The gate electrodes are spaced apart from each other on the second substrate in a vertical direction. The channel extends through the gate electrodes in the vertical direction.

SEMICONDUCTOR LAYOUT STRUCTURE

A semiconductor layout structure includes multiple active blocks which are disposed on a substrate, parallel with one another and extending along a first direction, multiple first shallow trench isolations which are disposed on a substrate, parallel with one another and respectively disposed on the multiple active blocks, and multiple second shallow trench isolations which are disposed on a substrate, cutting through multiple active blocks and extending along a second direction. The first direction has an angle about 1 degree to about 53 degrees to the second direction. 1. A semiconductor layout structure , comprising:a substrate;a plurality of active blocks, disposed on said substrate, parallel with each other and extending along a first direction;a plurality of first shallow trench isolations, disposed on said substrate, parallel with each other and respectively disposed between said plurality of active blocks; anda plurality of second shallow trench isolations, disposed on said substrate, cutting through said plurality of active blocks and extending along a second direction, wherein said first direction and said second direction have an angle between 1 degree to 53 degrees.2. The semiconductor layout structure of claim 1 , further comprising:a plurality of word lines, disposed on said substrate, parallel with each other and extending along a third direction, wherein said first direction and said third direction have an angle between 30 degrees to 60 degrees.3. The semiconductor layout structure of claim 1 , further comprising:a plurality of bit line contacts, disposed on said substrate, parallel with each other, respectively disposed between said plurality of second shallow trench isolations and extending along said second direction, wherein said plurality of bit line contacts respectively divide said plurality of active blocks into a gate area overlapping said plurality of bit line contacts, as well as a source region and a drain region disposed at both sides of ...

Semiconductor structures with deep trench capacitor and methods of manufacture

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

IC WITH LARGER AND SMALLER WIDTH CONTACTS

An integrated circuit (IC) includes a second metal level located between first and third metal levels, a dielectric layer located over the metal levels, and first, second and third vias within the dielectric layer. The first via traverses the first dielectric layer from a surface of the dielectric layer to the first metal level and has a first diameter. The second via traverses the dielectric layer from the surface to the second metal level and has the first diameter. The third via traverses the dielectric layer from the surface to the third metal level and has a second diameter greater than the first diameter. In some implementations the first, second and third metal levels implement a capacitor. 120-: (canceled)21. A method of fabricating an integrated circuit (IC) , comprising:forming a first via through a first dielectric layer to a first conductive level over a semiconductor substrate, the first via having a first diameter;forming a second via through the first dielectric layer to a second conductive level located over the first conductive level, the second via having the first diameter;forming a third via through the first dielectric layer to a third conductive level located over the second conductive level, the third via having a second diameter different than the first diameter.22. The method of claim 21 , wherein the second conductive level and the third conductive level include top and bottom plates of a capacitor.23. The method of claim 22 , wherein the first conductive level includes circuitry configured to implement a circuit function in cooperation with the capacitor.24. The method of claim 22 , wherein a capacitor dielectric is located between the second and third conductive levels claim 22 , and wherein forming the second via includes removing a portion of the capacitor dielectric.25. The method of claim 24 , wherein the capacitor dielectric comprises a multilayer stack including at least one layer of silicon oxide and at least one layer of silicon ...

Rectifying Devices and Rectifier Arrangements

A rectifying device includes a power transistor, a gate control circuit and a capacitor structure arranged on a single semiconductor die. The power transistor includes a source or emitter terminal connected to a first terminal of the rectifying device, a drain or collector terminal connected to a second terminal of the rectifying device, and a gate. The gate control circuit is operable to control a gate voltage at the gate of the power transistor based on at least one parameter relating to at least one of a voltage and a current between the first terminal and the second terminal. 1. A rectifying device , comprising:a power transistor having a source terminal connected to one of a first terminal and a second terminal of the rectifying device, a drain terminal connected to the other one of the first terminal and the second terminal of the rectifying device and a gate;a gate control circuit operable to control a gate voltage at the gate of the power transistor based on at least one parameter relating to at least one of a voltage and a current between the first terminal and the second terminal; anda capacitor structure,wherein the power transistor, the gate control circuit and the capacitor structure are arranged in a single semiconductor die.2. The rectifying device of claim 1 , wherein the power transistor is a MOSFET.3. The rectifying device of claim 1 , wherein the power transistor is a vertical transistor claim 1 , wherein the source terminal is arranged at a first side of the semiconductor die and the drain terminal is arranged at a second side of the semiconductor die.4. The rectifying device of claim 1 , wherein the power transistor comprises at least one gate trench comprising an insulation and a gate electrode.5. The rectifying device of claim 1 , wherein the capacitor structure comprises at least one capacitor trench in the semiconductor die.6. The rectifying device of claim 5 , wherein the at least one capacitor trench extends vertically from a front side of ...

PACKAGED SEMICONDUCTOR DEVICE

A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals. 118-. (canceled)19. An apparatus , comprising:a multi-layer molded interconnect substrate (MIS) having a signal layer including first and second traces for a first channel and first and second traces for a second channel on a dielectric layer with vias, wherein the first and second traces of the first and second channel include narrowed trace regions and the bottom mend layer comprises a patterned layer including a plurality of ground cut regions.20. The apparatus of claim 19 , further comprising:a first and a second direct current (DC) blocking capacitor in series within the first and second traces of the first channel.21. The apparatus of claim 20 , thither comprising:the first and second DC blocking capacitors each with one plate over One of the ground cuts.22. The apparatus of claim 19 , further comprising:a bottom metal layer under the dielectric layer for providing a ground return path.23. The apparatus of claim 20 , further comprising:a bottom metal layer under the dielectric layer for providing a ground return path.24. The apparatus of claim 21 , further comprising:a bottom metal layer under the dielectric layer ...

SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor substrate; a first transistor provided at an upper surface of the semiconductor substrate; and a first capacitor provided above the first transistor and connected to a gate of the first transistor. A tunnel current is able to flow between the gate and the semiconductor substrate. 1. A semiconductor device , comprising:a semiconductor substrate;a first transistor provided at an upper surface of the semiconductor substrate; anda first capacitor provided above the first transistor and connected to a gate of the first transistor,a tunnel current being able to flow between the gate and the semiconductor substrate.2. The device according to claim 1 , further comprising:a second transistor provided at the upper surface of the semiconductor substrate;a third transistor provided at the upper surface of the semiconductor substrate;a fourth transistor provided at the upper surface of the semiconductor substrate;a second capacitor provided above the second transistor and connected to a gate of the second transistor;a third capacitor provided above the third transistor and connected to a gate of the third transistor;a fourth capacitor provided above the fourth transistor and connected to a gate of the fourth transistor; andan insulating film provided at the upper surface of the semiconductor substrate, the insulating film having an opening formed in the insulating film,a tunnel current being able to flow between the semiconductor substrate and the gate for each of the gates of the first to fourth transistors, the tunnel currents being able to flow via the same opening.3. The device according to claim 1 , wherein the first capacitor is a MINI capacitor.4. A semiconductor device claim 1 , comprising:a semiconductor substrate;a first semiconductor region formed in an upper layer portion of the semiconductor substrate;a diffusion region formed in the upper layer portion of the semiconductor substrate and electrically isolated from the ...

Integrated Circuits with Capacitors

Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric. 1. A device comprising:a plurality of fins disposed on a substrate;an isolation structure disposed on the substrate between the plurality of fins;a dielectric isolation material disposed between the plurality of fins;a first electrode disposed on the isolation structure, wherein the first electrode forms a transistor gate; anda second electrode disposed on the isolation structure, wherein the second electrode forms a source/drain contact, wherein a first portion of the second electrode physically contacts the isolation structure and a second portion of the second electrode physically contacts the dielectric isolation material.2. The device of claim 1 , wherein the dielectric isolation material is further disposed under the isolation structure such that a bottom surface of the isolation structure interfaces with the dielectric isolation material.3. The device of claim 2 , wherein the isolation structure includes:a first hard mask layer defining the bottom surface of the isolation structure and disposed directly on the dielectric isolation material,a first dielectric material layer disposed directly on the first hard mask layer, anda second hard mask layer disposed on the first dielectric material layer.4. The ...

CAPACITOR STRUCTURE

A capacitor structure includes a first metal structure, a second metal structure, and a dielectric material. The second metal structure is disposed below the first metal structure. Each of the first metal structure and the second metal structure includes at least three conductive components. The conductive components have a fish-bone shape. The dielectric material is disposed in a plurality of isolators of the first metal structure, in a plurality of isolators of the second metal structure, and between the first metal structure and the second metal structure. 1. A capacitor structure comprising:a first metal structure;a second metal structure disposed below the first metal structure, wherein each of the first metal structure and the second metal structure comprises at least three conductive components, wherein the conductive components have a fish-bone shape; anda dielectric material disposed in a plurality of isolators of the first metal structure, in a plurality of isolators of the second metal structure, and between the first metal structure and the second metal structure.2. The capacitor structure of claim 1 , wherein the conductive components of the first metal structure comprise sequentially a first conductive component claim 1 , a second conductive component claim 1 , and a third conductive component claim 1 , wherein the conductive components of the second metal structure comprise sequentially a fourth conductive component claim 1 , a fifth conductive component claim 1 , and a sixth conductive component claim 1 , wherein each of the first conductive component claim 1 , the second conductive component claim 1 , the third conductive component claim 1 , the fourth conductive component claim 1 , the fifth conductive component claim 1 , and the sixth conductive component comprises a main branch and a plurality of secondary branches.3. The capacitor structure of claim 2 , wherein the secondary branches of the first conductive component are aligned to the secondary ...

Integrated Circuits with Capacitors

Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.

SEMICONDUCTOR DEVICE

A semiconductor device includes an antenna functioning as a coil, a capacitor electrically connected to the antenna in parallel, a passive element forming a resonance circuit with the antenna and the capacitor by being electrically connected to the antenna and the capacitor in parallel, a first field effect transistor controlling whether the passive element is electrically connected to the antenna and the capacitor in parallel or not, and a memory circuit. The memory circuit includes a second field effect transistor which includes an oxide semiconductor layer where a channel is formed and in which a data signal is input to one of a source and a drain. The gate voltage of the first field effect transistor is set depending on the voltage of the other of the source and the drain of the second field effect transistor. 1. (canceled)2. A semiconductor device comprising:a coil;a capacitor electrically connected to the coil in parallel;a passive element that forms a resonance circuit with the coil and the capacitor by being electrically connected to the coil and the capacitor in parallel;a first transistor capable of controlling whether the passive element is electrically connected to the coil and the capacitor in parallel or not;a memory circuit, wherein the memory circuit includes:a second transistor that comprises a semiconductor layer including a channel, the channel including an oxide semiconductor;a second capacitor; anda third transistor in which a voltage of one of a source and a drain of the third transistor is changed in accordance with an electric wave received by the coil, the other one of the source and the drain of the third transistor is electrically connected to a gate of the first transistor, and a gate of the third transistor is directly connected to one of a source and a drain of the second transistor and one of electrodes of the second capacitor;a second passive element whose first terminal is electrically connected to a first terminal of the coil; anda ...

METHOD FOR FORMING CAPACITOR, SEMICONDUCTOR DEVICE, MODULE, AND ELECTRONIC DEVICE

A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor. 1. A capacitor comprising:a first conductor;a second conductor; andan insulator,wherein the first conductor and the second conductor overlap with each other with the insulator provided therebetween,wherein the first conductor includes tungsten and silicon, andwherein the insulator includes a silicon oxide film that is formed by oxidizing the first conductor.2. A semiconductor device comprising:a transistor; and{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the capacitor according to ,'}wherein the transistor comprises a drain electrode,wherein the capacitor comprises a first electrode and a second electrode, andwherein the first electrode of the capacitor is electrically connected to the drain electrode.3. A module comprising:{'claim-ref': {'@idref': 'CLM-00002', 'claim 2'}, 'the semiconductor device according to ; and'}a printed circuit board.4. An electronic device comprising:{'claim-ref': {'@idref': 'CLM-00003', 'claim 3'}, 'the module according to ; and'}at least one of a speaker and an operation key.5. A capacitor comprising:a first conductor;a second conductor; andan insulator in contact with the first conductor,wherein the first conductor and the second conductor overlap with each other with the insulator provided therebetween,wherein the first ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip. 1. A semiconductor device comprising:a semiconductor chip; [ a source electrode and a drain electrode spaced from each other in a thickness direction of the semiconductor chip; and', 'a gate electrode which controls turning on/off a current flowing between the drain electrode and the source electrode,, 'wherein the power transistor includes, the source electrode being a first electrode;', 'a second electrode facing to the first electrode; and', 'a capacitor insulating film formed between the first electrode and the second electrode,', 'wherein the second electrode is electrically coupled with the drain electrode,, 'wherein the capacitor element includes, 'wherein a gate pad electrically coupled with the gate electrode, the source electrode, and the second electrode is formed over a main surface of the semiconductor chip, and', 'wherein, in a plan view, over the main surface of the semiconductor chip, a second electrode exposure region, where the second electrode is exposed, and a source electrode exposure region, where the source electrode is exposed, are formed, and the gate pad is exposed., 'a power transistor and a capacitor element electrically coupled with the power transistor formed on the semiconductor chip,'}2. The semiconductor device according to ...

Cell-based ic layout system and cell-based ic layout method

A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal layers. The decoupling capacitor cell is arranged in an unused region not occupied by basic cells in a cell-based IC and is connected to a power wiring and a ground wiring.

Semiconductor device

A semiconductor device includes a semiconductor substrate including a connection region, a pair of epitaxial patterns provided at the semiconductor substrate, a capacitor disposed between the pair of epitaxial patterns, a middle connection layer on the capacitor, an interconnection layer on the middle connection layer, and a through-via provided under the interconnection layer and penetrating the connection region of the semiconductor substrate. The capacitor includes an upper portion of the semiconductor substrate between the pair of epitaxial patterns, a metal electrode on the upper portion of the semiconductor substrate, and a dielectric pattern disposed between the upper portion of the semiconductor substrate and the metal electrode. The through-via is connected to the capacitor through the interconnection layer and the middle connection layer.

Semiconductor device and method of forming the same

A semiconductor device includes a substrate and an isolation feature. The isolation feature includes a first portion in the substrate, and a second portion extending along a top surface of the substrate, wherein a bottom surface of the second portion is below the top surface of the substrate. The semiconductor device further includes a gate structure over the substrate, wherein the gate structure extends along a top surface of the second portion of the isolation feature.

TRENCH BASED CHARGE PUMP DEVICE

A semiconductor device is provided including a fully depleted silicon-on-insulator (FDSOI) substrate and a charge pump device, wherein the FDSOI substrate comprises a semiconductor bulk substrate, and the charge pump device comprises a transistor device formed in and on the FDSOI substrate, and a trench capacitor formed in the semiconductor bulk substrate and electrically connected to the transistor device. A semiconductor device is further provided including a semiconductor bulk substrate, a first transistor device comprising a first source/drain region, a second transistor device comprising a second source/drain region, a first trench capacitor comprising a first inner capacitor electrode and a first outer capacitor electrode, and a second trench capacitor comprising a second inner capacitor electrode and a second outer capacitor electrode, wherein the first inner capacitor electrode is connected to the first source/drain region and the second inner capacitor electrode is connected to the second source/drain region. 1. A semiconductor device comprising a fully depleted silicon-on-insulator (FDSOI) substrate and a charge pump device , wherein:said FDSOI substrate comprises a semiconductor bulk substrate; and a transistor device formed in and on said FDSOI substrate; and', 'a trench capacitor formed in said semiconductor bulk substrate and electrically connected to said transistor device., 'said charge pump device comprises2. A semiconductor device , comprising:a semiconductor bulk substrate;a first transistor device comprising a first source/drain region;a second transistor device comprising a second source/drain region;a first trench capacitor comprising a first inner capacitor electrode and a first outer capacitor electrode; anda second trench capacitor comprising a second inner capacitor electrode and a second outer capacitor electrode;wherein said first inner capacitor electrode is connected to said first source/drain region and said second inner capacitor ...

METHOD OF MAKING A SEMICONDUCTOR DEVICE

A method of making a semiconductor device includes etching a substrate to define a trench in a substrate, wherein the trench is adjacent to an active region in the substrate, and etching the substrate includes patterning a mask. The method further includes partially removing the mask to expose a first portion of the active region, wherein the first portion extends a first distance from the trench. The method further includes depositing a dielectric material to fill the trench and cover the first portion of the active region. The method further includes removing the mask, wherein the removing of the mask includes maintaining the dielectric material covering the first portion of the active region. The method further includes forming a gate structure over the active region and over the dielectric material. 1. A method of making a semiconductor device , the method comprising:etching a substrate to define a trench in a substrate, wherein the trench is adjacent to an active region in the substrate, and etching the substrate comprises patterning a mask;partially removing the mask to expose a first portion of the active region, wherein the first portion extends a first distance from the trench;depositing a dielectric material to fill the trench and cover the first portion of the active region;removing the mask, wherein the removing of the mask comprises maintaining the dielectric material covering the first portion of the active region; andforming a gate structure over the active region and over the dielectric material.25. The method of claim 1 , wherein the partially removing of the mask comprises exposing the first portion extending greater than nanometers (nm) over the active region.3. The method of claim 1 , wherein the partially removing the mask comprises exposing a top surface of the substrate on an opposite side of the trench from the active region.4. The method of claim 1 , further comprising implanting a non-dopant material into the active region and the substrate ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip. 1. A semiconductor device comprising:a semiconductor substrate having a first main surface and a second main surface opposing to the first main surface;a trench formed in the first main surface;a gate insulating film formed on an inner surface of the trench;a gate electrode formed on the gate insulating film to fill in the trench;a channel region formed in the first main surface at a side of the trench;a source region formed in the channel region at the side of the trench;a drift layer formed in the semiconductor substrate under the channel region;a drain region formed in the second main surface and under the drift layer;a drain electrode formed on the second main surface and in contact with the drain region, the gate electrode, the channel region, the source region and the drain region serving as a vertical type MOSFET; anda capacitor element formed on the first main surface to stack over the vertical type MOSFET, the capacitor element including a first electrode electrically coupled to the source region, a second electrode electrically coupled to the drain region and an insulating film formed between the first and second electrodes,wherein the vertical type MOSFET and the capacitor element are disposed in an active region of the semiconductor substrate in a ...

SEMICONDUCTOR DEVICE

An object is to provide a semiconductor device which can store data even after the application of power supply voltage is stopped, a manufacturing method thereof, or a driving method thereof. Data stored in a first circuit portion is transmitted to a second circuit portion, the data is stored in the second circuit portion in a period during which the application of power supply voltage is stopped, and data corresponding to the data is transmitted to the first circuit portion at the time of applying power supply voltage again. With such a configuration, a semiconductor device can store data even in a period during which the application of the power supply voltage is stopped. In particular, the second circuit portion includes a transistor including an oxide semiconductor, whereby the data can be accurately stored. 1. A semiconductor device comprising:a first circuit portion comprising a first node and a second node; anda second circuit portion comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor,wherein a gate of the second transistor and a first electrode of the first capacitor are electrically connected to the first node through the first transistor,wherein a gate of the fifth transistor and a first electrode of the second capacitor are electrically connected to the second node through the fourth transistor,wherein one of a source and a drain of the second transistor is electrically connected to the second node through the third transistor,wherein one of a source and a drain of the fifth transistor is electrically connected to the first node through the sixth transistor, andwherein the first transistor and the fourth transistor each include an oxide semiconductor including indium in a channel formation region.2. The semiconductor device according to claim 1 , wherein the first circuit portion includes an even number of inverter circuits ...

SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins. 1. A method , comprising:forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate;simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate;forming an insulator layer on the polysilicon fins; andforming gate structures over the SOI fins and the insulator layer on the polysilicon fins.2. The method of claim 1 , wherein the polysilicon fins and the SOI fins are formed in contact with one another claim 1 , in the same processing step.3. The method of claim 1 , wherein the SOI fins are formed by a sidewall image transfer process.4. The method of claim 1 , wherein the insulator layer is oxide material blanket deposited on the polysilicon fins and the SOI fins claim 1 , and subsequently removed from the SOI fins prior to formation of the gate structures.5. The method of claim 1 , further comprising forming an epitaxial material over a connection between the polysilicon fins and the SOI fins.6. The method of claim 5 , wherein the connection is provided by material of the polysilicon fins and semiconductor material of the SOI fins.7. The method of claim 6 , wherein the forming of the epitaxial material comprises growing semiconductor material over exposed sidewalls of the polysilicon fins and semiconductor material of the SOI fins.8. The method of claim 7 , wherein the semiconductor material is silicon.9. The method of ...

INTERDIGITATED CAPACITOR TO INTEGRATE WITH FLASH MEMORY

Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate including a flash memory region and a capacitor region. A flash memory cell is arranged over the flash memory region and includes a polysilicon select gate arranged between first and second source/drain regions of the flash memory cell. The flash memory cell also includes a control gate arranged alongside the select gate and separated from the select gate by a control gate dielectric layer. A capacitor is arranged over the capacitor region and includes: a polysilicon first capacitor plate and polysilicon second capacitor plate, which are inter-digitated with one another and separated from one another by a capacitor dielectric layer. The capacitor dielectric layer and control gate dielectric layer are made of the same material. 1. An integrated circuit (IC) , comprising:a semiconductor substrate including a flash memory region and a capacitor region;a flash memory cell arranged over the flash memory region and including: a polysilicon select gate arranged between first and second source/drain regions of the flash memory cell, and a control gate arranged alongside the select gate and separated from the select gate by a control gate dielectric layer; anda capacitor arranged over the capacitor region and including: a polysilicon first capacitor plate and polysilicon second capacitor plate, which are inter-digitated with one another and have sidewalls separated from one another by a capacitor dielectric layer, wherein the capacitor dielectric layer and control gate dielectric layer are made of the same material.2. The IC of claim 1 , wherein the capacitor dielectric layer and control gate dielectric layer each comprise a charge trapping layer sandwiched between first and second dielectric layers.3. The IC of claim 1 , wherein the capacitor dielectric layer and control gate dielectric layer each comprise a tunnel dielectric layer claim 1 , a capping dielectric layer claim 1 , ...

Semiconductor device and method of manufacturing the same

Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Apparatuses Having Memory Cells with Two Transistors and One Capacitor, and Having Body Regions of the Transistors Coupled with Reference Voltages

Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another. 120-. (canceled)21. An apparatus , comprising:a memory cell comprising two transistors and one capacitor;the two transistors being a first transistor and a second transistor, the first transistor spaced in a lateral direction from the second transistor, the first transistor comprising a body region;the capacitor having a first node coupled with a source/drain region of the first transistor and having a second node coupled with a source/drain region of the second transistor; anda body connection line coupling the body region of the first transistor to a conductive region having a first reference voltage.22. The apparatus of wherein the first reference voltage comprises a ground voltage.23. The apparatus of wherein the body connection line comprises a length dimension that extends perpendicularly to the lateral direction.24. The apparatus of wherein the second transistor comprises a body region claim 21 , and further comprising:a body connection line coupling the body region of the second transistor to a conductive region having a second reference voltage, the first and second reference voltages are the same reference voltage.25. The apparatus of ...

Wire bonding between isolation capacitors for multichip modules

A packaged multichip device includes a first IC die with an isolation capacitor utilizing a top metal layer as its top plate and a lower metal layer as its bottom plate. A second IC die has a second isolation capacitor utilizing its top metal layer as its top plate and a lower metal layer as its bottom plate. A first bondwire end is coupled to one top plate and a second bondwire end is coupled to the other top plate. The second bondwire end includes a stitch bond including a wire approach angle not normal to the top plate it is bonded to and is placed so that the stitch bond's center is positioned at least 5% further from an edge of this top plate on a bondwire crossover side compared to a distance of the stitch bond's center from the side opposite the bondwire crossover side.

SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins. 1. A structure , comprising:a plurality of deep trench capacitors formed in a silicon on insulator (SOI) substrate, each of the plurality of deep trench capacitors having a fin structure including epitaxial material comprising semiconductor material over exposed sidewalls of fin structures and semiconductor material of SOI fins each of which have ends in contact with respective fin structures of the deep trench capacitors.2. The structure of claim 1 , wherein the epitaxial material is on ends of the SOI fins and ends of the fin structures of the deep trench capacitors3. The structure of claim 1 , wherein the semiconductor material is silicon.4. The structure of claim 1 , wherein the fin structures are polysilicon fins formed in contact with the SOI fins claim 1 , and ends of the SOI fins are connected to respective polysilicon fins.5. The structure of claim 1 , wherein the ends of the SOI fins contact ends of the fin structures of the deep trench capacitors in a longitudinal direction.6. The structure of claim 5 , wherein the epitaxial material comprises silicon at a depth of about 15 nm to 25 nm to reduce strap resistance and make a robust connection between the plurality of SOI fins and the respective fin structures of the deep trench capacitors.7. The structure of claim 1 , further comprising a gate structure extending over an insulator material and the SOI fins claim 1 , the gate structure comprises a gate ...

Method for forming capacitor, semiconductor device, module, and electronic device

A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor.

Semiconductor structures with deep trench capacitor and methods of manufacture

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

In an interlayer insulating film in which contact plugs are embedded, a capacitor element is formed which has electrodes each formed of a metal. Over a substrate, the interlayer insulating film is formed. The interlayer insulating film includes a first insulating film and a second insulating film. In the second insulating film, the first and second contact plugs are formed. The first and second contact plugs extend through the second insulating film to reach first and second gate electrodes. In a surface of the substrate, an isolation film is formed. Within a region overlapping the isolation film in planar view, the capacitor element is formed. The capacitor element includes the lower and upper electrodes. Each of the lower and upper electrodes contains a metal. The lower and upper electrodes of the capacitor element are formed over the first insulating film to be embedded in the second insulating film. 1. A semiconductor device , comprising:a first transistor formed over a substrate;a second transistor formed over the substrate and having a channel of a conductivity type different from that of a channel of the first transistor; andan interlayer insulating film formed over the substrate to cover the first transistor and the second transistor, a first gate electrode formed over the substrate and containing a metal; and', 'a first source/drain region formed in a surface of the substrate in lateral relation to the first gate electrode,, 'wherein the first transistor includes a second gate electrode formed over the substrate and containing a metal; and', 'a second source/drain region formed in the surface of the substrate in lateral relation to the second gate electrode, and, 'wherein the second transistor includes a first insulating film formed over the first source/drain region and the second source/drain region; and', 'a second insulating film formed over the first insulating film,, 'wherein the interlayer insulating film includesthe semiconductor device further ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

A semiconductor device includes a substrate, wherein the substrate includes a channel region. The semiconductor device further includes an isolation feature in the substrate. The isolation feature includes a first portion in the substrate, and a second portion extending along a top surface of the substrate. The second portion partially covers the channel region. The semiconductor device further includes a gate structure over the substrate, wherein the gate structure partially covers the second portion of the isolation feature. 1. A semiconductor device comprising:a substrate, wherein the substrate includes a channel region; a first portion in the substrate, and', 'a second portion extending along a top surface of the substrate, wherein the second portion partially covers the channel region; and, 'an isolation feature in the substrate, wherein the isolation feature comprisesa gate structure over the substrate, wherein the gate structure partially covers the second portion of the isolation feature.2. The semiconductor device of claim 1 , wherein a length of the channel region covered by the second portion is greater than about 5 nanometers (nm).3. The semiconductor device of claim 1 , wherein the channel region directly contacts the first portion.4. The semiconductor device of claim 1 , wherein the gate structure comprises a gate electrode claim 1 , and a thickness of the gate electrode over the second portion is less than a thickness of the gate electrode over a portion of the channel region exposed by the second portion.5. The semiconductor device of claim 1 , wherein the gate structure comprises a dielectric layer claim 1 , and the dielectric layer extends over the second portion.6. The semiconductor device of claim 1 , wherein the first portion is integral with the second portion.7. The semiconductor device of claim 1 , further comprising an implant contact in the substrate claim 1 , wherein the first portion is between the implant contact and the channel region.8 ...

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

A semiconductor device includes a semiconductor substrate including a pad region and a peripheral region, a first buffer layer formed to include a capacitor over the semiconductor substrate in the pad region, a second buffer layer formed to include a first contact pad over the first buffer layer, and a third buffer layer formed to include a second contact pad over the first contact pad. The semiconductor device, by additionally forming a buffer layer at a lower part in the pad region, reduces a stress caused by wire bonding. Thus, an applied stress to a lower structure in the pad region is also reduced. As a result, the buffer layer prevents formation of an electrical bridge between the pad region and the peripheral region. 1. A semiconductor device comprising:a semiconductor substrate including a pad region and a peripheral region;a first buffer layer formed to include a capacitor over the semiconductor substrate in the pad region;a second buffer layer formed to include a first contact pad over the first buffer layer; anda third buffer layer formed to include a second contact pad over the first contact pad.2. The semiconductor device according to claim 1 , further comprising:a metal-oxide-semiconductor (MOS) transistor formed below the first buffer layer, and formed over the semiconductor substrate in the pad region and the peripheral region.3. The semiconductor device according to claim 2 , wherein the MOS transistor includes a laminate structure of a polysilicon layer claim 2 , a metal layer claim 2 , and a hard mask layer.4. The semiconductor device according to claim 2 , further comprising:a first metal line formed over the MOS transistor.5. The semiconductor device according to claim 4 , further comprising:a first metal contact formed over the first metal line in the peripheral region.6. The semiconductor device according to claim 4 , wherein the first buffer structure is formed over the first metal line.7. The semiconductor device according to claim 1 , ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. A first control electrode is on the first semiconductor layer with a first insulating layer between the first control electrode and the first semiconductor layer. A second control electrode is on the first semiconductor layer with a second insulating layer between the second control electrode and the first semiconductor layer, a distance between the first control electrode and the first semiconductor layer is less than a distance between the second control electrode. A wiring electrically connects the first control electrode and the second control electrode. 1. A semiconductor device , comprising:a first semiconductor layer;a second semiconductor layer on a first portion of the first semiconductor layer;a first control electrode on a second portion of the first semiconductor layer, a first insulating layer being between the first control electrode and second portion of the first semiconductor layer in a first direction;a second control electrode on the second portion of the first semiconductor layer and spaced from the first control electrode in a second direction perpendicular to the first direction, a second insulating layer being between the second control electrode and the second portion of the first semiconductor layer; anda wiring that electrically connects the first control electrode and the second control electrode, whereina distance in the first direction between the second control electrode and the first semiconductor layer is greater than a distance in the first direction between the first control electrode and the first semiconductor layer.2. The semiconductor device according to claim 1 , wherein the first insulating layer directly contacts the first semiconductor layer.3. The semiconductor device according to claim 1 , wherein a portion of the second semiconductor layer is between the first insulating layer and the first ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a memory cell transistor in which a first insulation film, a first conductive layer, a second insulation film, and a second conductive layer are sequentially stacked on a semiconductor substrate, and a peripheral circuit element in which a third insulation film, a third conductive layer, a fourth insulation film, a fourth conductive layer are sequentially stacked on the semiconductor substrate and which has a contact electrically connected to the third conductive layer. In the semiconductor substrate, a recess is formed at least in a region immediately below the contact. The third conductive layer is also formed within the recess, and a film thickness of the third conductive layer in the recess is thicker than a film thickness of the first conductive layer. 1. A semiconductor device comprising:a memory cell transistor in which a first insulation film, a first conductive layer, a second insulation film, and a second conductive layer are sequentially stacked on a semiconductor substrate; anda peripheral circuit element in which a third insulation film, a third conductive layer, a fourth insulation film, a fourth conductive layer are sequentially stacked on the semiconductor substrate and which has a contact electrically connected to the third conductive layer,wherein in the semiconductor substrate, a recess is formed at least in a region immediately below the contact,wherein the third conductive layer is also formed within the recess, andwherein a film thickness of the third conductive layer in the recess is thicker than a film thickness of the first conductive layer.2. The semiconductor device according to claim 1 ,wherein a position of a lower end of the contact of the peripheral circuit element is located at a position lower than an upper surface of the portion of the semiconductor substrate in which the memory cell transistor is formed above the semiconductor substrate.3. The semiconductor device according to claim 1 ,wherein the ...

CONTACT WINDOW STRUCTURE, PIXEL STRUCTURE AND METHOD FOR MANUFACTURING THEREOF

The present disclosure provides a contact window structure. In the contact window structure, a first insulating layer, having a first opening, is positioned on a first metal layer, wherein the first opening exposes a part of the first metal layer. A second metal layer covers the first opening and contacts with the first metal layer via the first opening. A second insulating layer, having a second opening, is positioned on the first insulating layer, wherein the second opening exposes a part of the second layer and the first insulating layer. The projection area of the second opening on the first metal layer covers the projection area of the first opening on the first metal layer. A pixel structure containing the contact window structure and a manufacturing method thereof are also provided herein. 1. A contact window structure comprising:a first metal layer positioned on a substrate;a first insulating layer positioned on the first metal layer, wherein the first insulating layer has a first opening, and the first opening exposes a part of the first metal layer;a second metal layer covering the first opening and in contact with the first metal layer via the first opening;a second insulating layer positioned on the first insulating layer, wherein the second insulating layer has a second opening, the second opening exposes the second metal layer and a part of the first insulating layer, and a projection area of the second opening on the first metal layer covers a projection area of the first opening on the first metal layer; anda third metal layer covering the second insulating layer and the second opening, and in contact with the second metal layer via the second opening.2. The contact window structure of claim 1 , wherein the first opening has a first width and the second opening has a second width along a first direction of the substrate claim 1 , and the second width is greater than the first width.3. The contact window structure of claim 2 , wherein a ratio of the ...

POWER MOSFETS AND METHODS FOR MANUFACTURING THE SAME

A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate. 1. A semiconductor device , comprising:a substrate;a field plate over the substrate;a gate electrode having a first portion and a second portion, wherein the first portion of the gate electrode is located over the field plate; anda first dielectric between the first portion of the gate electrode and the field plate.2. The semiconductor device of claim 1 , further comprising a first spacer laterally surrounding the first dielectric.3. The semiconductor device of claim 3 , further comprising a second dielectric underlying the first dielectric and the first spacer.4. The semiconductor device of claim 1 , further comprising a second spacer laterally surrounding the gate electrode.5. The semiconductor device of claim 4 , wherein the second spacer further laterally surrounding the first spacer.6. The semiconductor device of claim 1 , further comprising a third dielectric laterally abutting the second dielectric.7. The semiconductor device of claim 1 , wherein the second portion of the gate electrode is directly over the third dielectric.8. A semiconductor device claim 1 , comprising:a substrate having a top surface;a field plate over the substrate;a gate electrode having a first portion and a second portion, wherein the first portion of the gate electrode is located over the field plate; anda first dielectric between the substrate and the field plate;an inner spacer on the top surface of the first ...

Monolithic microwave integrated circuit (mmic) cascode connected transistor circuit

A cascode transistor circuit having an active region, the active region having a source, a drain, a floating source/drain, a first gate disposed between the source and the floating source/drain and a second gate disposed between the floating source/drain and the drain. A first gate pad is displaced from the active region and is electrically connected to the first gate and a second gate pad is displaced from the active region and is electrically connected to the second gate. The first and the second gate pads are disposed on opposite sides of the active region.

RF SWITCHES, INTEGRATED CIRCUITS, AND DEVICES WITH MULTI-GATE FIELD EFFECT TRANSISTORS AND VOLTAGE LEVELING CIRCUITS, AND METHODS OF THEIR FABRICATION

Embodiments of field effect transistor (FET) circuits, RF switches, and devices include source and drain terminals coupled to an active surface of a semiconductor substrate, a channel in the substrate between the source and drain terminals, and a plurality of gate structures coupled to the active surface over the channel. A channel contact is coupled to the active surface over the channel between a pair of the gate structures. A first capacitor is electrically coupled between the channel contact and the source terminal, and a second capacitor is electrically coupled between the channel contact and the drain terminal. 1. A method of fabricating a field effect transistor (FET) circuit , the method comprising: coupling a source terminal to the active surface,', 'coupling a drain terminal to the active surface, wherein a multi-gate FET channel is present in the semiconductor substrate between the source and drain terminals, and', 'coupling a plurality of gate structures to the active surface over the multi-gate FET channel;, 'forming a FET in and over an active surface of a semiconductor substrate by'}coupling a first channel contact to the active surface over the multi-gate FET channel between a first pair of gate structures of the plurality of gate structures;electrically coupling a first capacitor between the first channel contact and the source terminal; andelectrically coupling a second capacitor between the first channel contact and the drain terminal.2. The method of claim 1 , wherein:forming the FET further comprises coupling a second channel contact to the active surface between a second pair of gate structures of the plurality of gate structures, and the method further comprises:electrically coupling a third capacitor between the first and second channel contacts.3. The method of claim 1 , further comprising:electrically coupling a third capacitor between the first channel contact and a gate structure of the plurality of gate structures.4. The method of claim ...

METHOD FOR FORMING CAPACITOR, SEMICONDUCTOR DEVICE, MODULE, AND ELECTRONIC DEVICE

A miniaturized transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A transistor having a large amount of on-state current is provided. A semiconductor device including the transistor is provided. A semiconductor device with high integration is provided. A novel capacitor is provided. The capacitor includes a first conductor, a second conductor, and an insulator. The first conductor includes a region overlapping with the second conductor with the insulator provided therebetween. The first conductor includes tungsten and silicon. The insulator includes a silicon oxide film that is formed by oxidizing the first conductor. 1. A capacitor comprising:a first conductor;a second conductor; andan insulator,wherein the first conductor and the second conductor overlap with each other with the insulator provided therebetween,wherein the first conductor includes tungsten and silicon, andwherein the insulator includes a silicon oxide film that is formed by oxidizing the first conductor.2. A semiconductor device comprising:a transistor; and{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the capacitor according to ,'}wherein the transistor comprises a drain electrode,wherein the capacitor comprises a first electrode and a second electrode, andwherein the first electrode of the capacitor is electrically connected to the drain electrode.3. A module comprising:{'claim-ref': {'@idref': 'CLM-00002', 'claim 2'}, 'the semiconductor device according to ; and'}a printed circuit board.4. An electronic device comprising:{'claim-ref': {'@idref': 'CLM-00003', 'claim 3'}, 'the module according to ; and'}at least one of a speaker and an operation key.5. A capacitor comprising:a first conductor;a second conductor; andan insulator in contact with the first conductor,wherein the first conductor and the second conductor overlap with each other with the insulator provided therebetween,wherein the first ...

COINTEGRATION OF FET DEVICES WITH DECOUPLING CAPACITOR

A semiconductor structure includes a decoupling capacitor on a semiconductor substrate. The decoupling capacitor includes a multilayer stack structure having one or more active regions on a top surface thereof. The semiconductor structure further includes one or more semiconductor devices on the one or more active regions on the decoupling capacitor. 1. A method for fabricating a semiconductor structure comprising:forming a decoupling capacitor on a semiconductor substrate, wherein the decoupling capacitor has an active region on a top surface thereof and wherein the decoupling capacitor comprises a multilayer stack structure; andforming one or more semiconductor devices on the active region on the top surface of the decoupling capacitor;wherein the step of forming the decoupling capacitor comprises forming the multilayer stack structure on the semiconductor substrate comprising:forming alternating layers of a first semiconductor material and a second semiconductor material, wherein the first semiconductor material is formed on the semiconductor substrate and is a top layer of the alternating layers;forming the active region comprising a semiconductor layer of a third semiconductor material on the top layer of the alternating layers;forming a hard mask on the active region;forming a central portion, a first outer portion and a second outer portion in the multilayer stack structure, wherein each of the central portion, the first outer portion and the second outer portion comprises a respective first opening, a second opening and a third opening through the hard mask, the active region, the alternating layers and a portion of the semiconductor substrate; anddepositing a fourth semiconductor material in each of the respective first opening, second opening and third opening through the hard mask.2. (canceled)3. The method of claim 1 , wherein the step of forming the decoupling capacitor further comprises:selectively removing the fourth semiconductor material in the ...

SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE

An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins. 1. A structure , comprising:a plurality of deep trench capacitors having a fin structure;a plurality of silicon on insulator (all) fins each of which have ends in contact with respective fin structures of the deep trench capacitors; andan epitaxial material over a connection between the fin structures and the SOI fins,wherein the epitaxial material comprises semiconductor material over exposed sidewalls of the fin structures and semiconductor material of the SOI fins, andthe semiconductor material of the epitaxial material comprises silicon at a predetermined depth to reduce strap resistance and to make the connection between the plurality of SOI fins and the fin structures of the deep trench capacitors.2. The structure of claim 1 , wherein the deep trench capacitors are eDRAM structures.3. The structure of claim 1 , wherein the SOI fins comprise portions of FinFETs.4. The structure of claim 1 , wherein the fin structures are polysilicon fins formed in contact with the SOI fins claim 1 , and an oxide material blanket is deposited on the polysilicon fins.5. The structure of claim 4 , wherein the oxide material is SiOat a depth of about 3 nm to 6 nm to provide protection to the SOI fins from shorting with a conductive material.6. The structure of claim 5 , further comprising a gate structure extending over the SOI fins and extends over the oxide material.7. The structure of claim 6 , wherein the SOI fins include a ...

PRECISION TRENCH CAPACITOR

A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection. 2. The capacitor structure of claim 1 , wherein said programmable electrical switching device comprises a field effect transistor claim 1 , and said capacitor structure further comprises a contiguous metal semiconductor alloy structure that contain at least:a trench top metal semiconductor alloy portion overlying said inner electrode of said trench capacitor; anda source-side metal semiconductor alloy portion contacting a source region of said field effect transistor.3. The capacitor structure of claim 1 , wherein said programmable electrical switching device comprises a field effect transistor claim 1 , and said first node of said capacitor structure is electrically shorted to a drain region of said field effect transistor only through a set of metal interconnect structures.4. The capacitor structure of claim 1 , wherein said programmable electrical switching device comprises a series connection of an electrically programmable fuse structure and a field effect transistor claim 1 , wherein said electrically programmable fuse is electrically shorted to said inner electrode of said trench capacitor claim 1 , and a drain region of said field effect transistor is electrically shorted to said first node of said ...

VERTICAL FETS WITH HIGH DENSITY CAPACITOR

A technique relates to semiconductors. A bottom terminal of a transistor and bottom plate of a capacitor are positioned on the substrate. A spacer is arranged on the bottom terminal of the transistor. A transistor channel region extends vertically from the bottom terminal through the spacer to contact a top terminal of the transistor. A capacitor channel region extends vertically from the bottom plate to contact a top plate of the capacitor. A first gate stack is arranged along sidewalls of the transistor channel region and is in contact with the spacer. A second gate stack is arranged along sidewalls of the capacitor channel region and is disposed on the bottom plate. A distance from a bottom of the first gate stack to a top of the bottom terminal is greater than a distance from a bottom of the second gate stack to a top of the bottom plate. 1. A semiconductor device comprising:a transistor extending vertically from a substrate, the transistor comprising a bottom terminal positioned on the substrate, a first gate stack, and a top terminal; anda capacitor extending vertically from the substrate, the capacitor comprising a bottom plate positioned on the substrate, a second gate stack, and a top plate.2. The device of claim 1 , wherein a spacer is arranged on the bottom terminal of the transistor.3. The device of claim 1 , wherein the transistor comprises a transistor channel region.4. The device of claim 1 , wherein the capacitor comprises a capacitor channel region.5. The device of claim 1 , wherein the first gate stack includes a dielectric material.6. The device of claim 1 , wherein the second gate stack includes a dielectric material.7. The device of claim 3 , wherein the transistor channel region of the transistor is doped.8. The device of claim 3 , wherein the transistor channel region is a semiconductor material.9. The device of claim 4 , wherein the capacitor channel region of the capacitor is doped.10. The device of claim 4 , wherein the capacitor channel ...

POWER MOSFETS STRUCTURE

A semiconductor device is provided. The semiconductor device includes a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate. 1. A semiconductor device , comprising:a substrate;a drain region of a first conductive type located in proximity to a first surface of the substrate;a field plate over the substrate and free from overlapping with the drain region; anda first spacer on the substrate and adjacent to the field plate, a side of the first spacer aligning with a boundary of the drain region.2. The semiconductor device of claim 1 , further comprising a gate electrode having a first portion and a second portion claim 1 , wherein the first portion of the gate electrode is located over the field plate.3. The semiconductor device of claim 2 , further comprising:a first drift region with a first conductivity type, extending from the first surface of the substrate into the substrate; anda second drift region with a first conductivity type, extending from the first surface of the substrate into the substrate and adjacent to the first drift region;wherein the drain region of the first conductivity type is within the first drift region.4. The semiconductor device of claim 3 , wherein the field plate overlaps with a boundary of the first drift region and the second drift region in the substrate.5. The semiconductor device of claim 2 , further comprising:a dielectric layer between the first portion of the gate electrode and the field plate; and a second spacer in contact with a first side of the dielectric layer and the first spacer;wherein a top surface the second spacer is ...

Semiconductor Component Arrangement Comprising a Trench Transistor

A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps.

Low noise device and method of forming the same

A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate. The gate stack includes a gate dielectric layer extending over a portion of the isolation feature, and a gate electrode over the gate dielectric layer. The low noise device further includes a charge trapping reducing structure adjacent to the isolation feature. The charge trapping reducing structure is configured to reduce a number of charge carriers adjacent an interface between the isolation feature and the channel.

Structure with Embedded Memory Device and Contact Isolation Scheme

The present disclosure provides an integrated circuit (IC) structure that includes a fin active region on a substrate; a metal gate stack on the fin active region; a source and a drain on the fin active region, wherein the metal gate stack spans from the source to the drain; an interlayer dielectric (ILD) layer disposed on the source and the drain; a first conductive feature and a second conductive feature formed in the ILD layer and being aligned on the source and the drain, respectively; and a dielectric material layer surrounding the first and second conductive features. The dielectric material layer continuously extends to a bottom surface of the first conductive feature and isolates the first conductive feature from the source and the second conductive feature contacts the drain.

Hybrid High and Low Stress Oxide Embedded Capacitor Dielectric

An electronic device, e.g. integrated circuit, has top and bottom metal plates located over a substrate, the bottom plate located between the top plate and the substrate. A high-stress silicon dioxide layer is located between the bottom plate and the substrate. At least one low-stress silicon dioxide layer is located between the top plate and the bottom plate. 1. An integrated circuit , comprising:a metal top plate located over a substrate;a metal bottom plate located between the top plate and the substrate;a high-stress silicon dioxide layer located between the bottom plate and the substrate; andat least one low-stress silicon dioxide layer located between the top plate and the bottom plate.2. The integrated circuit of claim 1 , wherein the high-stress silicon dioxide layer and the low-stress silicon dioxide layer are formed using a PE-TEOS process.3. The integrated circuit of claim 1 , further comprising a metal guard ring surrounding the top plate and the bottom plate.4. The integrated circuit of claim 3 , further comprising a transistor formed over the substrate claim 3 , the guard ring located between the transistor and the bottom plate.5. The integrated circuit of claim 1 , wherein the at least one low-stress silicon dioxide layer includes a first PE-TEOS layer claim 1 , and further comprising an HDP oxide layer between and touching the first PE-TEOS layer and a second PE-TEOS layer.6. The integrated circuit of claim 5 , wherein a first IMD level includes the first PE-TEOS layer and the HDP oxide layer claim 5 , and the at least one low-stress silicon dioxide layer includes a third PE-TEOS layer claim 5 , and further comprising a second IMD level including the third PE-TEOS layer and a second HDP oxide layer claim 5 , the second IMD level located between the first IMD level and the top plate.7. The integrated circuit of claim 1 , wherein the at least one low-stress silicon dioxide layer is one of a plurality of low-stress silicon dioxide layers located between ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a channel structure, a dielectric structure, a gate structure, a first conductive structure, and a second conductive structure. The channel structure has a top surface, a bottom surface, and a sidewall extending from the top surface to the bottom surface. The first conductive structure is disposed on the bottom surface of the channel structure and includes a body portion and at least one convex portion, and a top surface of the convex portion is higher than a top surface of the body portion. The second conductive structure is disposed on the top surface of the channel structure and includes a body portion and at least one convex portion, and a bottom surface of the body portion is higher than a bottom surface of the convex portion. 1. A semiconductor device , comprising:a channel structure having a top surface, a bottom surface, and a sidewall extending from the top surface to the bottom surface;a dielectric structure surrounding the sidewall of the channel structure;a gate structure surrounding the dielectric structure;a first conductive structure disposed on the bottom surface of the channel structure, wherein the first conductive structure comprises a body portion and at least one convex portion, and a top surface of the convex portion of the first conductive structure is higher than a top surface of the body portion of the first conductive structure; anda second conductive structure disposed on the top surface of the channel structure, wherein the second conductive structure comprises a body portion and at least one convex portion, and a bottom surface of the body portion of the second conductive structure is higher than a bottom surface of the convex portion of the second conductive structure.2. The semiconductor device of claim 1 , further comprising:a first isolation structure surrounding a portion of the body portion of the first conductive structure; anda second isolation structure surrounding a portion of the body portion of ...

SINGLE-MASK, HIGH-Q PERFORMANCE METAL-INSULATOR-METAL CAPACITOR (MIMCAP)

An integrated circuit structure comprises a first dielectric layer disposed above a substrate. The integrated circuit structure comprises an interconnect structure comprising a first interconnect on a first metal layer, a second interconnect on a second metal layer, and a via connecting the first interconnect and the second interconnect, the first interconnect being on or within the first dielectric layer. A metal-insulator-metal (MIM) capacitor is formed in or on the first dielectric layer in the first metal layer adjacent to the interconnect structure. The MIM capacitor comprises a bottom electrode plate comprising a first low resistivity material, an insulator stack on the bottom electrode plate, the insulator stack comprising at least one of an etch stop layer and a high-K dielectric layer; and a top electrode plate on the insulator stack, the top electrode plate comprising a second low resistivity material. 1. An integrated circuit structure , comprising:a first dielectric layer disposed above a substrate;an interconnect structure comprising a first interconnect on a first metal layer, a second interconnect on a second metal layer, and a via connecting the first interconnect and the second interconnect, the first interconnect being on or within the first dielectric layer; and a bottom electrode plate comprising a first low resistivity material;', 'an insulator stack on the bottom electrode plate, the insulator stack comprising at least one of an etch stop layer and a high-K dielectric layer; and', 'a top electrode plate on the insulator stack, the top electrode plate comprising a second low resistivity material., 'a metal-insulator-metal (MIM) capacitor formed in or on the first dielectric layer in the first metal layer adjacent to the interconnect structure, the MIM capacitor comprising2. The integrated circuit structure of claim 1 , wherein the first low resistivity material of the bottom electrode plate is the same as the second low resistivity material of ...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

A layout structure of a capacitive element using forksheet FETs is provided. A capacitive structure constituting the capacitive element includes: a first transistor having a first nanosheet extending in the X direction and a first gate interconnect extending in the Y direction and surrounding the periphery of the first nanosheet; and a second transistor having a second nanosheet extending in the X direction and a second gate interconnect extending in the Y direction and surrounding the periphery of the second nanosheet. The face of the first nanosheet closer to the second nanosheet is exposed from the first gate interconnect, and the face of the second nanosheet closer to the first nanosheet is exposed from the second gate interconnect. 1. A semiconductor integrated circuit device comprising a capacitive element , the capacitive element having at least one capacitive structure provided between a first node and a second node ,wherein a first transistor having a first nanosheet extending in a first direction and a first gate interconnect extending in a second direction perpendicular to the first direction formed to surround a periphery of the first nanosheet in the second direction and a third direction perpendicular to the first and second directions; and', 'a second transistor having a second nanosheet extending in the first direction and a second gate interconnect extending in the second direction formed to surround a periphery of the second nanosheet in the second and third directions,, 'the capacitive structure includesthe first and second transistors are adjacent to each other in the second direction and mutually connected at at least one node, andthe first nanosheet and the second nanosheet are opposed to each other in the second direction, a face of the first nanosheet closer to the second nanosheet is exposed from the first gate interconnect, and a face of the second nanosheet closer to the first nanosheet is exposed from the second gate interconnect.2. The ...

Semiconductor device and method for forming the same

본 발명의 반도체 소자는 패드 영역과 주변회로 영역을 포함하는 반도체 기판과, 상기 패드 영역의 반도체 기판 상에 구비되는 캐패시터를 포함하는 제 1 버퍼층과, 상기 제 1 버퍼층 상부에 구비되는 제 1 콘택 패드를 포함하는 제 2 버퍼층 및 상기 제 1 콘택 패드 상부에 구비되는 제 2 콘택 패드를 포함하는 제 3 버퍼층을 포함하는 것을 특징으로 한다. The semiconductor device of the present invention includes a semiconductor substrate including a pad region and a peripheral circuit region, a first buffer layer including a capacitor provided on a semiconductor substrate in the pad region, and a first contact pad provided on the first buffer layer. It characterized in that it comprises a second buffer layer and a third buffer layer including a second contact pad provided on the first contact pad.

Decoupling capacitor for finfet compatible process

핀 전계 효과 트랜지스터(FinFET)로부터 형성된 디커플링 캐패시터 및 이를 이용한 방법이 제공된다. 디커플링 캐패시터 실시예는 게이트 스택, 소스 및 드레인을 지지하는 반도체 기판을 갖는 핀 전계 효과 트랜지스터(FinFET), 반도체 기판과 게이트 스택에 커플링되며, 제1 전력 레일과 커플링되도록 구성된 제1 단자, 및 소스와 드레인에 커플링되며, 제1 전력 레일보다 높은 포텐셜을 갖는 제2 전력 레일과 커플링되도록 구성된 제2 단자를 포함한다. A decoupling capacitor formed from a fin field effect transistor (FinFET) and a method using the same are provided. A decoupling capacitor embodiment includes a fin field effect transistor (FinFET) having a gate stack, a semiconductor substrate supporting a source and a drain, a first terminal coupled to the semiconductor substrate and the gate stack, the first terminal configured to couple with the first power rail, And a second terminal coupled to the source and drain and configured to couple with a second power rail having a potential higher than the first power rail.

Structure with embedded memory device, integrated circuit structure and manufacturing method thereof

根据一些实施例，本发明提供了一种制造集成电路的方法。该方法包括在半导体衬底的鳍式有源区上形成源极和漏极；在源极和漏极上沉积层间介电(ILD)层；图案化ILD层以形成分别与源极和漏极对准的第一接触孔和第二接触孔；在第一接触孔中形成介电材料层；以及分别在第一接触孔和第二接触孔中形成第一导电部件和第二导电部件。本发明的实施例还提供了具有嵌入式存储器件的结构和集成电路结构。

Method for manufacturing a semiconductor device

반도체 장치 제조 방법에 관하여 개시한다. 본 발명은 필드 산화막이 형성된 반도체 기판 상에 게이트 절연막, 제1 다결정 실리콘층을 순차적으로 형성하는 단계; 활성 영역 상부의 제1 다결정 실리콘층 상에 실리사이드층 패턴을 형성하는 단계; 비활성 영역 상부의 제1 다결정 실리콘층 상에 순차적으로 적층된 유전막 패턴 및 제2 다결정 실리콘층 패턴을 형성하는 단계; 상기 결과물 전면에 산화막 또는 질화산화막으로 이루어진 반사 방지막을 형성하는 단계; 및 상기 게이트 절연막 및 필드 산화막이 노출되도록 상기 반사 방지막, 실리사이드층 패턴, 및 제1 다결정 실리콘층을 이방성 식각함으로써 반사 방지막 패턴, 변형된 실리사이드층 패턴, 및 제1 다결정 실리콘층 패턴을 형성하는 단계를 포함하는 것을 특징으로 한다. 본 발명에 의하면, 반사 방지막이 손상되는 것을 방지하여 트랜지스터의 전기적 특성을 향상시킬 수 있을 뿐만 아니라 커패시터의 양 전극을 모두 다결정 실리콘으로 형성함으로써 커패시터의 전기적 특성의 열화를 방지할 수 있다. A semiconductor device manufacturing method is disclosed. The present invention includes sequentially forming a gate insulating film and a first polycrystalline silicon layer on a semiconductor substrate on which a field oxide film is formed; Forming a silicide layer pattern on the first polycrystalline silicon layer over the active region; Forming a dielectric film pattern and a second polycrystalline silicon layer pattern sequentially stacked on the first polycrystalline silicon layer on the inactive region; Forming an anti-reflection film formed of an oxide film or an nitride oxide film on the entire surface of the resultant product; And forming an anti-reflection film pattern, a modified silicide layer pattern, and a first polycrystalline silicon layer pattern by anisotropically etching the anti-reflection film, the silicide layer pattern, and the first polycrystalline silicon layer to expose the gate insulating film and the field oxide film. It is characterized by including. According to the present invention, it is possible to prevent the antireflection film from being damaged to improve the electrical characteristics of the transistor, and to prevent deterioration of the electrical characteristics of the capacitor by forming both electrodes of the capacitor from polycrystalline silicon.

Semiconductor device

본 발명의 실시예에 따른 반도체 소자는, 2차원적으로 배열된 하부 전극들, 상기 하부 전극들의 표면들을 덮는 유전막, 및 상기 유전막 상의 상부 전극을 포함하는 캐패시터 구조체 및 상기 하부 전극들을 지지하는 지지 구조체를 포함하되, 상기 지지 구조체는 상기 하부 전극들 중 어느 일부의 측벽들을 덮는 제 1 지지 영역 및 상부에서 볼 때, 상기 제 1 지지 영역을 둘러싸는 오프닝을 포함한다. A semiconductor device according to an embodiment of the present invention includes a capacitor structure including two-dimensionally arranged lower electrodes, a dielectric film covering surfaces of the lower electrodes, and an upper electrode on the dielectric film, and a support structure supporting the lower electrodes. The support structure includes a first support region covering sidewalls of some of the lower electrodes and an opening surrounding the first support region when viewed from above.

Semiconductor device and a method of fabricating thereof

A semiconductor device and a manufacturing method thereof are provided to prevent the damage of the device due to a stepped portion between a gate electrode and a PIP(Polysilicon/Insulator/Polysilicon) capacitor. A semiconductor device includes a semiconductor substrate defined with an active region and an isolation layer, a gate electrode on the active region, a first polysilicon layer, a dielectric film and a second polysilicon layer. The first polysilicon layer(250) is spaced apart from the gate electrode. The dielectric film(260) is formed on the first polysilicon layer. The second polysilicon layer(270) is formed on the dielectric film. The height of the second polysilicon layer is the same as that of the gate electrode.

BURNER CAPACTER ASSOCIATED WITH A SRAM CELL

SEMICONDUCTOR MEMORY

Method for manufacturing bcd device

본 발명은 CMOS 캐패시터의 손상을 막을 수 있는 BCD 소자의 제조방법을 개시한다. 개시된 본 발명의 방법은, CMOS 영역과 DMOS 영역이 정의된 기판을 제공하는 단계; 상기 기판의 소정 부분에 소자분리막을 형성하는 단계; 상기 소자분리막을 포함한 상기 기판 상에 패드산화막 및 HLD 산화막을 차례로 형성하는 단계; 상기 HLD 산화막 및 패드산화막을 선택적으로 식각하여 DMOS 게이트 전극 형성영역 및 버스 전극 형성영역에 대응되는 기판 부분을 노출시키는 단계; 상기 식각후 잔류된 HLD 산화막을 식각 장벽으로 이용하여 상기 기판을 식각하여 제1트렌치 및 제2트렌치를 형성하는 단계; 상기 제1 및 제2트렌치 표면에 게이트 산화막을 형성하는 단계; 상기 제1 및 제2트렌치를 포함한 상기 기판 상에 제1 및 제2트렌치를 매립하도록 제1다결정실리콘막을 형성하는 단계; 상기 제1다결정실리콘막을 식각하여 상기 제1트렌치를 매립하는 DMOS 게이트 전극 및 제2트렌치를 매립하는 제1도전패턴을 형성하는 단계; 상기 DMOS 게이트 전극 및 제1도전패턴을 포함한 전면 상에 제2다결정실리콘막 및 유전체막 형성용 절연막을 차례로 형성하는 단계; 상기 유전체막 형성용 절연막과 제2다결정실리콘막을 선택적으로 식각하여 CMOS 캐패시터용 하부 전극 및 유전체막을 형성함과 동시에, 상기 제1도전패턴과 연결되는 제2도전패턴을 형성하는 단계; 상기 제2도전패턴 상에 잔류되는 유전체막 형성용 절연막을 제거하여 상기 제1 및 제2도전패턴으로 이루어지는 DMOS 버스 전극을 형성하는 단계; 상기 CMOS 액티브 영역에 잔류된 HLD 산화막 및 패드산화막 부분을 선택적으로 제거하는 단계; 및 상기 CMOS 액티브 영역의 기판 상에 CMOS 게이트 전극을 형성하고, 상기 유전체막 상에 CMOS 캐패시터용 상부 전극을 형성하는 단계를 포함한다.

PROCESS FOR MANUFACTURING SELF-ALIGNED INTEGRATED CIRCUITS AND RESULTING DEVICES

DYNAMIC SEMICONDUCTOR MEMORY

Method for manufacturing semiconductor circuit device

MOS 트랜지스터, 용량 소자를 가지는 반도체 장치의 제조 비용을 삭감할 수 있는 제조 방법을 제공하는 것으로서, MOS 트랜지스터의 게이트 전극이 제1의 폴리실리콘막으로 이루어지고, 용량이 제1의 폴리실리콘막과 용량막과 제2의 폴리실리콘막으로 이루어지고, 노멀리 오프 트랜지스터와 용량 하부 전극의 저저항화를 동시에 행하고, N형 MOS 트랜지스터와 용량 상부 전극의 저저항화를 동시에 행하는 것을 특징으로 하는 반도체 회로 장치의 제조 방법.

Semiconductor device with structure of decoupling capacitor

본 발명은 반도체 집적회로를 구성하는 트랜지스터들을 형성할 수 없는 영역에 전원전압 배선의 노이즈를 절감하기 위한 디커플링 커패시터를 형성함으로써, 반도체소자의 면적을 줄일 수 있는 디커플링 커패시터 구조를 갖는 반도체소자를 제공한다. 본 발명은 반도체 집적회로들간을 연결하는 신호 전달 배선이 밀집되어 있는 반도체 기판 주변부에 불순물울 주입하여 n형 웰을 형성하고, 신호 전달 배선과 상기 n형 웰을 각각 상기 디커플링 커패시터의 양쪽 전극으로 동작하게 하며, 그들 사이에 형성된 층간절연막을 그 유전체로 이용한다. The present invention provides a semiconductor device having a decoupling capacitor structure capable of reducing the area of a semiconductor device by forming a decoupling capacitor for reducing noise of power supply wiring in an area where transistors of a semiconductor integrated circuit cannot be formed. . The present invention forms n-type wells by implanting impurities into the periphery of a semiconductor substrate in which signal transmission lines connecting semiconductor integrated circuits are densely formed, and the signal transmission lines and the n-type wells are operated as both electrodes of the decoupling capacitor, respectively. The interlayer insulating film formed between them is used as the dielectric.

Circuitry with voltage limiting and capactive enhancement

Aspects of the present disclosure are directed to circuitry operable with enhanced capacitance and mitigation of avalanche breakdown. As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves respective transistors of a cascode circuit, one of which controls the other in an off state by applying a voltage to a gate thereof. A plurality of doped regions are separated by trenches, with the conductive trenches being configured and arranged with the doped regions to provide capacitance across the source and the drain of the second transistor, and restricting voltage at one of the source and the drain of the second transistor, therein mitigating avalanche breakdown of the second transistor.

RF switches, integrated circuits, and devices with multi-gate field effect transistors and voltage leveling circuits, and methods of their fabrication

Embodiments of field effect transistor (FET) circuits, RF switches, and devices include source and drain terminals coupled to an active surface of a semiconductor substrate, a channel in the substrate between the source and drain terminals, and a plurality of gate structures coupled to the active surface over the channel. A channel contact is coupled to the active surface over the channel between a first pair of the gate structures, and a first capacitor is electrically coupled between the channel contact and a gate structure of the plurality of gate structures.

Single-transistor storage elements

1517206 Transistor memory circuits SIEMENS AG 21 Oct 1975 [22 Oct 1974] 43088/75 Heading H3T A storage element comprises a field effect transistor 1 having its source electrode connected to one electrode of a metal-dielectric-semiconductor capacitor 2, the dielectric of which contains chargeable traps, its drain electrode connected to a bit line 31, and its gate electrode connected to a word line 10, the other electrode of the capacitor being connected to a write-in line 20. To write a "1" transistor 1 is turned on by a signal on line 10, to bring its source to -15v. A -30v signal is then applied to line 20 to form an inversion layer at the surface of the substrate. If a "0" is to be stored then only a depletion layer is present at the silicon surface of MNOS capacitor 2.

Transistor substrate, organic light emitting display panel including the same, method of manufacturing the transistor substrate, and organic light emitting display device including the organic light emitting display panel

Disclosed are a transistor substrate, an organic light emitting display panel including the same, a method of manufacturing the transistor substrate, and an organic light emitting display device including the organic light emitting display panel, in which a driving transistor (Tdr) and a switching transistor (Tsw) are provided and each include an oxide semiconductor of which both ends are covered by an insulation layer (103), and a gate (124) of the driving transistor (Tdr) and a gate (114) of the switching transistor (Tsw) are provided on different layers.

Patent JPS5549777B2

DYNAMIC MEMORY PERFECTED

A metal-oxide-metal (mom) capacitor with enhanced capacitance

특정 금속-산화물-금속(MOM) 캐패시터 디바이스는 기판에 연결된 전도 게이트 재료를 포함한다. MOM 캐패시터 디바이스는 전도 게이트 재료에 연결된 제 1 금속 구조를 더 포함한다. MOM 캐패시터 디바이스는 기판에 연결되고 제 1 금속 구조에 가장 가까운 제 2 금속 구조를 더 포함한다. A particular metal-oxide-metal (MOM) capacitor device comprises a conductive gate material connected to a substrate. The MOM capacitor device further comprises a first metal structure connected to the conductive gate material. The MOM capacitor device further includes a second metal structure connected to the substrate and closest to the first metal structure.

Memory in integrated circuit technology

Integrated circuit fabrication process

Single igfet memory cell with buried storage element

SINGLE IGFET MEMORY CELL WITH BURIED STORAGE ELEMENT Abstract of the Disclosure A semiconductor read/write memory comprised of an array of cells, each having a single active element that is a IGFET device formed in a recess with one source or drain region located directly above and its other source or drain region located within a buried storage capacitor. The gate of each device is connected to an address line in the array, and transverse diffused bit lines interconnect the drains of the devices in aligned and spaced apart cells. Voltage applied via an address line activates a gate to charge its buried capacitor and store a signal when its connected bit line is also activated. Readout of stored charges is controlled by the address line through the connected bit line in the conventional manner. A memory device with an array of such single element cells can be fabricated by forming an array of N-type buried layer diffusions in a P substrate, depositing an epitaxial layer of lightly doped P material that extends above the buried layer diffusions, forming a relatively thin diffusion of N material spaced directly above the buried layer, forming a recess that passes through the thin N layer and the epitaxial layer into the thicker buried N layer, and thereafter forming a gate within the recess.

Nagative capacitance finfet device and manufacturing method therefor

A negative capacitance FinFET device comprises: a FinFET device including a gate stack, a drain electrode, and a source electrode formed on a substrate; and a ferroelectric negative capacitor connected to the gate stack of the FinFET device and having a negative capacitance. The FinFET device has an extension length (L_ext) from a side wall of the gate stack to the drain electrode or the source electrode. The extension length can be set so that a size of a hysteresis window of the negative capacitance FinFET device is 1 V or less.

Storage cell for a charge transfer bucket-brigade circuit

1. A storage cell for a so-called bucket brigade device having a serially connected sequence of such cells, comprising a semiconductor substrate (102) of a first conductivity type with a source region (104') for a first cell, of a second conductivity type having a predetermined thickness, a drain region (104) for this cell, of the second conductivity type, spaced from the source region, having a first dopant concentration and a predeterminde thickness, also comprising a first ion-implanted drain region (107) for the first cell, of the second conductivity type having a second dopant concentration less than the first dopant concentration and a thickness less than the thickness of the source and the drain region, located between the drain region and the source region, spaced therefrom and immediately adjacent to the drain region, as well as with a thin insulating layer (110) lying on the surface of the substrate (2) over the channel and the first ionimplanted drain region (107), a thick insulating layer (106) lying on the surface of the substrate over the source and the drain region (104), and a gate electrode (112) lying over the thin insulating layer (110), characterized in that immediately adjacent to the first ion-implanted drain region (107) for the first cell, of the second conductivity type having a second dopant concentration, there is a second ion-implanted drain region (113) of the second conductivity type having a third dopant concentration less than the second dopant concentration, said second ion-implanted drain region being spaced from the first source region and having a thickness less than the first ionimplanted drain region, so that the resultant structure constitutes two combined FET elements with different threshold values, which as a combination of a charge storage capacitor with a field-effect transistor form a storage cell.

Power MOSFETs and methods for manufacturing the same

A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a substrate, a source region, a drain region, a filed plate and a gate electrode. The source region is of a first conductivity type located at a first side within the substrate. The drain region is of the first conductive type located at a second side within the substrate opposite to the first side. The field plate is located over the substrate and between the source region and the drain region. A portion of the gate electrode is located over the field plate.

CAPACITIVE MEMORY CELL

DYNAMIC MEMORY WITH NON-VOLATILE BACKUP MODE