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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 31714. Отображено 100.
12-01-2012 дата публикации

Nitride-based semiconductor device and method for manufacturing the same

Номер: US20120007049A1
Принадлежит: Samsung Electro Mechanics Co Ltd

The present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes: a base substrate having a diode structure; an epi-growth film disposed on the base substrate; and an electrode part disposed on the epi-growth film, wherein the diode structure includes: first-type semiconductor layers; and a second-type semiconductor layer which is disposed within the first-type semiconductor layers and has both sides covered by the first-type semiconductor layers.

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23-02-2012 дата публикации

Electrostatic discharge (esd) protection device, method of fabricating the device, and electronic apparatus including the device

Номер: US20120043643A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An electrostatic discharge (EDS) device includes a substrate, an external well of a first conductivity type in the substrate, and an internal well of a second conductivity type in the external well, the first conductivity type opposite the second conductivity type. The EDS device further includes a first heavily doped region of the first conductivity type located at a surface of the internal well, a second heavily doped region of the second conductivity type located at a surface of the internal well, and a third heavily doped region of the first conductivity type located at a surface of the external well. The second heavily doped region is interposed between and spaced from each of the first and third heavily doped regions, and at least one of a space between the first and second heavily doped regions and a space between the second and third heavily doped regions is devoid of a device isolation structure of electrical isolation material.

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22-03-2012 дата публикации

Conductive layers for hafnium silicon oxynitride

Номер: US20120068272A1
Автор: Kie Y. Ahn, Leonard Forbes
Принадлежит: Individual

Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum.

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05-04-2012 дата публикации

Method of manufacturing semiconductor device

Номер: US20120083079A1
Автор: Junji Oh
Принадлежит: Fujitsu Semiconductor Ltd

The method of manufacturing the semiconductor device includes amorphizing a first region and a second region of a semiconductor substrate by an ion implantation, implanting a first impurity and a second impurity respectively in the first region and the second region, activating the implanted impurities to form a first impurity layer and a second impurity layer, epitaxially growing a semiconductor layer above the semiconductor substrate with the impurity layers formed on, growing a gate insulating film above the first region and the second region, and forming a first gate electrode above the gate insulating film in the first region and the second gate electrode above the gate insulating film in the second region.

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12-04-2012 дата публикации

Semiconductor device and structure

Номер: US20120088367A1
Принадлежит: Monolithic 3D Inc

A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate; preparing a first monocrystalline layer comprising semiconductor regions; preparing a second monocrystalline layer comprising semiconductor regions overlying the first monocrystalline layer; and etching portions of said first monocrystalline layer and portions of said second monocrystalline layer as part of forming at least one transistor on said first monocrystalline layer.

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26-04-2012 дата публикации

Dummy gate for a high voltage transistor device

Номер: US20120098063A1

The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.

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24-05-2012 дата публикации

System comprising a semiconductor device and structure

Номер: US20120129301A1
Принадлежит: Monolithic 3D Inc

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

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07-06-2012 дата публикации

Semiconductor device

Номер: US20120139055A1
Принадлежит: Panasonic Corp

A semiconductor device includes a first MIS transistor and a second MIS transistor. The first MIS transistor includes a first gate insulating film which is formed on a first active region of a semiconductor substrate and has a first high dielectric constant film, and a first gate electrode formed on the first gate insulating film. The second MIS transistor includes a second gate insulating film which is formed on a second active region of the semiconductor substrate and has a second high dielectric constant film, and a second gate electrode formed on the second gate insulating film. The second high dielectric constant film contains first adjusting metal. The first high dielectric constant film has a higher nitrogen concentration than the second high dielectric constant film, and does not contain the first adjusting metal.

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14-06-2012 дата публикации

Jfet devices with increased barrier height and methods of making the same

Номер: US20120146049A1
Автор: Chandra Mouli
Принадлежит: Micron Technology Inc

Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

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21-06-2012 дата публикации

Sense amplifier structure for a semiconductor integrated circuit device

Номер: US20120154046A1
Автор: Duk Su Chun
Принадлежит: Hynix Semiconductor Inc

A semiconductor integrated circuit device includes a first signal line and a second signal line, and a sense amplifier that includes a plurality of PMOS transistors and a plurality of NMOS transistors. The sense amplifier is configured to sense amplify a potential difference between the first signal line and the second signal line. The junction regions of the NMOS and PMOS transistors having the same conductivity type, and to which the same signal is applied, are formed in one integrated active region.

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28-06-2012 дата публикации

Semiconductor device

Номер: US20120161219A1
Принадлежит: Elpida Memory Inc

a semiconductor device is provided, which includes an N well having a peak concentration of 2E+17 atom/cm 3 or more in the range of 0.2 to 1 μm depth from the surface of a P-type semiconductor substrate, and a region provided below the N well, the region containing P-type impurities with higher concentration than concentration of electrons.

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28-06-2012 дата публикации

Charge pump circuit

Номер: US20120161857A1
Автор: Makoto Sakaguchi
Принадлежит: Renesas Electronics Corp

A charge pump circuit includes first to fifth transistors disposed between a power supply terminal and an output terminal; first to fourth capacitive components between the junctions of the first to fifth transistors and one of first and second clock input terminals; sixth to tenth transistors between the power supply terminal and the output terminal; and fifth to eighth capacitive components between the junctions of the sixth to tenth transistors and one of the first and second clock input terminals. The conduction state of the fifth transistor is controlled according to the potential of a first node. The conduction state of the tenth transistor is controlled according to the potential of a second node. Each transistor is disposed on a triple well, and an n-well and a p-well are electrically coupled to each other in at least the triple wells forming the first to fourth and six to ninth transistors.

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05-07-2012 дата публикации

Asymmetric fet including sloped threshold voltage adjusting material layer and method of fabricating same

Номер: US20120171831A1
Принадлежит: International Business Machines Corp

A method of forming a semiconductor structure is provided. The method includes providing a structure including at least one dummy gate region located on a surface of a semiconductor substrate and a dielectric material layer located on sidewalls of the at least one dummy gate region. Next, a portion of the dummy gate region is removed exposing an underlying high k gate dielectric. A sloped threshold voltage adjusting material layer is then formed on an upper surface of the high k gate dielectric, and thereafter a gate conductor is formed atop the sloped threshold voltage adjusting material layer.

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19-07-2012 дата публикации

STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY

Номер: US20120181616A1
Принадлежит: International Business Machines Corp

A complementary metal oxide semiconductor (CMOS) structure including a scaled n-channel field effect transistor (nFET) and a scaled p-channel field transistor (pFET) which do not exhibit an increased threshold voltage and reduced mobility during operation is provided Such a structure is provided by forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. In some embodiments, the pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack is also plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N 2 and an nFET threshold voltage adjusted species located therein, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion includes up to 15 atomic % N 2 and a pFET threshold voltage adjusted species located therein.

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26-07-2012 дата публикации

Fabrication of cmos transistors having differentially stressed spacers

Номер: US20120187482A1
Принадлежит: International Business Machines Corp

CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.

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02-08-2012 дата публикации

Semiconductor device and method for manufacturing same

Номер: US20120196411A1
Принадлежит: Renesas Electronics Corp

A device and a method for manufacturing the same in which with device includes a single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) in which well diffusion layer regions, drain regions, gate insulating films, and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in the same steps. The bulk-type MISFET and the SOI-type MISFET are formed on the same substrate, so that board area is reduced and a simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.

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23-08-2012 дата публикации

Method of forming an integrated power device and structure

Номер: US20120211827A1
Принадлежит: Individual

In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.

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23-08-2012 дата публикации

Semiconductor memory device for minimizing mismatch of sense amplifier

Номер: US20120213025A1
Автор: Dong Chul Koo
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device is provided. The semiconductor memory device includes a cross-coupled latch type sense amplifier and a buffer that prevents mismatch. The buffer is formed between PMOS transistors and NMOS transistors of the sense amplifier so that mismatch for transistors operating in pair can be minimized.

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27-09-2012 дата публикации

Semiconductor devices and methods of fabricating the same

Номер: US20120241815A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.

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08-11-2012 дата публикации

Spacer as hard mask scheme for in-situ doping in cmos finfets

Номер: US20120280250A1

A method of fabricating a semiconductor device that includes at least two fin structures, wherein one of the at least two fin structures include epitaxially formed in-situ doped second source and drain regions having a facetted exterior sidewall that are present on the sidewalls of the fin structure. In another embodiment, the disclosure also provides a method of fabricating a finFET that includes forming a recess in a sidewall of a fin structure, and epitaxially forming an extension dopant region in the recess that is formed in the fin structure. Structures formed by the aforementioned methods are also described.

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15-11-2012 дата публикации

Sense-amp transistor of semiconductor device and method for manufacturing the same

Номер: US20120286357A1
Автор: Sang Ho Lee
Принадлежит: Hynix Semiconductor Inc

A sense-amp transistor for a semiconductor device and a method for manufacturing the same are disclosed. A sense-amp transistor for a semiconductor device includes a recess array formed in a gate region of a sense-amp, a plurality of buried gates formed in each recess of the recess array so as to form a vertical channel region, and an upper gate configured to form a horizontal channel region in an active region between the buried gates. As a result, the number of additional processes is minimized, and the sensing margin of the sense-amp is guaranteed.

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15-11-2012 дата публикации

Semiconductor integrated circuit

Номер: US20120286837A1
Автор: YOSHIHIRO Tomita
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor integrated circuit is provided, which has mounted thereto a flip-flop circuit including a latch portion that takes and holds input data based upon a clock signal, and a clock portion that inputs the clock signal to the latch portion, wherein an active region of the flip-flop circuit is divided in such a manner that the width of the active region is secured, and each of the active regions has uniform width.

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29-11-2012 дата публикации

Cmos with channel p-finfet and channel n-finfet having different crystalline orientations and parallel fins

Номер: US20120299067A1
Принадлежит: International Business Machines Corp

An integrated circuit fabrication apparatus is configured to fabricate an integrated circuit with at least one p-FinFET device and at least one n-FinFET device. A bonding control processor is configured to bond a first silicon layer having a first crystalline orientation to a second silicon layer having a second crystalline orientation that is different from the first crystalline orientation. A material growth processor is configured to form a volume of material extending through the first silicon layer from the second layer up to the surface of first layer. The material has a crystalline orientation that substantially matches the crystalline orientation of second layer. An etching processor is configured to selectively etch areas of the surface of the first layer that are outside of the region to create a first plurality of fins and areas inside the region to create a second plurality of fins.

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20-12-2012 дата публикации

Junction field effect transistor, integrated circuit for switching power supply, and switching power supply

Номер: US20120319177A1
Автор: Koji SONOBE, Masaru Saito
Принадлежит: Fuji Electric Co Ltd

A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regions (second n-type well regions) are formed circumferentially around the drift region. A drain region (a third n-type well region) is formed centrally of the source region. The drain region and the source regions can be formed at the same time. A metal wiring of the source electrode wiring connected to source regions is divided into at least two groups to form at least two junction field effect transistors.

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20-12-2012 дата публикации

Communication

Номер: US20120322215A1
Принадлежит: International Business Machines Corp

An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness t C ; and a dielectric film of thickness t g in contact with a surface of the channel. Further, the film comprises a material that exerts one of a compressive or a tensile force on the contacted surface of the channel such that electrical mobility of the charge carriers (electrons or holes) along the channel length is increased due to the compressive or tensile force in dependence on alignment of the channel length relative to the crystal structure. Embodiments are given for chips with both hole and electron mobility increased in different transistors, and a method for making such a transistor or chip.

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24-01-2013 дата публикации

Metal gate structure of a cmos semiconductor device and method of forming the same

Номер: US20130020651A1

The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate, an N-metal gate electrode, and a P-metal gate electrode. The substrate comprises an isolation region surrounding a P-active region and an N-active region. The N-metal gate electrode comprises a first metal composition over the N-active region. The P-metal gate electrode comprises a bulk portion over the P-active region and an endcap portion over the isolation region. The endcap portion comprises the first metal composition and the bulk portion comprises a second metal composition different from the first metal composition.

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24-01-2013 дата публикации

Integrated circuit having a stressor and method of forming the same

Номер: US20130020717A1

An embodiment of the disclosure includes a method of forming a semiconductor structure. A substrate has a region adjacent to a shallow trench isolation (STI) structure in the substrate. A patterned mask layer is formed over the substrate. The patterned mask layer covers the STI structure and a portion of the region, and leaves a remaining portion of the region exposed. A distance between an edge of the remaining portion and an edge of the STI structure is substantially longer than 1 nm. The remaining portion of the region is etched thereby forms a recess in the substrate. A stressor is epitaxially grown in the recess. A conductive plug contacting the stressor is formed.

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07-02-2013 дата публикации

Low Threshold Voltage And Inversion Oxide Thickness Scaling For A High-K Metal Gate P-Type MOSFET

Номер: US20130032886A1
Принадлежит: International Business Machines Corp

A structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in T inv and V t of the pFET, while scaling Tiny and maintaining Vt for the nFET, resulting in the V t of the pFET becoming closer to the V t of a similarly constructed nFET with scaled T inv values.

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14-02-2013 дата публикации

Semiconductor device

Номер: US20130037823A1
Принадлежит: Toshiba Corp

In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

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14-02-2013 дата публикации

Trench-gate metal oxide semiconductor device and fabricating method thereof

Номер: US20130037880A1
Принадлежит: United Microelectronics Corp

A trench-gate metal oxide semiconductor device includes a substrate, a first gate dielectric layer, a first gate electrode and a first source/drain structure. The substrate has a first doping region, a second doping region and at least one trench. A P/N junction is formed between the first doping region and the second doping region. The trench extends from a surface of the substrate to the first doping region through the second doping region and the P/N junction. The first gate dielectric layer is formed on a sidewall of the second trench. The first gate electrode is disposed within the trench. A height difference between the top surface of the first gate electrode and the surface of the substrate is substantially smaller than 1500 Å. The first source/drain structure is formed in the substrate and adjacent to the first gate dielectric layer.

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14-03-2013 дата публикации

Semiconductor device with high-voltage breakdown protection

Номер: US20130062694A1
Принадлежит: Seiko Epson Corp

A semiconductor device includes: a semiconductor substrate having a first conductivity type; a well having a second conductivity type and provided inside the semiconductor substrate; a first impurity region having the first conductivity type and provided within the well; a second impurity region having the second conductivity type, provided inside the well and away from the first impurity region; and a third impurity region having a first conductivity type, provided surrounding the well and away from the second impurity region. In this semiconductor device, the well is formed to be deeper than the first impurity region, the second impurity region, and the third impurity region, in a thickness direction of the semiconductor substrate; and a minimum distance between the first impurity region and the second impurity region is smaller than a minimum distance between the second impurity region and the third impurity region.

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14-03-2013 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20130062699A1
Принадлежит: Institute of Microelectronics of CAS

A semiconductor device and a method for manufacturing the same are disclosed. In one embodiment, the semiconductor device may comprise a semiconductor layer, a fin formed by patterning the semiconductor layer, and a gate stack crossing over the fin. The fin may comprise a doped block region at the bottom portion thereof. According to the embodiment, it is possible to effectively suppress current leakage at the bottom portion of the fin by the block region.

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28-03-2013 дата публикации

Junctionless transistor

Номер: US20130075817A1
Принадлежит: International Business Machines Corp

A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type.

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25-04-2013 дата публикации

Thin semiconductor-on-insulator mosfet with co-integrated silicon, silicon germanium and silicon doped with carbon channels

Номер: US20130099319A1
Принадлежит: International Business Machines Corp

A method of fabricating a semiconductor device that may begin with providing a semiconductor substrate including a first device region including a silicon layer in direct contact with a buried dielectric layer, a second device region including a silicon germanium layer in direct contact with the buried dielectric layer, and a third device region with a silicon doped with carbon layer. At least one low power semiconductor device may then be formed on the silicon layer within the first device region of the semiconductor substrate. At least one p-type semiconductor device may be formed on the silicon germanium layer of the second device region of the semiconductor substrate. At least one n-type semiconductor device may be formed on the silicon doped with carbon layer of the third device region of the semiconductor substrate.

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09-05-2013 дата публикации

SEMICONDUCTOR DEVICE WITH REDUCED THRESHOLD VARIABILITY HAVING A THRESHOLD ADJUSTING SEMICONDUCTOR ALLOY IN THE DEVICE ACTIVE REGION

Номер: US20130113019A1
Принадлежит: GLOBALFOUNDRIES INC.

Generally, the subject matter disclosed herein is directed to semiconductor devices with reduced threshold variability having a threshold adjusting semiconductor material in the device active region. One illustrative semiconductor device disclosed herein includes an active region in a semiconductor layer of a semiconductor device substrate, the active region having a region length and a region width that are laterally delineated by an isolation structure. The semiconductor device further includes a threshold adjusting semiconductor alloy material layer that is positioned on the active region substantially without overlapping the isolation structure, the threshold adjusting semiconductor alloy material layer having a layer length that is less than the region length. Additionally, the disclosed semiconductor device includes a gate electrode structure that is positioned above the threshold adjusting semiconductor alloy material layer, the gate electrode structure including a high-k dielectric material and a metal-containing electrode material formed above the high-k dielectric material. 125-. (canceled)26. A semiconductor device , comprising:an active region in a semiconductor layer of a semiconductor device substrate, said active region having a region length and a region width that are laterally delineated by an isolation structure;a threshold adjusting semiconductor alloy material layer having a layer length and a layer width that is positioned on said active region substantially without overlapping said isolation structure, wherein said layer length that is less said region length; anda gate electrode structure that is positioned above said threshold adjusting semiconductor alloy material layer, said gate electrode structure comprising a high-k dielectric material and a metal-containing electrode material formed above said high-k dielectric material, wherein said region length and said layer length extend substantially along a gate length direction of said gate ...

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16-05-2013 дата публикации

SEMICONDUCTOR STRUCTURE FOR AN ELECTRONIC INTERRUPTOR POWER SWITCH

Номер: US20130119443A1
Принадлежит:

The invention relates to a structure comprising an n-type substrate () having a bottom surface () and a top surface (), a drain (D) contacting the bottom surface () of the substrate (), a first n-type semiconductor region () having a top surface () provided with a contact area (), a source (S) contacting the contact area (), and a second p-type semiconductor region () arranged inside the first semiconductor region () and defining first and second conduction channels (C C) between the drain and the source, characterized in that said structure comprises first and second metal gratings (G G), each of which has a portion () contacting the first semiconductor region () so as to form a Schottky junction. 1. A semiconducting structure for an electronic power switch , including:a substrate of a first type of conductivity, having a lower face and an upper face,a drain electrode in contact with the lower face of the substrate,a first semiconducting region, of the first type of conductivity, having a lower surface laid out on the upper face of the substrate and an upper surface provided with a contact area,a source electrode in contact with the contact area of the first semiconducting region,a second semiconducting region, of a second type of conductivity, laid out inside the first semiconducting region, under the contact area, so as to delimit a first and a second conduction channel of the first type of conductivity between the drain electrode and the source electrode,the semiconducting structure being wherein it includes:a first metal gate electrode having at least one first portion in contact with the second semiconducting region, and at least one second portion in contact with the first semiconducting region so as to form a first junction of the Schottky type, anda second metal gate electrode having at least one first portion in contact with the upper surface of the first semiconducting region so as to form a second junction of the Schottky type, the second gate electrode ...

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16-05-2013 дата публикации

TRANSISTOR STRUCTURE

Номер: US20130119479A1
Принадлежит: UNITED MICROELECTRONICS CORP.

A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer. 1. A semiconductor structure , comprising:a substrate comprising a N-type well;a first gate disposed on the N-type well;a first spacer disposed on the gate;a first lightly doped region in the substrate below the spacer;a P-type source/drain region disposed in the substrate at two sides of the first gate;a first silicon cap layer covering the P-type source/drain region and the first lightly doped region; anda silicide layer disposed on the first silicon cap layer, and covering only a portion of the first silicon cap layer.21. The semiconductor structure of claim. , further comprising a first distance which is the shortest distance between first lightly doped region and the first gate , and a second distance which is the shortest distance between the first silicon cap layer and the first gate , and wherein the first distance is shorter than the second distance.3. The semiconductor structure of claim 1 , further comprising an NMOS disposed on the substrate claim 1 , wherein the NMOS comprises:a second gate disposed on the substrate;a second lightly doped region disposed at two side of the second gate, wherein a third distance which is the shortest distance disposed between the second lightly doped region and the second gate, and wherein the first distance is shorter than the third distance; andan N-type source/drain region disposed in the substrate at two sides of the second gate.4. The semiconductor structure of claim 3 , ...

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16-05-2013 дата публикации

SOLUTIONS FOR CONTROLLING BULK BIAS VOLTAGE IN AN EXTREMELY THIN SILICON-ON-INSULATOR (ETSOI) INTEGRATED CIRCUIT CHIP

Номер: US20130120055A1

Solutions for optimizing a bulk bias across a substrate of an ETSOI device are disclosed. In one embodiment, an apparatus for optimizing a bulk bias across a substrate of an ETSOI device is disclosed, including: a sensing circuit for sensing at least one predetermined circuit parameter; a charging circuit for applying a bias voltage to the substrate of the ETSOI device; and a processing circuit connected to the sensing circuit and the charging circuit, the processing circuit configured to receive an output of the sensing circuit, and adjust the bias voltage applied to substrate of the ETSOI device in response to determining whether the bias voltage deviates from a target amount. 1. A method for providing a bulk bias across an extremely thin silicon-on-insulator (ETSOI) device , the method comprising:monitoring a value of a designated circuit parameter in the ETSOI device; andadjusting a bias voltage applied to substantially an entirety of a substrate of the ETSOI device to modify the value of the designated circuit parameter in response to determining whether the value of the designated circuit parameter deviates from a target value.2. The method of claim 1 , wherein the adjusting of the bias voltage is performed using a charging circuit3. The method of claim 1 , wherein the monitoring of the value of the designated circuit parameter is performed using a sensing circuit4. The method of claim 1 , wherein the sensing circuit sensing circuit includes at least one of a leakage monitor or a performance monitor.5. The method of claim 1 , wherein the target value of the bias voltage is based upon the at least one designated circuit parameter.6. The method of claim 1 , further comprising iteratively repeating the monitoring on a predetermined cycle.7. The method of claim 1 , wherein the charging circuit is configured to iteratively repeat the applying of the bias voltage in response to processing circuit determining whether the bias voltage deviates from the target value.8. ...

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23-05-2013 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20130126972A1
Принадлежит: United Microelectronics Corp

A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate of a first conductivity type, a fin, a gate, source and drain regions of a second conductivity type, and a first doped region of the second conductivity type. A plurality of isolation structures is formed on the substrate. The fin is disposed on the substrate between two adjacent isolation structures. The gate is disposed on the isolation structures and covers a portion of the fin, wherein the portion of the fin covered by the gate is of the first conductivity type. The source and drain regions is configured in the fin at respective sides of the gate. The first doped region is configured in the fin underlying the source and drain regions and adjoining the substrate. The first doped region has an impurity concentration lower than that of the source and drain regions.

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23-05-2013 дата публикации

CIRCUITS WITH LINEAR FINFET STRUCTURES

Номер: US20130126978A1
Принадлежит:

A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source and drain regions within a second diffusion fin. The second diffusion fin projects from the surface of the substrate. The second diffusion fin extends lengthwise in the first direction from a first end to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin. 1. A semiconductor device , comprising:a substrate;a first transistor having a source region and a drain region within a first diffusion fin, the first diffusion fin structured to project from a surface of the substrate, the first diffusion fin structured to extend lengthwise in a first direction from a first end of the first diffusion fin to a second end of the first diffusion fin;a second transistor having a source region and a drain region within a second diffusion fin, the second diffusion fin structured to project from the surface of the substrate, the second diffusion fin structured to extend lengthwise in the first direction from a first end of the second diffusion fin to a second end of the second diffusion fin, the second diffusion fin positioned next to and spaced apart from the first diffusion fin,wherein either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin.2. A semiconductor device as recited in claim 1 , wherein the first and second transistors are located at different positions in the second direction.3. A semiconductor device as recited ...

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23-05-2013 дата публикации

Multi-gate semiconductor devices

Номер: US20130126981A1

A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

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23-05-2013 дата публикации

Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for cmos devices

Номер: US20130126986A1
Принадлежит: International Business Machines Corp

A semiconductor device including a germanium containing substrate including a gate structure on a channel region of the semiconductor substrate. The gate structure may include a silicon oxide layer that is in direct contact with an upper surface of the germanium containing substrate, at least one high-k gate dielectric layer in direct contact with the silicon oxide layer, and at least one gate conductor in direct contact with the high-k gate dielectric layer. The interface between the silicon oxide layer and the upper surface of the germanium containing substrate is substantially free of germanium oxide. A source region and a drain region may be present on opposing sides of the channel region.

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23-05-2013 дата публикации

Auto Switch Mosfet

Номер: US20130127519A1
Автор: Dac Thong Bui
Принадлежит: Individual

In one preferred form shown in FIGS. 2 a to 2 c there is provided a field effect transistor ( 24 ). The field effect transistor includes an off switch gate ( 42 ) and a switch bridge ( 44 ). The switch bridge ( 44 ) is provided for charging the off switch gate ( 42 ) such that the off switch gate ( 42 ) is able to screen the electric field of the control gate ( 32 ) of the field effect transistor.

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30-05-2013 дата публикации

Integrated Circuits Based on Aligned Nanotubes

Номер: US20130134394A1
Принадлежит: University of Southern California USC

Techniques, apparatus and systems are described for wafer-scale processing of aligned nanotube devices and integrated circuits. In one aspect, a method can include growing aligned nanotubes on at least one of a wafer-scale quartz substrate or a wafer-scale sapphire substrate. The method can include transferring the grown aligned nanotubes onto a target substrate. Also, the method can include fabricating at least one device based on the transferred nanotubes.

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30-05-2013 дата публикации

Semiconductor Device and Manufacturing Method thereof

Номер: US20130134488A1
Автор: MIENO FUMITAKE

A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.

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30-05-2013 дата публикации

Cmos transistors having differentially stressed spacers

Номер: US20130134523A1
Принадлежит: International Business Machines Corp

CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.

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06-06-2013 дата публикации

Metal gate features of semiconductor die

Номер: US20130140641A1

A CMOS semiconductor die comprises a substrate; an insulation layer over a major surface of the substrate; a plurality of P-metal gate areas formed within the insulation layer collectively covering a first area of the major surface; a plurality of N-metal gate areas formed within the insulation layer collectively covering a second area of the major surface, wherein a first ratio of the first area to the second area is equal to or greater than 1; a plurality of dummy P-metal gate areas formed within the insulation layer collectively covering a third area of the major surface; and a plurality of dummy N-metal gate areas formed within the insulation layer collectively covering a fourth area of the major surface, wherein a second ratio of the third area to the fourth area is substantially equal to the first ratio.

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06-06-2013 дата публикации

ANALOG CIRCUIT CELL ARRAY AND ANALOG INTEGRATED CIRCUIT

Номер: US20130140642A1
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein the first gate electrode and the second gate electrode are connected together for use, and the first source region and the second source region are connected together for use. 1. An analog integrated circuit comprising: an analog circuit cell array including a plurality of transistor cell arranged in an array , each of the transistor cells comprising:a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence in a first direction one adjacent to another; anda first gate electrode and a second gate electrode arranged on the first channel region and the second channel region, respectively, and the first gate electrode and the second gate electrode being extended in a second direction perpendicular to the first direction and whereinthe first gate electrode and the second gate electrode are connected together for use, andthe first source region and the second source region are connected together for use;wherein the plurality of transistor cells include PMOS transistor cells and NMOS transistor cells, transistor cells of identical type are arranged in continuous fashion in four rows and four or more columns; andwherein the analog integrated circuit comprises a transistor pair arranged in a common centroid configuration by using 2*2 transistor cells located in a center area of a section in which the transistor cells of identical type are arranged in continuous fashion in four rows and four or more columns.2. The analog integrated circuit according to ...

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06-06-2013 дата публикации

Integrated high-k/metal gate in cmos process flow

Номер: US20130140643A1

A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.

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06-06-2013 дата публикации

Localized carrier lifetime reduction

Номер: US20130140667A1

A semiconductor structure includes a substrate, a first power device and a second power device in the substrate, at least one isolation feature between the first and second power device, and a trapping feature adjoining the at least one isolation feature in the substrate.

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06-06-2013 дата публикации

Forming Structures on Resistive Substrates

Номер: US20130140668A1
Принадлежит: International Business Machines Corp

A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

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13-06-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Номер: US20130146879A1
Принадлежит: SHARP KABUSHIKI KAISHA

Disclosed is a semiconductor device in which an n-channel type first thin film transistor and a p-channel type second thin film transistor are provided on the same substrate. The first thin film transistor has a first semiconductor layer (), and the second thin film transistor has a second semiconductor layer (), a third semiconductor layer (), and a fourth semiconductor layer (). The first semiconductor layer (), the second semiconductor layer (), the third semiconductor layer () and the fourth semiconductor layer () are formed of the same film, and the first and second semiconductor layers () respectively have slanted portions () positioned at respective peripheries, and main portions () made of portions other than the slanted portions. A p-type impurity is implanted into the slanted portion () of the first semiconductor layer at a concentration higher than that in the main portion () of the first semiconductor layer and that in the main portion () of the second semiconductor layer. 1. A semiconductor device , comprising:a first thin film transistor of n-channel type and a second thin film transistor of p-channel type formed on a single substrate; andan insulating film on which the first and second thin film transistors are formed,wherein the first thin film transistor comprises: a first semiconductor layer that has a channel region, a source region, and a drain region; a gate electrode disposed so as to overlap the channel region; and a gate insulating film interposed between the first semiconductor layer and the gate electrode,wherein the second thin film transistor comprises: a second semiconductor layer that has a channel region, a source region, and a drain region; a third semiconductor layer and a fourth semiconductor layer that are disposed at opposite sides of the second semiconductor layer; a gate electrode disposed so as to overlap the channel region and the third and fourth semiconductor layers; and a gate insulating film interposed between the second ...

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13-06-2013 дата публикации

METHODOLOGY FOR FABRICATING ISOTROPICALLY RECESSED DRAIN REGIONS OF CMOS TRANSISTORS

Номер: US20130146965A1

A method for fabricating recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer. 1. A field effect transistor (FET) device , comprising:a buried oxide layer;a silicon layer above the buried oxide layer;a gate stack formed over a channel region of the silicon layer, the channel region having a thickness of less than 40 nanometers (nm);a source region arranged adjacent to the silicon layer on the buried oxide layer;a drain region arranged adjacent to the silicon layer on the buried oxide layer; anda native oxide layer arranged along sidewalls of the gate stack and over and in contact with a portion of the source region and a portion of the drain region, wherein the source and drain regions comprise different semiconductor materials with respect to the channel region.2. The device of claim 1 , wherein the silicon layer further comprises shallow trench isolation regions to provide isolated silicon regions.3. The device of claim 1 , wherein the silicon layer comprises p or n-doped polysilicon.4. The device of claim 1 , wherein a gate dielectric is formed on the silicon region and the gate stack is formed over the gate dielectric.5. The device of claim 1 , wherein the gate stack comprises:doped polysilicon; anda layer of dielectric over the native oxide. This application is a continuation of U.S. patent application Ser. No. 12/779,087, filed on May 13, 2010, the ...

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13-06-2013 дата публикации

Compensated Well ESD Diodes With Reduced Capacitance

Номер: US20130146979A1
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode. 1. An integrated circuit , comprising:a p-type substrate;a pwell formed in said p-type substrate where doping of said pwell is higher than doping of said p-type substrate;an NMOS transistor with N+ doped deep source and drain diffusions formed in said pwell;a first nwell formed in said p-type substrate;a PMOS transistor with P+ doped deep source and drain diffusions formed in said first nwell;a shallow trench isolation geometry which isolates an N+ deep diffusion from a P+ deep diffusion where said N+ deep diffusion and said N+ doped deep source and drain diffusion doping concentrations are equal and where said P+ deep diffusion and said P+deep source and drain diffusion doping concentrations are equal;a low capacitance STI ESD diode selected from the group consisting of:a diode formed between said N+ deep diffusion and said p-type substrate a diode formed between a second nwell and an isolated pwell where said isolated pwell is formed in said second nwell;a diode formed between a counter doped nwell N− diffusion and said p-type substrate; anda diode formed between said counter doped nwell N− diffusion and said isolated pwell;where said N+ deep diffusion is a cathode of said low capacitance STI ESD diode; andwhere said P+ deep diffusion is an anode of said low capacitance STI ESD diode.2. The integrated circuit of where said low capacitance STI ESD diode is a STI ESD P/N diode claim 1 , where said p-type substrate is under said N+ deep diffusion claim 1 , where said pwell is under said P+ deep diffusion claim 1 , where said low capacitance STI ESD P/N diode is formed between said N+ deep diffusion and said p-type ...

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13-06-2013 дата публикации

Integrated Semiconductor Structure for SRAM and Fabrication Methods Thereof

Номер: US20130146987A1

A SRAM device with metal gate transistors is provided. The SRAM device includes a PMOS structure and an NMOS structure over a substrate. Each of the PMOS and the NMOS structure includes a p-type metallic work function layer and an n-type metallic work function layer. The p-type work metallic function layer and the n-type metallic work function layer form a combined work function for the PMOS and the NMOS structures. 19-. (canceled)10. A semiconductor device comprising: a first gate dielectric overlying a substrate;', 'a first metal gate overlying the first gate dielectric;', 'a second metal gate overlying the first metal gate; and', 'a first conductor overlying the second metal gate; and, 'a NMOS structure, comprising,'} a second gate dielectric overlying the substrate;', 'a third metal gate overlying the second gate dielectric;', 'a fourth metal gate overlying the third metal gate; and', 'a second conductor overlying the fourth metal gate,, 'a PMOS structure, comprising,'}wherein the first metal gate is the same as the third metal gate and the second metal gate layer is the same as the fourth metal gate.11. The semiconductor device of claim 10 , wherein the device is static random access memory (SRAM).12. The semiconductor device of claim 10 , wherein the first and the third metal gates are p-type work function layers.13. The semiconductor device of claim 12 , wherein the p-type work function layers are titanium nitride claim 12 , tantalum nitride claim 12 , or cobalt.14. The semiconductor device of claim 10 , wherein the second and the fourth metal gates are n-type work function layers.15. The semiconductor device of claim 14 , wherein the n-type work function layers are titanium claim 14 , tantalum claim 14 , aluminum claim 14 , or combinations thereof.16. The semiconductor device of claim 10 , wherein the PMOS structure has a combined work function ranging from about 4.4 eV to about 4.8 eV.17. The semiconductor device of claim 10 , wherein the NMOS structure has ...

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13-06-2013 дата публикации

Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Shared Diffusion Regions on Opposite Sides of Two-Transistor-Forming Gate Level Feature

Номер: US20130146988A1
Принадлежит:

A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device. 1. An integrated circuit , comprising:a gate electrode level region having a number of adjacently positioned gate level feature layout channels, each gate level feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate level feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a line end spacing and a second end located adjacent to another line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends,wherein the gate electrode level region includes a first gate level feature that includes a first part that forms a gate electrode of a first transistor of a first transistor type and a second part that forms a gate electrode of a first transistor of a second transistor type, wherein the gate electrode ...

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20-06-2013 дата публикации

SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT, SRAM, AND METHOD FOR PRODUCING Dt-MOS TRANSISTOR

Номер: US20130154023A1
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

A semiconductor device includes a silicon substrate; an element isolation region; an element region including a first well; a contact region; a gate electrode extending from the element region to a sub-region of the element isolation region between the element region and the contact region; a source diffusion region; a drain diffusion region; a first insulating region contacting a lower end of the source diffusion region; a second insulating region contacting a lower end of the drain diffusion region; and a via plug configured to electrically connect the gate electrode with the contact region. The first well is disposed below the gate electrode and is electrically connected with the contact region via the silicon substrate under the sub-region. The lower end of the element isolation region except the sub-region is located lower than the lower end of the first well. 1. A static random access memory , comprising:a first CMOS inverter including a first MOS transistor forming a channel of a first conductivity type and a second MOS transistor forming a channel of a second conductivity type that is opposite to the first conductivity type, the first MOS transistor and the second MOS transistor being connected in series via a first node;a second CMOS inverter including a third MOS transistor forming a channel of the second conductivity type and a fourth MOS transistor forming a channel of the first conductivity type, the third MOS transistor and the fourth MOS transistor being connected in series via a second node, the first CMOS inverter and the second CMOS inverter forming a flip-flop circuit;a first transfer transistor connected between a first bit line and the first node and including a first gate electrode connected to a word line, the first transfer transistor being driven by a selection signal on the word line; anda second transfer transistor connected between a second bit line and the second node and including a second gate electrode connected to the word line, the ...

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20-06-2013 дата публикации

STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUGH WAFER VIA WITHIN CMOS CIRCUITRY

Номер: US20130154024A1

A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material. 1. A semiconductor structure , comprising:an NFET device having a P-well at a top side of a substrate;a PFET device having an N-well at the top side of the substrate; anda substrate contact comprising a through wafer via extending from a backside of the substrate to a bottom surface of an isolation structure located between the NFET device and the PFET device,wherein the substrate contact is arranged to prevent formation of a parasitic circuit.2. The semiconductor structure of claim 1 , wherein the through wafer via is in contact with and at substantially a same electrical potential as one of the P-well and the N-well claim 1 , and is remote from the other of the P-well and the N-well claim 1 , respectively.3. The semiconductor structure of claim 1 , wherein a top portion of the through wafer via contacts a bottom portion of the isolation structure.4. The semiconductor structure of claim 3 , wherein the isolation structure comprises one of:a shallow trench isolation (STI) structure,a trench isolation (TI) structure formed through a shallow trench isolation (STI) structure, anda deep trench (DT) structure formed below a shallow trench isolation (STI) structure.5. The semiconductor structure of claim 1 , further comprising a dopant out-diffused from surfaces of a via opening of the through wafer via into the substrate and a deep well.6. A semiconductor structure claim 1 , comprising:an NFET device having a P-well at a top side of a substrate;a PFET device having an N-well at the top side of the substrate;a deep well ...

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27-06-2013 дата публикации

Buried Power Grid Designs and the Methods for Forming Buried Power Grids in CMOS Technologies for Improved Radiation Hardness

Номер: US20130161758A1
Принадлежит:

Buried power grids are designed as a fine mesh-type pattern of heavily doped diffusion regions with neutral epitaxial region cores to allow the uninterrupted electrical continuity of the epitaxial substrate, thus avoiding floating substrate effects. The buried power grids are formed beneath the epitaxial substrate surface and are powered via electrical contact to adjacent well regions. The buried power grids, when powered, form strongly reverse-biased buried pn junction regions that restrict radiation induced excess charge collection volumes and draw excess charge away from sensitive circuit nodes The method for forming buried power grids requires no uniquely complex process steps and no critical mask alignments to the CMOS devices on the epitaxial top surface. Buried power grids provide enhanced protection to sensitive circuit nodes against logic upsets due to single-particle and prompt dose radiation events and thereby improve the radiation hardness and decreases the latchup susceptibility of CMOS circuits. 1. A semiconductor device comprising:a heavily doped substrate semiconductor material of first conductivity type; andan epitaxial layer of lightly doped semiconductor material of first conductivity type formed on the heavily doped substrate material having an first impurity concentration to function as the common substrate node of a plurality of first conductivity type CMOS transistors to be built on its surface and with an epitaxial layer thickness to fully contain the subsequent formation of well regions within the epitaxial layer; andfirst well regions of second conductivity type formed within the epitaxial layer that have a second impurity concentration greater than the first impurity concentration of the epitaxial layer and which function as the common substrate nodes of a plurality of complementary second conductivity type CMOS transistors to be built on the surface of the first well regions and with shallow well depth that supports the integrity of each ...

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27-06-2013 дата публикации

METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW

Номер: US20130161759A1
Принадлежит:

A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate. 1. A transistor structure comprising:a substrate;at least one first transistor positioned on a first region of said substrate;at least one second transistor positioned on a second region of said substrate;a gate conductor comprising first portions and second portions, said first portions of said gate conductor being positioned within said first transistor and said second portions of said gate conductor being positioned within said second transistor;a first conformal insulator positioned over said first portions of said gate conductor and said second portions of said gate conductor; anda second conformal insulator on said first conformal insulator positioned over said second portions of said gate conductor and having an end between said first portions of said gate conductor and said second portions of said gate conductor.2. The transistor structure according to claim 1 , said second conformal insulator layer contacting said first conformal insulator layer and being thinner than said first conformal insulator layer.3. The transistor structure according to claim 1 , said second conformal insulator layer comprising a molecular layer deposition layer.4. The transistor structure ...

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27-06-2013 дата публикации

Integrated Circuit Including Gate Electrode Tracks Including Offset End-to-End Spacings

Номер: US20130161760A1
Принадлежит:

An integrated circuit includes a first gate electrode feature of a first gate electrode track that forms a first n-channel transistor as it crosses an n-diffusion region, and a second gate electrode feature of the first gate electrode track that forms a first p-channel transistor as it crosses a p-diffusion region. The first and second gate electrode features of the first gate electrode track are separated by a first end-to-end spacing. The integrated circuit includes a first gate electrode feature of a second gate electrode track that forms a second n-channel transistor as it crosses the n-diffusion region, and a second gate electrode feature of the second gate electrode track that forms a second p-channel transistor as it crosses the p-diffusion region. The first and second gate electrode features of the second gate electrode track are separated by a second end-to-end spacing that is offset from the first end-to-end spacing. 1a first gate electrode feature of a first gate electrode track, wherein the first gate electrode feature of the first gate electrode track forms a first n-channel transistor as it crosses an n-diffusion region;a second gate electrode feature of the first gate electrode track, wherein the second gate electrode feature of the first gate electrode track forms a first p-channel transistor as it crosses a p-diffusion region, wherein the first and second gate electrode features of the first gate electrode track are separated by a first end-to-end spacing;a first gate electrode feature of a second gate electrode track, wherein the first gate electrode feature of the second gate electrode track forms a second n-channel transistor as it crosses the n-diffusion region; anda second gate electrode feature of the second gate electrode track, wherein the second gate electrode feature of the second gate electrode track forms a second p-channel transistor as it crosses the p-diffusion region, wherein the first and second gate electrode features of the second ...

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04-07-2013 дата публикации

Method of Forming CMOS FinFET Device

Номер: US20130168771A1

A CMOS FinFET device and method for fabricating a CMOS FinFET device is disclosed. An exemplary CMOS FinFET device includes a substrate including a first region and a second region. The CMOS FinFET further includes a fin structure disposed over the substrate including a first fin in the first region and a second fin in the second region. The CMOS FinFET further includes a first portion of the first fin comprising a material that is the same material as the substrate and a second portion of the first fin comprising a III-V semiconductor material deposited over the first portion of the first fin. The CMOS FinFET further includes a first portion of the second fin comprising a material that is the same material as the substrate and a second portion of the second fin comprising a germanium (Ge) material deposited over the first portion of the second fin.

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11-07-2013 дата публикации

Semiconductor device, display device, and production method for semiconductor device and display device

Номер: US20130175535A1
Автор: Kazushige Hotta
Принадлежит: Sharp Corp

In order to efficiently manufacture a semiconductor device having a plurality of TFTs formed thereon, which can be applied to a variety of uses, a semiconductor device ( 100 ) is disclosed that is provided with a first P-type TFT ( 10 a ), a second P-type TFT ( 10 b ), a first N-type TFT ( 10 c ), and a second N-type TFT ( 10 d ), each having a channel region that is formed of polycrystalline silicon. When d1, d2, d3, and d4 respectively represent the concentrations of p-type impurities in the respective channel regions of the TFTs ( 10 a to 10 d ), at least three values out of d1, d2, d3, and d4 are mutually different, and d1, d2, d3, and d4 satisfy relations of d1<d2 and d3<d4.

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11-07-2013 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20130175611A1
Принадлежит: Renesas Electronics Corp

An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate.

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11-07-2013 дата публикации

STRUCTURE AND METHOD FOR USING HIGH-K MATERIAL AS AN ETCH STOP LAYER IN DUAL STRESS LAYER PROCESS

Номер: US20130175634A1
Автор: HENSON William K.

A method is provided that includes forming a high-k dielectric etch stop layer over at least a first conductivity type semiconductor device on a first portion of a substrate and at least a second conductivity type semiconductor device on a second portion of the semiconductor device. A first stress-inducing layer is deposited over the first conductivity type semiconductor device and the second conductivity type semiconductor device. The portion of the first stress-inducing layer that is formed over the second conductivity type semiconductor device is then removed with an etch that is selective to the high-k dielectric etch stop layer to provide an exposed surface of second portion of the substrates that includes at least the second conductivity type semiconductor device. A second stress-inducing layer is then formed over the second conductivity type semiconductor device. 1. A semiconductor device comprising:a first conductivity type semiconductor device located in a first portion of a substrate;a second conductivity type semiconductor device located in a second portion of the substrate;at least one high-k dielectric etch stop layer present over the first conductivity type semiconductor device and the second conductivity type semiconductor device;a first stress-inducing layer located on a portion of the at least one high-k dielectric etch stop layer that is over the first conductivity type semiconductor device; anda second stress-inducing layer located on a portion of the at least one high-k dielectric etch stop layer that is over the second conductivity type semiconductor device.2. The semiconductor device of claim 1 , wherein the substrate is a silicon-containing substrate selected from the group consisting of Si claim 1 , bulk Si claim 1 , single crystal Si claim 1 , polycrystalline Si claim 1 , SiGe claim 1 , amorphous Si claim 1 , silicon-on-insulator substrates (SOI) claim 1 , SiGe-on-insulator (SGOI) claim 1 , strained-silicon-on-insulator claim 1 , annealed ...

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11-07-2013 дата публикации

REPLACEMENT METAL GATE STRUCTURES FOR EFFECTIVE WORK FUNCTION CONTROL

Номер: US20130175635A1

A stack of a barrier metal layer and a first-type work function metal layer is deposited in replacement metal gate schemes. The barrier metal layer can be deposited directly on the gate dielectric layer. The first-type work function metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the barrier metal layer in the regions of a second type field effect transistor. Alternately, the first-type work function layer can be deposited directly on the gate dielectric layer. The barrier metal layer is patterned to be present only in regions of a first type field effect transistor. A second-type work function metal layer is deposited directly on the gate dielectric layer in the regions of the second type field effect transistor. A conductive material fill and planarization form dual work function replacement gate structures. 2. The semiconductor structure of claim 1 , wherein each of said first and second gate dielectrics includes a horizontal gate dielectric portion and a vertical gate dielectric portion extending upward from peripheral regions of said horizontal gate dielectric portion claim 1 , wherein one of said first and second barrier metal portions contacts inner sidewalls of said vertical gate dielectric portion.3. The semiconductor structure of claim 1 , wherein said first field effect transistor further comprises a first gate conductor portion contacting an upper surface and inner sidewalls of said first second-type work function metal portion claim 1 , and said second field effect transistor further comprises a second gate conductor portion contacting an upper surface and inner sidewalls of said second second-type work function metal portion.4. The semiconductor structure of claim 1 , wherein one of said first and second field effect transistors is a p-type field effect transistor and the other of said first and second field effect transistors is an n-type ...

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25-07-2013 дата публикации

STRUCTURE AND METHOD OF Tinv SCALING FOR HIGH k METAL GATE TECHNOLOGY

Номер: US20130187239A1

A complementary metal oxide semiconductor structure including a scaled nFET and a scaled pFET which do not exhibit an increased threshold voltage and reduced mobility during operation is provided. The method includes forming a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion within an nFET gate stack, and forming at least a pFET threshold voltage adjusted high k gate dielectric layer portion within a pFET gate stack. The pFET threshold voltage adjusted high k gate dielectric layer portion in the pFET gate stack can also be plasma nitrided. The plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % Nand an nFET threshold voltage adjusted species, while the plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion contains up to 15 atomic % Nand a pFET threshold voltage adjusted species. 1. A complementary semiconductor (CMOS) structure comprising:a semiconductor substrate having an nFET device region and a pFET device; and{'sub': 2', '2, 'an nFET gate stack located in the nFET device region and a pFET gate stack located in the pFET device region, wherein the nFET gate stack includes, from bottom to top, a plasma nitrided, nFET threshold voltage adjusted high k gate dielectric layer portion including up to 15 atomic % N, and a first patterned portion of a gate electrode layer, and the pFET gate stack includes, from bottom to top, a plasma nitrided, pFET threshold voltage adjusted high k gate dielectric layer portion including up to 15 atomic % N, and a second patterned portion of a gate electrode layer.'}2. The CMOS structure of wherein said plasma nitrided claim 1 , pFET threshold voltage adjusted high k gate dielectric layer portion includes a high k gate dielectric material having at least one pFET threshold voltage adjusting species selected from Ta claim 1 , Ti claim 1 , Al and Ge present therein.3. The CMOS structure of wherein said high k ...

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01-08-2013 дата публикации

Semiconductor Structure and Method for Manufacturing the Same

Номер: US20130193490A1
Принадлежит: Institute of Microelectronics of CAS

The present invention provides a semiconductor structure, which comprises: a substrate, a semiconductor base, a semiconductor auxiliary base layer, a cavity, a gate stack, a sidewall spacer, and a source/drain region, wherein the gate stack is located on the semiconductor base; the sidewall spacer is located on the sidewalls of the gate stack; the source/drain region is embedded in the semiconductor base and is located on both sides of the gate stack; the cavity is embedded in the substrate; the semiconductor base is suspended above the cavity, the thickness of the middle portion of the semiconductor base is greater than the thickness of the two end portions of the semiconductor base in the direction of the length of the gate, and the two end portions of the semiconductor base are connected to the substrate in the direction of the width of the gate; and the semiconductor auxiliary base layer is located on the sidewall of the semiconductor base and has an opposite doping type to that of the source/drain region, and the doping concentration of the semiconductor auxiliary base layer is higher than that of the semiconductor base. Correspondingly, the present invention also provides a method for manufacturing a semiconductor structure. According to the present invention, the short channel effect can be suppressed, and the device performance can be improved, thereby reducing the cost and simplifying the process.

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01-08-2013 дата публикации

Modifying Work Function in PMOS Devices by Counter-Doping

Номер: US20130193521A1

A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode. 1. A structure comprising:a semiconductor substrate;a first p-type transistor device in a memory region in the semiconductor substrate, the first p-type transistor device comprising a first gate electrode; anda second p-type transistor device in a peripheral circuit, the second p-type transistor device comprising a second gate electrode,wherein a work function of the first gate electrode is different from a work function of the second gate electrode, and wherein a saturation voltage of the first p-type transistor device is greater than 10% more than a saturation voltage of the second p-type transistor device.2. The structure of claim 1 , wherein a leakage for the first p-type transistor device is less than a leakage for the second p-type transistor device.3. The structure of claim 1 , wherein a concentration of an n-type impurity in the first p-type transistor device is greater than a concentration of an n-type impurity in the second p-type transistor device.4. The structure of claim 3 , wherein the concentration of an n-type impurity in the first p-type transistor device is in the first gate electrode claim 3 , and wherein the concentration of an n-type impurity in the second p-type transistor device is in the second gate electrode.5. The structure of claim 1 , wherein a concentration of an n-type impurity in the first p-type transistor device is greater than 10/cm claim 1 , and the second p-type transistor ...

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01-08-2013 дата публикации

REPLACEMENT METAL GATE STRUCTURES PROVIDING INDEPENDENT CONTROL ON WORK FUNCTION AND GATE LEAKAGE CURRENT

Номер: US20130193522A1

The thickness and composition of a gate dielectric can be selected for different types of field effect transistors through a planar high dielectric constant material portion, which can be provided only for selected types of field effect transistors. Further, the work function of field effect transistors can be tuned independent of selection of the material stack for the gate dielectric. A stack of a barrier metal layer and a first-type work function metal layer is deposited on a gate dielectric layer within recessed gate cavities after removal of disposable gate material portions. After patterning the first-type work function metal layer, a second-type work function metal layer is deposited directly on the barrier metal layer in the regions of the second type field effect transistor. A conductive material fills the gate cavities, and a subsequent planarization process forms dual work function metal gate structures. 1. A semiconductor structure comprising a first field effect transistor and a second field effect transistor that are located on a semiconductor substrate , a first gate dielectric located over a first portion of said semiconductor substrate;', 'a first-type work function metal portion overlying a horizontal portion of said first gate dielectric; and', 'a first second-type work function metal portion contacting said first-type work function metal portion,, 'wherein said first field effect transistor comprises a second gate dielectric located over a second portion of said semiconductor substrate; and', 'a second second-type work function metal portion overlying a horizontal portion of said second gate dielectric, wherein said horizontal portion of said second gate dielectric has a different thickness than said horizontal portion of said first gate dielectric., 'and wherein said second field effect transistor comprises2. The semiconductor structure of claim 1 , wherein one of said first and second gate dielectrics includes a U-shaped gate dielectric portion ...

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01-08-2013 дата публикации

STRUCTURE AND METHOD FOR MAKING LOW LEAKAGE AND LOW MISMATCH NMOSFET

Номер: US20130193523A1

An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation , GIDL and junction leakage. 111-. (canceled)12. An SRAM chip comprising:a plurality of SRAM cells, each SRAM cell comprising a plurality of low leakage NFETs and a plurality of PFETS;a plurality of logic NFETs;wherein each of the PFETs and each of the logic NFETs comprises a gate stack encapsulated by a nitride layer, and wherein each of the low leakage NFETs comprise a gate stack encapsulated by an oxide layer, each gate stack comprised of a high-K dielectric layer, and a metal layer, and wherein a Vt delta exists between the low leakage NFETs and the logic NFETs, wherein the low leakage NFETs have a threshold voltage that is larger than the threshold voltage of the logic NFETs.13. The SRAM chip of claim 12 , wherein the Vt delta ranges from about 100 mV to about 400 mV.14. The SRAM chip of claim 12 , wherein the gate stack further comprises a polysilicon layer disposed above the metal layer.15. The SRAM chip of claim 12 , wherein the effective oxide thickness ranges from about 50 to about 300 angstroms.16. The SRAM chip of claim 12 , wherein the effective oxide thickness of the low leakage NFETs is about 1 to about 8 angstroms thicker than the effective oxide thickness of the PFETs and logic NFETs.17. The SRAM chip of claim 12 , wherein the nitride layer has a thickness ranging from about 1 nanometer to about 7 nanometers.18. The SRAM chip of claim 12 , wherein the metal layer of each gate stack is comprised of TiN.19. A semiconductor ...

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01-08-2013 дата публикации

Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track and Gate Node Connection Through Single Interconnect Layer

Номер: US20130193524A1
Принадлежит: Individual

A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection formed by linear-shaped conductive structures. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.

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08-08-2013 дата публикации

Device for detecting a laser attack in an integrated circuit chip

Номер: US20130200371A1
Принадлежит: STMICROELECTRONICS ROUSSET SAS

A device for detecting a laser attack in an integrated circuit chip formed in the upper P-type portion of a semiconductor substrate incorporating an NPN bipolar transistor having an N-type buried layer, including a detector of the variations of the current flowing between the base of said NPN bipolar transistor and the substrate.

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08-08-2013 дата публикации

USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES

Номер: US20130200434A1

Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET. 1. An integrated circuit (IC) chip comprising:a substrate having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) thereon, the PFET and NFET each including a source/drain region;a PFET contact to a source/drain region of the PFET;an NFET contact to a source/drain region of the NFET; anda silicon germanium (SiGe) layer only under the PFET contact, wherein the SiGe layer extends into the source/drain region of the PFET.2. The IC chip of claim 1 , wherein the SiGe layer extends approximately 50 to approximately 3000 angstroms into the source/drain region of the PFET.3. The IC chip of claim 1 , wherein the PFET contact includes a pair of PFET contacts claim 1 , one PFET contact to a source region of the PFET and one PFET contact to a drain region of the PFET.4. The IC chip of claim 1 , wherein an upper surface of the SiGe layer is coplanar with an upper surface of the source/drain region of the PFET.5. The IC chip of claim 1 , wherein a percentage of germanium (Ge) in the SiGe layer is approximately 20 percent.6. An integrated circuit (IC) chip comprising:a substrate having a p-type field effect transistor (PFET) and a n-type field effect transistor (NFET) thereon, the PFET and NFET each including a source/drain region;a PFET contact to a source ...

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08-08-2013 дата публикации

Integrated Circuit with Gate Electrode Conductive Structures Having Offset Ends

Номер: US20130200436A1
Принадлежит: Individual

A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES.

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08-08-2013 дата публикации

Semiconductor Substrate, Integrated Circuit Having the Semiconductor Substrate, and Methods of Manufacturing the Same

Номер: US20130200456A1
Принадлежит:

The present invention relates to a semiconductor substrate, an integrated circuit having the semiconductor substrate, and methods of manufacturing the same. The semiconductor substrate for use in an integrated circuit comprising transistors having back-gates according to the present invention comprises: a semiconductor base layer; a first insulating material layer on the semiconductor base layer; a first conductive material layer on the first insulating material layer; a second insulating material layer on the first conductive material layer; a second conductive material layer on the second insulating material layer; an insulating buried layer on the second conductive material layer; and a semiconductor layer on the insulating buried layer, wherein at least one first conductive via is provided between the first conductive material layer and the second conductive material layer to penetrate through the second insulating material layer so as to connect the first conductive material layer with the second conductive material layer, the position of each of the first conductive vias being defined by a region in which a corresponding one of a first group of transistors is to be formed. 1. A semiconductor substrate for manufacturing transistors having back-gates thereon , comprising:a semiconductor base layer;a first insulating material layer on the semiconductor base layer;a first conductive material layer on the first insulating material layer;a second insulating material layer on the first conductive material layer;a second conductive material layer on the second insulating material layer;an insulating buried layer on the second conductive material layer; anda semiconductor layer on the insulating buried layer,wherein at least one first conductive via is provided between the first conductive material layer and the second conductive material layer to penetrate through the second insulating material layer so as to connect the first conductive material layer with the second ...

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08-08-2013 дата публикации

Integrated Circuit with Offset Line End Spacings in Linear Gate Electrode Level

Номер: US20130200462A1
Принадлежит: Individual

A first linear-shaped conductive structure (LSCS) forms gate electrodes of a first p-transistor and a first n-transistor. A second LSCS forms a gate electrode of a second p-transistor. A third LSCS forms a gate electrode of a second n-transistor, and is separated from the second LSCS by a first end-to-end spacing (EES). A fourth LSCS forms a gate electrode of a third p-transistor. A fifth LSCS forms a gate electrode of a third n-transistor, and is separated from the fourth LSCS by a second EES. A sixth LSCS forms gate electrodes of a fourth p-transistor and a fourth n-transistor. An end of the second LSCS adjacent to the first EES is offset from an end of the fourth LSCS adjacent to the second EES, and/or an end of the third LSCS adjacent to the first EES is offset from an end of the fifth LSCS adjacent to the second EES.

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08-08-2013 дата публикации

Cross-Coupled Transistor Circuit Defined on Two Gate Electrode Tracks

Номер: US20130200463A1
Принадлежит:

A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a second gate electrode track. A second PMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along the first gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node. 1a first PMOS transistor defined by a gate electrode extending along a first gate electrode track;a first NMOS transistor defined by a gate electrode extending along a second gate electrode track;a second PMOS transistor defined by a gate electrode extending along the second gate electrode track;a second NMOS transistor defined by a gate electrode extending along the first gate electrode track,wherein the gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node,wherein the gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node, andwherein each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.. A cross-coupled transistor circuit, comprising: This application is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 13/741,305, filed Jan. 14, 2013, which is a continuation application under 35 U.S.C. ...

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08-08-2013 дата публикации

Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks

Номер: US20130200464A1
Принадлежит: Individual

A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a third gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

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15-08-2013 дата публикации

Cross-Coupled Transistor Circuit Defined on Four Gate Electrode Tracks

Номер: US20130207196A1
Принадлежит:

A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a third gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a fourth gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node. 1a first PMOS transistor defined by a gate electrode extending along a first gate electrode track;a second PMOS transistor defined by a gate electrode extending along a second gate electrode track;a first NMOS transistor defined by a gate electrode extending along a third gate electrode track;a second NMOS transistor defined by a gate electrode extending along a fourth gate electrode track,wherein the gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node,wherein the gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node, andwherein each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.. A cross-coupled transistor circuit, comprising: This application is a continuation application under 35 U.S.C. 120 of prior U.S. application Ser. No. 13/741,305, filed Jan. 14, 2013, which is a continuation application under 35 U.S.C. 120 of ...

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22-08-2013 дата публикации

Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Gate Contact Position and Offset Specifications

Номер: US20130214361A1
Принадлежит: Tela Innovations, Inc.

A semiconductor device includes conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device. 1. An integrated circuit , comprising:a gate electrode level region having a number of adjacently positioned gate electrode feature layout channels, each gate electrode feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate electrode feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, wherein each gate level feature forms an electrically conductive path extending between its first and second ends,wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type,wherein the gate electrode level region includes a second gate level feature that ...

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22-08-2013 дата публикации

METHOD OF PRODUCING A DEVICE WITH TRANSISTORS STRAINED BY MEANS OF AN EXTERNAL LAYER

Номер: US20130214362A1

A method of producing a microelectronic device with transistors wherein a strain layer is formed on a series of transistors and the strain exerted on at least one given transistor of said series is released by removing a sacrificial layer situated between said given transistor and said strain layer. 1. A method of producing a microelectronic device with transistors comprising the steps of:a) forming a strain layer on a first gate block of a transistor of a first type and on first semi-conductor areas situated on either side of said first gate block, as well as on a second gate block of a transistor of a second type and on second semi-conductor areas situated on either side of said second gate block, a sacrificial layer being provided between said strain layer and said second semi-conductor areas of the transistor of the second type,b) forming openings traversing the strain layer among which one or more given openings exposing the sacrificial layer,c) removing the sacrificial layer by etching through said openings.2. The method according to claim 1 , wherein among the openings formed at step b) one or more openings revealing the first semi-conductor areas.3. The method according to claim 2 , the method moreover comprising claim 2 , after step c) claim 2 , the deposition of a metallic material through said openings claim 2 , followed by an annealing claim 2 , so as to form areas of alloy of metal and semi-conductor.4. The method according to claim 3 , wherein the type of metallic material deposited claim 3 , the volume of metallic material deposited on the first semi-conductor areas claim 3 , as well as the duration of the annealing are chosen so as to form first areas of alloy of metal and semi-conductor exerting a compressive strain on a channel area of said transistor of the first type.5. The method according to claim 3 , wherein the removal of the sacrificial layer by etching through said given openings leads to the formation of cavities between said second semi- ...

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22-08-2013 дата публикации

MANUFACTURING METHOD FOR A DEVICE WITH TRANSISTORS STRAINED BY SILICIDATION OF SOURCE AND DRAIN ZONES

Номер: US20130214363A1

A method for making a microelectronic device with transistors, in which silicided source and drain zones are formed to apply a compressive strain on the channel, in some transistors. 1: A method for making a microelectronic transistor device comprising the following steps:a) formation of a barrier layer based on a given material on first semiconducting zones located on each side of a first gate block of a first transistor, said given material being different from the material used in said first semiconducting zones,b) form openings passing through the barrier layer, one or several given openings exposing the first semiconducting zones,c) deposit a metallic material through said openings, followed by annealing, so as to form metal and semiconductor alloy zones, the volume of metallic material deposited on the first semiconducting zones, and the annealing duration being chosen so as to form first metal and semiconductor alloy zones applying a compressive strain on a channel zone of said first transistor.2: The method for making a microelectronic device according to claim 1 , the given material being designed to prevent metal diffusion during step c).3: The method for making a microelectronic device according to claim 1 , wherein in step a) claim 1 , said barrier layer is also formed on second semiconducting layers located on each side of a second gate block of a second transistor claim 1 , a sacrificial layer being provided between said given material layer and said second semiconducting zones of the transistor of the second type claim 1 , and wherein in step b) claim 1 , among openings passing through the given material layer claim 1 , one or several given openings expose the second semiconducting zones claim 1 , the method also comprising between step b) and step c) claim 1 , the removal of the barrier layer by etching through said openings claim 1 , in step c) claim 1 , said metallic deposition and said annealing being done so as to form second metal and ...

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29-08-2013 дата публикации

FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME

Номер: US20130221447A1
Принадлежит:

Provided are field effect transistors and methods of fabricating the same. The transistor may include a substrate with an active pattern, the active pattern having a top surface and two sidewalls, a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern, a gate spacer covering a sidewall of the gate electrode, a gate dielectric pattern at a bottom surface of the gate electrode, a source electrode on the active pattern at one side of the gate electrode, a drain electrode on the active pattern at another side of the gate electrode, and silicide patterns on surfaces of the source and drain electrodes, respectively. The gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern. 1. A field effect transistor , comprising:a substrate with an active pattern, the active pattern having a top surface and two sidewalls;a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern;a gate spacer covering a sidewall of the gate electrode;a gate dielectric pattern at a bottom surface of the gate electrode;a source electrode on the active pattern at one side of the gate electrode;a drain electrode on the active pattern at another side of the gate electrode; andsilicide patterns on surfaces of the source and drain electrodes, respectively,wherein the gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern.2. The transistor of claim 1 , wherein the active pattern comprises a channel region between the source and drain electrodes and below the gate electrode claim 1 , and wherein the gate electrode comprises first portions facing both sidewalls of the channel region and a second portion provided on the channel region to connect the first portions with each other.3. ...

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29-08-2013 дата публикации

Methods of Fabricating Semiconductor Devices and Structures Thereof

Номер: US20130224942A1
Принадлежит: INFINEON TECHNOLOGIES AG

Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the workpiece. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the workpiece comprising an NMOS FET of a CMOS device and a second transistor in the second region of the workpiece comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.

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12-09-2013 дата публикации

SEMICONDUCTOR DEVICE, PRINTING APPARATUS, AND MANUFACTURING METHOD THEREOF

Номер: US20130234248A1
Принадлежит: CANON KABUSHIKI KAISHA

A manufacturing method of a semiconductor device including a DMOS transistor, an NMOS transistor and a PMOS transistor arranged on a semiconductor substrate, the DMOS transistor including a first impurity region and a second impurity region formed to be adjacent to each other, the first impurity region being of the same conductivity type as a drain region and a source region of the DMOS transistor, forming to enclose the drain region, and the second impurity region being of a conductivity type opposite to the first impurity region, forming to enclose the source region, the manufacturing method of the semiconductor device comprising forming the first impurity region and one of the NMOS transistor and the PMOS transistor, and forming the second impurity region and the other of the NMOS transistor and the PMOS transistor. 1. A manufacturing method of a semiconductor device including a DMOS transistor , an NMOS transistor , and a PMOS transistor arranged on a semiconductor substrate ,the DMOS transistor including a first impurity region that is of the same conductivity type as a drain region and a source region of the DMOS transistor and has a lower impurity concentration than the drain region and the source region, and a second impurity region that is of a conductivity type opposite to the first impurity region, which are formed to be adjacent to each other in an upper surface of the semiconductor substrate, the first impurity region being formed to enclose the drain region, and the second impurity region being formed to enclose the source region,the manufacturing method of the semiconductor device, comprising:a first step of forming the first impurity region at the same time as a well of one of the NMOS transistor and the PMOS transistor; anda second step of forming the second impurity region at the same time as a well of the other of the NMOS transistor and the PMOS transistor.2. The method according to claim 1 , whereinthe DMOS transistor further includes an ...

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12-09-2013 дата публикации

Spacer Elements for Semiconductor Device

Номер: US20130234255A1
Принадлежит:

The present disclosure describes a semiconductor device including a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is disposed on the substrate abutting the first gate stack. In an embodiment, the first spacer element includes silicon nitride. A second spacer element is adjacent the first spacer element. In an embodiment, the second spacer element includes silicon oxide. A raised source and a first raised drain is provided laterally contacting sidewalls of the second spacer element. In an embodiment, a contact directly interfaces with the second spacer element. 1. A semiconductor device , comprising:a semiconductor substrate;a first gate stack disposed on the semiconductor substrate;a first spacer element abutting the first gate stack; anda second spacer element adjacent the first spacer element, wherein the second spacer element includes silicon oxide; anda first raised source/drain region laterally contacting sidewalls of the second spacer element.2. The semiconductor device of claim 1 , wherein the semiconductor substrate includes a silicon germanium (SiGe) feature underlying the first raised source/drain region.3. The semiconductor device of claim 1 , wherein the first raised source/drain region comprises epitaxial silicon.4. The semiconductor device of claim 1 , wherein the first source/drain region and the first gate stack are portions of a P metal-oxide-semiconductor (PMOS) transistor.5. The semiconductor device of claim 1 , wherein the first gate stack includes a high-k dielectric and a metal gate electrode.6. The semiconductor device of claim 1 , wherein the first spacer element has a first height and the second spacer element has a second height claim 1 , and the first height is greater than the second height.7. The semiconductor device of claim 1 , wherein the first spacer element includes silicon nitride.8. The semiconductor device of claim 1 , further comprising:a contact disposed on the ...

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19-09-2013 дата публикации

Graphene Channel-Based Devices and Methods for Fabrication Thereof

Номер: US20130240839A1

Graphene-channel based devices and techniques for the fabrication thereof are provided. In one aspect, a semiconductor device includes a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; and a second wafer having a CMOS device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the wafers being bonded together by way of an oxide-to-oxide bond between the oxide layers. One or more of the contacts to the CMOS device layer are in contact with the source and drain contacts. One or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel. 1. A semiconductor device , comprising:a first wafer having at least one graphene channel formed on a first substrate, a first oxide layer surrounding the graphene channel and source and drain contacts to the graphene channel that extend through the first oxide layer; anda second wafer having a complementary metal oxide semiconductor (CMOS) device layer formed in a second substrate, a second oxide layer surrounding the CMOS device layer and a plurality of contacts to the CMOS device layer that extend through the second oxide layer, the first wafer and the second wafer being bonded together by way of an oxide-to-oxide bond between the first and second oxide layers,wherein one or more of the contacts to the CMOS device layer are in contact with the source and drain contacts to the graphene channel, and wherein one or more other of the contacts to the CMOS device layer are gate contacts for the graphene channel.2. The device of claim 1 , wherein the CMOS device layer comprises one or more CMOS wiring claim 1 , structures and devices.3. The device of claim 1 , wherein the first substrate ...

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19-09-2013 дата публикации

GATE STRUCTURES

Номер: US20130240979A1
Принадлежит:

A semiconductor device is provided. The device includes a semiconductor substrate, first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein, and a first gate structure engaging the first projection adjacent the first channel region. The first gate structure includes a first dielectric material over the first channel region, a first opening over the first dielectric material and the first channel region, and a pure first metal with an n-type work function value conformally deposited in the first opening. The device also includes a second gate structure engaging the second projection adjacent the second channel region. The second gate structure includes a second dielectric material over the second channel region, a second opening over the second dielectric material and the second channel region, and a pure second metal with a p-type work function value conformally deposited in the second opening. 1. A semiconductor device , comprising:a semiconductor substrate;first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein; a first dielectric material over the first channel region;', 'a first opening over the first dielectric material and the first channel region; and', 'a pure first metal with an n-type work function value and a low resistivity conformally deposited in the first opening;, 'a first gate structure engaging the first projection adjacent the first channel region, the first gate structure including a second dielectric material over the second channel region;', 'a second opening over the second dielectric material and the second channel region; and', 'a pure second metal with a p-type work function value and a low resistivity conformally deposited in the second opening., 'a second gate structure engaging the second projection adjacent the second channel region, the second gate structure ...

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19-09-2013 дата публикации

EFFECTING SELECTIVITY OF SILICON OR SILICON-GERMANIUM DEPOSITION ON A SILICON OR SILICON-GERMANIUM SUBSTRATE BY DOPING

Номер: US20130240999A1
Принадлежит:

A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. Several devices are, thus, provided. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art. 1. A semiconductor device , comprising:a semiconductor substrate layer having a first active region and a second active region, said first and second active regions separated from each other by an isolating region;a first gate dielectric on a top surface of the first active region;a second gate dielectric on a top surface of the second active region;a first gate electrode for a first transistor positioned on the first gate dielectric with sidewall spacers;a second gate electrode for a second transistor positioned on the second gate dielectric with sidewall spacers;a source region and drain region formed of the first active region on either side of the first gate electrode;a source region and drain region formed of the second active region on either side of the second gate electrode;wherein said source region and drain region formed of the first active region are elevated above said source region and drain region formed of the second active region.2. The semiconductor device of claim 1 , wherein the first transistor is an NMOS ...

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26-09-2013 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20130248946A1
Автор: Fumitake Mieno
Принадлежит:

A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region. 1. A fin semiconductor device , comprising:a fin including a semiconductor layer formed on a substrate;an insulating material layer formed over the substrate and surrounding the fin, the insulating material layer having a thickness less than the thickness of the semiconductor layer;a source region portion and a drain region portion formed on the insulating material layer; anda first channel control region, a second channel control region and a channel region between the source region portion and the drain region portion,wherein the first channel control region is at a center of the semiconductor layer away from the edge and has a first conductivity type,wherein the second channel control region is formed along an edge of the semiconductor layer in a portion of the semiconductor layer that is not covered by the insulating material layer, the second channel control region having the first conductivity type,wherein the channel region is between the first channel control region and the second channel control region, adjoining the source region portion and the drain region portion, wherein the channel region, the source region portion and the drain region portion have a second conductivity type which is opposite to the first conductivity type.2. The semiconductor device of further comprising:a gate for the fin, the gate ...

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26-09-2013 дата публикации

Short channel semiconductor devices with reduced halo diffusion

Номер: US20130249000A1
Автор: Bin Yang, Man Fai NG
Принадлежит: Globalfoundries Inc

A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off.

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26-09-2013 дата публикации

Metal gate semiconductor device

Номер: US20130249010A1

Provided is a method and device that includes providing for a plurality of differently configured gate structures on a substrate. For example, a first gate structure associated with a transistor of a first type and including a first dielectric layer and a first metal layer; a second gate structure associated with a transistor of a second type and including a second dielectric layer, a second metal layer, a polysilicon layer, the second dielectric layer and the first metal layer; and a dummy gate structure including the first dielectric layer and the first metal layer.

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26-09-2013 дата публикации

Integrated Circuit Including Linear Gate Electrode Structures Having Different Extension Distances Beyond Contact

Номер: US20130249013A1
Принадлежит:

A first linear-shaped conductive structure (LSCS) forming gate electrodes of both a first p-transistor and a first n-transistor. A second LSCS forming a gate electrode of a second p-transistor and including an extension portion extending away therefrom. A third LSCS forming a gate electrode of a second n-transistor and including an extension portion extending away therefrom. A fourth LSCS forming a gate electrode of a third p-transistor and including an extension portion extending away therefrom. A fifth LSCS forming a gate electrode of a third n-transistor and including an extension portion extending away therefrom. A sixth LSCS forming gate electrodes of both a fourth p-transistor and a fourth n-transistor. Four contact structures respectively contacting the extension portions of the second, third, fourth, and fifth LSCS's, such that at least two of the extension portions extend different distances beyond their contact structure. 1. An integrated circuit , comprising:a first linear-shaped conductive structure forming gate electrodes of both a first p-transistor and a first n-transistor;a second linear-shaped conductive structure that 1) forms a gate electrode of a second p-transistor and does not form any gate electrode of any n-transistor, and 2) is positioned next to and spaced apart from the first linear-shaped conductive structure, and 3) includes an extension portion extending away from the gate electrode of the second p-transistor;a third linear-shaped conductive structure that 1) forms a gate electrode of a second n-transistor and does not form any gate electrode of any p-transistor, and 2) is positioned next to and spaced apart from the first linear-shaped conductive structure, and 3) includes an extension portion extending away from the gate electrode of the second n-transistor;a fourth linear-shaped conductive structure that 1) forms a gate electrode of a third p-transistor and does not form any gate electrode of any n-transistor, and 2) includes an ...

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26-09-2013 дата публикации

DUMMY GATE CELL, CELL-BASED IC, LAYOUT SYSTEM AND LAYOUT METHOD OF CELL-BASED IC, AND PORTABLE DEVICE

Номер: US20130249014A1
Автор: Kito Yoshiharu
Принадлежит:

A dummy gate cell includes an nMOS transistor and a pMOS transistor which constitute a CMOS inverter, wherein a drain electrode of the nMOS transistor and a drain electrode of the pMOS transistor are not connected and the dummy gate cell is disposed in an unused area not occupied by a basic cell in a cell-based IC. 1. A dummy gate cell , comprising:an nMOS transistor; anda pMOS transistor,wherein the nMOS transistor and the pMOS transistor constitute a CMOS inverter, a drain electrode of the nMOS transistor and a drain electrode of the pMOS transistor are not connected, and the dummy gate cell is disposed in an unused area not occupied by a basic cell in a cell-based IC.2. A cell-based integrated circuit (IC) , comprising:a semiconductor substrate;a plurality of basic cells formed on the semiconductor substrate to have a plurality of semiconductor devices and internal wirings, and having a predetermined function provided by connecting the semiconductor devices using the internal wirings;a wiring region formed on the semiconductor substrate and having an external wiring to connect the basic cells;a power source wiring configured to supply power to the semiconductor devices, and a ground wiring; anda dummy gate cell formed on the semiconductor substrate and having an nMOS transistor and a pMOS transistor which constitute a CMOS inverter,wherein a drain electrode of the nMOS transistor and a drain electrode of the pMOS transistor are not connected, the dummy gate cell is disposed in an unused area not occupied by the basic cells, and a gate electrode of the dummy gate cell is connected to a wiring between the basic cells.3. The cell-based IC of claim 2 , wherein a source electrode of the pMOS transistor constituting the dummy gate cell is connected to the power source wiring claim 2 , and a source electrode of the nMOS transistor is connected to the ground wiring.4. The cell-based IC of claim 2 , wherein the dummy gate cell comprises an antenna diode claim 2 , a ...

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26-09-2013 дата публикации

SEMICONDUCTOR DEVICES WITH DIFFERENT DIELECTRIC THICKNESSES

Номер: US20130249015A1
Принадлежит: Freescale Semiconductor, Inc.

An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon. 115-. (canceled)16. An integrated circuit , comprising: a first layer comprising at least one of a group consisting of germanium and carbon; and', 'a first cap layer overlying the first layer, the first cap layer comprising silicon and substantially no carbon or germanium, and the first cap layer having a first thickness;, 'a first semiconductor device having a first active region underlying a first electrode stack, wherein the first active region comprises a second layer comprising at least one of the group consisting of germanium and carbon; and', 'a second cap layer overlying the second layer, the second cap layer comprising silicon and substantially no carbon or germanium, and the second cap layer having a second thickness,, 'a second semiconductor device having a second active region underlying a second electrode stack, wherein the second active region compriseswherein the first semiconductor device and the second semiconductor device have a same conductivity type, and wherein the first thickness and the second thickness are different.17. An integrated circuit as in claim 16 , wherein the first semiconductor device comprises a first p-channel transistor claim 16 , and wherein the second semiconductor device comprises a second p-channel transistor.18. An integrated circuit as in claim 16 , wherein the first electrode stack comprises a first electrode dielectric claim 16 , the first electrode dielectric including a first high-k dielectric layer overlying the first cap layer claim 16 , wherein the second electrode stack comprises a second ...

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26-09-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING ANALOG TRANSISTOR WITH IMPROVED OPERATING AND FLICKER NOISE CHARACTERISTICS AND METHOD OF MAKING SAME

Номер: US20130249016A1
Принадлежит:

A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1. 1a substrate including a strained-channel analog NMOS transistor and a strained-channel analog PMOS transistor;{'sup': 21', '3, 'a first etch stop liner (ESL) which extends over a top surface of the substrate and has a hydrogen concentration of less than 1×10/cm; and'}a gate of the strained-channel analog NMOS transistor disposed between the first ESL and the substrate,wherein a gate of the strained-channel analog PMOS transistor is disposed between the first ESL and the substrate.. A semiconductor device comprising: This is a divisional of application Ser. No. 13/091,327, filed Apr. 21, 2011, which is a divisional of application Ser. No. 11/802,281 filed on May 22, 2007, now U.S. Pat. No. 7,952,147, issued May 31, 2011, which is incorporated herein by reference in its entirety.1. Field of the InventionEmbodiments of the present invention relate to a semiconductor device and a method of fabrication and more particularly to a semiconductor device with improved flicker noise characteristics.This U.S non-provisional patent application claims priority under 35 U.S.C §119 of Korean Patent Application 10-2006-0045709 filed on May 22, 2006 the entire contents of which are hereby incorporated by reference.2. Discussion of Related ArtDevice sizes are becoming smaller and smaller in today's semiconductor manufacturing processes. Because of these size reductions, methods of enhancing the mobility of electrons ...

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03-10-2013 дата публикации

Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same

Номер: US20130256801A1

During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.

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03-10-2013 дата публикации

SEMICONDUCTOR DEVICE INCLUDING CONTACT HOLES AND METHOD FOR FORMING THE SAME

Номер: US20130256806A1
Автор: Huang Yi, WANG Xinpeng

A semiconductor device including contact holes and method for forming the same are provided. A dual-stress liner is formed on a substrate. A first, second and third dielectric layers are then formed over the dual-stress liner. The second dielectric layer has a top surface leveling with that of an overlapping portion of the dual-stress liner. The third dielectric layer is etched to form first openings to have the etching stop at the second dielectric layer and at the upper stress liner of the overlapping portion. The second dielectric layer, the first dielectric layer and the upper stress liner are etched along the first openings to form second openings having the etching stop at the lower stress liner of the overlapping portion and the dual-stress liner in other regions. The stress liners are etched to form contact holes. 1. A method for forming a semiconductor device comprising contact holes , comprising:forming a dual-stress liner over a substrate, wherein the dual-stress liner comprises a first stress liner and a second stress liner having opposite stress types and partially overlapped to form an overlapping portion, the overlapping portion comprising an upper stress liner formed by a portion of one of the first and second stress liners and a lower stress liner formed by a portion of an other of the first and second stress liners;forming a first dielectric layer over the dual-stress liner, a second dielectric layer over the first dielectric layer, and a third dielectric layer over the second dielectric layer, wherein the second dielectric layer has a top surface leveling with a top surface of the overlapping portion;etching the third dielectric layer with an etching selectivity over the second dielectric layer and over the upper stress liner to form a plurality of first openings through the third dielectric layer to expose the second dielectric layer and an upper stress liner in the overlapping portion;forming a plurality of second openings through the second and ...

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10-10-2013 дата публикации

Cost-Effective Gate Replacement Process

Номер: US20130264652A1

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device.

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