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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Применить Всего найдено 36. Отображено 27.
25-04-2017 дата публикации

Third type of metal gate stack for CMOS devices

Номер: US0009634006B2
Автор: Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman, DIVAKARUNI RAMACHANDRA, JAIN SAMEER H, SARDESAI VIRAJ Y, TABAKMAN KEITH H, Divakaruni Ramachandra, Jain Sameer H., Sardesai Viraj Y., Tabakman Keith H.
Принадлежит: International Business Machines Corporation, IBM

A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.

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Номер записи: 1
13-03-2018 дата публикации

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Номер: US0009917190B2
Автор: Eric C. Harley, Judson R. Holt, Yue Ke, Rishikesh Krishnan, Keith H. Tabakman, Henry K. Utomo, HARLEY ERIC C, HOLT JUDSON R, KE YUE, KRISHNAN RISHIKESH, TABAKMAN KEITH H, UTOMO HENRY K, Harley Eric C., Holt Judson R., Ke Yue, Krishnan Rishikesh, Tabakman Keith H., Utomo Henry K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION, IBM

A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

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Номер записи: 2
07-11-2017 дата публикации

Contact line having insulating spacer therein and method of forming same

Номер: US0009812400B1
Автор: Veeraraghavan S. Basker, Keith H. Tabakman, Patrick D. Carpenter, Guillaume Bouche, Michael V. Aquilino, BASKER VEERARAGHAVAN S, TABAKMAN KEITH H, CARPENTER PATRICK D, BOUCHE GUILLAUME, AQUILINO MICHAEL V, Basker Veeraraghavan S., Tabakman Keith H., Carpenter Patrick D., Bouche Guillaume, Aquilino Michael V.
Принадлежит: GLOBALFOUNDRIES INC, GLOBALFOUNDRIES INC.

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer.

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Номер записи: 3
10-08-2017 дата публикации

THIRD TYPE OF METAL GATE STACK FOR CMOS DEVICES

Номер: US20170229458A1
Автор: Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman, DIVAKARUNI RAMACHANDRA, JAIN SAMEER H, SARDESAI VIRAJ Y, TABAKMAN KEITH H, Divakaruni Ramachandra, Jain Sameer H., Sardesai Viraj Y., Tabakman Keith H.
Принадлежит: International Business Machines Corporation

A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack. 1. A semiconductor structure comprising:a first conductivity-type field effect transistor including a first type of metal gate stack located above a first semiconductor material layer portion of a substrate;a second conductivity-type field effect transistor including a second type of metal gate stack located above a second semiconductor material layer portion of said substrate, wherein said second conductivity type is of a different conductivity type than said first conductivity type; anda third type of metal gate stack located above a trench isolation structure that is positioned between said first semiconductor material layer portion and said semiconductor material layer portion, wherein said third type of metal gate stack comprises a portion of a first workfunction material layer of said first conductivity-type field effect transistor, a portion of a second workfunction material layer of said second conductivity-type field effect transistor, and a low resistance metal layer, wherein said low resistance metal layer has an uppermost surface that is substantially ...

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Номер записи: 4
03-05-2012 дата публикации

Method for growing strain-inducing materials in cmos circuits in a gate first flow

Номер: US20120104507A1
Автор: Abhishek Dube, Bo Bai, Judson R. Holt, Kathryn T. Schonenberg, Keith H. Tabakman, Linda Black, Matthew W. Stoker, Viorel C. Ontalus
Принадлежит: International Business Machines Corp

A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.

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Номер записи: 5
10-05-2012 дата публикации

STRESSED TRANSISTOR WITH IMPROVED METASTABILITY

Номер: US20120112208A1
Автор: Adam Thomas N., Bedell Stephen W., DUBE ABHISHEK, Harley Eric C.T., Holt Judson R., Reznicek Alexander, Sadana Devendra K., Schepis Dominic J., Stoker Matthew W., Tabakman Keith H.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material. 1. A method of fabricating a semiconductor structure comprising:forming at least one field effect transistor within an active device region of a semiconductor substrate, said at least one field effect transistor including a patterned gate stack, a source region and a drain region;forming a dielectric material on exposed surfaces of said semiconductor substrate and surrounding the at least one field effect transistor, said dielectric material having at least one set of contact openings that exposes an upper surface of the source region and the drain region;removing at least a portion of the exposed source region and drain region forming a trench in each of the source region and the drain region; andfilling at least the trench in the source region and the drain region with a strained epitaxial semiconductor material.2. The method of wherein said forming the at least one field effect transistor includes recessing the source region and the drain region claim 1 , and filling the recessed source region and drain region with a sacrificial epitaxial semiconductor material.3. The method of wherein said removing at least portion of the exposed source region and the exposed drain region includes completely removing said sacrificial epitaxial semiconductor material.4. The method of wherein said removing at least a portion of the exposed source region and drain region includes isotropic etching claim 1 , anisotropic etching or a combination ...

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Номер записи: 6
13-09-2012 дата публикации

SELF ALIGNED DEVICE WITH ENHANCED STRESS AND METHODS OF MANUFACTURE

Номер: US20120228639A1
Автор: Holt Judson R., Ontalus Viorel C., Tabakman Keith H.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer. 1. A structure comprisinga stressed Si layer in a trench formed in a stress layer deposited on a substrate, the stressed Si layer is an active channel region of a device and the stress layer has a lattice constant different than the stressed Si layer; anda gate structure formed in the active channel region formed from the stressed Si layer, the gate structure comprising a dielectric material formed on the stressed Si layer, a gate body and spacers formed on the side of the gate body.2. The structure of claim 1 , wherein the active channel region includes a well having a variable concentration of different dopant concentration at a top versus at bottom.3. The structure of claim 1 , wherein the stress layer is an epitaxial stressor material deposited on the substrate.4. The structure of claim 3 , wherein the epitaxial stressor material is a compressive stress material.5. The structure of claim 4 , wherein the compressive stress material comprises SiGe.6. The structure of claim 3 , wherein the epitaxial stressor material is a tensile stress material.7. The structure of claim 6 , wherein the tensile stress material comprises SiC.8. The structure of claim 1 , wherein the stressed Si layer is an embedded Si island surrounded by the stress layer.9. The structure of claim 1 , wherein the gate structure is a self aligned gate structure.10. The structure of claim 9 , wherein the dielectric material is a high-k dielectric material.11. The structure of claim 10 , wherein the gate body comprises metal.12. The structure of claim 10 , wherein the gate body comprises polysilicon.13. The structure of claim 9 , wherein the spacers are provided on a sidewall of the trench.14. The structure of claim ...

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Номер записи: 7
30-05-2013 дата публикации

STRESSED TRANSISTOR WITH IMPROVED METASTABILITY

Номер: US20130134444A1
Автор: Adam Thomas N., Bedell Stephen W., DUBE ABHISHEK, Harley Eric C. T., Holt Judson R., Reznicek Alexander, Sadana Devendra K., Schepis Dominic J., Stoker Matthew W., Tabakman Keith H.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material. 1. A semiconductor structure comprising:at least one field effect transistor located within an active device region of a semiconductor substrate, said at least one field effect transistor comprising a patterned gate stack, a source region and a drain region, wherein at least a portion of said source region and a portion of said drain region include a metastable strained epitaxial semiconductor material disposed therein;a dielectric material located on exposed surfaces of the semiconductor substrate and surrounding the at least one field effect transistor, said dielectric material having contact openings that expose an upper surface of said metastable strained epitaxial semiconductor material; anda conductive contact material located within said contact openings and directly on an upper surface of said metastable strained epitaxial semiconductor material.2. The semiconductor structure of wherein said at least one field effect transistor is a pFET and said strained epitaxial semiconductor material consists essentially of SiGe.3. The semiconductor structure of wherein said SiGe contains a Ge content of from 15 atomic % to 60 atomic %.4. The semiconductor structure of wherein said at least one field effect transistor is a pFET and said strained epitaxial semiconductor material consists essentially of SiGe:C.5. The semiconductor structure of wherein said SiGe:C contains a C content from 0.5 atomic % to 3.0 atomic %.6. The semiconductor ...

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Номер записи: 8
27-06-2013 дата публикации

Method for growing strain-inducing materials in cmos circuits in a gate first flow

Номер: US20130161759A1
Автор: Abhishek Dube, Bo Bai, Judson R. Holt, Kathryn T. Schonenberg, Keith H. Tabakman, Linda Black, Matthew W. Stoker, Viorel C. Ontalus
Принадлежит: Globalfoundries Inc, International Business Machines Corp

A complementary metal oxide semiconductor (CMOS) circuit incorporating a substrate and a gate wire over the substrate. The substrate comprises an n-type field effect transistor (n-FET) region, a p-type field effect transistor (p-FET) region and an isolation region disposed between the n-FET and p-FET regions. The gate wire comprises an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate. A first conformal insulator covers the gate wire and a second conformal insulator is on the first conformal insulator positioned over the p-FET gate without extending laterally over the n-FET gate. Straining regions for producing different types of strain are formed in recess etched into the n-FET and p-FET regions of the substrate.

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Номер записи: 9
11-07-2013 дата публикации

FIELD EFFECT TRANSISTOR DEVICE

Номер: US20130175547A1
Автор: Black Linda R., Chan Kevin K., DUBE ABHISHEK, Harley Eric C., Holt Judson R., Ontalus Viorel C., SCHONENBERG Kathryn T., Stoker Matthew W., Tabakman Keith H.
Принадлежит:

A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material. 1. A field effect transistor device comprising:a gate stack portion disposed on a substrate;a first cavity region in the substrate arranged on a first side of the gate stack portion;a second cavity region in the substrate arranged on a second side of the gate stack portion;a first epitaxially grown silicon material disposed in the first cavity region and the second cavity region; anda second epitaxially grown silicon material disposed in the first cavity region and the second cavity region, the second epitaxially grown silicon material in contact with the first epitaxially grown silicon material.2. The device of claim 1 , wherein the first epitaxially grown silicon material defines a planar surface on the first silicon material orientated along a [1 claim 1 ,1 claim 1 ,1] Miller index axis of the first silicon material.3. The device of claim 1 , wherein the first side of the gate stack portion opposes the second side of the gate stack portion.4. The device of claim 1 , wherein the first epitaxially grown silicon material includes a stress portion defined by the substrate claim 1 , a channel region of the device claim 1 , and a planar surface on the first silicon material orientated along a [1 claim 1 ,1 claim 1 ,1] Miller index axis of the first silicon material.5. The device of claim 1 , wherein the second epitaxially grown silicon material is a doped SiGe material.6. The device of claim 1 , wherein the first ...

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Номер записи: 10
20-03-2014 дата публикации

Semiconductor Device and Method With Greater Epitaxial Growth on 110 Crystal Plane

Номер: US20140077275A1
Автор: Adam Thomas N., Cheng Kangguo, Holt Judson R., Reznicek Alexander, Tabakman Keith H.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A semiconductor processing method is provided which promotes greater growth on <110> crystallographic planes than on other crystallographic planes. Growth rates with the process can be reversed compared to typical epitaxial growth processes such that the highest rate of growth occurs on <110> crystallographic planes and the least amount of growth occurs on <100> crystallographic planes. The process can be applied to form embedded stressor regions in planar field effect transistors, and the process can be used to grow semiconductor layers on exposed wall surfaces of adjacent fins in source-drain regions of finFETs to fill spaces between the fins. 1. A semiconductor processing method , comprising:epitaxially growing a semiconductor layer on a first surface of a first semiconductor region, the first surface oriented in a <110> crystallographic plane of the first semiconductor region, and the first surface extending in direction away from a second surface oriented in a <100> crystallographic plane of the first semiconductor region, the epitaxially growing performed under conditions which promote higher growth rate on the <110> crystallographic plane than on the <100> crystallographic plane so as to grow the semiconductor layer on the first surface at a location spaced from the second surface to a first thickness in a first direction normal to the first surface and to a second thickness less than the first thickness on the second surface at a location spaced from the first surface, the second thickness being in a second direction normal to the second surface.2. The method of claim 1 , wherein the first thickness of the semiconductor layer is at least five times greater than the second thickness.3. The method of claim 1 , wherein the first surface is an interior sidewall of a trench formed in the first semiconductor region and the second surface is a lower interior surface of the trench.4. The method of claim 1 , wherein the step of epitaxially growing the semiconductor ...

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Номер записи: 11
04-02-2016 дата публикации

Finfet with dielectric isolation after gate module for improved source and drain region epitaxial growth

Номер: US20160035878A1
Автор: Eric C. Harley, Henry K. Utomo, Judson R. Holt, Keith H. Tabakman, Rishikesh Krishnan, Yue Ke
Принадлежит: International Business Machines Corp

A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

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Номер записи: 12
27-02-2020 дата публикации

Finfet with dielectric isolation after gate module for improved source and drain region epitaxial growth

Номер: US20200066908A1
Автор: Eric C. Harley, Henry K. Utomo, Judson R. Holt, Keith H. Tabakman, Rishikesh Krishnan, Yue Ke
Принадлежит: International Business Machines Corp

A device and method for forming a semiconductor device includes forming a gate structure on a channel region of fin structures and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

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Номер записи: 13
05-04-2018 дата публикации

Finfet with dielectric isolation after gate module for improved source and drain region epitaxial growth

Номер: US20180097113A1
Автор: Eric C. Harley, Henry K. Utomo, Judson R. Holt, Keith H. Tabakman, Rishikesh Krishnan, Yue Ke
Принадлежит: International Business Machines Corp

A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

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Номер записи: 14
31-07-2014 дата публикации

PRE-GATE, SOURCE/DRAIN STRAIN LAYER FORMATION

Номер: US20140213029A1
Автор: Holt Judson R., Ontalus Viorel C., Tabakman Keith H.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator. 1. A method of producing a transistor , said method comprising:forming a base layer on a substrate;forming a strain-producing layer on said base layer;removing at least one portion of said strain-producing layer to create at least one opening in said strain-producing layer and leave first and second portions of said strain-producing layer on said base layer, said first and second portions of said strain-producing layer comprising source and drain stressor regions of said transistor;growing a channel region in said opening of said strain-producing layer from said base layer;forming a gate insulator on said channel region;forming a gate conductor on said gate insulator after forming said source and drain stressor regions, said channel region, and said gate insulator, wherein said gate conductor being on top of and vertically overlapping with said source and drain stressor regions; andafter forming said gate conductor, forming sidewall spacers adjacent sidewalls of said gate conductor.2. The method according to claim 1 , further comprising forming shallow trench isolation regions one of:before forming said strain-producing layer;after forming said strain-producing layer and before removing said portion of said strain-producing layer; andafter said growing of said channel region and before said forming of said gate conductor.3. The method according to ...

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Номер записи: 15
02-05-2019 дата публикации

METHODS FOR FORMING IC STRUCTURE HAVING RECESSED GATE SPACERS AND RELATED IC STRUCTURES

Номер: US20190131424A1
Автор: ONISHI Katsunori, Patil Suraj K., Tabakman Keith H., Xu Guowei, Zang Hui
Принадлежит:

The present disclosure relates to methods for forming IC structures having recessed gate spacers and related IC structures. A method may include: forming a first and second dummy gate over a fin, each dummy gate having gate spacers disposed on sidewalls thereof such that an opening is disposed between a first gate spacer and a second gate spacer, the opening exposing a source/drain region; recessing the first and second gate spacers; forming an etch stop layer within the opening such that the etch stop layer extends vertically along the recessed first and second gate spacers; forming a dielectric fill over the etch stop layer to substantially fill the opening; replacing the first and second dummy gates with first and second RMG structures; recessing the first and second RMG structures; and forming a gate cap layer over the first and second RMG structures. 1. A method for forming an integrated circuit structure , the method comprising:forming a first dummy gate over a fin and forming a second dummy gate over the fin, each dummy gate having gate spacers disposed on sidewalls thereof such that an opening is disposed between a first gate spacer of the first dummy gate and a second gate spacer of the second dummy gate, the opening exposing a source/drain region within the fin;recessing a height of the first gate spacer and the second gate spacer to a reduced height below a height of the first dummy gate and the second dummy gate;forming an etch stop layer within the opening over the exposed source/drain region such that the etch stop layer extends vertically along the recessed first gate spacer and the recessed second gate spacer;forming a dielectric fill over the etch stop layer within the opening and on the etch stop layer to substantially fill the opening;replacing the first dummy gate with a first replacement metal gate (RMG) structure and replacing the second dummy gate with a second RMG structure;recessing the first RMG structure and the second RMG structure; ...

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Номер записи: 16
14-05-2020 дата публикации

Apparatus and method for aligning integrated circuit layers using multiple grating materials

Номер: US20200152498A1
Автор: Dongyue YANG, Guanchen He, Keith H. Tabakman, Xintuo Dai, Xueli Hao
Принадлежит: Globalfoundries Inc

Embodiments of the disclosure provides an apparatus for aligning layers of an integrated circuit (IC), the apparatus including: an insulator layer positioned above a semiconductor substrate; a first diffraction grating within a first region of the insulator layer, the first diffraction grating including a first grating material within the first region of the insulator layer; and a second diffraction grating within a second region of the insulator layer, the second grating including a second grating material within the second region of the insulator layer, wherein the second grating material is different from the first grating material, and wherein an optical contrast between the first and second grating materials is greater than an optical contrast between the second grating material and the insulator layer.

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Номер записи: 17
07-07-2016 дата публикации

Finfet with dielectric isolation after gate module for improved source and drain region epitaxial growth

Номер: US20160197186A1
Автор: Eric C. Harley, Henry K. Utomo, Judson R. Holt, Keith H. Tabakman, Rishikesh Krishnan, Yue Ke
Принадлежит: International Business Machines Corp

A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

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Номер записи: 18
04-07-2019 дата публикации

THIRD TYPE OF METAL GATE STACK FOR CMOS DEVICES

Номер: US20190206866A1
Автор: Divakaruni Ramachandra, Jain Sameer H., Sardesai Viraj Y., Tabakman Keith H.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack. 1. A semiconductor structure comprising:a first conductivity-type field effect transistor including a first type of metal gate stack located above a first semiconductor material layer portion of a substrate;a second conductivity-type field effect transistor including a second type of metal gate stack located above a second semiconductor material layer portion of said substrate, wherein said second conductivity type is of a different conductivity type than said first conductivity type; anda third type of metal gate stack located above a trench isolation structure that is positioned between said first semiconductor material layer portion and said semiconductor material layer portion, wherein said third type of metal gate stack comprises a portion of a first workfunction metal layer of said first conductivity-type field effect transistor, a portion of a second workfunction metal layer of said second conductivity-type field effect transistor, and a low resistance metal layer, wherein said low resistance metal layer has an uppermost surface that is substantially ...

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Номер записи: 19
03-09-2015 дата публикации

THIRD TYPE OF METAL GATE STACK FOR CMOS DEVICES

Номер: US20150249086A1
Автор: Divakaruni Ramachandra, Jain Sameer H., Sardesai Viraj Y., Tabakman Keith H.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack. 1. A semiconductor structure comprising:a first conductivity-type field effect transistor including a first type of metal gate stack located above a first semiconductor material layer portion of a substrate;a second conductivity-type field effect transistor including a second type of metal gate stack located above a second semiconductor material layer portion of said substrate, wherein said second conductivity type is of a different conductivity type than said first conductivity type; anda third type of metal gate stack located above a trench isolation structure that is positioned between said first semiconductor material layer portion and said semiconductor material layer portion, wherein said third type of metal gate stack comprises a portion of a first workfunction material layer of said first conductivity-type field effect transistor, a portion of a second workfunction material layer of said second conductivity-type field effect transistor, and a low resistance metal layer.2. The semiconductor structure of claim 1 , wherein said low resistance metal layer has ...

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Номер записи: 20
10-09-2015 дата публикации

Electrical fuse with bottom contacts

Номер: US20150255393A1
Автор: Dan Moy, Keith H. Tabakman, Lawrence A. Clevenger, Viraj Y. Sardesai, Zhengwen Li
Принадлежит: International Business Machines Corp

A method including forming a fuse link after a first fuse contact and a second fuse contact. The fuse link is in direct contact with both the first fuse contact and the second fuse contact. Embodiments of the invention provide an e-fuse that is capable of being connected to a device either through back end of line or by a long contact allowing for sufficient separation between the e-fuse and the device.

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Номер записи: 21
20-08-2020 дата публикации

Gate cut first isolation formation with contact forming process mask protection

Номер: US20200266286A1
Автор: Jeffrey Chee, Keith H. Tabakman, Sipeng Gu, Xiaoming Yang
Принадлежит: Globalfoundries Inc

A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner.

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Номер записи: 22
16-11-2017 дата публикации

CONTACT LINE HAVING INSULATING SPACER THEREIN AND METHOD OF FORMING SAME

Номер: US20170330834A1
Автор: AQUILINO Michael V., Basker Veeraraghavan S., Bouche Guillaume, CARPENTER Patrick D., Tabakman Keith H.
Принадлежит:

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer. 1. A method of forming contact line spacers , the method comprising:forming a liner layer within a first trench over an exposed first source/drain epitaxial region of a fin-shaped field-effect-transistor (FINFET) to substantially line the first trench, and forming the liner layer within a second trench over an exposed second source/drain epitaxial region of the FINFET to substantially line the second trench;forming a sacrificial material over the liner layer within the first trench and the second trench to substantially fill the first trench and the second trench;removing a portion of the sacrificial material and a portion of the liner layer from the first trench to expose a first portion of the first source/drain epitaxial region thereunder and from the second trench to expose a second portion of the second source/drain epitaxial region thereunder;forming a dielectric film over the exposed first portion of the first source/drain epitaxial region within the first trench to form a first contact line spacer, and forming the dielectric film over the exposed second portion of the second source/drain epitaxial region within the second trench to form a second contact line spacer; andplanarizing to a top surface of the dielectric layer.2. The method of claim 1 , further comprising claim 1 , ...

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Номер записи: 23
03-12-2015 дата публикации

FINFET WITH DIELECTRIC ISOLATION AFTER GATE MODULE FOR IMPROVED SOURCE AND DRAIN REGION EPITAXIAL GROWTH

Номер: US20150349093A1
Автор: Harley Eric C., Holt Judson R., KE YUE, Krishnan Rishikesh, Tabakman Keith H., Utomo Henry K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures. 1. A method of forming a semiconductor device comprising:forming a gate structure on a channel region of a plurality of fin structures;forming a flowable dielectric material on a source region portion and a drain region portion of the plurality of fin structures, wherein the flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between said adjacent fin structures;exposing an upper surface of the source region portion and the drain region portion of the plurality of fin structures; andforming an epitaxial semiconductor material on the upper surface of the source region portion and the drain region portion of the plurality of fin structures.2. The method of claim 1 , wherein the forming of the gate structure on the channel region portion of the plurality of fin structures comprises:forming a sacrificial gate structure on the channel region of the fin structures prior to forming the epitaxial semiconductor material;removing the sacrificial gate structure after forming the epitaxial semiconductor material; andforming a functional gate structure on the channel region portion for the plurality of fin structures in the space formed by said removing the sacrificial gate structure.3. The method of claim 1 , wherein prior to said ...

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Номер записи: 24
28-12-2017 дата публикации

Contact line having insulating spacer therein and method of forming same

Номер: US20170373007A1
Автор: Guillaume Bouche, Keith H. Tabakman, Michael V. Aquilino, Patrick D. Carpenter, Veeraraghavan S. Basker
Принадлежит: Globalfoundries Inc

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer.

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Номер записи: 25
07-04-2020 дата публикации

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Номер: US10615279B2
Автор: Eric C. Harley, Henry K. Utomo, Judson R. Holt, Keith H. Tabakman, Rishikesh Krishnan, Yue Ke
Принадлежит: International Business Machines Corp

A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

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Номер записи: 26
26-03-2019 дата публикации

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Номер: US10243077B2
Автор: Eric C. Harley, Henry K. Utomo, Judson R. Holt, Keith H. Tabakman, Rishikesh Krishnan, Yue Ke
Принадлежит: International Business Machines Corp

A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

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Номер записи: 27