HIGH-K METAL GATE DEVICE

A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness Tthat is different from a thickness Tat the central portion of the device region. 1. A method of forming a semiconductor device comprising:providing a substrate prepared with a device region surrounded by an isolation region, the device region includes edge portions along a width direction of the device region and a central portion between the edge portions;{'sub': E', 'C, 'forming a gate electrode layer in the device region, wherein the gate electrode layer comprises a graded thickness in which a thickness Tat edge portions of the device region is different from a thickness Tat the central portion of the device region.'}2. The method of wherein forming the gate electrode with the graded thickness comprises:protecting the central portion of the gate electrode with a mask which leaves edge portions of the gate electrode exposed; and{'sub': 'E', 'thinning edge portions of the gate electrode to the thickness T.'}3. The method of wherein the mask is formed by printing the active area mask smaller.4. The method of wherein forming the gate electrode with the graded thickness comprises providing the isolation region with a top surface above a top surface of the substrate to form a raised isolation region.5. The method of wherein the gate electrode layer is formed by PVD.6. The method of wherein the top surface of the isolation region is sufficiently above the top surface of the substrate to form the gate electrode layer with the graded thickness.7. The method of wherein the top surface of the isolation region is about 40-50 Å higher than the top surface of the ...

Trench isolation structure

A trench isolation structure and method of forming the trench isolation structure are disclosed. The method includes forming a shallow trench isolation (STI) structure having an overhang and forming a gate stack. The method further includes forming source and drain recesses adjacent to the STI structure and the gate stack. The source and drain recesses are separated from the STI structure by substrate material. The method further includes forming epitaxial source and drain regions associated with the gate stack by filling the source and drain recesses with stressor material.

Structure and method for reduction of vt-w effect in high-k metal gate devices

A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices.

TRENCH ISOLATION STRUCTURE

A trench isolation structure and method of forming the trench isolation structure are disclosed. The method includes forming a shallow trench isolation (STI) structure having an overhang and forming a gate stack. The method further includes forming source and drain recesses adjacent to the STI structure and the gate stack. The source and drain recesses are separated from the STI structure by substrate material. The method further includes forming epitaxial source and drain regions associated with the gate stack by filling the source and drain recesses with stressor material. 1. A structure , comprising:a shallow trench isolation (STI) structure having an overhang in a substrate;a gate stack;source and drain recesses adjacent to the gate stack and to the STI structure and bounded by substrate material; andepitaxial source and drain regions filling the source and drain recesses with stressor material and bounded by the substrate material.2. The structure of claim 1 , wherein the STI structure is a T-shaped STI structure.3. The structure of claim 1 , wherein the STI structure includes a combination of a shallow recess of a first width forming the overhang and a deeper trench extending into the substrate claim 1 , forming remaining portions of the STI structure.4. The structure of claim 3 , wherein the shallow recess defines a facet of the epitaxial source and drain regions.5. The structure of claim 1 , wherein the STI structure comprises a stressor material grown along a sidewall of the STI.6. The structure of claim 3 , wherein the STI structure is lined with spacer sidewalls of an insulator material in the shallow recess.7. The structure of claim 6 , wherein the insulator material is one of nitride claim 6 , oxide and amorphous carbon.8. The structure of claim 6 , wherein the insulator material defines dimensions of the overhang of the STI structure.9. The structure of claim 6 , wherein the deeper trench is formed in the substrate claim 6 , through a processing window ...

Sealed shallow trench isolation region

A method for formation of a sealed shallow trench isolation (STI) region for a semiconductor device includes forming a STI region in a substrate, the STI region comprising a STI fill; forming a sealing recess in the STI fill of the STI region; and forming a sealing layer in the sealing recess over the STI fill.

FORMING FACET-LESS EPITAXY WITH SELF-ALIGNED ISOLATION

A method of forming a semiconductor structure may include preparing a continuous active layer in a region of the substrate and forming a plurality of adjacent gates on the continuous active layer. A first raised epitaxial layer may be deposited on a recessed region of the continuous active layer between a first and a second one of the plurality of gates, whereby the first and second gates are adjacent. A second raised epitaxial layer may be deposited on another recessed region of the continuous active layer between the second and a third one of the plurality of gates, whereby the second and third gates are adjacent. Using a cut mask, a trench structure is etched into the second gate structure and a region underneath the second gate in the continuous active layer. The trench is filled with isolation material for electrically isolating the first and second raised epitaxial layers. 1. A method of forming a semiconductor structure on a substrate , the method comprising:preparing a continuous active layer in a region of the substrate;forming a plurality of gates on top of the continuous active layer of the substrate;depositing a first raised epitaxial layer on a first recessed region of the continuous active layer, the first recessed region located between a first and a second one of the plurality of gates, wherein the first and the second one of the plurality of gates are adjacent;depositing a second raised epitaxial layer on a second recessed region of the continuous active layer, the second recessed region located between the second and a third one of the plurality of gates, wherein the second and the third one of the plurality of gates are adjacent;etching, using a cut mask, a trench structure into the second one of the plurality of gate structures and a region underneath the second one of the plurality of gate structures in the continuous active layer; andfilling the trench structure with isolation material, the isolation material electrically isolating the first ...

Semiconductor fin on local oxide

A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer.

STRUCTURE AND METHOD TO PREVENT EPI SHORT BETWEEN TRENCHES IN FINFET EDRAM

After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion. 1. A semiconductor structure comprising:a semiconductor fin located on a substrate;a deep trench capacitor located in a lower portion of a deep trench in the substrate;a conductive strap structure located over the deep trench capacitor, wherein the conductive strap structure comprises a stepped base portion vertically contacting the deep trench capacitor and a fin portion extending from the base portion and laterally contacting the semiconductor fin, the stepped base portion having a first recessed surface located below a topmost surface of the substrate by a first depth and a second recessed surface located below the topmost surface of the substrate by a second depth that is greater than the first depth; anda dielectric cap located over the base portion of the conductive strap structure and completely filling the deep trench.2. The semiconductor structure of claim 1 , wherein the dielectric cap laterally surrounds a lower portion of the fin portion of the conductive strap structure.3. The semiconductor structure of claim 2 , wherein a sidewall surface of the base portion of the conductive strap structure extends from the first recessed surface to the second recessed surface.4. The semiconductor structure of claim 3 , wherein the first recessed surface adjoins the fin ...

Semiconductor fin on local oxide

A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer.

TONE INVERSION METHOD AND STRUCTURE FOR SELECTIVE CONTACT VIA PATTERNING

A tone inversion method for integrated circuit (IC) fabrication includes providing a substrate with a layer of amorphous carbon over the substrate and a patterning layer over the amorphous carbon layer. The patterning layer is etched to define a first pattern of raised structures and a complementary recessed pattern that is filled with a layer of image reverse material. The first pattern of raised structures is then removed to define a second pattern of structures comprising the image reverse material. A selective etching step is used to transfer the second pattern into a dielectric layer disposed between the layer of amorphous carbon and the substrate. 1. A method for tone inversion for integrated circuit fabrication , the method comprising:forming a plurality of gate stacks over a semiconductor substrate;forming a spacer layer over sidewalls of the gate stacks;forming a dielectric layer over the spacer layers and between adjacent gate stacks;forming a patterning structure over the gate stacks, the spacer layers and the dielectric layer, the patterning structure comprising, from bottom to top, an etch stop layer, an amorphous carbon layer, an adhesion layer, an amorphous silicon layer, an optional oxide layer, and a hard mask layer;etching the hard mask layer, the optional oxide layer and the amorphous silicon layer to form a first pattern in the amorphous silicon layer;forming a layer of image reverse material over the adhesion layer and laterally adjacent to the first pattern in the amorphous silicon layer, wherein the layer of image reverse material defines a second pattern complementary to the first pattern;removing the amorphous silicon layer; andusing the image reverse material layer as a mask, etching the first pattern into the dielectric layer.2. The method of claim 1 , wherein the etch stop layer comprises silicon dioxide.3. The method of claim 1 , wherein the adhesion layer comprises SiCN.4. The method of claim 1 , wherein the hard mask layer comprises ...

CONTACT LINE HAVING INSULATING SPACER THEREIN AND METHOD OF FORMING SAME

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer. 1. A method of forming contact line spacers , the method comprising:forming a liner layer within a first trench over an exposed first source/drain epitaxial region of a fin-shaped field-effect-transistor (FINFET) to substantially line the first trench, and forming the liner layer within a second trench over an exposed second source/drain epitaxial region of the FINFET to substantially line the second trench;forming a sacrificial material over the liner layer within the first trench and the second trench to substantially fill the first trench and the second trench;removing a portion of the sacrificial material and a portion of the liner layer from the first trench to expose a first portion of the first source/drain epitaxial region thereunder and from the second trench to expose a second portion of the second source/drain epitaxial region thereunder;forming a dielectric film over the exposed first portion of the first source/drain epitaxial region within the first trench to form a first contact line spacer, and forming the dielectric film over the exposed second portion of the second source/drain epitaxial region within the second trench to form a second contact line spacer; andplanarizing to a top surface of the dielectric layer.2. The method of claim 1 , further comprising claim 1 , ...

STRUCTURE AND METHOD TO PREVENT EPI SHORT BETWEEN TRENCHES IN FINFET EDRAM

After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion. 1. A method of forming a semiconductor structure comprising:forming a deep trench extending through a top semiconductor layer, a buried insulator layer and into a handle substrate of a semiconductor-on-insulator (SOI) substrate;forming a deep trench capacitor in a lower portion of the deep trench;forming a conductive material cap over the deep trench capacitor to completely fill the deep trench;forming a laterally contacting pair of a semiconductor fin and a conductive strap structure by patterning the top semiconductor layer and the conductive material cap, wherein the conductive strap structure comprises a stepped base portion vertically contacting the deep trench capacitor and a fin portion extending from the base portion and laterally contacting the semiconductor fin; andforming a dielectric cap over the stepped base portion of the conductive strap structure to fill the deep trench.2. The method of claim 1 , wherein the stepped base portion comprises a first recessed surface located below a top surface of the buried insulator layer by a first depth and a second recessed surface located below the top surface of the buried insulator layer by a second depth greater than the first depth.3. The method of claim 2 , wherein forming the laterally contacting pair of the ...

Contact line having insulating spacer therein and method of forming same

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer.

EPITAXIAL STRUCTURES OF A SEMICONDUCTOR DEVICE HAVING A WIDE GATE PITCH

A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack. 1. A semiconductor device comprising:an array of active regions, gate stacks and substantially uniform epitaxial structures, the gate stacks including a first gate stack and a second gate stack over an active region, the second gate stack being adjacent to the first gate stack;an active pillar between the first gate stack and the second gate stack;two substantially uniform epitaxial structures between the first and second gate stacks and are separated by the active pillar; anda contact structure over the active pillar that is positioned equidistant from the first gate stack and the second gate stack.2. The semiconductor device of claim 1 , wherein the active pillar has a top surface substantially coplanar with a top surface of the active region.3. The semiconductor device of claim 1 , further comprises a dielectric segment over the active pillar.4. The semiconductor device of claim 1 , wherein the active pillar further comprises a conductive region at an upper portion of the active pillar.5. The semiconductor device of claim 1 , wherein the contact structure has a width at least as wide as the active pillar and electrically connects the two substantially uniform epitaxial structures.6. The semiconductor device of claim 1 , wherein each of the substantially uniform epitaxial structures has a top surface substantially coplanar with a top surface of the active pillar.7. The semiconductor device of claim 1 , wherein each of the substantially uniform epitaxial ...

Epitaxial structures of a semiconductor device having a wide gate pitch

A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack.

Structure and method to prevent EPI short between trenches in FINFET eDRAM

After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure having a base portion vertically contacting a deep trench capacitor embedded in a substrate and a fin portion laterally contacting the semiconductor fin, conducting spikes that are formed on the sidewalls of the deep trench are removed or pushed deeper into the deep trench. Subsequently, a dielectric cap that inhibits epitaxial growth of a semiconductor material thereon is formed over at least a portion of the base portion of the conductive strap structure. The dielectric cap can be formed either over an entirety of the base portion having a stepped structure or on a distal portion of the base portion.

Structure and method for reduction of vt-w effect in high-k metal gate devices

A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices.

Grabenisolationsstruktur

Es werden eine Grabenisolationsstruktur und ein Verfahren zum Bilden der Grabenisolationsstruktur offengelegt. Das Verfahren beinhaltet das Bilden einer flachen Grabenisolationsstruktur (STI-Struktur) mit einem Überhang und das Bilden eines Gate-Elektrodenstapels. Das Verfahren beinhaltet ferner das Bilden von Source- und Drain-Aussparungen nahe der STI-Struktur und dem Gate-Elektrodenstapel. Die Source- und Drain-Aussparungen werden durch Substratmaterial von der STI-Struktur getrennt. Das Verfahren beinhaltet ferner das Bilden epitaxialer Source- und Drain-Bereiche, die dem Gate-Elektrodenstapel zugehörig sind, durch Ausfüllen der Source- und Drain-Aussparungen mit Stressormaterial.

Semiconductor fin on local oxide

A semiconductor substrate 10 including a first epitaxial semiconductor layer 60 is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entire semiconductor substrate. A second epitaxial semiconductor layer 30 including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer 60 as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer.

Structure and method for reduction of Vt-W effect in high-k metal gate devices

Structure and method for reduction of vt-w effect in high-k metal gate devices

A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices.

Contact line having insulating spacer therein and method of forming same

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer.