Speichervorrichtung

Eine Speichervorrichtung enthält einen Peripherieschaltungsbereich, der ein erstes Substrat und Schaltungselemente auf dem ersten Substrat enthält, wobei die Schaltungselemente einen Reihendecoder enthalten; einen Zellenarraybereich, der Wortleitungen, die auf einem zweiten Substrat auf dem Peripherieschaltungsbereich gestapelt sind, und Kanalstrukturen, die sich in eine Richtung senkrecht zu einer oberen Oberfläche des zweiten Substrats erstrecken und die Wortleitungen durchdringen, enthält; und einen Zellkontaktbereich, der Zellkontakte enthält, die mit den Wortleitungen verbunden und auf beiden Seiten des Zellenarraybereichs in eine erste Richtung parallel zu der oberen Oberfläche des zweiten Substrats sind, wobei die Zellkontakte einen ersten Zellkontaktbereich und einen zweiten Zellkontaktbereich enthalten, wobei der erste und zweite Zellkontaktbereich in der ersten Richtung verschiedene Längen zueinander aufweisen. Sowohl der erste als auch der zweite Zellkontaktbereich enthält erste ...

Verfahren zur Bearbeitung eines Trägers, Verfahren zur Herstellung einer Ladungsspeicherzelle, Verfahren zur Bearbeitung eines Chips und Verfahren zum elektrischen Kontaktieren einer Abstandhalterstruktur

Ein Verfahren (100) zur Bearbeitung eines Trägers gemäß verschiedenen Ausführungsformen kann enthalten: Bilden einer Struktur über dem Träger, wobei die Struktur mindestens zwei benachbarte Bauelemente aufweist, die mit einem ersten Abstand zueinander angeordnet sind (110); Abscheiden einer Abstandhalterschicht über der Struktur, wobei die Abstandhalterschicht mit einer Dicke größer als eine Hälfte des ersten Abstandes abgeschieden werden kann, wobei die Abstandhalterschicht elektrisch leitendes Abstandhaltermaterial enthalten kann (120); Entfernen eines Teils der Abstandhalterschicht, wobei Abstandhaltermaterial der Abstandhalterschicht in einem Bereich zwischen den mindestens zwei benachbarten Bauelementen verbleiben kann (130); und elektrische Kontaktierung des verbleibenden Abstandhaltermaterials (140).

High density read only memory

Vertical memory cell with mechanical structural reinforcement

Method for forming integrated structure

Three-dimensional semiconductor device

VERTICAL DEVICE ARCHITECTURE

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device includes a semiconductor substrate, plural semiconductor columns arranged in a matrix form on the substrate, plural first conductive areas zonally formed in a column direction on the substrate between the semiconductor columns and functioning as word lines, plural second conductive areas formed at tops of the semiconductor columns, respectively, plural bit lines connecting the second conductive areas in a row direction, plural channel areas respectively formed in the semiconductor columns between the first and second conductive areas and contacting the first and second conductive areas, plural third conductive areas continuously formed via first insulating films above the substrate and opposite to the channel areas in the column direction between the semiconductor columns and functioning as control gates, and plural charge accumulation areas respectively formed via second insulating films at upper portions of the channel areas at a position higher ...

PLASMA TREATMENT METHOD AND PLASMA ASHING DEVICE

Flash memory as well as preparation method and operation method thereof

Non-volatile memory device manufacturing method

PROTECTED INTEGRATED CIRCUIT AGAINST SHORT CIRCUITS CAUSED BY THE SILICIDE.

FLASH MEMORY WITH ULTRA THIN VERTICAL BODY TRANSISTORS

3차원 반도체 장치 및 그 제조 방법

... 3차원 반도체 장치 및 그 제조 방법이 제공된다. 이 장치는 수직하게 차례로 적층된 주형막들, 적층된 주형막들 사이에 배치되는 도전 패턴, 적층된 주형막들을 수직하게 관통하는 플러깅 패턴, 도전 패턴과 플러깅 패턴 사이에 배치되는 중간개재 패턴, 그리고 중간개재 패턴에 의해 수직하게 분리되면서 주형막들과 플러깅 패턴 사이에 배치되는 보호막 패턴들을 포함한다.

3차원 반도체 장치 및 그 제조 방법

... 3차원 반도체 장치 및 그 제조 방법이 제공된다. 이 장치는 차례로 적층된 도전 패턴들을 포함하면서 하부 구조체 상에 배치되는 상부 구조체, 상부 구조체를 관통하여 하부 구조체에 연결되는 반도체 패턴, 그리고 반도체 패턴과 상부 구조체 사이에 개재된 절연 스페이서를 포함하며, 절연 스페이서의 바닥면은 수직적 위치에 있어서 하부 구조체의 가장 높은 상부면 위에 위치한다.

3차원 메모리 구조

... 3차원 메모리 구조를 제조하는 방법은, 어레이 스택을 형성하는 단계, 어레이 스택 위에 희생 재료의 층을 생성하는 단계, 희생 재료의 층 및 어레이 스택을관통하여 홀을 에칭하는 단계, 홀에 반도체 재료의 필러(pillar)를 생성하여, 필러를 공통 바디로서 사용하는 적어도 2개의 수직 스택형(stacked) 플래시 메모리 셀들을 형성하는 단계, 필러 주위의 희생 재료의 층의 적어도 일부를 제거하여, 필러의 일부를 노출시키는 단계, 및 이러한 필러의 부분을 FET(Field Effect Transistor)의 바디로서 사용하는 FET를 형성하는 단계를 포함한다.

INTEGRATED CIRCUIT DEVICE WITH LAYERED TRENCH CONDUCTORS

VERTICAL MEMORY DEVICE

A vertical memory device comprises: a substrate; a plurality of channels extending in a direction perpendicular to an upper surface of the substrate; a plurality of gate lines arranged to be spaced apart from each other along a vertical direction and a horizontal direction; common wires electrically connected to the gate lines of the same level among gate lines; and signal wires electrically connected to the gate lines through the common wires. The present invention has excellent electrical characteristics. COPYRIGHT KIPO 2017 (AA) Third direction (BB) Second direction (CC) First direction ...

DRY ETCHING METHOD

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device according to the present invention includes active pillars which protrude from a semiconductor substrate and are separately arranged in a first direction and a second direction which cross each other, a word line which is extended in the first direction between the active pillars, a drain region which is arranged on the upper sides of the active pillars, and a separation pattern which is provided between the word line and the drain region and has a lower side which is located on a lower level than the lower side of the drain region. Accordingly, the present invention can provide a memory device including a vertical channel transistor. COPYRIGHT KIPO 2017 ...

SEMICONDUCTOR MEMORY DEVICE HAVING ASYMMETRIC WORDLINE PAD

The present invention relates to a semiconductor memory device. The semiconductor memory device includes a semiconductor substrate, a first stack which is formed on the semiconductor substrate and has a plurality of first wordlines including a plurality of first wordline pads stacked in the form of steps, and a second stack which is stacked on the first stack and has a plurality of second wordlines including a plurality of second wordline pads stacked in the form of steps. The second stack may be shifted on the first stack so as to expose the sides of the plurality of first wordline pads. COPYRIGHT KIPO 2017 ...

소스들의 에지들에 인접한 소스 접촉부들을 갖는 메모리 어레이들을 포함하는 장치들

... 3-차원(3D) 메모리 디바이스들 및 이를 포함하는 시스템들을 포함하는, 다양한 장치가 본 출원에 설명된다. 일 실시예에서, 3D 메모리 디바이스는 적어도 두 개의 소스; 각각 적어도 두 개의 소스 위에 형성되고 적어도 두 개의 소스에 결합되는 적어도 두 개의 메모리 어레이; 및 각각 소스의 하나 이상의 에지에 인접한 소스 접촉부들을 사용하여 적어도 두 개의 소스에 전기적으로 결합되는 소스 전도체를 포함할 수 있다. 적어도 두 개의 메모리 어레이의 각각은 메모리 셀들, 제어 게이트들, 및 데이터 라인들을 포함할 수 있다. 소스의 에지 및 에지에 인접한 소스 접촉부들 사이에는 데이터 라인이 없다.

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, a first electrode structure on the substrate, and a first dummy structure that touches the connection region of the substrate through the first electrode structure. The first electrode structure includes a first electrode part extended in a first direction parallel to the upper surface of the substrate, a second electrode part extended in the first direction and spaced apart from the first electrode part in the second direction parallel to the upper surface of the substrate and intersecting with the first direction, and an electrode connection part provided between the first and second electrode parts. The first dummy structure passes through the electrode connection part. It is possible to independently control a voltage applied to a ground selection transistor. COPYRIGHT KIPO 2018 ...

SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELL WITH BURIED FLOATING GATE AND POINT CHANNEL REGION TO GREATLY REDUCE CELL SIZE AND PROVIDE STRENGTHENED PROGRAMMING EFFICIENCY

PURPOSE: A semiconductor memory array of a floating gate memory cell is provided to greatly reduce a cell size and provide strengthened programming efficiency by obtaining a self-aligned memory cell with a reduced size and a new structure. CONSTITUTION: A substrate is made of a semiconductor material, having the first conductivity type and a surface. A trench is formed in the surface of the substrate. The first and second spatially isolated regions are formed on the substrate, having the second conductivity type. A channel region formed in the substrate is included in an intermediated part of the first and second spatially isolated regions. A conductive floating gate has at least a lower portion that is adjacent to the first part and is disposed in a trench insulated from the first part. A conductive control gate is disposed over the second part of the channel region and is insulated from the second part. The trench includes a sidewall that meets the surface of the trench at an acute angle ...

VERTICAL MEMORY DEVICE

A vertical memory device can comprise: a substrate including a cell region and a peripheral circuit region; gate electrodes stacked on the cell region of the substrate in a vertical direction perpendicular to the upper surface of the substrate; a channel extending in the vertical direction on the cell region of the substrate and penetrating at least a portion of the gate electrodes; a first lower contact plug extending in the vertical direction on the peripheral circuit region of the substrate; a second lower contact plug extending in the vertical direction on the peripheral circuit region of the substrate and adjacent to the first lower contact plug; and a first upper wiring electrically connected to the first lower contact plug and applying a signal thereto, wherein the second lower contact plug may not be electrically connected to an upper wiring applying a signal. Therefore, the vertical memory device is able to have excellent electrical characteristics. COPYRIGHT KIPO 2018 (AA) First ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Provided is a method for manufacturing a semiconductor device having a stable structure and improved properties with ease. The method for manufacturing a semiconductor device comprises the steps of: forming an amorphous channel film; forming a diffusion prevention film on the amorphous channel film; forming an amorphous seed film on the diffusion prevention film; forming a seed film by crystallizing the amorphous seed film; and forming a channel film by crystallizing the amorphous channel film through transfer of a grain structure of the seed film to the amorphous channel film. COPYRIGHT KIPO 2018 ...

NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The present invention provides a semiconductor device capable of reducing structural distortion of a three-dimensional semiconductor device, and a manufacturing method thereof. According to an embodiment of the present invention, the semiconductor device comprises: gate laminates surrounding channel films; a common source line filling a separation region between the gate laminates adjacent to each other, and having the upper surface including first concave parts; and an insulating film for support filling the first concave parts, and having a side wall facing a part of the channel films. COPYRIGHT KIPO 2018 ...

3 Dimensional memory device stacked device chip using interposer

Three dimensional semiconductor memory device

Three Dimensional Semiconductor Device

THREE DIMENSIONAL MEMORY DEVICE AND A PROGRAMMING METHOD THEREOF, CAPABLE OF REDUCING PROGRAM DISTURBANCE

PURPOSE: A three dimensional memory device and a programming method thereof are provided to reduce a program time by simultaneously programming memory cells of two or more pages through one program operation. CONSTITUTION: A plurality of word line planes are laminated on a memory cell array(1000). A writing reading circuit simultaneously programs memory cells of two or more pages formed on a selected word line plane. A control circuit controls the program operation of a writing and reading circuit. The writing and reading circuit latches program data of two or more pages to be programmed on the memory cells. COPYRIGHT KIPO 2011 ...

NONVOLATILE MEMORY DEVICE OF A VERTICAL STRUCTURE INCLUDING A MEASUREMENT STRUCTURE

PURPOSE: A nonvolatile memory device of a vertical structure is provided to improve reliability by accurately controlling a position of the end of a gate line of a memory cell string. CONSTITUTION: A nonvolatile memory device(1000) includes a cell array region and a connection region. A cell array region is defined on a substrate(100). A dummy pattern is located in the edge of the cell array region. A plurality of conductive lines cover the dummy pattern and are vertically laminated on the substrate. The conductive lines are extended to expose the position of the dummy pattern in at least one extension direction. COPYRIGHT KIPO 2012 ...

THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

The present invention relates to a three-dimensional non-volatile memory device and a manufacturing method thereof. According to an embodiment of the present invention, the three-dimensional non-volatile memory device comprises: a substrate; semiconductor pillars arranged at prescribed intervals in a first direction parallel with a main surface of the substrate and a second direction different from the first direction; a string separation film arranged between semiconductor pillars arranged in the first direction among the semiconductor pillars, and extended in a direction perpendicular to the first direction and the main surface of the substrate; first sub-electrodes repeatedly deposited on the substrate in the perpendicular direction; second sub-electrodes electrically separated from the first sub-electrodes by the string separation film, and repeatedly deposited on the substrate in the perpendicular direction; and an information storage film between the first sub-electrodes and the semiconductor ...

APPARATUS AND METHODS INCLUDING SOURCE GATES

THREE DIMENSIONAL SEMICONDUCTOR DEVICE, AN OPERATING METHOD THEREOF, AND A MANUFACTURING METHOD THEREOF, INCLUDING A SELECTION TRANSISTOR COMPRISED OF AT LEAST ONE DEPLETION TRANSISTOR AND AT LEAST ONE ACTIVE TRANSISTOR

PURPOSE: A semiconductor device, an operating method thereof, and a manufacturing method thereof are provided to select one of cell strings using difference between threshold voltages of the depletion and active transistors. CONSTITUTION: A three dimensional semiconductor device includes a first wiring structure(BLP), a second wiring structure(CSP), and a cell string(STR). The cell strings connect the first and second wiring structures in parallel. The cell strings have memory cell transistors and a plurality of first selection transistors. The memory cell transistors are serially connected. The selection transistors connect the first wiring structure with the adjacent memory cell transistors in series. COPYRIGHT KIPO 2010 ...

VERTICAL MEMORY DEVICE

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A TUNNEL INSULATION LAYER

PURPOSE: A method for manufacturing a semiconductor device is provided to form a tunnel insulation layer applied to a reverse gate stack structure. CONSTITUTION: Conductive layers(211-216) and insulating layers(251-256) are alternative laminated on a substrate(200). An opening(290) passes through the conductive layers and the insulating layers. A blocking insulation layer(220) and a charge trapping layer(230) covering the blocking insulation layer are formed on the sidewall of the opening. A tunnel insulation layer(240) covering the charge trapping layer is formed. An active pillar is formed to fill the opening. COPYRIGHT KIPO 2010 ...

SEMICONDUCTOR DEVICE

Floating gate memory cells in vertical memory

INTER-STACK PLUG IN THREE-DIMENSIONAL MEMORY ELEMENT AND METHOD OF FORMING SAME

Semiconductor devices and methods of fabricating the same

A semiconductor device includes a semiconductor substrate having a plurality of active regions defined by a trench. A gate electrode crosses the plurality of active regions. A plurality of charge storing cells is disposed between the gate electrode and each of the plurality of active regions. A porous insulating layer is disposed between the gate electrode and the plurality of charge storing cells. The porous insulating layer includes a portion extended over the trench. An air gap is disposed between the extended portion of the porous insulating layer and a bottom surface of the trench.

Nonvolatile semiconductor storage apparatus and method for manufacturing the same

According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a substrate; a columnar semiconductor disposed perpendicular to the substrate; a charge storage laminated film disposed around the columnar semiconductor; a first conductor layer that is in contact with the charge storage laminated film and that has a first end portion having a first end face; a second conductor layer that is in contact with the charge storage laminated film, that is separated from the first conductor layer and that has a second end portion having a second end face; a first contact plug disposed on the first end face; and a second contact plug disposed on the second end face.

Apparatus and method for split gate NROM memory

A split gate, vertical NROM memory cell is comprised of a plurality of oxide pillars that each has a source/drain region formed in the top of the pillar. A trench is formed between each pair of oxide pillars. A polysilicon control gate is formed in the trench between the pair of oxide pillars. A polysilicon program gate is formed between the control gate and each oxide pillar. The program gates extend along the sidewall of each oxide pillar. A gate insulator layer is formed between each program gate and the adjacent oxide pillar. Each gate insulator layer has a structure for trapping at least one charge. In one embodiment, the gate insulator structure is an oxide-nitride-oxide layer in which the charge is stored at the trench bottom end of the nitride layer. An interpoly insulator is formed between the program gates and the control gate.

Structure containing self-aligned conductive line and method for fabricating thereof

Structure containing self-aligned conductive line and method for fabricating thereof are provided. First, a substrate, which a plurality of ribs has been formed in the substrate, is provided. And ribs are protruded above the surface of the substrate. Between each two ribs is an active area defined by thereof and a plurality of semiconductor devices is already formed in the active area. Then, a conductive layer is formed on the substrate to cover the ribs and the active area. After that, removes parts of the conductive layer with the ribs as the removing stop layer till exposing the surface of the ribs. As the results, a plurality of conductive line is automatically formed on the active area to electrically connect the semiconductor devices. As the shrinks of the scale of the device, the scale of the self-aligned conductive line won't be limited by the design rule of the process of lithography. Therefore, effective conductive lines for electrically connected between semiconductors devices ...

Dry etching method

This dry etching method comprises: performing, on a laminated film which is formed on a substrate and which consists of silicon oxide layers and silicon nitride layers, etching in which a dry etching agent is turned into plasma and a negative direct-current self-bias voltage of 500 V or higher in terms of absolute value is applied, via a mask that has a predetermined opening pattern and that is formed on the laminated film; and forming a through hole in the vertical direction in the laminated film. The method is characterized in that: the dry etching agent contains at least C3F6, hydrogen-containing saturated fluorocarbons represented by CxHyFz, and oxidized gas; and the volume of the hydrogen-containing saturated fluorocarbons contained in the dry etching agent is in the range of 0.1 to 10 times the volume of the C3F6 contained in the dry etching agent.

Storage device

A storage device includes: a plurality of electrode films stacked in a first direction, and extending in a second direction intersecting the first direction; a first semiconductor film provided adjacent to the plurality of electrode films, and extending in the first direction; a first charge holding film provided between one electrode film among the plurality of electrode films, and the semiconductor film, and including any one of a metal, a metal compound, and a high dielectric material; and a second semiconductor film located between the first semiconductor film and the charge holding film, and extending in the first direction along the first semiconductor film. The second semiconductor film is electrically insulated from the plurality of electrode films, the first charge holding film, and the first semiconductor film.

Substrate processing method and device manufactured by using the same

Provided are a substrate processing method and a device manufactured by using the same, which may improve etch selectivity of an insulating layer deposited on a stepped structure. The substrate processing method includes: forming a first layer on a stepped structure having an upper surface, a lower surface, and a side surface connecting the upper surface and the lower surface; weakening at least a portion of the first layer; forming a second layer on the first layer; and performing an isotropic etching process on the first layer and the second layer.

Method of forming 3D memory device and method of forming stair structure of 3D memory device

Methods of forming dual side wiring stair structures of 3D memory devices are disclosed. In an example, a first dielectric layer is formed on a substrate, and a photoresist layer is formed on the first dielectric layer. A recess penetrating the first dielectric layer and patterning till the substrate is formed by circles of trimming etching the first dielectric layer. Dielectric/sacrifice layer pairs are formed on the first dielectric layer and the recess is filled with the dielectric/sacrifice layer pairs. A second photoresist layer is formed on the dielectric/sacrifice layer pairs. The dielectric/sacrifice layer pairs are patterned by circles of trimming etching the dielectric/sacrifice layer pairs. A second dielectric layer is formed on the first dielectric layer and covers the patterned dielectric/sacrifice layer pairs. A memory stack layer including conductor/dielectric layer pairs is formed by replacing sacrifice layers in the patterned dielectric/sacrifice layer pairs with conductor ...

Three dimensional memory device having embedded dynamic random access memory units

Embodiments of a three-dimensional (3D) memory device and a forming method thereof are disclosed. In an example, a 3D memory device comprises a first semiconductor structure, wherein the first semiconductor structure comprises peripheral circuits, an array of embedded dynamic random access memory (DRAM) units and a first bonding layer comprising a plurality of first bonding contacts. The 3D memory device further comprises a second semiconductor structure, wherein the second semiconductor structure comprises an array of 3D NAND memory strings and a second bonding layer comprising a plurality of second bonding contacts. The 3D memory device further comprises a bonding interface located between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts in the bonding interface.

Method of Manufacturing Semiconductor Device, Substrate Processing Apparatus and Non-transitory Computer-readable Recording Medium

There is provided a technique that includes forming halogen terminated sites on a surface of a substrate having a base film formed thereon by supplying a halogen-containing gas to the substrate; and terminating the surface of the substrate with hydroxyl group by supplying a hydroxyl-containing gas containing.

THREE-DIMENSIONAL (3D) MEMORY DEVICE AND METHOD OF OPERATING THE SAME

METAL FILL PROCESS FOR THREE-DIMENSIONAL VERTICAL NAND WORDLINE

SILICON NITRIDE ETCHING LIQUID COMPOSITION

3D NON-VOLATILE STORAGE WITH ADDITIONAL WORD LINE SELECT GATES

Disclosed herein are 3D stacked memory devices having WL select gates (229). The 3D stacked memory device could have NAND strings. The WL select gates may be located adjacent to a word line hookup area (301) of a word line plate. The word line plate may be driven by a word line plate driver and may have many word lines. The WL select gates may select individual word lines or groups of word lines. Therefore, smaller units that the entire block may be selected. This may reduce capacitive loading. The WL select gates may include thin film transistors (231, 402, 404). 3D decoding may be provided in a 3D stacked memory device using the WL select gates.

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film.

ELECTRONIC DEVICE INCLUDING DISCONTINUOUS STORAGE ELEMENTS

An electronic device can include discontinuous storage elements (64) that lie within a trench (22, 23). The electronic device can include a substrate including a trench that includes a wall and a bottom and extends from a primary surface of the substrate (12). The electronic device can also include discontinuous storage elements, wherein a portion of the discontinuous storage elements lies at least within the trench. The electronic device can further include a first gate electrode, wherein at least a part of the portion of the discontinuous storage elements lies between the first gate electrode and the wall of the trench. The electronic device can still further include a second gate electrode overlying the first gate electrode and the primary surface of the substrate.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device may be provided. The semiconductor device may include a sub-channel layer located over a conductive layer. The semiconductor device may include a hole source layer interposed between the conductive layer and the sub-channel layer. The semiconductor device may include source select lines located over the sub-channel layer. The semiconductor device may include source channel layers contacting the sub-channel layer by penetrating the source select lines.

Integrated Structures Containing Vertically-Stacked Memory Cells

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Semiconductor memory device

A semiconductor memory device includes: a substrate; a first memory transistor and a first selection transistor aligned in a first direction intersecting a surface of the substrate and connected to each other; a first wiring connected to a gate electrode of the first memory transistor; and a second wiring connected to a gate electrode of the first selection transistor. Moreover, in a write operation, at a first timing, a voltage of the first wiring rises, at a subsequent second timing, the voltage of the first wiring falls, at a subsequent third timing, a voltage of the second wiring rises, at the third timing or at a subsequent fourth timing, the voltage of the first wiring rises, at a subsequent fifth timing, the voltage of the second wiring falls, and at a subsequent sixth timing, the voltage of the first wiring falls.

Nonvolatile semiconductor memory device and method of manufacturing the same

According to one embodiment, a nonvolatile semiconductor memory device includes a fin structure stacked in order of a first oxide layer, a semiconductor layer and a second oxide layer in a first direction perpendicular to a surface of the semiconductor substrate, the fin structure extending in a second direction parallel to the surface of the semiconductor substrate, and a gate structure stacked in order of a gate oxide layer, a charge storage layer, a block insulating layer and a control gate electrode in a third direction perpendicular to the first and second directions from a surface of the semiconductor layer in the third direction.

Methods for manufacturing semiconductor devices having three-dimensionally arranged memory cells

Methods for manufacturing semiconductor devices may include forming a stack structure including layers stacked on a substrate, forming a mask pattern on the stack structure, and patterning the stack structure using the mask pattern such that the stack structure has an end portion with a stepped profile. The patterning of the stack structure may include performing a pad etching process of etching the stack structure using the mask pattern as an etch mask, and performing a mask etching process of etching a sidewall of the mask pattern. The performing of the mask etching process may include irradiating an ion beam onto the mask pattern, which may be irradiated at a first tilt angle with respect to the sidewall of the mask pattern and at a second tilt angle with respect to a top surface of the mask pattern. The first tilt angle may be different from the second tilt angle.

SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, a semiconductor memory device includes a via provided above a substrate, a conductive layer provided on the via, and a via provided on the conductive layer. The via, the conductive layer, and the via are one continuous structure.

Electronic device including discontinuous storage elements and a process for forming the same

An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate that includes a trench extending into a semiconductor material. The trench can include a ledge and a bottom, wherein the bottom lies at a depth deeper than the ledge. The electronic device can include discontinuous storage elements, wherein a trench portion of the discontinuous storage elements lies within the trench. Gate electrodes may lie adjacent to walls of the trench. In a particular embodiment, a portion of a channel region within a memory cell may not be covered by a gate electrode. In another embodiment, a doped region may underlie the ledge and allow for memory cells to be formed at different elevations within the trench. In other embodiment, a process can be used to form the electronic device.

2F-square memory cell for gigabit memory applications

A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has columns of bitlines and rows of wordlines. The gates of the transistors act as the wordlines, while the source or drain regions acts as the bitlines. The array also has vertical pillars, each having a channel formed between source and drain regions. Two transistors are formed per pillar. This is achieved by forming two gates per pillar formed on opposite pillar sidewalls which are along the bitline direction. This forms two wordlines or gates per pillar arranged in the wordline direction. The source regions are self-aligned and located below the pillars. The source regions of adjacent bit lines are isolated from each other without increasing the cell size. Two floating gates per pillar may be used for EEPROM or flash memory application. The isolated sources allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile ...

SEMICONDUCTOR DEVICES, NONVOLATILE MEMORY DEVICES INCLUDING THE SAME, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND METHODS FOR FABRICATING THE SAME

A semiconductor device comprises a substrate; an element isolation film that defines a first active region in the substrate; a first gate electrode on the first active region; a first source/drain region located inside the first active region between the element isolation film and the first gate electrode; and an isolation contact that extends in a vertical direction intersecting an upper face of the substrate, in the element isolation film. The isolation contact is configured to have a voltage applied thereto.

Semiconductor device

Fins lined up in a Y direction, a control gate electrode and a memory gate electrode each extending in the Y direction so as to straddle the fins, a plurality of first plugs electrically connected with a drain region formed in each of the fins, and a plurality of second plugs electrically connected with a source region formed in each of the fins are formed. Here, a N-th plug of the plurality of first plugs lined up in the Y direction is coupled with each of (2N−1)-th and 2N-th fins in the Y direction. Also, a N-th plug of the plurality of second plugs lined up in the Y direction is coupled with each of 2N-th and (2N+1)-th fins in the Y direction.

NONVOLATILE MEMORY DEVICE, STORAGE DEVICE, AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE

Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly. 1. A nonvolatile memory device comprising:a memory cell array disposed on a substrate, wherein the memory cell array comprises a plurality of memory blocks;a row decoder connected to the memory cell array through word lines; anda page buffer connected to the memory cell array through bit lines,wherein each of the memory blocks comprises a pillar including a first portion disposed on the substrate and a second portion stacked on the first portion,wherein at least a portion of a width of the first portion increases as a distance from the substrate increases, and first conductive materials and first insulating layers surround the first portion and are stacked in turn on the substrate,wherein at least a portion of a width of the second portion increases as a distance from the substrate increases, and second conductive materials and second insulating layers surround the second portion and are stacked in turn on the substrate,wherein a first boundary is located between the first portion and the second portion,wherein the first conductive materials form first memory cells together with the first ...

NONVOLATILE MEMORY DEVICE INCLUDING ERASE TRANSISTORS

A nonvolatile memory device includes bitlines, a source line, cell channel structures, a gate electrode structure, erase channel structures and an erase selection line. The bitlines are disposed at a first end portion of a cell region, arranged in a first horizontal direction and extend in a second horizontal direction. The source line is disposed at a second end portion of the cell region and extend in the second horizontal direction. The cell channel structures are disposed in a cell string area of the cell region and are respectively connected between the bitlines and the source line. The erase channel structures are disposed in a contact area of the cell region and respectively connected between the bitlines and the source line. The erase channel structures include erase transistors. The erase selection line is disposed in the contact area to form a gate electrode of the erase transistors.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR STORAGE DEVICE

A semiconductor device includes first and second gate electrodes, a semiconductor layer between the first and second gate electrodes and extending along a first direction, a first gate insulating layer between the first gate electrode and the semiconductor layer, a second gate insulating layer between the second gate electrode and the semiconductor layer, a first insulating layer including a first region adjacent to the first gate electrode in the first direction and contacting the semiconductor layer, and a second insulating layer extending including a second region adjacent to the second gate electrode in the first direction and contacting the semiconductor layer. An interface between the first region and the semiconductor layer in a direction crossing the first direction is adjacent to the first gate electrode in the first direction.

Deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators

Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al₂O₃, Ta₂O₅, TiO₂, ZrO₂, Nb₂O₅, SrBi₂Ta₂O₃, SrTiO₃, PbTiO₃, and PbZrO₃.

SEMICONDUCTOR STORAGE DEVICE

According to one embodiment, a semiconductor storage device includes a first memory cell, a second memory cell, a first transistor, a second transistor, and a third transistor. The first transistor includes a first portion electrically connected to a first circuit, a second portion electrically connected to the first memory cell, and a first gate electrode installed between the first portion and the second portion. The second transistor includes a third portion electrically connected to the first circuit, a fourth portion electrically connected to the second memory cell, and a first gate electrode installed between the third portion and the fourth portion. The third transistor includes the second portion, the fourth portion, a fifth portion electrically connected to a second circuit, and a second gate electrode installed between the second portion and the fifth portion and between the fourth portion and the fifth portion.

Method for forming vertical channel flash memory cell and device manufactured thereby

A vertical memory device on a silicon semiconductor substrate is formed by the following steps. Form an array of isolation silicon oxide structures on the surface of the silicon semiconductor substrate. Form a floating gate trench in the silicon semiconductor substrate between the silicon oxide structures in the array, the trench having trench sidewall surfaces. Dope the sidewalls of the floating gate trench with a threshold implant through the trench sidewall surfaces. Form a tunnel oxide layer on the trench sidewall surfaces, the tunnel oxide layer having an outer surface. Form a floating gate electrode in the trench on the outer surface of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Form an interelectrode dielectric layer over the top surface of the floating gate electrode. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode. Form a source line ...

Semiconductor apparatus with multiple tiers of memory cells with peripheral transistors, and methods

Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

Three-dimensional memory device including wrap around word lines and methods of forming the same

A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, forming lateral recesses at levels of the sacrificial material layers around the memory opening, forming a vertical stack of discrete clam-shaped semiconductor liners in the lateral recesses, replacing the vertical stack of discrete clam-shaped semiconductor liners with a vertical stack of inner clam-shaped metallic liners, forming a vertical stack of discrete charge storage elements on the vertical sack of inner clam-shaped metallic liners, forming a tunneling dielectric layer and a vertical semiconductor channel over the vertical stack of discrete charge storage elements and the vertical stack of inner clam-shaped metallic liners, and replacing each of the sacrificial material layers with an electrically conductive layer.

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

An object is to shorten the time for rewriting data in memory cells. A memory module includes a first memory cell, a second memory cell, a selection transistor, and a wiring WBL1. The first memory cell includes a first memory node. The second memory cell includes a second memory node. One end of the first memory cell is electrically connected to the wiring WBL1 through the selection transistor. The other end of the first memory cell is electrically connected to one end of the second memory cell. The other end of the second memory cell is electrically connected to the wiring WBL1. When the selection transistor is on, data in the first memory node is rewritten by a signal supplied through the selection transistor to the wiring WBL1. When the selection transistor is off, data in the first memory node is rewritten by a signal supplied through the second memory node to the wiring WBL1.

Three-dimensional integrated circuit structure and method of making same

Composition for etching

The disclosure is related to a composition for etching, a method for manufacturing the composition, and a method for fabricating a semiconductor using the same. The composition may include a first inorganic acid, at least one of silane inorganic acid salts produced by reaction between a second inorganic acid and a silane compound, and a solvent. The second inorganic acid may be at least one selected from the group consisting of a sulfuric acid, a fuming sulfuric acid, a nitric acid, a phosphoric acid, and a combination thereof.

Vertical semiconductor devices

A vertical semiconductor device includes a substrate with a first and second region. A conductive pattern on the first region extends in a first direction. The first region includes a cell region, a first dummy region and a second dummy region. The conductive pattern extends in a first direction. A pad is disposed on the second region, the pad contacts a side of the conductive pattern. A plurality of first dummy structures extends through the conductive pattern on the first dummy region. A plurality of second dummy structures extend through the conductive pattern on the second dummy region, the second dummy structures disposed in a plurality of columns that extend in a second direction perpendicular to the first direction. Widths of upper surfaces of the second dummy structures are different in each column, and the widths of upper surfaces of the second dummy structures increase toward the second region.

3D stacked memory and vertical interconnect structures for 3D stacked memory

Provided is a 3D stacked memory device having a cell region in which memory stacks are arranged on a substrate. Vertical memory stacks and a vertical interconnect structure are provided in the cell region. The vertical interconnect structure includes: a via-hole formed along a vertical direction of the cell region; and a conductive pillar shaped by filling the via-hole with a conductive material. The vertical interconnect structure is configured to interconnect a top electrode of the vertical memory stack and a conductive region of the substrate along the vertical direction. The 3D stacked memory device has a vertical interconnect structure configured with a vertical wiring plug of a conductive material in a cell region, so that it is possible to facilitate the manufacturing process and providing a vertical interconnect between top and bottom electrodes of the stacked memory device or a peripheral circuit of the substrate.

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a substrate including a cell array region and a pad region, a stack structure disposed on the cell array region and the pad region of the substrate and including gate electrodes, a device isolation layer vertically overlapping the stack structure and disposed in the pad region of the substrate, a dummy vertical channel portion penetrating the stack structure on the pad region of the substrate and disposed in the device isolation layer, and a dummy semiconductor pillar disposed between the dummy vertical channel portion and one portion of the substrate being in contact with one sidewall of the device isolation layer.

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate a substrate including a peripheral circuit region and a cell array region, an electrode structure including a plurality of electrodes vertically stacked on the cell array region of the substrate, a peripheral logic circuit provided on the peripheral circuit region of the substrate, the peripheral logic circuit including a first impurity region doped with first impurities, a peripheral contact plug connected to the first impurity region, and a second impurity region between the first impurity region and the peripheral contact plug, the second impurity region being including second impurities different from the first impurities. The peripheral contact plug includes a lower portion contacting the second impurity region, and an upper portion continuously extending from the lower portion a lower width of each of the lower and upper portions is less than an upper ...

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE

Provided is a three-dimensional semiconductor memory device include a first stack structure and a second stack structure adjacent to each other on a substrate, a first common source plug between the first stack structure and the second stack structure, a second common source plug between the first stack structure and the second stack structure, and a vertical dielectric structure between the first common source plug and the second common source plug. Each of the first stack structure and the second stack structure may include a plurality of insulation layers and a plurality of electrodes alternately stacked on the substrate. The first common source plug may be connected to the substrate. The second common source plug may be spaced apart from the substrate.

MOLYBDENUM-CONTAINING CONDUCTIVE LAYERS FOR CONTROL GATE ELECTRODES IN A MEMORY STRUCTURE

A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a metallic barrier material portion can be formed in each backside recess. A molybdenum-containing portion can be formed in each backside recess. Each backside recess can be filled with a molybdenum-containing portion alone, or can be filled with a combination of a molybdenum-containing portion and a metallic material portion including a material other than molybdenum.

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a circuit chip including a first substrate, peripheral circuit elements which are defined on the first substrate and a first dielectric layer which covers the peripheral circuit elements, and having first pads which are coupled to the peripheral circuit elements, on one surface thereof; a memory chip including a second substrate which is disposed on a base dielectric layer, a memory cell array which is defined on the second substrate and a second dielectric layer which covers the memory cell array, and having second pads which are coupled with the first pads, on one surface thereof which is bonded with the one surface of the circuit chip; a contact passing through the base dielectric layer and the second dielectric layer; and one or more dummy contacts passing through the base dielectric layer and the second dielectric layer, and disposed around the contact. 1. A semiconductor memory device comprising:a circuit chip including a first substrate, peripheral circuit elements which are defined on the first substrate, a first dielectric layer which covers the peripheral circuit elements, and a plurality of first pads which are coupled to the peripheral circuit elements, on one surface thereof;a memory chip including a second substrate which is disposed on a base dielectric layer, a memory cell array which is defined on the second substrate, a second dielectric layer which covers the memory cell array, and a plurality of second pads which are coupled with the first pads, on one surface thereof which is bonded with the one surface of the circuit chip;a contact passing through the base dielectric layer and the second dielectric layer; andone or more dummy contacts passing through the base dielectric layer and the second dielectric layer, and disposed around the contact.2. The semiconductor memory device according to claim 1 , wherein the contact and the dummy contacts are formed of the same material.3. The semiconductor memory device ...

Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof

A three-dimensional memory device including self-aligned drain select level electrodes is provided. Memory stack structures extend through an alternating stack of insulating layers and spacer material layers. Each of the memory stack structures includes a memory film and a memory level channel portion. Drain select level channel portions are formed over the memory level channel portions with respective lateral shifts with respect to underlying memory stack structures. The direction of lateral shifts alternates from row to row for each row of drain select level channel portions. Drain select level gate dielectrics and drain select level gate electrodes are formed on the drain select level channel portions. Each drain select level gate electrode controls two rows of drain select level channel portions, and is laterally spaced from neighboring drain select level gate electrodes.

Three-dimensional semiconductor memory device

A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.

Vertical floating gate NAND with selectively deposited ALD metal films

A method of making a monolithic three dimensional NAND string which contains a semiconductor channel and a plurality of control gate electrodes, includes selectively forming a plurality of discrete charge storage regions using atomic layer deposition. The plurality of discrete charge storage regions includes at least one of a metal or an electrically conductive metal oxide.

Multiheight contact via structures for a multilevel interconnect structure

Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via structures. In another embodiment, encapsulated unfilled cavities can be formed in the contact openings by non-conformal deposition of a material layer, electrically conductive electrodes can be formed by replacement of portions of the sacrificial layers, and the electrically conductive via contacts can be subsequently formed on the electrically conductive electrodes. Electrically conductive via contacts extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a first memory cell, a first select transistor between the first memory cell and a source line, a second select transistor between the first memory cell and a bit line, a third select transistor between the source line and the bit line, and a control circuit. During an erase operation, the control circuit is configured to apply a first voltage to the source line, apply a second voltage lower than the first voltage to a gate of the third select transistor while applying the first voltage to the source line to cause a third voltage to be applied to the bit line, and apply a fourth voltage lower than the third voltage to the gate of the second select transistor while the third voltage is applied to the bit line.

Method of reading and writing nonvolatile memory cells

The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.

SEMICONDUCTOR STORAGE DEVICE

According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line. 1. A semiconductor storage device , comprising:a first memory string including a first memory transistor;a first word line connected to a gate electrode of the first memory transistor;a source line connected to one end of the memory string; anda first connection transistor connected between the first word line and the source line.2. The semiconductor storage device according to claim 1 , further comprising:a first selection transistor connected in series with the first memory transistor in the first memory string;a first selection gate line connected to a gate electrode of the first selection transistor; anda second connection transistor connected between the first selection gate line and the source line.3. The semiconductor storage device according to claim 1 , further comprising:a third connection transistor connected between the first connection transistor and the source line, whereinthe first connection transistor is an enhancement-type transistor, andthe third connection transistor is a depletion-type transistor.4. The semiconductor storage device according to claim 3 , further comprising:an equalizer circuit including the first and third connection transistors, whereingates of the first and third connection transistor are connected to each other in common.5. The semiconductor storage device according to claim 4 , further comprising:a source line driver connected to the source line and configured to supply voltages to source line; anda fourth connection transistor connected between the equalizer circuit and the source line driver, the fourth connection transistor being between the source line driver and the ...

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES

A three-dimensional semiconductor memory device includes: a peripheral circuit structure; and a cell array structure on the peripheral circuit structure. The peripheral circuit structure includes a lower wiring on a substrate, a stopping insulating layer on the lower wiring, a contact via on the lower wiring, a floating via on the stopping insulating layer, and an upper wiring on the contact via. The floating via does not contact the lower wiring. The contact via contacts the lower wiring through a via hole in the stopping insulating layer. The upper wiring contacts the contact via. 1. A three-dimensional semiconductor memory device , comprising:a peripheral circuit structure; anda cell array structure on the peripheral circuit structure, a lower wiring on a substrate,', 'a stopping insulating layer on the lower wiring,', 'a contact via on the lower wiring and contacting the lower wiring through a via hole in the stopping insulating layer,', 'a floating via on the stopping insulating layer, the floating via not contacting the lower wiring, and', 'an upper wiring on the contact via, the upper wiring contacting the contact via., 'wherein the peripheral circuit structure includes'}2. The device of claim 1 , wherein the floating via comprises a different material from the contact via.3. The device of claim 1 , wherein the floating via is on only one side of the contact via.4. The device of claim 1 , further comprising:a second floating via on the stopping insulating layer, the floating via and the second floating via being on opposite sides of the contact via.5. The device of claim 1 , wherein the floating via surrounds the contact via.6. The device of claim 1 , further comprising:a contact via structure on the floating via and the upper wiring, the contact via structure contacting both the floating via and the upper wiring.7. The device of claim 1 , wherein the lower wiring comprises a line-type wiring extending on the substrate in a line shape.8. The device of claim 1 ...

3-D NAND Control Gate Enhancement

Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. 1. A method of forming a NAND memory structure , the method comprising:depositing a plurality of alternating layers of a nitride material and an oxide material separated by a silicon layer;etching a memory hole through the plurality of alternating layers to form an exposed surface of the plurality of alternating layers;selectively etching laterally through the memory hole from the exposed surface a portion of the nitride material;depositing a blocking oxide layer in the memory hole to form a conformal oxide liner on the exposed surface of the plurality of alternating layers, the conformal oxide layer having a first side adjacent to the plurality of alternating layers of nitride material and oxide material, and second adjacent to the memory hole;depositing a floating gate metal into the memory hole to form a floating gate adjacent the conformal oxide liner, the floating gate material having a first side, a second side, a third side, and a fourth side, the conformal oxide layer surrounding the floating gate on the first side, the second, side, and the third side, and the fourth side facing the memory hole channel;depositing a gate oxide material into the memory hole to form a layer of gate oxide material adjacent the floating gate, the gate oxide material conformally extending along the fourth side of the floating gate material and conformally extending along the conformal blocking oxide liner adjacent the face of the first and second insulating layers facing the memory hole channel;depositing a silicon material in the memory hole to form a silicon channel ...

Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. A channel-material string is in individual channel openings in the vertically-alternating first tiers and second tiers. A conductor-material contact is in the individual channel openings directly against the channel material of individual of the channel-material strings. The conductor-material contacts are vertically recessed in the individual channel openings. A conductive via is formed in the individual channel openings directly against the vertically-recessed conductor-material contact in that individual channel opening. Other aspects, including structure independent of method, are disclosed. 1. A method used in forming a memory array comprising strings of memory cells , comprising:forming a stack comprising vertically-alternating first tiers and second tiers, a channel-material string being in individual channel openings in the vertically-alternating first tiers and second tiers, a conductor-material contact being in the individual channel openings directly against the channel material of individual of the channel-material strings;vertically recessing the conductor-material contacts in the individual channel openings; andforming a conductive via in the individual channel openings directly against the vertically-recessed conductor-material contact in that individual channel opening.2. The method of wherein an uppermost of the vertically-alternating first tiers and second tiers of the stack is a second tier at start of the vertical recessing claim 1 , the conductor-material contacts in the individual channel openings individually having a top that is above an uppermost of the first tiers after the vertical recessing.3. The method of wherein the uppermost second tier is thicker than the second tier immediately-there-below.4. The method of comprising vertically recessing the individual channel-material ...

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING STAIRLESS WORD LINE CONTACT STRUCTURES FOR AND METHOD OF MAKING THE SAME

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities. 1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;memory openings located in a memory array region and vertically extending through the alternating stack;memory opening fill structures located in the memory openings;support pillar structures located in a contact region, vertically extending through the alternating stack, and comprising a dielectric material; andlaterally-isolated contact via assemblies located in the contact region, wherein each of the laterally-isolated contact via assemblies comprises a contact via structure contacting a top surface of a respective one of the electrically conductive layers and a tubular dielectric spacer laterally surrounding the contact via structure, first support pillar structures that vertically extend through each layer within the alternating stack; and', 'second support pillar structures that are shorter than the first support pillar structures and contacting a respective one of the ...

MEMORY DEVICE HAVING VERTICAL STRUCTURE

A memory device includes a cell wafer including a memory cell array; and a peripheral wafer including a row control circuit, a column control circuit and a peripheral circuit which control the memory cell array, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer includes a first substrate having a first surface and a second surface which face away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, and including the row control circuit and the column control circuit; and a second logic structure disposed on the second surface of the first substrate, and including the peripheral circuit. 1. A memory device comprising:a cell wafer including a memory cell array; anda peripheral wafer, including a row control circuit, a column control circuit and a peripheral circuit, stacked on and bonded to the cell wafer in a first direction,the peripheral wafer comprising:a first substrate having a first surface and a second surface that face away from each other in the first direction;a first logic structure, disposed on the first surface of the first substrate, that includes the row control circuit and the column control circuit; anda second logic structure, disposed on the second surface of the first substrate, that includes the peripheral circuit.2. The memory device according to claim 1 , wherein the first surface is closer to the cell wafer in the first direction than the second surface.3. The memory device according to claim 2 ,wherein the cell wafer includes, on one surface thereof bonded to the peripheral wafer, a plurality of first bonding pads that are coupled to word lines and bit lines of the memory cell array, andwherein the peripheral wafer includes, on the one surface thereof bonded to the cell wafer, a plurality of second bonding pads that are bonded to the plurality of first bonding pads, each of the plurality of second bonding pads are coupled to the row control ...

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING STAIRLESS WORD LINE CONTACT STRUCTURES FOR AND METHOD OF MAKING THE SAME

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities. 1. A method of forming a semiconductor device , comprising:forming an alternating stack of insulating layers and sacrificial material layers over a substrate;forming memory openings through the alternating stack;forming memory opening fill structures in the memory openings;forming via cavities vertically extending through the alternating stack without forming any stepped surfaces in the alternating stack;forming sacrificial via fill structures in the via cavities;replacing the sacrificial material layers with electrically conductive layers;forming voids in volumes of the via cavities by removing the sacrificial via fill structures;forming tubular dielectric spacers on sidewalls of the via cavities; andforming contact via structures in remaining volumes of the via cavities on an inner sidewall of a respective one of the tubular dielectric spacers and directly on a top surface of a respective one of the electrically conductive layers.2. The method of claim 1 , wherein each of the sacrificial material layers contains a ...

SEMICONDUCTOR DEVICE

A semiconductor device includes gate electrodes and insulating layers spaced apart from each other on a substrate and alternately stacked in a direction perpendicular to an upper surface of the substrate, and channel structures that extend through stack structures. Ones of the structures include a channel insulating layer, a pad layer on the channel insulating layer, and a channel layer. The channel layer includes a first channel region, and a second channel region including a semiconductor material having a length shorter than a length of the first channel region and having an impurity concentration of a first conductivity type and the pad layer includes a semiconductor material doped with a second conductivity type impurity. A height level of a lower surface of the second channel region is lower than a height level of a lower surface of a first erase gate electrode. 1. A semiconductor device comprising:gate electrodes spaced apart from each other on a substrate and stacked in a direction perpendicular to an upper surface of the substrate;insulating layers alternately stacked with the gate electrodes; andchannel structures that extend through the gate electrodes and the insulating layers,wherein ones of the channel structures comprise a channel insulating layer, a pad layer on the channel insulating layer, and a channel layer on a side surface of the channel insulating layer and on at least a portion of a side surface of the pad layer,wherein the channel layer comprises a first channel region and a second channel region,wherein a length of the second channel region is shorter than a length of the first channel region,wherein the second channel region comprises a semiconductor material doped with a first conductivity type impurity, the first channel region comprises a semiconductor material having an impurity concentration lower than an impurity concentration in the second channel region, and the pad layer comprises a semiconductor material doped with a second ...

TECHNIQUES FOR MANUFACTURING SPLIT-CELL 3D-NAND MEMORY DEVICES

Techniques for manufacturing memory devices, such as 3-dimensional NAND (3D-NAND) memory devices, may include splitting gate planes (e.g., the planes that include the word lines) into strips, thereby splitting the memory cells and increasing a density of memory cells for a respective memory device. The techniques described herein are applicable to various types of 3D-NAND or other memory devices. 120.-. (canceled)21. A method of manufacturing a 3-dimensional NAND (3D-NAND) memory device , the method comprising:depositing a plurality of alternating first and second layers to form a stack, wherein the first layers comprising a first material and the second layers comprising a second material;forming a plurality of grooves comprising the first material in the stack, the grooves extending along a wordline direction of the 3D-NAND memory device and dividing at least some of the second layers into strips extending along the wordline direction;etching a plurality of channel holes in the stack, each channel hole overlapping one of the grooves and being wider than the one of the grooves in a bitline direction orthogonal to the wordline direction; anddepositing a memory layer and a channel layer into the channel holes to form vertical NAND strings.22. The method of claim 21 , wherein forming plurality of grooves comprises defining a gap region between two adjacent grooves substantially in alignment along the wordline direction.23. The method of claim 22 , wherein the channel holes etched in the stack are not overlapping the gap region.24. The method of claim 22 , further comprising:etching a plurality of separation trenches in the stack, the separation trenches extending along the wordline direction;selectively removing the second material of the second layers from exposed sidewalls of the second layers in the separation trenches;depositing gate metal into spaces revealed by the removed second material, wherein the gap region providing a path for removing the second material ...

3d nand flash memory

A memory device includes an array of NAND strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. The device includes charge storage structures in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and inter-stack semiconductor body elements of a plurality of bit line structures. At least one reference line structure is arranged orthogonally over the stacks, including vertical conductive elements between the stacks in electrical communication with a reference conductor between the bottom plane of conductive strips and a substrate, and linking elements over the stacks connecting the vertical conductive elements. The vertical conductive elements have a higher conductivity than the semiconductor body elements.

MODULAR INTERCONNECTS FOR GATE-ALL-AROUND TRANSISTORS

A modular interconnect structure facilitates building complex, yet compact, integrated circuits from vertical GAA FETs. The modular interconnect structure includes annular metal contacts to the transistor terminals, sectors of stacked discs extending radially outward from the vertical nanowires, and vias in the form of rods. Extension tabs mounted onto the radial sector interconnects permit signals to fan out from each transistor terminal. Adjacent interconnects are linked by linear segments. Unlike conventional integrated circuits, the modular interconnects as described herein are formed at the same time as the transistors. Vertical GAA NAND and NOR gates provide building blocks for creating all types of logic gates to carry out any desired Boolean logic function. Stacked vertical GAA FETs are made possible by the modular interconnect structure. The modular interconnect structure permits a variety of specialized vertical GAA devices to be integrated on a silicon substrate using standard CMOS processes. 1. An apparatus comprising:a substrate having a substrate surface;a plurality of transistors, each transistor having a source terminal, a gate terminal, and a drain terminal extending out from the substrate in a direction transverse to the substrate surface; and a plurality of annular contacts, each annular contact aligned with and coupled to one of the terminals of the selected ones of the plurality of transistors;', 'a plurality of radial sectors, each radial sector coupled to one of the annular contacts and forming a conductive domain in a plane aligned with a respective one of the terminals; and', 'a plurality of vias coupled to selected ones of the conductive domains, the vias aligned substantially transverse to the substrate surface., 'a modular interconnect structure coupled to selected terminals of selected ones of the plurality of transistors, the modular interconnect structure including2. The apparatus of wherein the substrate is doped.3. The apparatus of ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars. 1. A semiconductor memory device comprising:a first semiconductor pillar extending in a first direction;a second semiconductor pillar extending in the first direction, the first semiconductor pillar and the second semiconductor pillar being arranged in a second direction intersecting the first direction;a first electrode film extending in a third direction intersecting the first direction and the second direction;a second electrode film extending in the third direction, the first electrode film and the second electrode film being arranged in the second direction;a first memory portion provided between the first semiconductor pillar and the first electrode film;a second memory portion provided between the second semiconductor pillar and the second electrode film;a first connection member being electrically connected in common to an upper portion of the first semiconductor pillar and an upper portion of the second semiconductor pillar;a first contact, a lower portion of the first contact being electrically connected to the first connection member; anda first upper interconnect extending in the second direction and electrically connected to an upper portion of the first contact.2. The device according to claim 1 , whereinthe first semiconductor pillar and the second semiconductor pillar are disposed between the first electrode film and the second electrode film.3. The device according to claim 1 , further comprising:a conductive layer containing silicon, the conductive layer being electrically connected in common to a lower portion of the first semiconductor pillar and a lower portion of the second semiconductor pillar.4. The device according to claim 1 , whereinthe first semiconductor ...

THREE-DIMENSIONAL MEMORY DEVICES HAVING HYDROGEN BLOCKING LAYER AND FABRICATION METHODS THEREOF

Embodiments of three-dimensional (3D) memory devices have a blocking layer and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, an array of NAND memory strings each extending vertically through the memory stack, a plurality of logic devices above the array of NAND memory strings, a semiconductor layer above and in contact with the logic devices, a pad-out interconnect layer above the semiconductor layer, and a blocking layer vertically between the semiconductor layer and the pad-out interconnect layer and configured to block outgassing of hydrogen. 1. A memory device , comprising:a memory array;a plurality of logic devices above the memory array;a semiconductor layer above and in contact with the logic devices;a pad-out interconnect layer above the semiconductor layer; anda blocking layer vertically between the semiconductor layer and the pad-out interconnect layer,wherein the semiconductor layer is vertically between the plurality of logic devices and the blocking layer.2. The memory device of claim 1 , wherein the blocking layer comprises a high dielectric constant (high-k) dielectric material.3. The memory device of claim 1 , wherein a thickness of the blocking layer is between about 1 nm and about 100 nm.4. The memory device of claim 1 , wherein the blocking layer extends laterally to cover the semiconductor layer.5. The memory device of claim 1 , wherein the blocking layer is configured to block outgassing of the hydrogen from the logic devices into or beyond the pad-out interconnect layer during fabrication of the memory device.6. The memory device of claim 1 , further comprising:a first bonding layer above the memory array and comprising a plurality of first bonding contacts;a second bonding layer below the logic devices and above the first bonding layer and comprising a plurality of second bonding contacts; anda ...

THREE-DIMENSIONAL MEMORY AND FABRICATING METHOD THEREOF

Three-dimensional memories are provided. A three-dimensional memory includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines. The memory cells are divided into a plurality of groups, and the groups of memory cells are formed in respective levels stacked along a first direction. The word lines extend along a second direction, and the second direction is perpendicular to the first direction. Each of the bit lines includes a plurality of sub-bit lines formed in the respective levels. Each of the source lines includes a plurality of sub-source lines formed in respective levels. In each of the levels, the memory cells of the corresponding group are arranged in a plurality of columns, and the sub-bit lines and the sub-source lines are alternately arranged between two adjacent columns. 1. A three-dimensional memory , comprising:a plurality of memory cells divided into a plurality of groups, wherein the groups of memory cells are formed in respective levels stacked in a first direction;a plurality of word lines extending along a second direction, wherein the second direction is perpendicular to the first direction;a plurality of bit lines, wherein each of the bit lines comprises a plurality of sub-bit lines formed in the respective levels; anda plurality of source lines, wherein each of the source lines comprises a plurality of sub-source lines formed in respective levels,wherein in each of the levels, the memory cells of the corresponding group are arranged in a plurality of columns, and the sub-bit lines and the sub-source lines are alternately arranged between two adjacent columns.2. The three-dimensional memory as claimed in claim 1 , wherein the memory cells of the two adjacent columns are coupled to the different word lines.3. The three-dimensional memory as claimed in claim 1 , wherein the memory cells of odd columns are aligned with each other claim 1 , and the memory cells of even columns are aligned ...

THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE

A three-dimensional semiconductor memory device is provided. A stacked structure is formed on a substrate. The stacked structure includes conductive patterns vertically stacked on the substrate. A selection structure including selection conductive patterns is stacked on the stacked structure. A channel structure penetrates the selection structure and the stacked structure to connect to the substrate. An upper interconnection line crosses the selection structure. A conductive pad is disposed on the channel structure to electrically connect the upper interconnection line to the channel structure. A bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the selection conductive patterns. 1. A three-dimensional semiconductor memory device , comprising:a stacked structure including a plurality of conductive patterns vertically stacked on a substrate;a selection structure including a plurality of selection conductive patterns stacked on the stacked structure;a channel structure penetrating the selection structure and the stacked structure to connect to the substrate;an upper interconnection line crossing the selection structure; anda conductive pad disposed on the channel structure to electrically connect the upper interconnection line to the channel structure,wherein a bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the plurality of selection conductive patterns.2. The device of claim 1 , wherein the bottom surface of the conductive pad is positioned between top surfaces of two adjacent selection conductive patterns in a vertical direction.3. The device of claim 1 , wherein the bottom surface of the conductive pad is positioned between top and bottom surfaces of the uppermost selection conductive pattern.4. The device of claim 1 , wherein the bottom surface of the conductive pad is positioned below a bottom surface of the uppermost ...

Data Line Arrangement and Pillar Arrangement in Apparatuses

Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern which has at least portions of 7 different pillars. Each of the different pillars in a respective one of the repeating pillar patterns is capable of being electrically coupled to a different data line of a plurality of data lines. Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed arrangement includes a repeating pillar pattern having at least portions of 7 different pillars. All 7 different pillars of a repeating pillar pattern are encompassed by a single drain-side select gate (SGD). 124-. (canceled)25. An apparatus , comprising a plurality of semiconductor pillars in a substantially hexagonally closest packed arrangement; the hexagonally closest packed arrangement comprising a repeating pillar pattern , with the repeating pillar pattern having at least portions of 7 different pillars , wherein each of the different pillars in a respective one of the repeating pillar patterns is electrically coupled to a different data line of a plurality of data lines; and wherein each of the pillars in a respective one of the repeating pillar patterns is encompassed by a single drain-side select gate (SGD); the pillars and SGD being supported by a base comprising monocrystalline silicon.26. The apparatus of claim 25 , wherein said each of the pillars in a respective one of the repeating pillar patterns being encompassed by a single drain-side select gate (SGD) comprises each of the pillars in the respective one of the repeating pillar patterns being at least partially surrounded by the single SGD claim 25 , and wherein activation of the single SGD electrically couples the 7 different pillars to 7 different data lines.27. The apparatus of claim 26 , wherein a drain-side ...

SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SEMICONDUCTOR DEVICE

To provide a semiconductor device with a high output voltage. A gate of a first transistor is electrically connected to a first terminal through a first capacitor. A gate of a second transistor is electrically connected to a second terminal through a second capacitor. One of a source and a drain of a third transistor is electrically connected to the gate of the first transistor through a third capacitor. One of a source and a drain of a fourth transistor is electrically connected to the gate of the second transistor through a fourth capacitor. The other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor are electrically connected to a high potential power source. A third terminal is electrically connected to one of a source and a drain of the second transistor. 1. A semiconductor device comprising:a comparator comprising a first transistor to a seventh transistor, a first capacitor to a fourth capacitor, a first input terminal, a second input terminal, and an output terminal;an eighth transistor and a ninth transistor each comprising a front gate and a back gate; anda fifth capacitor,wherein a gate of the first transistor is electrically connected to the first input terminal through the first capacitor,wherein a gate of the second transistor is electrically connected to the second input terminal through the second capacitor,wherein one of a source and a drain of the third transistor is electrically connected to the gate of the first transistor through the third capacitor,wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the second transistor through the fourth capacitor,wherein the other of the source and the drain of the third transistor, the other of the source and the drain of the fourth transistor, one of a source and a drain of the sixth transistor, and one of a source and a drain of the seventh transistor are electrically connected to a high ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a common source region formed in a semiconductor substrate, a bit line formed over the semiconductor substrate, first and second vertical channel layers coupled between the bit line and the common source region, wherein the first and second vertical channel layers are alternately arranged on the semiconductor substrate, first conductive layers stacked over the semiconductor substrate to surround one side of the first vertical channel layer, second conductive layers stacked over the semiconductor substrate to surround one side of the second vertical channel layer, and a charge storage layer formed between the first vertical channel layer and the first conductive layers and between the second vertical channel layer and the second conductive layers. 113-. (canceled)14. A semiconductor device , comprising:first, second, fifth and sixth vertical channel layers vertically coupled between a semiconductor substrate and a bit line;third, fourth, seventh and eighth vertical channel layers vertically coupled between the semiconductor substrate and a common source line;first, third, fifth and seventh multilayer conductive layers stacked on the semiconductor substrate at predetermined distances to surround one side of the first, third, fifth and seventh vertical channel layers, respectively;second, fourth, sixth and eighth multilayer conductive layers stacked on the semiconductor substrate at predetermined distances to surround one side of the second, fourth, sixth and eighth vertical channel layers, respectively;charge storage layers formed between the first to eighth vertical channel layers and the first to eighth multilayer conductive layers;a first pipe channel layer formed in the semiconductor substrate to couple lower portions of the first and eighth vertical channel layers;a second pipe channel layer formed in the semiconductor substrate to couple lower portions of the second and third vertical channel layers;a third pipe channel layer ...

Three-dimensional memory device containing annular etch-stop spacer and method of making thereof

A monolithic three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, an insulating cap layer overlying the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers and overlying the insulating cap layer, memory openings extending through the second alternating stack, the insulating cap layer, and the first alternating stack, memory stack structures located within the memory openings, and annular spacers located within the insulating cap layer and laterally surrounding a respective one of the memory stack structures.

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion. 1. A semiconductor memory device , comprising:a semiconductor pillar extending in a first direction;a first electrode extending in a second direction crossing the first direction;a second electrode provided between the semiconductor pillar and the first electrode;a first insulating film provided between the semiconductor pillar and the second electrode; anda second insulating film provided between the first electrode and the second electrode, a thin sheet portion disposed on the first electrode side, and', 'a thick sheet portion disposed on the semiconductor pillar side, a length in the first direction of the thick sheet portion being longer than a length in the first direction of the thin sheet portion., 'the second electrode including'}2. The device according to claim 1 , wherein a first layer disposed between the thin sheet portion and the first electrode and on two first-direction sides of the thin sheet portion; and', 'a second layer disposed between the first layer and the first electrode and on two first-direction sides of the first electrode., 'the second insulating film includes3. The device according to claim 2 , wherein a portion of the second layer is disposed on two first-direction sides of the first ...

Semiconductor memory device

A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.

Semiconductor memory device and method of manufacturing the same

According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.

METHODS AND APPARATUS FOR THREE-DIMENSIONAL NAND NON-VOLATILE MEMORY DEVICES WITH SIDE SOURCE LINE AND MECHANICAL SUPPORT

A method of fabricating a monolithic three dimensional memory structure is provided. The method includes forming a stack of alternating word line and dielectric layers above a substrate, forming a source line above the substrate, forming a memory hole extending through the alternating word line and dielectric layers and the source line, and forming a mechanical support element on the substrate adjacent to the memory hole. 1. A method of fabricating a monolithic three dimensional memory structure , the method comprising:forming a stack of alternating word line and dielectric layers above a substrate;forming a source line above the substrate;forming a memory hole extending through the alternating word line and dielectric layers and the source line; andforming a mechanical support element on the substrate adjacent to the memory hole.2. The method of claim 1 , further comprising:forming a vertical channel in the memory hole;forming an outer layer and a channel in the memory hole;selectively removing a portion of the outer layer to expose a peripheral exterior of the channel; andforming the source line in contact with the exposed peripheral exterior of the channel.3. The method of claim 2 , wherein forming the mechanical support element comprises forming the mechanical support element adjacent the exposed peripheral exterior of the channel.4. The method of claim 1 , further comprising:forming a sacrificial material layer on the substrate;etching a trench in the sacrificial material layer and the substrate; andforming the mechanical support element in the trench.5. The method of claim 4 , further comprising:selectively removing the sacrificial material layer; andreplacing the sacrificial material with the source line.6. The method of claim 1 , further comprising forming a plurality of mechanical support elements on the substrate adjacent to the memory hole.7. The method of claim 1 , wherein forming the mechanical support element comprises forming a first plurality of ...

THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE

A three-dimensional semiconductor memory device is provided. A stacked structure is formed on a substrate. The stacked structure includes conductive patterns vertically stacked on the substrate. A selection structure including selection conductive patterns is stacked on the stacked structure. A channel structure penetrates the selection structure and the stacked structure to connect to the substrate. An upper interconnection line crosses the selection structure. A conductive pad is disposed on the channel structure to electrically connect the upper interconnection line to the channel structure. A bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the selection conductive patterns. 1. A three-dimensional semiconductor memory device , comprising:a stacked structure including a plurality of conductive patterns vertically stacked on a substrate;a selection structure including a plurality of selection conductive patterns stacked on the stacked structure;a channel structure penetrating the selection structure and the stacked structure to connect to the substrate;an upper interconnection line crossing the selection structure; anda conductive pad disposed on the channel structure to electrically connect the upper interconnection line to the channel structure,wherein a bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the plurality of selection conductive patterns,wherein the conductive pad has impurities of a first conductivity type, and the channel structure comprises a channel impurity region having impurities of a second conductivity type and positioned adjacent to at least one of the plurality of selection conductive patterns, andwherein bottom surfaces of the channel impurity region and the conductive pad are positioned at different vertical levels.2. The device of claim 1 , wherein the bottom surface of the conductive pad is ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; 1a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film;a first conductive body contacting the stacked body to extend in a stacking direction;a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films,the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a lower surface of the projecting part contacting an upper surface of the one of the first conductive films; anda second insulating film configured from a material different from that of the first insulating film, disposed on the one of the first conductive films of the stacked body, and disposed in the same layer as the projecting part of the first conductive body.. A semiconductor device, comprising: The present application is a continuation application of U.S. application Ser. No. 15/074,338, filed on Mar 18, 2016, which is based upon and claims the benefit of priority from the prior U.S. Provisional Application 62/301,903, filed on Mar. 1, 2016, the entire contents of both of which are incorporated herein by reference.Embodiments of the present invention relate to a semiconductor device and a method of manufacturing the same.A flash memory is a semiconductor device known for its low cost and large capacity. One example of a semiconductor device to replace the flash memory is a variable resistance type memory (ReRAM: Resistance RAM) which employs a variable resistance film in its memory cell. The ReRAM can configure a cross-point type memory cell array, hence can achieve an increased capacity similarly to the flash memory. Moreover, in order to further increase capacity, there is also being ...

THREE-DIMENSIONAL MEMORY DEVICE HAVING ON-PITCH DRAIN SELECT GATE ELECTRODES AND METHOD OF MAKING THE SAME

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and an array of memory opening fill structures extending through the alternating stack, an array of drain-select-level assemblies overlying the alternating stack and having a same two-dimensional periodicity as the array of memory opening fill structures, a first strip electrode portion laterally surrounding a first set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies, and a drain-select-level isolation strip including an isolation dielectric that contacts the first strip electrode portion and laterally spaced from the drain-select-level assemblies and extending between the first strip electrode portion and a second strip electrode portion. 1. A three-dimensional memory device , comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate;an array of memory opening fill structures extending through the alternating stack and arranged as rows that extend along a first horizontal direction and are spaced apart along a second horizontal direction, wherein each of the memory opening fill structures comprises a memory film and a memory-level channel portion;an array of drain-select-level assemblies overlying the alternating stack and having a same two-dimensional periodicity as the array of memory opening fill structures, wherein each of the drain-select-level assemblies comprises a drain-select-level channel portion contacting a respective memory-level channel portion, a drain region contacting an upper end of the drain-select-level channel portion, and a gate dielectric laterally surrounding the drain-select-level channel portion;a first strip electrode portion laterally surrounding a first set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies; anda drain-select-level ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device according to the present technology includes a stack body including a lower conductive pattern and an upper conductive pattern stacked apart from each other in a first direction, and at least one intermediate conductive pattern disposed between the lower conductive pattern and the upper conductive pattern, a contact plug connected to the lower conductive pattern and extending in the first direction, and at least one lower dummy plug overlapping the lower conductive pattern. 1. A semiconductor memory device comprising:a stack body including a lower conductive pattern and an upper conductive pattern stacked apart from each other in a first direction, and at least one intermediate conductive pattern disposed between the lower conductive pattern and the upper conductive pattern;a first contact plug connected to the lower conductive pattern and extending in the first direction; andat least one lower dummy plug overlapping the lower conductive pattern and extending in the first direction.2. The semiconductor memory device of claim 1 , wherein the at least one lower dummy plug is formed to be narrower than the first contact plug in a plane orthogonal to the first direction.3. The semiconductor memory device of claim 1 , wherein the at least one lower dummy plug is formed to be shorter than the first contact plug in the first direction.4. The semiconductor memory device of claim 1 , wherein the lower dummy plug is spaced apart from the lower conductive pattern in the first direction.5. The semiconductor memory device of claim 1 , further comprising:a second contact plug connected to the upper conductive pattern and extending in the first direction; andat least one upper dummy plug formed to be narrower than the second contact plug in the plane perpendicular to the first direction and overlapping the upper conductive pattern.6. The semiconductor memory device of claim 5 , further comprising:a third contact plug connected to the intermediate ...

MEMORY ARRAY HAVING CONNECTIONS GOING THROUGH CONTROL GATES

Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates. 1. An apparatus comprising:a first memory array including a first memory cell string over a substrate, and a first select gate and control gates located along a body of the first memory string and over the substrate;a second memory array including a second memory cell string over the substrate, and a second select gate and control gates located along a body of the second memory string and over the substrate;a first connection coupled to the first select gate and including a portion going through a portion of a first control gate among the control gates of the first memory array;a second connection coupled to the second select gate and including a portion going through a portion of a second control gate among the control gates of the second memory array; anda third connection coupling the first connection to the second connection.2. The apparatus of claim 1 , wherein the third connection includes a segment parallel to substrate.3. The apparatus of claim 2 , wherein the first connection includes a first segment perpendicular to the substrate claim 2 , a second segment perpendicular to the substrate claim 2 , and a third segment coupling the first segment to the second segment claim 2 , the third segment being parallel to the substrate.4. The apparatus of claim 3 , wherein the second connection includes a first segment perpendicular to the substrate claim 3 , a second segment perpendicular to the substrate ...

MEMORY CELL STRUCTURE OF A THREE-DIMENSIONAL MEMORY DEVICE

Various embodiments disclose a 3D memory device, including a substrate; a plurality of conductor layers disposed on the substrate; a plurality of NAND strings disposed on the substrate; and a plurality of slit structures disposed on the substrate. The plurality of NAND strings can be arranged perpendicular to the substrate and in a hexagonal lattice orientation including a plurality of hexagons, and each hexagon including three pairs of sides with a first pair perpendicular to a first direction and parallel to a second direction. The second direction is perpendicular to the first direction. The plurality of slit structures can extend in the first direction. 1. A three-dimensional (3D) memory device , comprising:an alternating conductor/dielectric stack disposed on a substrate; anda plurality of channel structures extending vertically through the alternating conductor/dielectric stack, wherein the plurality of channel structures are arranged in a hexagonal lattice.2. The 3D memory device of claim 1 , further comprising:a slit extending vertically through the alternating conductor/dielectric stack, wherein the slit is arranged in a zigzag pattern extending laterally in a first direction.3. The 3D memory device of claim 2 , wherein the hexagonal lattice comprises a plurality of hexagons claim 2 , each having three pairs of sides claim 2 , wherein:a first pair of side is perpendicular to the first direction; anda second pair and a third pair of sides are parallel to the slit in the zigzag pattern.4. The 3D memory device of claim 2 , wherein the slit is configured to divide the 3D memory device into multiple memory blocks and/or multiple memory fingers.5. The 3D memory device of claim 2 , wherein the slit is configured as a common source contact for the plurality of channel structures.6. The 3D memory device of claim 2 , further comprising:a top select gate, parallel to the slit, wherein the top select gate is arranged in a zigzag pattern extending in the first direction ...

Multi-gate string drivers having shared pillar structure

Some embodiments include apparatuses, and methods of forming the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a pillar extending through the conductive materials and the dielectric materials, memory cells located along the first pillar, a conductive contact coupled to a conductive material of the first group of conductive materials, and additional pillars extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion of each of the additional pillars is part of a piece of material extending from a first pillar to a second pillar of the additional pillars.

METHOD FOR ETCHING BOTTOM PUNCH-THROUGH OPENING IN A MEMORY FILM OF A MULTI-TIER THREE-DIMENSIONAL MEMORY DEVICE

First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film. 1. A method of forming a three-dimensional memory device comprising:forming a first alternating stack of first insulating layers and first spacer material layers over a semiconductor material layer;forming first memory openings through the first alternating stack, wherein a top surface of the semiconductor material layer is physically exposed at a bottom of each of the first memory openings;filling each of the first memory openings with a first memory film, a sacrificial liner, and a first-tier opening fill material portion;forming a second alternating stack of second insulating layers and second spacer material layers over the first alternating stack and the first-tier opening fill material portions;forming second memory openings through the second alternating stack, wherein a top surface of a respective one of the first-tier opening fill material portions is physically exposed at a bottom of each of the second memory openings;forming a second memory film within each of the second memory openings;removing the first-tier opening fill material portions selective to the sacrificial liners;removing the sacrificial liners selective to the second memory films and the first memory films; ...

VERTICAL TYPE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

A vertical type semiconductor device includes a substrate that has a plurality of trenches, a support pattern that fills the plurality of trenches and protrudes from a top surface of the substrate, a semiconductor layer disposed on the substrate that fills a space between the support patterns, a stacked structure disposed on the support pattern and the semiconductor layer that includes a plurality of insulation layers and a plurality of first conducive patterns that are alternately and repeatedly stacked, and a plurality of channel structures that penetrate through the structure and the semiconductor layer and that extend into the support pattern. Each channel structure includes a channel layer. At least a portion of the channel layer makes contact with the semiconductor layer. 1. A method for manufacturing a vertical semiconductor device , comprising:forming a lower stacked layer including a lower sacrificial layer on a substrate;forming a mold structure on the lower stacked layer, the mold structure including insulation layers and sacrificial layers alternately stacked;forming preliminary channel structures passing through the mold structure and the lower stacked layer and extending to an inner portion of the substrate, each of the preliminary channel structures including a channel layer, a preliminary tunnel insulation layer, a preliminary charge storage layer and a preliminary blocking layer;etching the mold structure to form a first trench extending in one direction, and the lower sacrificial layer being exposed by a bottom portion of the first trench;removing the lower sacrificial layer exposed by the first trench to form a first gap between the substrate and the mold structure;sequentially etching portions of the preliminary blocking layer, the preliminary charge storage layer and the preliminary tunnel insulation layer through the first gap to expose channel layer; andforming a semiconductor pattern that fills the first gap and forms channel structures, ...

Three-dimensional semiconductor memory device

A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.

Assemblies Having Conductive Structures with Three or More Different Materials

Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions. 1. A memory cell , comprising:a conductive gate; the conductive gate including at least three different materials; said at least three different materials including a first material having an outer perimeter in a cross-section, a second material directly adjacent the first material and compositionally different than the first material, and a third material directly adjacent the second material and compositionally different than each of the first and second materials; the first and third materials comprising metal and being electrically conductive, the third material being present along an entirety of the outer perimeter of the first material in the cross-section;a charge-blocking region adjacent the conductive gate;a charge-storage region adjacent the charge-blocking region;tunneling material adjacent the charge-storage region; andchannel material adjacent the tunneling material, the tunneling material being between the channel material and the charge-storage region.2. The memory cell of wherein the first material comprises one or more of Co claim 1 , Mo claim 1 , Ni claim 1 , Ru and W.3. The memory cell of wherein the first material consists of one or more of Co claim 1 , Mo claim 1 , Ni claim 1 , Ru and W.4. The memory cell of wherein the second material comprises one or more compositions selected from the group consisting of metal nitrides claim 1 , metal carbides claim 1 , metal borides claim 1 , metal oxides and metal carbonitrides.5. The memory cell of wherein the second material comprises one or more of AlO claim 1 , ...

COMPACT NON-VOLATILE MEMORY DEVICE

A non-volatile memory cell includes a selection transistor having an insulated selection gate embedded in a semiconducting substrate region. A semiconducting source region contacts a lower part of the insulated selection gate. A state transistor includes a floating gate having an insulated part embedded in the substrate region above an upper part of the insulated selection gate, a semiconducting drain region, and a control gate insulated from the floating gate and located partially above the floating gate. The source region, the drain region, the substrate region, and the control gate are individually polarizable. 1. A method of erasing a memory cell , the method comprising:applying a first voltage to a control gate of the memory cell, wherein the control gate is disposed over and insulated from a floating gate of the memory cell, wherein the floating gate comprises an embedded portion disposed over and insulated from a selection gate of the memory cell, wherein the embedded portion of the floating gate is located between a first substrate region of a semiconductor substrate and a second substrate region of the semiconductor substrate, wherein the floating gate further comprises a projecting portion extending out of the semiconductor substrate and disposed over the embedded portion of the floating gate and below the control gate, wherein the selection gate is embedded in the semiconductor substrate and below the embedded portion of the floating gate, wherein the selection gate is located between the first substrate region of the semiconductor substrate and the second substrate region of the semiconductor substrate, wherein the semiconductor substrate further comprises a source region disposed below the selection gate, the first substrate region of the semiconductor substrate, and the second substrate region of the semiconductor substrate;applying a second voltage to the first substrate region of the semiconductor substrate; andapplying a third voltage to the second ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

According to one embodiment, a stacked body includes a plurality of conductive layers stacked with an insulator interposed. The stacked body includes a first stacked portion and a second stacked portion. The second stacked portion includes a plurality of terrace portions arranged in a staircase configuration with level differences in a first direction and a second direction. The second stacked portion includes a conductive portion and a spacer portion. The conductive portion is connected to the conductive layer and is provided in same layer as the conductive layer. The spacer portion is provided in same layer as the conductive layer and the conductive portion. The spacer portion is of a material different from the conductive portion. 1. A semiconductor device , comprising:a stacked body including a plurality of conductive layers stacked with an insulator interposed, the stacked body including a first stacked portion and a second stacked portion, the second stacked portion including a plurality of terrace portions arranged in a staircase configuration with level differences in a first direction and a second direction, the second direction crossing the first direction; anda columnar portion extending in a stacking direction of the stacked body through the first stacked portion, a conductive portion connected to a conductive layer of the first stacked portion and provided in same layer as the conductive layer, the conductive layer being one layer of the conductive layers, and', 'a spacer portion provided in same layer as the conductive layer and the conductive portion, the spacer portion being of a material different from the conductive portion., 'one of the terrace portions in the second stacked portion including'}2. The device according to claim 1 , wherein the spacer portion is an insulating portion.3. The device according to claim 1 , wherein the insulator is a silicon oxide layer claim 1 , and the spacer portion is a silicon nitride layer.4. The device according ...

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ALUMINUM-SILICON WORD LINES AND METHODS OF MANUFACTURING THE SAME

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines. 1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate; andmemory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film, and extends through each of the electrically conductive layers and is laterally surrounded by each of the electrically conductive layers,wherein each of the electrically conductive layers comprises a respective conductive fill material structure including an aluminum-containing portion surrounded on at least three sides by a silicon-containing portion.2. The three-dimensional memory device of claim 1 , wherein at least 85% of all atoms within the aluminum-containing portions comprise aluminum atoms.3. The three-dimensional memory device of claim 1 , wherein at least 95% of all atoms within the silicon-containing portions comprise silicon atoms.4. The three-dimensional memory device of claim 1 , wherein each of electrically conductive layers further comprises a metallic barrier layer embedding the conductive fill material structure.5. The three-dimensional memory device of claim 4 , wherein the metallic barrier ...

STACKED NANOSHEET FIELD EFFECT TRANSISTOR FLOATING-GATE EEPROM CELL AND ARRAY

Semiconductor device, memory arrays, and methods of forming a memory cell include or utilize one or more memory cells. The memory cell(s) include a first nanosheet transistor connected to a first terminal, a second nanosheet transistor located on top of the first nanosheet transistor and connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal, and an access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate. 1. A semiconductor device , comprising:a first nanosheet transistor connected to a first terminal;a second nanosheet transistor located on top of the first nanosheet transistor and connected in parallel to the first nanosheet transistor and connected to a second terminal, where the first and second nanosheet transistors share a common floating gate and a common output terminal; andan access transistor connected in series to the common output terminal and a low voltage terminal, the access transistor configured to trigger hot-carrier injection to the common floating gate to change a voltage of the common floating gate.2. The semiconductor device of claim 1 , wherein the first nanosheet transistor is an n-type nanosheet transistor and the second nanosheet transistor is a p-type nanosheet transistor.3. The semiconductor device of claim 2 , wherein hot-carrier injection is triggered when a voltage across one of the n-type nanosheet transistor and the p-type nanosheet transistor is about 3.0 volts.4. The semiconductor device of claim 1 , wherein a voltage of the common floating gate determines a logical state of the semiconductor device.5. The semiconductor device of claim 1 , wherein the first nanosheet transistor includes a first low injection- ...

3D-Stacked Module with Unlimited Scalable Memory Architecture for Very High Bandwidth and Very High Capacity Data Processing Devices

A 3-D memory module comprising a plurality of packaged integrated memory circuits or devices is mounted to a substrate with integrated pins that are edge-connected on two surfaces where the top surface provides an edge connection from the integrated memory circuits to an orthogonally-mounted memory controller circuit through a wide-word interface. Each integrated memory device can be accessed independently wherein the memory controller is configured to reduce the wide-word interface to a serial interface which is brought to the opposite surface of the memory module for electrical coupling to an external system or printed circuit assembly. 1. A device comprising a plurality of packaged memory integrated circuits mounted to a substrate with integrated pins that are edge connected on two surfaces where the top surface provides an edge connection from the integrated circuits to an orthogonally mounted memory controller through a wide-word interface and configured where each integrated circuit can be accessed independently and wherein the memory controller reduces the wide-word interface to a serial interface which is routed to an opposite face for attachment to a system substrate.2. A method of producing the device of wherein the package substrate uses a lead frame that is soldered or welded to the substrate and each finger of the lead frame is used for aligning the layers to the required pitch to mount the controller as well as providing a means for compliance and flexibility in achieving said pitch.3. A method using the lead frame of wherein after the plurality of packages are stacked and the lead frame fingers are bent in a J-lead fashion to provide a planar surface for mounting the controller circuit.4. A method of communication between cubes using the faces of the module in any direction independently to allow bypassing of routing signals out of the overall physical memory and back in.5. A method of using the enclosure to help channel communication via waveguide ( ...

THREE-DIMENSIONAL NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING REPLACEMENT GATE

The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices. In one aspect, a vertical three-dimensional semiconductor memory device comprises a memory block comprising at least one memory hole formed through a stack of alternating layers of control gate layers and dielectric layers, wherein the memory hole is filled with a plurality of materials forming at least one memory cell. The semiconductor memory device additionally includes at least one trench formed through the stack so as to define part of a boundary of the memory block, wherein a sidewall of the trench comprises the control gate layers each having at least a portion that is in part laterally recessed relative to vertically adjacent dielectric layers, and wherein the trench is filled with an electrically conductive material. 1. A vertical three-dimensional semiconductor memory device , comprising:a memory block comprising at least one memory hole formed through a stack of alternating layers of control gate layers and dielectric layers, wherein the memory hole is filled with a plurality of materials forming at least one memory cell; andat least one trench formed through the stack so as to define part of a boundary of the memory block, wherein a sidewall of the trench comprises the control gate layers each having at least a portion that is in part laterally recessed relative to vertically adjacent dielectric layers, and wherein the trench is filled with an electrically conductive material.2. The memory device of claim 1 , wherein the control gate layers comprise semiconductor layers claim 1 , and wherein the electrically conductive material comprises a metallic material.3. The memory device of claim 1 , wherein the electrically conductive material comprises one or more of tungsten claim 1 , tungsten nitride claim 1 , tantalum claim 1 , tantalum nitride claim 1 , ...

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING HYDROGEN DIFFUSION BARRIER LAYER FOR CMOS UNDER ARRAY ARCHITECTURE AND METHOD OF MAKING THEREOF

A semiconductor structure includes a semiconductor device, a hydrogen diffusion barrier layer, a lower metal line structure located below the hydrogen diffusion barrier layer, an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack in a memory array region, a through-stack contact via structure extending through the alternating stack and through the hydrogen diffusion barrier layer in the memory array region and contacting the lower metal line structure, and a through-stack insulating spacer laterally surrounding the through-stack contact via structure and extending through the alternating stack but not extending through the hydrogen diffusion barrier layer. 1. A semiconductor structure , comprising:at least one semiconductor device;a dielectric layer stack of at least one first dielectric material layer, a silicon nitride layer comprising a hydrogen diffusion barrier, and at least one second dielectric material layer overlying the at least one semiconductor device;lower metal interconnect structures embedded within the dielectric layer stack, the lower metal interconnect structures comprising a lower metal line structure located below the silicon nitride layer;a three-dimensional memory array overlying the dielectric layer stack and including an alternating stack of insulating layers and electrically conductive layers, and including memory stack structures vertically extending through the alternating stack in a memory array region;a through-stack contact via structure extending through the alternating stack, through the at least one second dielectric material layer, and through the silicon nitride layer, and contacting the lower metal line structure; anda through-stack insulating spacer laterally surrounding the through-stack contact via structure and extending through the alternating stack and through the at least one second dielectric material layer, but not extending ...

Semiconductor device and method for manufacturing same

According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided above the foundation layer, a columnar portion, a hole, and a sealing film. The stacked body includes a plurality of conductive layers stacked with an air gap interposed. The columnar portion includes a semiconductor body. The semiconductor body extends in a stacking direction of the stacked body through the stacked body and contacts the foundation layer. The hole extends in the stacking direction through the stacked body and forms a cavity communicating with the air gap. The sealing film plugs an upper end of the hole forming the cavity.

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a semiconductor layer having a termination region surrounding a device region, the termination region including a first stacked body having a first, insulating, layer located on a surface of the substrate, a second, conductive, layer located over the first layer, and a third, insulating, layer located over the second layer, an opening extending through the first stacked body, a fourth, insulating, layer located in the opening in the first stacked body and over the surface of the semiconductor substrate in the opening, a fifth, insulating, layer, located over the fourth layer, and a wall surrounding the device region, the wall extending inwardly of the opening and contacting one of the surface of the semiconductor substrate or a nitride material on the surface of the substrate, wherein the composition of the third and fifth layers is different from that of the first and third layers. 1. A semiconductor memory device , comprising:a semiconductor substrate comprising a termination region surrounding a device region thereof, the termination region comprising a first stacked body extending around the device region and including a first layer composed of an insulating material located on a surface of the substrate, a second layer composed of a conductive material located over the first layer, and a third layer composed of an insulating material located over the second layer;an opening extending through the first stacked body and extending around the device region;a fourth layer, composed of an insulating material, located in the opening in the first stacked body and over the surface of the semiconductor substrate in the opening;a fifth layer, composed of an insulating material, located over the fourth layer; anda wall surrounding the device region, the wall extending inwardly of the opening and contacting one of the surface of the semiconductor substrate or a nitride material on the surface of the substrate, whereinthe composition of ...

SEMICONDUCTOR DEVICES

A semiconductor device may include a plurality of conductive patterns and an insulation pattern. The plurality of conductive patterns may be formed on a substrate. The plurality of conductive patterns may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate. Each of the plurality of conductive patterns may have an extension portion and a step portion. The step portion may be disposed at an edge of the corresponding conductive pattern. The insulation pattern may be formed between the plurality of conductive patterns in the vertical direction. A lower surface and an upper surface of the step portion of each of the plurality of conductive patterns may be bent upwardly. 1. A semiconductor device comprising:a plurality of conductive patterns disposed on a substrate, each of the plurality of conductive patterns being spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the substrate, each of the plurality of conductive patterns having an extension portion and a step portion, the step portion being disposed at an edge of a corresponding one of the plurality of conductive patterns; andan insulation pattern disposed between each of the plurality of conductive patterns in the vertical direction,wherein a lower surface of the step portion and an upper surface of the step portion of each of the plurality of conductive patterns are bent upwardly.2. The semiconductor device of claim 1 , wherein a first length of the insulation pattern is less than a second length of each of the plurality of conductive patterns that adjoins the insulation pattern.3. The semiconductor device of claim 1 , wherein a recess is defined by a sidewall of the insulation pattern claim 1 , an upper surface of a first one of the plurality of conductive patterns that is in contact with a lower surface of the insulation pattern and a lower surface of a second one of the plurality of conductive patterns that is in ...

Semiconductor Constructions, Methods of Forming Vertical Memory Strings, and Methods of Forming Vertically-Stacked Structures

Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures. 1. A memory device , comprising:a stack of alternating electrically conductive levels and electrically insulative levels over a material comprising tungsten silicide;electrically insulative pillars that extends through the stack and contact an upper surface of the material comprising tungsten silicide;a channel material post between a first adjacent pair of the pillars, the channel material post extending through the material comprising tungsten silicide and having a first pair of opposing sides and a second pair of opposing sides; each side of the first pair of opposing sides being spaced from a respective one of a second adjacent pair of the pillars by a corresponding intervening region of the stack; none of the stack being present between each side of the second pair of opposing sides and a respective one of the first adjacent pair of the pillars;gate dielectric material and charge-storage material between edges of the electrically conductive levels and the channel material post.2. The memory device of claim 1 , further comprising charge blocking material ...

THREE DIMENSIONAL NAND DEVICE WITH BIRDS BEAK CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF

A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer. 1. A method of making a monolithic , three dimensional array of memory devices located over a silicon substrate , comprising an array of vertically oriented NAND strings in which at least one memory cell in a first device level of the array is located over another memory cell in a second device level , the method comprising:forming an integrated circuit comprising a driver circuit for the array of memory devices on the silicon substrate;forming a stack of alternating layers of a first material and a second material over the silicon substrate, wherein the first material comprises an electrically insulating material and wherein the second material comprises a semiconductor or conductor material;etching the stack to form a front side opening in the stack;forming a blocking dielectric layer of at least one NAND string of the array over the stack of alternating layers of a first material and a second material exposed in the front side opening;forming a semiconductor or metal charge storage layer of the at least one NAND string over the blocking dielectric; ...

SEMICONDUCTOR STORAGE DEVICE

A semiconductor storage device includes: a first memory cell and a second memory cell that are adjacent to each other and connected to each other in series; a first word line connected to the first memory cell; a second word line connected to the second memory cell; and a control circuit. The control circuit is configured to, in a first read operation to read a first bit stored in the first memory cell, apply a first voltage to the first word line, and then, apply a first read voltage lower than the first voltage, to the first word line, and apply a second voltage to the second word line, and then, apply a third voltage lower than the second voltage and higher than the first voltage, to the second word line. The third voltage is applied to the second word line after the first read voltage is applied to the first word line. 1. A semiconductor storage device comprising:a first memory cell;a second memory cell adjacent to the first memory cell and connected to the first memory cell in series;a first word line connected to the first memory cell;a second word line connected to the second memory cell; and read, in a first read operation, a first bit stored in the first memory cell,', 'apply a first voltage to the first word line, and then, apply a first read voltage lower than the first voltage, to the first word line, and', 'apply a second voltage to the second word line, and then, apply a third voltage lower than the second voltage and higher than the first voltage, to the second word line,', 'wherein the third voltage is applied to the second word line after the first read voltage is applied to the first word line., 'a control circuit configured to2. The semiconductor storage device according to claim 1 , wherein the control circuit is configured to:read, in a second read operation, a second bit stored in the first memory cell,apply the first voltage to the first word line, and then, apply a second read voltage lower than the first voltage and higher than the first ...

Integrated Circuitry, A Method Used In Forming Integrated Circuitry, And A Method Used In Forming A Memory Array Comprising Strings Of Memory Cells

A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers comprise doped silicon dioxide and the second tiers comprise undoped silicon dioxide. Horizontally-elongated trenches are formed into the stack. Through the trenches, the doped silicon dioxide that is in the first tiers is etched selectively relative to the undoped silicon dioxide that is in the second tiers. Conducting material is formed in the void space in the first tiers that is left by the etching. Structure independent of method is disclosed.

SEMICONDUCTOR STRUCTURE

A semiconductor structure includes a stack of memory cells and a CMOS structure. The CMOS structure is located below the stack of memory cells. The CMOS structure includes a source line transistor and a bit line transistor. 1. A semiconductor structure , comprising:a stack of memory cells, anda CMOS structure, located below the stack of memory cells, wherein the CMOS structure comprises a source line transistor and a bit line transistor.2. The semiconductor structure according to claim 1 , wherein the source line transistor is adjacent to the bit line transistor.3. The semiconductor structure according to claim 1 , wherein the stack of memory cells does not overlap the source line transistor and the bit line transistor.4. The semiconductor structure according to claim 1 , further comprising:a local bit line, located above the stack of memory cells, anda first pillar element, located between the local bit line and the bit line transistor, wherein the local bit line is electrically connected to the bit line transistor through the first pillar element.5. The semiconductor structure according to claim 4 , further comprising:an insulating stack, adjacent to the stack of memory cells,wherein the first pillar element penetrates the insulating stack, and the first pillar element transmits a signal in the local bit line to the bit line transistor.6. The semiconductor structure according to claim 1 , further comprising:a first metal layer, located above the bit line transistor,a second pillar element, located above the first metal layer, anda global bit line, located above the stack of memory cells,wherein the bit line transistor is electrically connected to the global bit line through the first metal layer and the second pillar element.7. The semiconductor structure according to claim 6 , further comprising:a second metal layer, located between the first metal layer and the second pillar element, wherein the bit line transistor is electrically connected to the global bit ...

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE

A three-dimensional semiconductor memory device includes a peripheral circuit structure having peripheral circuits on a semiconductor substrate, and landing pads connected to the peripheral circuits, an electrode structure on the peripheral circuit structure, the electrode structure including vertically stacked electrodes, a planarized dielectric layer that covers the electrode structure, peripheral through plugs spaced apart from the electrode structure, the peripheral through plugs penetrating the planarized dielectric layer to connect to the landing pads, conductive lines connected through contact plugs, respectively, to the peripheral through plugs, and at least one dummy through plug adjacent to a first peripheral through plug of the peripheral through plugs, the at least one dummy through plug penetrating the planarized dielectric layer and being insulated from the conductive lines. 1. A three-dimensional semiconductor memory device , comprising: peripheral circuits on a semiconductor substrate, and', 'landing pads connected to the peripheral circuits;, 'a peripheral circuit structure includingan electrode structure on the peripheral circuit structure, the electrode structure including vertically stacked electrodes;a planarized dielectric layer that covers the electrode structure;peripheral through plugs spaced apart from the electrode structure, the peripheral through plugs penetrating the planarized dielectric layer to connect to the landing pads;conductive lines connected through contact plugs, respectively, to the peripheral through plugs; andat least one dummy through plug adjacent to a first peripheral through plug of the peripheral through plugs, the at least one dummy through plug penetrating the planarized dielectric layer and being insulated from the conductive lines.2. The device as claimed in claim 1 , wherein the peripheral through plugs include:a second peripheral through plug spaced apart at a first distance from the first peripheral through ...

Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells

A memory array comprising strings of memory cells comprises an upper stack above a lower stack. The lower stack comprises vertically-alternating lower conductive tiers and lower insulative tiers. The upper stack comprises vertically-alternating upper conductive tiers and upper insulative tiers. An intervening tier is vertically between the upper and lower stacks. The intervening tier is at least predominantly polysilicon and of different composition from compositions of the upper conductive tier and the upper insulative tier immediately-above the intervening tier and of different composition from compositions of the lower conductive tier and the lower insulative tier immediately-below the intervening tier. Channel-material strings of memory cells extend through the upper stack, the intervening tier, and the lower stack. Other structures and methods are disclosed. 1. A method used in forming a memory array comprising strings of memory cells , comprising: (a): of a thickness greater than that of the upper first tier and that of the upper second tier immediately-above the intervening tier and greater than that of the lower first tier and that of the lower second tier immediately-below the intervening tier;', '(b): at least predominantly polysilicon and of different composition from compositions of the upper first tier and the upper second tier immediately-above the intervening tier and of different composition from compositions of the lower first tier and the lower second tier immediately-below the intervening tier; and', '(c): at least predominantly conductive and of different composition from the compositions of the upper first tier and the upper second tier immediately-above the intervening tier and of different composition from the compositions of the lower first tier and the lower second tier immediately-below the intervening tier;, 'forming an upper stack above a lower stack, the lower stack comprising vertically-alternating lower first tiers and lower second ...

THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

A three-dimensional memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate; a first stairway structure and a second stairway structure defined in the electrode structure, and positioned at different heights from each other; a sidewall of the electrode structure formed due to a difference in height between the first stairway structure and the second stairway structure; and a dielectric support passing through the electrode structure, and isolating a corner portion of the sidewall from the plurality of electrode layers. 1. A three-dimensional memory device comprising:an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers, which are alternately stacked on a substrate;a first stairway structure and a second stairway structure, defined in the electrode structure, and positioned at different heights from each other;a sidewall of the electrode structure between the first stairway structure and the second stairway structure; anda dielectric support passing through the electrode structure and isolating a corner portion of the sidewall from the plurality of electrode layers.2. The three-dimensional memory device of claim 1 , wherein the dielectric support is formed of the same material as the plurality of interlayer dielectric layers.3. The three-dimensional memory device of claim 1 , wherein the dielectric support includes an oxide.4. The three-dimensional memory device of claim 1 , wherein the dielectric support comprises a pillar that passes through the electrode structure at the corner portion.5. The three-dimensional memory device of claim 1 , wherein the dielectric support has a shape corresponding to a shape of the corner portion when viewed from the top.6. The three-dimensional memory device of claim 1 , wherein the dielectric support comprises:a vertical pillar passing through the ...

Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells

A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells are in the stack. The channel-material strings project upwardly from material of an uppermost of the tiers. A first insulator material is above the material of the uppermost tier directly against sides of channel material of the upwardly-projecting channel-material strings. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is above the first insulator material. The first and second insulator materials comprise different compositions relative one another. Conductive vias in the second insulator material are individually directly electrically coupled to individual of the channel-material strings. Other embodiments, including methods, are disclosed. 128-. (canceled)29. A memory array comprising strings of memory cells , comprising:a vertical stack comprising alternating insulative tiers and conductive tiers, channel-material strings of memory cells in the stack, the channel-material strings projecting upwardly from material of an uppermost of the tiers;a first insulator material above the material of the uppermost tier directly against sides of channel material of the upwardly-projecting channel-material strings, the first insulator material comprising at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide;second insulator material above the first insulator material, the first and second insulator materials comprising different compositions relative one another; andconductive vias in the second insulator material that are individually directly electrically coupled to individual of the channel-material strings.30. The memory array of comprising NAND. ...

MEMORY HAVING MEMORY CELL STRING AND COUPLING COMPONENTS

Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described. 1. An apparatus comprising:a memory device; and a first pillar;', 'first memory cells and associated control gates located in different levels of the memory device and along a first portion of the first pillar;', 'a first select gate, a control line, and a second select gate located in different levels of the memory device and along a second portion of the first pillar;', 'a second pillar, and second memory cells located in different levels of the memory device and along a first portion of the second pillar;', 'third memory cells located in different levels of the memory device and located along a third pillar;', 'a first conductive material coupled to the first pillar and the second pillar, wherein the first select gate, the control line, and the second select gate are between the first conductive material and the first memory cells;', 'a second conductive material coupled to the third memory cells; and', 'a first coupling component located along the second portion of the first pillar, the first coupling component being between the first select gate and the second select gate;', 'a second coupling component located along a second portion of the second pillar; and', 'a third coupling component coupled to the second conductive material and the third memory cells and located between the second conductive material and the third memory cells., 'an external device coupled to the memory device, the memory device including2. The apparatus of claim 1 , wherein the external device includes a memory controller.3. The apparatus of claim 1 , wherein the external device includes a processor.4. The ...

MEMORY SYSTEM AND SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device. 1. A memory system comprising:a semiconductor memory device including a first memory cell configured to store data; anda controller configured to output a first parameter and a first command, the first parameter relating to an erase voltage for a first erase operation with respect to the first memory cell, the first command instructing the first erase operation,wherein the controller is configured to output the first command after outputting the first parameter to the semiconductor memory device.2. The memory system according to claim 1 , wherein the first parameter includes at least one of a pulse time and a voltage value of an erase voltage that is applied to the first memory cell when the first erase operation is executed.3. The memory system according to claim 1 , wherein:the semiconductor memory device includes a block containing a plurality of memory cells including the first memory cell; andthe controller is configured to instruct the first erase operation with respect to the block.4. The memory system according to claim 1 , wherein:the semiconductor memory device includes a plurality of memory cells including the first memory cell; and output a second parameter relating to a first voltage for a read operation with respect to the first memory cell;', 'obtain a first number that is a number of memory cells in an OFF state among the memory cells during the read operation; and', 'update the first parameter when the first ...

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

Disclosed is a three-dimensional semiconductor device including a horizontal semiconductor layer including a plurality of well regions having a first conductivity and a separation impurity region having a second conductivity, and a plurality of cell array structures provided on the well regions of the horizontal semiconductor layer, respectively. The separation impurity region is between and in contact with the well regions. Each of the cell array structures comprises a stack structure including a plurality of stacked electrodes in a vertical direction to a top surface of the horizontal semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to a corresponding well region. 125.-. (canceled)26. A three-dimensional semiconductor device , comprising:a semiconductor layer including first, second, third, and fourth well regions doped with first conductivity impurities, the first and second well regions that are adjacent to each other in a first direction, the first and third well regions that are adjacent to each other in a second direction crossing the first direction, and the second and fourth regions that are adjacent to each other in the second direction; andfirst, second, third, and fourth cell array structures disposed on the first, second, third, and fourth well regions, respectively; a stack structure including a plurality of stacked electrodes stacked in a vertical direction on a top surface of the semiconductor layer; and', 'a plurality of vertical structures penetrating the stack structure and connected to a corresponding well region,, 'wherein each of the first, second, third, and fourth cell array structure compriseswherein the semiconductor layer further includes a separation impurity region doped with second conductivity impurities, and a first region continuously extending along the second direction between the first and second well regions and between the third and fourth well region; and', 'a second ...

Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells

A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. A first insulator tier is above the stack. First insulator material of the first insulator tier comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in the stack and in the first insulator tier. Conducting material is in the first insulator tier directly against sides of individual of the channel-material strings. A second insulator tier is formed above the first insulator tier and the conducting material. Second insulator material of the second insulator tier comprises at least one of the (a) and the (b). Conductive vias are formed and extend through the second insulator tier and that are individually directly electrically coupled to the individual channel-material strings through the conducting material. Other aspects, including structure independent of method, are disclosed.

VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME

A vertical memory device includes first gate electrodes stacked on a cell region of a substrate and spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel extending through the first gate electrodes and extending in the vertical direction, a first contact plug structure contacting a corresponding one of the first gate electrodes, extending in the vertical direction, and including a first metal pattern, a first barrier pattern covering a lower surface and a sidewall of the first metal pattern and a first metal silicide pattern covering a lower surface and a sidewall of the first barrier pattern, and a second contact plug structure extending in the vertical direction on a peripheral circuit region of the substrate and including a second metal pattern and a second barrier pattern covering a lower surface and a sidewall of the second metal pattern. 1. A method of manufacturing a vertical memory device , the method comprising:forming a circuit pattern on a substrate;forming a first insulating interlayer to cover the circuit pattern;forming first gate electrodes spaced apart from each other on the first insulating interlayer in a vertical direction substantially perpendicular to an upper surface of the substrate, the first gate electrodes being covered by a second insulating interlayer and including a low electrical resistance metal and a metal nitride;forming first contact holes extending through the second insulating interlayer in the vertical direction to expose portions of the first gate electrodes, respectively;forming a polysilicon layer on the exposed portions of the first gate electrodes, sidewalls of the first contact holes, and the second insulating interlayer;forming a barrier layer on the polysilicon layer and the second insulating interlayer;transforming a portion of the barrier layer and the polysilicon layer into a metal silicide layer; andforming first metal patterns to fill ...

METHODS FOR FABRICATING A 3-DIMENSIONAL MEMORY STRUCTURE OF NOR MEMORY STRINGS

A process for manufacturing a -D NOR memory array provides thin-film storage transistors of each NOR memory string in either shafts or portions of a trench between adjacent shafts. 1. A process , comprising:providing over a planar surface of a semiconductor substrate a semiconductor structure which comprises a plurality of active multi-layers which are stacked one on top of another along a first direction that is substantially normal to the planar surface, wherein adjacent active multi-layers are electrically isolated from each other by a layer of dielectric material, and wherein each active multi-layer comprises first and second semiconductor layers of a first conductivity type separated by a dielectric material;providing a plurality of shafts arrayed in a regular pattern along both a second direction and a third direction, the second and third directions being substantially orthogonal to each other and each being orthogonal to the first direction, each shaft extending in depth along the first direction through the semiconductor structure and having a predetermined extent along the second direction;providing a plurality of trenches in the semiconductor structure each extending in depth along the first direction and in length along the third direction, each trench (a) intersecting a plurality of the shafts in the second direction, and (b) having a width along the second direction that is less than the extent of each shaft; andforming, in either (i) each shaft, or (ii) portions of each trench between adjacent shafts: (a) a third semiconductor layer of a second conductivity type opposite the first conductivity type, the third semiconductor layer being formed adjacent to and in contact with the first and second semiconductor layers of each active multi-layer, (b) a charge-trapping layer adjacent the third semiconductor layer; and (c) a conductor layer in contact with the charge-trapping layer.2. The process of claim 1 , wherein the first and second semiconductor layers ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a first stacked structure, a first supporter layer, a second stacked structure, a block cut structure, and a second supporter layer on the second stacked structure and separated by a second cut pattern. The first stacked structure includes a first and second stack, the second stacked structure includes a third stack separated by the block cut structure and a fourth stack, the first supporter layer is on the first stack and the second stack, the second supporter layer is on the third stack and the fourth stack, the first cut pattern includes a first connection on the block cut structure and connecting the first supporter layer and the second stack, and the second cut pattern of the second supporter layer includes a second connection on the block cut structure and connecting the second supporter layer placed on the third stack and the fourth stack. 1. A semiconductor memory device comprising:a first stacked structure on a substrate, the first stacked structure including first gate electrodes stacked in a first direction;a first supporter layer on the first stacked structure, the first supporter layer divided by a first cut pattern;a second stacked structure on the first supporter layer, the second stacked structure including second gate electrodes stacked in the first direction;a block cut structure extending in a second direction intersecting the first direction and cutting at least one of the second stacked structure or the first stacked structure;a second supporter layer on the second stacked structure and divided by a second cut pattern; anda channel structure including a lower channel structure penetrating the first stacked structure, and an upper channel structure penetrating the first supporter layer and the second stacked structure,wherein a width of an upper face of the channel structure in a third direction intersecting the second direction is greater than a width of a lower surface of the channel structure in the third ...

Vertical memory devices

In a semiconductor device, a stack of alternating gate layers and insulating layers is formed over a substrate. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. The first staircase is positioned over the second staircase. The first staircase includes first group stair steps descending in a second direction parallel to the substrate and first division stair steps descending in a third direction and a fourth direction that are parallel to the substrate and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other. The second staircase includes second group stair steps descending in the second direction and second division stair steps descending in the third direction and the fourth direction.

Assemblies Which Include Wordlines Having a First Metal-Containing Material at Least Partially Surrounding a Second Metal-Containing Material and Having Different Crystallinity than the Second Metal-Containing Material

Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. The wordline levels include conductive regions which have a first metal-containing material and a second metal-containing material. The first metal-containing material at least partially surrounds the second metal-containing material. The first metal-containing material has a different crystallinity than the second metal-containing material. In some embodiments the first metal-containing material is substantially amorphous, and the second metal-containing material has a mean grain size within a range of from greater than or equal to about 5 nm to less than or equal to about 200 nm. Charge-storage regions are adjacent the wordline levels. Charge-blocking regions are between the charge-storage regions and the conductive regions. 134-. (canceled)35. A memory cell , comprising:a conductive gate; the conductive gate including a first metal-containing material substantially enveloping a second metal-containing material; the first and second metal-containing materials differing from one another in crystallinity, with the second metal-containing material having a larger mean grain size than the first metal-containing material; the first metal-containing material comprising one or more of the following compositions: metal carbides, metal oxides and metal germides; anda charge-blocking region adjacent the conductive gate; anda charge-storage region adjacent the charge-blocking region.36. The memory cell of wherein the metal within the first metal-containing material comprises one or more of tungsten claim 35 , tantalum claim 35 , titanium claim 35 , ruthenium claim 35 , molybdenum claim 35 , cobalt claim 35 , nickel and aluminum.37. The memory cell of wherein the metal within the second metal-containing material comprises one or more of tungsten claim 35 , tantalum claim 35 , titanium claim 35 , ruthenium ...

SELF-ALIGNED FLOATING GATE IN A VERTICAL MEMORY STRUCTURE

A memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate. Methods for building such a memory device are also disclosed. 1. (canceled)2. A method of manufacturing a memory device comprising:creating a stackup of at least three tier insulating layers alternating with at least two circuit layers, the circuit layers individually include a conductive layer sandwiched between sacrificial layers that are differentiated from the tier insulating layer to allow selective etching of the sacrificial layers without etching the tier insulating layers;creating a hole through the stackup;etching the conductive layers back from the hole;etching the sacrificial layers back from the hole;forming a blocking dielectric film inside at least a portion of the hole, the blocking dielectric film no thicker than an individual sacrificial layer of the sacrificial layers;creating floating gates in the cavities created by the etching of the conductive layers and the sacrificial layers, the floating gates separated from the conductive layers and the tier insulating layers by the blocking dielectric film;forming a tunneling dielectric film inside the hole; andfilling the hole with semiconductor material, the semiconductor material separated from the floating gates by the tunneling dielectric film.3. The method of claim 2 , the conductive layers claim 2 , the floating gates and the semiconductor material comprise polysilicon claim 2 , and the tier insulating layers and the sacrificial layers comprise an oxide or a nitride.4. The method of claim 2 , further comprising:creating an outer oxide film on an ...

Semiconductor memory device and method for manufacturing the same

A semiconductor memory device according to one embodiment, includes a plurality of first interconnects extending in a first direction and arrayed along a second direction crossing the first direction, a plurality of semiconductor pillars arrayed in a row along the first direction in each of spaces among the first interconnects and extending in a third direction crossing the first direction and the second direction, a first electrode disposed between one of the semiconductor pillars and one of the first interconnects, a first insulating film disposed between the first electrode and one of the first interconnects, a first insulating member disposed between the semiconductor pillars in the first direction and extending in the third direction and opposed the first interconnects not via the first insulating film.

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes string select lines extending in a first direction, vertical pillars connected to the string select lines, sub-interconnections on the string select lines, bitlines connected to the vertical pillars through the sub-interconnections, and upper contact plugs connecting the sub-interconnections to the bitlines. The string select lines include odd and even string select lines alternately arranged in a second direction. The sub-interconnections each connect a pair of vertical pillars respectively connected to one of the odd string select lines and one of the even string select lines that are adjacent to each other. Each of the upper contact plugs is between one of the sub-interconnections and one of the bitlines. Each of the upper contact plugs is arranged more adjacent to one string select line of the adjacent string select lines to which the pair of vertical pillars connected by the sub-interconnections are connected. 1. A semiconductor memory device comprising: 'the string select lines including odd string select lines alternately arranged with even string select lines in a second direction that intersects the first direction;', 'string select lines extending in a first direction,'}a plurality of vertical pillars connected to the string select lines; 'the sub-interconnections each connecting a pair of vertical pillars that respectively are connected to one of the odd string select lines and one of the even string select lines that are adjacent to each other from among the string select lines;', 'sub-interconnections on the string select lines,'} 'the bitlines extending in the second direction; and', 'bitlines connected to the plurality of vertical pillars through the sub-interconnections,'} each of the upper contact plugs being between one of the sub-interconnections and one of the bitlines,', 'a distance between each corresponding one of the upper contact plugs and one of the odd and even string select lines connected by a ...

Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells. 113-. (canceled)14. A method of forming vertically-stacked memory cells , comprising:forming a first insulative material over a stack of alternating dielectric levels and conductive levels;forming a first opening through the first insulative material and through the stack of alternating dielectric levels and conductive levels;forming cavities extending into the conductive levels along sidewalls of the first opening;forming a silicon nitride liner within the first opening and extending into the cavities;forming a second insulative material over the silicon nitride liner and over the first insulative material, the second insulative material covering the first opening and not extending downwardly into the first opening to an uppermost level of the stack, a remaining portion of the first opening being beneath the second insulative material;forming select gate material over the second insulative material;forming a second opening the through the select gate material and the second insulative material, and to the remaining portion of the first ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME

A semiconductor structure and a manufacturing method of the same are disclosed. The semiconductor structure includes a conductive layer, a conductive strip, a dielectric layer, and a conductive element. The conductive layer has a first conductive material. The conductive strip is in the same level as the conductive layer and has a second conductive material. The second conductive material is adjoined with the first conductive material having a conductivity characteristic different from a conductivity characteristic of the second conductive material. The conductive element crisscrosses the conductive strip and separated from the conductive strip by the dielectric layer. 1. A semiconductor structure , comprising:a conductive layer having a first conductive material;a conductive strip in the same level as the conductive layer and having a second conductive material, wherein the second conductive material is adjoined with the first conductive material having a conductivity characteristic different from a conductivity characteristic of the second conductive material;a dielectric layer; anda conductive element crisscrossing the conductive strip and separated from the conductive strip by the dielectric layer.2. The semiconductor structure according to claim 1 , comprising a stack of conductive levels each comprising the conductive layer and the conductive strip.3. The semiconductor structure according to claim 2 , wherein the conductive layers of the different levels are exposed by openings of different depths in the stack.4. The semiconductor structure according to claim 1 , comprising a memory array region and a pad region adjacent to the memory array region claim 1 , wherein the conductive strip is in the memory array region claim 1 , the conductive layer is in the pad region.5. The semiconductor structure according to claim 1 , wherein the memory array region and the pad region are non-overlapping.6. The semiconductor structure according to claim 1 , wherein the ...

NON-VOLATILE MEMORY DEVICE

According to one embodiment, a non-volatile memory device includes a plurality of electrodes, at least one semiconductor layer, conductive layers, and first and second insulating films. The electrodes are arranged side by side in a first direction. The semiconductor layer extends into the electrodes in the first direction. The conductive layers are provided between each electrode and the semiconductor layer and separated from each other in the first direction. The first insulating film contacts the conductive layers, and extends in the first direction along the semiconductor layer between the conductive layers and the semiconductor layer. The second insulating film is provided between the first insulating film and the semiconductor layer. The first insulating film includes a first portion located between the conductive layers and the second insulating film, and a second portion located between the interlayer insulating film and the second insulating film. 1. (canceled)2. A non-volatile semiconductor storage device , comprising:a stacked structural unit including a plurality of electrode films stacked in a first direction, the plurality of electrode films including a first electrode film, a second electrode film and a first inter-layer insulating film provided between the first electrode film and the second electrode film;a silicon pillar extending through the stacked structural unit in the first direction;a first insulating film provided between the first electrode film and the silicon pillar;a second insulating film provided between the second electrode film and the silicon pillar;a first silicon film provided between the first insulating film and the silicon pillar;a second silicon film provided between the second insulating film and the silicon pillar;a tunnel insulating film including parts provided between the first silicon film and the silicon pillar, and between the second silicon film and the silicon pillar.3. The non-volatile semiconductor storage device ...

MEMORY CELL PROFILES

Examples of the present disclosure provide devices and methods for processing a memory cell. A method embodiment includes removing a key-hole shaped column from a material, to define a profile for the memory cell. The method also includes partially filling the key-hole shaped column with a first number of materials. The method further includes filling the remaining portion of the key-hole shaped column with a second number of materials. 120-. (canceled)21. A method of processing a memory cell , comprising:removing a column from a material to define a profile for the memory cell, wherein the plurality of memory cells have a cross-sectional shape including a circular portion, a first projecting rectangular portion, and a second projecting rectangular portion;partially filling an outer portion of the column with a first number of materials; andfilling a remaining portion of the column with a second number of materials.22. The method of claim 21 , wherein removing the column comprises:removing the circular portion in a first stage; andremoving the first projecting rectangular portion and the second projecting rectangular portion in a second stage.23. The method of claim 21 , wherein filling the outer portion of the column with the first number of materials comprises:partially filling the column from the outer portion of the column towards an inner portion of the column.24. The method of claim 23 , wherein filling the remaining portion of the column with the second number of materials comprises:filling the inner portion of the column including the circular portion, the first projecting rectangular portion, and the second projecting rectangular portion from the outer portion towards the inner portion.25. The method of claim 21 , wherein removing the column comprises removing the column through a reactive ion etching process.26. The method of claim 21 , further comprising removing the column in a single stage.27. The method of claim 21 , wherein the first projecting ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device may include a first pattern. The semiconductor device may include a second pattern intersecting with the first pattern and including an intersection region with the first pattern and a non-intersection region. 1. A semiconductor device comprising:a first pattern; anda second pattern intersecting with the first pattern and including an intersection region with the first pattern and a non-intersection region, the intersection region having a width less than a width of the non-intersection region.2. The semiconductor device according to claim 1 , wherein the second pattern has a tapered shape in which the width of the second pattern is increased along a longitudinal direction of the second pattern.3. The semiconductor device according to claim 1 , wherein the second pattern has a first width on a first edge of the first pattern and has a second width on a second edge of the first pattern claim 1 , and the first width has a value greater than the second width.4. The semiconductor device according to claim 3 , wherein an end of the second pattern that is adjacent to the first edge has a third width claim 3 , and the third width is the same as the first width or has a value greater than the first width.5. The semiconductor device according to claim 3 , wherein a distance between the first edge and the end of the second pattern has a fourth width claim 3 , and the fourth width has a value greater than ½ of the first width.6. The semiconductor device according to claim 5 , wherein an end of the second pattern that is adjacent to the first edge has a third width claim 5 , and the third width has a value less than the first width and greater than the second width.7. The semiconductor device according to claim 1 , wherein the second pattern has a minimum width on a center of the intersection region and has a shape in which the width of the second pattern is increased from the center of the intersection region to both ends of the second pattern.8. The ...

Vertical memory devices

A vertical memory device includes a substrate including a cell region and a peripheral circuit region, gate electrodes sequentially stacked on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel on the cell region and extending through the gate electrodes in the vertical direction, a first lower contact plug on the peripheral circuit region and extending in the vertical direction, a second lower contact plug on the peripheral circuit region adjacent to the first lower contact plug and extending in the vertical direction, and a first upper wiring electrically connected to the first lower contact plug. The first upper wiring is configured to and apply an electrical signal to the first lower contact plug. The second lower contact plug is not electrically connected to an upper wiring configured to apply an electrical signal.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE INCLUDING BARRIER PATTERN

The invention is related to a method for manufacturing a semiconductor device having a barrier pattern. The method includes alternately forming first sacrificial layers and insulating layers forming channel patterns penetrating the first sacrificial layers and the insulating layers, and forming a slit penetrating the first sacrificial layers and the insulating layers. In order to form the barrier pattern, the method also includes forming openings by removing the first sacrificial layers through the slit, and respectively forming conductive layers in the openings. The conductive layers include first barrier patterns having inclined inner surfaces and metal patterns in the first barrier patterns. 1. A semiconductor device comprising:a stack structure including conductive layers and insulating layers, which are alternately stacked, each of the conductive layers including a first barrier pattern having an inclined inner surface and a metal pattern in the first barrier pattern.2. The semiconductor device of claim 1 , further comprising:channel patterns penetrating the stack structure; anda slit spaced apart from the channel patterns and penetrating the stack structure.3. The semiconductor device of claim 2 , wherein the first barrier pattern includes a first region having the inclined inner surface and a second region having a non-inclined inner surface.4. The semiconductor device of claim 3 , wherein the first region is located closer to the slit than the second region.5. The semiconductor device of claim 3 ,wherein the thickness of the first region decreases as the first region approaches the slit.6. The semiconductor device of claim 3 , wherein the second region of the first barrier pattern has a uniform thickness.7. The semiconductor device of claim 3 , wherein the metal pattern has a uniform thickness in the second region claim 3 , and the thickness of the metal pattern increases as the metal pattern approaches the slit in the first region.8. The semiconductor ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Disclosed is a method of manufacturing a semiconductor device, including: forming a slacked structure including first material layers and second material layers alternately stacked on each other; forming a pillar passing through the stacked structure, the pillar including a protruding portion protruding above an uppermost surface of the stacked structure; forming a conductive layer surrounding the protruding portion of the pillar; and forming a conductive pattern in contact with the protruding portion of the pillar by oxidizing a surface of the conductive layer. 113-. (canceled)14. A semiconductor device , comprising:a stacked structure including conductive layers and insulating layers alternately stacked on each other;an insulating layer on the stacked structure;pillars including an insulating pattern passing through the stacked structure and a part of the insulating layer, a channel pattern surrounding a side wall of the insulating pattern, and a memory pattern surrounding a side wall of the channel pattern; andconductive patterns which are in contact with the pillars, respectively, and are formed within the insulating layer.15. The semiconductor device of claim 14 , wherein heights from a top surface of an uppermost conductive layer among the conductive layers to the lowermost surfaces of the conductive patterns have a substantially uniform value.16. The semiconductor device of claim 14 , wherein the insulating pattern claim 14 , the channel pattern claim 14 , and the memory pattern included in one pillar have substantially the same height.17. The semiconductor device of claim 14 , wherein the conductive pattern and the pillar in contact with each other claim 14 , have substantially the same width.18. The semiconductor device of claim 14 , wherein the conductive pattern and the channel pattern in contact with each other claim 14 , have substantially the same width.19. The semiconductor device of claim 14 , wherein the pillars have substantially the same height. ...

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Provided is a semiconductor device including a lower layer structure on a substrate, the lower layer structure having different thicknesses on first and second regions of the substrate, the lower layer structure including an electrode layer at a top and an insulating layer thereunder, an etch stop layer on the lower layer structure, an upper layer structure on the etch stop layer, the etch stop layer having an etch selectivity to the upper and lower layer structures, first and second contact plugs filling first and second openings defined in the upper layer structure and the etch stop layer on the first and second regions, respectively, and contacting corresponding electrode layers of the lower layer structure, respectively, such that one of the first and second contact plugs downwardly extends further with respect to a bottom of the etch stop layer than the other one of the first and second contact plugs. 1. A semiconductor device comprising:a substrate including a first region and a second region;a lower layer structure on the substrate, the lower layer structure having a first thickness on the first region and a second thickness on the second region, the second thickness being greater than the first thickness, the lower layer structure including an electrode layer at a top and an insulating layer under the electrode layer;an etch stop layer on the lower layer structure;an upper layer structure on the etch stop layer, a top surface of the upper layer structure being substantially a same level on the first and second regions, the etch stop layer having an etch selectivity with respect to both the upper layer structure and the lower layer structure; anda first contact plug filling a first opening, the upper layer structure and the etch stop layer including the first opening defined therethrough on the first region, the first contact plug being in connection with the electrode layer of the lower layer structure; anda second contact plug filling a second opening, the ...

APPARATUSES AND METHODS FOR FORMING MULTIPLE DECKS OF MEMORY CELLS

Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described. 1. An apparatus comprising:a first deck including alternating levels of first conductor materials and levels of first dielectric materials;first memory cells located in the first deck, each of the first memory cells located in a respective level of the levels of first conductor materials;a second deck including alternating levels of second conductor materials and levels of second dielectric materials;second memory cells located in the second deck, each of the second memory cells located in a respective level of the levels of second conductor materials;a level of third conductor material located between the first and second decks;a level of fourth conductor material located between the first and second decks; anda level of a dielectric material located between the level of third conductor material and the level of fourth conductor material.2. The apparatus of claim 1 , wherein the first conductor materials have a first conductivity type and each of the third and fourth conductor materials has a second conductivity type.3. The apparatus of claim 1 , wherein the first conductor materials have a conductivity of n-type and each of the third and fourth conductor materials has a conductivity of p-type.4. The apparatus of claim 1 , wherein each of the third and fourth conductor materials includes conductively doped semiconductor material.5. The apparatus of claim 4 , wherein the conductively doped semiconductor has a p-type conductivity.6. The ...

NAND Memory Arrays, Devices Comprising Semiconductor Channel Material and Nitrogen, and Methods of Forming NAND Memory Arrays

Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays. 1. (canceled)2: The device of wherein the semiconductor channel material further comprises one or more of germanium claim 3 , GaAs claim 3 , InP claim 3 , GaP and GaN.3: A device claim 3 , comprising:a gate spaced from a semiconductor channel material by a dielectric region;a nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region; and wherein:the semiconductor channel material comprises conductively doped polycrystalline silicon,the nitrogen-containing material comprises silicon nitride;the semiconductor channel material joining to the silicon nitride along an interface;a volume of the semiconductor channel material comprising nitrogen to a concentration within a range of from about 0.1 atomic percent to about 5 atomic percent; said volume of the semiconductor channel material being within a distance of no greater than about 10 Å from said interface; andsaid volume of the semiconductor channel material comprising fluorine.4: ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and an opening. The pad structure may include a first stepped structure and a second stepped structure located between the first cell structure and the second cell structure. The first stepped structure may include first pads electrically connected to the first and second cell structures and stacked on top of each other, and the second stepped structure may include second pads electrically connected to the first and second cell structures and stacked on top of each other. The circuit may be located under the pad structure. The opening may pass through the pad structure to expose the circuit, and may be located between the first stepped structure and the second stepped structure to insulate the first pads and the second pads from each other. 1. A semiconductor device , comprising:a first cell structure including first channel layers;a second cell structure including second channel layers;a pad structure located between the first cell structure and the second cell structure and including a first stepped structure and a second stepped structure, the first stepped structure including first pads electrically connected to the first and second cell structures and stacked on top of each other;a circuit vertically arranged with the first cell structure, the second cell structure and the pad structure;an interconnection electrically connecting the first pads to the circuit.2. The semiconductor device of claim 1 , further comprising an opening passing through the pad structure to expose the circuit.3. The semiconductor device of claim 2 , wherein the interconnection is electrically connected to the circuit through the opening.4. The semiconductor device of claim 1 , wherein the pad structure includes a dummy structure including wiring lines stacked on top of each other claim 1 , the wiring lines electrically connecting the first cell structure and the second cell ...

Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells And Operative Through-Array-Vias

A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region. At least a majority of channel material of the dummy channel-material strings is replaced in the TAV region with insulator material and operative TAVs are formed in the TAV region. Other methods and structures independent of method are disclosed. 1. A method used in forming a memory array comprising strings of memory cells and operative through array-vias (TAVs) , the method comprising:forming a stack comprising vertically-alternating insulative tiers and conductive tiers, the stack comprising a TAV region and an operative memory cell string region;forming operative channel-material strings in the stack in the operative memory cell string region and dummy channel-material strings in the stack in the TAV region;replacing at least a majority of channel material of the dummy channel material strings in the TAV region with insulator material; andforming operative TAVs in the TAV region.2. The method of wherein the replacing removes all of the channel material of the channel material strings.3. The method of wherein the operative channel-material strings are within laterally-spaced memory blocks that comprise part of a memory plane; and 'forming multiple of said TAV regions that are laterally spaced relative one another, at least one of said TAV regions being within the memory plane, at least another one of said TAV regions being outside of the memory plane.', 'further comprising4. The method of wherein the replacing comprises:masking the operative channel-material strings in the operative memory cell string ...

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include forming a first sacrificial layer including a first portion and a second portion having a thickness thicker than a thickness of the first portion, forming a stack including first material layers and second material layers alternating with each other on the first sacrificial layer, forming a channel structure passing through the stack and extending to the first portion, forming a slit passing through the stack and extending to the second portion, removing the first sacrificial layer through the slit to form a first opening, and forming a second source layer connected to the channel structure in the first opening. 1. A method of manufacturing a semiconductor device , the method comprising:forming a first sacrificial layer comprising a first portion and a second portion having a thickness thicker than a thickness of the first portion;forming a stack comprising first material layers and second material layers alternating with each other on the first sacrificial layer;forming a channel structure passing through the stack and extending to the first portion;forming a slit passing through the stack and extending to the second portion;removing the first sacrificial layer through the slit to form a first opening; andforming a second source layer connected to the channel structure in the first opening.2. The method of claim 1 , further comprising:forming a first source layer comprising a second opening before forming the first sacrificial layer.3. The method of claim 2 , wherein the first sacrificial layer is formed on the first source layer claim 2 , and the second portion is formed in the second opening.4. The method of claim 2 , further comprising:forming a second sacrificial layer on the first source layer before forming the first sacrificial layer.5. The method of claim 4 , wherein the first sacrificial layer comprises polysilicon claim 4 , and the second ...

ELECTRONIC DEVICES AND SYSTEMS WITH CHANNEL OPENINGS OR PILLARS EXTENDING THROUGH A TIER STACK, AND METHODS OF FORMATION

Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack. 1. A method of forming a semiconductor device , the method comprising:forming a stack of vertically-alternating tiers of insulative material and other material over a base material, a sacrificial material disposed in the base material, and a soft plug material disposed in the sacrificial material;forming an opening extending through the stack and through the soft plug material, leaving remnants of the soft plug material along sidewalls of the opening;forming a liner in the opening;exposing, through the liner, a portion of the sacrificial material;without removing the liner, removing the sacrificial material and the remnants of the soft plug material to define a gap between the liner and a sidewall of the base material, the gap exposing a portion of a lower tier of the stack;etching into the portion of the lower tier of the stack to define an undercut portion in the lower tier of the stack; andremoving the liner to form a channel opening extending through the stack and into the base material, the channel opening exposing a source region of the base material at a base of the channel opening, the channel opening defined by sidewalls comprising the undercut portion.2. The method of claim 1 , wherein forming a liner in the opening comprises conformally forming polysilicon in the opening.3. The method of claim 1 , wherein etching into the portion of the lower tier of the stack to define an undercut portion in the lower tier of the stack comprises isotropically etching into the portion of the lower tier of the stack.4. The method of claim 1 , ...

3D SEMICONDUCTOR DEVICE AND STRUCTURE

A 3D memory device, the device including: a first vertical pillar; a second vertical pillar, where the first vertical pillar and the second vertical pillar function as a source or a drain for a plurality of overlaying horizontally-oriented memory transistors, where the plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following the same lithography step; and memory control circuits, where the memory control circuits are disposed at least partially directly underneath the plurality of overlaying horizontally-oriented memory transistors, or are disposed at least partially directly above the plurality of overlaying horizontally-oriented memory transistors. 121-. (canceled)22. A 3D memory device , the device comprising:a first vertical pillar; wherein said first vertical pillar and said second vertical pillar function as a source or a drain for a plurality of overlaying horizontally-oriented memory transistors,', 'wherein said plurality of overlaying horizontally-oriented memory transistors are self-aligned being formed following the same lithography step; and, 'a second vertical pillar,'} 'wherein said memory control circuits are disposed at least partially directly underneath said plurality of overlaying horizontally-oriented memory transistors, or are disposed at least partially directly above said plurality of overlaying horizontally-oriented memory transistors.', 'memory control circuits,'}23. The 3D memory device according to claim 22 ,wherein said plurality of overlaying horizontally-oriented memory transistors each comprise a tunneling oxide region and a charge trap region, andwherein said tunneling oxide region is thinner than 1 nm or does not exist.24. The 3D memory device according to claim 22 , further comprising: 'wherein said third vertical pillar and said second vertical pillar function as a source or a drain for a second plurality of overlaying horizontally-oriented memory transistors.', 'a third vertical ...

Integrated Assemblies Having Anchoring Structures Proximate Stacked Memory Cells, and Methods of Forming Integrated Assemblies

Some embodiments include an assembly having channel material structures extending upwardly from a conductive structure. Anchor structures are laterally offset from the channel material structures and penetrate into the conductive structure to a depth sufficient to provide mechanical stability to at least a portion of the assembly. The conductive structure may include a first conductive material over a second conductive material, and may be a source line of a three-dimensional NAND configuration. Some embodiments include methods of forming assemblies to have channel material structures and anchor structures.

Integrated Assemblies Having Thicker Semiconductor Material Along One Region of a Conductive Structure than Along Another Region, and Methods of Forming Integrated Assemblies

Some embodiments include an integrated assembly having a conductive structure which includes a semiconductor material over a metal-containing material. A stack of alternating conductive levels and insulative levels is over the conductive structure. A partition extends through the stack. The partition has wall regions, and has corner regions where two or more wall regions meet. The conductive structure includes a first portion which extends directly under the corner regions, and includes a second portion which is directly under the wall regions and is not directly under the corner regions. The first portion has a first thickness of the semiconductor material and the second portion has a second thickness of the semiconductor material. The first thickness is greater than the second thickness. Some embodiments include methods of forming integrated assemblies. 17-. (canceled)8. An integrated assembly , comprising:a conductive structure comprising a semiconductor material over a metal-containing material;an assembly over the conductive structure and comprising a stack of wordline levels;a partition extending through the stack; the partition comprising wall regions, and comprising corner regions where two or more wall regions meet; the partition dividing the assembly into sub-blocks; andthe conductive structure comprising a first portion which extends to directly under the corner regions, and comprising a second portion which is directly under the wall regions and is not directly under the corner regions; the first portion comprising a thicker region of the semiconductor material than the second portion.9. The integrated assembly of wherein the partition directly contacts a top of the conductive structure.10. The integrated assembly of wherein the conductive structure has an overall thickness; wherein the semiconductor material of the first portion comprises greater than about half of said overall thickness; and wherein the semiconductor material of the second portion ...

Method for in situ Preparation of Antimony-doped Silicon and Silicon Germanium films

A process for forming an antimony-doped silicon-containing layer includes: (a) depositing by chemical vapor deposition the antimony-doped silicon-containing layer above a semiconductor structure, using an antimony source gas and a silicon source gas or a combination of the silicon source gas and a germanium source gas; and (b) annealing the antimony-doped silicon-containing layer at a temperature of no greater than 800° C. The antimony source gas may include one or more of: trimethylantimony (TMSb) and triethylantimony (TESb). The silicon source gas comprises one or more of: silane, disilane, trichlorosilane, (TCS), dichlorosilane (DCS), monochlorosilane (MCS), methylsilane, and silicon tetrachloride. The germanium source gas comprises germane 1. A process , comprising:exposing a surface of a semiconductor structure; andflowing over the surface of the semiconductor structure an antimony source gas and a silicon source gas or a combination of the silicon source gas and a germanium source gas, so as to deposit by chemical vapor deposition an antimony-doped silicon-containing layer at a temperature no greater than 900° C.2. The process of claim 1 , wherein the antimony source gas comprises one or more of: trimethylantimony (TMSb) and triethylantimony (TESb).3. The process of claim 1 , wherein the silicon source gas comprises one or more of: silane claim 1 , disilane claim 1 , trichlorosilane claim 1 , (TCS) claim 1 , dichlorosilane (DCS) claim 1 , monochlorosilane (MCS) claim 1 , methylsilane claim 1 , and silicon tetrachloride.4. The process of claim 1 , wherein the germanium source gas comprises germane.5. The process of claim 1 , wherein the antimony-doped silicon-containing layer is deposited into a cavity formed by removal of a sacrificial layer.1. process of claim 1 , further comprising:forming an n-type semiconductor layer above the semiconductor structure; andannealing the n-type semiconductor layer at a temperature higher than 800° C., prior to annealing the ...

Memory Circuitry Comprising A Vertical String Of Memory Cells And A Conductive Via And Method Used In Forming A Vertical String Of Memory Cells And A Conductive Via

A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. An upper material is formed above the lower material and above the first material in the first and second lower openings. A first upper opening is formed through the upper material to the first material in the first lower opening. At least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. After forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. Conductive material of the conductive via is formed within the second upper opening. Structure embodiments independent of method of formation are disclosed. 123-. (canceled)24. Memory circuitry comprising a vertical string of memory cells and a conductive via , comprising:a first region of vertically-alternating tiers of insulative material and control gate material, a second region of vertically-alternating tiers of different composition insulating materials laterally of the first region;a channel pillar extending elevationally through multiple of the vertically-alternating tiers within the first region;tunnel insulator, charge storage material, and control gate blocking insulator between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region; anda conductive via extending elevationally through the vertically-alternating tiers in the second region, the conductive via comprising vertically-stacked conductive containers within the alternating tiers of the different composition insulating materials in the second region, the conductive containers ...

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device is provided, comprising: a memory cell region including a memory cell array; and a peripheral circuit region which at least partially overlaps the memory cell region and includes control logic configured to control operation of the memory cell array, wherein the control logic includes a state machine configured to output a plurality of state signals responsive to operation commands of the memory cell region, the plurality of state signals including a first state signal output from a first output terminal, and a second state signal output from a second output terminal different from the first output terminal, a logical sum calculator configured to perform a logical sum calculation based on at least one of the first state signal or the second state signal, and an accumulation circuit configured to receive an output of the logical sum calculator as a clock signal, and that outputs a toggle signal to one probing pad in response to the clock signal, the accumulation circuit being connected to the probing pad through a Through Hole Via (THV) penetrating the memory cell region. 1. A semiconductor memory device comprising:a memory cell region including a memory cell array; anda peripheral circuit region which at least partially overlaps the memory cell region and includes control logic configured to control operation of the memory cell array,wherein the control logic includesa state machine configured to output a plurality of state signals responsive to operation commands of the memory cell region, the plurality of state signals including a first state signal output from a first output terminal, and a second state signal output from a second output terminal different from the first output terminal,a logical sum calculator configured to perform a logical sum calculation based on at least one of the first state signal or the second state signal, andan accumulation circuit configured to receive an output of the logical sum calculator as a clock ...

PATTERN FORMING METHOD AND BAKE CONDITION DETERMINING METHOD

In a pattern forming method according to an embodiment, a work film to be processed is formed on a substrate, and a resist pattern is formed on the top of the work film. Then, the resist pattern is baked in the bake condition set at positions of the substrate. This forms first inclined surfaces those are not parallel to the top and side surfaces of the work film on the resist pattern. The first inclined surfaces are formed into shapes in accordance with the bake condition at positions of the substrate. Furthermore, the work film is etched using the resist pattern as a mask so as to form a second inclined surface on the work film. 1. A pattern forming method comprising:forming a work film to be processed on a substrate;forming a resist pattern on a top of the work film;baking the resist pattern in a bake condition set at positions on the substrate;forming a first inclined surfaces on the resist pattern at the positions on the substrate, the first inclined surfaces being not parallel to top and side surfaces of the work film, the first inclined surfaces having shapes in accordance with the bake condition;etching the work film using the resist pattern as a mask; andforming second inclined surfaces on the work film.2. The pattern forming method according to claim 1 , wherein the bake condition is set at the positions on the substrate in accordance with an etching rate ratio between the resist pattern and the work film.3. The pattern forming method according to claim 2 , wherein claim 2 , when the bake condition is set claim 2 ,a first inclination angle of the first inclined surfaces is set in accordance with the etching rate ratio, and the bake condition is set in accordance with the first inclination angle.4. The pattern forming method according to claim 3 , wherein the first inclination angle is set in accordance with first correspondence relationship information indicating a correspondence relationship between the etching rate ratio and the first inclination angle.5. ...

SEMICONDUCTOR STRUCTURE

A semiconductor structure is provided. The semiconductor structure includes a conductive strip, a conductive layer, a first dielectric layer, and a second dielectric layer. The first dielectric layer is between the conductive strip and the conductive layer arranged in a crisscross manner. The second dielectric layer is different from the first dielectric layer. The second dielectric layer and the first dielectric layer are adjoined with the conductive strip in different positions on the same sidewall of the conductive strip. 1. A semiconductor structure , comprising:a conductive strip;a conductive layer;a first dielectric layer between the conductive strip and the conductive layer arranged in a crisscross manner; anda second dielectric layer different from the first dielectric layer, wherein the second dielectric layer and the first dielectric layer are adjoined with the conductive strip in different positions on the same sidewall of the conductive strip.2. The semiconductor structure according to claim 1 , comprising a plurality of the first dielectric layers separated from each other by the second dielectric layer.3. The semiconductor structure according to claim 1 , comprising a plurality of the conductive strips and a plurality of the conductive layers claim 1 , wherein the second dielectric layer is between adjacent two of the conductive strips and between adjacent two of the conductive layers.4. The semiconductor structure according to claim 1 , wherein the conductive strip has a first conductive portion and a second conductive portion adjoined with the first conductive portion claim 1 , the first dielectric layer is adjoined with the first conductive portion claim 1 , the second dielectric layer is adjoined with the second conductive portion claim 1 , a width of the first conductive portion is different from a width of the second conductive portion.5. The semiconductor structure according to claim 1 , wherein the first dielectric layer and the second ...

Semiconductor device

A semiconductor device includes a first vertical memory string connected to a common source line, a second vertical memory string connected to a bit line, a pipe transistor suitable for selectively connecting the first and second vertical memory strings based on a block selection signal, and a plurality of transistors suitable for selectively connecting local lines of the first and second vertical memory strings to corresponding global lines based on the block selection signal.

Multi-tiered semiconductor devices and associated methods

Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first dielectric is formed, and a second dielectric is formed in contact with the first dielectric. A channel is formed through the first dielectric and the second dielectric with a first etch chemistry, a void is formed in the first dielectric with a second etch chemistry, and a device is formed at least partially in the void in the first dielectric. Additional embodiments are also described.

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a first insulating layer. The plurality of control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The first insulating layer is positioned between the semiconductor layer and the control gate electrode. In addition, part of the first insulating layer is a charge accumulation layer. Moreover, part of the first insulating layer is an oxide layer positioned upwardly of the charge accumulation layer. 1. A semiconductor memory device , comprising:a plurality of control gate electrodes stacked above a substrate;a semiconductor layer having as its longitudinal direction a direction perpendicular to the substrate, the semiconductor layer facing the plurality of control gate electrodes; anda first insulating layer positioned between the semiconductor layer and the control gate electrode,part of the first insulating layer being a charge accumulation layer, andpart of the first insulating layer being an oxide layer positioned upwardly of the charge accumulation layer.2. The semiconductor memory device according to claim 1 , further comprising:a second insulating layer positioned between the semiconductor layer and the first insulating layer; anda third insulating layer provided between the first insulating layer and the control gate electrode.3. The semiconductor memory device according to claim 1 , whereinthe plurality of control gate electrodes include a first control gate electrode and a second control gate electrode positioned more upwardly than the first control gate electrode, anda boundary of the charge accumulation layer and the oxide layer is positioned more upwardly than the first control gate electrode and more downwardly than an upper surface of the second control gate electrode.4. ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction crossing the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A gap is provided between the semiconductor layer and a lower end portion of the charge accumulation layer. 1. A semiconductor memory device , comprising:a plurality of control gate electrodes provided as a stack above a substrate;a semiconductor layer having as its longitudinal direction a direction crossing the substrate, the semiconductor layer facing the plurality of control gate electrodes; anda charge accumulation layer positioned between the control gate electrode and the semiconductor layer,a gap being provided between the semiconductor layer and a lower end portion of the charge accumulation layer.2. The semiconductor memory device according to claim 1 , further comprising:a first insulating layer covering a sidewall of the semiconductor layer; anda second insulating layer covering a sidewall of the charge accumulation layer,wherein the lower end portion of the charge accumulation layer has a recess portion which is recessed with respect to lower end portions of the first insulating layer and the second insulating layer.3. The semiconductor memory device according to claim 1 , further comprisinga first insulating layer provided between the semiconductor layer and the charge accumulation layer,wherein a distance, via the gap, between the semiconductor layer and the lower end portion of the charge accumulation layer, when converted to an electrical resistance value, is not less than a distance equivalent to a film thickness of the first insulating layer.4. The ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes. 1. A semiconductor memory device , comprising:a plurality of control gate electrodes provided as a stack above a substrate;a semiconductor layer having as its longitudinal direction a direction perpendicular to the substrate, the semiconductor layer facing the plurality of control gate electrodes; anda charge accumulation layer positioned between the control gate electrode and the semiconductor layer,a lower end of the charge accumulation layer being positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.2. The semiconductor memory device according to claim 1 , whereinthe plurality of control gate electrodes include: a first control gate electrode; and a plurality of second control gate electrodes positioned more upwardly than the first control gate electrode, andthe lower end of the charge accumulation layer is positioned between the first control gate electrode and the plurality of second control gate electrodes.3. The semiconductor memory device according to claim 2 , further comprising:a memory string including a plurality of memory cells connected in series; anda select gate transistor connected to one end of the memory string,wherein the first control gate electrode functions as a control gate electrode of the select gate transistor, andthe second ...

Capacitor With 3D NAND Memory

An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other. 2. The computer readable medium of claim 1 , wherein the stack of conductive strips is at least one of: transistor channels in the 3D NAND memory array claim 1 , conductors routing signals that select memory cells in the 3D NAND memory array claim 1 , and conductors routing output from the 3D NAND memory array.3. The computer readable medium of claim 1 , wherein the 3D NAND memory array is a vertical gate memory array claim 1 , and the conductive strips in the stack are NAND transistor channels in the vertical gate memory array.4. The computer readable medium of claim 1 , wherein the 3D NAND memory array is a vertical channel memory array claim 1 , and the conductive strips in the stack of conductive strips are word lines in the vertical channel memory array.5. The computer readable medium of claim 1 , wherein the stack of capacitor terminal strips includes a first plurality of capacitor terminal strips alternating with a second plurality of capacitor terminal strips claim 1 , the first plurality of capacitor terminal strips electrically connected together and the second plurality of capacitor terminal ...

ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF

Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. 1. A method of making a monolithic three dimensional NAND string , comprising:forming a stack of alternating layers of a first material and a second material different from the first material over a substrate;etching the stack to form at least one opening in the stack;forming a charge storage material layer on a sidewall of the at least one opening;forming a tunnel dielectric layer on the charge storage material layer in the at least one opening;forming a semiconductor channel material on the tunnel dielectric layer in the at least one opening;selectively removing the first material layers to expose side wall of the charge storage material layer;forming a blocking dielectric on the exposed side wall of the charge storage material layer; andforming control gates on the blocking dielectric.2. The method of claim 1 , further comprising:forming an etch stop layer on the sidewall of the at least one opening prior to the step of forming the charge storage material layer; andetching the etch stop layer expose portions of a side of the charge storage material layer.3. The method of claim 1 , wherein the charge storage material layer comprises a charge storage dielectric material.4. The method of claim 1 , wherein:the second material comprises an insulating material; andthe first material comprises a sacrificial material.5. The method of claim 1 , wherein:the second material comprises ...

CARBON LAYER COVERED MASK IN 3D APPLICATIONS

Embodiments of the present disclosure generally relate to a method for forming an opening using a mask. In one embodiment, a method includes forming a mask on a feature layer. The method includes forming a first opening in the mask to expose a portion of the feature layer. The method further includes forming a carbon layer on the mask and the exposed portion of the feature layer. The method also includes removing portions of the carbon layer and a portion of the exposed portion of the feature layer in order to form a second opening in the feature layer. 1. A method , comprising:forming a mask on a feature layer;forming a first opening in the mask to expose a portion of the feature layer;forming a carbon layer on the mask and the exposed portion of the feature layer; andremoving portions of the carbon layer and a portion of the exposed portion of the feature layer to form a second opening in the feature layer.2. The method of claim 1 , wherein the mask comprises doped carbon.3. The method of claim 2 , wherein the feature layer comprises silicon claim 2 , germanium claim 2 , silicon germanium claim 2 , silicon oxide claim 2 , aluminum oxide claim 2 , silicon oxide nitride claim 2 , or silicon nitride.4. The method of claim 2 , wherein the feature layer comprises a metal.5. The method of claim 2 , wherein the carbon layer comprises a graphene layer.6. The method of claim 2 , wherein the carbon layer comprises a plurality of graphene layers.7. The method of claim 6 , wherein the plurality of graphene layers is formed by a microwave-assisted chemical vapor deposition process.8. A method claim 6 , comprising:forming a mask on alternating layers;forming a first plurality of openings in the mask to expose portions of the alternating layers;forming a carbon layer on the mask and the exposed portions of the alternating layers; andremoving portions of the carbon layer and portions of the exposed portions of the alternating layers to form a second plurality of openings in the ...

METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES WITH SUPPORTING STRUCTURE FOR STAIRCASE REGION

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral circuit is formed on a first substrate. A first semiconductor layer is formed on a second substrate. A supporting structure and a second semiconductor layer coplanar with the supporting structure are formed on the first semiconductor layer. A memory stack is formed above the supporting structure and the second semiconductor layer. The memory stack has a staircase region overlapping the supporting structure. A channel structure extending vertically through the memory stack and the second semiconductor layer into the first semiconductor layer is formed. The first substrate and the second substrate are bonded in a face-to-face manner. 1. A method for forming a three-dimensional (3D) memory device , comprising:sequentially forming a first semiconductor layer, a first block layer, and a sacrificial layer on a substrate;forming a block plug extending vertically through the sacrificial layer and the first block layer to divide the sacrificial layer into a supporting portion and a sacrificial portion;forming a dielectric stack above the sacrificial layer and having a staircase region, such that the supporting portion of the sacrificial layer is below and overlaps the staircase region of the dielectric stack;forming a channel structure extending vertically through the dielectric stack, the sacrificial portion of the sacrificial layer, and the first block layer, into the first semiconductor layer;forming an opening extending vertically through the dielectric stack to expose part of the sacrificial portion of the sacrificial layer; andreplacing, through the opening, the sacrificial portion of the sacrificial layer with a second semiconductor layer coplanar with the supporting portion of the sacrificial layer.2. The method of claim 1 , wherein replacing the sacrificial portion of the sacrificial layer with the second ...

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE

A semiconductor device includes: a substrate extending in a first direction and a second direction intersecting with the first direction; a plurality of input/output pads disposed at one side of the substrate; a first circuit adjacent to the input/output pads in the first direction; a second circuit disposed to be spaced farther apart from the input/output pads in the first direction than the first circuit; a first memory cell array overlapping the first circuit; a second memory cell array overlapping the second circuit; first metal source patters overlapping the first memory cell array and being spaced apart from each other in the second direction; and a second metal source pattern overlapping the second memory cell array and formed to have a width wider than a width of each of the first metal source patterns in the second direction. 1. A semiconductor memory device comprising:a substrate extending in a first direction and a second direction intersecting with the first direction;a plurality of input/output pads disposed at one side of the substrate;a first circuit adjacent to the input/output pads in the first direction;a second circuit disposed to be spaced farther apart from the input/output pads in the first direction than the first circuit;a first memory cell array overlapping the first circuit;a second memory cell array overlapping the second circuit;first metal source patters overlapping the first memory cell array, wherein the first metal source patterns are spaced apart from each other in the second direction; anda second metal source pattern overlapping the second memory cell array, wherein the second metal source pattern has a width wider than a width of each of the first metal source patterns in the second direction.2. The semiconductor memory device of claim 1 , further comprising a transmission line overlapping the first memory cell array between the first metal source patterns claim 1 ,wherein the transmission line is configured to transmit an ...