НИТРИДНОЕ ПОЛУПРОВОДНИКОВОЕ УСТРОЙСТВО И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

... 1. Нитридное полупроводниковое устройство, включающее подложку из стабилизированного оксидом иттрия оксида циркония, ниже обозначаемого YSZ, и нитридный полупроводниковый слой, включающий кристалл InN гексагональной системы, причем указанный кристалл InN ориентирован своей с-осью приблизительно вертикально по отношению к плоскости (111) подложки YSZ. 2. Нитридное полупроводниковое устройство по п.1, у которого на плоскости (111) подложки YSZ образована атомная ступенька. 3. Нитридное полупроводниковое устройство, включающее подложку из ZnO, и нитридный полупроводниковый слой, включающий кристалл GaN гексагональной системы, причем указанный кристалл GaN ориентирован своей с-осью приблизительно вертикально по отношению к плоскости (000-1) или плоскости (0001) указанной ZnO подложки. 4. Нитридное полупроводниковое устройство по п.3, в котором на плоскости (000-1) или на плоскости (0001) указанной ZnO подложки образована атомная ступенька. 5. Нитридное полупроводниковое устройство, включающее ...

ПЕРЕКЛЮЧАЮЩИЙ ЭЛЕМЕНТ И СПОСОБ ИЗГОТОВЛЕНИЯ ПЕРЕКЛЮЧАЮЩЕГО ЭЛЕМЕНТА

Переключающий элемент включает в себя полупроводниковую подложку, которая включает в себя первый слой полупроводника n-типа, базовый слой р-типа, образованный эпитаксиальным слоем, и второй слой полупроводника n-типа, отделенный от первого слоя полупроводника n-типа базовым слоем, изолирующую пленку затвора, которая покрывает зону, перекрывающую поверхность первого слоя полупроводника n-типа, поверхность базового слоя и поверхность второго слоя полупроводника n-типа, а также электрод затвора, который расположен напротив базового слоя в пределах изолирующей пленки затвора. Граница раздела между первым слоем полупроводника n-типа и базовым слоем включает в себя наклонную поверхность. Наклонная поверхность наклонена таким образом, что глубина базового слоя увеличивается при увеличении расстояния в горизонтальном направлении от края базового слоя. Наклонная поверхность расположена под электродом затвора. Изобретение обеспечивает более эффективное ослабление электрического поля, воздействующего ...

СПОСОБ СНИЖЕНИЯ ВНУТРЕННИХ МЕХАНИЧЕСКИХ РАПРЯЖЕНИЙ В ПОЛУПРОВОДНИКОВОЙ СТРУКТУРЕ И ПОЛУПРОВОДНИКОВАЯ СТРУКТУРА С НИЗКИМИ МЕХАНИЧЕСКИМИ НАПРЯЖЕНИЯМИ

... 1. Способ снижения внутренних механических напряжений в полупроводниковой структуре, образованной нитридами металлов группы III на (0001) ориентированной инородной подложке (1), отличающийся тем, что указанный способ включает стадии:- выращивания нитрида на инородной подложке (1) с образованием первого нитридного слоя (2);- формирования рельефа на первом нитридном слое (2) путем селективного удаления объемов из него до заданной глубины от верхней поверхности (5) первого нитридного слоя (2), для обеспечения релаксации внутренних механических напряжений в оставшихся частях слоя между удаленными объемами, и- выращивания на первом нитридном слое (2) дополнительного нитрида, начиная с оставшихся частей верхней поверхности (5) первого нитридного слоя (2) до формирования непрерывного второго нитридного слоя (8), с получением замкнутых пустот (7) из удаленных объемов под вторым нитридным слоем (8) внутри полупроводниковой структуры; при этом указанное выращивание включает выращивание дополнительного ...

Halbleitervorrichtung aus einer galliumnitridartigen III-V-Halbleiterverbindung und Verfahren zu ihrer Herstellung

Halbleiteranordnung auf Basis von Gallium-Nitrid und Verfahren zur Herstellung

GALLIUMNITRIDVORRICHTUNG FÜR HOCHFREQUENZ- UND HOCHLEISTUNGSANWENDUNGEN

Eine Halbleitervorrichtung weist eine Schicht eines ersten halbleitenden Materials auf, wobei das erste halbleitende Material epitaktisch gewachsen ist, um eine Kristallstruktur eines ersten Substrats zu haben. Die Halbleitervorrichtung weist ferner eine Schicht eines zweiten halbleitenden Materials auf, das der Schicht des ersten halbleitenden Materials benachbart angeordnet ist, um einen Heteroübergang mit der Schicht des ersten halbleitenden Materials zu bilden. Die Halbleitervorrichtung weist ferner ein erstes Bauelement, das elektrisch mit dem Heteroübergang verbunden ist, und ein zweites Substrat, das an die Schicht des ersten halbleitenden Materials gebunden ist, auf.

Halbleiterbauelement und ein Verfahren zu dessen Herstellung

Die Erfindung betrifft ein Halbleiterbauelement basierend auf Elementen der Gruppe-III-Nitride auf einem Hetero- oder Homosubstrat oder einer Gruppe-III-Nitrid-Pufferschicht, gekennzeichnet durch eine mindestens einmal wechselnde Polarität der Gruppe-III-Nitrid-Schicht im Bauelement oder von benachbarten Bauelementen durch eine lokale Beschichtung des Substrats oder der Gruppe-III-Nitrid-Pufferschicht mit einem bei Herstellungstemperatur nicht schmelzenden Metall.

Transistoranordnung mit hoher Elektronenbeweglichkeit und Verfahren

Ausführungsformen der vorliegenden Offenbarung beschreiben strukturelle Gestaltungen als einer integrierten Schaltkreis-Vorrichtung (IC-Vorrichtung) wie etwa einer Transistorschalteinrichtung mit einer hohen Elektronenbeweglichkeit (HEMT) und Herstellungsverfahren. Die IC-Vorrichtung weist eine auf einem Substrat gebildete Pufferschicht, eine auf der Pufferschicht gebildete Kanalschicht, um einen Weg für Stromfluss in einer Transistorvorrichtung bereitzustellen, eine auf der Kanalschicht gebildete Abstandsschicht, eine auf der Abstandsschicht gebildete Sperrschicht, wobei die Sperrschicht Aluminium (Al), Stickstoff (N) und des weiteren Indium (In) und/oder Gallium (Ga) aufweist, ein mit der Abstandsschicht oder der Kanalschicht direkt gekoppeltes Gate-Dielektrikum und ein auf dem Gate-Dielektrikum gebildetes Gate auf, wobei das Gate mit dem Gate-Dielektrikum direkt gekoppelt ist. Andere Ausführungsformen können auch beschrieben und/oder beansprucht werden.

High temperature change-fixed insertion diode e.g. trench junction barrier schottky diode, for use in motor vehicle-generator system, has isolating plastic layer overlapping radial inner-lying end area of another isolating plastic layer

The diode (1) has a semiconductor chip (3) fixed between a socket and a head wire (6) by an interconnection layer i.e. solder layer (5), and made from semiconductor material e.g. silicon carbide or gallium nitride. The layer is arranged on a chip front side relative to a chip outer edge, and a circulating, isolating plastic layer (10) is arranged above an interconnection layer-free area of the chip. Another completely circulating, isolating plastic layer (11) overlaps a radial inner-lying end area of the former plastic layer, where the latter plastic layer is made from polyimide.

Schaltvorrichtung

Eine Schaltvorrichtung umfasst eine Elektronentransportschicht; eine Elektronenzufuhrschicht, die auf der Elektronentransportschicht bereitgestellt ist und in Kontakt mit der Elektronentransportschicht durch einen Heteroübergang ist; eine Sourceelektrode, die in Kontakt mit der Elektronenzufuhrschicht ist; eine Drainelektrode, die in Kontakt mit der Elektronenzufuhrschicht bei einer Position ist, die von der Sourceelektrode beabstandet ist; und eine erste Gateelektrode, die über der Elektronenzufuhrschicht bereitgestellt ist und zwischen der Sourceelektrode und der Drainelektrode bereitgestellt ist, wenn sie in einer Draufsicht von oben betrachtet werden. Die erste Gateelektrode ist elektrisch über der Elektronenzufuhrschicht mit der Drainelektrode verbunden. Ein Einschaltwiderstand bzw. Durchlasswiderstand der Schaltvorrichtung ist niedriger als ein elektrischer Widerstand zwischen der ersten Gateelektrode und der Drainelektrode.

Halbleiterbauteil und Verfahren zu dessen Herstellung

Eine elektrische Feld-Pufferschicht (13) wird eine aktive Zone (12) umgebend ausgebildet. Die elektrische Feld-Pufferschicht (13) umfasst mehrere Fremdstoffschichten des P-Typs (21 bis 25). Jede der Fremdstoffschichten des P-Typs (21 bis 25) umfasst Implantationsschichten des P-Typs (21a bis 25a) und Diffusionsschichten des P-Typs (21b bis 25b), die so ausgebildet werden, dass sie jeweils die Implantationsschichten des P-Typs (21a bis 25a) umgeben und Fremdstoffe des P-Typs in einer Konzentration enthalten, die geringer ist als diejenige der Implantationsschichten des P-Typs (21a bis 25a). Eine erste Implantationsschicht des P-Typs (21a) wird in Kontakt mit der oder die aktive Zone (12) teilweise überlagernd ausgebildet. Jede der Diffusionsschichten des P-Typs (21b bis 25b) wird mit einer Ausdehnung in einem Ausmaß ausgebildet, in dem die erste Diffusionsschicht des P-Typs (21b) mit der zweiten Diffusionsschicht des P-Typs (22b) in Kontakt steht oder diese überlagert. Abstände (s2 bis s5 ...

Leistungshalbleitermodul

Ein Leistungshalbleitermodul wird bereitgestellt, das eine Induktivität zwischen Verdrahtungsleitungen im Leistungshalbleitermodul reduziert, um eine Unterbindung eines Bruchs des Leistungshalbleiterelements durch eine Stoßspannung zu ermöglichen. Das Leistungshalbleitermodul: einen positiven Zweig und einen negativen Zweig, die durch eine Reihenschaltung von Halbleiterelementen (6) des lichtbogenselbstlöschenden Typs gebildet sind, und die an einer Reihenanschlussstelle zwischen den Halbleiterelementen (6) des lichtbogenselbstlöschenden Typs angeschlossen sind; eine positivseitige Gleichstromelektrode (10), eine negativseitige Gleichstromelektrode (11) und eine Wechselstromelektrode (12), die an den positiven Zweig und den negativen Zweig angeschlossen sind; und ein Substrat (2), auf dem ein Verdrahtungsmuster (3, 4) ausgebildet ist, wobei das Verdrahtungsmuster (3, 4) die Halbleiterelemente (6) des lichtbogenselbstlöschenden Typs des positiven Zweigs und des negativen Zweigs an die positivseitige ...

Nitridhalbleitervorrichtung und deren Herstellungsverfahren

Nitridhalbleitervorrichtung, die einen IIIV Nitridhalbleiter umfasst, der aus zumindest einem Element der Gruppe III aus einer Gallium, Aluminium, Bor und Indium enthaltenden Gruppe und zumindest Stickstoff als Element der Gruppe V aus einer Stickstoff, Phosphor und Arsen enthaltenden Gruppe zusammengesetzt ist, die Nitridhalbleitervorrichtung umfasst dabei: eine erste Nitridhalbleiterschicht, die den auf einem Substrat abgeschiedenen IIIV Nitridhalbleiter aufweist, wobei die erste Nitridhalbleiterschicht als Ladungszufuhrschicht eingerichtet ist; eine zweite Nitridhalbleiterschicht, die den IIIV Nitridhalbleiter aufweist, der auf der ersten Nitridhalbleiterschicht abgeschieden ist und kein Aluminium enthält; und eine Steuerelektrode, die einen Schottky-Kontakt mit der zweiten Nitridhalbleiterschicht ausbildet, wobei die erste Nitridhalbleiterschicht eine Epitaxieschicht ist, und die zweite Nitridhalbleiterschicht eine Schicht mit einer Kristallinität mit winzigen Körnern ist, die durch ...

Transistor mit hoher Elektronenmobilität mit Ladungsträgerinjektionsabschwächungs-Gate-Struktur

Ein Verfahren umfasst das Bereitstellen eines Heterostrukturkörpers mit einem Pufferbereich und einem Barrierebereich, der auf dem Pufferbereich angeordnet ist, und das Herstellen einer Gate-Struktur zum Steuern des Kanals auf dem Heterostrukturkörper, wobei die Gate-Struktur einen dotierten Halbleiterbereich, der auf dem Heterostrukturkörper angeordnet ist, eine Zwischenschicht, die auf dem dotierten Halbleiterbereich angeordnet ist, und eine Gate-Elektrode, die auf der Zwischenschicht angeordnet ist, aufweist. Das Herstellen der Gate-Struktur umfasst das Steuern einer Dotierungskonzentration des dotierten Halbleiterbereichs, so dass ein Abschnitt des Kanals benachbart zur Gate-Struktur bei einer Gate-Vorspannung von null nicht leitfähig ist, und das Steuern von elektrischen und geometrischen Eigenschaften der Zwischenschicht auf der Basis einer Beziehung zwischen den elektrischen und geometrischen Eigenschaften der Zwischenschicht und entsprechenden Effekten auf eine statische Schwellenspannung ...

III-Nitrid-Halbleiterkomponente mit niedriger Versetzungsdichte

Vorliegend sind verschiedene Ausführungsformen einer Halbleiterkomponente einschließlich eines Ausbuchtungspropagationskörpers offenbart. Die Halbleiterkomponente beinhaltet Folgendes: ein Substrat, einen III-Nitrid-Zwischenstapel einschließlich des Ausbuchtungspropagationskörpers, der sich über dem Substrat befindet, eine III-Nitrid-Pufferschicht, die sich über dem Gruppe-III-Nitrid-Zwischenstapel befindet, und eine III-Nitrid-Vorrichtung, die über der Gruppe-III-Nitrid-Pufferschicht hergestellt ist. Der Ausbuchtungspropagationskörper beinhaltet wenigstens eine Ausbuchtungserzeugungsschicht und zwei oder mehr Ausbuchtungsausbreitungsmehrfachschichten.

Transistorvorrichtung, Schichtstruktur und Verfahren zum Herstellen einer Transistorvorrichtung

Die Erfindung betrifft eine Transistorvorrichtung (1a; 1b; 1c), mit einem Trägersubstrat (11); einem Drain-Anschluss (12), einem Source-Anschluss (13) und einem Gate-Anschluss (14), welche auf einer dem Trägersubstrat (11) gegenüberliegenden Seite der Transistorvorrichtung (1a; 1b; 1c) angeordnet sind; und einer auf dem Trägersubstrat (11) ausgebildeten Struktur (15a; 15b; 15c) aus 3C-Siliziumcarbid, welche zumindest teilweise zwischen dem Trägersubstrat (11) und dem Gate-Anschluss (14) angeordnet ist.

Umverdrahtungssubstrat, elektronisches Bauelement und Modul

Ein Umverdrahtungssubstrat umfasst eine erste leitfähige Schicht, die eine Umverdrahtungsstruktur für Niederspannungssignale aufweist, eine zweite leitfähige Schicht, die eine Umverdrahtungsstruktur für Hochspannungssignale aufweist, und eine nicht leitfähige Schicht. Die zweite leitfähige Schicht ist von der ersten leitfähigen Schicht durch die nicht leitfähige Schicht beabstandet. Das Umverdrahtungssubstrat umfasst außerdem einen leitfähigen Verbinder, der von einer Bestückungsoberfläche des Umverdrahtungssubstrats zu der zweiten leitfähigen Schicht verläuft. Der leitfähige Verbinder ist von einer Niederspannungsleiterbahn der ersten leitfähigen Schicht umgeben.

Gruppe-III-Nitrid-basierte ESD-Schutzvorrichtung

Vorrichtung zum Schutz vor elektrostatischen Entladungen, umfassend:eine erste Gruppe-III-Nitrid-p-i-n-Diode; undeine zweite Gruppe-III-Nitrid-p-i-n-Diode, die mit der ersten Gruppe-III-Nitrid-p-i-n-Diode in einer antiparallelen Anordnung verbunden ist, wobei die Anordnung eingerichtet ist,ein Spannungsklemmen bei 5V oder weniger unter Vorspannung in Durchlassrichtung entweder der ersten oder der zweiten Gruppe-III-Nitrid-p-i-n-Diode für transienten Strom sowohl in der Durchlass- als auch in der Sperrrichtung bereitzustellen,wobei die erste Gruppe-III-Nitrid-p-i-n-Diode eine erste intrinsische Gruppe-III-Nitridzone umfasst, die zwischen einer ersten Gruppe-III-Nitridzone vom n-Typ und einer ersten Gruppe-III-Nitridzone vom p-Typ angeordnet ist;die zweite Gruppe-III-Nitrid-p-i-n-Diode eine zweite intrinsische Gruppe-III-Nitridzone umfasst, die zwischen einer zweiten Gruppe-III-Nitridzone vom n-Typ und einer zweiten Gruppe-III-Nitridzone vom p-Typ angeordnet ist;die erste Gruppe-III-Nitridzone ...

Halbleitervorrichtung

Eine Halbleitervorrichtung umfasst eine Halbleiterschicht, die ein erstes Vorrichtungsausbildungsgebiet und ein zweites Vorrichtungsausbildungsgebiet aufweist, einen ersten HEMT, der in dem ersten Vorrichtungsausbildungsgebiet ausgebildet ist und ein Gebiet zweidimensionalen Elektronengases als einen Kanal aufweist, einen zweiten HEMT, der in dem zweiten Vorrichtungsausbildungsgebiet ausgebildet ist und ein Gebiet zweidimensionalen Elektronengases als einen Kanal aufweist, und eine Gebietstrennstruktur, die in der Halbleiterschicht ausgebildet ist und das erste Vorrichtungsausbildungsgebiet und das zweite Vorrichtungsgebiet definiert.

ZENERDIODEN UND ZUGEHÖRIGE HERSTELLUNGSVERFAHREN

In einem allgemeinen Gesichtspunkt kann eine Halbleitervorrichtung ein hochdotiertes Substrat eines ersten Leitfähigkeitstyps, eine niedrigdotierte Epitaxialschicht eines zweiten Leitfähigkeitstyps, die auf dem hochdotierten Substrat angeordnet ist, und eine hochdotierte Epitaxialschicht des zweiten Leitfähigkeitstyps einschließen, die auf der niedrigdotierten Epitaxialschicht angeordnet ist. Die hochdotierte Epitaxialschicht kann eine Dotierungskonzentration aufweisen, die größer ist als eine Dotierungskonzentration des niedrigdotierten Epitaxialschicht. Mindestens ein Abschnitt des hochdotierten Substrats kann in einer ersten Anschlussklemme einer Zenerdiode eingeschlossen sein, und mindestens ein Abschnitt der niedrigdotierten Epitaxialschicht und mindestens ein Abschnitt der hochdotierten Epitaxialschicht können in einer zweiten Anschlussklemme der Zenerdiode eingeschlossen sein. Die Halbleitervorrichtung kann ferner einen Abschlussgraben einschließen, der sich durch die hochdotierte ...

Gruppe-III-Nitrid-Basierter Anreicherungstransistor

Ein Gruppe-III-Nitrid-basierter Anreicherungstransistor umfasst eine Heteroübergang-Finnenstruktur. Seitenflächen und eine obere Fläche der Heteroübergang-Finnenstruktur sind von einer p-leitenden Gruppe-III-Nitrid-Schicht bedeckt.

Halbleitervorrichtung

Halbleitervorrichtung miteinem Gehäuse (1),einer Eingangsanpassschaltung (4) und einer Ausgangsanpassschaltung (5) in dem Gehäuse (1) undeiner Mehrzahl von Transistorchips (6) zwischen der Eingangsanpassschaltung (4) und der Ausgangsanpassschaltung (5) in dem Gehäuse (1),wobei jeder Transistorchip (6) ein rechteckiges Halbleitersubstrat (8) mit langen Seiten und kurzen Seiten, die kürzer als die langen Seiten sind, sowie eine Gateelektrode (9), eine Drainelektrode (10) und eine Sourceelektrode (11) auf dem Halbleitersubstrat (8) enthält,die Gateelektrode (9) eine Mehrzahl von Gatefingern (9a), die entlang der langen Seiten des Halbleitersubstrats (8) angeordnet sind, und eine Gateanschlussfläche (9b) enthält, die mit der Mehrzahl von Gatefingern (9a) gemeinsam verbunden ist und die über einen Draht (12) mit der Eingangsanpassschaltung (4) verbunden ist,die Drainelektrode (10) über einen Draht (13) mit der Ausgangsanpassschaltung (5) verbunden ist unddie langen Seiten der Halbleitersubstrate ...

Schaltungsanordnung

Die Erfindung betrifft eine Schaltungsanordnung (1) mit zumindest einem Startelement (2, 20), einem ersten Schaltbereich (3) und einem zweiten Schaltbereich (4) sowie optional einer beliebigen Anzahl weiterer Schaltbereiche (3, 4, 5), wobei das Startelement (2, 20) einen Transistor oder eine Diode aufweist und jeder Schaltbereich zumindest einen Schalttransistor aufweist und zumindest das Startelement (2, 20), der erste Schaltbereich (3) und der zweite Schaltbereich (4) sowie weitere Schaltbereiche als Kaskadenschaltung miteinander verbunden sind. Wesentlich ist, dass die Schalttransistoren der Schaltbereiche als normally-on-Transistoren mit einer negativen Schwellspannung ausgebildet sind und dass in der Kaskadenschaltung ein Potentialrückführungsanschluss zu einem Source-Kontakt des Startelements (2, 20) mit einem Gate-Kontakt des ersten Schaltbereichs (3) verbunden ist und ein Drain-Kontakt des Startelements (2, 20) mit einem Gate-Kontakt des zweiten Schaltbereichs (4) verbunden ist.

Isolierschicht-Feldeffekttransistor

Isolierschicht-Feldeffekttransistor (MISFET) mit Drain (104), Source (106) und Gate (102), der dazu eingerichtet ist, bei angesteuertem Gate (102) in einem Kanalgebiet zwischen Drain (104) und Source (106) einen Kanal auszubilden, der einen Stromfluss zwischen Source (106) und Drain (104) ermöglicht, wobei in dem Isolierschicht-Feldeffekttransistor (100) integriert ein spannungsabhängiger Vorwiderstand (108) ausgebildet ist, der zwischen Source (106) und dem Kanalgebiet angeordnet und dazu eingerichtet ist, den Stromfluss zwischen Source (106) und Drain (104) zu beeinflussen.

Heterostrukturanordnung aus Nitrid-Verbindungshalbleitermaterialien und Substrat dafür

Heterostrukturanordnung aus Nitrid-Verbindungshalbleitermaterialien und Substrat dafür

Im Normalzustand abgeschalteter HEMT mit ohmischem Gateanschluss

Halbleitervorrichtung und Herstellungsverfahren dafür

Eine Halbleitervorrichtung, enthaltend:eine Nitridhalbleiterschicht, die ein Gruppe-III-V-Nitridhalbleitermaterial enthält;einen Gate-Isolierfilm, der über der Nitridhalbleiterschicht ausgebildet ist und ein Material mit großer Dielektrizitätskonstante enthält;eine Gate-Elektrode, die auf dem Gate-Isolierfilm ausgebildet ist; undeine Source-Elektrode eine Drain-Elektrode, undeine Basisschicht, die ein leitfähiges Nitridmaterial enthält, um wenigstens eine Unterseite des Gate-Isolierfilms unter der Gate-Elektrode zu bedecken,wobei die Basisschicht mit der Source-Elektrode und der Drain-Elektrode kontaktlos ist.

Method of manufacturing high resistance nitride buffer layers comprising high carbon impurity concentrations

A method of manufacturing a nitride semiconductor device includes, forming a high-resistance buffer layer made of a nitride semiconductor having carbon concentration controlled to 1018cm-3 or above on a semiconductor substrate by an MOCVD method using an organic metal compound as a group III raw material and using a hydrazine derivative as a group V raw material; and forming a nitride semiconductor layer having a resistance value lower than the high-resistance buffer layer on the high-resistance buffer layer. In one embodiment the substrate is Silicon Carbide SiC 1 and the high resistance buffer layer on the substrate comprises AlN (aluminium nitride) with a carbon concentration of 1018cm-3 or above. An electron transit Gallium Nitride GaN layer is grown on top of the AlN high resistance buffer layer, and an AlGaN electron supply layer is grown on top of the GaN layer. Source, gate and drain contacts are then placed on top of the AlGaN layer. Of importance is the growth method of the high ...

Synthetic Diamond Heat Spreaders

High power complimentary field-effect transistors

Diode assembly and method of manufacture thereof

A diode assembly comprises first and second diodes 15, 16, each having a different breakdown voltage, the first and second diodes each comprising a semiconductor substrate 12, an electrically conducting channel layer 13 on the semiconductor substrate, an upper semiconductor layer 14 on the channel layer, the upper semiconductor layer comprising a recess 17, first and second ohmic contacts 22, 23 on the upper semiconductor layer on opposite sides of the recess, the ohmic contacts being connected together to form a first diode contact, and a gate electrode 21 within the recess, the gate electrode forming a second diode contact, wherein the area of the recess of the first diode covered by the first gate electrode is different to the area of the recess of the second diode covered by the second gate electrode. The diode assembly may be used to provide electrostatic discharge protection for a gallium arsenide based circuit.

A diode assembly

Synthetic diamond heat spreaders

A synthetic diamond heat spreader comprising a first layer of synthetic diamond material forming a base support layer, a second layer of synthetic diamond material disposed on the first layer and forming a diamond surface layer, wherein the diamond surface layer has a thickness equal to/less than a thickness of the base support layer and a nitrogen content less than that of the base support layer, and wherein the nitrogen content of the diamond surface layer and the diamond surface layer is selected such that the thermal conductivity layers are 1000 W/mK to 1800 W/mK and 1900 W/mK to 2800 W/mK respectively. The heat spreader may include a metal, silicon/silicon carbide, semiconductor or an adhesive layer. A method of manufacturing a synthetic diamond heat spreader comprising growing a synthetic diamond material in a chemical vapour deposition (CVD) reactor using a carbon source gas, controlling nitrogen concentration in the CVD reactor during growth to form a two layer diamond structure ...

A diode assembly

Epitaxial substrate for field effect transistor

Semiconductor devices and fabrication methods

Semi conductor devices

Transfer printing for RF applications

A semiconductor structure for amplifying an RF signal comprises a cascode structure including a micro transfer printed GaN transistor on an SOI wafer or die. The circuit may comprise further GaN or SOI transistors and may further comprise a linearizer. .

Transfer printing for RF applications

A semiconductor structure for amplifying an RF signal comprises first and second low noise amplifiers where the first low noise amplifier is a micro transfer printed GaN transistor on an SOI wafer and the second low noise amplifier is a SOI transistor. The circuit may comprise further GaN or SOI transistors and may further comprise a linearizer.

Nanowire light emitting switch devices and methods thereof

A nanowire system includes a substrate and at least one nanowire structure which extends out along an axis from a surface of the substrate. The nanowire structure comprises a light emitting diode and a device driver electrically coupled to control an operational state of the light emitting diode. The light emitting diode and the device driver are integrated to each share at least one doped region.

Schottky diode

Compound semiconductor device structures comprising polycrystalline CVD diamond

GALLIUM NITRIDE MATERIALEN AND PROCEEDING FOR THE PRODUCTION OF LAYERS THESE MATERIALEN

LATERAL FIELD-EFFECT TRANSISTOR AND ITS PRODUCTION WITH A SPACER LAYER OVER AND UNDER THE CHANNEL LAYER

PROCEDURE FOR THE BREED OF GAN SINGLE CRYSTALS

Semiconductor wafer and method for testing a semiconductor wafer

Durch die vorliegende Erfindung wird ein Halbleiterwafer bereitgestellt, der durch Ausilden einer Gruppe-III-Nitridhalbleiterschicht durch epitaktisches Wachstum auf emem Si-Wafer erhalten wird, wobei die Gruppe-III-Nitrid-Halbleiterschicht zufriedenstellende Eigenschaften erzielen kann, wie beispielsweise die erforderliche Spannungsfestigkeit, die physikalischen Eigenschaften, wie beispielsweise der Schichtwiderstand zum zuverlässigen Erzielen einer geeigneten Gleichmäßigkeit innerhalb der Ebene, und der Halbleiterwafer sich nur wenig verzieht. Es wird ein Halbleiterwafer bereitgestellt, bei dem eine Nitridkristallschicht auf einem Siliziumwafer eine Reaktionsunterdrückungsschicht, die konfiguriert ist, die Reaktion zwischen einem Siliziumatom und einem Gruppe-lil-Atom zu unterdrücken, eine spannungserzeugende Schicht, die konfiguriert ist, eine Druckspannung zu erzeugen, und eine aktive Schicht aufweist, in der ein elektronisches Element ausgebildet werden soll, wobei die Reaktionsunterdrückungsschicht ...

OPTICAL ELEMENTS WITH TEXTURIERTEN SEMICONDUCTOR LAYERS

PROCEDURE FOR THE PRODUCTION OF AN ELEMENT ON GANBASIS

PIEZOELECTRIC HEMT STRUCTURES WITH ZERO-ALLOY DISORDER

Semiconductor-based, large-area, flexible, electronic devices on {110}less than100greater than oriented substrates

Chimeric Factor VII molecules

The present invention relates to chimeric Factor VII polypeptides and methods of using the same.

Nitride nanowires and method of producing such

Semiconductor devices with non-punch-through semiconductor channels having enhanced conduction and methods of making

Semiconductor device and method of forming a semiconductor device

HIGH POWER-LOW NOISE MICROWAVE GAN HETEROJUNCTION FIELD EFFET TRANSISTOR

Telecommunications switch array with thyristor addressing

Power supply device

A power supply device is provided with: a resistor 11 for limiting the current supplied from an AC power supply 2; a switching unit 12 connected in parallel with the resistor 11; a rectifier circuit unit 13 connected at a stage subsequent to the resistor 11 and the switching unit 12 and rectifying the AC voltage of the AC power supply 2; a booster circuit unit 14 for boosting the rectified DC voltage; a DC voltage detection unit 15 for detecting the DC voltage output from the booster circuit unit 14; an AC voltage detection unit 19 for detecting the AC voltage of the AC power supply 2; a protection setting unit 16 for comparing a first protection voltage calculated on the basis of the boost level obtained by the booster circuit unit 14 with a second protection voltage calculated on the basis of the AC voltage detected by the AC voltage detection unit 19 and setting one of the first and second protection voltages as a protection voltage; and a control unit 17 for, when the DC voltage becomes ...

Field effect transistor (FET) structure with integrated gate connected diodes

A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.

NITRIDE-BASED TRANSISTORS WITH A PROTECTIVE LAYER AND A LOW-DAMAGE RECESS AND METHODS OF FABRICATION THEREOF

Transistors are fabricated by forming a nitride-based semiconductor barrier layer on a nitride-based semiconductor channel layer and forming a protective layer on a gate region of the nitride-based semiconductor barrier layer. Patterned ohmic contact metal regions are formed on the barrier layer and annealed to provide first and second ohmic contacts. The annealing is carried out with the protective layer on the gate region. A gate contact is also formed on the gate region of the barrier layer. Transistors having protective layer in the gate region are also provided as are transistors having a barrier layer with a sheet resistance substantially the same as an as-grown sheet resistance of the barrier layer.

WIDE BANDGAP TRANSISTORS WITH MULTIPLE FIELD PLATES

ISLAND MATRIXED GALLIUM NITRIDE MICROWAVE AND POWER SWITCHING TRANSISTORS

A gallium nitride (GaN) device that has greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The layout scheme, which uses island electrodes rather than finger electrodes, is shown to increase the active area density over that of conventional interdigitated structures. Ultra low on resistance transistors can be built using the island topology. Specifically, the present invention, which uses conventional GaN lateral technology and electrode spacing, provides a means to enhance cost/effective performance of all lateral GaN structures.

CHIMERIC FACTOR VII MOLECULES

The present invention relates to chimeric Factor VII polypeptides comprising EGF-2 and catalytic domains of Factor VII; a GLA domain; and an EGF-1 domain, and methods of using the same.

NITRIDE SEMICONDUCTOR DEVICE

A nitride semiconductor device includes a semiconductor layer, a first electrode for establishing an ohmic contact disposed on the semiconductor layer, and a second electrode on the first electrode, having a different shape from that of the first electrode. A join region is formed with the upper layer of the first electrode and the lower layer of the second electrode. The joint region comprises an element of the platinum group.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE

A power semiconductor device (10) has an active region that includes a drift region (20). At least a portion of the drift region (20) is provided in a membrane )16) which has opposed top and bottom surfaces (15, 17). In one embodiment, the top surface (15) of the membrane (16) has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region (20). In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface (15) and at least one electrical terminal is connected directly or indirectly to the bottom surface (17) to allow a voltage to be applied vertically across the drift region (20). In each of these embodiments, the bottom surface (17) of the membrane (16) does not have a semiconductor substrate positioned adjacent thereto.

VERTICAL-SIDE SOLDER METHOD AND PACKAGE FOR POWER GAN DEVICES

A packaged GaN semiconductor device with improved heat dissipation is provided. A GaN device is packaged on a printed circuit board (PCB) with a vertical side of the device, and optionally the back side of the device, in thermal contact with the PCB. The packaging is compatible with surface mount technologies such as land grid array (LGA), ball grid array (BGA), and other formats. Thermal contact between the PCB and a vertical side of the device, and optionally the back side of the device, is made through solder. The solder used for the thermal contact may also connect a source terminal of the device, which also improves electrical stability of the device. The packaging is particularly suitable for GaN HEMT devices.

METHODS OF FABRICATING NITRIDE-BASED TRANSISTORS WITH A CAP LAYER AND A RECESSED GATE

LATERAL JUNCTION FIELD-EFFECT TRANSISTOR

On p--type epitaxial layer (3), there are sequentially superimposed n-typ e epitaxial layer (4) and gate region (5). Gate electrode (12a) is electrica lly connected to the gate region (5), and source electrode (12b) and drain e lectrode (12c) are disposed with a spacing therebetween so as to interpose t he gate electrode (12a). Control electrode (12d) is for application, to the p--type epitaxial layer (3), of a voltage such that in off operation, the p- -type epitaxial layer (3) and the n-type epitaxial layer (4) fall in reverse bias states.

PULSED GROWTH OF GAN NANOWIRES AND APPLICATIONS IN GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE MATERIALS AND DEVICES

Exemplary embodiments provide semiconductor devices including high-quality (i.e., defect free) group III-N nanowires and uniform group III-N nanowire arrays as well as their scalable processes for manufacturing, where the position, orientation, cross-sectional features, length and the crystallinity of each nanowire can be precisely controlled. A pulsed growth mode can be used to fabricate the disclosed group III-N nanowires and/or nanowire arrays providing a uniform length of about 10 nm to about 1000 microns with constant cross-sectional features including an exemplary diameter of about 10- 1000 nm. In addition, high-quality GaN substrate structures can be formed by coalescing the plurality of GaN nanowires and/or nanowire arrays to facilitate the fabrication of visible LEDs and lasers. Furthermore, core-shell nanowire/MQW active structures can be formed by a core-shell growth on the nonpolar sidewalls of each nanowire.

IMPROVEMENTS TO PARTICLE DETECTORS

A beam detector (10) including a light source (32), a receiver (34), and a target (36), acting in cooperation to detect particles in a monitored area (38). The target (36), reflects incident light (40), resulting in reflected light (32) being returned to receiver (34). The receiver (34) is a receiver is capable of recording and reporting light intensity at a plurality of points across its field of view. In the preferred form the detector (10) emits a first light beam (3614) in a first wavelength band; a second light beam (3618) in a second wavelength band; and a third light beam (3616) in a third wavelength band, wherein the first and second wavelengths bands are substantially equal and are different to the third wavelength band.

SWITCHING ELEMENT AND METHOD OF MANUFACTURING SWITCHING ELEMENT

A switching element includes a semiconductor substrate that includes a first n- type semiconductor layer, a p-type body layer constituted by an epitaxial layer, and a second n-type semiconductor layer separated from the first n-type semiconductor layer by the body layer, a gate insulating film that covers a range across the surface of the first n-type semiconductor layer, the surface of the body layer, and the surface of the second n-type semiconductor layer, and a gate electrode that faces the body layer through the gate insulating film. An interface between the first n-type semiconductor layer and the body layer includes an inclined surface. The inclined surface is inclined such that the depth of the body layer increases as a distance from an end of the body layer increases in a horizontal direction. The inclined surface is disposed below the gate electrode.

INCOHERENT TYPE-III MATERIALS FOR CHARGE CARRIERS CONTROL DEVICES

A semiconductor junction may include a first semiconductor material and a second material. The first and the second semiconductor materials are extrinsically undoped. At least a portion of a valence band of the second material has a higher energy level than at least a portion of the conduction band of the first semiconductor material (type-III band alignment). A flow of a majority of free carriers across the semiconductor junction is diffusive. A region of generation and/or recombination of a plurality of free carriers is confined to a two-dimensional surface of the second material, and at the interface of the first semiconductor material and the second material.

DEVICES, SYSTEMS, AND METHODS FOR THE DETECTION OF ANALYTES

Disclosed are devices, systems, and methods for the rapid and accurate detection of analytes, including Salmonella.

ALUMINUM NITRIDE SUBSTRATE AND GROUP-III NITRIDE LAMINATE

... [Problem] The purpose of the present invention is to provide a high-efficiency, high-quality group-III nitride semiconductor element, and to provide a novel aluminum nitride substrate (aluminum nitride single crystal substrate) for fabricating the group-III nitride semiconductor element. [Solution] A substrate comprising aluminum nitride, wherein the aluminum nitride substrate has on at least a surface thereof an aluminum nitride single-crystal layer having as a principal plane a plane that is inclined 0.050 to 0.40° in the m-axis direction from the (0001) plane of a wurtzite structure.

AlGaN/GaN hybrid MOS-HFET

A field effect transistor (FET) includes source and drain electrodes, a channel layer, a barrier layer over the channel layer, a passivation layer covering the barrier layer for passivating the barrier layer, a gate electrode extending through the barrier layer and the passivation layer, and a gate dielectric surrounding a portion of the gate electrode that extends through the barrier layer and the passivation layer, wherein the passivation layer is a first material and the gate dielectric is a second material, and the first material is different than the second material.

Current aperture diode and method of fabricating same

A diode and a method of making same has a cathode, an anode and one or more semiconductor layers disposed between the cathode and the anode. A dielectric layer is disposed between at least one of the one or more semiconductor layers and at least one of the cathode or anode, the dielectric layer having one or more openings or trenches formed therein through which the at least one of said cathode or anode projects into the at least one of the one or more semiconductor layers, wherein a ratio of a total surface area of the one or more openings or trenches formed in the dielectric layer at the at least one of the one or more semiconductor layers to a total surface area of the dielectric layer at the at least one of the one or more semiconductor layers is no greater than 0.25.

Semiconductor device

An aspect of the present invention inheres in a semiconductor device includes a semiconductor region, a source electrode and a drain electrode, which are provided on a main surface of the semiconductor region, a gate electrode exhibiting normally-off characteristics, the gate electrode being provided above the main surface of the semiconductor region while interposing a p-type material film therebetween, and being arranged between the source electrode and the drain electrode, and a fourth electrode that is provided on the main surface of the semiconductor region, and is arranged between the gate electrode and the drain electrode.

ENGINEERED SUBSTRATE STRUCTURE FOR POWER AND RF APPLICATIONS

Semiconductor device

Compound semiconductor device, method of manufacturing the same, power supply device and high-frequency amplifier

Power semiconductor module and power unit

Plasma oscillation switching device

Nitride compound semiconductor

Semiconductor device and method for manufacturing same

Semiconductor device

Source equalizes and electronic equipment

Field effect transistor

Semiconductor device and manufacturing method thereof and power supply device

Group-III-element nitride crystal semiconductor device

Nucleation of aluminum nitride on a silicon substrate using an ammonia preflow

A silicon wafer used in manufacturing crystalline GaN for light emitting diodes (LEDs) includes a silicon substrate, a buffer layer of aluminum nitride (A1N) and an upper layer of GaN. The silicon wafer has a diameter of at least 200 millimeters and an Si (111) 1xl surface. The A1N buffer layer overlies the Si (111) surface. The GaN upper layer is disposed above the buffer layer. Across the entire wafer substantially no aluminum atoms of the A1N are present in a bottom most plane of atoms of the A1N, and across the entire wafer substantially only nitrogen atoms of the A1N are present in the bottom most plane of atoms of the A1N. A method of making the A1N buffer layer includes preflowing a first amount of ammonia equaling less than 0.01% by volume of hydrogen flowing through a chamber before flowing trimethylaluminum and then a subsequent amount of ammonia through the chamber.

Semiconductor device and method for manufacturing same

Nanobelt-based transistor and preparation method thereof

Semiconductor device and method for manufacturing same

This semiconductor device is provided with an HEMT (10, 20, 21, 30, 31, 32), and a diode (60, 70). The HEMT has: a substrate (10) that includes a GaN layer (13), which is a channel layer where a two-dimensional electron gas is generated, and an AlGaN layer (14), which is a barrier layer on the GaN layer; a source electrode (30), which is formed on the AlGaN layer and in ohmic contact with the AlGaN layer; a drain electrode (31), which is provided on the AlGaN layer by being spaced apart from the source electrode, and is in ohmic contact with the AlGaN layer; interlayer insulating films (20, 21), which are formed on the AlGaN layer between the source electrode and the drain electrode; and a gate electrode (32), which is formed on the interlayer insulating film. The substrate has an active layer region (40) where the two-dimensional electron gas is generated in the GaN layer. The diode has an anode electrically connected to the gate electrode, and a cathode electrically connected to the drain ...

一种特别适用于光学、电子学或光电子学器件的基片加工方法和由该方法获得的基片

... 本发明涉及一种加工基片的方法，该基片包括一构成机械支承的一层来承载的薄层；这一加工方法特别适用于光学、电子学或光电子学器件。根据本发明的方法包括以下步骤：自源基片(6)上分离一层材料，以形成薄层(2)；而后在薄层(2)上沉积材料制备一厚层(4)，以形成构成机械支承的所述层。 ...

Suppression of relaxation by limited area epitaxy on non-c-plane (in,al,b,ga)n

An (AlInGaN) based semiconductor device, including one or more (In,Al)GaN layers overlying a semi-polar or non-polar Ill-nitride substrate or buffer layer, wherein the substrate or buffer employs patterning to influence or control extended defect morphology in layers deposited on the substrate; and one or more (AlInGaN) device layers above and/or below the (In,Al)GaN layers.

Layer structures for controlling stress of heteroepitaxially grown III-nitride layers

An III-N layer structure is described that includes a III-N buffer layer on a foreign substrate, an additional III-N layer, a first III-N structure, and a second III-N layer structure. The first III-N structure above the III-N buffer layer includes at least two III-N layers, each having an aluminum composition, and the III-N layer of the two III-N layers that is closer to the III-N buffer layer having the larger aluminum composition. The second III-N structure includes an III-N superlattice, the III-N superlattice including at least two III-N well layers interleaved with at least two III-N barrier layer. The first III-N structure and the second III-N structure are between the additional III-N layer and the foreign substrate.

Compound semiconductor device and method of manufacturing the same

The invention provides a compound semiconductor device and a method of manufacturing the same. Concretely, provided is an AlGaN/GaN HEMT that includes: an electron transit layer; an electron supply layer formed above the electron transit layer; and a gate electrode formed above the electron supply layer, wherein a p-type semiconductor region is formed only at a site of the electron transit layer which is contained in a region below the gate electrode.

Method and system fabricating floating guard rings in GaN materials

Composite semiconductor device

Power diode preparation method

Semiconductor substrate and semiconductor device

A semiconductor substrate inclu8des an AlN layer that is formed so as to contact a Si substrate and has an FWMH of a rocking curve of a (002) plane by x-ray diffraction, the FWMH being less than or equal to 1500 seconds, and a GaN-based semiconductor layer formed on the AlN layer.

Nitride-based semiconductor device and method for manufacturing the same

The present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes: a base substrate having a diode structure; an epi-growth film disposed on the base substrate; and an electrode part disposed on the epi-growth film, wherein the diode structure includes: first-type semiconductor layers; and a second-type semiconductor layer which is disposed within the first-type semiconductor layers and has both sides covered by the first-type semiconductor layers.

Performance of nitride semiconductor devices

A method of forming a transistor over a nitride semiconductor layer includes surface-treating a first region of a nitride semiconductor layer and forming a gate over the first region. Surface-treating the first region can cause the transistor to have a higher intrinsic small signal transconductance than a similar transistor formed without the surface treatment. A portion of the bottom of the gate can be selectively etched. A resulting transistor can include a nitride semiconductor layer having a surface-treated region and a gate formed over or adjacent to the surface-treated region.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a SiC substrate, a semiconductor layer formed on the SiC substrate, a via hole penetrating through the SiC substrate and the semiconductor layer, a Cu pad that is formed on the semiconductor layer and is in contact with the via hole, and a barrier layer covering an upper face and side faces of the Cu pad, and restrains Cu diffusion.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device includes: forming a lower electrode layer in contact with a surface of a nitride semiconductor layer; forming an Al layer on the lower electrode layer; performing a heat treatment after the formation of the Al layer; removing the Al layer after the heat treatment is performed; and forming an upper electrode layer on the lower electrode layer after the removal of the Al layer.

Microwave semiconductor device using compound semiconductor and method for manufacturing the same

An undoped AlGaN layer 13 is formed on a buffer layer composed of a GaN series material formed on a semiconductor substrate, a drain electrode 15 and a source electrode 16 forming ohmic junction with the undoped AlGaN layer 13 are formed separately from each other on the undoped AlGaN layer 13. A gate electrode 17 composed of metal Ni and Au laminated in this order is formed between the drain electrodes 15 and the source electrode 16 on the undoped AlGaN layer 13. The end portion 17 - 2 of the gate electrode 17 is formed on the underlying metal 18 formed by a metal containing Ti via an insulating film 14 on a GaN buffer layer 12 surrounding the undoped AlGaN layer 13.

Programmable Gate III-Nitride Power Transistor

A III-nitride semiconductor device which includes a charged floating gate electrode.

Limiting strain relaxation in iii-nitride hetero-structures by substrate and epitaxial layer patterning

A method of fabricating a substrate for a semipolar III-nitride device, comprising patterning and forming one or more mesas on a surface of a semipolar III-nitride substrate or epilayer, thereby forming a patterned surface of the semipolar III-nitride substrate or epilayer including each of the mesas with a dimension/along a direction of a threading dislocation glide, wherein the threading dislocation glide results from a III-nitride layer deposited heteroepitaxially and coherently on a non-patterned surface of the substrate or epilayer.

Iii nitride semiconductor substrate, epitaxial substrate, and semiconductor device

In a semiconductor device 100 , it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×10 10 pieces/cm 2 to 2000×10 10 pieces/cm 2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12 . By thus preventing C from piling up, a high-resistivity layer is prevented from being formed on the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10 . Accordingly, it is possible to reduce electrical resistance at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10 , and improve the crystal quality of the epitaxial layer 22 . Consequently, it is possible to improve the emission intensity and yield of the semiconductor device 100.

METHOD FOR FABRICATING A GaN-BASED THIN FILM TRANSISTOR

A method for fabricating a GaN-based thin film transistor includes: forming a semiconductor epitaxial layer on a substrate, the semiconductor epitaxial layer having a n-type GaN-based semiconductor material; forming an insulating layer on the semiconductor epitaxial layer; forming an ion implanting mask on the insulating layer, the ion implanting mask having an opening to partially expose the insulating layer; ion-implanting a p-type impurity through the opening and the insulating layer to form a p-doped region in the n-type GaN-based semiconductor material, followed by removing the insulating layer and the ion implanting mask; forming a dielectric layer on the semiconductor epitaxial layer; partially removing the dielectric layer; forming source and drain electrodes; and forming a gate electrode.

Reducing wafer distortion through a low cte layer

Provided is a method of fabricating a semiconductor device. The method includes forming a first layer on a first side of a first silicon wafer. The first silicon wafer has a second side opposite the first side. The first layer has a coefficient-of-thermal-expansion (CTE) that is lower than that of silicon. The method includes bonding the first wafer to a second silicon wafer in a manner so that the first layer is disposed in between the first and second silicon wafers. The method includes removing a portion of the first silicon wafer from the second side. The method includes forming a second layer over the second side of the first silicon wafer. The second layer has a CTE higher than that of silicon.

Island matrixed gallium nitride microwave and power switching transistors

A gallium nitride (GaN) device that has greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The layout scheme, which uses island electrodes rather than finger electrodes, is shown to increase the active area density over that of conventional interdigitated structures. Ultra low on resistance transistors can be built using the island topology. Specifically, the present invention, which uses conventional GaN lateral technology and electrode spacing, provides a means to enhance cost/effective performance of all lateral GaN structures.

Compound semiconductor device and manufacturing method thereof

A compound semiconductor device includes a substrate; an initial layer formed over the substrate; and a core layer which is formed over the initial layer and contains a Group III-V compound semiconductor. The initial layer is a layer of Group III atoms of the Group III-V compound semiconductor contained in the core layer.

Compound semiconductor device and method of manufacturing the same

A compound semiconductor device includes: a substrate; an electron transit layer formed over the substrate; an electron supply layer formed over the electron transit layer; and a buffer layer formed between the substrate and the electron transit layer and including Al x Ga 1-x N(0≦x≦1), wherein the x value represents a plurality of maximums and a plurality of minimums in the direction of the thickness of the buffer layer, and the variation of x in any area having a 1 nm thickness in the buffer layer is 0.5 or less.

Compound semiconductor device and manufacturing method thereof

A first AlGaN layer formed over a substrate, a second AlGaN layer formed over the first AlGaN layer, an electron transit layer formed over the second AlGaN layer, and an electron supply layer formed over the electron transit layer are provided. A relationship of “0≦x1<x2≦1” is found when a composition of the first AlGaN layer is represented by Al x1 Ga 1-x1 N, and a composition of the second AlGaN layer is represented by Al x2 Ga 1-x2 N. Negative charges exist at an upper surface of the AlGaN layer more than positive charges existing at a lower surface of the AlGaN layer.

particle detectors

A beam detector ( 10 ) including a light source ( 32 ), a receiver ( 34 ), and a target ( 36 ), acting in co-operation to detect particles in a monitored area ( 38 ). The target ( 36 ), reflects incident light ( 40 ), resulting in reflected light ( 32 ) being returned to receiver ( 34 ). The receiver ( 34 ) is a receiver is capable of recording and reporting light intensity at a plurality of points across its field of view. In the preferred form the detector ( 10 ) emits a first light beam ( 3614 ) in a first wavelength band; a second light beam ( 3618 ) in a second wavelength band; and a third light beam ( 3616 ) in a third wavelength band, wherein the first and second wavelengths bands are substantially equal and are different to the third wavelength band.

Nitride based semiconductor device

Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including: a base substrate; a semiconductor layer disposed on the base substrate; and an electrode structure disposed on the semiconductor layer, wherein the electrode structure includes: a cathode structure ohmic-contacting the semiconductor layer; and an anode structure having a schottky electrode schottky-contacting the semiconductor layer and an ohmic electrode ohmic-contacting the nitride layer.

Semiconductor Device And Method Of Manufacturing The Same

Example embodiments relate to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a pre-seeding layer and a nucleation layer. The pre-seeding layer may include a first material for pre-seeding and a second material for masking so as to reduce tensile stress.

Ohmic cathode electrode on the backside of nonpolar m-plane (1-100) and semipolar (20-21) bulk gallium nitride substrates

Ohmic cathode electrodes are formed on the backside of nonpolar m-plane (1-100) and semipolar (20-21) bulk gallium nitride (GaN) substrates. The GaN substrates are thinned using a mechanical polishing process. For m-plane GaN, after the thinning process, dry etching is performed, followed by metal deposition, resulting in ohmic I-V characteristics for the contact. For (20-21) GaN, after the thinning process, dry etching is performed, followed by metal deposition, followed by annealing, resulting in ohmic I-V characteristics for the contact as well.

Epitaxial substrate and method for manufacturing epitaxial substrate

Provided is a crack-free epitaxial substrate having a small amount of warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes a (111) single crystal Si substrate, a buffer layer, and a crystal layer. The buffer layer is formed of a first lamination unit and a second lamination unit being alternately laminated. The first lamination unit includes a composition modulation layer and a first intermediate layer. The composition modulation layer is formed of a first unit layer and a second unit layer having different compositions being alternately and repeatedly laminated so that a compressive strain exists therein. The first intermediate layer enhances the compressive strain existing in the composition modulation layer. The second lamination unit is a second intermediate layer that is substantially strain-free.

Semiconductor device

A semiconductor device of one embodiment, including the semiconductor layer including a III-V group nitride semiconductor; a groove portion formed in the semiconductor layer; the gate insulating film formed at least on a bottom surface of the groove portion, the gate insulating film being a stacked film of a first insulating film and a second insulating film of which dielectric constant is higher than that of the first insulating film; the gate electrode formed on the gate insulating film; and a source electrode and a drain electrode formed on the semiconductor layer across the gate electrode, in which the second insulating film is selectively formed only under the gate electrode.

Semiconductor element, hemt element, and method of manufacturing semiconductor element

A semiconductor device is provided such that a reverse leak current is suppressed, and a Schottky junction is reinforced. The semiconductor device includes an epitaxial substrate formed by laminating a group of group-III nitride layers on a base substrate in such a manner that (0001) surfaces of said group-III nitride layers are substantially parallel to a substrate surface, and a Schottky electrode, in which the epitaxial substrate includes a channel layer formed of a first group-III nitride having a composition of In x1 Al y1 Ga z1 N, a barrier layer formed of a second group-III nitride having a composition of In x2 Al y2 N, and a contact layer formed of a third group-III nitride having insularity and adjacent to the barrier layer, and the Schottky electrode is connected to the contact layer. In addition, a heat treatment is performed under a nitrogen atmosphere after the gate electrode has been formed.

Heterostructure device and associated method

A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.

Ohmic contact to semiconductor device

Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, the ohmic contact structure has less than or equal to 5%, more preferably less than or equal to 2%, more preferably less than or equal to 1.5%, and even more preferably less than or equal to 1% degradation for 1000 hours High Temperature Soak (HTS) at 300 degrees Celsius. In another embodiment, the ohmic contact structure additionally or alternatively has less than or equal to 10% degradation, more preferably less than or equal to 7.5% degradation, more preferably less than or equal to 6% degradation, more preferably less than or equal to 5% degradation, and even more preferably less than 3% degradation for 1000 hours High Temperature operating Life (HToL) at 225 degrees Celsius and 50 milliamps (mA) per millimeter (mm).

Semiconductor device and method of manufacturing the same

A semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, and a protective insulating film composed of silicon nitride, which is formed over a surface of the compound semiconductor layer and whose film density in an intermediate portion is lower than that in a lower portion.

Method for making gallium nitride substrate

A method for making a GaN substrate for growth of nitride semiconductor is provided. The method first provides a GaN single crystal substrate. Then an ion implanting layer is formed inside the GaN single crystal substrate, which divides the GaN single crystal substrate into a first section and a second section. After that, the GaN single crystal substrate is connected with an assistant substrate through a connecting layer. Thereafter, the GaN single crystal substrate is heated whereby the ion implanting layer is decompounded. Finally, the second section is separated from the first section. The first section left on a surface of the assistant substrate is provided for growth of nitride semiconductor thereon.

Method for Growth of Indium-Containing Nitride Films

A method for growth of indium-containing nitride films is described, particularly a method for fabricating a gallium, indium, and nitrogen containing material. On a substrate having a surface region a material having a first indium-rich concentration is formed, followed by a second thickness of material having a first indium-poor concentration. Then a third thickness of material having a second indium-rich concentration is added to form a sandwiched structure which is thermally processed to cause formation of well-crystallized, relaxed material within a vicinity of a surface region of the sandwich structure.

High-quality non-polar/semi-polar semiconductor device on porous nitride semiconductor and manufacturing method thereof

Provided are a high-quality non-polar/semi-polar semiconductor device having reduced defect density of a nitride semiconductor layer and improved internal quantum efficiency and light extraction efficiency, and a manufacturing method thereof. The method for manufacturing a semiconductor device is to form a template layer and a semiconductor device structure on a sapphire, SiC or Si substrate having a crystal plane for a growth of a non-polar or semi-polar nitride semiconductor layer. The manufacturing method includes: forming a nitride semiconductor layer on the substrate; performing a porous surface modification such that the nitride semiconductor layer has pores; forming the template layer by re-growing a nitride semiconductor layer on the surface-modified nitride semiconductor layer; and forming the semiconductor device structure on the template layer.

Compound semiconductor device and method of manufacturing the same

At least one kind of impurity selected from, for example, Fe, C, B, Ti, Cr is introduced into at least a buffer layer of a compound semiconductor layered structure from a rear surface of the compound semiconductor layered structure to make a resistance value of the buffer layer high.

Method of producing semiconductor device and semiconductor device

A method of producing a semiconductor device, includes: forming a semiconductor layer on a substrate; forming an a recess in the semiconductor layer by dry etching with a gas containing fluorine components, the recess having an opening portion on the surface of the semiconductor layer; forming a fluorine-containing region by heating the semiconductor layer and thus diffusing, into the semiconductor layer, the fluorine components attached to side surfaces and a bottom surface of the recess; forming an insulating film on an inner surface of the recess and on the semiconductor layer; and forming an electrode on the insulating film in a region in which the recess is formed.

Semiconductor device and method of manufacturing the same, and power supply apparatus

A semiconductor device includes an electrode material diffusion suppression layer provided either between a gate electrode and a gate insulation film, between Al-containing ohmic electrodes and an Au interconnection, and below the gate electrode and above the Al-containing ohmic electrodes, the electrode material diffusion suppression layer having a structure wherein a first the TaN layer, a Ta layer, and a second the TaN layer are stacked in sequence.

Semiconductor diodes with low reverse bias currents

A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.

Semiconductor rectifier device

A semiconductor rectifier device according to an embodiment includes a semiconductor substrate of a first conductive type of a wide gap semiconductor, a semiconductor layer of the first conductive type of the wide gap semiconductor formed on an upper surface of the semiconductor substrate, wherein an impurity concentration of the semiconductor layer is between 1E+14 atoms/cm 3 and 5E+16 atoms/cm 3 inclusive, and a thickness thereof is 8 μm or more, a first semiconductor region of the first conductive type of the wide gap semiconductor formed on the semiconductor layer surface, a second semiconductor region of the second conductive type of the wide gap semiconductor formed as sandwiched by the first semiconductor regions, wherein a width of the second semiconductor region is 15 μm or more, a first electrode formed on the first and second semiconductor regions, and a second electrode formed on a lower surface of the semiconductor substrate.

High temperature performance capable gallium nitride transistor

A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III nitrides) and exhibits decreased degradation when operating at high temperatures. The device may also incorporate a field plate to further increase the operating lifetime of the device.

Normally-Off Semiconductor Devices

Normally-off semiconductor devices are provided. A Group III-nitride buffer layer is provided. A Group III-nitride barrier layer is provided on the Group III-nitride buffer layer. A non-conducting spacer layer is provided on the Group III-nitride barrier layer. The Group III-nitride barrier layer and the spacer layer are etched to form a trench. The trench extends through the barrier layer and exposes a portion of the buffer layer. A dielectric layer is formed on the spacer layer and in the trench and a gate electrode is formed on the dielectric layer. Related methods of forming semiconductor devices are also provided herein.

method for reducing internal mechanical stresses in a semiconductor structure and a low mechanical stress semiconductor structure

A semiconductor structure with low mechanical stresses, formed of nitrides of group III metals on a (0001) oriented foreign substrate ( 1 ) and a method for reducing internal mechanical stresses in a semiconductor structure formed of nitrides of group III metals on a (0001) oriented foreign substrate ( 1 ). The method comprises the steps of; growing nitride on the foreign substrate ( 1 ) to form a first nitride layer ( 2 ); patterning the first nitride layer ( 2 ) by selectively removing volumes of it to a predetermined depth from the upper surface of the first nitride layer ( 2 ), for providing relaxation of mechanical stress σ in the remaining portions of the layer between the removed volumes; and growing, on the first nitride layer ( 2 ), additional nitride until a continuous second nitride layer ( 8 ) is formed, the second nitride layer ( 8 ) enclosing voids ( 7 ) from the removed volumes under the second nitride layer ( 8 ) inside the semiconductor structure.

Semiconductor device based on the cubic silicon carbide single crystal thin film

A semiconductor apparatus includes a cubic silicon carbide single crystal thin film of a multilayer structure including an Al x Ga 1-x As (0.6>x≧ 0 ) layer and a cubic silicon carbide single crystal layer. The apparatus also includes a substrate on which a metal layer is formed. The multilayer structure is bonded to a surface of the metal layer with the Al x Ga 1-x As (0.6>x≧ 0 ) in direct contact with the metal layer.

Epitaxial substrate for electronic device and method of producing the same

An epitaxial substrate for an electronic device, in which a lateral direction of the substrate is defined as a main current conducting direction and a warp configuration of the epitaxial substrate is adequately controlled, as well as a method of producing the epitaxial substrate. Specifically, the epitaxial substrate for an electron device, including: a Si single crystal substrate; and a Group III nitride laminated body formed by epitaxially growing plural Group III nitride layers on the Si single crystal substrate, wherein a lateral direction of the epitaxial substrate is defined as a main current conducting direction, is characterized in that the Si single crystal substrate is a p-type substrate having a specific resistance value of not larger than 0.01 Ω·cm.

Bidirectional switch and charge/discharge protection device using same

A bidirectional switch device, has: a bidirectional switch having a HEMT; and a control circuit which, during a first condition, applies a first voltage lower than a threshold voltage across a gate and one terminal among a source and a drain of the HEMT to turn off a first current path from the other terminal among the source and the drain to the one terminal, and during a second condition, applies a second voltage lower than the threshold voltage across the other terminal and the gate to turn off a second current path from the one terminal to the other terminal, and further during a third condition, applies a third voltage higher than the threshold voltage across the source and the gate and across the drain and the gate of the HEMT to turn on the first and second current paths.

Functional element and manufacturing method of same

Provided is a functional element which is obtained by forming a lamination film on a substrate and then dividing the substrate and the lamination film into a desired shape. The functional element has a hexagonal substrate, a lamination film formed on a C surface of the substrate, and a plurality of divided surfaces which are exposed by dividing the substrate into quadrilaterals. At least one line of division lines in the case of dividing the substrate into quadrilaterals is perpendicular to any one of equivalent directions of [ 1 - 100], [ - 1010], and [ 01 - 01] of the substrate from a [ 0001 ] direction of the substrate, and the divided surfaces formed by the division lines are inclined in a direction of other divided surfaces to which at least a part thereof is opposed.

Monolithic Group III-V Power Converter

A power arrangement that includes a monolithically integrated III-nitride power stage having III-nitride power switches and III-nitride driver switches.

Lateral trench mesfet

A transistor includes a trench formed in a semiconductor body, the trench having sidewalls and a bottom. The transistor further includes a first semiconductor material disposed in the trench adjacent the sidewalls and a second semiconductor material disposed in the trench and spaced apart from the sidewalls by the first semiconductor material. The second semiconductor material has a different band gap than the first semiconductor material. The transistor also includes a gate material disposed in the trench and spaced apart from the first semiconductor material by the second semiconductor material. The gate material provides a gate of the transistor. Source and drain regions are arranged in the trench with a channel interposed between the source and drain regions in the first or second semiconductor material so that the channel has a lateral current flow direction along the sidewalls of the trench.

Compound semiconductor device and method for manufacturing the same

An AlGaN/GaN-HEMT has a structure including: compound semiconductor layers formed on a substrate; a gate electrode, a gate pad that has a current path formed between the gate electrode and itself, and a semiconductor layer that is spontaneously polarized and piezoelectrically polarized, which are formed on the compound semiconductor layer; and a gate electrode connection layer formed on the semiconductor layer, wherein the gate electrode connection layer and the gate electrode are electrically connected with each other. This structure which is relatively simple allows the AlGaN/GaN-HEMT to realize an intended normally-off operation without causing such inconveniences as increase in a sheet resistance, increase in an on-resistance, and increase in a leakage current.

Bi-fet cascode power switch

Power switch devices for high-speed applications are disclosed. The power switch device includes a depletion mode field effect transistor (D-FET), an enhancement mode field effect transistor (E-FET) and a bipolar transistor. In one embodiment, the E-FET is coupled in cascode with the D-FET such that turning off the E-FET turns off the D-FET and turning on the E-FET turns on the D-FET. Furthermore, the bipolar transistor is operably associated with the D-FET and the E-FET such that turning on the bipolar transistor drives current from the D-FET through the bipolar transistor to the E-FET to provide a charge that turns on the E-FET. The bipolar transistor provides several advantages such as a higher Schottky breakdown voltage for the E-FET and faster current switching speed for the power switch device.

Semiconductor structure and method of forming the same

An embodiment of the disclosure includes a semiconductor structure. The semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. An interface is defined between the first III-V compound layer and the second III-V compound layer. A gate is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on opposite side of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second III-V compound layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.

Power semiconductor device

A power semiconductor device and a manufacturing method thereof are provided. The power semiconductor device includes an anode electrode including an anode electrode pad, electrode bus lines connected to a first side and a second side on the anode electrode pad, the electrode bus lines each having a decreasing width in a direction away from the anode electrode pad, and pluralities of first anode electrode fingers and second anode electrode fingers connected with a third side and a fourth side on the anode electrode pad and with both sides of the electrode bus line, a cathode electrode including a first cathode electrode pad and a second cathode electrode pad, a plurality of cathode electrode fingers connected with the first cathode electrode pad, and a plurality of second cathode electrode fingers connected with the second cathode electrode pad, and an insulation layer disposed at an external portion of the anode.

Method for manufacturing diode, and diode

A semiconductor substrate having a first side and a second side made of single crystal silicon carbide is prepared. A mask layer having a plurality of openings and made of silicon oxide is formed on the second side. The plurality of openings expose a plurality of regions included in the second side, respectively. A plurality of diamond portions are formed by epitaxial growth on the plurality of regions, respectively. The epitaxial growth is stopped before the plurality of diamond portions come into contact with each other. A Schottky electrode is formed on each of the plurality of diamond portions. An ohmic electrode is formed on the first side.

Digital oxide deposition of sio2 layers on wafers

Novel silicon dioxide and silicon nitride deposition methods are generally disclosed. In one embodiment, the method includes depositing silicon on the surface of a substrate having a temperature of between about 65° C. and about 350° C. The heated substrate is exposed to a silicon source that is substantially free from an oxidizing agent. The silicon on the surface is then oxidized with an oxygen source that is substantially free from a silicon source. As a result of oxidizing the silicon, a silicon oxide layer forms on the surface of the substrate. Alternatively, or in additionally, a nitrogen source can be provided to produce silicon nitride on the surface of the substrate.

Method and system for doping control in gallium nitride based devices

A method of growing a III-nitride-based epitaxial structure includes providing a substrate in an epitaxial growth reactor and heating the substrate to a predetermined temperature. The method also includes flowing a gallium-containing gas into the epitaxial growth reactor and flowing a nitrogen-containing gas into the epitaxial growth reactor. The method further includes flowing a gettering gas into the epitaxial growth reactor. The predetermined temperature is greater than 1000° C.

Metal chloride gas generator, hydride vapor phase epitaxy growth apparatus, and nitride semiconductor template

A metal chloride gas generator includes: a tube reactor including a receiving section for receiving a metal on an upstream side, and a growing section in which a growth substrate is placed on a downstream side; a gas inlet pipe arranged to extend from an upstream end with a gas inlet via the receiving section to the growing section, for introducing a gas from the upstream end to supply the gas to the receiving section, and supplying a metal chloride gas produced by a reaction between the gas and the metal in the receiving section to the growing section; and a heat shield plate placed in the reactor to thermally shield the upstream end from the growing section. The gas inlet pipe is bent between the upstream end and the heat shield plate.

Hemt with integrated low forward bias diode

A high electron mobility transistor includes a source, gate and drain, a first III-V semiconductor region having a two-dimensional electron gas (2DEG) which provides a first conductive channel controllable by the gate between the source and drain, and a second III-V semiconductor region below the first III-V semiconductor region and having a second conductive channel connected to the source or drain and not controllable by the gate. The first and second III-V semiconductor regions are spaced apart from one another by a region of the high electron mobility transistor having a different band gap than the first and second III-V semiconductor regions.

Nitride semiconductor transistor

A nitride semiconductor transistor includes a heterojunction layer including a plurality of nitride semiconductor layers having different polarizations, and a gate electrode disposed on the heterojunction layer. An electron current reduction layer having a p-type conductivity is disposed between the heterojunction layer and the gate electrode to pass hole current therethrough and reduce electron current.

Ge QUANTUM DOTS FOR DISLOCATION ENGINEERING OF III-N ON SILICON

A virtual substrate structure includes a crystalline silicon substrate with a first layer of III-N grown on the silicon substrate. Ge clusters or quantum dots are grown on the first layer of III-N and a second layer of III-N is grown on the Ge clusters or quantum dots and any portions of the first layer of III-N exposed between the Ge clusters or quantum dots. Additional alternating Ge clusters or quantum dots and layers of III-N are grown on the second layer of III-N forming an upper surface of III-N. Generally, the additional alternating layers of Ge clusters or quantum dots and layers of III-N are continued until dislocations in the III-N adjacent the upper surface are substantially eliminated.

Nitride semiconductor crystal producing method, nitride semiconductor epitaxial wafer, and nitride semiconductor freestanding substrate

A nitride semiconductor crystal producing method, a nitride semiconductor epitaxial wafer, and a nitride semiconductor freestanding substrate, by which it is possible to suppress the occurrence of cracking in the nitride semiconductor crystal and to ensure the enhancement of the yield of the nitride semiconductor crystal. The nitride semiconductor crystal producing method includes growing a nitride semiconductor crystal over a seed crystal substrate, while applying an etching action to an outer end of the seed crystal substrate during the growing of the nitride semiconductor crystal.

CRYSTAL PRODUCING APPARATUS, CRYSTAL PRODUCING METHOD, SUBSTRATE PRODUCING METHOD, GALLIUM NITRIDE CRYSTAL, AND GALLIUM NITRIDE SUBSTRATE

A crystal producing apparatus includes a crystal forming unit and a crystal growing unit. The crystal forming unit forms a first gallium nitride (GaN) crystal by supplying nitride gas into melt mixture containing metal sodium (Na) and metal gallium (Ga). The first GaN crystal is sliced and polished to form GaN wafers. The crystal growing unit grows a second GaN crystal on a substrate formed by using a GaN wafer, by the hydride vapor phase epitaxy method, thus producing a bulked GaN crystal. 123-. (canceled)24. A method for producing a columnar-shaped group-III nitride crystal , the method comprising:{'sup': 5', '−2, '(a) obtaining a first group-III nitride crystal, grown by a flux method at a first crystal-growth speed, and having a dislocation density equal to or less than 10cm;'}{'sup': 5', '−2, '(b) growing a second group-III nitride crystal at a second crystal-growth speed, by vapor phase epitaxy method on a surface of the first group-III nitride crystal having the dislocation density equal to or less than 10cm,'}wherein the second crystal-growth speed is faster than the first crystal-growth speed, andwherein the first group-III nitride crystal is in a columnar shape, in which a length in a c-axis direction is longer than a length in an a-axis direction.25. The method according to claim 24 , further comprising slicing the first group-III nitride crystal before performing the growing.26. The method according to claim 25 , wherein the first group-III nitride crystal is capable of being reused.27. The method according to claim 24 , wherein the first group-III nitride crystal and the second group-III nitride crystal are gallium nitride crystals.28. The method according to claim 24 , wherein the flux method includes:detecting a temperature of the seed crystal and first group-III nitride crystal and a temperature of a melt mixture; andcontrolling a flow rate of the nitrogen source gas supplied into the melt mixture, to change the temperature of the seed crystal and ...

Semiconductor device and solid state relay using same

A semiconductor device includes one or more unipolar compound semiconductor element; and bypass semiconductor elements externally connected to the respective compound semiconductor elements in parallel. A turn-on voltage of the bypass semiconductor elements is smaller than a turn-on voltage of the compound semiconductor elements in the direction from the source to the drain.

Compound semiconductor device and method of manufacturing the same

An embodiment of a compound semiconductor device includes: a Si substrate; a Si oxide layer formed over a surface of the Si substrate; a nucleation layer formed over the Si oxide layer, the nucleation layer exposing a part of the Si oxide layer; and a compound semiconductor stacked structure formed over the Si oxide layer and the nucleation layer.

Semiconductor device

A semiconductor device includes a first semiconductor layer formed on a substrate; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; a gate electrode formed on the third semiconductor layer; and a source electrode and a drain electrode formed on the second semiconductor layer. The third semiconductor layer is formed with a semiconductor material doped with a p-type impurity element. In the third semiconductor layer, a p-type area is formed immediately below the gate electrode, and a high resistance area having a higher resistance than the p-type area is formed in an area other than the p-type area.

Compound semiconductor device and method of manufacturing the same

An embodiment of a compound semiconductor device includes: a substrate; an electron channel layer and an electron supply layer formed over the substrate; a gate electrode, a source electrode and a drain electrode formed on or above the electron supply layer; a p-type semiconductor layer formed between the electron supply layer and the gate electrode; and a hole barrier layer formed between the electron supply layer and the p-type semiconductor layer, a band gap of the hole barrier layer being larger than that of the electron supply layer.

SEMICONDUCTOR DEVICE, FABRICATION METHOD OF THE SEMICONDUCTOR DEVICES

In a semiconductor device, a YAG substrate is formed as a single-crystal substrate of any of surface orientations (100), (110), and (111). In the fabrication of the semiconductor device, a TMAl gas is first fed onto the YAG substrate so as to form a nucleation layer made of aluminum, which is a group-III element. Then, an NHgas is fed onto the nucleation layer. This turns the surface of the nucleation layer into a group-V element and then forms a group-III-V compound layer of AlN. Then, a mixed gas of TMAl gas and NHgas is fed onto the group-III-V compound layer so as to form another group-III-V compound layer. Finally, a group-III nitride semiconductor layer is crystal-grown on the group-III compound layer. 1. A method for fabricating a semiconductor device , the method comprising:{'sub': 3', '5', '12, 'forming a buffer layer, containing a group-III-V compound, on a substrate formed of YAlO; and'}forming a group-III nitride semiconductor layer on the buffer layer,wherein the forming the buffer layer includes forming a nucleation layer made of a group-III element in at least a part on the substrate,wherein the substrate is a single-crystal substrate of any of surface orientations (100) and (110).2. A method for fabricating a semiconductor device according to claim 1 , wherein the nucleation layer is formed by supplying a first gas containing a group-III element onto the substrate.3. A method for fabricating a semiconductor device according to claim 1 , wherein the forming a buffer layer further includes changing at least a part of the surface of the nucleation layer into a group-III-V compound by combining the at least a part of the surface of the nucleation layer with a group V element.4. A method for fabricating a semiconductor device according to claim 3 , wherein the at least a part of the surface of the nucleation layer is changed into a group-III-V compound by supplying a second gas containing a group-V element onto the nucleation layer.5. A method for ...

Semiconductor device

A semiconductor device including a high resistance layer formed on a substrate, the high resistance layer being formed with a semiconductor material doped with an impurity element that makes the semiconductor material highly resistant; a multilayer intermediate layer formed on the high resistance layer; an electron transit layer formed with a semiconductor material on the multilayer intermediate layer; and an electron supply layer formed with a semiconductor material on the electron transit layer, wherein the multilayer intermediate layer is formed with a multilayer film in which a GaN layer and an AlN layer are alternately laminated.

Semiconductor device and method of manufacturing the same, and power supply apparatus

A semiconductor device includes a substrate; a first nitride semiconductor layer provided over the substrate and having a nitride-polar surface; a gate electrode provided over the first nitride semiconductor layer; and a semiconductor layer provided on the first nitride semiconductor layer and only under the gate electrode, and exhibiting a polarization.

Nitride semiconductor device and manufacturing method thereof

The present invention relates to a nitride semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a plurality of p-type nitride semiconductor segments formed on the nitride semiconductor layer and each formed lengthways from a first sidewall thereof, which is spaced apart from the source electrode, to a drain side; and a gate electrode formed to be close to the source electrode and in contact with the nitride semiconductor layer between the plurality of p-type semiconductor segments and portions of the p-type semiconductor segments extending in the direction of a source-side sidewall of the gate electrode aligned with the first sidewalls of the p-type nitride semiconductor segments is provided.

Compound semiconductor device and method for fabricating the same

A compound semiconductor multilayer structure is formed on a Si substrate. The compound semiconductor multilayer structure includes an electrode transit layer, an electrode donor layer formed above the electron transit layer, and a cap layer formed above the electron donor layer. The cap layer contains a first crystal polarized in the same direction as the electron transit layer and the electron donor layer and a second crystal polarized in the direction opposite to the polarization direction of the electron transit layer and the electron donor layer.

Nitride semiconductor wafer, nitride semiconductor device, and method for growing nitride semiconductor crystal

According to one embodiment, a nitride semiconductor wafer includes a silicon substrate, a lower strain relaxation layer provided on the silicon substrate, an intermediate layer provided on the lower strain relaxation layer, an upper strain relaxation layer provided on the intermediate layer, and a functional layer provided on the upper strain relaxation layer. The intermediate layer includes a first lower layer, a first doped layer provided on the first lower layer, and a first upper layer provided on the first doped layer. The first doped layer has a lattice constant larger than or equal to that of the first lower layer and contains an impurity of 1×10 18 cm −3 or more and less than 1×10 21 cm −3 . The first upper layer has a lattice constant larger than or equal to that of the first doped layer and larger than that of the first lower layer.

Epitaxial growth substrate, semiconductor device, and epitaxial growth method

In heteroepitaxially growing a group-III nitride semiconductor on a Si single crystal substrate, the occurrence of cracks initiating in the wafer edge portion can be suppressed. Region A is an outermost peripheral portion outside the principal surface, being a bevel portion tapered. Regions B and C are on the same plane (the principal surface), region B (mirror-surface portion) being the center portion of the principal surface, and region C a region in the principal surface edge portion surrounding region B. The principal surface has a plane orientation, and in region B, is mirror-surface-finished. Region B occupies most of the principal surface of this Si single crystal substrate, and a semiconductor device is manufactured therein. Region C (surface-roughened portion) has a plane orientation as with region B, however, region B is mirror-surface-finished, whereas region C is surface-roughened.

High power semiconductor electronic components with increased reliability

An electronic component includes a depletion-mode transistor, an enhancement-mode transistor, and a resistor. The depletion-mode transistor has a higher breakdown voltage than the enhancement-mode transistor. A first terminal of the resistor is electrically connected to a source of the enhancement-mode transistor, and a second terminal of the resistor and a source of the depletion-mode transistor are each electrically connected to a drain of the enhancement-mode transistor. A gate of the depletion-mode transistor can be electrically connected to a source of the enhancement-mode transistor.

GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate. 1. A composite substrate for a semiconductor to grow thereon comprising:a silicon substrate comprising a first surface and a second surface opposite to the first surface, the first surface defining a plurality of grooves therein, the second surface being configured for growth of the semiconductor thereon; anda filler filled into the plurality of grooves on the first surface of the silicon substrate, a thermal expansion coefficient of the filler being bigger than that of the silicon substrate.2. The composite substrate as claimed in claim 1 , wherein the plurality of grooves are uniformly arranged in the first surface.3. The composite substrate as claimed in claim 1 , wherein the plurality of grooves have a same depth.4. The composite substrate as claimed in claim 1 , wherein the depth of the grooves is in a range from one third of a thickness of the silicon substrate to a half of the thickness of the silicon substrate.5. The composite substrate as claimed in claim 1 , wherein the filler is selected from the group consisting of AlO claim 1 , SiC claim 1 , AlN claim 1 , InN claim 1 , MgN claim 1 , ZnO claim 1 , GaAs claim 1 , GaP and Ge.6. A gallium nitride-based semiconductor device comprising: a silicon substrate comprising a first surface and a second surface opposite to the first surface, the first surface defining a plurality of grooves therein; and', 'a filler filled into ...

EPITAXIAL SUBSTRATE AND METHOD FOR MANUFACTURING EPITAXIAL SUBSTRATE

Provided is a crack-free epitaxial substrate having a small amount of warping, in which a silicon substrate is used as a base substrate. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer formed of a plurality of lamination units being continuously laminated. The lamination unit includes: a composition modulation layer formed of a first and a second unit layer having different compositions being alternately and repeatedly laminated such that a compressive strain exists therein; a termination layer formed on an uppermost portion of the composition modulation layer, the termination layer acting to maintain the compressive strain existing in the composition modulation layer; and a strain reinforcing layer formed on the termination layer, the strain reinforcing layer acting to enhance the compressive strain existing in the composition modulation layer. 1. An epitaxial substrate in which a group of group-III nitride layers are formed on a base substrate made of (111)-oriented single crystal silicon such that a (0001) crystal plane of said group of group-III nitride layers is substantially in parallel with a substrate surface of said base substrate , said epitaxial substrate comprising:a buffer layer formed of a plurality of lamination units being continuously laminated; anda crystal layer formed on said buffer layer, a composition modulation layer formed of a first unit layer and a second unit layer having different compositions being alternately and repeatedly laminated such that a compressive strain exists therein;', 'a termination layer formed on an uppermost portion of said composition modulation layer, said termination layer acting to maintain said compressive strain existing in said composition modulation layer; and', 'a strain reinforcing layer formed on said termination layer, said strain reinforcing layer acting to enhance said compressive strain existing in said composition modulation layer., 'said lamination unit ...

NORMALLY-OFF III-NITRIDE METAL-2DEG TUNNEL JUNCTION FIELD-EFFECT TRANSISTORS

Structures, devices and methods are provided for creating heterojunction AlGaN/GaN metal two-dimensional electron gas (2DEG) tunnel-junction field-effect transistors (TJ-FET). In one aspect, metal-2DEG Schottky tunnel junctions can be employed in group III-Nitride field-effect devices that enable normally-off operation, large breakdown voltage, low leakage current, and high on/off current ratio. As a further advantage, AlGaN/GaN metal-2DEG TJ-FETs are disclosed that can be fabricated in a lateral configuration and/or a vertical configuration. Further non-limiting embodiments are provided that illustrate the advantages and flexibility of the disclosed structures. 1. A tunnel junction field-effect transistor (TJ-FET) having prospective locations for a source , a gate , and a drain , the TJ-FET comprising:a substrate comprising a buffer layer deposited on the substrate and a bather layer deposited on the buffer layer, the buffer layer and the barrier layer forming a heterojunction at an interface of the buffer layer and the barrier layer; anda metal region adjacent to the buffer layer, proximate to the prospective location for the source, and spanning a portion of the heterojunction.2. The TJ-FET of claim 1 , the substrate comprising at least one of sapphire claim 1 , silicon (111) claim 1 , silicon carbide (SiC) claim 1 , aluminum nitride (AlN) claim 1 , or GaN.3. The TJ-FET of claim 1 , the buffer layer is deposited on the substrate over a nucleation layer comprised of a group III-nitride.4. The TJ-FET of claim 1 , the substrate comprises sapphire claim 1 , the buffer layer comprises undoped GaN claim 1 , and the bather layer comprises a III-nitride barrier layer.5. The TJ-FET of claim 1 , further comprising:an insulating dielectric layer deposited above the bather layer proximate to the prospective location for the gate.6. The TJ-FET of claim 5 , further comprising:the gate deposited above the insulating dielectric layer.7. The TJ-FET of claim 6 , the gate further ...

SUBSTRATE FOR EPITAXIAL GROWTH

A surface of the substrate consists in plurality of neighbouring stripe shaped flat surfaces of a width from 1 to 2000 μm. Longer edges of the flat surfaces are parallel one to another and planes of these surfaces are disoriented relatively to the crystallographic plane of gallium nitride crystal defined by Miller-Bravais indices (0001), (11-22) or (11-20). Disorientation angle of each of the flat surfaces is between 0 and 3 degree and is different for each pair of neighbouring flat surfaces. Substrate according to the invention allows epitaxial growth of a layered AlInGaN structure by MOCVD or MBE method which permits for realization of a non-absorbing mirrors laser diode emitting a light of the wavelength from 380 to 550 nm and a laser diodes array which may emit simultaneously light of various wavelengths in the range of 380 to 550 nm. 1. A substrate for epitaxial growth made of gallium nitride crystal , and having epi-ready growth surface , characterized in that the growth surface consists of set of neighbouring flat surfaces in form of stripes of a width from 1 to 2000 μm , longer edges of the stripes are parallel on to another , planes of the stripes are disoriented relatively to the crystallographic plane defined by Miller-Bravais indices (0001) , (10-10) , (11-22) or (11-20) and disorientation angle of each of the flat surfaces is from 0 to 3 degree and it is different for each of two neighbouring surfaces.2. The substrate according to claim 1 , characterized in that all the flat surfaces are disoriented relatively to the crystallographic plane defined by the Miller-Bravais indices (0001).3. The substrate according to claim 2 , characterized in that the longer edges of all the flat surfaces are parallel to a given crystallographic direction of gallium nitride crystal while the flat surfaces are delimited by said longer edges and form over the whole crystal an array of repeating sequences.4. The substrate according to claim 3 , characterized in that the ...

SEMICONDUCTOR DEVICES HAVING A RECESSED ELECTRODE STRUCTURE

An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance. 1. A field effect transistor , comprising:a source region;a drain region;a semiconductor region between the source region and the drain region, the semiconductor region having trenches extending along a direction that extends between the source region and the drain region;a conductive electrode having conductive regions formed in the trenches, the conductive electrode extending no more than a portion of a distance between the source region and the drain region; andan insulating region between the semiconductor region and the conductive electrode, the insulating region extending at least partially across an interface between the semiconductor region and the conductive electrode.2. The field effect transistor of claim 1 , wherein the first semiconductor region includes a III-N semiconductor material.3. The field effect transistor of claim 2 , wherein the III-N semiconductor material includes GaN.4. The field effect transistor of claim 1 , wherein the semiconductor region is a first semiconductor region claim 1 , and the field effect transistor further comprises a second semiconductor region between the first semiconductor region and the insulating region and/or conductive electrode.5. The field effect transistor of claim 4 , wherein the first semiconductor region includes a first III-N semiconductor material and the second semiconductor region includes a second III-N semiconductor material claim 4 , and wherein the first III-N semiconductor material has a different bandgap from that of the ...

Group iii-nitride metal-insulator-semiconductor heterostructure field-effect transistors

Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device such as, for example, a high electron mobility transistor (HEMT) or metal-insulator-semiconductor field-effect transistor (MISFET), or combinations thereof. The IC device includes a buffer layer formed on a substrate, a barrier layer formed on the buffer layer, the barrier layer including aluminum (Al), nitrogen (N), and at least one of indium (In) and gallium (Ga), a cap layer formed on the barrier layer, the cap layer including nitrogen (N) and at least one of indium (In) and gallium (Ga), and a gate formed on the cap layer, the gate being directly coupled with the cap layer. Other embodiments may also be described and/or claimed.

Gan-on-si switch devices

A low leakage current switch device ( 110 ) is provided which includes a GaN-on-Si substrate ( 11, 13 ) with one or more device mesas ( 41 ) in which isolation regions ( 92, 93 ) are formed using an implant mask ( 81 ) to implant ions ( 91 ) into an upper portion of the mesa sidewalls and the peripheral region around each elevated surface of the mesa structures exposed by the implant mask, thereby preventing the subsequently formed gate electrode ( 111 ) from contacting the peripheral edge and sidewalls of the mesa structures.

FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING THE SAME, AND ELECTRONIC DEVICE

The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer , a channel layer , a barrier layer , and a spacer layer is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer , the channel layer having a compressive strain, and the barrier layer having a tensile strain, and the spacer layer having a compressive strain are laminated on a substrate in this order. The gate insulating film is arranged on the spacer layer . The gate electrode is arranged on the gate insulating film . The source electrode and the drain electrode are electrically connected to the channel layer directly or via another component. 1. A field effect transistor comprising:a substrate;a buffer layer;a channel layer;a barrier layer;a spacer layer;a gate insulating film;a gate electrode;a source electrode; anda drain electrode, wherein{'sub': x', '1-x, 'the buffer layer is formed of lattice-relaxed AlGaN (0 Подробнее

Semiconductor device

A semiconductor device includes a nitride semiconductor stack having at least two hetero junction bodies where a first nitride semiconductor layer and a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer are disposed, and includes a drain electrode and, a source electrode disposed to the nitride semiconductor stack, and gate electrodes at a position put between the drain electrode and the source electrode and disposed so as to oppose them respectively in which the drain electrode and the source electrode are disposed over the surface or on the lateral side of the nitride semiconductor stack, and the gate electrode has a first gate electrode disposed in the direction of the depth of the nitride semiconductor stack and a second gate electrode disposed in the direction of the depth of the nitride semiconductor at a depth different from the first gate electrode.

Active Area Shaping for III-Nitride Devices

A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same. 120-. (canceled)21. A III-nitride semiconductor device comprising:a first III-nitride body having one band gap, and a second III-nitride body having another band gap disposed over said first III-nitride body; 'a gate well having a first mouth defined in said first insulation body, and a second mouth defined in said second insulation body, said second mouth being wider than said first mouth;', 'a first insulation body situated over said second III-nitride body, and a second insulation body situated over said first insulation body;'}a gate arrangement disposed at least partially within said gate well, said gate arrangement including a gate dielectric formed along said first mouth and said second mouth in said gate well, and a gate electrode over said gate dielectric, said gate arrangement filling said gate well.22. The III-nitride semiconductor device of claim 21 , further comprising a drain electrode and a source electrode on respective sides of said gate arrangement.23. The III-nitride semiconductor device of claim 21 , wherein said first insulation body comprises silicon nitride.24. The III-nitride semiconductor device of claim 21 , wherein said second insulation body comprises a nitride dielectric.25. The III-nitride semiconductor device of claim 21 , wherein said second insulation body comprises silicon nitride.26. The III-nitride semiconductor device of claim 21 , wherein said second insulation body comprises aluminum nitride.27. The III-nitride semiconductor device of claim 21 , wherein said second insulation body comprises titanium nitride.28. The III-nitride semiconductor device of claim 21 , wherein said first III-nitride body comprises GaN and said second III-nitride body comprises AlGaN.29. A method of fabricating a III-nitride semiconductor device ...

DIODE

A diode includes: a semiconductor layer stack; cathode and anode electrodes formed on the semiconductor layer stack so as to be spaced apart from each other; and a protection film covering a region of an upper surface of the semiconductor layer stack. The semiconductor layer stack includes a first nitride semiconductor layer, and a second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer, and has a channel. The anode electrode includes: a p-type third nitride semiconductor layer formed on the semiconductor layer stack; a first metal layer being in ohmic contact with the third nitride semiconductor layer; and a second metal layer being in contact with the first metal layer, and being in ohmic contact with the channel. 1. A diode comprising:a semiconductor layer stack formed on a principal surface of a substrate, including a first nitride semiconductor layer, and a second nitride semiconductor layer which is formed on the first nitride semiconductor layer, and has a larger band gap than the first nitride semiconductor layer, and having a channel through which electrons travel in a direction parallel to the principal surface of the substrate;cathode and anode electrodes formed on the semiconductor layer stack so as to be spaced apart from each other; anda protection film covering a region of an upper surface of the semiconductor layer stack between the cathode and anode electrodes, wherein a p-type third nitride semiconductor layer formed on the semiconductor layer stack;', 'a first metal layer formed on the third nitride semiconductor layer, and being in ohmic contact with the third nitride semiconductor layer; and', 'a second metal layer being in contact with the first metal layer, being opposite to the cathode electrode with respect to the third nitride semiconductor layer, and being in ohmic contact with the channel., 'the anode electrode includes2. The diode of claim 1 , whereinthe first nitride semiconductor layer ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

The present invention discloses a semiconductor device, comprising: a substrate, an insulating isolation layer formed on the substrate, a first active region layer and a second active region layer formed in the insulating isolation layer, characterized in that the carrier mobility of the first active region layer and/or second active region layer is higher than that of the substrate. In accordance with the semiconductor device and the manufacturing method thereof in the present invention, an active region formed of a material different from that of the substrate is used, the carrier mobility in the channel region is enhanced, thereby the device response speed is substantially improved and the device performance is enhanced greatly. Furthermore, unlike the existing STI manufacturing process, for the present invention, an STI is formed first, and then filling is performed to form an active region, thus avoiding the problem of generation of holes in STI, and improving the device reliability. 1. A semiconductor device , comprising: a substrate , an insulating isolation layer formed on the substrate , a first active region layer and a second active region layer formed in the insulating isolation layer , characterized in that the carrier mobility of the first active region layer and/or second active region layer is higher than that of the substrate.2. The semiconductor device according to claim 1 , wherein the hole mobility of the first active region layer is higher than that of the substrate claim 1 , and the electron mobility of the second active region layer is higher than that of the substrate.3. The semiconductor device according to claim 2 , wherein the substrate is formed of silicon claim 2 , the first active region layer is formed of Ge claim 2 , and the second active region layer is formed of InSb.4. The semiconductor device according to claim 3 , wherein a buffer layer formed of GaAs or GaN exists between the second active region layer and the substrate.5. The ...

Gallium Nitride Semiconductor Devices and Method Making Thereof

The present disclosure relates to an enhancement mode gallium nitride (GaN) transistor device. The GaN transistor device has an electron supply layer located on top of a GaN layer. An etch stop layer (e.g., AlN) is disposed above the electron supply layer. A gate structure is formed on top of the etch stop layer, such that the bottom surface of the gate structure is located vertically above the etch stop layer. The position of etch stop layer in the GaN transistor device stack allows it to both enhance gate definition during processing (e.g., selective etching of the gate structure located on top of the AlN layer) and to act as a gate insulator that reduces gate leakage of the GaN transistor device.

SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING THE SAME

An embodiment of a method for manufacturing a semiconductor wafer includes providing a monocrystalline silicon wafer, epitaxially growing a first layer of a first material on the silicon wafer, and epitaxially growing a second layer of a second material on the first layer. For example, said first material may be monocrystalline silicon carbide, and said second material may be monocrystalline silicon. 18-. (canceled)9. A semiconductor wafer , comprising:a substrate of monocrystalline silicon;a layer of a material other than monocrystalline silicon disposed over the substrate; anda layer of monocrystalline silicon disposed over the layer of the material.10. The semiconductor wafer of wherein at least one of the substrate claim 9 , the layer of material claim 9 , and the layer of monocrystalline silicon includes a dopant.11. The semiconductor wafer of wherein one of the substrate claim 9 , the layer of material claim 9 , and the layer of monocrystalline silicon is bowed.12. The semiconductor wafer of wherein one of the substrate claim 9 , the layer of material claim 9 , and the layer of monocrystalline silicon has a bow in a range of approximately 20-30 μm.13. The semiconductor wafer of wherein the layer of the material has a thickness in a range of approximately 2-6 μm.14. The semiconductor wafer of wherein the material includes silicon carbide.15. The semiconductor wafer of wherein the material includes monocrystalline silicon carbide.16. The semiconductor wafer of wherein the material includes 3C silicon carbide.17. The semiconductor wafer of wherein the material includes gallium nitride.18. The semiconductor wafer of wherein the layer of monocrystalline silicon has a thickness in a range of approximately 1-3 μm.19. An integrated circuit claim 9 , comprising:a substrate of monocrystalline silicon;a layer of a material other than monocrystalline silicon disposed over the substrate;a layer of monocrystalline silicon disposed over the layer of the material; anda device ...

Termination Structure for Gallium Nitride Schottky Diode

A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.

NITRIDE-BASED HETEROJUCTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACUTRING THE SAME

Disclosed is a semiconductor device. More specifically, disclosed are a nitride-based heterojunction semiconductor device and a method for manufacturing the same. The nitride-based heterojunction semiconductor device includes a first drain electrode, a conductive semiconductor layer including a nitride-based semiconductor disposed on the first drain electrode, a channel layer disposed on the conductive semiconductor layer, a barrier layer disposed on the channel layer, a source electrode and a second drain electrode spaced from each other on the barrier layer, and a gate electrode disposed between the source electrode and the second drain electrode. 1. A nitride-based heterojunction semiconductor device comprising:a first drain electrode;a conductive semiconductor layer comprising a nitride-based semiconductor disposed on the first drain electrode;a channel layer disposed on the conductive semiconductor layer;a barrier layer disposed on the channel layer;a source electrode and a second drain electrode spaced from each other on the barrier layer; anda gate electrode disposed between the source electrode and the second drain electrode.2. The nitride-based heterojunction semiconductor device according to claim 1 , further comprising:a current barrier layer disposed between the conductive semiconductor layer and the channel layer,wherein the current barrier layer has an opening at least at the side of the second drain electrode.3. The nitride-based heterojunction semiconductor device according to claim 2 , wherein the current barrier layer is disposed at least at a lower side of the gate electrode.4. The nitride-based heterojunction semiconductor device according to claim 2 , wherein the current barrier layer extends from a lower side of the source electrode to the lower side of the gate electrode.5. The nitride-based heterojunction semiconductor device according to claim 1 , wherein the current barrier layer comprises high-resistance gallium nitride.6. The nitride- ...

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A nitride-based semiconductor light-emitting device includes a GaN substrate , of which the principal surface is an m-plane , a semiconductor multilayer structure that has been formed on the m-plane of the GaN-based substrate , and an electrode arranged on the semiconductor multilayer structure . The electrode includes an Mg layer , which contacts with the surface of a p-type semiconductor region in the semiconductor multilayer structure 1. A nitride-based semiconductor device comprising:a nitride-based semiconductor multilayer structure including a p-type semiconductor region, a surface of the p-type semiconductor region being an m-plane; andan electrode that is arranged on the p-type semiconductor region; wherein{'sub': x', 'y', 'z, 'the p-type semiconductor region is made of an AlInGaN semiconductor (where x+y+z=1, x≧0, y≧0, z>0);'}the electrode comprises a Mg layer, a metal alloy layer, and a metal layer;the Mg layer is in contact with the p-type semiconductor region;the Mg layer consists of magnesium, gallium, and nitride;the Mg layer is covered with the metal alloy layer;the Mg layer is made up of islands of Mg portions that are present on a surface of the p-type semiconductor region;the metal layer is made of at least one metal that would make an alloy with Mg less easily than Au;the metal alloy layer consists of magnesium and the same metal as the metal of the metal layer; anda concentration of gallium included in the Mg layer is greater than a concentration of nitride included in the Mg layer.2. The nitride-based semiconductor device according to claim 1 , whereinthe metal alloy layer is made up of islands of Mg-alloy portions each covering at least one of the island of Mg portions.3. The nitride-based semiconductor device according to claim 1 , whereina portion of the metal alloy layer is in contact with the p-type semiconductor region.4. The nitride-based semiconductor device according to claim 1 , whereina portion of the metal layer is in contact with ...

METHOD FOR TESTING GROUP III-NITRIDE WAFERS AND GROUP III-NITRIDE WAFERS WITH TEST DATA

The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control. 1. A certified Group III-nitride wafer comprising (i) a documentation of a value of a physical property in combination with (ii) a wafer from a first set of Group III-nitride substrates cut from an ingot formed using a seed material , wherein the value of the physical property is derived by a method comprisinga) selecting substrates from the first set of substrates to form a second set of substrates, the second set of substrates being a subset of the first set and therefore being a selection of substrates from the first set of substrates that does not include all members from the first set of substrates, the second set of substrates having at least one substrate selected from the substrates cut from a portion of the ingot located on one side of a seed used to form the ingot, and the second set of substrates having at least one substrate selected from the substrates cut from a second portion of the ingot located on the other side of the seed,b) analyzing samples taken from the substrates of the second set to assess values of a first property of each of the substrates of the second set, i) applying said correlation to substrates not in said second set of substrates to provide estimated values of said first property for said substrates; or', 'ii) comparing said correlation against a value of said property for ...

Large area nitride crystal and method for making it

Techniques for processing materials in supercritical fluids including processing in a capsule disposed within a high-pressure apparatus enclosure are disclosed. The disclosed techniques are useful for growing crystals of GaN, AlN, InN, and their alloys, including InGaN, AlGaN, and AlInGaN for the manufacture of bulk or patterned substrates, which in turn can be used to make optoelectronic devices, lasers, light emitting diodes, solar cells, photoelectrochemical water splitting and hydrogen generation devices, photodetectors, integrated circuits, and transistors.

DEVICE STRUCTURE INCLUDING HIGH-THERMAL-CONDUCTIVITY SUBSTRATE

Methods and apparatuses for forming a device structure including a high-thermal-conductivity substrate are disclosed herein. A method forming such a device structure may comprise forming an active layer over a first substrate in a manner such that a frontside of the active layer faces the first substrate and a backside of the active layer faces away from the first substrate, forming a second substrate over the backside of the active layer, and removing the first substrate to expose the frontside of the active layer. Other embodiments are described and claimed. 1. A method comprising: a first substrate;', 'an etch stop layer including aluminum gallium arsenide or indium gallium phosphide formed over the first substrate;', 'an inverted epitaxial structure formed over etch stop layer in a manner such that the etch stop layer is between the first substrate and the inverted epitaxial structure and such that a frontside of the inverted epitaxial structure faces the etch stop layer and a backside of the inverted epitaxial structure faces away from the etch stop layer; and', 'a bonding layer formed over the backside of the inverted epitaxial structure;, 'providing an apparatus includingafter providing the apparatus, forming a second substrate over the bonding layer such that the bonding layer is between the backside and the second substrate; andafter said forming the second substrate, removing the first substrate and the etch stop layer to expose the frontside of the inverted epitaxial structure.2. The method of claim 1 , wherein said forming the second substrate comprises forming a high thermal conductivity material over the oxide layer.3. The method of claim 2 , wherein the high thermal conductivity material comprises a material selected from polycrystalline silicon carbide claim 2 , diamond claim 2 , or aluminum nitride.4. The method of claim 1 , wherein said forming of the second substrate over the oxide layer comprises wafer bonding the second substrate to the oxide ...

Aluminum gallium nitride etch stop layer for gallium nitride bases devices

A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, and a first metallic structure electrically coupled to the second surface of the III-nitride substrate. The semiconductor structure further includes an AlGaN epitaxial layer coupled to the III-nitride epitaxial layer of the first conductivity type, and a III-nitride epitaxial structure of a second conductivity type coupled to the AlGaN epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.

Edge Termination by Ion Implantation in GaN

An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure.

Manufacturable Enhancement-Mode Group III-N HEMT with a Reverse Polarization Cap

An enhancement-mode group III-N high electron mobility transistor (HEMT) with a reverse polarization cap is formed in a method that utilizes a reverse polarization cap structure, such as an InGaN cap structure, to deplete the two-dimensional electron gas (2DEG) and form a normally off device, and a spacer layer that lies below the reverse polarization cap structure and above the barrier layer of the HEMT which allows the reverse polarization cap layer to be etched without etching into the barrier layer.

P-Type Amorphous GaNAs Alloy as Low Resistant Ohmic Contact to P-Type Group III-Nitride Semiconductors

A new composition of matter is described, amorphous GaNAs:Mg, wherein 0 Подробнее

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A nitride semiconductor layer formed from a nitride semiconductor is provided on at least one surface side of a semiconductor substrate. Impurity regions (a source region, a drain region, and the like) are provided on one surface side in the nitride semiconductor layer and contain an impurity of a first conductivity type. In addition, amorphous regions (a first amorphous region and a second amorphous region) are a part of the impurity regions and are located in a surface layer of the impurity regions. In addition, metallic layers (a source electrode and a drain electrode) come into contact with the amorphous regions (the first amorphous region and the second amorphous region). 1. A semiconductor device , comprising:a semiconductor substrate that includes a nitride semiconductor layer formed from a nitride semiconductor on at least one surface side;an impurity region that is provided on the one surface side in the nitride semiconductor layer and contains a first conductivity type impurity;an amorphous region that is a part of the impurity region and is located in a surface layer of the impurity region; anda metallic layer that comes into contact with the amorphous region.2. The semiconductor device according to claim 1 ,wherein the amorphous region includes a crystal defect that is formed by ion implantation of the impurity.3. The semiconductor device according to claim 1 ,wherein the amorphous region and the metallic layer come into ohmic contact with each other.4. The semiconductor device according to claim 1 ,wherein the amorphous region includes a microcrystalline region in which a grain size is equal to or less than 10 nm.5. The semiconductor device according to claim 1 , further comprising:a source region that is provided in the nitride semiconductor layer and is a first of the impurity region;a drain region that is provided in the nitride semiconductor layer to be spaced apart from the source region in a plan view and that is a second of the impurity region;a ...

Low voltage diode with reduced parasitic resistance and method for fabricating

A method of making a diode begins by depositing an Al x Ga 1-x N nucleation layer on a SiC substrate, then depositing an n+ GaN buffer layer, an n− GaN layer, an Al x Ga 1-x N barrier layer, and an SiO 2 dielectric layer. A portion of the dielectric layer is removed and a Schottky metal deposited in the void. The dielectric layer is affixed to the support layer with a metal bonding layer using an Au—Sn utectic wafer bonding process, the substrate is removed using reactive ion etching to expose the n+ layer, selected portions of the n+, n−, and barrier layers are removed to form a mesa diode structure on the dielectric layer over the Schottky metal; and an ohmic contact is deposited on the n+ layer.

Gallium Nitride Devices with Vias

Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others. 127-. (canceled)2842-. (canceled)43. A transistor comprising a source electrode , a drain electrode and a gate electrode , said transistor further comprising:a substrate;a transition layer situated over said substrate;a gallium nitride layer situated over said transition layer;a via that extends through at least a portion of said substrate;a barrier layer along sidewalls of said via;an electrically conductive layer on a back surface of said substrate.44. The transistor of claim 43 , wherein said substrate comprises silicon.45. The transistor of claim 43 , wherein said electrically conductive layer comprises aluminum.46. The transistor of claim 43 , wherein said electrically conductive layer includes a first portion comprising gold and a second portion comprising aluminum.47. The transistor of further comprising a passivating layer situated over said gallium nitride layer.48. The transistor of claim 43 , wherein said gate electrode is defined by an electrode-defining layer comprising silicon nitride.49. The transistor of ...

III-V SEMICONDUCTOR STRUCTURES AND METHODS FOR FORMING THE SAME

Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation. 1. An indium gallium nitride (InGaN) layer , comprising:a first InGaN sublayer; andat least a second InGaN sublayer disposed over the first InGaN sublayer;wherein a total thickness of the InGaN layer equals a sum of a thickness of the first InGaN sublayer and a thickness of the at least a second InGaN sublayer, the total thickness of the InGaN layer being greater than a critical thickness of the first InGaN sublayer and less than a critical thickness of the at least a second InGaN sublayer.2. The InGaN layer of claim 1 , wherein a concentration of indium in the first InGaN sublayer is at least substantially equal to a concentration of indium in the at least a second InGaN sublayer.3. The InGaN layer of claim 1 , wherein a concentration of indium in the InGaN layer is at least substantially constant across the total thickness of the InGaN layer.4. The InGaN layer of claim 1 , wherein the InGaN layer is at least substantially free of strain relaxation.5. The InGaN layer of claim 1 , wherein the InGaN layer has an indium concentration of at least about 5% and a total thickness of at least about 200 nm.6. The InGaN layer of claim 1 , wherein the InGaN layer has a concentration of indium of at least about 8% and a total thickness of at least about 150 nm.7. An indium gallium nitride (InGaN) layer claim 1 , comprising:a first InGaN sublayer having a thickness less than or equal to a critical thickness of ...

Semiconductor Device with Multiple Space-Charge Control Electrodes

A circuit including a semiconductor device having a set of space-charge control electrodes is provided. The set of space-charge control electrodes is located between a first terminal, such as a gate or a cathode, and a second terminal, such as a drain or an anode, of the device. The circuit includes a biasing network, which supplies an individual bias voltage to each of the set of space-charge control electrodes. The bias voltage for each space-charge control electrode can be: selected based on the bias voltages of each of the terminals and a location of the space-charge control electrode relative to the terminals and/or configured to deplete a region of the channel under the corresponding space-charge control electrode at an operating voltage applied to the second terminal.

Metallization structure for high power microelectronic devices

A semiconductor device structure is disclosed that includes a wide-bandgap semiconductor portion selected from the group consisting of silicon carbide and the Group III nitrides. An interconnect structure is made to the semiconductor portion, and the interconnect structure includes at least two diffusion barrier layers alternating with two respective high electrical conductivity layers. The diffusion barrier layers have a coefficient of thermal expansion different from and lower than the coefficient of thermal expansion of the high electrical conductivity layers. The difference in the respective coefficients of thermal expansions are large enough to constrain the expansion of the high conductivity layers but less than a difference that would create a strain between adjacent layers that would exceed the bond strength between the layers. 1. A semiconductor device structure comprising:a wide-bandgap semiconductor portion selected from the group consisting of silicon carbide and Group III nitrides; a first diffusion barrier layer on a surface of a portion of the semiconductor device structure selected from the group consisting of said wide-bandgap semiconductor portion, an ohmic contact, a Schottky contact, and a dielectric layer;', 'a first high electrical conductivity layer on a surface of the first diffusion barrier layer opposite the portion of the semiconductor device structure;', 'a second diffusion barrier layer on a surface of the first high electrical conductivity layer opposite the first diffusion barrier layer; and', 'a second high electrical conductivity layer on a surface of the second diffusion barrier layer opposite the first high electrical conductivity layer, wherein each of the conductivity layers has a thickness greater than 800 Angstroms;, 'an interconnect structure to said wide-bandgap semiconductor portion, said interconnect structure comprising a plurality of diffusion barrier layers alternating with a plurality of high electrical conductivity ...

Method for forming gallium nitride devices with conductive regions

Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.

EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT, PN JUNCTION DIODE, AND METHOD FOR MANUFACTURING AN EPITAXIAL SUBSTRATE FOR SEMICONDUCTOR ELEMENT

Provided is an epitaxial substrate for use in a semiconductor element, having excellent characteristics and capable of suitably suppressing diffusion of elements from a cap layer. An epitaxial substrate for use in a semiconductor element, in which a group of group-III nitride layers are laminated on a base substrate such that a (0001) crystal plane of the group of group-III nitride layers is substantially in parallel with a substrate surface of the base substrate, includes: a channel layer made of a first group-III nitride having a composition of InAlGaN (x1+y1+z1=1, z1>0); a barrier layer made of a second group-III nitride having a composition of InAlN (x2+y2=1, x2>0, y2>0); an anti-diffusion layer made of AlN and having a thickness of 3 nm or more; and a cap layer made of a third group-III nitride having a composition of InAlGaN (x3+y3+z3=1, z3>0). 1. An epitaxial substrate for use in a semiconductor element , in which a group of group-III nitride layers are laminated on a base substrate such that a (0001) crystal plane of said group of group-III nitride layers is substantially in parallel with a substrate surface of said base substrate , said epitaxial substrate comprising:{'sub': x1', 'y1', 'z1, 'a channel layer made of a first group-III nitride having a composition of InAlGaN (x1+y1+z1=1, z1>0);'}{'sub': x2', 'y2, 'a barrier layer made of a second group-III nitride having a composition of InAlN (x2+y2=1, x2>0, y2>0);'}an anti-diffusion layer made of AlN and having a thickness of 3 nm or more; and{'sub': x3', 'y3', 'z3, 'a cap layer made of a third group-III nitride having a composition of InAlGaN (x3+y3+z3=1, z3>0).'}2. The epitaxial substrate according to claim 1 , whereina band gap of said second group-III nitride is larger than a band gap of said first group-III nitride.3. The epitaxial substrate according to claim 1 , wherein{'sub': x2', 'y2, 'said second group-III nitride is InAlN (x2+y2=1, 0.14≦x2≦0.24),'}{'sub': y3', 'z3, 'said third group-III nitride is ...

NITRIDE SEMICONDUCTOR DIODE

Disclosed is a high performance nitride semiconductor having a reverse leak current characteristic with two-dimensional electron gas as a conductive layer. A desired impurity is diffused into or a nitride semiconductor to which a desired impurity is added is re-grown on the bottom surface and the side face portion of a recessed portion formed by dry etching using chlorine gas on the upper surface of a nitride semiconductor stacked film to increase resistance of the side face portion of the nitride semiconductor stacked film contacting an anode electrode, reducing the reverse leak current. 1. A nitride semiconductor diode comprising:a substrate;a heterojunction stacked film on which a first nitride semiconductor layer formed on the substrate and a second nitride semiconductor layer greater in band gap energy than the first nitride semiconductor layer are stacked;a cathode electrode ohmically connected with the side face of the stacked film; andan anode electrode,wherein the stacked film is provided with a recessed portion which reaches the depth of a heterojunction surface being the interface of the first and second nitride semiconductor layers,wherein the recessed portion is provided with an region where at least one type of impurity selected from among a group of carbon (C), iron (Fe), zinc (Zn), and magnesium (Mg) is implanted, andwherein the anode electrode contacts the region and is Schottky connected with the stacked film.2. The nitride semiconductor diode according to claim 1 , wherein the region is formed by implanting the impurity into the stacked film itself or forming a film including the impurity.3. The nitride semiconductor diode according to claim 1 , wherein the region includes C or Fe with a density of 4×10cmor more or Mg with a density of 1×10cmor more.4. The nitride semiconductor diode according to claim 1 , wherein the density of the impurity in the region is higher than that of the impurity in the stacked film of the interface between the cathode ...