Methods of forming semiconductor elements using micro-abrasive particle stream

A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device.

Method and electrostatic transfer stamp for transferring semiconductor dice using electrostatic transfer printing techniques

A transfer stamp that can be charged with a spatial pattern of electrostatic charge for picking up selected semiconductor dice from a host substrate and transferring them to a target substrate. The stamp may be bulk charged and then selectively discharged using irradiation through a patterned mask. The technique may also be used to electrostatically transfer selected semiconductor dice from a host substrate to a target substrate.

Chip Pad Resistant to Antenna Effect and Method

A chip pad structure of an integrated circuit (IC) and the method of forming are disclosed. The chip pad comprises a main pad portion and a ring pad portion. During a charging process involved in forming the chip pad structure, electrical connections from the gate electrodes of MOS transistors in the IC substrate generally are made only to the ring pad portion that has an antenna-to-gate area ratio substantially below a predetermined antenna design rule ratio, and thus is resistant or immune to antenna effect. The main pad portion and the ring pad portion are coupled together through metal bridges formed in an upper interconnect metal layer or in the top conductive pad layer. The chip pad may be used as probe pads on a parametric testline or bonding pads on an IC.

Method to form solder deposits and non-melting bump structures on substrates

Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Power recovery circuit based on partial standing waves

A power recovery system includes a transmission line that is coupled to transfer an RF signal received via an antenna. The RF signal generates a partial standing wave in the transmission line and the transmission line has at least one standing wave anti-node. A power recovery circuit converts an anti-node signal from the at least one standing wave anti-node to a power signal.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core

A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.

Power semiconductor device and method therefor

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

Microelectronic elements with post-assembly planarization

A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.

Microelectronic elements with post-assembly planarization

A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.

Power semiconductor device and method therefor

A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.

Semiconductor component e.g. transistor, has electroplating area extending from circuit contact port on lateral surfaces, and insulation layer arranged between area and body comprising opening for connection of port with area

The component has a semiconductor body with two main surfaces and lateral surfaces connecting the main surfaces. A coupling area adjacent to one of the main surfaces comprises a circuit contact port (104a). An electroplating area extends from the port on the lateral surfaces. An insulation layer (110) arranged between the area and the body comprises an opening for connection of the port with the area. An independent claim is also included for a method of producing a semiconductor component.

Electronic component with flexible contacting pads and method for producing the electronic component

An electronic component has an electronic circuit and a rubber-elastic elevation. The rubber-elastic elevation is formed of an insulating rubber-elastic material disposed on a surface of the electronic component and has a conductive land on its crest. The rubber-elastic elevation also has on its sloping side or in its volume a conduction path between the land and the electronic circuit.

Metal paste with oxidation agents

The present invention relates to a sintering method which allows joining components in a stable manner, wherein the process temperature is below 200 °C and stable contact points occur which have a low porosity and a high electrical and thermal conductivity. The invention relates to a method for joining components, in which (a) a sandwich arrangement is provided, which comprises at least (a1) a component (1), (a2) a component (2) and (a3) a metal paste situated between component (1) and component (2), and in which (b) the sandwich arrangement is sintered. The invention is characterized in that the metal paste comprises (A) 75-90 % by weight of at least one metal, which is present in the form of particles having a coating, containing at least one organic compound; (B) 0-12 % by weight of at least one metal precursor; (C) 6-20 % by weight of at least one solvent; and (D) 0.1-15 % by weight of at least one auxiliary sintering agent which is selected from the group consisting of (i) organic peroxides, (ii) inorganic peroxides, and (iii) inorganic acids.

Method of forming a multi-layer semiconductor structure incorporating a processing handle member

A method of forming a multi-layer semiconductor structure includes attaching a handle-member to a top surface of a first structure using a first interface. At least one region of a bottom surface of the first structure is etched to form at least a first via-hole for exposing a portion of a first conductive member defined on the first structure. A conductive material is disposed in the first via-hole such that a first end of the conductive material is in electrical communication with the first conductive member and a second end of the conductive material is exposed at the bottom surface of the first structure. A second interface is disposed over at least the second end of the conductive material, which serves as a bonding and/or electrical interface between the first conductive member defined on the first structure and a second structure of the multi-layer semiconductor device structure.

Method for manufacturing semiconductor device and semiconductor device

Method for low temperature bonding and bonded structure

A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO 2 . The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

Copper bonding wire for semiconductor packaging

Provided is a copper bonding wire formed of a high purity copper of 99.999% or more including at least one of P and Nb within a range between 20 wt ppm and 100 wt ppm and at least one of Zr, Sn, Be, Nd, Sc, Ga, Fr, and Ra within a range between 1 wt ppm and 100 wt ppm. Here, a total content of the added elements is restricted within a range between 20 wt ppm and 200 wt ppm, and a residual amount of the copper bonding wire is a high purity copper of 99.98% or more. As a result, metal squeeze out and chip cratering can be reduced in a general semiconductor chip and a low dielectric semiconductor chip. Also, a short tail of the copper bonding wire occurring during bonding of the copper bonding wire to a lead finger can be reduced.

Semiconductor device and manufacturing method of the same

Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate.

晶片用双阶段底部填充胶

本发明公开了供施用至大晶片或集成电路芯片正面的100％非挥发性、单组分液态底部填充胶密封剂。涂覆后，通过暴露于尤其为UV、可见、红外光谱的辐射线，使密封剂转变为可液化、不发粘的固体。底部填充胶涂覆的晶片显示出出色的、长达数月的储存时效，而不会发生进一步固化。大晶片可被切分成小晶片区域并储存数月，之后在焊料回流过程中晶片连接被固定，且底部填充胶液化并流出而形成填角，并在热活化的交联下转变成热固性状态。

Adhesive Sheet and Method for Manufacturing the Same, Semiconductor Device Manufacturing Method and Semiconductor Device

An adhesive sheet comprising a release substrate 10 , a substrate film 14 , and a first tacky-adhesive layer 12 placed between the release substrate 10 and the substrate film 14 , wherein an annular incision D is formed on the release substrate 10 from the surface of the first tacky-adhesive layer 12 side, the first tacky-adhesive layer 12 is laminated so as to cover the whole inner surface of the incision D in the release substrate 10 , and the incision D has a depth d of less than the thickness of the release substrate 10 and 25 μm or less.

Method for gluing a component to a surface

By using a specially modified epoxide-based adhesive, surfaces can be glued both precisely and quickly to a component. The parts which are to be glued are precisely adjusted to the gluing area, fixed by UV light and subsequently thermally hardened.

Printed wiring board

A printed wiring board is provided by arranging a solder resist layer on the surface of a wiring board whereupon a conductor circuit is formed, forming as a conductor pad a part of the conductor circuit exposed from an opening section arranged on the solder resist layer, and by forming a solder bump on the conductor pad for mounting an electronic component. The connecting reliability and the insulating reliability are improved by permitting a rate (H/D) of a height (H) of the solder bump from the surface of the solder resist layer to the opening diameter (D) of the opening section to be 0.55-1.0, even in a narrow pitch structure where the pitch of the opening section arranged on the solder resist layer is 200μm or less.

Method for manufacturing a multilayer electronic component mounting substrate

패턴의 층간격을 줄이고, 또한 도통신뢰성이 우수한 미세 도통용 홀을 용이하게 형성할 수 있고, 또한, 에칭엑에 대한 내식성, 및 본딩와이어에 대한 접속신뢰성이 우수한 접속단자를 갖는 다층전자부품탑재용 기판의 제조 방법을 제공한다. For multi-layer electronic component mounting having a connection terminal which reduces the layer spacing of the pattern and can easily form a fine conductive hole excellent in conduction reliability, and also has excellent corrosion resistance for etching and connection reliability for bonding wires. Provided is a method of manufacturing a substrate.

Multilayer printed wiring board and method for manufacturing the same

본 발명은, 패턴층 사이의 거리를 짧게 하고, 우수한 접속 신뢰성을 가진 미세 도통용 홀의 형성을 용이하게 하는 다층 프린트 배선판의 제조 방법에 관한 것이다. 코어 패턴(12,13)을 포함하는, 패드(101,111)를 가진 코아 기판(21)을 먼저 준비한 다음, 상기 코어 기판 표면에, 절연층(22)을 적층하여 적층판을 형성한다. 그 다음, 상기 적층판 표면에 표면 패턴(11)을 형성한다. 상기 적층판에, 레이저 빔을 조사함으로써 도통용 홀을(30,31)을 형성한다. 도통용 홀(30,31) 저부의 개구부는, 패드(101,111)로 덮는다. This invention relates to the manufacturing method of the multilayer printed wiring board which shortens the distance between pattern layers, and makes formation of the hole for fine conduction which has the outstanding connection reliability easy. The core substrate 21 having the pads 101 and 111 including the core patterns 12 and 13 is first prepared, and then an insulating layer 22 is laminated on the surface of the core substrate to form a laminate. Next, a surface pattern 11 is formed on the surface of the laminate. The conductive plates 30 and 31 are formed by irradiating the laminated plate with a laser beam. The openings at the bottom of the conductive holes 30 and 31 are covered with the pads 101 and 111.

적층체 부착 반도체 웨이퍼의 제조방법 및 적층체 첩부방법

박리기재, 기재 필름, 및, 상기 박리기재와 상기 기재 필름과의 사이에 배치되는 점접착층을 구비하는 접착시트로부터 상기 박리기재를 박리하고, 상기 기재 필름 및 상기 점접착층으로부터 이루어지는 적층체를 얻는 박리공정과, 상기 적층체에 있어서 상기 점접착층을 반도체 웨이퍼에 첩부하는 첩부공정을 포함하고, 상기 박리기재에는, 상기 점접착층측의 면으로부터 절입부가 환상으로 형성되어 있고, 상기 점접착층은, 상기 박리기재에 있어서 상기 절입부의 내측의 면 전체를 덮도록 적층되어 있고, 상기 절입부의 칼자국 깊이는, 상기 박리기재의 두께 미만이며, 또한, 25㎛ 이하이고, 상기 반도체 웨이퍼로의 상기 적층체의 첩부를, 자동화된 공정으로 연속하여 행하는, 적층체 부착 반도체 웨이퍼의 제조방법. 반도체 웨이퍼

Method for contacting electrical contact surfaces of a substrate and device consisting of a substrate having electrical contact surfaces

본 발명은 기판(1)의 표면(20) 상에 전기적 콘택트면들(21, 112)을 접속하기 위한 방법과 관련된다. 상기 방법에 따라, 폴리이미드 또는 에폭시에 기반하는 막(3)이 진공에서 상기 콘택트면들을 포함하는 상기 표면을 완전히 덮고 그 표면에 부착되는 방법으로 상기 표면상으로 적층된다. 상기 막의 개별적인 개방 창(31)으로 인해 상기 표면상에서 접속되어질 각 콘택트면은 덮어지지 않으며, 각 덮어지지 않은 콘택트면과 금속층(4) 사이에 평면으로 콘택트가 형성된다. 본 발명에 따른 방법은 전력 반도체 칩들을 위한 넓은 면적의 콘택트를 형성하는데 사용되어, 고전류밀도를 가능하게 한다. The invention relates to a method for connecting electrical contact surfaces 21, 112 on the surface 20 of the substrate 1. According to the method, a film 3 based on polyimide or epoxy is deposited onto the surface in such a way that it completely covers and adheres to the surface comprising the contact surfaces in vacuum. The individual open windows 31 of the membranes do not cover each contact surface to be connected on the surface, and a contact is formed in a plane between each uncovered contact surface and the metal layer 4. The method according to the invention is used to form large area contacts for power semiconductor chips, enabling high current densities.

Flip-chip mounting resin composition and bump forming resin composition

차세대 LSI의 플립 칩 실장에 적용가능한, 생산성 및 신뢰성이 높은 플립 칩 실장에 적합한 플립 칩 실장용 수지 조성물은, 수지(13)가 가열되었을 때에 비등하는 대류 첨가제(12)를 함유하고 있다. 수지(13)가 가열되었을 때, 금속 입자가 수지 중에서 용융함과 아울러, 비등한 대류 첨가제(12)가 수지 속을 대류한다. The resin composition for flip chip mounting suitable for flip chip mounting with high productivity and reliability applicable to flip chip mounting of next generation LSI contains the convection additive 12 which boils when resin 13 is heated. When the resin 13 is heated, the metal particles melt in the resin, and the boiling convection additive 12 convex in the resin. 회로 기판(10)과 반도체 칩(20)의 사이에 공급된 수지(13)를 가열하고, 수지(13) 속에서 용융한 금속 입자가, 회로 기판(10)과 반도체 칩(20)의 단자(11, 21) 사이에 자기 집합함으로써, 단자 사이를 전기적으로 접속하는 접속체(22)를 형성하고, 그 후, 수지(13)를 경화시켜서, 반도체 칩(20)을 회로 기판(10)에 고정시킴으로써 플립 칩 실장체가 얻어진다. The metal particles melted in the resin 13 by heating the resin 13 supplied between the circuit board 10 and the semiconductor chip 20 form the terminals of the circuit board 10 and the semiconductor chip 20 ( By self-assembly between 11 and 21, the connection body 22 which electrically connects between terminals is formed, after that, resin 13 is hardened and the semiconductor chip 20 is fixed to the circuit board 10. FIG. By doing so, a flip chip mounting body is obtained.

晶片用双阶段底部填充胶

本发明公开了供施用至大晶片或集成电路芯片正面的100％非挥发性、单组分液态底部填充胶密封剂。涂覆后，通过暴露于尤其为UV、可见、红外光谱的辐射线，使密封剂转变为可液化、不发粘的固体。底部填充胶涂覆的晶片显示出出色的、长达数月的储存时效，而不会发生进一步固化。大晶片可被切分成小晶片区域并储存数月，之后在焊料回流过程中晶片连接被固定，且底部填充胶液化并流出而形成填角，并在热活化的交联下转变成热固性状态。

Method for building a component into a base and for setting up electric contact with component

FIELD: electric engineering. SUBSTANCE: in accordance to method, semiconductor components, forming a part of electronic circuit, or at least some of such components, are built into base, for example, electronic board during its manufacture. Therefore, structure of base is to a certain degree formed around the semiconductor component. In accordance to invention, at least one conductive pattern and apertures for semiconductor components are formed in the base. After that semiconductor components are placed in apertures, combining these with conductive pattern. Semiconductor components are connected to structure of base, in which one or more conductive patterns are made, so that at least one conductive pattern forms electric contact with contact areas on the surface of semiconductor component. EFFECT: increased reliability. 2 cl, 23 dwg ÐÎÑÑÈÉÑÊÀß ÔÅÄÅÐÀÖÈß RU (19) (11) 2 297 736 (13) C2 (51) ÌÏÊ H05K 1/18 (2006.01) ÔÅÄÅÐÀËÜÍÀß ÑËÓÆÁÀ ÏÎ ÈÍÒÅËËÅÊÒÓÀËÜÍÎÉ ÑÎÁÑÒÂÅÍÍÎÑÒÈ, ÏÀÒÅÍÒÀÌ È ÒÎÂÀÐÍÛÌ ÇÍÀÊÀÌ (12) ÎÏÈÑÀÍÈÅ ÈÇÎÁÐÅÒÅÍÈß Ê ÏÀÒÅÍÒÓ (21), (22) Çà âêà: 2004126137/09, 28.01.2003 (72) Àâòîð(û): ÒÓÎÌÈÍÅÍ Ðèñòî (FI) (24) Äàòà íà÷àëà îòñ÷åòà ñðîêà äåéñòâè ïàòåíòà: 28.01.2003 (73) Ïàòåíòîîáëàäàòåëü(è): ÈÌÁÅÐÀ ÝËÅÊÒÐÎÍÈÊÑ ÎÉ (FI) R U (30) Êîíâåíöèîííûé ïðèîðèòåò: 31.01.2002 FI 20020190 (43) Äàòà ïóáëèêàöèè çà âêè: 10.06.2005 (45) Îïóáëèêîâàíî: 20.04.2007 Áþë. ¹ 11 2 2 9 7 7 3 6 (56) Ñïèñîê äîêóìåíòîâ, öèòèðîâàííûõ â îò÷åòå î ïîèñêå: US 5306670 A, 26.04.1994. RU 13740 U1, 10.05.2000. RU 2133081 C1, 10.07.1999. RU 2126612 Ñ1, 20.02.1999. RU 2169962 Ñ2, 27.06.2001. US 3192307 A, 29.06.1965. WO 0021344 A1, 13.04.2000. US 4737446 A, 12.04.1988. US 5162144 A, 10.11.1992. (86) Çà âêà PCT: FI 03/00064 (28.01.2003) C 2 C 2 (85) Äàòà ïåðåâîäà çà âêè PCT íà íàöèîíàëüíóþ ôàçó: 31.08.2004 R U 2 2 9 7 7 3 6 (87) Ïóáëèêàöè PCT: WO 03/065778 (07.08.2003) Àäðåñ äë ïåðåïèñêè: 191186, Ñàíêò-Ïåòåðáóðã, à/ 230, "ÀÐÑÏÀÒÅÍÒ", ïàò.ïîâ. Â.Ì.Ðûáàêîâó, ðåã. ¹ 90 (54) ÑÏÎÑÎÁ ÂÑÒÐÀÈÂÀÍÈß ÊÎÌÏÎÍÅÍÒÀ  ...

Flip chip mounting resin composition and bump forming resin composition

次世代ＬＳＩのフリップチップ実装に適用可能な、生産性及び信頼性の高いフリップチップ実装に適したフリップチップ実装用樹脂組成物は、樹脂１３が加熱されたときに沸騰する対流添加剤１２を含有している。樹脂１３が加熱されたとき、金属粒子が樹脂中で溶融するとともに、沸騰した対流添加剤１２が樹脂中を対流する。回路基板１０と半導体チップ２０との間に供給された樹脂１３を加熱し、樹脂１３中で溶融した金属粒子が、回路基板１０と半導体チップ２０の端子１１、２１間に自己集合することによって、端子間を電気的に接続する接続体２２を形成し、その後、樹脂１３を硬化させて、半導体チップ２０を回路基板１０に固定させることによって、フリップチップ実装体が得られる。 A flip chip mounting resin composition suitable for flip chip mounting with high productivity and reliability applicable to next-generation LSI flip chip mounting contains a convection additive 12 that boils when the resin 13 is heated. is doing. When the resin 13 is heated, the metal particles melt in the resin, and the boiled convective additive 12 convects in the resin. By heating the resin 13 supplied between the circuit board 10 and the semiconductor chip 20, the metal particles melted in the resin 13 are self-assembled between the terminals 11 and 21 of the circuit board 10 and the semiconductor chip 20, A connection body 22 that electrically connects the terminals is formed, and then the resin 13 is cured, and the semiconductor chip 20 is fixed to the circuit board 10 to obtain a flip chip mounting body.

Bonding wire for semiconductor device

A very fine high purity copper wire for bonding a semiconductor device is made of a high purity copper cotaining 0-2ppm of S, 0-2ppm of Ag, 0-1ppm of Se and 0-1 or Te, with the total content of these and any other incidental impurities present being held at a level not exceeding 10ppm, with the balance being copper, and has an elongation of 5-22%, a breaking strength of 14-33Kg/mm2, and a vickers hardness of 38-50.

Copper bonding wire for semiconductor packaging

P 및 Nb 중의 적어도 어느 하나가 20-100 중량ppm으로 첨가된 99.999% 이상의 고순도 구리(Cu)에 Zr, Sn, Be，Nd, Sc, Ga, Fr 및 Ra 중의 적어도 어느 하나가 1-100 중량ppm의 범위로 첨가된 것으로, 첨가원소의 전체 함유량이 20-200 중량ppm으로 제한되고 잔여량은 99.98% 이상의 고순도 구리로 구성되는 구리 본딩 와이어를 개시한다. 이러한 구리 본딩 와이어는 일반적인 반도체 칩뿐만 아니라 저유전체 반도체 칩에서도 패드 밀림 및 칩 패임 현상을 감소시키고 리드 핑거와의 접합시 발생하는 구리 본딩 와이어의 길이 부족 현상을 감소시킨다.  At least one of Zr, Sn, Be, Nd, Sc, Ga, Fr, and Ra is 1-100 ppm by weight to 99.999% or more of high purity copper (Cu) in which at least one of P and Nb is added by 20-100 ppm by weight In addition, the present invention discloses a copper bonding wire in which the total content of added elements is limited to 20-200 ppm by weight and the remaining amount is composed of high purity copper of 99.98% or more. Such copper bonding wires reduce pad push and chip dents in low dielectric semiconductor chips as well as general semiconductor chips, and reduce the shortage of copper bonding wires generated when bonding the lead fingers.

Adhesive sheet and method for manufacturing the same, semiconductor device manufacturing method and semiconductor device

박리기재, 접착층, 점착층 및 기재 필름이 순차 적층된 구성을 갖는 접착시트로서, 상기 접착층은 소정의 제 1의 평면형상을 갖고, 또한, 상기 박리기재 위에 부분적으로 형성되어 있고, 상기 박리기재에는, 상기 제 1의 평면형상의 주변에 따라, 상기 접착층에 접하는 측의 면으로부터 제 1의 절입부가 형성되어 있고, 상기 제 1의 절입부의 칼자국 깊이는, 상기 박리기재의 두께 미만이며, 또한, 25㎛ 이하인 접착시트. An adhesive sheet having a configuration in which a peeling base material, an adhesive layer, an adhesive layer, and a base film are sequentially stacked, wherein the adhesive layer has a predetermined first planar shape and is formed partially on the peeling base material. And a first cutout portion is formed from a surface of the side in contact with the adhesive layer along the periphery of the first planar shape, and the cut depth of the first cutout portion is less than the thickness of the peeling substrate, and is 25 μm. The adhesive sheet which is below.

Process for producing chip and pressure sensitive adhessive sheet for said process

본 발명은 적어도 1층의 수축성 필름과 점착제층을 포함하는 점착시트에 다이싱할 물체를 결합하는 공정, 그 물체를 다이싱하여 칩으로 만드는 공정, 그리고 상기 수축성 필름을 수축시켜 칩과 점착제층의 접촉면적을 감소시키는 공정을 포함하는 칩의 제조방법에 관한 것으로, 이 방법을 사용하면 두께가 얇고 면적이 큰 칩을 제조하는 픽업공정에 있어서 트러스트 니들을 사용할 필요가 없이 쉽게 픽업이 가능하다. The present invention provides a process for bonding an object to be diced to an adhesive sheet including at least one layer of shrinkable film and an adhesive layer, dicing the object into chips, and shrinking the shrinkable film to form a chip and an adhesive layer. The present invention relates to a method for manufacturing a chip including a step of reducing the contact area, and this method makes it possible to easily pick up the pick-up process for manufacturing a chip having a small thickness and a large area without using a trust needle.

Chip scale ball grid array for integrated circuit package

본 발명은 반도체 다이와 기판 사이에 위치한 비중합체 층 또는 지지 구조물을 갖는 집적 회로 패키징용 칩 스케일 볼 그리드 어레이에 관한 것이다. 비중합체 지지 구조물은 열응력 효과를 감소시키고 및/또는 집적 회로 패키지 내에서 공극의 형성을 감소시키거나 제거함으로써 회로 신뢰성을 증가시키는 역할을 한다. 비중합체 지지 구조물은 구리 호일과 같이, 스트립 포맷에서 칩 스케일 패키지의 프로세싱이 가능한 충분한 강도를 갖는 재료일 수 있다. The present invention relates to a chip scale ball grid array for integrated circuit packaging having a non-polymeric layer or support structure positioned between a semiconductor die and a substrate. Non-polymeric support structures serve to increase thermal reliability by reducing thermal stress effects and / or reducing or eliminating the formation of voids in integrated circuit packages. The non-polymeric support structure may be a material with sufficient strength to allow processing of the chip scale package in strip format, such as copper foil.

Device and method for making devices comprising at least chip mounted on support

本发明涉及一种器件的制造方法,此器件包含与至少一个微电路芯片(6)(例如芯片卡)相连的底座(2)。本发明的特征是,该芯片或每个芯片的制造包括以下各步骤:首先,给上述芯片提供一个组件,该组件包含一个通过与衬底(8)结合第一表面(6b)支持的薄芯片(6),且在相反的第二表面(6a)上有至少一个焊接垫(12);在底座的一个表面(2a)上形成一个通信接口(4),该组件包含至少一个与上述芯片相连的连接元件(4b);然后依次将包括芯片(6)和衬底(8)构成的组件放在通信接口上,使得有至少一个芯片焊接垫(12)靠接在通信接口的相应连接元件(4b;24a;24b)上;将每个焊接垫与和它相应的连接元件连在一起;并将衬底(8)从芯片的第一表面(6b)去掉。这种方法能很方便地利用SOI芯片工艺。

Method for fabricating self-assembling microstructures

A method for assembling microstructures onto a substrate through fluid transport. The microstructures being shaped blocks self-align into recessed regions located on a substrate such that the microstructure becomes integral with the substrate 20, 70, 90, 120, 200. The improved method includes a step of transferring the shaped blocks into a fluid to create a slurry. Such slurry is then poured evenly over the top surface of a substrate having recessed regions thereon. The microstructure via the shape and fluid tumbles onto the surface of the substrate, self-aligns, and engages into a recessed region.

Process and integrated circuit connection support to another support by means of bumps

본 발명은 집적 회로(11)와 일측에서 도전체들(14)을 지지하고 타측에서 통과구멍(16)에 의해 각 도전체들에 접속된 볼들(15)을 지지하며 상기 구멍들에 직접 고정된 절연막(13)을 포함하는 접속 기판(12)을 갖는 집적회로(IC) 패키지(10)를 제공한다. 상기 구멍들의 기부는 각 도전체들에 의해 형성된다. 상기 볼들은 주석 납등의 재용융가능한 재료로 제조되며 먼저 점착성 물질에 의해 고정된다. 볼들(15)에 의해 2개의 접속 기판(12,22)을 연결하는 방법에 있어서, 상기 기판들중 하나는 일측에 도전체들이 제공되고, 타측에 통과 구멍들(16)이 제공된 막(13)을 포함하며, 상기 방법은 볼들을 재용융하여 상기 통과 구멍내에서 도전체들에 직접 볼들을 고정하는 단계로 구성된다. 그 볼들은 점착성 물질에 의해 접속 보드(22)의 접속 패드(23)에 납땜되거나 또는 미리 고정된다.

Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device

A semiconductor package has a semiconductor die with an optically active region which converts light to an electrical signal. An expansion region is formed around the semiconductor die. A through hole via (THV) is formed in the expansion region. Conductive material is deposited in the THV. A passivation layer is formed over the semiconductor die. The passivation layer allows for passage of light to the optically active region of the semiconductor die. A glass layer is applied to the passivation layer. A first RDL is electrically connected between the THV and a contact pad of the semiconductor die. Additional RDLs are formed on a front and back side of the semiconductor die. An under bump metallization (UBM) layer is formed over and electrically connected to the intermediate conduction layer. Solder material is deposited on the UBM and reflowed to form a solder bump.

Bonding integrated circuit chip and electric element assembly

(57)【要約】 【課題】 フラックス残留物を除去し、かつ充填部を形 成するための、比較的迅速で効率よい方法を実現可能 な、優れた集積回路結合技術を提供する。 【解決手段】 基板１０の基板表面１５上に設けられた コンタクトパッド２０は、ＩＣチップ１のコンタクトパ ッド１００と位置合わせされる。基板１０には、ＩＣチ ップ１が実装される実装領域４０内に孔３０が設けられ る。ＩＣチップ１のコンタクトパッド１００と基板１０ のコンタクトパッド２０との間には、相互接続結合部１ １０が形成され、素子アセンブリ１３０が形成される。 孔３０によって、低プロファイルギャップ１４０内にフ ラックス洗浄流体や充填用エポキシを良好に供給でき る。この孔３０は、約３００μｍ以下の高さを持つ低プ ロファイルギャップ１４０に対して好適である。

Method for fabricating self-assembling microstructures

一种通过液体传送将微结构组装到衬底上的方法。呈成型模块(19)的微结构自对准到位于衬底(50)上的凹槽区域(55)，使微结构变成与衬底结合起来。所改进的方法包括将成型模块移入液体形成一种悬浮物的步骤，然后将这种悬浮物均匀地倾倒在其上具有凹槽区域的衬底的顶面(53)的上方。通过成型和流体的作用微结构跌落到衬底的表面，自对准并接合到凹槽区域。

Chip manufacturing method and adhesive sheet for manufacturing the chip

본 발명은 적어도 1층의 수축성 필름과 점착제층으로 이루어지는 점착시트에 다이싱한 물체를 결합하는 공정, 그 물체를 다이싱하여 칩으로 만드는 공정, 그리고 상기 수축성 필름을 수축시켜 칩과 점착제의 면적을 감소시키는 공정을 포함하는 칩의 제조방법에 관한 것으로, 이 방법을 사용하면 두께가 얇고 면적이 큰 칩을 제조하는 픽업공정에 있어서 트러스트 니들을 사용할 필요가 없이 쉽게 픽업이 가능하다.

CONTACTLESS ELECTRONIC CARD AND MANUFACTURING METHOD THEREOF

La carte comporte un support isolant (1) qui supporte un enroulement (4) servant d'antenne et un circuit intégré (9) relié électriquement aux extrémités (7, 8) de l'enroulement. Selon l'invention le support (1) comporte, sur une face structurée (2), un logement (3) sur les parois et le fond duquel passent les spires de l'enroulement (4) qui sont formées par ailleurs sur la face structurée. Le logement (3) comporte aussi les extrémités (7, 8) de l'enroulement et contient le circuit intégré (9) qui est appliqué contre les spires. Le logement (3) est par ailleurs comblé avec une résine de protection (14) polymérisée, et une feuille en matériau isolant (15) couvre la face structurée (2) à laquelle elle est collée.Application à l'échange d'informations au moyen d'une carte électronique sans contacts. The card includes an insulating support (1) which supports a winding (4) serving as an antenna and an integrated circuit (9) electrically connected to the ends (7, 8) of the winding. According to the invention, the support (1) comprises, on a structured face (2), a housing (3) on the walls and the bottom of which pass the turns of the winding (4) which are also formed on the structured face. . The housing (3) also has the ends (7, 8) of the winding and contains the integrated circuit (9) which is applied against the turns. The housing (3) is also filled with a polymerized protective resin (14), and a sheet of insulating material (15) covers the structured face (2) to which it is bonded. by means of an electronic card without contacts.

Substrate for packaging a semiconductor device, packaging structure and method

내용 없음. No content.

Method of making semiconductor device leadframe and memory card

내용 없음. No content.

Method For Low Temperature Bonding And Bonded Structure

저온 또는 실온에서의 결합 방법은 세정 또는 에칭에 의한 표면 세정 및 활성화 단계를 포함한다. 상기 방법은 또한 계면 중합의 부산물을 제거하여 역 중합 반응을 방지함으로써, 실리콘, 질화규소 및 SiO 2 와 같은 재료를 실온에서 화학 결합시키는 단계를 포함할 수도 있다. 결합시킬 표면들은 고도의 평활도 및 평면도로 폴리싱한다(2). VSE 단계는 반응성 이온 에칭 또는 습식 에칭을 이용하여 결합시킬 표면들을 약하게 에칭시킬 수 있다(3). VSE 공정에 의해 표면 조도 및 평면도는 저하되지 않으며 높아질 수 있다. 에칭된 표면을 수산화암모늄 또는 플루오르화암모늄과 같은 용액에서 세정하여 표면 위의 원하는 결합 종의 형성을 촉진시킬 수 있다(4).

SEMICONDUCTOR UNIT PACKAGE, SEMICONDUCTOR UNIT PACKAGING METHOD, AND COMPACTING MATERIALS FOR USE IN PACKAGING SEMICONDUCTOR UNITS (FROM P-961658)

Electronic component with a plastic housing and method for production thereof

The invention relates to an electronic component, in which a semiconductor chip (3) is arranged, with a plastic housing (2) and method for production thereof. The lower side (6) of the plastic housing (2) comprises external contacts (7). The external contacts (7) are connected to contact surfaces (11) on the active upper side (12) of the semiconductor chip (3) by means of contact pegs (8) on the semiconductor chip (3) and by interconnecting lines (10) arranged on the plastic housing body (9). The contact pegs (8) thus represent an electrically-conducting projection of the contact surfaces (11).

Semiconductor device and manufacturing method thereof

Adhesive sheet, its manufacturing method, method for manufacturing semiconductor device and semiconductor device

本发明是粘接片及其制造方法、以及半导体装置的制造方法及半导体装置。本发明半导体装置制造方法包括：贴合步骤，对于依次层叠剥离基材、粘接层、粘着层及基材薄膜构成的、粘接层有规定的第1平面形状且部分性形成于剥离基材上、粘着层层叠为覆盖粘接层且于其周围与剥离基材接触的粘接片，剥下由粘接层、粘着层及基材薄膜所成的层叠体，隔着粘接层贴于半导体晶片，得到附层叠体半导体晶片；切割步骤，切割附层叠体半导体晶片，得到规定尺寸附层叠体半导体元件；剥离步骤，以高能量射线照射粘着层，使其粘着力降低后，剥离粘着层及基材薄膜，得到附粘接层半导体元件；粘接步骤，将附粘接层半导体元件，隔着粘接层粘接于半导体元件搭载用支持部件。

Process for contacting an electrical component, especially a semiconductor component, to a substrate comprises applying a connecting unit between the electrical component

Zur Kontaktierung eines elektrischen Bauelementes (2), insbesondere eines Halbleiterbauelementes, auf einem eine Leiterstruktur (3) aufweisenden Substrat (1) wird die Fügetemperatur derart gewählt, daß das Substrat (1) unter Ausübung eines Drucks auf das elektrische Bauelement (2) eine plastische Verformung erfährt, so daß das elektrische Bauelement zusammen mit der Leiterstruktur (3) formschlüssig in das Substrat (1) gedrückt wird. Zur Herstellung der Verbindung zwischen dem Bauelement und dem Substrat wird vorzugsweise eine dünne Diffusionslotschicht verwendet, die bei Temperaturen verarbeitet werden kann, die unter dem Schmelzpunkt des Substrates liegt.

Device for soldering contacts on semiconductor chips

According to the invention, a chip (4), maintained on a chip support (13) by means of a mandrel (1) is heated by a radiation source (12) on the side opposite to the wafer (2) so as to melt an input soldering metal applied on one side opposite to the wafer. A cleaning device (5) comprising a plate (6) provided with a slot (7), a gas channel (8) and a gas evacuation port (14) located proximate to the slot and designed for a forming gas is placed parallel to the wafer. The chip is moved vertically relative to the wafer, compressed on the wafer through the slot and soldered by isothermal solidification.

Method for contact-connecting an electrical component to a substrate having a conductor structure

For the purpose of contact-connecting an electrical component, in particular a semiconductor component, on a substrate having a conductor structure, a joining temperature is chosen in such a way that the substrate, with a pressure being exerted on the electrical component, experiences a plastic deformation, with the result that the electrical component is pressed together with the conductor structure into the substrate in a positively locking manner. In order to produce the connection between the component and the substrate, use is preferably made of a thin diffusion solder layer which can be processed at temperatures lying below the melting point of the substrate.

Device for soldering contacts on semiconductor chips

Vorrichtung zum Verlöten von Kontakten auf vertikal integrierten Halbleiterchips, bei der eine Spannvorrichtung (1), die dafür vorgesehen ist, einen Wafer (2) mit Bauelementen aufzunehmen und zu transportieren, eine Spülvorrichtung (5), eine Chiphalterung (13) und eine Heizung vorhanden sind, dadurch gekennzeichnet, dass – die Spülvorrichtung (5) eine Platte (6) mit einem Fenster (7), einem Gaskanal (8) und einer bei dem Fenster angeordneten Gasauslassöffnung (14) aufweist, wobei diese Platte parallel zu einer für den Wafer vorgesehenen Transportfläche der Spannvorrichtung (1) ausgerichtet ist und in dieser Lage über der Spannvorrichtung (1) gehalten wird, – die Chiphalterung (13) über der Spannvorrichtung (1) über dem Fenster (7) angeordnet ist, so dass ein Chip (4) auf einer der Spannvorrichtung (1) zugewandten Seite der Chiphalterung über einem Wafer (2) gehalten werden kann und mittels einer bezüglich des Wafers vertikalen Bewegung der Chiphalterung dem Wafer beliebig dicht angenähert werden kann, und... Device for soldering contacts on vertically integrated semiconductor chips, in which a clamping device (1) which is intended to receive and transport a wafer (2) with components, a flushing device (5), a chip holder (13) and heating is available characterized in that - The flushing device (5) has a plate (6) with a window (7), a gas channel (8) and a gas outlet opening (14) arranged at the window, this plate parallel to a transport surface of the clamping device (1 ) is aligned and held in this position above the tensioning device (1), - The chip holder (13) is arranged above the clamping device (1) above the window (7), so that a chip (4) can be held on a side of the chip holder facing the clamping device (1) above a wafer (2) and by means of a vertical movement of the chip holder with respect to the wafer can be approximated as closely as desired to the wafer, and ...

Device and method for soldering contacts on semiconductor chips

A device for soldering contacts on semiconductor chips. A chip is held on a chip mount by a chuck and is heated from a side facing away from the wafer by means of a radiation source, so that a solder applied to a side facing the wafer is melted. A flushing device, having a plate with a window, a gas channel, and a gas outlet opening for a forming gas, is arranged at the window, is fitted parallel to the wafer. The chip is moved vertically in relation to the wafer, pressed onto the wafer through the window, and soldered on by means of isothermal solidification.

METHOD AND JOINING MATERIAL FOR METALLICALLY CONNECTING COMPONENTS

Component and method for producing the component

The invention relates to a component and to a method for the production thereof. Said component is more particularly an electronic component with a micro electronic chip and a carrier which is produced by means of isothermal coagulation.

Connecting electronic component to substrate with several contact faces

Printed wiring board

導体回路を形成した配線基板に対し、その表面にソルダーレジスト層を設けると共に、そのソルダーレジスト層に設けた開口部から露出する前記導体回路の一部を導体パッドとして形成し、その導体パッド上に電子部品を実装するための半田バンプを形成してなるプリント配線板において、ソルダーレジスト層に設けた開口部のピッチが２００μｍ以下の挟ピッチ構造でも、半田バンプのソルダーレジスト層表面からの高さＨと開口部の開口径Ｄとの比（Ｈ／Ｄ）を０．５５〜１．０とすることで、接続信頼性および絶縁信頼性が向上する。 A solder resist layer is provided on the surface of the wiring board on which the conductor circuit is formed, and a part of the conductor circuit exposed from the opening provided in the solder resist layer is formed as a conductor pad, on the conductor pad. In a printed wiring board formed with solder bumps for mounting electronic components, the height H of the solder bumps from the surface of the solder resist layer, even if the pitch of the openings provided in the solder resist layer is 200 μm or less. Connection reliability and insulation reliability are improved by setting the ratio (H / D) of the opening diameter D of the opening to 0.55 to 1.0.

UV CURABLE ADHESIVE FOR A SEMICONDUCTOR CHIP ASSEMBLY PROCESS

Proposed for the assembly of semiconductor chips (31, 32...36) is an acrylate-based adhesive which can be cured rapidly by UV light and which gives an adhesive bond that is resistant to welding but can be readily removed with solvents after welding. Thus, during assembly, semiconductor chips can first be bonded on a temporary carrier (1) by means of the adhesive, it being possible to adjust the position of a chip before curing the adhesive. The definitive chip array is then welded in one step on to the component (5) and, finally, the carrier (1) removed with solvents.

Electronic circuit components

본 발명의 목적은 도금액중에서 미립자가 응집되지 않고, 효율적으로 모든 미립자에 균일한 두께의 도금층을 형성할 수 있는 도전성 미립자의 제조방법을 제공하는 것이다. An object of the present invention is to provide a method for producing conductive fine particles which can form a plating layer having a uniform thickness on all fine particles without aggregation of fine particles in a plating solution. 본 발명은 수직인 구동축의 상단부에 고정된 원반형상의 저판; 상기 저판의 외주상면에 배치되며, 도금액만을 통과시키는 다공체; 상기 다공체 상면에 배치된 통전용 접촉링; 상부중앙에 개구부를 갖는 원추사다리꼴형상 커버의 상단부에 개구직경과 동일한 구멍직경의 중공원통을 접합하며, 이 중공원통의 상단부가 중공원통 내벽측으로 되접어 꺽여 있는 중공커버; 상기 중공커버의 외주부와 상기 저판 사이에 상기 다공체와 상기 접촉링을 끼워 지지하여 형성된 회전가능한 처리실; 상기 개구부로부터 도금액을 상기 처리실로 공급하는 공급관; 상기 다공체의 구멍에서 비산한 도금액을 받는 용기; 상기 용기에 고인 도금액을 배출하는 배출관; 및 상기 개구부로부터 삽입되어 도금액에 접촉하는 전극을 갖는 도전성 미립자의 제조장치이다. The present invention is a disk-shaped bottom plate fixed to the upper end of the vertical drive shaft; A porous body disposed on an outer circumferential upper surface of the bottom plate and configured to pass only a plating liquid; A contact ring for electricity disposed on the upper surface of the porous body; A hollow cover joined to a top end of a cone trapezoidal cover having an opening in an upper center thereof, the hollow park having a hole diameter equal to the opening diameter, and having an upper end folded back to the inner wall side of the hollow park; A rotatable processing chamber formed by sandwiching the porous body and the contact ring between an outer circumferential portion of the hollow cover and the bottom plate; A supply pipe for supplying a plating liquid from the opening to the processing chamber; A container receiving the plating liquid scattered from the hole of the porous body; A discharge pipe for discharging the plating liquid accumulated in the container; And an electrode inserted into the opening and contacting the plating liquid. 도전성 미립자, 이방성 도전접착제, 도전접속구조체, 전자회로부품 Conductive fine particles, anisotropic conductive adhesive, conductive connecting structure, electronic circuit parts

Package of integrated circuits and vertical integration

A first level packaging wafer is made of a semiconductor or insulating material. The bumps on the wafer are made using vertical integration technology, without solder or electroplating. More particularly, vias are etched part way into a first surface of the substrate. Metal is deposited into the vias. Then the substrate is blanket-etched from the back side until the metal is exposed and protrudes from the vias to form suitable bumps. Dicing methods and vertical integration methods are also provided. Solder or electroplating are used in some embodiments.

Chip and wafer integration process using vertical connections

A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

CSP semiconductor device, semiconductor circuitry, and method of fabricating the CSP semiconductor device

CSP-Halbleiterbaustein (100) mit folgenden Merkmalen: einem Halbleiterkörper (102) mit einer ersten und einer gegenüberliegenden zweiten Hauptoberfläche (102a, 102b) und mit die Hauptoberflächen verbindenden Seitenflächen (102c–f), einem Schaltungsbereich (104) in dem Halbleiterkörper (102) angrenzend an die erste Hauptoberfläche (102a), der einen ersten und zweiten Schaltungskontaktanschluss (104a, 104b) aufweist, einem ersten und zweiten Metallisierungsbereich (106; 106a–b; 106a–c; 106a–d), wobei sich der erste Metallisierungsbereich (106; 106a–b; 106a–c; 106a–d) von dem ersten Schaltungskontaktanschluss (104a) auf der ersten Hauptoberfläche (102a) auf eine erste Seitenfläche des Halbleiterkörpers (102) erstreckt, um an der ersten Seitenfläche des Halbleiterkörpers (102) einen ersten frei liegenden Kontaktierungsbereich (108; 108a–b; 108a–c; 108a–d) bereitzustellen, und wobei sich der zweite Metallisierungsbereich (106; 106a–b; 106a–c; 106a–d) von dem zweiten Schaltungskontaktanschluss (104b) auf der ersten Hauptoberfläche (102a) auf eine zweite Seitenfläche des Halbleiterkörpers (102) erstreckt, um an der zweiten Seitenfläche des Halbleiterkörpers (102) einen zweiten frei liegenden Kontaktierungsbereich (108; 108a–b; 108a–c; 108a–d) bereitzustellen,...

Semiconductor device and method for producing same

The semiconductor device includes a semiconductor body having a first and an opposite second main surface and side faces connecting the main surfaces, a circuit region in the semiconductor body adjacent to the first main surface, having a circuit contact terminal, a metallization region extending from the circuit contact terminal on the first main surface onto a side face of the semiconductor body to provide an exposed contacting region on the side face of the semiconductor body, and an insulation layer arranged between the metallization region and the semiconductor body, the insulation layer having an opening for electrically connecting the circuit contact terminal to the metallization region.

Semiconductor device and method for producing same

The semiconductor device includes a semiconductor body having a first and an opposite second main surface and side faces connecting the main surfaces, a circuit region in the semiconductor body adjacent to the first main surface, having a circuit contact terminal, a metallization region extending from the circuit contact terminal on the first main surface onto a side face of the semiconductor body to provide an exposed contacting region on the side face of the semiconductor body, and an insulation layer arranged between the metallization region and the semiconductor body, the insulation layer having an opening for electrically connecting the circuit contact terminal to the metallization region.

Method of housing components and housed component

Verfahren zum Gehäusen von Bauelementen, wobei ein Basissubstrat (100) an seiner Funktionsseite (101) eine Vielzahl von voneinander beabstandeten Funktionsbereichen (110) aufweist und mit der Funktionsseite (101) mit einem Decksubstrat (200) im Waferverbund dauerhaft derart verbunden wird, dass die Funktionsbereiche (110) jeweils gehäust werden, wobei Kontaktflächen (130) auf dem Basissubstrat (100) von einer Rückseite (102) des Basissubstrats (100), welche der Funktionsseite (101) gegenüber liegt, mittels Erzeugen von Kontaktierungsausnehmungen (301) in dem Basissubstrat (100) freigelegt werden, wobei das Basissubstrat (100) in Rumpfbereiche (104) und Anschlussbereiche (300) unterteilt wird, wobei sich die Rumpfbereiche (104) jeweils über die Funktionsbereiche (110) erstrecken und einen Teil der Gehäuse für die Funktionsbereiche (110) bilden, wobei das Basissubstrat (100) in den Rumpfbereichen (104) oder den Anschlussbereichen (300) gedünnt wird, bis es in den Rumpfbereichen (104) und den Anschlussbereichen (300) unterschiedliche Dicken aufweist und wobei der zumindest aus Basissubstrat (100) und Decksubstrat (200) gebildete... Method for housing components, wherein a base substrate (100) on its functional side (101) has a plurality of spaced-apart functional areas (110) and the functional side (101) with a cover substrate (200) in the wafer composite permanently connected such that the functional areas (110) housed respectively become, wherein contact surfaces (130) on the base substrate (100) are exposed from a back side (102) of the base substrate (100) facing the functional side (101) by creating contact recesses (301) in the base substrate (100), wherein the base substrate (100) is divided into body regions (104) and connection regions (300), wherein the body regions (104) each extend over the functional regions (110) and form part of the housing for the functional regions (110), wherein the base substrate (100) in the body regions (104) or the connection ...

Component and method for prodn. thereof

制造一种在两个元件部分之间有连接层的元件的方法，其中：第一元件部分以其设有第一金属镀层的第一接触侧放在第二元件部分的设有第二金属镀层的第二接触侧上，两个金属镀层之一的外表面由低熔点组成部分构成，另一金属镀层的外表面由高熔点的组成部分构成；此元件在反应持续时间期间按预定的温度过程加热到反应温度，直到在两个金属镀层之间的等温凝固反应结束并构成连接层为止；接缝持续时间在反应持续时间的开始时开始，此接缝持续时间比反应持续时间短，以及，元件部分在接缝持续时间期间被施加静态压紧力；在两个元件部分上从接缝持续时间开始起至少在部分接缝持续时间内施加振动能量，在此期间至少使其中一个元件部分沿纵向和/或横向振动。

A substrate and method for connecting an integrated circuit to another substrate by balls

Integrated-circuit Attachment Structure With Solder Balls And Pins

一种集成电路附接结构包括集成电路和封装组件。该封装组件包括包含该集成电路的封装。该封装在其角落处具有管脚并且在其底面上具有至少主要是焊球的栅格。

Self-adhesive electronic circuit

An electronic circuit including a planar base having first and second base surfaces, an antenna attached on the first surface of the base, and a chip connected to the antenna, characterized in that a double faced adhesive is glued on one of the base surfaces, the double faced adhesive having an opening and the chip being arranged at least partially in the opening.

Noncontact information storage medium and method for manufacturing same

一种非接触型信息存储介质，包括：至少具有存储信息的功能的半导体IC芯片(30)，和形成有用于与外围设备进行信号的交换的天线方向图(14)的树脂基板(10)；其中，设置在树脂基板(10)上的天线方向图(14)的一个端部上的天线端子(141)与IC芯片(30)的电极端子(22)以相对的方式进行安装，并且在天线方向图(14)与IC芯片(30)的电路形成面(20)之间设置有至少5μm的间隙限制用绝缘层(32)。

Method for contacting a circuit chip

The invention relates to a method for contacting a circuit chip (2) which has at least two connection surfaces (8, 10) on a first main surface. According to said method, the circuit chip (2) is first placed on a main surface of a support substrate (4) by a second main surface which faces its first main surface, in such a way that the entire thickness of the circuit chip (2) protrudes beyond the surface of the support substrate (4). A structured metallic coating is then applied to the first main surface of the circuit chip (2) and the surface of the support substrate (4) by means of screen printing or stamping in order to connect the connection surfaces (8, 10) of the circuit chip (2) to a conductor structure (16) located on the main surface of the support substrate (4). Alternatively, the screen printing or stamping process is used to apply a structured metallic coating to the first main surface of the circuit chip (2) and the surface of the support substrate (4) in order to produce a peripheral conductor structure on the main surface of the support substrate and on the first main surface of the circuit chip (2), said conductor structure being connected to the connection surfaces of the circuit chip.

Method for forming a structured metallization on a semiconductor wafer

According to the inventive method for making a structured metallization (30) on a semiconductor wafer (20), consisting in applying a passivation layer onto the main surface of the wafer for the purpose of securing a bond pad (24), a metal hump (26) is formed on at least one bond pad (24). Then, in the passivation layer areas (22) where the structured metallization is to be effected, an activated dielectric is created (28). Therafter, metal is chemically precipitated on both the dielectric (28) and the metal hump (26), so that the structured metallization on the activated dielectric and the metal chemically precipitated on said metal hump are electroconductively connected.

Component and method of manufacturing the component

(57)【要約】 本発明は構成素子に関する。さらに本発明は、該構成素子、特にマイクロ電子チップとキャリヤとを備えた、等温凝固により製造された電子構成素子を製造するための方法に関する。

Wafer bonding of thinned electronic materials and circuits to high performance substrates

A method of bonding a wafer to a substrate comprising the steps of: providing a wafer having a front surface and a back surface; attaching the front surface of the wafer to a support; thinning the wafer from the back surface; bonding the back surface of the wafer to a substrate using a thin bonding technique; and removing the support from the front surface of the wafer. A circuit comprising: a substrate; and a wafer; wherein the wafer is at most about 50 microns thick; wherein the wafer has a front surface comprising features; and wherein the wafer has a back surface bonded to the substrate using a thin bonding technique.

Semiconductor device and preparation there of and bonding wire used there of

내용 없음. No content.

Method for metalizing blind vias

A method for metalizing at least one blind via formed in at least one substrate, including at least the following steps: a) arranging at least one solid portion of electrically conductive material in the blind via, b) performing a thermal treatment of the solid portion of electrically conductive material, making it melt in the blind via, c) cooling the electrically conductive material, solidifying it in the blind via, and wherein, before carrying out step a), at least part of the walls of the blind via is covered with a material able to prevent wetting of said part of the walls of the blind via by the melted electrically conductive material obtained during the performance of step b), the solidified electrically conductive material obtained after carrying out step c) being able not to be secured to said non-wetting part of the walls of the blind via.

Method for metalizing blind vias

A method for metalizing at least one blind via formed in at least one substrate, including: a) arranging at least one solid portion of electrically conductive material in the blind via, b) performing a thermal treatment of the solid portion of electrically conductive material, making it melt in the blind via, cooling the electrically conductive material, solidifying it in the blind via, and wherein, before carrying out step a), at least part of the walls of the blind via is covered with a material able to prevent wetting of said part of the walls of the blind via by the melted electrically conductive material obtained during the performance of step b), the solidified electrically conductive material obtained after carrying out step c) being able not to be secured to said non-wetting part of the walls of the blind via.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES

Connection terminal, semiconductor package using connection terminal, and method of manufacturing semiconductor package

The connection reliability of connecting terminals with displacement gold plating films is improved by connecting terminals comprising a conductive layer, an electroless nickel plating film, a first palladium plating film which is a displacement or electroless palladium plating film with a purity of 99% by mass or greater, a second palladium plating film which is an electroless palladium plating film with a purity of at least 90% by mass and less than 99% by mass, and a displacement gold plating film, wherein the electroless nickel plating film, the first palladium plating film, the second palladium plating film and the displacement gold plating film are laminated in that order on one side of the conductive layer, and the displacement gold plating film is situated on the uppermost surface layer on the opposite side from the conductive layer.

Semiconductor device and manufacturing method of the same

반도체 장치는 배리어 금속막으로서 기능하는 탄탈계 금속의 적어도 접속 부분과; 이 접속 부분과 접속되는 구리 매립 배선 간의 접속도가 향상되어 구리 매립 배선이 박리되는 것을 방지함에 따라 신뢰도가 향상된다. 층간 절연막의 매립 배선용으로 설계된 트렌치내에 200 내지 500 옴스트롱의 막 두께를 가진 탄탈막과; 1.1 내지 1.15 ㎛의 막 두께를 가진 구리 매립 배선이 형성된다. 이 구리 매립 배선은 0.08 내지 0.12 ㎛의 막 두께를 가진 구리 박막과 1.0 내지 1.5 ㎛의 막 두께를 가진 구리 후막을 함께 적층함으로써 형성된다. 더욱이 탄탈막과 구리 매립 배선 사이에는 약 수 옴스트롱의 두께를 가진 비정질 금속막이 형성된다. 또한, 탄탈막과 각각의 표면 보호막 및 층간 절연막 사이에 약 수 옴스트롱의 막 두께를 가진 탄탈막이 형성된다. The semiconductor device includes at least a connection portion of a tantalum metal serving as a barrier metal film; The connection degree between this connection part and the copper-embedded wiring connected is improved and reliability is improved by preventing peeling of a copper-embedded wiring. A tantalum film having a film thickness of 200 to 500 ohms strong in a trench designed for buried wiring of an interlayer insulating film; A copper buried wiring with a film thickness of 1.1 to 1.15 mu m is formed. This copper buried wiring is formed by laminating together a copper thin film having a film thickness of 0.08 to 0.12 mu m and a copper thick film having a film thickness of 1.0 to 1.5 mu m. Furthermore, an amorphous metal film having a thickness of about several ohms is formed between the tantalum film and the copper buried wiring. Further, a tantalum film having a film thickness of about several ohms is formed between the tantalum film and each of the surface protective film and the interlayer insulating film.

Method for metallizing blind vias

Method for mounting an integrated circuit on a support and resulting support

An array of conductors (14) is first etched onto a deposited layer and the free ends of each sector are fixed by ILB to terminals of the IC (11) directly by, for example, thermal compression or ultrasound or indirectly by solder balls or similar which raise up the input-output terminals of the IC. A force is used to separate the conductors from a passifying layer (20) and an insulating resin (21) is then deposited on each conductor or on a group or all conductors or all or part of the surface of the IC. Alternatively, an insulating spacer is fixed under the conductor outside the area of the IC.

Power semiconductor device

【課題】外部配線の接続により主端子部に発生する不良を低減でき、歩留まりが高く生産性に優れるともに、信頼性の高いトランスファーモールド樹脂により封止された電力用半導体装置を得ることである。 【解決手段】回路基板の配線パターンに接合された電力用半導体素子と筒状外部端子連通部と、電力用半導体素子と筒状外部端子連通部との間などを電気的に接続する配線成手段とが、トランスファーモールド樹脂で封止された電力用半導体装置であって、筒状外部端子連通部が、配線パターンに対して略垂直に設置され、外部端子を挿入接続可能であり、且つ各主回路である配線パターンに複数個が２次元に配置されたものである。 【選択図】図１

Methods for electronic fluorescent perturbation for analysis and electronic perturbation catalysis for synthesis

Methods for electronic perturbation of fluorescence, chemilluminescence and other emissive materials provide for molecular biological analysis. In a preferred method for hybridization analysis of a sample, an electronic stringency control device is used to perform the steps of: providing the sample, a first probe with a fluorescent label and a second probe with a label under hybridization conditions on the electronic stringency control device, forming a hybridization product, subjecting the hybridization product to an electric field force, monitoring the fluorescence from the hybridization product, and analyzing the fluorescent signal. The label preferably serves as a quencher for the fluorescent label. In yet another aspect of this invention, a method for achieving electronic fluorescence perturbation on an electronic stringency control device comprising the steps of: locating a first polynucleotide and a second polynucleotide adjacent the electronic stringency control device, the first polynucleotide and second polynucleotide being complementary over at least a portion of their lengths and forming a hybridization product, the hybridization product having an associated environmental sensitive emission label, subjecting the hybridization product and label to a varying electrophoretic force, monitoring the emission from the label, and analyzing the monitored emission to determine the electronic fluorescence perturbation effect. In yet another aspect of this invention, a method is provided for electronic perturbation catalysis of substrate molecules on an electronic control device containing at least one microlocation comprising the steps of: immobilizing on the microlocation an arrangement of one or more reactive groups, exposing the reactive groups to a solution containing the substrate molecules of interest, and applying an electronic pulsing sequence which causes charge separation between the reactive groups to produce a catalytic reaction on the substrate ...

Patterned array of uniform metal microbeads

The present invention provides a method for providing an array of metal microbeads on a substrate, preferably in a regular pattern of very fine, uniform size microspheres or microbeads at precise spacing or scale previously unachievable. The method of the present invention comprises the steps of providing a metal layer on a substrate that is partitioned into metal regions; heating the metal layer to a temperature sufficient to melt the metal and to permit beading of the layer into discrete microbeads.

Heat curable adhesive composition, article, semiconductor apparatus and method

반도체의 다이싱 및 다이싱된 반도체 칩의 다이 결합에 적합한 열 경화성 접착제 조성물 및 접착제 물품, 및 반도체 장치 및 상기 접착제 조성물 및 접착제 물품을 사용한 반도체 장치의 제조 방법이 제공된다. 한 실시태양에서, 본 발명은 카프로락톤 개질 에폭시 수지 및 점성 저하 성분을 포함하는 열 경화성 접착제 조성물을 제공한다. 본 발명의 다른 실시태양은 카프로락톤 개질 에폭시 수지 및 점성 저하 성분을 포함하는 열 경화성 접착제 조성물의 열 경화성 접착제층 및 적어도 일부 상에 상기 접착제층을 보유하는 배킹층을 포함하는 접착제 물품을 제공한다. Provided are a thermosetting adhesive composition and an adhesive article suitable for dicing a semiconductor and die bonding of a diced semiconductor chip, and a semiconductor device and a method for manufacturing a semiconductor device using the adhesive composition and the adhesive article. In one embodiment, the present invention provides a heat curable adhesive composition comprising a caprolactone modified epoxy resin and a viscosity reducing component. Another embodiment of the present invention provides an adhesive article comprising a heat curable adhesive layer of a heat curable adhesive composition comprising a caprolactone modified epoxy resin and a viscosity reducing component and a backing layer retaining the adhesive layer on at least a portion. 반도체, 다이싱, 열 경화성 접착제 조성물, 접착제층, 배킹층, 접착제 물품 Semiconductor, Dicing, Thermosetting Adhesive Compositions, Adhesive Layers, Backing Layers, Adhesive Articles

Patent DE3424241C2

Method of integration of components to plate-base

FIELD: electrotechnics. SUBSTANCE: invention is related to the method, according to which semiconductor elements, forming the part of electronic circuit or at least some of its components, of integration to the plate-base, for example to the printing board in the process of its production. The effect of the invention is achieved by making through-holes in the plate-base for semiconductor components, together with that these holes move between the first and the second surfaces of the plate-base. After creating these holes on the second surface structure plate-base one lays on the plastic foil, which covers the through-holes for semiconducting elements from the side of the second surface structure plates-base. Before hardening of he plastic foil or after its partial hardening the semiconductor elements are cut in from the side of the first surface. Semiconductor elements are pressed down to the plastic foil after that they are being glued to it. After that the final hardening of the plastic foil is carried out. EFFECT: creation of the method, by which packageless microcircuit are inbuilt safely and economically to the plate-base. 24 cl, 23 dwg ÐÎÑÑÈÉÑÊÀß ÔÅÄÅÐÀÖÈß RU (19) (11) 2 327 311 (13) C2 (51) ÌÏÊ H05K 3/30 H05K 1/18 (2006.01) (2006.01) ÔÅÄÅÐÀËÜÍÀß ÑËÓÆÁÀ ÏÎ ÈÍÒÅËËÅÊÒÓÀËÜÍÎÉ ÑÎÁÑÒÂÅÍÍÎÑÒÈ, ÏÀÒÅÍÒÀÌ È ÒÎÂÀÐÍÛÌ ÇÍÀÊÀÌ (12) ÎÏÈÑÀÍÈÅ ÈÇÎÁÐÅÒÅÍÈß Ê ÏÀÒÅÍÒÓ (21), (22) Çà âêà: 2004126136/09, 28.01.2003 (72) Àâòîð(û): ÒÓÎÌÈÍÅÍ Ðèñòî (FI) (24) Äàòà íà÷àëà îòñ÷åòà ñðîêà äåéñòâè ïàòåíòà: 28.01.2003 (73) Ïàòåíòîîáëàäàòåëü(è): ÈÌÁÅÐÀ ÝËÅÊÒÐÎÍÈÊÑ ÎÉ (FI) R U (30) Êîíâåíöèîííûé ïðèîðèòåò: 31.01.2002 (ïï.1-25) FI 20020191 (43) Äàòà ïóáëèêàöèè çà âêè: 27.05.2005 (45) Îïóáëèêîâàíî: 20.06.2008 Áþë. ¹ 17 2 3 2 7 3 1 1 (56) Ñïèñîê äîêóìåíòîâ, öèòèðîâàííûõ â îò÷åòå î ïîèñêå: US 4246595 À, 20.01.1981. RU 2001132099 À, 20.07.2003. SU 202258 À, 24.11.1967. SU 320959 A, 12.01.1972. SU 997268 A, 15.02.1983. JP 11-307686 À, 05.11.1999. JP 2002-016327 À, 18.01.2002. JP 11-186676 À, 09.07. ...

Method to form solder alloy deposits on substrates

Described is a method of forming a solder alloy deposit on a substrate comprising the following steps i) provide a substrate including a surface bearing electrical circuitry that includes at least one inner layer contact pad, ii) form a solder mask layer that is placed on the substrate surface and patterned to expose the at least one contact area, iii) contact the entire substrate area including the solder mask layer and the at least one contact area with a solution suitable to provide a metal seed layer on the substrate surface, iv) form a structured resist layer on the metal seed layer, v) electroplate a first solder material layer containing tin onto the conductive layer, vi) electroplate a second solder material layer onto the first solder material layer, vii) remove the structured resist layer and etch away an amount of the metal seed layer sufficient to remove the metal seed layer from the solder mask layer area and reflow the substrate and in doing so form a solder alloy deposit from the metal seed layer, the first solder material layer and the second solder material layer.

Method of forming lead-free bump interconnections

A method of forming solder bumps on a chip or wafer for flip-chip applications comprises the steps of providing a chip or wafer having a plurality of metal bonds pads which provide electrical connection to the chip or wafer, and applying a solder bump comprising pure tin or a tin alloy selected from tin-copper, tin-silver, tin-bismuth or tin-silver-copper by an electroplating technique, and melting the solder bumps by heating to a temperature above the bump melting point to effect reflow.

Method to form solder alloy deposits on substrates

Described is a method of forming a solder alloy deposit on a substrate comprising the following steps i) provide a substrate including a surface bearing electrical circuitry that includes at least one inner layer contact pad, ii) form a solder mask layer that is placed on the substrate surface and patterned to expose the at least one contact area, iii) contact the entire substrate area including the solder mask layer and the at least one contact area with a solution suitable to provide a metal seed layer on the substrate surface, iv) form a structured resist layer on the metal seed layer, v) electroplate a first solder material layer containing tin onto the conductive layer, vi) electroplate a second solder material layer onto the first solder material layer, vii) remove the structured resist layer and etch away an amount of the metal seed layer sufficient to remove the metal seed layer from the solder mask layer area and reflow the substrate and in doing so form a solder alloy deposit from the metal seed layer, the first solder material layer and the second solder material layer.

Patent JPS58501372A

(57)【要約】本公報は電子出願前の出願データであるため要約のデータは記録されません。

Method of bonding high voltage aluminum ball

Nanowires, nanostructures and devices fabricated therefrom

One-dimensional nanostructures having uniform diameters of less than approximately 200 nm. These inventive nanostructures, which we refer to as “nanowires”, include single-crystalline homostructures as well as heterostructures of at least two single-crystalline materials having different chemical compositions. Because single-crystalline materials are used to form the heterostructure, the resultant heterostructure will be single-crystalline as well. The nanowire heterostructures are generally based on a semiconducting wire wherein the doping and composition are controlled in either the longitudinal or radial directions, or in both directions, to yield a wire that comprises different materials. Examples of resulting nanowire heterostructures include a longitudinal heterostructure nanowire (LOHN) and a coaxial heterostructure nanowire (COHN).

Assembly, in particular wafer assembly

The module (10) is especially a wafer module and has two functional elements (11, 12) which lie opposite each other and which are functionally interconnected by a compression-deformable layer of a joining agent (13) located in-between them. The invention provides that at least one functional element (11; 12; 11, 12) is surface-structured in such a way as to form a depression (14) and that the functional connection lies exclusively in the area of this depression (14).

Feedthrough design and method for a hermetically sealed microdevice

A microdevice ( 20, 120, 220 ) having a hermetically sealed cavity ( 22, 122, 222 ) to house a microstructure ( 26, 126, 226 ). In one embodiment, the microdevice ( 20 ) comprises a substrate ( 30 ), a cap ( 50 ) and an isolation layer ( 70 ). The substrate ( 30 ) has a plurality of conductive traces ( 38 ) formed on at least a portion of its top side ( 32 ) and outer edge ( 36 ). The conductive traces ( 38 ) provide electrical conductivity to the microstructure ( 26 ). The isolation layer ( 70 ) is attached between an outer edge of a sidewall ( 54 ) of the cap ( 50 ) and the plurality of conductive traces ( 38 ). The cavity ( 22 ) is at least partially defined by a recess ( 56 ) in the cap ( 50 ). There is also a microdevice ( 120 ) comprising a substrate ( 130 ), a cap ( 150 ) and a plurality of via covers ( 170 ). The substrate ( 130 ) has conductive vias ( 196 ) that terminate at a contact point ( 146 ) within the sealed cavity ( 122 ). The via covers ( 170 ) are attached to the substrate ( 130 ) to provide a hermetic seal. There is a further microdevice ( 220 ) comprising a substrate ( 230 ), a cap ( 250 ), and a plurality of conductive members ( 270 ). The cap ( 250 ) has conductive vias ( 296 ) that terminate at the conductive members ( 270 ). The conductive members ( 270 ) are electrically connected to the microstructure ( 226 ). There are also methods of forming the microdevice ( 20, 120, 220 ).