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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 22182. Отображено 100.
05-01-2012 дата публикации

Active energy ray-curable pressure-sensitive adhesive for re-release and dicing die-bonding film

Номер: US20120003470A1
Автор: Chie Kitano, Hironao OTAKE, Katsuhiko Kamiya, Masatsugu KOSO, Mika Okada, Shuhei Murata, Takeshi Matsumura, Tomokazu Takahashi
Принадлежит: Nitto Denko Corp

Provided is an active energy ray-curable pressure-sensitive adhesive for re-release, which has a small influence on an environment or a human body, can be easily handled, can largely change its pressure-sensitive adhesiveness before and after irradiation with an active energy ray, and can express high pressure-sensitive adhesiveness before the irradiation with the active energy ray and express high releasability after the irradiation with the active energy ray. The active energy ray-curable pressure-sensitive adhesive for re-release includes an active energy ray-curable polymer (P), in which the polymer (P) includes one of a polymer obtained by causing a carboxyl group-containing polymer (P3) and an oxazoline group-containing monomer (m3) to react with each other, and a polymer obtained by causing an oxazoline group-containing polymer (P4) and a carboxyl group-containing monomer (m2) to react with each other.

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Номер записи: 1
12-01-2012 дата публикации

Method for Reducing Chip Warpage

Номер: US20120007220A1
Автор: Chun-Ren Cheng, Jiou-Kang Lee, Jung-Huei Peng, Shang-Ying Tsai, Ting-Hau Wu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.

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Номер записи: 2
12-01-2012 дата публикации

Semiconductor device

Номер: US20120007224A1
Автор: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
Принадлежит: Hitachi Hokkai Semiconductor Ltd, Renesas Electronics Corp

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

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Номер записи: 3
12-01-2012 дата публикации

Method of forming cu pillar capped by barrier layer

Номер: US20120007231A1
Автор: Wei Sen CHANG
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.

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Номер записи: 4
12-01-2012 дата публикации

Resin-Encapsulated Semiconductor Device

Номер: US20120007247A1
Автор: Motoharu Haga, Shoji Yasunaga, Yasumasa Kasuya
Принадлежит: ROHM CO LTD

A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more.

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Номер записи: 5
19-01-2012 дата публикации

Interconnections for flip-chip using lead-free solders and having reaction barrier layers

Номер: US20120012642A1
Автор: Balaram Ghosal, Da-Yuan Shih, Donna S. Zupanski-Nielsen, Henry A. Nye, III, Keith E. Fogel, Paul A. Lauro, Stephen Kilpatrick, Sung K. Kang
Принадлежит: International Business Machines Corp

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. With a two-layer ball-limiting composition comprising an adhesion/reaction barrier layer, wherein the adhesion/reaction barrier layer serves both as an adhesion layer and a reaction barrier layer, the adhesion/reaction barrier layer can be comprised of a material selected from the group consisting of Zr and ZrN

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Номер записи: 6
19-01-2012 дата публикации

Stacked semiconductor package and method of fabricating the same

Номер: US20120013026A1
Автор: Won-Gil HAN
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A stacked semiconductor package and an electronic system, the stacked semiconductor package including a plurality of semiconductor chips, a set of the semiconductor chips being stacked such that an extension region of a top surface of each semiconductor chip of the set extends beyond an end of a semiconductor chip stacked thereon to form a plurality of extension regions; and a plurality of protection layers on the extension regions and on an uppermost semiconductor chip of the plurality of semiconductor chips.

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Номер записи: 7
19-01-2012 дата публикации

Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another

Номер: US20120013028A1
Автор: Belgacem Haba, Ilyas Mohammed
Принадлежит: Tessera LLC

A microelectronic assembly includes first and second microelectronic elements. Each of the microelectronic elements has oppositely-facing first and second surfaces and edges bounding the surfaces. The first microelectronic element is disposed on the second microelectronic element with the second surface of the first microelectronic element facing toward the first surface of the second microelectronic element. The first microelectronic element preferably extends beyond at least one edge of the second microelectronic element and the second microelectronic element preferably extends beyond at least one edge of the first microelectronic element. A first edge of the first microelectronic element has a length that is smaller than a first edge of the second microelectronic element. A second edge of the first microelectronic element has a length that is greater than the second edge of the second microelectronic element.

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Номер записи: 8
26-01-2012 дата публикации

Substrate for semiconductor element, method for manufacturing substrate for semiconductor element, and semiconductor device

Номер: US20120018867A1
Автор: Junko Toda, Susumu Maniwa, Takehito Tsukamoto
Принадлежит: Toppan Printing Co Ltd

Provided is a manufacturing method of a semiconductor element substrate including: a step of forming a first photoresist pattern on a first surface of a metallic plate, to form a semiconductor element mounting part, a semiconductor element electrode connection terminal, a wiring, an outer frame part, and a slit; a step of forming a second photoresist pattern on the second surface of the metallic plate; a step of forming the slit by half etching to connect the metallic chip with a four corners of the outer frame part; a step of forming a plurality of concaved parts on the second surface of the metallic plate; a step of forming a resin layer by injecting a resin to the plurality of concaved parts; and a step of etching the first surface of the metallic plate and forming the semiconductor element electrode connection terminal and the outer frame.

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Номер записи: 9
26-01-2012 дата публикации

Methods of forming semiconductor elements using micro-abrasive particle stream

Номер: US20120018893A1
Автор: Belgacem Haba, Craig Mitchell, Ilyas Mohammed, Piyush Savalia, Vage Oganesian
Принадлежит: TESSERA RESEARCH LLC

A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device.

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Номер записи: 10
26-01-2012 дата публикации

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

Номер: US20120018904A1
Автор: Jianmin Fang, KANG Chen, Xia Feng, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

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Номер записи: 11
02-02-2012 дата публикации

Chip having a driving integrated circuit

Номер: US20120025372A1
Автор: Pao-Yun Tang, Wei-Hao Sun
Принадлежит: Hannstar Display Corp

A chip having a bump layout suitable for the chip on glass technology and a driving IC includes a plurality of first bumps and a plurality of second bumps for electrically connecting to a glass substrate of a displayer. The first and second bumps are disposed on a surface of the chip and near two opposite long sides of the chip respectively. The ratio of the total contacting area of the first bumps to that of the second bumps is between 0.8 and 1.2. Thus, a pressure applied on the chip and the glass substrate of the displayer for connection can be uniformly exerted all over the chip, and the stability of the connection is therefore improved.

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Номер записи: 12
02-02-2012 дата публикации

Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device

Номер: US20120025400A1
Автор: Fumiteru Asai, Goji Shiga, Naohide Takamoto, Yusuke Komoto
Принадлежит: Nitto Denko Corp

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, in which the film for flip chip type semiconductor back surface before thermal curing has, at the thermal curing thereof, a volume contraction ratio within a range of 23° C. to 165° C. of 100 ppm/° C. to 400 ppm/° C.

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Номер записи: 13
09-02-2012 дата публикации

Gas delivery system for reducing oxidation in wire bonding operations

Номер: US20120031877A1
Автор: Gary S. Gillotti, Peter J. Van Emmerik, Stanley Szczesniak
Принадлежит: Kulicke and Soffa Industries Inc

A wire bonding machine is provided. The wire bonding machine includes a bonding tool and an electrode for forming a free air ball on an end of a wire extending through the bonding tool where the free air ball is formed at a free air ball formation area of the wire bonding machine. The wire bonding machine also includes a bond site area for holding a semiconductor device during a wire bonding operation. The wire bonding machine also includes a gas delivery mechanism configured to provide a cover gas to: (1) the bond site area whereby the cover gas is ejected through at least one aperture of the gas delivery mechanism to the bond site area, and (2) the free air ball formation area.

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Номер записи: 14
09-02-2012 дата публикации

Semiconductor device and method for producing such a device

Номер: US20120032295A1
Автор: Carsten Von Koblinski, Francisco Javier Santos Rodriguez, Friedrich Kroener
Принадлежит: INFINEON TECHNOLOGIES AG

A semiconductor device and method for producing such a device is disclosed. One embodiment provides a semiconductor functional wafer having a first and second main surface. Component production processes are performed for producing a component functional region at the first main surface, wherein the component production processes produce an end state that is stable up to at least a first temperature. A carrier substrate is fitted to the first main surface. Access openings are produced to the first main surface. At least one further component production process is performed for producing patterned component functional regions at the first main surface of the functional wafer in the access openings. The end state produced in this process is stable up to a second temperature, which is less than the first temperature.

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Номер записи: 15
09-02-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120032323A1
Автор: Akihiro Osaki, Atsushi Ishii, Masahiko Fujisawa, Masahiro Matsumoto
Принадлежит: Renesas Electronics Corp

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

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Номер записи: 16
09-02-2012 дата публикации

Semiconductor device

Номер: US20120032325A1
Автор: Osamu Miyata, Shingo Higuchi
Принадлежит: ROHM CO LTD

There is provided a semiconductor device with which stress can be prevented from locally concentrating on an external connecting terminal on a post and thus damages of the external connecting terminal can be prevented. The semiconductor device includes a semiconductor chip, a sealing resin layer stacked on a surface of the semiconductor chip, and the post which penetrates the sealing resin layer in a stacking direction of the semiconductor chip and the sealing resin layer, protrudes from the sealing resin layer, and has a periphery of the protruding portion opposedly in contact with a surface of the sealing resin layer in the stacking direction.

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Номер записи: 17
09-02-2012 дата публикации

Systems and Methods for Heat Dissipation Using Thermal Conduits

Номер: US20120032350A1
Автор: Jianjun Li, Nic Rossi, Robert W. Warren
Принадлежит: Conexant Systems LLC

The addition of thermal conduits by bonding bond wires to bond pads either in a wire loop configuration or a pillar configuration can improve thermal dissipation of a fabricated die. The thermal conduits can be added as part of the normal packaging process of a semiconductor die and are electrically decoupled from the circuitry fabricated on the fabricated die. In an alternative, a dummy die is affixed to the fabricated die and the thermal conduits are affixed to the dummy die. Additionally, thermal conduits can be used in conjunction with a heat spreader.

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Номер записи: 18
16-02-2012 дата публикации

Stitch bump stacking design for overall package size reduction for multiple stack

Номер: US20120038059A1
Автор: Foong Yue Ho, Kevin Guan, Koo Eng LUON, Lai Nguk Chin, Sally Foong, Wong Kwet Nam
Принадлежит: Individual

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

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Номер записи: 19
23-02-2012 дата публикации

Image Sensor Package with Dual Substrates and the Method of the Same

Номер: US20120043635A1
Автор: Wen-Kun Yang
Принадлежит: King Dragon International Inc

The image sensor package with dual substrates comprises a first substrate with a die receiving opening and a plurality of first through hole penetrated through the first substrate; a second substrate with a die opening window and a plurality of second through hole penetrated through the second substrate, formed on the first substrate. A part of the second wiring pattern is coupled to a part of the third wiring pattern; an image die having conductive pads and sensing array received within the die receiving opening and the sensing array being exposed by the die opening window; and a through hole conductive material refilled into the plurality of second through hole, some of the plurality of second through hole coupling to the conductive pads of the image sensor.

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Номер записи: 20
23-02-2012 дата публикации

Packaging Integrated Circuits

Номер: US20120043650A1
Автор: Liang Kng Ian Koh, Richard Mangapul Sinaga
Принадлежит: INFINEON TECHNOLOGIES AG

An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.

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Номер записи: 21
23-02-2012 дата публикации

Mechanisms for forming copper pillar bumps using patterned anodes

Номер: US20120043654A1
Автор: Chih-Wei Lin, Chung-Shi Liu, Ming-Da Cheng, Wen-Hsiung LU
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

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Номер записи: 22
01-03-2012 дата публикации

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

Номер: US20120049343A1
Автор: Frank Kuechenmeister, Lei Fu, Michael Su, Thomas Schulze
Принадлежит: Advanced Micro Devices Inc, Globalfoundries Inc

A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement has a stepped via that terminates at the contact pad, and the stepped via has a plurality of inwardly sloped and concentric sections in a stacked orientation. The connection structure also includes underbump metallization overlying at least a portion of the contact pad and lining the stepped via, and a conductive connection element coupled to the underbump metallization. The conductive connection element fills the lined recess.

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Номер записи: 23
15-03-2012 дата публикации

Power Semiconductor Chip Package

Номер: US20120061812A1
Автор: Ralf Otremba
Принадлежит: INFINEON TECHNOLOGIES AG

A device includes a vertical power semiconductor chip having an epitaxial layer and a bulk semiconductor layer. A first contact pad is arranged on a first main face of the power semiconductor chip and a second contact pad is arranged on a second main face of the power semiconductor chip opposite to the first main face. The device further comprises an electrically conducting carrier attached to the second contact pad.

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Номер записи: 24
15-03-2012 дата публикации

Semiconductor device and manufacturing method of the same

Номер: US20120061817A1
Автор: Mamoru SHISHIDO, Noriyuki Takahashi
Принадлежит: Renesas Electronics Corp

A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

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Номер записи: 25
15-03-2012 дата публикации

Semiconductor chip with redundant thru-silicon-vias

Номер: US20120061821A1
Автор: Bryan Black, Gamal Refai-Ahmed, Joe Siegel, Michael Z. Su, Seth Prejean
Принадлежит: Advanced Micro Devices Inc, ATI TECHNOLOGIES ULC

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip. The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.

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Номер записи: 26
15-03-2012 дата публикации

Semiconductor device having pad structure with stress buffer layer

Номер: US20120061823A1
Автор: Chao-Wen Shih, Shang-Yun Hou, Shin-puu Jeng, Tzu-Wei Chiu, Tzuan-Horng LIU, Wei-Cheng Wu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

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Номер записи: 27
15-03-2012 дата публикации

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

Номер: US20120064666A1
Автор: Shigeru Hosomomi, Yoichiro Hamada
Принадлежит: SUMITOMO METAL MINING CO LTD

A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate.

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Номер записи: 28
15-03-2012 дата публикации

Method of manufacture of integrated circuit packaging system with stacked integrated circuit

Номер: US20120064668A1
Автор: Henry Descalzo Bathan, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho
Принадлежит: Individual

A method of manufacture of an integrated circuit packaging system includes: forming a base lead having an outer protrusion and an inner protrusion with a recess in between; forming a stack lead having an elongated portion; mounting a base integrated circuit over the inner protrusion or under the elongated portion; mounting the stack lead over the base lead and the base integrated circuit; connecting a stack integrated circuit and the stack lead with the stack integrated circuit over the base integrated circuit; and encapsulating at least a portion of both the base integrated circuit and the stack integrated circuit with the base lead and the stack lead exposed.

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Номер записи: 29
22-03-2012 дата публикации

Multi-function and shielded 3d interconnects

Номер: US20120068327A1
Автор: Belgacem Haba, Craig Mitchell, Ilyas Mohammed, Piyush Savalia, Vage Oganesian
Принадлежит: TESSERA RESEARCH LLC

A microelectronic unit includes a semiconductor element consisting essentially of semiconductor material and having a front surface, a rear surface, a plurality of active semiconductor devices adjacent the front surface, a plurality of conductive pads exposed at the front surface, and an opening extending through the semiconductor element. At least one of the conductive pads can at least partially overlie the opening and can be electrically connected with at least one of the active semiconductor devices. The microelectronic unit can also include a first conductive element exposed at the rear surface for connection with an external component, the first conductive element extending through the opening and electrically connected with the at least one conductive pad, and a second conductive element extending through the opening and insulated from the first conductive element. The at least one conductive pad can overlie a peripheral edge of the second conductive element.

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Номер записи: 30
22-03-2012 дата публикации

Microsprings Partially Embedded In A Laminate Structure And Methods For Producing Same

Номер: US20120068331A1
Автор: Eric Peeters, Eugene M. Chow
Принадлежит: Palo Alto Research Center Inc

At least one microspring has applied thereover a laminate structure to provide: mechanical protection during handling and wafer processing, a spring spacer layer, strengthening of the anchor between spring and substrate, provision of a gap stop during spring deflection, and moisture and contaminant protection. A fully-formed laminate structure may be applied over the microspring structure or a partly-formed laminate structure may be applied over the microspring structure then cured or hardened. The tip portion of the microspring may protrude through the laminate structure and be exposed for contact or may be buried within the contact structure. The laminate structure may remain in place in the final microspring structure or be removed in whole or in part. The laminate structure may be photolithographically patternable material, patterned and etched to remove some or all of the structure, forming for example additional structural elements such as a gap stop for the microspring.

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Номер записи: 31
22-03-2012 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20120068334A1
Автор: Hirokazu Ezawa, Soichi Yamashita, Tatsuo Migita
Принадлежит: Toshiba Corp

Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.

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Номер записи: 32
22-03-2012 дата публикации

Method of making a light emitting device having a molded encapsulant

Номер: US20120070921A1
Автор: Catherine A. Leatherdale, D. Scott Thompson, Larry D. Boardman
Принадлежит: 3M Innovative Properties Co

Disclosed herein is a method of making a light emitting device having an LED die and a molded encapsulant made by polymerizing at least two polymerizable compositions. The method includes: (a) providing an LED package having an LED die disposed in a reflecting cup, the reflecting cup filled with a first polymerizable composition such that the LED die is encapsulated; (b) providing a mold having a cavity filled with a second polymerizable composition; (c) contacting the first and second polymerizable compositions; (d) polymerizing the first and second polymerizable compositions to form first and second polymerized compositions, respectively, wherein the first and second polymerized compositions are bonded together; and (e) optionally separating the mold from the second polymerized composition. Light emitting devices prepared according to the method are also described.

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Номер записи: 33
29-03-2012 дата публикации

Semiconductor module including a switch and non-central diode

Номер: US20120074428A1
Автор: Gourab Majumdar, Kiyoshi Arai
Принадлежит: Mitsubishi Electric Corp

A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

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Номер записи: 34
29-03-2012 дата публикации

Methods of fabricating package stack structure and method of mounting package stack structure on system board

Номер: US20120074586A1
Автор: Eun-Jin Choi, Sun-Kyoung SEO
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

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Номер записи: 35
05-04-2012 дата публикации

Off-chip vias in stacked chips

Номер: US20120080807A1
Автор: Belgacem Haba, David Ovrutsky, Ilyas Mohammed, Laura Wills Mirkarimi, Vage Oganesian
Принадлежит: Tessera LLC

A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.

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Номер записи: 36
05-04-2012 дата публикации

Semiconductor die package including low stress configuration

Номер: US20120083071A1
Автор: Maria Clemens Y. Quinones, Maria Cristina B. Estacio
Принадлежит: Individual

A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.

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Номер записи: 37
12-04-2012 дата публикации

Package with embedded chip and method of fabricating the same

Номер: US20120086117A1
Автор: Chiang-Cheng Chang, Hsin-Yi Liao, Shih-Kuang Chiu
Принадлежит: Siliconware Precision Industries Co Ltd

A package embedded with a chip and a method of fabricating the package of embedded chip. The package of embedded chip includes a dielectric layer having a first surface and a second surface opposing the first surface; a plurality of conductive pillars formed in the dielectric layer and exposed from the second surface of the dielectric layer; a chip embedded in the dielectric layer; a circuit layer formed on the first surface of the dielectric layer; a plurality of conductive blind vias formed in the dielectric layer, allowing the circuit layer to be electrically connected via the conductive blind vias to the chip and each of the conductive pillars; and a first solder mask layer formed on the first surface of the dielectric layer and the circuit layer, thereby using conductive pillars to externally connect with other electronic devices as required to form a stacked structure. Therefore, the manufacturing process can be effectively simplified.

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Номер записи: 38
12-04-2012 дата публикации

Semiconductor assembly and semiconductor package including a solder channel

Номер: US20120086123A1
Автор: Jeong-Woo Park, Moon-Gi Cho, Sun-Hee Park, Ui-Hyoung Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

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Номер записи: 39
19-04-2012 дата публикации

Microelectronic assemblies having compliancy and methods therefor

Номер: US20120091582A1
Автор: Belgacem Haba, David Ovrutsky, Guilian Gao, Vage Oganesian
Принадлежит: Tessera LLC

A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

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Номер записи: 40
19-04-2012 дата публикации

Method of die bonding onto dispensed adhesives

Номер: US20120094440A1
Автор: Kui Kam Lam, Kwok Kee Chung, Kwok Kiu CHAN, Yen Hsi Tang
Принадлежит: ASM Assembly Automation Ltd

A method of bonding semiconductor dice onto a substrate first uses an optical assembly to perform pattern recognition of a die bonding section of the substrate in which multiple die pads are located so as to identify positions of the multiple die pads simultaneously during such pattern recognition step. After pattern recognition of the said die bonding section, an adhesive is dispensed with an adhesive dispenser onto at least one of the die pads located in the die bonding section. While the adhesive dispenser is dispensing the adhesive to further die pads located in the die bonding section, a pick-and-place arm concurrently bonds a die onto each die pad where the adhesive has already been dispensed.

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Номер записи: 41
26-04-2012 дата публикации

Light emitting diode package

Номер: US20120098003A1
Автор: Kai-Lun Wang, Shih-Yuan Hsu
Принадлежит: Advanced Optoelectronic Technology Inc

An exemplary light emitting diode (LED) package includes a substrate, an LED chip mounted on the substrate, and a wire. The LED chip includes a semiconductor structure and an electrode disposed on the semiconductor structure. The wire electrically connects the electrode of the LED chip to an electrical portion of the substrate. The wire has a first joint and a second joint connected to the substrate. The wire forms a first curved portion between the electrode and the first joint and a second curved portion between the first joint and the second joint.

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Номер записи: 42
26-04-2012 дата публикации

Bond pad for wafer and package for cmos imager

Номер: US20120098105A1
Автор: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Richard L. Rassel
Принадлежит: International Business Machines Corp

An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.

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Номер записи: 43
26-04-2012 дата публикации

Power/ground layout for chips

Номер: US20120098127A1
Автор: Albert Wu, Chuan-Cheng Cheng, Chung Chyung Han, Sehat Sutardja, Shuhua Yu, Weidan Li
Принадлежит: MARVELL WORLD TRADE LTD

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.

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Номер записи: 44
03-05-2012 дата публикации

Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product

Номер: US20120104588A1
Автор: Hong-Chin Lin, Nan-Jang Chen
Принадлежит: MediaTek Inc

A leadframe package includes a die pad with four unitary, outwardly extending slender bars; a plurality of leads arranged along periphery of the die pad; a separate pad segment separated from the die pad and isolated from the plurality of leads; a semiconductor die mounted on an upper side of the die pad, wherein the semiconductor die contains first bond pads wire-bonded to respective the plurality of leads and a second bond pad wire-bonded to the separate pad segment; and a molding compound encapsulating the semiconductor die, the upper side of the die pad, the first suspended pad segment and inner portions of the plurality of leads.

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Номер записи: 45
10-05-2012 дата публикации

Electronic element unit and reinforcing adhesive agent

Номер: US20120111617A1
Автор: Koji Motomura, Seiichi Yoshinaga, Tadahiko Sakai
Принадлежит: Panasonic Corp

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

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Номер записи: 46
10-05-2012 дата публикации

Semiconductor Device and Method of Forming Prefabricated EMI Shielding Frame with Cavities Containing Penetrable Material Over Semiconductor Die

Номер: US20120112327A1
Автор: Reza A. Pagaila, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a plurality of semiconductor die mounted to a temporary carrier. A prefabricated shielding frame has a plate and integrated bodies extending from the plate. The bodies define a plurality of cavities in the shielding frame. A penetrable material is deposited in the cavities of the shielding frame. The shielding frame is mounted over the semiconductor die such that the penetrable material encapsulates the die. The carrier is removed. An interconnect structure is formed over the die, shielding frame, and penetrable material. The bodies of the shielding frame are electrically connected through the interconnect structure to a ground point. The shielding frame is singulated through the bodies or through the plate and penetrable material to separate the die. TIM is formed over the die adjacent to the plate of the shielding frame. A heat sink is mounted over the plate of the shielding frame.

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Номер записи: 47
10-05-2012 дата публикации

Semiconductor device with nested rows of contacts

Номер: US20120112333A1
Автор: Qiang Liu, Qingchun He, Zhaojun Tian
Принадлежит: FREESCALE SEMICONDUCTOR INC

A molded surface mount semiconductor device has electrical contact elements disposed in a set of pairs of zigzag rows extending adjacent and generally parallel to opposite edges of an active face of a semiconductor die. Each of the pairs of rows includes an inner zigzag row of electrical contact elements nested inside an outer zigzag row of electrical contact elements. The electrical contact elements of the inner and outer zigzag rows are partially inter-digitated. A lead frame used in making the device also has a die pad located inside the set of pairs of zigzag rows, and an outer frame element located outside the set of pairs of zigzag rows, and which support the electrical contact elements of the inner and outer zigzag rows respectively.

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Номер записи: 48
17-05-2012 дата публикации

Semiconductor Device And Method Of Manufacturing Semiconductor Device

Номер: US20120119338A1
Автор: Shintaro Yamamichi, Takahito Watanabe, Yoshitaka USHIYAMA
Принадлежит: Renesas Electronics Corp

A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

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Номер записи: 49
24-05-2012 дата публикации

Connecting and Bonding Adjacent Layers with Nanostructures

Номер: US20120125537A1
Автор: Andrzej Brud, Mohammad Shafiqul Kabir
Принадлежит: Smoltek AB

An apparatus, comprising two conductive surfaces or layers and a nanostructure assembly bonded to the two conductive surfaces or layers to create electrical or thermal connections between the two conductive surfaces or layers, and a method of making same.

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Номер записи: 50
24-05-2012 дата публикации

Package carrier

Номер: US20120125669A1
Автор: Chau-Jie Zhan, Jing-Yao Chang, Tao-Chih Chang, Tsung-Fu Tsai
Принадлежит: Industrial Technology Research Institute ITRI

A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

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Номер записи: 51
24-05-2012 дата публикации

Semiconductor device package with electromagnetic shielding

Номер: US20120126378A1
Автор: Allan C. Toriaga, Anang Subagio, Michael H. McKerreghan, Romarico S. San Antonio
Принадлежит: Unisem (Mauritius) Holdings Ltd

A package for a semiconductor device includes shielding from RF interference. The package has a lead frame with a lead and a connecting bar. The lead has an inner end for connecting to the device and an outer end having an exposed surface at the package side face. The connecting bar also has an end with an exposed surface at the package side face. A molding compound overlying the leadframe forms a portion of the side face. Electrically conductive shielding forms a top surface of the package, and extends downward therefrom to form an upper portion of the package side face. The exposed surface at the connecting bar end has an upper edge higher than the upper edge of the exposed surface of lead end. Accordingly, the shielding makes electrical contact with the connecting bar adjacent to its exposed surface, while being electrically isolated from the lead.

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Номер записи: 52
24-05-2012 дата публикации

Structures and methods for improving solder bump connections in semiconductor devices

Номер: US20120129336A1
Автор: Anthony K. Stamper, Daniel C. Edelstein, Felix P. Anderson, Thomas L. McDevitt, William Cote
Принадлежит: International Business Machines Corp

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

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Номер записи: 53
31-05-2012 дата публикации

Semiconductor device

Номер: US20120133058A1
Автор: Kunihiro Komiya
Принадлежит: ROHM CO LTD

The semiconductor device has the CSP structure, and includes: a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps are arranged in two rows along the periphery of the semiconductor device. The electrode pads are arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring is extended from an electrode pad, and is connected to any one of the outermost solder bumps or any one of the inner solder bumps.

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Номер записи: 54
31-05-2012 дата публикации

Mechanisms for resistivity measurement of bump structures

Номер: US20120133379A1
Автор: Feynmann CHU, Jeff Wang, Mill-Jer Wang, Pi-Huang Lee, You-Hua Chou
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

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Номер записи: 55
07-06-2012 дата публикации

Semiconductor Device

Номер: US20120139130A1
Автор: Masaki Shiraishi, Nobuyoshi Matsuura, Tomoaki Uno, Yukihiro Satou
Принадлежит: Renesas Electronics Corp

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

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Номер записи: 56
14-06-2012 дата публикации

Brace for long wire bond

Номер: US20120145446A1
Автор: Hanmin Zhang, Jie Yang, Qingchin He
Принадлежит: FREESCALE SEMICONDUCTOR INC

An electrical connection includes a first wire bonded to adjacent bond pads proximate to an edge of a die and a second wire having one end bonded to a die bond pad distal to the die edge and a second end bonded to a lead finger of a lead frame or a connection pad of a substrate. The second wire crosses and is supported by the first wire. The first wire acts as a brace that prevents the second wire from touching the edge of the die. The first wire also prevents the second wire from excessive lateral movement during encapsulation.

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Номер записи: 57
14-06-2012 дата публикации

Mold release film and process for producing light emitting diode

Номер: US20120148820A1
Автор: Tamao Okuya
Принадлежит: Asahi Glass Co Ltd

To provide a mold release film for producing a light emitting diode by a mold, which is less susceptible to formation of pin holes or rupture and which is applicable to mass production of a light emitting diode by means of a mold having a plurality of cavities, and a process for producing a light emitting diode by means of such a mold release film. A mold release film to be disposed on the cavity surface of a mold to form a substantially hemispherical lens portion by encapsulating a light emitting element of a light emitting diode with an encapsulation resin, which release film has a thickness of from 16 to 175 μm and a tensile rupture elongation of from 600 to 3,000% at 110° C. as measured in accordance with JIS K7127, and a process for producing a light emitting diode by means of such a mold release film.

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Номер записи: 58
21-06-2012 дата публикации

Semiconductor component, semiconductor wafer component, manufacturing method of semiconductor component, and manufacturing method of joining structure

Номер: US20120153461A1
Автор: Akio Furusawa, Hidetoshi Kitaura, Shigeaki Sakatani, Taichi Nakamura, Takahiro Matsuo
Принадлежит: Panasonic Corp

A semiconductor component of the present invention includes a semiconductor element and a joining layer formed on one surface of the semiconductor element and consisting of a joining material containing Bi as an essential ingredient, and projecting sections are formed on a surface of the joining layer on a side opposite to a surface in contact with the semiconductor element. By joining the semiconductor component to an electrode arranged so as to face the joining layer, the generation of a void can be suppressed.

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Номер записи: 59
28-06-2012 дата публикации

Semiconductor device and assembling method thereof

Номер: US20120161336A1
Автор: Chau-Jie Zhan, Su-Tsai Lu, Yu-Min Lin
Принадлежит: Industrial Technology Research Institute ITRI

A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.

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Номер записи: 60
28-06-2012 дата публикации

Bond package and approach therefor

Номер: US20120162958A1
Автор: Michael Rother
Принадлежит: NXP BV

Lead-free or substantially lead-free structures and related methods are implemented for manufacturing electronic circuits. In accordance with various example embodiments, circuit components are joined using a copper-tin (Cu—Sn) alloy, which is melted and used to form a Cu—Sn compound having a higher melting point than the Cu—Sn alloy and both physically and electrically coupling circuit components together.

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Номер записи: 61
28-06-2012 дата публикации

Method of manufacturing semiconductor device including plural semiconductor chips stacked together

Номер: US20120164788A1
Автор: Akira Ide
Принадлежит: Elpida Memory Inc

Such a method is disclosed that includes preparing first and second semiconductor chips, the first semiconductor chip including a first electrode formed on one surface thereof and a second electrode formed on the other surface thereof so as to overlap the first electrode as viewed from a stacking direction, and the second semiconductor chip including a third electrode formed on one surface thereof and a fourth electrode formed on the other surface thereof so as not to overlap the third electrode as viewed from the stacking direction, and stacking the first and second semiconductor chips in the stacking direction so that the second electrode is connected to the third electrode by using a bonding tool including a concave at a position corresponding to the fourth electrode.

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Номер записи: 62
05-07-2012 дата публикации

Semiconductor device

Номер: US20120168927A1
Автор: Shingo Itoh
Принадлежит: Sumitomo Bakelite Co Ltd

A semiconductor device is configured that two or more semiconductor elements are stacked and mount on a lead frame, the aforementioned lead frame is electrically joined to the semiconductor element with a wire, and the semiconductor element, the wire and an electric junction are encapsulated with a cured product of an epoxy resin composition for encapsulating semiconductor device, and that the epoxy resin composition for encapsulating semiconductor device contains (A) an epoxy resin; (B) a curing agent; and (C) an inorganic filler, and that the (C) inorganic filler contains particles having particle diameter of equal to or smaller than two-thirds of a thinnest filled thickness at a rate of equal to or higher than 99.9% by mass.

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Номер записи: 63
12-07-2012 дата публикации

Test Contact System For Testing Integrated Circuits With Packages Having An Array Of Signal and Power Contacts

Номер: US20120176151A1
Автор: Brian K. Warwick, Jeffrey C. Sherry, Patrick J. Alladio, Russell F. Oberg
Принадлежит: Johnstech International Corp

A test fixture ( 120 ) is disclosed for electrically testing a device under test ( 130 ) by forming a plurality of temporary mechanical and electrical connections between terminals ( 131 ) on the device under test ( 130 ) and contact pads ( 161 ) on the load board ( 160 ). The test fixture ( 120 ) has a replaceable membrane ( 150 ) that includes vias ( 151 ), with each via ( 151 ) being associated with a terminal ( 131 ) on the device under test ( 130 ) and a contact pad ( 161 ) on the load board ( 160 ). In some cases, each via ( 151 ) has an electrically conducting wall for conducting current between the terminal ( 131 ) and the contact pad ( 161 ). In some cases, each via ( 151 ) includes a spring ( 152 ) that provides a mechanical resisting force to the terminal ( 131 ) when the device under test ( 130 ) is engaged with the test fixture ( 120 ).

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Номер записи: 64
19-07-2012 дата публикации

Adhesive film for light emitting device and method of manufacturing led package using the same

Номер: US20120181571A1
Автор: II Woo Park, Kyu Jin Lee, Na Na Park
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided is an adhesive film for an LED chip, including: a double-sided adhesive layer having the LED chip adhered to an upper surface thereof and a lead frame adhered to a lower surface thereof; an ultraviolet (UV) cured layer adhered to one surface of the double-sided adhesive layer; and upper and lower cover layers respectively adhered to faces exposed to the exterior of the double-sided adhesive layer and the UV cured layer.

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Номер записи: 65
19-07-2012 дата публикации

Semiconductor Device and Method of Forming Bond Wires and Stud Bumps in Recessed Region of Peripheral Area around the Device for Electrical Interconnection to Other Devices

Номер: US20120181689A1
Автор: Byung Tai Do, Linda Pei Ee CHUA, Reza A. Pagaila
Принадлежит: Stats Chippac Pte Ltd

A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A recessed region with angled or vertical sidewall is formed in the peripheral area. A conductive layer is formed in the recessed region. A first stud bump is formed over a contact pad of the semiconductor die. A second stud bump is formed over the first conductive layer within the recessed region. A bond wire is formed between the first and second stud bumps. A third stud bump is formed over the bond wire and first stud bump. A dicing channel partially formed through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the bond wire and stud bumps.

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Номер записи: 66
26-07-2012 дата публикации

Semiconductor package and method for manufacturing semiconductor package

Номер: US20120187557A1
Автор: Akihiko Tateiwa, Masahiro Kyozuka, Masato Tanaka
Принадлежит: Shinko Electric Industries Co Ltd

A semiconductor package includes a semiconductor chip including a circuit forming surface and a side surface, and a sealing insulation layer that seals the circuit forming surface and the side surface of the semiconductor chip, the sealing insulation layer having a first surface on a side of the circuit forming surface. At least one wiring layer and at least one insulation layer are formed one on top of the other on the first surface. The wiring layer formed on the first surface is electrically connected to the semiconductor chip. The insulation layer has a reinforcement member installed therein.

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Номер записи: 67
26-07-2012 дата публикации

Direct Edge Connection for Multi-Chip Integrated Circuits

Номер: US20120187577A1
Автор: James L. Speidell, John U. Knickerbocker, Matthew J. Farinelli, Peter A. Gruber, Sherif A. Goma, Steven A. Cordes
Принадлежит: International Business Machines Corp

The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

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Номер записи: 68
02-08-2012 дата публикации

Solder, soldering method, and semiconductor device

Номер: US20120193800A1
Автор: Keisuke Uenishi, Nobuhiro Imaizumi, Seiki Sakuyama, Tetsuhiro Nakanishi, Toshiya Akamatsu
Принадлежит: Fujitsu Ltd

A solder includes Sn (tin), Bi (bismuth) and Zn (zinc), wherein the solder has a Zn content of 0.01% by weight to 0.1% by weight.

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Номер записи: 69
02-08-2012 дата публикации

Chip package structure

Номер: US20120196438A1
Автор: Sung-Chuan MA, Tse-Ming CHU
Принадлежит: Individual

The formation of the conductive wire of a chip package consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved.

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Номер записи: 70
16-08-2012 дата публикации

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

Номер: US20120208326A9
Автор: Rajendra D. Pendse
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

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Номер записи: 71
23-08-2012 дата публикации

Device mounting board and method of manufacturing the same, semiconductor module, and mobile device

Номер: US20120211269A1
Автор: Kouichi Saitou, Toshiya Shimizu
Принадлежит: Sanyo Electric Co Ltd

A device mounting board includes: an insulating resin layer; a wiring layer formed on one of the principal surfaces of the insulating resin layer; a protection layer covering the insulating resin layer and the wiring layer; a protruding electrode electrically connected to the wiring layer, the protruding electrode protruding from the wiring layer toward the insulating resin layer and penetrating through the insulating resin layer; a wiring-layer-side convex portion protruding from the wiring layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer; and a resin-layer-side convex portion protruding from the protection layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer.

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Номер записи: 72
23-08-2012 дата публикации

Semiconductor device and method for manufacturing semiconductor device

Номер: US20120211764A1
Автор: Keiji Watanabe, Keishiro Okamoto, Nobuhiro Imaizumi, Tadahiro Imada
Принадлежит: Fujitsu Ltd

A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.

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Номер записи: 73
23-08-2012 дата публикации

Chip package with plank stack of semiconductor dies

Номер: US20120211878A1
Автор: Bruce M. Guenin, Darko R. Popovic, David C. Douglas, Ivan Shubin, Jing Shi, John A. Harada, Matthew D. Giere, Theresa Y. Sze
Принадлежит: Oracle International Corp

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

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Номер записи: 74
30-08-2012 дата публикации

Semiconductor Device and Method of Forming the Device Using Sacrificial Carrier

Номер: US20120217634A9
Автор: Il Kwon Shim, Seng Guan Chow, Yaojian Lin
Принадлежит: Stats Chippac Pte Ltd

A semiconductor device includes a first semiconductor die or component having a plurality of bumps, and a plurality of first and second contact pads. In one embodiment, the first and second contact pads include wettable contact pads. The bumps are mounted directly to a first surface of the first contact pads to align the first semiconductor die or component. An encapsulant is deposited over the first semiconductor die or component. An interconnect structure is formed over the encapsulant and is connected to a second surface of the first and second contact pads opposite the first surface of the first contact pads. A plurality of vias is formed through the encapsulant and extends to a first surface of the second contact pads. A conductive material is deposited in the vias to form a plurality of conductive vias that are aligned by the second contact pads to reduce interconnect pitch.

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Номер записи: 75
30-08-2012 дата публикации

Semiconductor devices and methods of manufacturing semiconductor devices

Номер: US20120217652A1
Автор: David S. Pratt
Принадлежит: Micron Technology Inc

Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed.

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Номер записи: 76
30-08-2012 дата публикации

Multi-chip module package

Номер: US20120217657A1
Автор: Chih-Feng Huang, Chiu-Chih Chiang, Lih-Ming Doong, You-Kuo Wu
Принадлежит: Individual

A multi-chip module package is provided, which includes a first chip mounted on via a first conductive adhesive and electrically connected to a first chip carrier, a second chip mounted on via a second conductive adhesive and electrically connected to a second chip carrier which is spaced apart from the first chip carrier, wherein the second conductive adhesive is made of an adhesive material the same as that of the first conductive material, a plurality of conductive elements to electrically connect the first chip to the second chip and an encapsulant encapsulating the first chip, the first chip carrier, the second chip, the second chip carrier and the plurality of conductive elements, allowing a portion of both chip carriers to be exposed to the encapsulant, so that the first chip and second chip are able to be insulated by the separation of the first and second chip carriers.

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Номер записи: 77
30-08-2012 дата публикации

Semiconductor apparatus, method for manufacturing the same and electric device

Номер: US20120217660A1
Автор: Keishiro Okamoto, Motoaki Tani
Принадлежит: Fujitsu Ltd

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

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Номер записи: 78
20-09-2012 дата публикации

Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer

Номер: US20120235285A1
Автор: Andreas Ott, Joerg Hohage, Matthias Lehr
Принадлежит: Globalfoundries Inc

When forming complex metallization systems on the basis of copper, the very last metallization layer may receive contact regions on the basis of copper, the surface of which may be passivated on the basis of a dedicated protection layer, which may thus allow the patterning of the passivation layer stack prior to shipping the device to a remote manufacturing site. Hence, the protected contact surface may be efficiently re-exposed in the remote manufacturing site on the basis of an efficient non-masked wet chemical etch process.

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Номер записи: 79
20-09-2012 дата публикации

Electronic device and method for producing a device

Номер: US20120235298A1
Автор: Harry Hedler, Markus Brunnbauer, Thorsten Meyer
Принадлежит: INFINEON TECHNOLOGIES AG

An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body.

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Номер записи: 80
20-09-2012 дата публикации

Manufacturing method of semiconductor device, and semiconductor device

Номер: US20120235308A1
Автор: Noriyuki Takahashi
Принадлежит: Renesas Electronics Corp

To suppress the reduction in reliability of a resin-sealed semiconductor device. A first cap (member) and a second cap (member) with a cavity (space formation portion) are superimposed and bonded together to form a sealed space. A semiconductor including a sensor chip (semiconductor chip) and wires inside the space is manufactured in the following way. In a sealing step of sealing a joint part between the caps, a sealing member is formed of resin such that an entirety of an upper surface of the second cap and an entirety of a lower surface of the first cap are respectively exposed. Thus, in the sealing step, the pressure acting in the direction of crushing the second cap can be decreased.

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Номер записи: 81
27-09-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120241942A1
Автор: Takumi Ihara
Принадлежит: Fujitsu Semiconductor Ltd

A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element.

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Номер записи: 82
27-09-2012 дата публикации

Apparatuses and methods to enhance passivation and ild reliability

Номер: US20120241952A1
Автор: Bob Sankman, Richard J. Harries, Sudarashan V. Rangaraj
Принадлежит: Individual

Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.

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Номер записи: 83
27-09-2012 дата публикации

Magnetic integration double-ended converter

Номер: US20120241959A1
Автор: Leif Bergstedt
Принадлежит: Huawei Technologies Co Ltd

The present invention relates to a method of bonding a chip to an external electric circuit. The conductors of the external electric circuit for connection to the chip are formed with physical extensions and the chip is directly bonded to these extensions. The invention also relates to an electric device comprising at least one chip and an external electric circuit. The chip is directly bonded to physical extensions of conductors of the external electric circuit.

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Номер записи: 84
18-10-2012 дата публикации

Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof

Номер: US20120261808A1
Автор: Dioscoro A. Merilo, Henry Descalzo Bathan, Lionel Chien Hui Tay, Zigmund Ramirez Camacho
Принадлежит: Individual

A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

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Номер записи: 85
25-10-2012 дата публикации

Semiconductor device

Номер: US20120267682A1
Автор: Takamitsu Kanazawa, Toshiyuki Hata
Принадлежит: Renesas Electronics Corp

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

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Номер записи: 86
25-10-2012 дата публикации

Die attach film

Номер: US20120270381A1
Автор: Hyo Sook Joo, Hyo Soon Park, Hyun Ju Cho, Jang Soon Kim, Jong Wan Hong, Suk Ky Chang, Yong Su Park
Принадлежит: LG Chem Ltd

Provided are a die attach film, a semiconductor wafer, and a semiconductor packaging method. The die attach film can prevent generation of burrs or scattering of chips in a dicing process, and exhibits excellent expandability and pick-up characteristics in a die pressure-sensitive adhesive process. Further, the die attach film can prevent release, shifting, or deflection of a chip in a wire pressure-sensitive adhesive or molding process. Thus, it is possible to improve embeddability, inhibit warpage of a wafer or wiring substrate, and enhance productivity in a semiconductor packaging process.

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Номер записи: 87
01-11-2012 дата публикации

Contact Metal for Hybridization and Related Methods

Номер: US20120273951A1
Автор: Aaron M. Ramirez, Andreas Hampp, Jonathan GETTY, Scott S. Miller
Принадлежит: Raytheon Co

A contact structure for interconnecting a first substrate to an indium interconnect structure on a second substrate. The contact structure comprises a diffusive layer and a non-oxidizing layer, with a thickness of less than approximately 150 nm, positioned on the diffusive layer for alignment with the indium interconnect.

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Номер записи: 88
08-11-2012 дата публикации

Circuit module and manufacturing method for the same

Номер: US20120281370A1
Автор: Fumikiyo KAWAHARA, Hiroshi Nishikawa, Makoto Fujita
Принадлежит: Murata Manufacturing Co Ltd

A circuit module and a manufacturing method for the same, reduce a possibility that a defect area where an electrically conductive resin is not coated may occur in a shield layer. A mother board is prepared. A plurality of electronic components are mounted on a principal surface of the mother board. An insulator layer is arranged so as to cover the principal surface of the mother board and the electronic components. The insulator layer is cut such that grooves and projections are formed in and on the principal surface of the insulator layer and the insulator layer has a predetermined thickness H. An electrically conductive resin is coated on the principal surface of the insulator layer to form a shield layer. The mother board including the insulator layer and the shield layer both formed thereon is divided to obtain a plurality of circuit modules.

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Номер записи: 89
08-11-2012 дата публикации

Manufacturing method of semiconductor device

Номер: US20120282737A1
Автор: Tetsuharu TANOUE
Принадлежит: Individual

Performing electrolysis plating to a wiring is made possible, aiming at the increasing of pin count of a semiconductor device. Package substrate 3 by which ring shape common wiring 3 p for electric supply was formed in the inner area of bonding lead 3 j in device region 3 v of main surface 3 a is used. Since a plurality of first plating lines 3 r and fourth plating lines 3 u for electric supply connected to common wiring 3 p can be arranged by this, the feeder for electrolysis plating can be arranged to all the land parts on the back. Hereby, it becomes possible to perform electrolysis plating to the wiring of main surface 3 a of package substrate 3 , and the back surface.

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Номер записи: 90
15-11-2012 дата публикации

Electronic device and manufacturing thereof

Номер: US20120286293A1
Автор: Josef Hoeglauer, Ralf Otremba
Принадлежит: INFINEON TECHNOLOGIES AG

An electronic device and manufacturing thereof. One embodiment provides a carrier and multiple contact elements. The carrier defines a first plane. A power semiconductor chip is attached to the carrier. A body is formed of an electrically insulating material covering the power semiconductor chip. The body defines a second plane parallel to the first plane and side faces extends from the first plane to the second plane. At least one of the multiple contact elements has a cross section in a direction orthogonal to the first plane that is longer than 60% of the distance between the first plane and the second plane.

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Номер записи: 91
15-11-2012 дата публикации

Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance

Номер: US20120289001A1
Автор: Anup Bhalla, Francois Hebert, Kai Liu, Ming Sun
Принадлежит: Alpha and Omega Semiconductor Ltd

A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.

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Номер записи: 92
22-11-2012 дата публикации

Method for Producing a Metal Layer on a Substrate and Device

Номер: US20120292773A1
Автор: Hans-Joachim Schulze, Khalil Hosseini
Принадлежит: INFINEON TECHNOLOGIES AG

A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation.

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Номер записи: 93
29-11-2012 дата публикации

Distributed semiconductor device methods, apparatus, and systems

Номер: US20120302006A1
Автор: Hussein I. Hanafi, Paul A. Farrar
Принадлежит: Individual

Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice.

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Номер записи: 94
06-12-2012 дата публикации

High-frequency module manufacturing method

Номер: US20120306063A1
Автор: Jun'ichi KIMURA, Masahisa Nakaguchi, Misao Kanba, Motoyoshi Kitagawa, Takayuki Hiruma, Tomohide Ogura
Принадлежит: Panasonic Corp

In a method of manufacturing a high-frequency module, a resin substrate with a high frequency circuit including an electronic component mounted thereon is placed so that the electronic component faces a resin bath. A resin which is in a non-flowable state in the resin bath is softened until the resin becomes flowable, and air in space formed between the resin substrate and the resin is sucked. The resin substrate is brought into contact with a liquid surface of the resin. The resin is pressurized and allowed to flow into a gap between the resin substrate and the electronic component. The resin is cured so that a resin portion is formed on the resin substrate. A shield metal film is formed on a surface of the resin portion.

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Номер записи: 95
06-12-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120306100A1
Автор: Teruaki Chino
Принадлежит: Shinko Electric Industries Co Ltd

A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.

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Номер записи: 96
06-12-2012 дата публикации

Component-embedded substrate

Номер: US20120307466A1
Автор: Isamu Fujimoto, Masanori Fujidai
Принадлежит: Murata Manufacturing Co Ltd

In a component-embedded substrate, a component and wiring block units are embedded in a component-embedded layer; conductive layers are located on all surfaces of the wiring block units; the component and the wiring block units are arranged such that lower surface side conductive layers of the wiring block units and electrodes of the component contact lower surface side wiring layers; via-hole conductors are located in respective upper positions relative to upper surface side conductive layers of the wiring block units and the electrodes of the component; and upper surface side wiring layers of the component-embedded layer are thus electrically connected to upper surface side conductive layers of the wiring block units, and the electrodes of the component by the via-hole conductors.

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Номер записи: 97
13-12-2012 дата публикации

Apparatus for restricting moisture ingress

Номер: US20120311855A1
Автор: Anna J. Malin, Geoffrey Batchelder, Michael F. Mattes, Paul F. Gerrish, Ralph B. Danzl, Trevor D. Marrott, Tyler Mueller
Принадлежит: MEDTRONIC INC

Apparatus and methods to protect circuitry from moisture ingress, e.g., using a metallic structure as part of a moisture ingress barrier.

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Номер записи: 98
13-12-2012 дата публикации

Semiconductor package, electrical and electronic apparatus including the semiconductor package, and method of manufacturing the semiconductor package

Номер: US20120313244A1
Автор: Ji-Seok HONG, Jong-Gi Lee, Sang-Wook Park
Принадлежит: Individual

In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.

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Номер записи: 99
20-12-2012 дата публикации

Electronic device and manufacturing thereof

Номер: US20120319109A1
Автор: Andreas Schloegl, Marco Seibt, Mario Feldvoss, Michael Treu, Ralf Otremba, Uwe Kirchner, Wolfgang Peinhopf
Принадлежит: INFINEON TECHNOLOGIES AG

An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

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Номер записи: 100