Manufacturing method of gallium nitride substrate

A method of manufacturing a gallium nitride substrate, the method including forming a first buffer layer on a silicon substrate such that the first buffer layer has one or more holes therein; forming a second buffer layer on the first buffer layer such that the second buffer layer has one or more holes therein; and forming a GaN layer on the second buffer layer, wherein the one or more holes of the first buffer layer are filled by the second buffer layer.

APPARATUS AND METHODS FOR MICRO-TRANSFER PRINTING

Semiconductor device and method of manufacturing the same

A semiconductor device includes: a substrate; a nitride semiconductor layer on the substrate; a source electrode, a drain electrode and a gate electrode on the nitride semiconductor layer; and a SiN surface protective film covering the nitride semiconductor layer, wherein a composition ratio Si/N of Si and N that form a Si—N bond of the SiN surface protective film is 0.751 to 0.801.

WRINKLED PATTERN STRUCTURE USING SEMICONDUCTING MATERIAL AND METHOD FOR MANUFACTURING THE SAME

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

According to an embodiment of the present invention, a semiconductor device includes: a first semiconductor layer placed on a substrate; a second semiconductor layer placed on the first semiconductor layer; a gate electrode placed on the second semiconductor layer; a low dielectric layer placed on the second semiconductor layer, and having a first dielectric constant; a high dielectric layer placed on the second semiconductor layer, and having a second dielectric constant which is greater than the first dielectric constant; and source and drain electrodes formed on the second semiconductor layer at a distance from the gate electrode. The gate electrode, the high dielectric layer, and the low dielectric layer are placed on the same plane. As such, the present invention is capable of improving a breakdown voltage. COPYRIGHT KIPO 2017 ...

마이크로-전사 인쇄를 위한 장치 및 방법들

... 일 양상에서는, 목적지 기판의 수신 표면 상에 반도체 디바이스를 어셈블링하기 위한 시스템 및 방법이 개시된다. 다른 양상에서는, 토포그래픽 특징들을 갖는 목적지 기판 상에 반도체 디바이스를 어셈블링하기 위한 시스템 및 방법이 개시된다. 다른 양상에서는, 반도체 디바이스를 인쇄하기 위한 중력-보조 분리 시스템 및 방법이 개시된다. 다른 양상에서는, 반도체 디바이스들을 인쇄하기 위한 전사 디바이스의 다양한 특징들이 개시된다.

Apparatus and methods for micro-transfer-printing

In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.

Halbleiteranordnung und Verfahren zum Herstellen derselben

Eine Halbleiteranordnung umfasst: ein Substrat; eine Nitrid-Halbleiterschicht an dem Substrat; eine Source-Elektrode, eine Drain-Elektrode und eine Gate-Elektrode an der Nitrid-Halbleiterschicht; und eine SiN-Oberflächenschutzschicht, welche die Nitrid-Halbleiterschicht abdeckt, wobei ein Zusammensetzungsverhältnis Si/N von Si und N, die eine Si-N-Verbindung der SiN-Oberflächenschutzschicht bilden, in einem Bereich von 0,751 bis 0,801 liegt.

APPARATUS AND METHODS FOR MICRO-TRANSFER PRINTING

Apparatus and methods for micro-transfer-printing

In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.

APPARATUS AND METHODS FOR MICRO-TRANSFER-PRINTING

In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.

HIGH ELECTRON MOBILITY TRANSISTOR FABRICATION PROCESS ON REVERSE POLARIZED SUBSTRATE BY LAYER TRANSFER

A method including forming a barrier layer on a polar compound semiconductor layer on a sacrificial substrate; coupling the sacrificial substrate to a carrier substrate to form a composite structure wherein the barrier layer is disposed between the polar compound semiconductor layer and the carrier substrate; separating the sacrificial substrate from the composite structure to expose the polar compound semiconductor layer; and forming at least one circuit device. An apparatus including a barrier layer on a substrate; a transistor device on the barrier layer; and a polar compound semiconductor layer disposed between the barrier layer and the transistor device, the polar compound semiconductor layer including a two-dimensional electron gas therein.

Apparatus and methods for micro-transfer-printing

In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.

SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF

Provided are a semiconductor device capable of suppressing electric current collapse with good reproducibility and a manufacturing method thereof. Nitride semiconductor layers (3, 4) are formed on a substrate (1). A source electrode (5), a gate electrode (7), and a drain electrode (6) are formed on the nitride semiconductor layers (3, 4). A SiN surface protective film (8) covers the nitride semiconductor layers (3, 4). The composition ratio of Si and N constituting a Si-N bond of the SiN surface protective film (8) is 0.751 to 0.801. COPYRIGHT KIPO 2017 ...

MANUFACTURING METHOD OF GALLIUM NITRIDE SUBSTRATE

According to one embodiment of the present invention, a manufacturing method of a gallium nitride substrate, capable of preventing meltback of a silicon substrate and GaN comprises the steps of: forming a first buffer layer having at least one hole on a silicon substrate; forming a second buffer layer having at least one hole on the first buffer layer; and forming a GaN layer on the second buffer layer. The hole of the first buffer layer is filled with the second buffer layer. COPYRIGHT KIPO 2018 ...

반도체 장치 및 그 제조 방법

... (과제) 재현성이 좋게 전류 붕괴를 억제할 수 있는 반도체 장치 및 그 제조 방법을 얻는다. (해결 수단) 기판(1)상에 질화물 반도체층(3, 4)이 형성되어 있다. 질화물 반도체층(3, 4)상에 소스 전극(5), 게이트 전극(7) 및 드레인 전극(6)이 형성되어 있다. SiN 표면 보호막(8)이 질화물 반도체층(3, 4)을 덮는다. SiN 표면 보호막(8)의 Si-N 결합을 이루는 Si와 N의 구성비 Si/N이 0.751~0.801이다.

GaN-BASED COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICE, AND MANUFACTURING METHOD THEREOF

The present invention relates to a GaN-based complementary metal oxide semiconductor (CMOS) having a simple structure, which comprises a negative (N)-metal oxide semiconductor field effect transistor (MOSFET) unit and a positive (P)-MOSFET unit separated by trench. The N-MOSFET unit includes an undoped GaN layer and an undoped AlGaN layer formed on the GaN layer, source and drain electrodes installed to be spaced apart from each other on the AlGaN layer, a gate electrode installed by recessing at least a part of the AlGaN layer, and a gate insulating layer formed between the gate electrode and the AlGaN layer. The P-MOSFET unit includes an undoped GaN layer and a P-GaN layer formed on the GaN layer and doped by a P-type, source and drain electrodes installed to be spaced apart from each other on the P-GaN layer, a gate electrode installed by recessing at least a part of the P-GaN layer, and a gate insulating layer formed between the gate electrode and the P-GaN layer. According to the present ...

층 이송에 의해 극성이 반전된 기판 상의 고 전자 이동도 트랜지스터 제조 프로세스

... 희생용 기판 상의 극성 화합물 반도체층 상에 장벽층을 형성하는 단계; 복합 구조체를 형성하기 위해 희생용 기판을 캐리어 기판에 결합하는 단계 -극성 화합물 반도체층과 캐리어 기판 간에 장벽층이 배치됨- ; 극성 화합물 반도체층을 노출시키기 위해 복합 구조체로부터 희생용 기판을 분리하는 단계; 및 적어도 하나의 회로 디바이스를 형성하는 단계를 포함하는 방법. 기판 상의 장벽층; 장벽층 상의 트랜지스터 디바이스; 및 장벽층과 트랜지스터 디바이스 간에 배치되는 극성 화합물 반도체층 -극성 화합물 반도체층은 그 안에 2차원 전자 가스를 포함함- 을 포함하는 장치.

High electron mobility transistor fabrication process on reverse polarized substrate by layer transfer

A method including forming a barrier layer on a polar compound semiconductor layer on a sacrificial substrate; coupling the sacrificial substrate to a carrier substrate to form a composite structure wherein the barrier layer is disposed between the polar compound semiconductor layer and the carrier substrate; separating the sacrificial substrate from the composite structure to expose the polar compound semiconductor layer; and forming at least one circuit device. An apparatus including a barrier layer on a substrate; a transistor device on the barrier layer; and a polar compound semiconductor layer disposed between the barrier layer and the transistor device, the polar compound semiconductor layer including a two-dimensional electron gas therein.

Apparatus and methods for micro-transfer-printing

In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes: a substrate; a nitride semiconductor layer on the substrate; a source electrode, a drain electrode and a gate electrode on the nitride semiconductor layer; and a SiN surface protective film covering the nitride semiconductor layer, wherein a composition ratio Si/N of Si and N that form a Si—N bond of the SiN surface protective film is 0.751 to 0.801 ...

APPARATUS AND METHODS FOR MICRO-TRANSFER-PRINTING

In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.

Apparatus and methods for micro-transfer-printing

In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.

Apparatus and methods for micro-transfer-printing

APPARATUS AND METHODS FOR MICRO-TRANSFER-PRINTING

In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed. In yet another aspect, a method and structure for heat-assisted micro-transfer printing is disclosed.

High electron mobility transistor fabrication process on reverse polarized substrate by layer transfer

For micro-transfer printing apparatus and method

High electron mobility transistor fabrication process on reverse polarized substrate by layer transfer

A method including forming a barrier layer on a polar compound semiconductor layer on a sacrificial substrate; coupling the sacrificial substrate to a carrier substrate to form a composite structure wherein the barrier layer is disposed between the polar compound semiconductor layer and the carrier substrate; separating the sacrificial substrate from the composite structure to expose the polar compound semiconductor layer; and forming at least one circuit device. An apparatus including a barrier layer on a substrate; a transistor device on the barrier layer; and a polar compound semiconductor layer disposed between the barrier layer and the transistor device, the polar compound semiconductor layer including a two-dimensional electron gas therein.

APPARATUS AND METHODS FOR MICRO-TRANSFER-PRINTING

In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.

Apparatus and methods for micro-transfer printing

Apparatus and methods for micro-transfer-printing

In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.

Substrate bonding method and semiconductor device

A first Sn absorption layer is formed on a principal surface of a first substrate, the first Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A second Sn absorption layer is formed on a principal surface of a second substrate, the second Sn absorption layer being made of metal absorbing Sn from AuSn alloy and lowering a relative proportion of Sn in the AuSn alloy. A solder layer made of AuSn alloy is formed at least on one Sn absorption layer of the first and second Sn absorption layers. The first and second substrates are bonded together by melting the solder layer in a state that the first and second substrates are in contact with each other, with the principal surfaces of the first and second substrates facing each other.

Semiconductor Device

According to example embodiments, a semiconductor device includes a first layer and second layer. The first layer includes a nitride semiconductor doped with a first type dopant. The second layer is below the first layer and includes a high concentration layer. The high concentration layer includes the nitride semiconductor doped with the first type dopant and has a doping concentration higher than a doping concentration of the first layer.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Semiconductor apparatus comprised of two types of transistors

A semiconductor apparatus that includes two types of transistors is disclosed. The first semiconductor chip includes the first semiconductor device of a type of GaAs-HEMT, while, the second semiconductor chip includes the second semiconductor device of another type of GaN-HEMT. The second semiconductor device is formed in a SiC substrate, and the first semiconductor chip is mounted in an inactive region of the SiC substrate.

Heterojunction Semiconductor Device for Reducing Parasitic Capacitance

A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer. 1. A semiconductor device , comprising:an active layer made of III-V group semiconductor materials;a source electrode disposed on the active layer;a drain electrode disposed on the active layer;a gate electrode disposed above the active layer and between the source electrode and the drain electrode;a gate field plate disposed above the active layer;an interlayer dielectric covering the source electrode, the drain electrode, the gate field plate, and the gate electrode, the interlayer dielectric having a plurality of inter-gate via holes;an inter-source layer disposed on the interlayer dielectric and electrically connected to the source electrode;an inter-drain layer disposed on the interlayer dielectric and electrically connected to the drain electrode;an inter-gate layer disposed on the interlayer dielectric, wherein the gate field plate is separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer; anda plurality of inter-gate plugs filled into the inter-gate via holes;wherein at least one of the inter-gate via holes positioned on the gate field ...

III-Nitride Device and FET in a Package

One exemplary disclosed embodiment comprises a three-terminal stacked-die package including a field effect transistor (PET), such as a silicon PET, stacked atop a III-nitride transistor, such that a drain of the PET resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a gate of the FET, a second terminal of the package is coupled to a drain of the III-nitride transistor. A third terminal of the package is coupled to a source of the FET. In this manner, devices such as cascoded switches may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.

Stretchable Form of Single Crystal Silicon for High Performance Electronics on Rubber Substrates

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices. 1. A stretchable semiconductor element comprising:a flexible substrate having a supporting surface; anda semiconductor structure having a curved internal surface, wherein at least a portion of said curved internal surface is bonded to said supporting surface of said flexible substrate.2. The stretchable semiconductor element of wherein said semiconductor structure is a bent semiconductor structure.3. The stretchable semiconductor element of wherein said bent semiconductor structure has a wave-shaped claim 2 , wrinkled claim 2 , coiled or buckled conformation.4. The stretchable semiconductor element of wherein said bent semiconductor structure is under strain.5. The stretchable semiconductor element of wherein said bent semiconductor structure is under strain selected over the range of about 1% to about 30%.6. The stretchable semiconductor element of wherein said curved internal surface has at least one convex region claim 1 , at least one concave region or a combination of at least one convex region and at least one concave region.7. The stretchable semiconductor element of wherein said curved internal surface has a contour profile comprising a periodic wave or an aperiodic wave.8. The stretchable semiconductor element of wherein said bent semiconductor structure has a conformation comprising a ...

Apparatus and methods for micro-transfer-printing

In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.

Heterojunction Semiconductor Device for Reducing Parasitic Capacitance

A semiconductor device including an active layer made of III-V group semiconductors, a source electrode and a drain electrode disposed on the active layer, a gate electrode disposed on or above the active layer and between the source electrode and the drain electrode, an interlayer dielectric covering the source electrode, the drain electrode, and the gate electrode and having a plurality of inter-gate via holes. The semiconductor device further includes an inter-source layer, an inter-drain layer, and an inter-gate layer disposed on the interlayer dielectric. The semiconductor device further includes an inter-gate plug filled in the inter-gate via hole and electrically connected to the gate electrode and the inter-gate layer, and a gate field plate being separated from the gate electrode and electrically connected to the gate electrode through the inter-gate layer. 1an active layer;at least one source electrode disposed on the active layer, an orthogonal projection of the source electrode on the active layer forming a source region;at least one drain electrode disposed on the active layer, the drain electrode being separate from the source electrode, and an orthogonal projection of the drain electrode on the active layer forming a drain region;at least one gate electrode disposed above the active layer and between the source electrode and the drain electrode;a gate field plate disposed above the active layer and adjacent to the gate electrode;an interlayer dielectric covering the source electrode, the drain electrode, the gate field plate, and the gate electrode, the interlayer dielectric having at least one first inter-source via hole above the source electrode, at least one first inter-drain via hole above the drain electrode, and at least one inter-gate via hole above the gate field plate;an inter-source layer disposed on the interlayer dielectric and electrically connected to the source electrode through an inter-source plug disposed in the inter-source via ...

Semiconductor Package with Conductive Carrier Integrated Heat Spreader

In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier.

SEMICONDUCTOR DEVICE

A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a source pad, a drain pad, and a source external connecting element. The source electrode, the drain electrode, and the gate electrode are disposed on an active region of the active layer. The source pad is electrically connected to the source electrode and includes a body portion, a plurality of branch portions, and a current diffusion portion. The body portion is at least partially disposed on the active region of the active layer. The current diffusion portion interconnects the body portion and the branch portions. A width of the current diffusion portion is greater than a width of the branch portion and less than a half of a width of the body portion. The source external connecting element is disposed on the body portion and spaced from the current diffusion portion. 1. A semiconductor device , comprising:an active layer having an active region;a source electrode, a drain electrode, and a gate electrode disposed on the active region of the active layer; a body portion at least partially disposed on the active region of the active layer, wherein the body portion of the source pad extends along a first direction;', 'a plurality of branch portions extending along a second direction different from the first direction; and', 'at least one current diffusion portion interconnecting the body portion of the source pad and the branch portions of the source pad and extending along the first direction, wherein a width of the current diffusion portion of the source pad is greater than a width of one of the branch portions of the source pad and less than a half of a width of the body portion of the source pad;, 'a source pad electrically connected to the source electrode, wherein the source pad comprisesa drain pad electrically connected to the drain electrode; andat least one source external connecting element disposed on the body portion of the source pad and spaced ...

System on Integrated Chips and Methods of Forming Same

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die. 1. A package comprising:a first semiconductor die;a second semiconductor die bonded to the first semiconductor die, wherein a first dielectric layer of the first semiconductor die is directly bonded to a second dielectric layer of the second semiconductor die;a third semiconductor die bonded to the first semiconductor die, wherein the first dielectric layer of the first semiconductor die is directly bonded to a third dielectrics layer of the third semiconductor die;a first isolation material disposed around the second semiconductor die and the third semiconductor die, wherein the second semiconductor die is physically separated from the third semiconductor die by the first isolation material; anda redistribution structure electrically connected to the first semiconductor die, the second semiconductor die, and the third semiconductor die.2. The package of claim 1 , wherein the redistribution structure is disposed on an opposing side of the first semiconductor die as the second semiconductor die and the third semiconductor die.3. The package of claim 1 , wherein the redistribution structure is electrically connected to the second semiconductor die by a conductive via extending through a second isolation material claim 1 , and wherein the first semiconductor die is physically separated from the conductive via by the second isolation material.4. The package of claim 3 , wherein the second ...

STRUCTURES AND METHODS FOR PROVIDING ELECTRICAL ISOLATION IN SEMICONDUCTOR DEVICES

Semiconductor package structures and methods of forming the same are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon. 17-. (canceled)8. A method of forming a semiconductor structure , the method comprising:forming a plurality of semiconductor chips, each of the semiconductor chips comprising a substrate with one or more transistors or integrated circuits formed thereon;forming, on a top surface of each of the plurality of semiconductor chips, first solder bumps having a first pitch;flipping the plurality of semiconductor chips having the first solder bumps formed thereon;bonding the flipped plurality of semiconductor chips to a first side of an interposer through the first solder bumps; andbonding the interposer to a printed circuit board (PCB) or package substrate through second solder bumps disposed on a second side of the interposer, the second solder bumps having a second pitch that is greater than the first pitch.9. The method of claim 8 , wherein the flip-chip bonding of the semiconductor chips to the first side of the interposer comprises:bonding the plurality of semiconductor chips to the first side of the interposer in an arrangement that includes air gaps or insulating passivation material separating adjacent semiconductor chips, the air gaps or insulating passivation material providing electrical isolation between the adjacent chips.10. The method of claim 8 , wherein the flip-chip bonding of the semiconductor chips to the first side of the interposer ...

SEMICONDUCTOR DEVICE

According to a first aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first transistor, a second transistor, at least one source terminal, at least one gate terminal, at least one drain terminal, a source wire, a gate wire, a drain wire and a support part. The support part includes two first support-part edges and two second support-part edges. Each of the two first support-part edges is parallel to a first direction, and the two first support-part edges are spaced apart from each other in a second direction that is perpendicular to the first direction. Each of the two second support-part edges is physically connected to the two first support-part edges. The source wire, the gate wire and the drain wire cross at least one of the two second support-part edges in plan view. 1. A semiconductor device comprising:a first transistor that includes a first source electrode, a first drain electrode and a first gate electrode;a second transistor that includes a second source electrode, a second drain electrode and a second gate electrode;at least one source terminal electrically connected to the first source electrode;at least one gate terminal electrically connected to the first gate electrode;at least one drain terminal electrically connected to the second drain electrode;a source wire electrically connected to the first source electrode, the source wire constituting a conduction path between the first source electrode and one of the at least one source terminal;a gate wire electrically connected to the first gate electrode, the gate wire constituting a conduction path between the first gate electrode and one of the at least one gate terminal;a drain wire electrically connected to the second drain electrode, the drain wire constituting a conduction path between the second drain electrode and one of the at least one drain terminal; anda support part that supports the first transistor and the second transistor;wherein ...

Structure and method for cooling three-dimensional integrated circuits

A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

SEMICONDUCTOR DEVICE

A semiconductor device according to an embodiment includes: a first nitride semiconductor layer having a first surface and a second surface; a first source electrode provided on the first surface; a first drain electrode provided on the first surface; a first gate electrode provided on the first surface between the first source electrode and the first drain electrode; a second nitride semiconductor layer having a third surface and a fourth surface, the third surface being provided on the second surface and facing the second surface, and the second nitride semiconductor layer having a smaller band gap than the first nitride semiconductor layer; and a first semiconductor device having a fifth surface provided on the fourth surface and facing the fourth surface with a size equal to or smaller than a size of the fourth surface, the first semiconductor device including a first semiconductor material having a smaller band gap than the second nitride semiconductor layer. 1. A semiconductor device comprising:a first nitride semiconductor layer having a first surface and a second surface;a first source electrode provided on the first surface;a first drain electrode provided on the first surface;a first gate electrode provided on the first surface between the first source electrode and the first drain electrode;a second nitride semiconductor layer having a third surface and a fourth surface, the third surface being provided on the second surface and facing the second surface, and the second nitride semiconductor layer having a smaller band gap than the first nitride semiconductor layer; anda first semiconductor device having a fifth surface provided on the fourth surface and facing the fourth surface with a size equal to or smaller than a size of the fourth surface, the first semiconductor device including a first semiconductor material having a smaller band gap than the second nitride semiconductor layer.2. The semiconductor device according to claim 1 , further comprising:a ...

Structures for Providing Electrical Isolation in Semiconductor Devices

Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon. 1. A semiconductor package structure comprising:a printed circuit board (PCB) or package substrate;an interposer bonded to the PCB or package substrate through first solder bumps disposed on a first side of the interposer, the first solder bumps having a first pitch; anda plurality of semiconductor chips, each of the semiconductor chips (i) being bonded to a second side of the interposer through second solder bumps having a second pitch that is less than the first pitch, and (ii) comprising a substrate with one or more transistors or integrated circuits formed thereon.2. The semiconductor package structure of claim 1 , wherein adjacent semiconductor chips bonded to the interposer are separated by air gaps or insulating passivation material claim 1 , the air gaps or insulating passivation material providing electrical isolation between the adjacent chips.3. The semiconductor package structure of claim 1 , wherein the semiconductor chips are bonded to the second side of the interposer in an arrangement that minimizes distances between adjacent semiconductor chips bonded to the interposer.4. The semiconductor package structure of claim 1 , wherein diameters of the first solder bumps are greater than diameters of the second solder bumps.5. The semiconductor package structure of claim 1 , wherein the interposer comprises silicon material and conductive lines and conductive vias formed ...

Heterostructure Power Transistor with AlSiN Passivation Layer

A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.

SEMICONDUCTOR DEVICE

Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction, each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends. 1. A semiconductor device comprising:a plurality of transistor units including first, second and third transistor units arranged in a first direction in this order, each transistor unit having a plurality of transistors that are coupled to each other along a second direction intersecting the first direction; wherein the source wiring is shared by first and second transistor units,', 'wherein the second portions and third portions are connected to the first portion, and', 'wherein the second portions are coupled to the transistors in the first transistor unit, and the third portions are coupled to the transistors in the second transistor unit;, 'a source wiring having a first portion extending along the second direction, second portions and third portions each extending along the first direction,'} wherein the drain wiring is shared by second and third transistor units,', 'wherein the fifth portions and sixth portions are connected to the fourth portion, and', 'wherein the fifth portions are coupled to the transistors in the second transistor unit, and the sixth portions are coupled to the transistors in the third transistor unit;, 'a drain wiring having a fourth portion extending along the second direction, fifth portions and sixth portions ...

Semiconductor package with redistribution structure and manufacturing method thereof

A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

Dummy Metal with Zigzagged Edges

A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge. 1. An integrated circuit structure comprising:a metal pad;a first dielectric layer over the metal pad;a conductive line over and contacting the first dielectric layer;an under-bump metallurgy over and contacting the conductive line;a first metal plate at a same level as the conductive line; anda second metal plate at the same level as the conductive line, wherein the first metal plate is spaced apart from the second metal plate by a straight elongated space, and wherein the first metal plate comprises a first protruding portion protruding toward the second metal plate, and the first protruding portion crosses the straight elongated space.2. The integrated circuit structure of claim 1 , wherein the first protruding portion protrudes into a recess in the second metal plate.3. The integrated circuit structure of claim 1 , wherein the second metal plate comprises a second protruding portion protruding toward the first metal plate claim 1 , and the second protruding portion crosses the straight elongated space to extend into the first metal plate.4. The integrated circuit structure of claim 1 , wherein each of the first metal plate and the second metal plate comprises a plurality of through-openings therein.5. The integrated circuit structure of further comprising a polymer layer comprising:a first portion filling the straight elongated space; anda second portion overlying the first metal plate and the second metal plate.6. The integrated circuit structure of claim 1 , wherein the first metal plate and the ...

SEMICONDUCTOR DEVICE

A semiconductor device includes an active layer having an active region, a source electrode, a drain electrode, a gate electrode, a source metal layer, a drain metal layer, and a source pad. The source metal layer and the drain metal layer are electrically connected to the source electrode and the drain electrode, respectively. An orthogonal projection of the drain metal layer on the active layer each forms a drain metal layer region. The source pad is electrically connected to the source metal layer. An orthogonal projection of the source pad on the active layer forms a source pad region overlapping the drain metal layer. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region. 1. A semiconductor device , comprising:an active layer having a plurality of active regions spaced apart from each other;a plurality of source electrodes, a plurality of drain electrodes, and a plurality of gate electrodes respectively disposed on the active regions of the active layer, wherein the gate electrodes are electrically connected with each other;a source metal layer electrically connected to the source electrodes;a drain metal layer electrically connected to the drain electrodes, wherein a projection of the drain metal layer on the active layer forms a drain metal layer region; anda source pad disposed on the active region, wherein the source pad is electrically connected to the source metal layer, an orthogonal projection of the source pad on the active layer forms a source pad region that overlaps the drain metal layer region, and an area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.2. The semiconductor device of claim 1 , wherein a projection of the source metal layer on the active layer forms a source metal layer region claim 1 , and the ...

Packages and Methods of Forming Packages

Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM). 1. A structure comprising:a first die embedded in an encapsulant, a first pad being on an active side of the first die, a first die connector being on the first pad, the first pad having a first width and the first die connector having a second width, the first and second widths being measured in a first direction, the first direction being parallel to the active side of the first die;a second die embedded in the encapsulant, a second pad being on an active side of the second die, a second die connector contacting the second pad, the second pad having a third width and the second die connector having a fourth width, the third and fourth widths being measured in the first direction, the fourth width being less than the third width; anda redistribution structure over the encapsulant, the first die, and the second die, the first die being electrically coupled to the second die through the first die connector, the redistribution structure, and the second die connector.2. The structure of claim 1 , wherein the second width is less than the first width.3. The structure of further comprising:a third die connector contacting the second pad, a size of the third die connector being greater than a size of the second die connector.4. The structure of claim 1 , wherein a surface of the first die connector claim 1 , a surface of the second die connector claim 1 , and a surface of the encapsulant are level with each other ...

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT)

HEMT having a drain field plate is provided. The drain field plate is formed in the area between the gate and drain of a HEMT. The drain field plate includes a metal pad that has a larger projection area than the drain pad. The drain field plate and semiconductor layer disposed beneath the drain field plate form a metal-semiconductor (M-S) Schottky structure. The capacitance of the M-S Schottky structure generates capacitance in the semiconductor area, which increases the breakdown voltage of the transistor components of the HEMT. A portion of the substrate under the active area may be removed to thereby increase the heat conductivity and reduce the junction temperature of the transistor components of the HEMT. 1. A method for processing a semiconductor transistor , the semiconductor transistor including a substrate , an epitaxial layer , and a plurality of transistor components that are formed on the epitaxial layer , the method comprising:removing a portion of the substrate that is disposed below a portion of the plurality of transistor components, to thereby expose a portion of a bottom surface of the epitaxial layer;forming an insulating layer on the expose portion of the bottom surface of the epitaxial layer, the insulating layer being made of an electrically insulating material;forming at least one via that extends from a bottom surface of the insulating layer to a bottom surface of at least one of the plurality of the transistor components; anddepositing at least one metal layer on the bottom surface of the insulating layer, on a side wall of the via and on the bottom surface of the at least one of the plurality of transistor components.2. The method of claim 1 , further comprising:applying a solder paste on a bottom surface of the at least one metal layer.3. The method of claim 1 , wherein the step of depositing at least one metal layer includes:depositing a first metal layer on the bottom surface of the insulating layer, on the side wall of the via and on ...

Device and Method for UBM/RDL Routing

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad. 1. A micro-electromechanical systems (MEMS) package structure , comprising:a circuit layer;a MEMS die on the circuit layer;a conductive pillar having a top surface and disposed on the circuit layer adjacent to the MEMS die;an encapsulant on the circuit layer and encapsulating the MEMS die and the conductive pillar; anda polymer layer disposed on the encapsulant and on the top surface of the conductive pillar, wherein the polymer layer defines a recess that exposes at least a portion of the top surface of the conductive pillar.2. The MEMS package structure of claim 1 , further comprising a seed layer within the conductive pillar.3. The MEMS package structure of claim 1 , wherein a sidewall of the conductive pillar directly contacts the encapsulant.4. The MEMS package structure of claim 1 , wherein the polymer layer comprises polyimide (PI) or polybenzoxazole (PBO).5. The MEMS package structure of claim 1 , further comprising an external connector located within the recess and in physical contact with the top surface of the conductive pillar.6. The MEMS package structure of claim 5 , further comprising a package bonded to the external connector.7. The MEMS package structure ...

SURFACE EMITTING LIGHT SOURCE WITH LATERAL VARIANT REFRACTIVE INDEX PROFILE

A micro-LED includes a light emitting device that emits a light beam surface-normally and a plurality of semiconductor layers that modify the light beam. Each semiconductor layer includes a first lateral region and a second lateral region, where the first lateral region and the second lateral region are characterized by different respective refractive indices. The first lateral regions of the plurality of semiconductor layers are arranged in two or more different lateral areas of the semiconductor light source. The second lateral region in each semiconductor layer of the plurality of semiconductor layers includes a semiconductor material with a different respective composition. The plurality of semiconductor layers form a planar optical component that is used to, for example, collimate, converge, diverge, or deflect the light beam emitted by the light emitting device. 1. A semiconductor light source comprising:a light emitting device configured to emit a light beam surface-normally; anda plurality of semiconductor layers epitaxially grown on the light emitting device and forming a planar optical component that is configured to refract and modify a wavefront of the light beam emitted by the light emitting device,wherein each semiconductor layer of the plurality of semiconductor layers includes a first lateral region and a second lateral region, the first lateral region and the second lateral region characterized by different respective refractive indices; andwherein the first lateral regions of different semiconductor layers of the plurality of semiconductor layers are in two or more different lateral areas of the semiconductor light source.2. The semiconductor light source of claim 1 , wherein the second lateral region in each semiconductor layer of the plurality of semiconductor layers includes a semiconductor material with a different respective composition.3. The semiconductor light source of claim 2 , wherein the semiconductor material in the second lateral ...

Structures for Providing Electrical Isolation in Semiconductor Devices

Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon. 1. A semiconductor package structure comprising:a printed circuit board (PCB) or package substrate;an interposer bonded to the PCB or package substrate through first solder bumps disposed on a first side of the interposer; anda plurality of semiconductor chips, each of the semiconductor chips being bonded to a second side of the interposer through second solder bumps;wherein the first solder bumps have diameters of 10 μm or less, and the second solder bumps have diameters of 100 to 300 μm.2. The semiconductor package structure of claim 1 , wherein adjacent semiconductor chips bonded to the interposer are separated by air gaps or insulating passivation material claim 1 , the air gaps or insulating passivation material providing electrical isolation between the adjacent chips.3. The semiconductor package structure of claim 1 , wherein the semiconductor chips are bonded to the second side of the interposer in an arrangement that minimizes distances between adjacent semiconductor chips bonded to the interposer.4. The semiconductor package structure of claim 1 , wherein diameters of the first solder bumps are greater than diameters of the second solder bumps.5. The semiconductor package structure of claim 1 , wherein the interposer comprises silicon material and conductive lines and conductive vias formed in the silicon material claim 1 , the conductive lines and conductive vias being ...

Dummy Metal with Zigzagged Edges

A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.

LIGHT EMITTING DEVICE

A light emitting device includes: a base including: a main body, and a frame disposed on an upper surface of the main body; one or more laser elements disposed on the upper surface of the main body and positioned inward of the frame; and a cover including: a support member that is fixed to an upper surface of the frame and that has an opening inside the frame, and a light transmissive portion that is fixed to the support member and that is disposed so as to close the opening. A first interface, between the light transmissive portion and the support member, is located inward of and lower than a second interface, between the support member and the frame. A portion of the support member that extends at least from an outermost end of the first interface to an innermost end of the second interface has a constant thickness. 1. A light emitting device comprising: a main body, and', 'a frame disposed on an upper surface of the main body;, 'a base comprisingone or more laser elements disposed on the upper surface of the main body and positioned inward of the frame; and a support member that is fixed to an upper surface of the frame and that has an opening inside the frame, and', 'a light transmissive portion that is fixed to the support member and that is disposed so as to close the opening;, 'a cover comprisingwherein a first interface, between the light transmissive portion and the support member, is located inward of and lower than a second interface, between the support member and the frame, andwherein a portion of the support member that extends at least from an outermost end of the first interface to an innermost end of the second interface has a constant thickness.2. The light emitting device according to claim 1 , further comprising:a lens body that is disposed on the support member such that the lens body is above the light transmissive portion.3. The light emitting device according to claim 2 , wherein:a difference between a thermal expansion coefficient of the ...

FRONT-TO-BACK BONDING WITH THROUGH-SUBSTRATE VIA (TSV)

Methods for forming a semiconductor device structure are provided. The method includes bonding a first wafer and a second wafer, and a first transistor is formed in a front-side of the first semiconductor wafer. The method further includes thinning a front-side of the second wafer and forming a second transistor in the front-side of the second wafer. 1. A method for forming a semiconductor device structure , comprising:bonding a first wafer and a second wafer, wherein a first transistor is formed in a front-side of the first wafer;thinning a front-side of the second wafer; andforming a second transistor in the front-side of the second wafer.2. The method as claimed in claim 1 , further comprising:forming at least one first TSV in the second wafer, wherein the first TSV directly contacts a conductive feature of the first wafer; andforming at least one second TSV in the first wafer and the second wafer to directly contact a redistribution (RDL) structure formed over a backside of the first wafer.3. The method as claimed in claim 2 , further comprising:thinning a backside of the first wafer to expose the second TSV.4. The method as claimed in claim 2 , wherein the second TSV has a second height greater than a first height of the first TSV.5. The method as claimed in claim 2 , further comprising:forming a contact plug over the first transistor, wherein a top surface of the contact plug is level with a top surface of the first TSV.6. The method as claimed in claim 1 , further comprising:forming an interconnect structure over the front-side of the second wafer, wherein the interconnect structure is electrically connected to the conductive feature of the first wafer.7. The method as claimed in claim 1 , wherein the step of bonding the first wafer and the second wafer is performed by using a first bonding layer and a second bonding layer claim 1 , and the first bonding layer and the second bonding layer made of silicon oxide claim 1 , silicon oxynitride or silane oxide.8. ...

METHOD OF FABRICATING DIAMOND-SEMICONDUCTOR COMPOSITE SUBSTRATES

A method of fabricating a semiconductor-on-diamond composite substrate, the method comprising: (i) starting with a native semiconductor wafer comprising a native silicon carbidesubstrate on which a compound semiconductor is disposed; (ii) bonding a silicon carbide carrier substrate to the compound semiconductor; (iii) removing the native silicon carbide substrate; (iv) forming a nucleation layer over the compound semiconductor; (v) growing polycrystalline chemical vapour deposited (CVD) diamond on the nucleation layer to form a composite diamond-compound semiconductor-silicon carbide wafer, and (vi) removing the silicon carbide carrier substrate y laser lift-off to achieve a layered structure comprising the compound semiconductor bonded to the polycrystalline CVD diamond via the nucleation layer, wherein in step (ii) the silicon carbide carrier substrate is bonded to the compound semiconductor via a laser absorption material which absorbs laser light, wherein the laser has a coherence length shorter than a thickness of the silicon carbide carrier substrate. 1. A method of fabricating a semiconductor-on-diamond composite substrate , the method comprising:(i) starting with a native semiconductor wafer comprising a native silicon carbide growth substrate on which a compound semiconductor is disposed;(ii) bonding a silicon carbide carrier substrate to the compound semiconductor;(iii) removing the native silicon carbide growth substrate;(iv) forming a nucleation layer over the compound semiconductor;(v) growing polycrystalline CVD diamond on the nucleation layer to form a composite diamond-compound semiconductor-silicon carbide wafer, and(vi) removing the silicon carbide carrier substrate to achieve a layered structure comprising the compound semiconductor bonded to the polycrystalline CVD diamond via the nucleation layer,wherein in step (ii) the silicon carbide carrier substrate is bonded to the compound semiconductor via a laser absorption material which absorbs laser ...

WAFER STRUCTURE AND METHOD FOR WAFER DICING

The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed on a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top surface of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top surface layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the wafer substrate is exposed. 1. A semiconductor die , comprising:a base body with sidewalls;a plurality of protruding portions laterally protruding from the sidewalls respectively; anda plurality of bonding pads disposed on the protruding portions respectively.2. The semiconductor die of claim 1 , wherein the protruding portions of two opposite sidewalls are staggered.3. The semiconductor die of claim 1 , further comprising a seal ring disposed in the base body claim 1 , wherein the sidewalls are located between the seal ring and the bonding pads.4. The semiconductor die of claim 1 , wherein each of the protruding portions has one of the bonding pads disposed thereon.5. The semiconductor die of claim 1 , wherein each of the bonding pads has a width of substantially 90 μm.6. A semiconductor wafer claim 1 , comprising:a first semiconductor die;a second semiconductor die connected to the first semiconductor die;a plurality of bonding pads disposed on a border line between the first semiconductor die and the second semiconductor die; anda scribe line disposed along the bonding pads.7. The semiconductor wafer of claim 6 , wherein the scribe line has a ...

Manufacturing method of gallium nitride substrate

A method of manufacturing a gallium nitride substrate, the method including forming a first buffer layer on a silicon substrate such that the first buffer layer has one or more holes therein; forming a second buffer layer on the first buffer layer such that the second buffer layer has one or more holes therein; and forming a GaN layer on the second buffer layer, wherein the one or more holes of the first buffer layer are filled by the second buffer layer.

Optoelectronic system

An embodiment of the invention discloses an optoelectronics system. The optoelectronic system includes an optoelectronic element having a first width; an adhesive material enclosing the optoelectronic element and having a second width larger than the first width; a phosphor structure formed between the optoelectronic element and the adhesive material; and a transparent substrate formed on the adhesive material.

METHOD FOR APPLYING A BONDING LAYER

A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate. 111-. (canceled)12. Method for bonding a first substrate with a second substrate , said method comprising:applying an oxidizable basic material as a basic layer on a bonding side of the first substrate,at least partially covering the basic layer with a protective layer comprised of a protective material that is at least partially dissolvable in the basic material, said protective layer having a thickness of less than 100 nm,bonding the first and second substrates, wherein the protective material is dissolved completely in the basic material during the bonding.13. The method according to claim 12 , wherein the basic material is oxygen-affine and is comprised of aluminum and/or copper.14. The method according to claim 12 , wherein the step of applying the basic material as the basic layer and/or covering the basic layer with the protective layer is/are carried out by deposition.15. The method according to claim 12 , wherein the protective layer is applied such that the basic layer is sealed at least predominantly relative to the atmosphere.16. The method according to claim 12 , wherein the protective layer is treated before the step of bonding claim 12 , said protective layer treated with one or more of the following processes:(a) chemical oxide removal;(b) physical oxide removal, in particular with plasma; and(c) ion-assisted chemical etching.17. The method according to claim 12 , wherein one or more of the following materials are selected as the basic material and/or the protective material:(a) metals;(b) alkali ...

Semiconductor Package with Conductive Clips

One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadfirame and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. 138-. (canceled)39. A semiconductor package comprising:a control transistor disposed on a leadframe and including a bottom surface having a control source and a control gate and a top surface having a control drain;a sync transistor disposed on said leadframe and including a bottom surface having a sync drain and a top surface having a sync source and a sync gate;a conductive clip electrically coupling said control drain to a first pad of said leadframe, said control source being electrically coupled to said sync drain by a common region of said leadframe;said control gate electrically coupled to a second pad of said leadframe;a driver integrated circuit (IC) disposed on a third pad of said leadframe, said third pad isolated from said common region.40. The semiconductor package of claim 39 , wherein said driver IC is electrically coupled to said sync gate using a wirebond.41. The semiconductor package of claim 39 , wherein said sync source and said sync gate are arranged into a grid.42. The semiconductor package of claim 39 , wherein said semiconductor package is a leadless package.43. The semiconductor package of claim 39 , wherein said conductive clip is attached to said control drain by solder.44. ...

SOLDER-CONTAINING SEMICONDUCTOR DEVICE, MOUNTED SOLDER-CONTAINING SEMICONDUCTOR DEVICE, PRODUCING METHOD AND MOUNTING METHOD OF SOLDER-CONTAINING SEMICONDUCTOR DEVICE

A solder-containing semiconductor device includes a semiconductor device. The semiconductor device includes a substrate, at least one group III nitride semiconductor layer disposed on the substrate, a Schottky electrode disposed on the group III nitride semiconductor layer, and a pad electrode disposed on the Schottky electrode. The pad electrode has a multi-layer structure including at least a Pt layer. The solder-containing semiconductor device further includes a solder having a melting point of 200 to 230° C. and being disposed on the pad electrode of the semiconductor device. Thereby, the solder-containing semiconductor device including the Schottky electrode, the pad electrode disposed on the Schottky electrode and the solder disposed on the pad electrode can be mounted to offer a mounted solder-containing semiconductor device without degrading the semiconductor device properties. 1. A solder-containing semiconductor device comprising a semiconductor device , a substrate;', 'at least one group III nitride semiconductor layer disposed on said substrate;', 'a Schottky electrode disposed on said group III nitride semiconductor layer; and', 'a pad electrode disposed on said Schottky electrode,', 'said pad electrode having a multi-layer structure including at least a Pt layer,, 'the semiconductor device includingthe solder-containing semiconductor device further comprising a solder having a melting point of 200 to 230° C. and being disposed on said pad electrode of said semiconductor device.2. The solder-containing semiconductor device according to claim 1 , whereinsaid solder-containing semiconductor device further includes a dielectric layer having an opening and being disposed on said group III nitride semiconductor layer, andsaid Schottky electrode is disposed on a portion of said group III nitride semiconductor layer that is positioned within said opening of said dielectric layer.3. The solder-containing semiconductor device according to claim 1 , whereinsaid ...

Light emitting device

A light emitting device includes: a base including: a main body, and a frame disposed on an upper surface of the main body; one or more laser elements disposed on the upper surface of the main body and positioned inward of the frame; a cover including: a support member that is fixed on an upper surface of the frame and has an opening inside the frame, and a light transmissive portion disposed so as to close the opening; and a lens body disposed on the support member and above the light transmissive portion. A difference between a thermal expansion coefficient of the light transmissive portion and a thermal expansion coefficient of the lens body is smaller than a difference between a thermal expansion coefficient of the light transmissive portion and a thermal expansion coefficient of the main body.

Chromium/Titanium/Aluminum-based Semiconductor Device Contact

A contact to a semiconductor including sequential layers of Cr, Ti, and Al is provided, which can result in a contact with one or more advantages over Ti/Al-based and Cr/Al-based contacts. For example, the contact can: reduce a contact resistance; provide an improved surface morphology; provide a better contact linearity; and/or require a lower annealing temperature, as compared to the prior art Ti/Al-based contacts.

SEMICONDUCTOR DEVICE AND A METHOD OF MAKING A SEMICONDUCTOR DEVICE

An LED device capable of emitting electromagnetic radiation ranging from about 200 nm to 365 nm, the device. The device includes a substrate member, the substrate member being selected from sapphire, silicon, quartz, gallium nitride, gallium aluminum nitride, or others. The device has an active region overlying the substrate region, the active region comprising a light emitting spatial region comprising a p-n junction and characterized by a current crowding feature of electrical current provided in the active region. The light emitting spatial region is characterized by about 1 to 10 microns. The device includes an optical structure spatially disposed separate and apart the light emitting spatial region and is configured to facilitate light extraction from the active region. 1. A device comprising:a p-n junction for emitting electromagnetic radiation ranging from about 200 nm to 365 nm; andan AlGaN layer disposed over the p-n junction, wherein the AlGaN layer is shaped as a lens and is wider than the p-n junction.2. The device of wherein the p-n junction comprises a mesa comprising a light emitting layer disposed between an n-type region and a p-type region.3. The device of wherein the mesa has a sloped sidewall.4. The device of wherein the p-n junction is a first p-n junction claim 1 , the device further comprising a second p-n junction disposed beneath the lens.5. The device of wherein semiconductor material forming the first p-n junction and the second p-n junction is removed from a region between the first and second p-n junctions.6. The device of wherein the p-n junction is part of an array of p-n junctions disposed beneath the lens.7. A method comprising: an AlGaN layer; and', 'a light emitting layer disposed between an n-type region and a p-type region; and, 'growing a semiconductor structure comprisingshaping the AlGaN layer into a lens.8. The method of wherein growing a semiconductor structure comprises growing the AlGaN layer over a growth substrate and ...

METHOD FOR PERMANENTLY BONDING WAFERS

This invention relates to a method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate with the following steps, especially the following sequence: 1. A method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate comprising the following steps:{'sub': x', '1−x', 'x', '1−x', '2', '2', '2', '2−x', '2−x', '3−y, 'forming a first reservoir in a surface layer on the first contact surface and a second reservoir in a surface layer on the second contact surface, the surface layers of the first and second contact surfaces being comprised of respective native oxide materials of one or more second educts respectively contained in reaction layers of the first and second substrates, the second educts being selected from the group consisting of Ge, Al, GaP, GaAs, InP, InSb, InAs, GaSb, GaN, InN, AlGaAs, InGaN, InAlP, CuInSe, CuInGaSe, CuInGaS, and InSnO;'}partially filling the first and second reservoirs with one or more first educts; andreacting the first educts filled in the first reservoir with the second educts contained in the reaction layer of the second substrate to at least partially strengthen a permanent bond formed between the first and second contact surfaces.2. The method as claimed in claim 1 , wherein the reacting takes place by diffusion of the first educts of the first reservoir into the reaction layer of the second substrate.3. The method as claimed in claim 1 , wherein the reacting takes place at a temperature between room temperature and 200° C. claim 1 , during a maximum 12 day period.4. The method as claimed in claim 1 , wherein the permanent bond has a bond strength of greater than 1.5 J/m.5. The method as claimed in claim 1 , wherein a reaction product is formed in the reaction layer of the second substrate during the reacting claim 1 , said reaction product having a greater molar volume than a molar volume of the second educts contained in the ...

PACKAGES AND METHODS OF FORMING PACKAGES

Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM). 1. A structure comprising:a first die embedded in an encapsulant, a first pad being on an active side of the first die, a first die connector being on the first pad;a second die embedded in the encapsulant, a second pad being on an active side of the second die, a second die connector contacting the second pad and a third die connector contacting the second pad, a size of the third die connector being greater than a size of the second die connector; anda redistribution structure on the encapsulant, the first die, and the second die, the first die being electrically coupled to the second die through the first die connector, the redistribution structure, and the second die connector.2. The structure of claim 1 , wherein the first die comprises processor integrated circuitry claim 1 , and wherein the second die comprises memory integrated circuitry.3. The structure of claim 2 , wherein the second die comprises dynamic random access memory (DRAM).4. The structure of claim 2 , wherein the second die is a Wide Input/Output die or a Wide Input/Output 2 die.5. The structure of claim 2 , wherein the second die is a Low Power Double Data Rate die.6. The structure of claim 1 , wherein the second die is a cache memory of the first die claim 1 , the first die being a processor die.7. The structure of claim 1 , wherein the second die further has a third pad on the active side of the second die claim 1 , a fourth die ...

SENSOR AND MANUFACTURING METHOD THEREOF

Provided is a manufacturing method of a sensor including the following steps. A mold having a cavity is provided. At least one chip is disposed in the cavity. The chip has an active surface and a back surface opposite to each other. The active surface faces toward a bottom surface of the cavity. A polymer material is filled in the cavity to cover the back surface of the chip. A heat treatment is performed, such that the polymer material is solidified to form a polymer substrate. A mold release treatment is performed to isolate the polymer substrate from the cavity. A plurality of conductive lines are formed on a first surface of the polymer substrate. The conductive lines are electrically connected with the chip. 1. A manufacturing method of a sensor , comprising:providing a mold having a cavity;disposing at least one chip in the cavity, wherein the at least one chip has an active surface and a back surface opposite to each other, and the active surface faces toward a bottom surface of the cavity;filling a polymer material in the cavity to cover the back surface of the chip;performing a heat treatment, such that the polymer material is solidified to form a polymer substrate;performing a mold release treatment to isolate the polymer substrate from the cavity; andforming a plurality of conductive lines on a first surface of the polymer substrate, wherein the conductive lines are electrically connected with the at least one chip.2. The manufacturing method of the sensor according to claim 1 , after forming the conductive lines claim 1 , further comprising forming a microchannel structure on the at least one chip.3. The manufacturing method of the sensor according to claim 2 , before forming the microchannel structure claim 2 , further comprising forming a protective layer on the first surface of the polymer substrate claim 2 , wherein the protective layer has an opening claim 2 , and the opening at least exposes a sensing area of the at least one chip.4. The ...

Semiconductor Devices, Multi-Die Packages, and Methods of Manufacture Thereof

Semiconductor device, multi-die packages, and methods of manufacture thereof are described. In an embodiment, a semiconductor device may include: first conductive pillars and second conductive pillars respectively aligned to a first row of first pins and a second row of second pins of a first die, the first pins and the second pins differing in function; a first insulating layer covering surfaces of the first conductive pillars and the second conductive pillars facing away from the first die; first pads disposed on a surface of the first insulating layer facing away from the first die, the first pads substantially aligned to the first conductive pillars; and first traces coupled to the first pads, the first traces extending over a portion of the first insulating layer covering the second conductive pillars. 1. A method , comprising:forming a passivation layer over a front side of a die, the die having a first plurality of signal pins and a plurality of power pins;forming a pillar layer over the passivation layer, the pillar layer comprising a conductive pillar aligned over and coupled to a respective one of each of the first plurality of signal pins and each of the plurality of power pins;depositing a first insulating material layer over the pillar layer, the first insulating material layer having a signal opening formed over each conductive pillar of the first plurality of signal pins;forming a signal pad over each of the signal openings, each signal pad coupled to a respective one of the first plurality of signal pins; andforming a respective signal trace coupled to each signal pad, wherein one or more signal traces overlaps at least one of the conductive pillars of the plurality of power pins.2. The method of claim 1 , further comprising:depositing a second insulating material layer over the signal pads and signal traces.3. The method of claim 1 , further comprising:forming, in the pillar layer, a power bridging line coupling the conductive pillars of each of the ...

Semiconductor Device with a Passivation Layer and Method for Producing Thereof

A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers comprise outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer. The inner and outer edge sides of the third layer are closer to the outer edge side of the electrode than the respective inner and outer edge sides of the first and second layer.

Light-emitting device

A light-emitting device including a light-emitting diode including an n-doped InGaN layer and a p-doped GaN layer, and an active zone including a number m of InGaN-emitting layers each one arranged between two InGaN barrier layers, of which the indium compositions of the emitting layers are different and are greater on the side of the n-doped InGaN layer than on the side of the p-doped GaN layer, and of which the indium compositions of the barrier layers are different and which are greater on the side of the n-doped InGaN layer than on the side of the p-doped GaN layer. An electric power supply supplies the diode with a periodic signal. A controller of the power supply can alter the peak value of the periodic signal according to a spectrum of the light emitted.

Electronic Device and Method for Producing an Electronic Device

An electronic device and a method for producing an electronic device are disclosed. In an embodiment the electronic device includes a first component and a second component and a sinter layer connecting the first component to the second component, the sinter layer comprising a first metal, wherein at least one of the components comprises at least one contact layer which is arranged in direct contact with the sinter layer, which comprises a second metal different from the first metal and which is free of gold.

System on Integrated Chips and Methods of Forming Same

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

Surface Mount Device Package Having Improved Reliability

A semiconductor package for mounting to a printed circuit board (PCB) includes a case comprising a ceramic base, a semiconductor die in the case, a mounting pad under the ceramic base and coupled to the semiconductor die through at least one opening in the ceramic base. The mounting pad includes at least one layer having a coefficient of thermal expansion (CTE) approximately matching a CTE of the ceramic base. The mounting pad includes at least one layer having a low-yield strength of equal to or less than 200 MPa. The mounting pad includes at least one copper layer and at least one molybdenum layer. The semiconductor package also includes a bond pad coupled to another mounting pad under the ceramic base through a conductive slug in the ceramic base. 1. A semiconductor package for mounting to a printed circuit board (PCB) , said semiconductor package comprising:a case comprising a ceramic base; a semiconductor die in said case; anda mounting pad under said ceramic base, and coupled to said semiconductor die through at least one opening in said ceramic base, wherein said mounting pad comprises a first metal layer having a coefficient of thermal expansion (CTE) approximately matching a CTE of said ceramic base and a second metal layer contacting the ceramic base and having a yield strength less than the first metal layer.2. (canceled)3. The semiconductor package of wherein the second metal layer has a low-yield strength of equal to or less than 200 Mpa.4. The semiconductor package of wherein the second metal layer comprises a copper layer and the first metal layer comprises a molybdenum layer.5. The semiconductor package of further comprising a bond pad coupled to another mounting pad under said ceramic base through a conductive slug in said ceramic base.6. The semiconductor package of further comprising a bond pad coupled to another mounting pad under said ceramic base through at least one conductive via in said ceramic base.7. The semiconductor package of wherein ...

PACKAGE STRUCTURE

A package structure is provided. The package structure includes a die, a lead frame, and a conductive glue. The lead frame includes a die pad and a retaining wall structure. The die pad is configured to support the die, and the retaining wall structure surrounds the die. The conductive glue is disposed between the die and the lead frame. 1. A package structure , comprising:a die;a lead frame comprising a die pad and a retaining wall structure, wherein the die pad is configured to support the die and the retaining wall structure surrounds the die; anda conductive glue disposed between the die and the lead frame.2. The package structure of claim 1 , wherein the conductive glue is positioned between the die and the die pad and is positioned between the die and the retaining wall structure.3. The package structure of claim 2 , wherein the retaining wall structure is not lower than the conductive glue between the die and the retaining wall structure.4. The package structure of claim 1 , wherein the retaining wall structure exposes an upper portion of the die.5. The package structure of claim 1 , wherein the retaining wall structure is integrally formed on the die pad.6. The package structure of claim 1 , wherein the die comprises:a substrate;a seed layer on the substrate;an epitaxial layer on the seed layer; anda transistor structure on the epitaxial layer.7. The package structure of claim 6 , wherein the retaining wall structure is higher than a top surface of the seed layer.8. The package structure of claim 6 , wherein a top surface of the conductive glue is higher than or equal to a bottom surface of the seed layer.9. The package structure of claim 6 , wherein the conductive glue electrically connects the lead frame and the seed layer.10. The package structure of claim 6 , wherein the lead frame and the transistor structure are electrically connected by a conductive wire.11. The package structure of claim 6 , wherein a metal layer of a top portion of the transistor ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

There is provided a method for manufacturing a semiconductor device comprising: forming a first organic insulating layer on a semiconductor region; forming a bump base film including an edge portion contacting with the first organic insulating layer; performing heat treatment of the bump base film; and forming a second organic insulating layer so as to cover the edge portion of the bump base film and the first organic insulating layer around the bump base film while contacting with the first organic insulating layer, the second organic insulating layer being provided with a first opening that exposes a surface of the bump base film. 1. A method for manufacturing a semiconductor device comprising:forming a first organic insulating layer on a semiconductor region;forming a bump base film including an edge portion contacting with the first organic insulating layer;performing heat treatment of the bump base film; andforming a second organic insulating layer so as to cover the edge portion of the bump base film and the first organic insulating layer around the bump base film while contacting with the first organic insulating layer, the second organic insulating layer being provided with a first opening that exposes a surface of the bump base film.2. The method for manufacturing a semiconductor device according to claim 1 , wherein the heat treatment of the bump base film is performed before the forming of the second organic insulating layer.3. The method for manufacturing a semiconductor device according to claim 1 , further comprising:etching the first organic insulating layer after the performing of the heat treatment and before the forming of the second organic insulating layer.4. The method for manufacturing a semiconductor device according to claim 3 , wherein a recessed portion depressed from a surface of the first organic insulating layer is formed by the etching of the first organic insulating layer.5. The method for manufacturing a semiconductor device according ...

METHODS FOR PROCESSING HIGH ELECTRON MOBILITY TRANSISTOR (HEMT)

Methods for processing a semiconductor transistor are provided, where the semiconductor transistor includes a substrate, an epitaxial layer, and transistor components that are formed on the epitaxial layer. The method includes: removing a portion of the substrate that is disposed below a portion of the transistor components, to thereby expose a portion of a bottom surface of the epitaxial layer; forming an electrically insulating layer on the exposed portion of the bottom surface of the epitaxial layer; forming a via that extends from a bottom surface of the insulating layer to a bottom surface of one of the transistor components; depositing at least one metal layer on the bottom surface of the insulating layer, on a side wall of the via and on the bottom surface of one of the transistor components; and applying a solder paste to a bottom surface of the at least one metal layer. 1. A method for processing a semiconductor transistor , the semiconductor transistor including a substrate , an epitaxial layer , and a plurality of transistor components that are formed on the epitaxial layer , the method comprising:removing a portion of the substrate that is disposed below a portion of the plurality of transistor components, to thereby expose a portion of a bottom surface of the epitaxial layer;forming an insulating layer on the exposed portion of the bottom surface of the epitaxial layer, the insulating layer being made of an electrically insulating material;forming at least one via that extends from a bottom surface of the insulating layer to a bottom surface of at least one of the plurality of the transistor components;depositing at least one metal layer on the bottom surface of the insulating layer, on a side wall of the via and on the bottom surface of the at least one of the plurality of transistor components; andapplying a solder paste to a bottom surface of the at least one metal layer.2. The method of claim 1 , wherein the step of depositing at least one metal ...

METHOD FOR WAFER DICING

The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed at a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top layer of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the semiconductor wafer is exposed. 1. A wafer dicing method , comprising:forming a plurality of chips on a semiconductor wafer;forming a plurality of bonding pads at a border line between every two of the adjacent chips;forming a scribe line disposed along the bonding pads;forming a photolithographic pattern on a top layer of the semiconductor wafer to expose the scribe line;etching the scribe line to a depth in the semiconductor wafer substantially below the top layer to form an etched pattern; andthinning a back surface of the semiconductor wafer until the etched pattern in the semiconductor wafer is exposed.2. The wafer dicing method of claim 1 , wherein the operation of providing the semiconductor wafer further comprises providing the semiconductor wafer formed from a material including gallium arsenide (GaAs) claim 1 , gallium arsenide-phosphide (GaAsP) claim 1 , indium phosphide (InP) claim 1 , gallium phosphide (GaP) claim 1 , gallium aluminum arsenic (GaAlAs) claim 1 , indium gallium phosphide (InGaP) claim 1 , gallium nitride (GaN) claim 1 , Indium gallium nitride (InGaN) claim 1 , GaN/InGaN on sapphire claim 1 , silicon (Si) claim 1 , germanium (Ge) ...

ENHANCEMENT-MODE III-NITRIDE DEVICES

A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact. 1. A bidirectional switch , comprising:a III-N structure including a conductive channel therein;a first gate electrode and a second gate electrode, the first and second gate electrodes being on the III-N structure; anda first source contact and a second source contact, the first source and second source contacts electrically contacting the conductive channel, wherein the first and second gate electrodes are each between the first and second source contacts; whereinthe first source contact is part of a first electrode and the second source contact is part of a second electrode, the first electrode including a first portion which is between the first and second gate electrodes, and the second electrode including a second portion that is between the first and second gate electrodes, the first gate electrode including a main gate portion and an extending portion, the extending portion extending from the main gate portion towards the second gate electrode, wherein a separation between the conductive channel and the extending portion of the first gate electrode is greater ...

OPTOELECTRONIC SYSTEM

An embodiment of the invention discloses an optoelectronics system. The optoelectronic system includes an optoelectronic element having a top surface, a bottom surface, a plurality of lateral surfaces arranged between the top surface and the bottom surface, and a first electrode arranged on the bottom surface; a wavelength converting material covering a plurality of lateral surfaces; and a reflecting layer, formed on the wavelength converting material which is arranged on the top surface. 1. An optoelectronic system comprising:an optoelectronic element, having a top surface, a bottom surface, a plurality of lateral surfaces arranged between the top surface and the bottom surface, and a first electrode arranged on the bottom surface;a wavelength converting material, covering a plurality of lateral surfaces; anda reflecting layer, formed on the wavelength converting material which is arranged on the top surface.2. The optoelectronic system of claim 1 , further comprising an adhesive arranged between the optoelectronic element and the reflecting layer.3. The optoelectronic system of claim 2 , wherein the adhesive comprises silicone.4. The optoelectronic system of claim 1 , wherein the wavelength converting material is arranged to surround the plurality of lateral surfaces.5. The optoelectronic system of claim 1 , wherein the wavelength converting material directly contacts the plurality of lateral surfaces.6. The optoelectronic system of claim 1 , wherein the wavelength converting material exposes the first electrode.7. The optoelectronic system of claim 1 , wherein the wavelength converting material comprises different kinds of phosphors.8. The optoelectronic system of claim 1 , wherein the reflecting layer is a sheet-like structure.9. The optoelectronic system of claim 1 , wherein the reflecting layer has a portion extending beyond at least one of the plurality of lateral surfaces.10. The optoelectronic system of claim 1 , further comprising a fan-out electrode ...

Method for Fabricating a Semiconductor Package with Conductive Carrier Integrated Heat Spreader

In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier. 114-. (canceled)15. A method for fabricating a semiconductor package , said method comprising:providing a contiguous conductive carrier having a die side and an opposite input/output (I/O) side;providing a control FET and a sync FET of a power converter switching stage, said control FET having a control drain and said sync FET having a sync source;attaching said control drain of said control FET and said sync source of said sync FET to said die side of said contiguous conductive carrier;forming a control conductive carrier attached to said control drain and a sync conductive carrier attached to said sync source from said contiguous conductive carrier;said control conductive carrier and said sync conductive carrier configured to sink heat produced, respectively, by said control FET and said sync FET into a mounting surface for said semiconductor package.16. The method claim 15 , wherein said contiguous conductive carrier comprises a lead frame.17. The method claim 15 , wherein said contiguous conductive carrier is pre-patterned.18. The method claim 15 , wherein said control FET and said sync FET comprise silicon FETs.19. The method claim 15 , wherein said control FET and said sync ...

Semiconductor Package with Integrated Heat Spreader

In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier. 120-. (canceled)21. A semiconductor package comprising:a control conductive carrier connecting said semiconductor package to a mounting surface;a control FET having a control drain attached to said control conductive carrier;said control conductive carrier configured to sink heat produced by said control FET into said mounting surface.22. The semiconductor package of claim 21 , further comprising a sync conductive carrier connecting said semiconductor package to said mounting surface claim 21 , and a sync FET having a sync source attached to said sync conductive carrier.23. The semiconductor package of claim 21 , wherein said control conductive carrier comprises a portion of a lead frame24. The semiconductor package of claim 21 , wherein said control FET comprises a silicon FET.25. The semiconductor package of claim 21 , wherein said control FET comprises a III-Nitride FET.26. The semiconductor package of claim 21 , further comprising a driver integrated circuit (IC) for driving said control FET.27. The semiconductor package of claim 21 , wherein said control FET is part of a power converter switching stage.28. The semiconductor package of claim 27 , wherein said power converter ...

Device and Method for UBM/RDL Routing

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad. 1. A method comprising:forming a redistribution layer (RDL) over a first side of a first die, the first die having a second side opposite the first side, the RDL comprising a first portion and a second portion, the first portion separated from the second portion by insulating material of the RDL, the first portion and the second portion at a same level in the RDL;forming an under bump metallurgy (UBM) layer over the RDL, the UBM layer comprising a UBM trace and a UBM pad, the UBM trace electrically coupling the first portion to the second portion, the UBM pad electrically coupled to the second portion, wherein the UBM trace is formed after the RDL; andforming a first conductive connector over and electrically coupled to the UBM pad.2. The method of claim 1 , further comprising forming a first electrical connector adjacent the first die.3. The method of claim 2 , wherein the RDL and the UBM pad electrically connect the first die to the first conductive connector.4. The method of claim claim 2 , further comprising at least laterally encapsulating the first die and the first electrical connector with a molding compound to form a first package.5. The method of claim claim 2 , ...

SEMICONDUCTOR DEVICE

A semiconductor device includes an active layer having an active region, a source electrode, a drain electrode, a gate electrode, a source metal layer, a drain metal layer, and a source pad. The source metal layer and the drain metal layer are electrically connected to the source electrode and the drain electrode, respectively. An orthogonal projection of the drain metal layer on the active layer each forms a drain metal layer region. The source pad is electrically connected to the source metal layer. An orthogonal projection of the source pad on the active layer forms a source pad region overlapping the drain metal layer. An area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region. 1. A semiconductor device , comprising:an active layer having an active region;a source electrode, a drain electrode, and a gate electrode disposed on the active region of the active layer and extending along a first direction;a source metal layer disposed on the active region and electrically connected to the source electrode;a drain metal layer disposed on the active region and electrically connected to the drain electrode, wherein an orthogonal projection of the drain metal layer on the active layer forms a drain metal layer region; anda source pad disposed on the active region, wherein the source pad is electrically connected to the source metal layer, an orthogonal projection of the source pad on the active layer forms a source pad region that overlaps the drain metal layer region, and an area of an overlapping region between the source pad region and the drain metal layer region is smaller than or equal to 40% of an area of the drain metal layer region.2. The semiconductor device of claim 1 , wherein an orthogonal projection of the source metal layer on the active layer forms a source metal layer region claim 1 , and the semiconductor device further comprises:a drain pad ...

Device and Method for UBM/RDL Routing

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad. 1. A semiconductor device comprising:a first semiconductor die encapsulated within an encapsulant;a through via extending from a first side of the encapsulant to a second side of the encapsulant;a first redistribution layer electrically connected to the first semiconductor die;a dielectric layer over the first redistribution layer;a first conductive material extending through the dielectric layer and in physical contact with a first portion of the first redistribution layer at a first interface, the first interface having a first width;a second conductive material extending through the dielectric layer and in physical contact with the first portion of the first redistribution layer at a second interface, the second interface having a second width less than the first width, the first portion of the first redistribution layer extending continuously from the first interface to the second interface;an external connection in physical contact with the first conductive material; anda dielectric material extending continuously from an interface with the external connection to completely cover a surface of the second conductive material facing away from the through via.2. The ...

Method for fabricating semiconductor device

本发明提供一种半导体装置的制造方法，优点是在将多个半导体元件混合集成而成的半导体装置中，制造时既采用FSA工艺，又可以容易并且确实地安装各半导体元件。该制造方法的特征是：在对应多个半导体激光元件的配置图形的位置分别形成具有开口部(30a、30b)的模板(30)，然后保持模板在配置各半导体激光元件的安装用的晶圆(10A)的主面上。接着，将多个半导体激光元件分散在液体中，通过将分散了多个半导体激光元件的液体流经模板(30)保持的晶圆(10A)上，从而将多个半导体激光元件自行调整地分别嵌入到模板(30)的各开口部(30a、30b)内。

Film-like Adhesive, Connection Structure of Circuit Member and Semiconductor Device

본 발명의 접착제 조성물은 라디칼 발생제, 열가소성 수지, 및 분자 내에 2 이상의 라디칼 중합성기를 갖고 중량 평균 분자량이 3000 내지 30000인 우레탄 (메트)아크릴레이트를 함유하는 것이다.

Two steps for package application mold grinding

本公开的实施例包括半导体封装件及其形成方法。一个实施例是一种方法，包括：将管芯安装到衬底的顶面以形成器件；将管芯和衬底的顶面封装在模塑料中，模塑料在管芯之上具有第一厚度；以及去除管芯之上的模塑料的部分但非所有厚度。该方法还包括对器件执行进一步处理并且去除管芯之上的模塑料的剩余厚度。

Light Emitting Device and Method for the same

실시 예는 제1방향으로 배치되는 제1반도체층, 활성층, 및 제2반도체층을 포함하는 발광 구조물; 및 상기 발광 구조물상에 배치되는 광추출층;을 포함하고, 상기 광추출층은 Al을 포함하고, 상기 Al의 함량은 상기 제1방향으로 상이한 발광소자 및 발광소자 제조방법을 개시한다.

Adhesive composition, circuit connecting material, connection structure of circuit member, and semiconductor device

本发明是粘接剂组合物、电路连接材料、电路构件的连接结构及半导体装置。本发明的粘接剂组合物含有：自由基产生剂、热塑性树脂、分子内具有2个以上的自由基聚合性基团、包含下述通式（B）和/或（C）的结构、包含选自下述通式（D）、（E）和（F）中的至少1种结构、且重均分子量为3000～30000的聚氨酯（甲基）丙烯酸酯、以及分子内具有1以上磷酸基的乙烯基化合物， 通式（C）中，R 5 表示氢、R 6 表示甲基，或者，R 5 表示甲基、R 6 表示氢，

Dislocation filtering systems and methods for layer delivery

반도체 디바이스를 제조하는 방법은 제1 기판 상에 제1 에피택셜 층을 형성하는 단계를 포함한다. 제1 기판은 제1 격자 상수를 가진 제1 반도체 재료를 포함하고 제1 에피택셜 층은 제1 격자 상수와 상이한 제2 격자 상수를 가진 제2 반도체 재료를 포함한다. 방법은 또한 제1 에피택셜 층 상에 그래핀 층을 배치하고 그래핀 층 상에 제2 반도체 재료를 포함하는 제2 에피택셜 층을 형성하는 단계를 포함한다. 이 방법은 기판 재사용성을 증가시키고, 기능성 층들의 방출 속도를 증가시키고, 방출 두께의 정확한 제어를 실현할 수 있다.

Connection Structure of Circuit Member and Circuit Connection Member

본 발명의 접착제 조성물은 라디칼 발생제, 열가소성 수지, 및 분자 내에 2 이상의 라디칼 중합성기를 갖고 중량 평균 분자량이 3000 내지 30000인 우레탄 (메트)아크릴레이트를 함유하는 것이다. The adhesive composition of the present invention is a radical generator, a thermoplastic resin, and a urethane (meth) acrylate having two or more radical polymerizable groups in a molecule and having a weight average molecular weight of 3000 to 30000.

Semiconductor element and manufacturing method thereof

本发明公开一种半导体元件及其制作方法，其中该制作半导体元件的方法为：首先形成一第一半导体层以及一绝缘层于一基底上，然后去除该绝缘层以及该第一半导体层以形成多个开口，形成一第二半导体层于该等开口内，再图案化该第二半导体层、该绝缘层以及该第一半导体层以形成多个鳍状结构。

Electronic component and manufacturing method thereof

Enhancement-mode III-nitride devices

A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.

Substrate bonding method and semiconductor device

LED with self aligned bond pad

A method is disclosed for attaching a bonding pad to the ohmic contact of a diode while reducing the complexity of the photolithography steps. The method includes the steps of forming a blanket passivation layer over the epitaxial layers and ohmic contacts of a diode, depositing a photoresist layer over the blanket passivation layer, opening a via through the photoresist above the ohmic contacts and on the blanket passivation layer, removing the portion of the blanket passivation layer defined by the via to expose the surface of the ohmic contact, depositing a metal layer on the remaining photoresist, and on the exposed portion of the ohmic contact defined by the via, and removing the remaining photoresist to thereby concurrently remove any metal on the photoresist and to thereby establish a metal bond pad on the ohmic contact in the via.

Light emitting diode chip with electrical insulation element

A light emitting diode chip comprising a light emitting diode and a thermally conductive substrate. The light emitting diode is on the substrate with the substrate providing a thermal path from the light emitting diode through the substrate. A mounting pad is also on a substrate and an electrically insulating layer is integral to the substrate. The insulating layer electrically insulates the mounting pad from the light emitting diode. A method for fabricating a light emitting diode chip comprises providing a thermally conductive substrate, forming an electrical insulating layer integral to the substrate and forming a mounting pad on the substrate. A light emitting diode is fabricated and mounted to the substrate, with the light emitting diode electrically insulated from the mounting pad by the electrically insulating layer.

Manufacturing method of semiconductor composite device

LED with self aligned bond pad

A method is disclosed for attaching a bonding pad to the ohmic contact of a diode while reducing the complexity of the photolithography steps. The method includes the steps of forming a blanket passivation layer over the epitaxial layers and ohmic contacts of a diode, depositing a photoresist layer over the blanket passivation layer, opening a via through the photoresist above the ohmic contacts and on the blanket passivation layer, removing the portion of the blanket passivation layer defined by the via to expose the surface of the ohmic contact, depositing a metal layer on the remaining photoresist, and on the exposed portion of the ohmic contact defined by the via, and removing the remaining photoresist to thereby concurrently remove any metal on the photoresist and to thereby establish a metal bond pad on the ohmic contact in the via.

LED with self aligned bond pad

A method is disclosed for attaching a bonding pad to the ohmic contact of a diode while reducing the complexity of the photolithography steps. The method includes the steps of forming a blanket passivation layer over the epitaxial layers and ohmic contacts of a diode, depositing a photoresist layer over the blanket passivation layer, opening a via through the photoresist above the ohmic contacts and on the blanket passivation layer, removing the portion of the blanket passivation layer defined by the via to expose the surface of the ohmic contact, depositing a metal layer on the remaining photoresist, and on the exposed portion of the ohmic contact defined by the via, and removing the remaining photoresist to thereby concurrently remove any metal on the photoresist and to thereby establish a metal bond pad on the ohmic contact in the via.

Heterostructure power transistor with AlSiN passivation layer

一种异质结构半导体器件，包含第一活性层和布置在该第一活性层上的第二活性层。二维电子气层被形成在该第一活性层与该第二活性层之间。AlSiN钝化层被布置在该第二活性层上。第一欧姆接触点和第二欧姆接触点电学连接到该第二活性层。该第一欧姆接触点和该第二欧姆接触点横向间隔开，栅极被布置在该第一欧姆接触点与该第二欧姆接触点之间。

Heterostructure power transistor and method of fabricating a heterostructure semiconductor device

一種異質結構半導體裝置，包含一第一主動層和佈置於該第一主動層上之一第二主動層。一二維電子氣層被形成於該第一主動層與該第二主動層之間。一AlSiN鈍化層被佈置於該第二主動層上。一第一歐姆接觸點和一第二歐姆接觸點電性連接至該第二主動層。該第一歐姆接觸點和該第二歐姆接觸點橫向間隔開，一閘極被佈置於該第一歐姆接觸點與該第二歐姆接觸點之間。

Epitaxial substrate for semiconductor device, semiconductor device, and method for manufacturing epitaxial substrate for semiconductor device

누설 전류가 억제되어 이루어지며 또한 내압이 높은 반도체 소자용의 에피택셜 기판을 제공한다. 반도체 소자용 에피택셜 기판에 있어서, Zn이 도핑된 GaN으로 이루어지는 반절연성의 자립 기판과, 자립 기판에 인접하여 이루어지는 13족 질화물로 이루어지는 버퍼층과, 버퍼층에 인접하여 이루어지는 13족 질화물로 이루어지는 채널층과, 채널층을 사이에 두고서 버퍼층과는 반대쪽에 마련되어 이루어지는 13족 질화물로 이루어지는 장벽층을 포함하고, 자립 기판과 버퍼층으로 이루어지는 제1 영역의 일부가 Si를 1×10 17 cm -3 이상의 농도로 포함하는 제2 영역이고, 제2 영역에 있어서의 Zn의 농도의 최소치가 1×10 17 cm -3 이도록 했다.

QUANTUM WELL ELECTROLUMINESCENT DIODE SEPARATED BY BARRIER LAYERS OF INGAN HAVING VARIABLE INDIUM COMPOSITIONS

Diode électroluminescente (100) comportant une couche d'InXnGa(1-Xn)N dopé n (102) et une couche de GaN dopé p (104), et une zone active (110) comprenant m couches émissives d'InYiGa(1-Yi)N (112) chacune disposée entre deux couches barrières d'InZjGa(1-Zj)N (114), dans laquelle : - pour i compris entre 1 et m-1, les compositions en indium des couches émissives sont telles que Y(i+1) < Yi, la (i+1)ème couche émissive étant disposée entre la (i)ème couche émissive et la couche de GaN dopé p ; - pour j compris entre 1 et m, les compositions en indium des couches barrières sont telles que Z(j+1) < Zj, la (j+1)ème couche barrière étant disposée entre la (j)ème couche barrière et la couche de GaN dopé p ; - pour i = j, les compositions en indium des couches émissives et des couches barrières sont telles que Zj < Yi et Z(j+1) < Yi. An electroluminescent diode (100) having an n-doped InXnGa (1-Xn) N layer (102) and a p-doped GaN layer (104), and an active region (110) comprising m InYiGa emitting layers (1) Yi) N (112) each disposed between two barrier layers of InZjGa (1-Zj) N (114), wherein: for i between 1 and m-1, the indium compositions of the emitting layers are such that Y (i + 1) <Yi, the (i + 1) th emissive layer being disposed between the (i) th emissive layer and the p-doped GaN layer; for j between 1 and m, the indium compositions of the barrier layers are such that Z (j + 1) <Zj, the (j + 1) th barrier layer being disposed between the (j) th barrier layer and the layer p-doped GaN; for i = j, the indium compositions of the emissive layers and the barrier layers are such that Zj <Yi and Z (j + 1) <Yi.

FinFET DEVICE

FinFET 소자가 개시된다. FinFET 소자는 기판, 기판에 형성된 버퍼층, 버퍼층에 핀 형상으로 형성되고, 폭이 20nm 내지 80nm이며, 제1 물질층과 제2 물질층이 접합되어 형성된 이종물질 접합층, 이종물질 접합층을 감싸도록 형성된 유전체층 및 유전체층을 감싸도록 형성된 게이트층을 포함한다. A FinFET device is disclosed. The FinFET device is formed in a fin shape on a substrate, a buffer layer formed on the substrate, and a buffer layer, has a width of 20 nm to 80 nm, and covers a heterogeneous material bonding layer and a heterogeneous material bonding layer formed by bonding the first material layer and the second material layer. And a formed dielectric layer and a gate layer formed to surround the dielectric layer.

Apparatus and method for micro transfer printing

本发明描述一种用于使用微转贴印刷将半导体装置组装于目的地衬底上的设备和方法。例如弹性体或粘弹性体压印器等服贴式转贴装置(102)包含支柱阵列(114)，用于从用于制作可印刷半导体元件(104)的原生衬底(108)拾取所述可印刷半导体元件(104)且将所述可印刷半导体元件(104)转贴到目的地衬底(110)。在某些实施例中，所述可印刷半导体元件(104)在被拾取之前囊封于聚合物层(106)中。在某些实施例中，可在微转贴印刷期间执行等离子体处理(例如，大气等离子体)。可将所述等离子体应用于附接到弹性体转贴元件的装置的底部表面。可使用对底部表面的此处理以提供所述装置与目的地衬底之间的经改进结合，使用外延剥离方法清洁已制造的装置的所述底部表面，及移除薄氧化物层。在某些实施例中，如果所述装置具有背侧金属，那么使用已涂覆有助焊剂的配接金属垫而将所述半导体元件印刷到目的地衬底。在转贴所述装置之后，所述助焊剂可回流，借此留下所述垫与所述装置上的所述背侧金属之间的良好金属连接。在某些实施例中，本发明包含经设计以消除或减小关于凸起的问题的转贴装置。在某些实施例中，使用剃刀剪切所述凸起，使得可印刷半导体元件在印刷操作期间不由所述凸起拾取。

Method for manufacturing diamond semiconductor composite substrate

一种制造钻石半导体复合基板的方法，方法包括以下步骤：(i)从原生半导体晶圆开始，包括化合物半导体设置在其上的原生碳化硅生长基板；(ii)将碳化硅载体基板贴合至化合物半导体；(iii)移除原生碳化硅生长基板；(iv)形成化合物半导体上的成核层；(v)在成核层上生长多晶化学气相沉积(CVD)钻石以形成复合钻石‑化合物半导体‑碳化硅晶圆；以及(vi)通过激光剥离移除碳化硅载体基板以实现层状结构，包括经由成核层贴合至多晶化学气相沉积钻石的化合物半导体。其中在步骤(ii)中，碳化硅载体基板是经由激光吸收材料贴合至化合物半导体，激光吸收材料吸收在相干长度短于碳化硅载体基板的厚度的激光。

Adhesive composition, circuit connecting material, connecting structure for circuit member, and semiconductor device

The adhesive composition of the invention comprises a thermoplastic resin, a radical polymerizing compound, a radical polymerization initiator and a radical polymerization regulator. According to the present invention it is possible to provide an adhesive composition, a circuit connecting material, a connection structure for a circuit member and a semiconductor device whereby curing treatment can be carried out with sufficient speed at low temperature, curing treatment can be carried out with a wide process margin, and adequately stable adhesive strength can be obtained.

Bifet and manufacturing method thereof

본 발명은 하나의 반도체 기판에 이종접합 바이폴라 트랜지스터와 전계효과 트랜지스터가 함께 형성되어 있는 BiFET 및 그 제조방법에 관한 것으로서, 통상의 HBT와 접합 부동 전자 채널 FET(Junction Gate-Floated Electron Channel FET)를 형성하되, 반절연 반도체 기판상에 일정 방향의 유전체막 패턴을 형성한 후에 선택적 에피택시 성장 방법으로 오믹층이 되는 서브콜렉터층과, 채널층이 되는 콜렉터층과, 게이트층이 되는 베이스층과, 에미터층 및 에미터캡층을 순차적으로 형성하고, 후속 공정을 진행하여 삼각 형상의 공동을 주요 특징으로 하는 J-FECFET과 통상의 HBT를 한 기판위에 집적하였으므로, 제작 공정이 간단하고 수율이 향상되고 각 소자의 동작 특성이 향상된다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BiFET having a heterojunction bipolar transistor and a field effect transistor formed together on a semiconductor substrate, and to a method of fabricating the same, and to forming a conventional HBT and a junction gate-floated electron channel FET. After forming a dielectric film pattern in a predetermined direction on the semi-insulating semiconductor substrate, a sub-collector layer serving as an ohmic layer, a collector layer serving as a channel layer, a base layer serving as a gate layer, and an emi by a selective epitaxial growth method The formation of the emitter layer and the emitter cap layer were carried out sequentially, and the subsequent process was performed to integrate the J-FECFET, which is characterized by triangular cavities, and the conventional HBT on one substrate, thereby simplifying the manufacturing process and improving the yield. The operation characteristic of the is improved.

Method for producing diamond / semiconductor composite substrates

Verfahren zum Herstellen eines Halbleiter-auf-Diamant-Verbundsubstrats, das Verfahren umfassend: (i) Ausgehen von einem nativen Halbleiterwafer, der ein natives Siliciumcarbidsubstrat umfasst, auf dem ein Verbundhalbleiter abgelagert wird; (ii) Bonden eines Siliciumcarbidträgersubstrats an den Verbundhalbleiter; (iii) Abtragen des nativen Siliciumcarbidsubstrats; (iv) Ausbilden einer Keimbildungsschicht über dem Verbundhalbleiter; (v) Züchten von polykristallinem, durch chemische Gasphasenabscheidung (CVD) abgelagertem Diamant auf der Keimbildungsschicht zum Ausbilden eines Diamant/Verbundhalbleiter/Siliciumcarbid-Verbundwafers, und (vi) Abtragen des Siliciumcarbidträgersubstrats zum Erzielen einer geschichteten Struktur, die den Verbundhalbleiter umfasst, der über die Keimbildungsschicht an den polykristallinen CVD-Diamant gebondet ist, wobei in Schritt (ii) das Siliciumcarbidträgersubstrat über ein Laserabsorptionsmaterial an den Verbundhalbleiter gebondet wird, das Laserlicht auf einer Kohärenzlänge absorbiert, die kleiner als eine Dicke des Siliciumcarbidträgersubstrats ist, wobei in Schritt (vi) das Siliciumcarbidträgersubstrat durch folgendes vom Verbundhalbleiter abgetragen wird: Erhitzen des Diamant/Verbundhalbleiter/Siliciumcarbid-Verbundwafers auf eine Temperatur von zumindest 100 ºC; Leiten von Laserlicht mit einer Kohärenzlänge, die kleiner als die Dicke des Siliciumcarbidträgersubstrats ist, durch das Siliciumcarbidträgersubstrat, wobei das Laserlicht durch das Laserabsorptionsmaterial absorbiert wird; und Kühlen des Diamant/Verbundhalbleiter/Siliciumcarbid-Verbundwafers nach der Laserlichtaussetzung, wodurch Trennung des Siliciumcarbidträgersubstrats vom Verbundhalbleiter bewirkt wird. A method for producing a semiconductor-on-diamond composite substrate, the method comprising: (i) starting from a native semiconductor wafer comprising a native silicon carbide substrate on which a compound semiconductor is deposited; (ii) bonding a silicon carbide ...

High Electron Mobility Transistor (HEMT)

Hybrid microwave integrated circuit

An integrated microwave transistor amplifier includes a AlGaN/GaN active transistor arrangement on a thinned Si 1-mil heat spreader. Elongated, plated-through vias extend from the source portions of the transistor arrangement through the spreader to a thick gold supporting layer. A matching circuit is defined on a four-mil GaAs substrate, also with a thick gold support layer. A stepped heat sink supports the matching circuit and the active transistor with surfaces coplanar. Bond wires interconnect the matching circuit with the gate or drain connections of the transistor.

Method of manufacturing diamond-semiconductor composite substrate

다이아몬드-반도체 복합체 기판의 제조 방법이 개시된다. 본 발명에 의한 다이아몬드-반도체 복합체 기판의 제조 방법은 (i) 화합물 반도체가 상부에 배치된 천연 탄화규소 기판을 포함하는 모 반도체 웨이퍼로 시작하는 단계; (ii) 탄화규소 캐리어 기판을 상기 화합물 반도체에 결합시키는 단계; (iii) 상기 천연 탄화규소 기판을 제거하는 단계; (iv) 상기 화합물 반도체 위에 핵형성 층을 형성시키는 단계; (v) 상기 핵형성 층 위에 다결정성 화학 증착(CVD) 다이아몬드를 성장시켜 복합체 다이아몬드-화합물 반도체-탄화규소 웨이퍼를 형성시키는 단계, 및 (vi) 상기 탄화규소 캐리어 기판을 제거하여 핵형성 층을 통해 다결정성 CVD 다이아몬드에 결합된 화합물 반도체를 포함하는 적층 구조물을 달성하는 단계를 포함한다. 이 때, 단계 (ii)에서 상기 탄화규소 캐리어 기판은 레이저 광을 흡수하는 레이저 흡수 물질을 통해 화합물 반도체에 결합되며, 여기서 상기 레이저는 상기 탄화규소 캐리어 기판의 두께보다 더 짧은 정합 길이를 갖는 것을 특징으로 한다. A method of making a diamond-semiconductor composite substrate is disclosed. Method for producing a diamond-semiconductor composite substrate according to the present invention (i) starting with a parent semiconductor wafer comprising a natural silicon carbide substrate having a compound semiconductor disposed thereon; (ii) bonding a silicon carbide carrier substrate to the compound semiconductor; (iii) removing the natural silicon carbide substrate; (iv) forming a nucleation layer on the compound semiconductor; (v) growing polycrystalline chemical vapor deposition (CVD) diamond over the nucleation layer to form a composite diamond-compound semiconductor-silicon carbide wafer, and (vi) removing the silicon carbide carrier substrate to achieve a laminate structure comprising a compound semiconductor bonded to polycrystalline CVD diamond through a nucleation layer. Wherein, in step (ii), the silicon carbide carrier substrate is coupled to the compound semiconductor via a laser absorbing material that absorbs laser light, wherein the laser has a matching length shorter than the thickness of the silicon carbide carrier substrate. It is done.

Epitaxial substrate for semiconductor element, semiconductor element, and manufacturing method of epitaxial substrate for semiconductor element

リーク電流が抑制されてなり、かつ、耐圧の高い半導体素子用のエピタキシャル基板を提供する。半導体素子用エピタキシャル基板において、ＺｎがドープされたＧａＮからなる半絶縁性の自立基板と、自立基板に隣接してなる、１３族窒化物からなるバッファ層と、バッファ層に隣接してなる、１３族窒化物からなるチャネル層と、チャネル層を挟んでバッファ層とは反対側に設けられてなる、１３族窒化物からなる障壁層と、を備え、自立基板とバッファ層とからなる第１の領域の一部がＳｉを１×１０１７ｃｍ−３以上の濃度で含む第２の領域であり、第２の領域におけるＺｎの濃度の最小値が１×１０１７ｃｍ−３である、ようにした。

Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure

Embodiments of mechanisms of forming a semiconductor device are provided. The semiconductor device includes a first semiconductor wafer comprising a first transistor formed in a front-side of the first semiconductor wafer. The semiconductor device also includes a second semiconductor wafer comprising a second transistor formed in a front-side of the second semiconductor wafer, and a backside of the second semiconductor wafer is bonded to the front-side of the first semiconductor wafer. The semiconductor device further includes an first interconnect structure formed between the first semiconductor wafer and the second semiconductor wafer, and the first interconnect structure comprises a first cap metal layer formed over a first conductive feature. The first interconnect structure is electrically connected to first transistor, and the first cap metal layer is configured to prevent diffusion and cracking of the first conductive feature.

Method of fabricating diamond-semiconductor composite substrates

Method of making light emitting diode displays

Light emitting diodes (LEDs) and LED bars and LED arrays formed of semiconductive material, such as III-V, and particularly AlGaAs/CaAs material, are formed in very thin structures using organometallic vapor deposition (OMCVD). Semiconductor p-n junctions are formed as deposited using carbon as the p-type impurity dopant. Various lift-off methods are described which permit back side processing when the growth substrate is removed and also enable device registration for LED bars and arrays to be maintained.

Packages and methods of forming packages

Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM).

Substrate bonding method and semiconductor device

Adhesive composition, circuit connecting material, connection structure of circuit member, and semiconductor device

本发明为粘接剂组合物、电路连接材料、电路构件的连接结构及半导体装置。电路构件的连接结构体具备第1电路构件、第2电路构件及作为含粘接剂组合物的电路连接材料的固化物的电路连接构件，粘接剂组合物含自由基产生剂、热塑性树脂和分子内有2个以上自由基聚合性基团且重均分子量3000～30000的聚氨酯(甲基)丙烯酸酯(其含分子内有式(B)和/或通式(C)所示2价有机基团及选自通式(D)、(E)和(F)所示2价有机基团中1种以上基团的聚氨酯(甲基)丙烯酸酯)，第1和第2电路构件中至少一方是挠性电路板， 式中，R 5 及R 6 各自表示氢原子和甲基或各自表示甲基和氢原子，

Adhesive composition, circuit connecting material, connecting structure for circuit member, and semiconductor device

Disclosed is an adhesive composition containing a thermoplastic resin, a radically polymerizable compound, a radical polymerization initiator and a radical polymerization modifier. The adhesive composition can be cured sufficiently quickly at low temperatures while exhibiting sufficiently stable adhesion strength, and has a wide process margin for curing. Also disclosed are a circuit connecting material, a connecting structure for circuit members and a semiconductor device.

System on integrated chips and methods of forming same

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.