Obere Elektrodensperrschicht für RRAM

Verschiedene Ausführungsformen der vorliegenden Anmeldung richten sich an eine resistive Direktzugriffsspeicherzelle (RRAM-Zelle), die eine obere Elektrodensperrschicht aufweist, welche zum Blockieren der Bewegung von Stickstoff oder einem anderen geeigneten nichtmetallischen Element von einer oberen Elektrode der RRAM-Zelle zu einer aktiven Metallschicht der RRAM-Zelle konfiguriert ist. Blockieren der Bewegung des nichtmetallischen Elements kann die Ausbildung einer unerwünschten Schaltschicht zwischen der aktiven Metallschicht und der oberen Elektrode verhindern. Die unerwünschte Schaltschicht würde parasitären Widerstand der RRAM-Zelle erhöhen, sodass die obere Elektrodensperrschicht parasitären Widerstand durch Verhindern der Ausbildung der unerwünschten Schaltschicht verhindern kann.

Memristive Einheit auf Grundlage einer Alkali-Dotierung von Übergangsmetalloxiden

Eine memristive Einheit beinhaltet eine erste leitfähige Materialschicht. Eine Oxidmaterialschicht ist auf der ersten leitfähigen Schicht angeordnet. Eine zweite leitfähige Materialschicht ist auf der Oxidmaterialschicht angeordnet, wobei die zweite leitfähige Schicht eine Metall-Alkali-Legierung aufweist.

Integrierte Schaltkreise; Verfahren zum Herstellen eines integrierten Schaltkreises und Speichermodul

Ausführungsformen der vorliegenden Erfindung betreffen im Allgemeinen integrierte Schaltkreise, Verfahren zum Herstellen eines integrierten Schaltkreises und ein Speichermodul. In einer Ausführungsform der Erfindung wird ein integrierter Schaltkreis mit einer programmierbaren Anordnung bereitgestellt. Die programmierbare Anordnung weist auf: ein Substrat, mindestens eine erste Elektrode, die in oder über dem Substrat angeordnet ist, Ionenleiter-Dotier-Material, das über der mindestens einen ersten Elektrode angeordnet ist, Ionenleiter-Material, das über dem Ionenleiter-Dotier-Material angeordnet ist, und mindestens eine zweite Elektrode, die über dem Ionenleiter-Material angeordnet ist.

Verfahren zum Herstellen eines Festkörperelektrolytmaterialbereichs

Verfahren zum Herstellen eines Festkörperelektrolytmaterialbereichs (16) für ein Speicherelement (10) einer Festkörperelektrolytspeicherzelle (1), – bei welchem der Festkörperelektrolytmaterialbereich (16) aus oder mit einem Chalcogenidmaterial (16') ausgebildet wird, – bei welchem zunächst mindestens ein erster Materialbereich (16'') aus mindestens einem dem Chalcogenidmaterial (16') zugrunde liegenden ersten Material (16-1) in im Wesentlichen reiner Form ausgebildet wird, und zwar aus der Gruppe von Materialien, die gebildet wird von Ge und Si, – bei welchem dann an der so erhaltenen Struktur ein thermischer Behandlungsschritt unter Anwesenheit mindestens eines zweiten dem Chalcogenidmaterial (16') zugrunde liegenden Materials (16-2) durchgeführt wird, und – bei welchem dadurch das Chalcogenidmaterial (16') des Festkörperelektrolytmaterialbereichs (16) erzeugt wird, und zwar mit oder aus einer Verbindung aus der Gruppe, die gebildet wird von GeSex, GeSx, SiSex und SiSx, – wobei das mindestens ...

Solid electrolyte storage cell comprises cathode, anode and solid electrolytes, where anode has intercalation material and metal species, which are unfixed in intercalation material

The storage cell comprises a cathode (2), an anode and solid electrolytes, where the anode has an intercalation material and metal species, which are unfixed in intercalation material. The metal species are silver atoms and ions. The intercalation material has carbon, silicon, inorganic material, electrically conductive organic polymer, material of artificial graphite, oil coke, coal tar, coke, carbon fibers, acetylene, graphite sphere, high-crystalline oil coke, hard carbon. The solid electrolyte is a chalcogenide material (3) and another metal species. Independent claims are also included for the following: (1) a method for manufacturing solid electrolyte storage cell (2) a solid electrolyte storage cell arrangement.

Electrical circuit for electronic system, has arrangement of vertical selection transistors vertically formed in substrate, and gate-electrode-ditches filled with gate-electrode-material

The circuit has an arrangement of vertical selection transistors (120, 121) vertically formed in a substrate and selecting memory cells (110, 111) by selection of a word line (150) and a bit line (140). A primary surface of the substrate defines a horizontal reference plane, and a set of gate-electrode-ditches is filled with a gate-electrode-material. A set of gate-electrodes is connected with the word line that is positioned perpendicular to the gate-electrode-ditches and above the reference plane. Independent claims are also included for the following: (1) an electronic system (2) a method for producing an electrical system.

Verfahren zum Hertstellen einer Speicherzelle, Speicherzelle und Speicherzellen-Anordnung

Mikroelektronische Vorrichtung mit Speicherelementen und Verfahren zu ihrer Herstellung

Memristive device based on reversible intercalated ion transfer between two meta-stable phases

Memristive devices based on ion-transfer between two meta-stable phases in an ion intercalated material are provided. In one aspect, a memristive device is provided. The memristive device includes: a first inert metal contact; a layer of a phase separated material disposed on the first inert metal contact, wherein the phase separated material includes interstitial ions; and a second inert metal contact disposed on the layer of the phase separated material. The first phase of the phase separated material can have a different concentration of the interstitial ions from the second phase of the phase separated material such that the first phase of the phase separated material has a different electrical conductivity from the second phase of the phase separated material. A method for operating the present memristive device is also provided.

Circuit structure and method for programming and re-programming a low power multiple states, electronic fuse(E-fuse)

PROGRAMMABLE MICROELECTRONIC STRUCTURE AS WELL AS PROCEDURE FOR YOUR PRODUCTION AND PROGRAMMING

MEMORY DEVICE AND CBRAM MEMORY WITH INCREASED RELIABILITY

Silver-selenide/chalcogenide glass stack for resistance variable memory

Manufacturing methods for resistance variable material cells

ELECTRODE STRUCTURE FOR USE IN AN INTEGRATED CIRCUIT

Programmable microelectronic devices and methods of forming and programming same

ELECTRICALLY ERASABLE, DIRECTLY OVERWRITABLE, MULTIBIT SINGLE CELL MEMORY ELEMENTS AND ARRAYS FABRICATED THEREFROM

The present invention comprises an electrically operated, directly overwritable, multibit, single-cell memory element. The memory element includes a volume of memory material (36) which defines the single cell memory element, a pair of spacedly disposed contacts (32, 34, 38, 40) for supply electrical input signals to set the memory material to a selected resistance value within a dynamic range, a filamentary portion controlling means disposed between the volume of memory material and at least one of the spacedly disposed contacts. The controlling means defining the size and the position of the filamentary portion during electrical formation of the memory element and limiting the size and confining the location of the filamentary portion during use of the memory element, thereby proving for a high current density within the filamentary portion of the single cell memory element upon input of a very low total current electrical signal to the spacedly disposed contacts.

Three-demensional semiconductor memory devices having double-intersection array and methods of fabricating the same

Two terminal re-writeable non-volatile ion transport memory device

The invention relates to a two terminal re-writeable non-volatile ion transport memory device. The device comprises a re-writeable non-volatile ion transport memory (ME) which has two terminals and comprises a channel potential barrier and an ion memory, wherein the channel potential barrier has first conductivity, and the channel potential barrier and the ion memory are electrically connected with the two terminals. The ion memory comprises movable ions and has second conductivity that is higher than the first conductivity. The channel potential barrier and the ion memory are electrically connected with each other.

Resistive memory having confined filament formation

VARIABLE CAPACITANCE CAPACITOR COMPRISING A LAYER OF MATERIAL AND A METHOD OF VARYING A CAPACITY OF A CAPACITOR

PROCEEDED OF ENGRAVING Of a MICROELECTRONIC DEVICE HAS PROGRAMMABLE MEMORY

La présente invention concerne un procédé de gravure d'un dispositif microélectronique à mémoire programmable (10) comportant un substrat (1) recouvert par au moins les couches successives suivantes : - une première électrode (2) à base d'un premier élément métallique, - une couche (4) de chalcogénure dopé avec un deuxième élément métallique, - une deuxième électrode (5) à base d'un troisième élément métallique, - une couche électriquement conductrice (6) du type barrière de diffusion, et - un masque dur (7), le procédé comprenant une étape consistant à graver à l'aide d'un plasma de gaz inerte au moins le masque dur (7), la couche électriquement conductrice (6), la deuxième électrode (5), et la couche de chalcogénure (4), l'étape de gravure étant caractérisée en ce qu'elle s'effectue par pulvérisation cathodique, à une température strictement inférieure à 150°C, de préférence inférieure à 120°C, et de façon particulièrement préférée à une température inférieure à 100°C.

Microelectronic device manufacturing method, involves disseminating metal ions from ionizable metal layer, and depositing electrode on layer of chalcogenide material containing metal ions to form microelectronic device

La présente invention concerne un procédé de fabrication d'un dispositif microélectronique à mémoire programmable comprenant les étapes consistant à : i. déposer sur une première électrode, une couche intermédiaire d'un matériau comprenant un chalcogénure, ii. irradier par rayonnements ultra-violets la couche intermédiaire de l'étape i, iii. déposer une couche métallique ionisable sur la couche intermédiaire obtenue à l'étape ii, iv. diffuser les ions métalliques, provenant de la couche métallique ionisable de l'étape iii, dans la couche intermédiaire pour former un matériau chalcogénure contenant des ions métalliques, et v. déposer une deuxième électrode sur la couche de matériau chalcogénure contenant des ions métalliques obtenue à l'étape iv, pour former ledit dispositif microélectronique.

ELECTRONIC COMPONENT OPERABLE ELECTROCHEMICALLY AND METHOD OF MANUFACTURING THE ELECTRONIC COMPONENT OPERABLE

L'invention concerne Composant électronique actionnable électrochimiquement comprenant : - un substrat (7) ; - au moins une première et une deuxième électrodes d'actionnement (11, 12); - au moins une première et une deuxième électrodes de mesure (21, 22); - au moins une électrode de stockage configurée pour libérer des ions (3) sous l'action des électrodes d'actionnement ; - au moins un conducteur ionique (4) conducteur desdits ions et situé dans une région disposée entre lesdites électrodes de mesure ; - un dispositif adapté pour : ○ appliquer une tension ou un courant entre les première et deuxième électrodes d'actionnement pour permettre la migration d'ions de l'électrode de stockage vers la première électrode d'actionnement formant sur celle-ci un dépôt électrochimique à travers le conducteur ionique et ○ pour mesurer entre les première et deuxième électrodes de mesure une modification d'au moins une caractéristique de la région disposée entre les première et deuxième électrodes de ...

저항 메모리 소자 및 그 형성방법

... 저항 메모리 소자 및 그 형성방법이 제공된다. 이 저항 메모리 소자는 기판 상의 제1 전극과 제2 전극, 제1 전극과 제2 전극 사이의 전이금속 산화물층, 제2 전극과 전이금속 산화물층 사이의 전해질층, 및 전해질층 내의 제2 전극과 전기적으로 접하는 일 단을 포함하는 도전 브릿지를 포함한다.

MEMORY CELL

Semiconductor memory device with three dimensional solid electrolyte structure and manufacturing method thereof

RESISTIVE MEMORY HAVING CONFINED FILAMENT FORMATION

... 국한된 필라멘트 형성을 구비하는 저항성 메모리가 여기에서 설명된다. 하나 이상의 방법 실시예는 실리콘 재료 및 실리콘 재료 상의 산화물 재료를 갖는 적층체에 개구부를 형성하는 단계, 및 실리콘 재료에 인접하여 개구부에 산화물 재료를 형성하는 단계를 포함하되, 개구부에 형성된 산화물 재료는 저항성 메모리 셀에서의 필라멘트 형성을 개구부에 형성된 산화물 재료에 의해 에워싸인 구역으로 국한한다.

선택 디바이스를 구비한 3차원 메모리 어레이

... 3차원 메모리 어레이 그 형성 방법이 제공된다. 3차원 메모리 어레이의 한 예는, 적어도 하나의 절연 물질에 의해 서로로부터 분리되는 복수의 제 1 전도 라인을 포함하는 스택과, 상기 복수의 제 1 전도 라인에 실질적으로 수직으로 연장되도록 배열되는 적어도 하나의 전도 연장부 - 적어도 하나의 전도 연장부가 상기 복수의 제 1 전도 라인 각각과 교차함 - 를 포함할 수 있다. 저장 요소 물질은 적어도 하나의 전도 연장부 주위로 배열되고, 선택 디바이스는 저장 요소 물질 주위로 배열된다. 저장 요소 물질은 복수의 제 1 전도 라인을 분리시키는 절연 물질에 반경 방향으로 인접하여 위치하고, 상기 저장 요소 물질 주위로 배열되는 복수의 물질은 상기 복수의 제 1 전도 라인 각각과 반경 방향으로 인접하여 위치한다.

ELECTRICALLY ACTUATED DEVICE AND METHOD OF CONTROLLING THE FORMATION OF DOPANTS THEREIN

NON-VOLATILE MEMORYU HAVING 3D ARRAY OF READ/WRITE ELEMENTS WITH VERTICAL BIT LINES AND LATERALLY ALIGNED ACTIVE ELEMENTS AND METHODS THEREOF

RESISTIVITY MEMORY DEVICE CARRYING THE STABLE OPERATING VOLTAGE AND ON/OFF RATIO

PURPOSE: A resistivity memory device is provided, which makes high operation speed possible by the resistance conversion property that the current value flowing into the resistant layer changes. CONSTITUTION: A resistivity memory device comprises the storage node connected to the switching structure(10) and switching element. The storage node comprises the bottom electrode(11), the first layer(12), the second layer(13) and the upper electrode(14). The bottom electrode is successively laminated. The first layer includes one or more material among O, S, Se or Te. The second level is formed on the first layer and is one or more material of Cu or Ag. The upper electrode is formed on the second layer. © KIPO 2009 ...

METHOD FOR FABRICATING HIGH DENSITY PILLAR STRUCTURES BY DOUBLE PATTERNING USING POSITIVE PHOTORESIST

Reduced diffusion in metal electrode for two-terminal memory

Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.

Dual oxide analog switch for neuromorphic switching

Exemplary semiconductor structures for neuromorphic applications may include a first layer overlying a substrate material. The first layer may be or include a first oxide material. The structures may include a second layer disposed adjacent the first layer. The second layer may be or include a second oxide material. The structures may also include an electrode material deposited overlying the second layer.

Memory devices and methods of fabricating the same

Electroless plating of metal caps for chalcogenide-based memory devices

A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first conductive material over a substrate, depositing an insulating layer over the first conductive material and the substrate, forming an opening in the insulating layer to expose at least a portion of the first conductive material, depositing a second conductive material over the insulating layer and within the opening, removing portions of the second conductive material to form a conductive area within the opening, recessing the conductive area within the opening to a level below an upper surface of the insulating layer, forming a cap of a third conductive material over the recessed conductive area within the opening, the third conductive material selected from the group consisting of cobalt, silver, gold, copper, nickel, palladium, platinum, and alloys thereof, depositing a stack of a chalcogenide based memory cell material over the cap ...

DUAL INSULATING LAYER DIODE WITH ASYMMETRIC INTERFACE STATE AND METHOD OF FABRICATION

An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. The diode is a metal-insulator diode having a first metal layer, a first insulating layer, a second insulating layer and a second metal layer. At least one asymmetric interface state is provided at the intersection of at least two of the layers to increase the ratio of the diode's on-current to its reverse bias leakage current. In various examples, the asymmetric interface state is formed by a positive or negative sheet charge that alters the barrier height and/or electric field at one or more portions of the diode. Two-terminal devices such as passive element memory cells can utilize the diode as a steering element in series with a state change element. The devices can be formed using pillar structures at the intersections of upper and lower conductors.

NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS AND READ/WRITE CIRCUITS AND METHOD THEREOF

A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.

3-DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING SAME

Embodiments according to the present invention relate to a 3-dimensional non-volatile memory device and a method of manufacturing same. The 3-dimensional non-volatile memory device according to an embodiment includes: a plurality of conductive lines spaced apart from each other in parallel; a plurality of flat plates crossing the plurality of conductive lines, and being spaced apart from each other in parallel; and non-volatile information storage layer patterns respectively disposed between intersecting areas of the plurality of conductive lines and the plurality of conductive flat plates.

NANOPARTICLE ASSEMBLY-BASED SWITCHING DEVICE

The present invention relates to a switching device fabricated by using nanoparticles and a preparation method thereof. The present invention ensures the mass production of switching devices (e.g., memristor) by use of nanoparticles that exhibits reversible switching behavior at current of less than mA and at room temperature (25°C) 〧 250°C in a more convenient and economical manner. Predictions of the high potential of memristors based on nanoparticle assemblies are supported by the tremendous versatility to tune the electrical behavior of nanoparticles by controlling their nanoscale characteristics such as size, composition, dimension, surface area, and chemical potential.

NONVOLATILE RESISTANCE CHANGE ELEMENT

According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode and a first layer. The first electrode includes a metal element. The second electrode includes an n type semiconductor. The first layer is formed between the first electrode and the second electrode and includes a semiconductor element. The first layer includes a conductor portion made of the metal element. The conductor portion and the second electrode are spaced apart.

MEMORY USING MIXED VALENCE CONDUCTIVE OXIDES

A memory using a mixed valence conductive oxides. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and an electrolytic tunnel barrier that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

Information recording and reproducing apparatus

There is proposed a nonvolatile information recording and reproducing device with low power consumption and high thermal stability. The information recording and reproducing apparatus according to an aspect of the present invention includes a recording layer and a unit for recording information by applying a voltage to the recording layer to generate a state change in the recording layer. The recording layer being configured to include at least a first compound having a hollandite structure.

Front to back resistive random access memory cells

A resistive random access memory cell formed in an integrated circuit includes a first resistive random access memory device including an anode and a cathode, a second resistive random access memory device including an anode and a cathode, the cathode of the second resistive random access memory device connected to the anode of the first resistive random access memory device, a programming transistor having a first source/drain terminal connected to a programming potential node, a second source/drain terminal connected to the anode of the first resistive random access memory device and the cathode of the second resistive random access memory device, and a gate connected to a program-enable nod, and at least one switch transistor having a gate connected to the anode of the first resistive random access memory device and the cathode of the second resistive random access memory device.

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

Implementations of the disclosed technology provide an electronic device including a semiconductor memory and a method for fabricating the same, in which processes are easily performed and the characteristics of a variable resistance element are improved. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a substrate; a conductive contact plug formed over the first conductive layer and including a stack of a conductive low-resistance structure and a conductive planarizing layer; and a variable resistance pattern coupled to the contact plug, wherein the low-resistance structure comprises a diffusion barrier layer, a low-resistance material layer and a gap-fill layer.

Memristive RF switches

A memristive radio frequency (RF) switch circuit comprises a first metal electrode and a second metal electrode arranged on an insulating substrate and separated by an air gap, wherein the air gap is fifty nanometers (50 nm) or less, and wherein applying and removing an enabling voltage to the memristive RF switch enables the memristive RF switch to pass RF signals between the first electrode and the second electrode even when the enabling voltage is removed from the memristive switch, and wherein applying and removing a disabling voltage to the memristive switch disables the memristive switch.

Memory circuit having memory cells which have a resistance memory element

In a memory circuit having memory cells which are connected in series between a ground line PL and a bit line BL and in each case have a resistance memory element said element having a bipolar switching behavior having an anode electrode and a cathode electrode, and a drive transistor connected in parallel with the resistance memory element, the drive transistors of the memory cells in each case are connected to a word line in order to switch the drive transistor on and off in such a way that a current path is formed via the associated drive transistor in a non-activated state of a memory cell and a current path is formed via the associated resistance memory element in an activated state of a memory cell, a first changeover switch being arranged at one end and a second changeover switch at other ends of the series of memory cells in order alternately to produce a connection between the series-connected memory cells and the ground line and the bit line in a manner dependent on an applied ...

Electronic memory device

An electronic device includes a first electrode, a second electrode, and a solid electrolyte made of an ion-conducting material, the first and second electrodes being configured to form a metal dendrite. The device further includes a third electrode, an interface layer contacting the third electrode and a third surface of the electrolyte, the interface layer being an ionic insulator and an electronic insulator. The third electrode and the dendrite are arranged such that the device has two resistive states.

Electrode structures and method to form electrode structures that minimize electrode work function variation

Electrode structures, variable resistance memory devices, and methods of making the same, which minimize electrode work function variation. Methods of forming an electrode having a minimized work function variation include methods of eliminating concentric circles of material having different work functions. Exemplary electrodes include electrode structures having concentric circles of materials with different work functions, wherein this difference in workfunction has been minimized by recessing these materials within an opening in a dielectric and forming a third conductor, having a uniform work function, over said recessed materials.

Structure for amorphous carbon based non-volatile memory

A memory device including at least one first memory element comprising a first layer of amorphous carbon over at least one second memory element comprising a second layer of amorphous carbon. The device also includes at least one first conductive layer common to the at least one first and the at least one second memory elements.

Nonvolatile memory device and method for manufacturing same

According to one embodiment, a nonvolatile memory device includes a first wiring layer. The device includes a second wiring layer intersecting with the first wiring layer. And the device includes a first memory layer provided at a position where the first wiring layer and the second wiring layer intersect. And the first memory layer contacts with the first wiring layer, and the first wiring layer is a layer which is capable of supplying a metal ion to the first memory layer.

Multiple data state memory cell

A programmable multiple data state memory cell including a first electrode layer formed from a first conductive material, a second electrode layer formed from a second conductive material, and a first layer of a metal-doped chalcogenide material disposed between the first and second electrode layers. The first layer providing a medium in which a conductive growth can be formed to electrically couple together the first and second electrode layers. The memory cell further includes a third electrode layer formed from a third conductive material, and a second layer of a metal-doped chalcogenide material disposed between the second and third electrode layers, the second layer providing a medium in which a conductive growth can be formed to electrically couple together the second and third electrode layers.

Memory Arrays and Methods of Forming Memory Arrays

Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines over the first series of access/sense lines and which extend along a second direction substantially orthogonal to the first direction, and memory cells vertically between the first and second series of access/sense lines. Each memory cell is uniquely addressed by a combination of an access/sense line from the first series and an access/sense line from the second series. The memory cells have programmable material. At least some of the programmable material within each memory cell is a polygonal structure having a sidewall that extends along a third direction which is different from the first and second directions. Some embodiments include methods of forming memory arrays.

Fabrication methods of conducting bridge random access memory (CBRAM) device structures

A method of forming a conductive bridging memory cell can include forming an active electrode layer above a barrier layer formed on a lower conductive layer; forming at least one ion conductor layer over an active electrode layer; incorporating conductive ions into the ion conductor layer to create a switch memory layer that changes impedance in response to an electric field; and the active electrode layer is a source of conductive ions for the ion conductor, and the barrier layer substantially prevents a movement of conductive ions therethrough.

Semiconductor memory device

A semiconductor memory device comprises a semiconductor substrate; a memory block formed on the semiconductor substrate and including plural stacked cell array layers of cell arrays each comprising a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of contacts extending in the stack direction of the cell array layers and connecting the first lines in the cell arrays with diffusion regions formed on the semiconductor substrate. A certain one of the cell array layers is smaller in the number of the first lines divided and the number of contacts connected than the cell array layers in a lower layer located closer to the semiconductor substrate than the certain one.

Nonvolatile memory devices that use resistance materials and internal electrodes, and related methods and processing systems

A nonvolatile memory device, a method of fabricating the nonvolatile memory device and a processing system including the nonvolatile memory device. The nonvolatile memory device may include a plurality of internal electrodes that extend in a direction substantially perpendicular to a face of a substrate, a plurality of first external electrodes that extend substantially in parallel with the face of the substrate, and a plurality of second external electrodes that also extend substantially in parallel with the face of the substrate. Each first external electrode is on a first side of a respective one of the internal electrodes, and each second external electrode is on a second side of a respective one of the internal electrodes. These devices also include a plurality of variable resistors that contact the internal electrodes, the first external electrodes and the second external electrodes.

Three dimensional stacked semiconductor memory device

A semiconductor memory device may include: a plurality of row lines extended in parallel to each other in a first horizontal direction; a plurality of column line stacks extended in parallel to each other in a second horizontal direction perpendicular to the first horizontal direction, wherein each of the plurality of column line stacks includes a plurality of column lines extended in parallel to each other in a vertical direction; and a plurality of cell pillars that pass vertically through the column lines of the column line stacks, each of the plurality of cell pillars has a first end and a second end, wherein the first ends of the plurality of cell pillars are electrically coupled to the plurality of row lines, and the second ends of the plurality of cell pillars are floated. Each cell pillar includes a core and variable resistance memory layers.

Optical ovonic threshold switch

A method and device for accomplishing transformation of a switching material from a resistive state to a conductive state. The method utilizes a non-electrical source of energy to effect the switching transformation. The switching material may be a chalcogenide switching material, where the non-electrical source of energy initiates switching by liberating lone pair electrons from bound states of chalcogen atoms. The liberated lone pair electrons form a conductive filament having the characteristics of a solid state plasma to permit high current densities to pass through the switching material. The device includes a switching material with electrical contacts and may be interconnected with other elements in a circuit to regulate electrical communication therebetween.

Method of forming a chalcogenide comprising device

A method of metal doping a chalcogenide material includes forming a metal over a substrate. A chalcogenide material is formed on the metal. Irradiating is conducted through the chalcogenide material to the metal effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal outwardly into the chalcogenide material. A method of metal doping a chalcogenide material includes surrounding exposed outer surfaces of a projecting metal mass with chalcogenide material. Irradiating is conducted through the chalcogenide material to the projecting metal mass effective to break a chalcogenide bond of the chalcogenide material at an interface of the projecting metal mass outer surfaces and diffuse at least some of the projecting metal mass outwardly into the chalcogenide material. In certain aspects, the above implementations are incorporated in methods of forming non-volatile resistance variable devices ...

Device fabrication

Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.

MEMORY ELEMENT AND MEMORY DEVICE

A memory element with a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, an ion source layer provided on the second electrode side, an intermediate layer provided between the resistance change layer and the ion source layer, and a barrier layer provided at least either between the ion source layer and the intermediate layer, or between the intermediate layer and the resistance change layer.

MEMORY DEVICE

According to one embodiment, a memory device includes a first electrode, a second electrode and a variable resistance layer. The second electrode includes a metal. The metal is more easily ionizable than a material of the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The variable resistance layer includes a first layer and a second layer. The first layer has a relatively high crystallization rate. The second layer contacts the first layer. The second layer has a relatively low crystallization rate. The first layer and the second layer are stacked along a direction connecting the first electrode and the second electrode. 110-. (canceled)11. A memory device , comprising:a first electrode;a second electrode including a metal, the metal being more easily ionizable than a material of the first electrode; anda variable resistance layer disposed between the first electrode and the second electrode, a first layer having a first crystallization rate;', 'a second layer having a second crystallization rate lower than the first crystallization rate; and', 'an oxide layer disposed between the first layer and the second layer,, 'the variable resistance layer includingthe first layer, the oxide layer, and the second layer being stacked along a direction connecting the first electrode and the second electrode.12. The device according to claim 11 , further comprising a metal layer disposed between the first electrode and the variable resistance layer claim 11 , the metal layer including nickel claim 11 ,the first layer being nearer to the first electrode than the second layer,the variable resistance layer including silicon,the second electrode including silver.1320-. (canceled)21. The device according to claim 11 , wherein the first layer and the second layer include silicon claim 11 , and the oxide layer includes silicon and oxygen.22. The device according to claim 11 , wherein the crystallization rate of the first ...

PCRAM cell manufacturing

An exemplary embodiment of the present invention includes a method for forming a programmable cell by forming an opening in a dielectric material to expose a portion of an underlying first conductive electrode, forming a recessed chalcogenide-metal ion material in the opening and forming a second conductive electrode overlying the dielectric material and the chalcogenide-metal ion material. A method for forming a recessed chalcogenide-metal ion material comprises forming a glass material to be recessed approximately 50% or less, in the opening in the dielectric material, forming a metal material on the glass material within the opening and diffusing metal ions from the metal material into the glass material by using ultraviolet light or ultraviolet light in combination with a heat treatment, to cause a resultant metal ion concentration in the glass material.

SEMICONDUCTOR STORAGE DEVICE

A semiconductor storage device includes interconnections in a first layer and a second layer, a first memory cell between a first and a second interconnection, and a dummy memory cell between the first interconnection and a third interconnection. A controller applies a first voltage of a first polarity to the first interconnection and a second voltage of a second polarity opposite the first polarity to the second interconnection at a first time. The controller applies a third voltage at a second time after the first time to the first interconnection. The third voltage having a smaller magnitude smaller than first voltage. The controller applies a fourth voltage to the third interconnection at the second time. The fourth voltage has a magnitude larger than the third voltage but smaller than the first voltage.

ACCESS DEVICE AND PHASE CHANGE MEMORY COMBINATION STRUCTURE IN BACKEND OF LINE (BEOL)

A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.

ELECTROCHROMIC THIN FILM TRANSISTORS WITH LATERAL OR VERTICAL STRUCTURE USING FUNCTIONALIZED OR NON-FUNCTIONALIZED SUBSTRATES AND METHOD OF MANUFACTURING SAME

The presently disclosed subject matter can include or consist of the creation and manufacture of electrochromic thin film transistors, either self-sustaining or not, with lateral or vertical structure, deposited on any kind of functionalized substrate, referred to as electrochromic substrate, or non-functionalized substrate. The electrolyte material and the presence or not of an ultra-thin membrane can act as dielectric element. The electrochromic material can act as active semiconductor of the channel region. The gate, source and drain electrodes can be based on metal materials, such as Titanium, Gold, Aluminium, or degenerate semiconductive oxides, like Indium and Zinc oxide, Gallium-doped Zinc oxide. The device operation control process can be made by means of electronic and ionic current, and the off-state to on-state switch, or vice-versa, can be followed by a change of colour of the device.

RESISTANCE RANDOM ACCESS MEMORY DEVICE

A resistance random access memory device according to one embodiment includes an interlayer insulation film which a trench is made therein, an ion supply layer provided along a bottom surface and a side surface of the trench, a portion of the ion supply layer provided along the bottom surface is thicker than a portion of the ion supply layer provided along the side surface, and a resistance change layer provided at least below the ion supply layer.

Semiconductor device and method of manufacturing same

A semiconductor device including a transistor on a main surface side of a semiconductor substrate; and a resistance change element on a back-surface side of the semiconductor substrate, wherein the transistor includes a low-resistance section in the semiconductor substrate, the low-resistance section extending to the back surface of the semiconductor substrate, an insulating film is provided in contact with a back surface of the low-resistance section, the insulating film has an opening facing the low-resistance section, and the resistance change element is connected to the low-resistance section through the opening.

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

The embodiments provide a semiconductor memory device including: a plurality of first wiring lines extending in a first direction, the first wiring lines being provided in a second direction intersecting the first direction; a plurality of second wiring lines extending in the second direction, the second wiring lines being provided in the first direction; a plurality of memory cells provided in the intersections between the first wiring lines and the second wiring lines, each memory cell having a first stack structure comprising at least a variable resistor film; a contact extending in a third direction intersecting the first and second directions, the contact having a first end connected to one of the first wiring lines or one of the second wiring lines, the contact having a second stack structure having a stack of a plurality of films; and a wiring layer connected to a second end of the contact. At least some of the films of the second stack structure have generally the same third direction position and film thickness as at least some of layers of the first stack structure. And, the second stack structure has a higher metal ratio than the first stack structure. 1. A semiconductor memory device comprising:a plurality of first wiring lines extending in a first direction, the first wiring lines being provided in a second direction intersecting the first direction;a plurality of second wiring lines extending in the second direction, the second wiring lines being provided in the first direction;a plurality of memory cells provided in the intersections between the first wiring lines and the second wiring lines, each memory cell having a first stack structure comprising at least a variable resistor film;a contact extending in a third direction intersecting the first and second directions, the contact having a first end connected to one of the first wiring lines or one of the second wiring lines, the contact having a second stack structure having a stack of a plurality of ...

MEMORY DEVICE HAVING STITCHED ARRAYS OF 4 F+hu 2 +l MEMORY CELLS

A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts.

Method for manufacturing an integrated circuit including an electrolyte material layer

A method for manufacturing an electrolyte material layer with a chalcogenide material incorporated or deposited therein for use in semiconductor memory devices, in particular resistively-switching memory devices or components. The method comprises the steps of producing a semiconductor substrate, depositing a binary chalcogenide layer onto the semiconductor substrate, depositing a sulphur-containing layer onto the binary chalcogenide layer, and creating a ternary chalcogenide layer comprising at least two different chalcogenide compounds ASexSy. One component A of the chalcogenide compounds ASexSy comprises materials of the IV elements main group, e.g., Ge, Si, or of a transition metal, preferably of the group consisting of Zn, Cd, Hg, or a combination thereof.

Resistance memory device and memory apparatus and data processing system

A resistance memory device and a memory apparatus and data processing apparatus having the same are provided. The resistance memory device includes a pair of electrode layers and a variable resistance layer interposed between the pair of electrode layers. The variable resistance layer includes at least one variable resistance material layer and a piezoelectric material layer coupled to the at least one variable resistance material layer.

Semiconductor memory device and manufacturing method for same

A semiconductor memory device includes a plurality of first interconnections extending in a first direction, and a second interconnection extending in a second direction different from the first direction. The device further includes a resistance change film provided between the plurality of first interconnections and the second interconnection, the resistance change film including (a) silicon and a semiconductor layer including one or more elements selected from among oxygen, carbon, nitrogen, phosphorus, boron, and germanium, or (b) a first layer containing the germanium and a second layer containing the silicon.

Storage device and storage unit

A storage device includes: a first electrode; a storage layer including an ion source layer; and a second electrode. The first electrode, the storage layer, and the second electrode are provided in this order. The ion source layer contains a movable element, and has a volume resistivity of about 150 m·cm to about 12000 m·cm both inclusive.

NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICE

A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.

BUFFER LAYER IN MEMORY CELL TO PREVENT METAL REDEPOSITION

Some embodiments relate to a memory device. The memory device includes a first electrode overlying a substrate. A data storage layer overlies the first electrode. A second electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the first electrode to the second electrode. An active metal layer is disposed between the data storage layer and the second electrode. A buffer layer is disposed between the active metal layer and the second electrode. The buffer layer has a lower reactivity to oxygen than the active metal layer.

SOLUTION-PROCESSED SOLID ELECTROLYTIC LAYER DEVICE AND FABRICATION

MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide a memory device that is stably operated even when the device is miniaturized. SOLUTION: The memory device includes: a memory layer 13 that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer 14 that is formed to be isolated for each memory cell and to be laminated on the memory layer 13, and contains at least one element selected from among Cu, Ag, Zn, Al and Zr and at least one element selected from among Te, S and Se; an insulating layer 17 that isolates the memory layer 13 and the ion source layer 14 for each memory cell; and a diffusion preventing barrier 18 that is provided at a periphery of the memory layer 13 and the ion source layer 14 of each memory cell to prevent the diffusion of the element. COPYRIGHT: (C)2012,JPO&INPIT ...

丸いコーナーを有する複数の柱を備えるクロスポイント形不揮発性メモリ装置およびその製造方法

STORAGE ELEMENT AND MEMORY DEVICE

PROBLEM TO BE SOLVED: To provide a storage element exhibiting superior low current operation and having excellent retention properties, and to provide a memory device. SOLUTION: In the storage element 1 laminating a lower electrode 10, a memory layer 20 and an upper electrode 30 in this order, the memory layer 20 has a resistance change layer 22 including a layer containing the most tellurium (Te), and an ion source layer 21 containing aluminum (Al) within the range of 27.7-47.4 atom%. Consequently, metal elements precipitated into the resistance change layer 22 during erasure dissolve easily into the ion source layer 21, and the resistive state after writing and erasure is maintained. COPYRIGHT: (C)2012,JPO&INPIT ...

МЕМРИСТОР НА ОСНОВЕ СМЕШАННОГО ОКСИДА МЕТАЛЛОВ

Настоящее изобретение относится к устройствам микро- и наноэлектроники на основе перспективных материалов. Такие мемристорные устройства со стабильными и повторяемыми характеристиками могут быть использованы для создания компьютерных систем на основе аналоговой архитектуры искусственных нейронных сетей. Данное устройство состоит из активного слоя, расположенного между двумя токопроводящими слоями, находящегося с ними в электрическом контакте и представляющего собой оксид типа АВО, где элемент В является титаном, или цирконием, или гафнием, а элемент А - трехвалентным металлом с ионным радиусом, равным 0,7-1,2 ионного радиуса титана, или циркония, или гафния. Если элемент В является титаном, то в качестве А выбирают алюминий или скандий, если элемент В является цирконием или гафнием, то в качестве А выбирают скандий, или иттрий, или лютеций. Повышение стабильности и повторяемости напряжения переключения, сопротивления в низко- и высокоомном состояниях является техническим результатом предложенного ...

Электрически перепрограммируемый запоминающий прибор

... 1. Электрически перепрограммируемый запоминающий прибор, состоящий:из определенного порядка резистивно-программируемых ячеек памяти, сформированных в халькогенидном материале, который включает как минимум две запоминающие ячейки;вышеназванные ячейки памяти имеют как минимум два интерфейса между халькогенидными пленками; в одних из вышеназванных пленок содержится кислород, или фтор, и эти вышеназванные халькогенидные пленки контактируют (имеют интерфейс) с многослойным халькогенидным материалом, содержащим определенную концентрацию электрически активных примесей-доноров, и этот вышеназванный многослойный халькогенидный материал помещен между двумя вышеназванными ячейками памяти и;множества электродов, включающих первый и второй электроды и два отводящих электрода; вышеназванный первый электрод позиционирован ниже всех, и он электрически контактирует с нижней областью первой ячейки памяти; вышеназванный, второй электрод позиционирован сверху и он электрически контактирует с верхней областью ...

Non-volatile (sic) resistive storage cell with solid electrolyte matrix between first and second electrode as active layer useful in semiconductor technology has elements from groups IVb and Vb and transition metals in active layer

Non-volatile (sic) resistive storage cell with solid electrolyte matrix (300) between first (100) and second (200) electrode as active layer. Active layer includes first, second and third layers, where first and third layers (300a and 300c) have composition MmX(1-m) and Mm'X(1-m') respectively, where M = element selected from groups IVb and Vb and transition metals, X and Y = O, S, Se or Te and m and m' =0-1. INDEPENDENT CLAIM is included for preparation of storage cell involving deposition of a dielectric layer on first electrode. Second layer (300b) is formed from Z-chalcogenide compound, where one of electrodes can be Z-chalcogenide compound, where Z = Ag, Cu, Sn, Na, Li, or K.

Festkörperelektrolyt-Speicherzelle sowie Festkörperelektrolyt-Speicherzellenarray

Festkorperelektrolyt-Speicherzelle mit wahlfreiem Zugriff, mit einem Festkörperelektrolytblock, der wenigstens drei Festkörperelektrolyt-Kontaktierbereiche aufweist, mit Elektroden, die mit dem Festkorperelektrolyt-Kontaktierbereichen elektrisch verbunden sind, wobei in dem Festkörperelektrolytblock leitende Pfade ausbildbar, löschbar oder detektierbar sind durch Anlegen von Spannungen zwischen den Festkorperelektrolyt-Kontaktierbereichen, wobei die Kontaktierbereiche räumlich voneinander getrennt sind, derart, dass leitende Pfade, die von unterschiedlichen Festkorperelektrolyt-Kontaktierbereichen ausgehen und/oder in unterschiedlichen Festkörperelektrolyt-Kontaktierbereichen enden, nicht miteinander uberlappen, wobei wenigstens zwei Festkörperelektrolyt-Kontaktierbereiche auf einer ersten Oberfläche angeordnet sind, und eine leitfähige Widerstandsschicht zwischen den wenigstens zwei Festkörperelektrolyt-Kontaktierbereichen auf der ersten Oberfläche angeordnet und mit den wenigstens zwei ...

Neuartiges resistives Random-Access-Memory-Bauelement

Ein Speicher weist Folgendes auf: eine erste Elektrode mit einer oberen Grenzfläche und einer Seitenwand, eine Schicht aus Widerstandsmaterial, die über der ersten Elektrode angeordnet ist und zumindest einen ersten Abschnitt und einen mit einem ersten Ende des ersten Abschnitts gekoppelten zweiten Abschnitt umfasst, und eine zweite Elektrode, die über der Schicht aus Widerstandsmaterial angeordnet ist, wobei der erste Abschnitt der Schicht aus Widerstandsmaterial an der oberen Grenzfläche der ersten Elektrode und der zweite Abschnitt der Schicht aus Widerstandsmaterial an einem oberen Abschnitt der Seitenwand der ersten Elektrode entlang verläuft.

SPEICHERZELLE

Verfahren zum Herstellen einer integrierten Schaltung, Speichermodul und integrierte Schaltung

Verfahren zum Herstellen einer integrierten Schaltung, das aufweist: – Ausbilden eines Halbleitersubstrats mit einer Mehrzahl von Auswahlvorrichtungen (32001', 32002'), – Ausbilden einer Mehrzahl von Auswahlvorrichtungen (32001', 32002'), wobei die Auswahlvorrichtungen (32001', 32002') derart ausgebildet werden, dass ein Stromfluss durch die Auswahlvorrichtungen (32001', 32002') vertikal zur Hauptprozessierungsoberfläche des Halbleitersubstrats erfolgt, – Ausbilden einer Mehrzahl von Wortleitungen (808, 2000), wobei die Wortleitungen (808, 2000) oberhalb der Auswahlvorrichtungen (32001', 32002') ausgebildet werden, – Ausbildung einer Mehrzahl von Speicherelementen (804), wobei die Speicherelemente (804) oberhalb der Wortleitungen (808, 2000) ausgebildet werden, – Ausbildung einer Mehrzahl von Bitleitungen (810), wobei die Bitleitungen (810) oberhalb der Speicherelemente (804) ausgebildet werden, und wobei die Auswahlvorrichtungen (32001', 32002') Bipolartransistoren sind.

Reaktiver Sputterprozess zur Optimierung der thermischen Stabilität dünner Chalkogenidschichten

Chalkogenidschicht der Zusammensetzung M¶m¶X¶1-m¶, wobei M aus einem oder mehreren Elementen bzw. Metallen aus der Gruppe, bestehend aus IVb-Gruppe des Periodensystems, Vb-Gruppe des Periodensystems, und Übergangsmetallen ausgewählt ist, X ein Element oder mehrere Elemente der Gruppe S, Se und Te bedeutet und m einen Wert zwischen 0 und 1 aufweist, dadurch gekennzeichnet, dass die Chalkogenidschicht einen Gehalt an Sauerstoff oder Stickstoff im Bereich von 0,001 at% bis 75 at% aufweist.

Interactive greeting card

NON VOLATILE MEMORY CELL WITH AN ADJUSTABLE RESISTANCE AND TRANSISTOR

MANUFACTURING PROCESS FOR A CBRAM MEMORY WITH IMPROVED RELIABILITY

IMPROVED PROCEDURE FOR THE PRODUCTION OF MEMORY CELLS OF THE TYPE PMC

MANUFACTURING PROCESS FOR CELLS WITH RESISTANCE-VARIABLE MATERIAL

PROGRAMMABLE METALLIZATION STRUCTURE WITH SOLIDIFICATION NEAR THE SURFACE AND MANUFACTURING PROCESS FOR IT

METHOD OF CONTROLLABLY ALTERING THE CONDUCTIVITY OF A GLASSY AMORPHOUS MATERIAL

PROGRAMMABLE MICROELECTRONIC DEVICES AND METHODS OF FORMING AND PROGRAMMING SAME

A microelectronic programmable structure (300) and methods of forming and programming the structure (300) are disclosed. The programmable structure (300) generally includes an ion conductor (340) and a plurality of electrodes (320, 330). Electrical properties of the structure (300) may be altered by applying a bias across the electrodes (320, 330), and thus information may be stored using the structure (300).

PROGRAMMABLE SUB-SURFACE AGGREGATING METALLIZATION STRUCTURE AND METHOD OF MAKING SAME

A programmable sub-surface aggregating metallization structure (100) includes an ion conductor (110) such as a chalcogenide glass which includes metal ions and at least two electrodes (120, 130) disposed at opposing surfaces of the ion conductor (110). Preferably, the ion conductor (110) includes a chalcogenide material with Group IB or Group IIB metals. One of the two electrodes (120, 130) is preferably configured as a cathode and the other as an anode. When a voltage is applied to between the anode and cathode, a metal dendrite (140) grows from the cathode through the ion conductor (11) toward the anode. The grow rate of the dendrite may be stopped by removing the voltage or the dendrite may be retracted back toward the cathode by reversing the voltage polarity at the anode and the cathode. When a voltage is applied for a sufficient length of time, a continuous metal dendrite grows through the ion conductor (110) and connects the electrodes (120, 130), thereby shorting the device. The ...

METHOD OF FABRICATING A MICROELECTRONIC DEVICE WITH PROGRAMMABLE MEMORY

A method is provided for fabricating a microelectronic device with programmable memory that includes: i) depositing an intermediate layer of a material having a chalcogenide on a first electrode; ii) irradiating the intermediate layer of step i with ultraviolet radiation; iii) depositing an ionizable metallic layer on the intermediate layer obtained in step ii; iv) diffusing the metal ions originating from the ionizable metallic layer of step iii into the intermediate layer to form a chalcogenide material containing metal ions; and v) depositing a second electrode on the layer of chalcogenide material containing metal ions obtained in step iv to form the microelectronic device. 1. A method of fabricating a microelectronic device with programmable memory , said method comprising the steps of:i) depositing an intermediate layer of a material comprising a chalcogenide on a first electrode;ii) irradiating the intermediate layer of step i with ultraviolet radiation;iii) depositing an ionizable metallic layer on the intermediate layer obtained in step ii;iv) diffusing the metal ions originating from the ionizable metallic layer of step iii into the intermediate layer to form a chalcogenide material containing metal ions; andv) depositing a second electrode on the layer of chalcogenide material containing metal ions obtained in step iv to form said microelectronic device.2. The method as claimed in claim 1 , wherein the intermediate layer obtained after irradiation in step ii and diffusion in step iv has a metal ion content that is reduced by at least 20% relative to the metal ion content in the same intermediate layer obtained after diffusion in step iv claim 1 , without having undergone the irradiation of step ii.3. The method as claimed in claim 1 , wherein the irradiation of step ii is carried out in a non-oxidizing atmosphere.4. The method as claimed in claim 1 , wherein the intensity of the ultraviolet radiation in step ii is at least 80 mW/cm.5. The method as ...

NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, and a memory cell provided between the first electrode and the second electrode. The memory cell includes a retention unit, a resistance change unit, and an ion supply unit. The retention unit is provided on the first electrode and has an electron trap. The resistance change unit is provided on the retention unit. The ion supply unit is provided between the resistance change unit and the second electrode and includes a metal element. 1. A nonvolatile memory device comprising a first electrode , a second electrode , and a memory cell provided between the first electrode and the second electrode , a retention unit provided on the first electrode and having an electron trap;', 'a resistance change unit provided on the retention unit; and', 'an ion supply unit provided between the resistance change unit and the second electrode and including a metal element., 'the memory cell including2. The device according to claim 1 , wherein the retention unit includes a metal oxide having the electron trap.3. The device according to claim 1 , wherein the retention unit includes at least one selected from the group consisting of hafnium oxide (HfO) claim 1 , silicon oxynitride (SiON) claim 1 , aluminum oxide (AlO) claim 1 , lanthanum oxide (LaO) claim 1 , tantalum oxide (TaO) claim 1 , strontium oxide (SrO) claim 1 , yttrium oxide (YO) claim 1 , barium oxide (BaO) claim 1 , and zinc oxide (ZnO).4. The device according to claim 1 , wherein an electron trap density of the retention unit is 1×10/cmor more.5. The device according to claim 1 , wherein an electron trap density of the retention unit is 1×10/cmor less.6. The device according to claim 1 , wherein the retention unit includes a plurality of layers stacked.7. The device according to claim 1 , wherein the retention unit includes:{'sub': 'x', 'a layer including silicon oxide (SiO); and'}{'sub': x', 'x', 'y', 'x', 'y', 'x', 'y ...

PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING

Programmable metallization memory cells include an electrochemically active electrode, an inert electrode and an internal layer between the electrochemically active electrode and the inert electrode. The internal layer having a fast ion conductor material and an apertured layer having a plurality of apertures defined by an electrically insulating material. Each aperture defines at least a portion of a column of fast ion conductor material having superionic clusters. 1. A programmable metallization memory cell comprising:a first electrode in electrical contact with a bit line, the first electrode comprising an electrochemically active metal layer;a second electrode in electrical contact with a word line, the bit line being orthogonal to the word line; andan internal layer between the electrochemically active metal layer and the second electrode, the internal layer comprising a fast ion conductor material and an apertured layer comprising a plurality of apertures defined by an electrically insulating material, each aperture defines at least a portion of a column of fast ion conductor material having superionic clusters.2. The memory cell of wherein the electrically insulating material comprises a dielectric material.3. The memory cell of wherein the fast ion conductor material comprises a chalcogenide material.4. The memory cell of wherein the fast ion conductor material comprises a germanium selenide material.5. The memory cell of wherein the apertured layer is in contact with the electrochemically active metal layer.6. The memory cell of wherein the apertured layer is in contact with the inert electrode.7. The memory cell of wherein the apertured layer is in contact with the electrochemically active metal layer and the inert electrode.8. The memory cell of wherein the plurality of apertures each have an aperture diameter of about 20 to 50 nm.9. A programmable metallization memory cell comprising:an electrochemically active electrode;an inert electrode; andan ...

CONDUCTIVE METAL OXIDE STRUCTURES IN NON VOLATILE RE WRITABLE MEMORY DEVICES

A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s). 130.-. (canceled)31. A memory device , comprising:a first terminal structure;a second terminal structure; and an electrolytic insulator layer electrically coupled with the first terminal structure and including a first thickness, and', {'sub': X', 'Y, 'a binary oxide material having a form AO, where O represents oxygen and A represents a metal, the binary oxide material in contact with the tunnel barrier layer and electrically coupled with the second terminal structure, the binary oxide material reversibly programmable between multiple resistance states via exchange of ions with the electrolytic insulator layer.'}], 'a re-writeable non-volatile memory element electrically in series with the first and second terminal structures and operative to store at least one-bit of data as a plurality of conductivity profiles that are retained in the absence of electrical power, the memory element including32. The memory device of claim 31 , wherein the binary oxide material comprises tin oxide.33. The memory device of claim 31 ...

PROGRAMMABLE RESISTIVE MEMORY CELL WITH SACRIFICIAL METAL

Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode. The sacrificial metal has a more negative standard electrode potential than the filament forming metal 1. A programmable metallization memory cell comprising:an electrochemically active electrode and an inert electrode, the electrochemically active electrode comprising filament forming metal;an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode; anda sacrificial metal disposed between the ion conductor solid electrolyte material and the inert electrode, the sacrificial metal having a more negative standard electrode potential than the filament forming metal.2. The programmable metallization memory cell of wherein the sacrificial metal has a smaller atomic radius than the filament forming metal.3. The programmable metallization memory cell of wherein the filament forming metal is silver and the sacrificial metal is chromium claim 1 , nickel or zinc.4. The programmable metallization memory cell of wherein sacrificial metal donates electrons to the filament forming metal to stabilize filaments formed by the filament forming metal claim 1 , the filaments electrically connecting the electrochemically active electrode and the inert electrode.5. The programmable metallization memory cell of wherein the ion conductor solid electrolyte material comprises a chalcogenide material6. The programmable metallization memory cell of wherein the sacrificial metal forms a sacrificial metal layer on either the electrochemically active electrode or the inert electrode and the layer having a thickness of less than 50 nanometers.7. The programmable metallization memory cell of wherein the sacrificial ...

Resistive-Switching Memory Elements Having Improved Switching Characteristics

Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness. 1. A resistive-switching memory element comprising:a first electrode and a second electrode;a switching layer between the first electrode and the second electrode, wherein the switching layer comprises hafnium oxide and has a first thickness; anda coupling layer between the switching layer and the second electrode, wherein the coupling layer comprises a material including metal titanium and has a second thickness that is less than 25 percent of the first thickness.2. The memory element of claim 1 , wherein the first electrode is doped silicon and the memory element is configured to receive a negative reset voltage relative to a common electrical reference and a positive set voltage relative to the common electrical reference at the second electrode.3. The memory element of claim 1 , wherein the first thickness is between 20 and 100 angstroms.4. The memory element of claim 1 , wherein the switching layer comprises a hafnium oxide having an elemental composition of between HfOand HfO.5. The memory element of claim 4 , wherein the first electrode is n-type polysilicon.6. The memory element of claim 1 , further comprising an interface layer between the first electrode and the switching layer claim 1 , wherein the interface layer has a thickness less than 10 Å.7. The memory element of claim 1 , wherein the switching layer comprises a hafnium oxide having an oxygen concentration that is between 60 and 95% of stoichiometric.8. The memory element of claim 1 , ...

MEMORY ELEMENT AND MEMORY DEVICE

A memory element and a memory device, the memory element including a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer provided on the first electrode side, and an ion source layer provided on the second electrode side and is higher in resistance value than the resistance change layer. A resistance value of the resistance change layer is changeable in response to a composition change by applied voltage to the first and second electrodes 1. A memory element , comprising a first electrode , a memory layer , and a second electrode in this order , wherein the memory layer includes:a resistance change layer provided on the first electrode side thereof; andan ion source layer provided on the second electrode side thereof, a resistance value of the resistance change layer is configured to change in response to a composition change by means of a voltage applied to the first and second electrodes,', 'a resistance value of the ion source layer is higher than the resistance value of the resistance change layer, and', 'the ion source layer comprises (a) at least one of metallic elements of copper (Cu), aluminum (Al), germanium (Ge), and zinc (Zn), (b) at least one of zirconium (Zr), titanium (Ti), and tungsten (W), and (c) at least one of oxygen (O), tellurium (Te), sulfur (S), and selenium (Se)., 'wherein,'}2. The memory element according to claim 1 , wherein the memory layer includes an oxide layer between the resistance change layer and the first electrode.3. The memory element according to claim 1 , wherein the resistance change layer contains tellurium (Te).4. The memory element according to claim 1 , wherein the change of resistance value occurs by formation of claim 1 , in the resistance change layer claim 1 , a low-resistance section containing a metallic element by the applied voltage to the first and second electrodes.5. A memory device claim 1 , comprising:a plurality of memory elements each ...

Electronic memory device

An electronic device includes a first electrode, a second electrode, and a solid electrolyte made of an ion-conducting material, the first and second electrodes being configured to form a metal dendrite. The device further includes a third electrode, an interface layer contacting the third electrode and a third surface of the electrolyte, the interface layer being an ionic insulator and an electronic insulator. The third electrode and the dendrite are arranged such that the device has two resistive states.

RESISTANCE VARIABLE ELEMENT, SEMICONDUCTOR DEVICE INCLUDING IT AND MANUFACTURING METHODS THEREFOR

A resistance variable element includes a first electrode, a second electrode and an ion conductor layer interposed between the first and second electrodes. Metal ions supplied from the first electrode into the ion conductor layer accept electrons from the second electrode and are turned into metal. The so formed metal is precipitated to cross-link and interconnect the first and second electrodes to provide for voltage variations. The ion conductor layer has a stacked layer structure comprised of a first ion conductor layer formed by a compound containing oxygen and carbon and a second ion conductor layer formed by a metal oxide. The metal oxide that forms the second ion conductor layer includes at least one out of zirconium oxide and hafnium oxide. 1. A resistance variable element , comprising a first electrode , a second electrode and an ion conductor layer interposed between the first and second electrodes;metal ions supplied from the first electrode into the ion conductor layer accepting electrons from the second electrode and being turned into metal which is precipitated; the metal cross-linking and interconnecting the first and second electrodes to provide for variations in resistance of the element; wherein,the ion conductor layer is a stacked layer structure made up by a first ion conductor layer formed by a compound containing oxygen and carbon and a second ion conductor layer formed of metal oxide;the metal oxide that forms the second ion conductor layer containing at least one out of zirconium oxide and hafnium oxide.2. The resistance variable element according to claim 1 , wherein claim 1 ,the second ion conductor layer further contains aluminum oxide.3. The resistance variable element according to claim 1 , wherein claim 1 ,the second ion conductor layer is one selected from the group consisting of a layered product of titanium oxide and zirconium oxide, a mixed product of titanium oxide and zirconium oxide, a layered product of titanium oxide and ...

ELECTRONIC DEVICE

This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes a semiconductor memory, and the semiconductor memory includes a variable resistance structure including a material having a resistance that is changed by formation or dissipation of conductive filaments; and a Magnetic Tunnel Junction (MTJ) structure inserted in the variable resistance structure and comprising a first magnetic layer having a pinned magnetization direction, a second magnetic layer having a variable magnetization direction, and a tunnel dielectric layer interposed between the first magnetic layer and the second magnetic layer. 120-. (canceled)21. An electronic device , comprising: (1) a first variable resistance structure including a first material having a resistance that is changed by formation or dissipation of one or more conductive filaments or passages in the first material in response to a first control signal applied to the first material;', '(2) a Magnetic Tunnel Junction (MTJ) structure comprising a first magnetic layer having a pinned magnetization direction, a second magnetic layer having a variable magnetization direction, and a tunnel dielectric layer interposed between the first magnetic layer and the second magnetic layer, the MTJ structure being coupled to the first variable resistance structure by having the first magnetic layer in contact with the first variable resistance structure, wherein the MTJ structure exhibits a first MTJ resistance state when magnetizations of the first and second magnetic layers are parallel to each other and a second, different MTJ resistance state when magnetizations of the first and second magnetic layers are anti-parallel to each other; and', '(3) a second variable resistance structure including a second material having a resistance that is changed by formation or dissipation of one or more conductive filaments or passages in the second material in response to a second ...

MEMORY CELL STRUCTURES

The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode. 1. A memory cell , comprising:a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode;a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode; anda storage element between the first electrode and the electrode contact portion of the second electrode.2. The memory cell of claim 1 , wherein an electrode contact portion of the second electrode has sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode.3. The memory cell of claim 1 , wherein the first electrode has a trapezoidal cross-sectional area and sidewalls that are selected from the group consisting of straight claim 1 , concave claim 1 , or convex.4. The memory cell of claim 3 , wherein a top surface of the trapezoidal cross-sectional area of the first electrode is an electrode contact portion of the first electrode and is in contact with the storage element.5. The memory cell of claim 1 , wherein the first electrode has a triangular cross-sectional area and sidewalls that are selected from the group consisting of straight claim 1 , concave claim 1 , or convex.6. The memory cell of claim 1 , wherein the storage element includes a resistance variable ...

THREE-DIMENSIONAL NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING REPLACEMENT GATE

The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices. In one aspect, a vertical three-dimensional semiconductor memory device comprises a memory block comprising at least one memory hole formed through a stack of alternating layers of control gate layers and dielectric layers, wherein the memory hole is filled with a plurality of materials forming at least one memory cell. The semiconductor memory device additionally includes at least one trench formed through the stack so as to define part of a boundary of the memory block, wherein a sidewall of the trench comprises the control gate layers each having at least a portion that is in part laterally recessed relative to vertically adjacent dielectric layers, and wherein the trench is filled with an electrically conductive material. 1. A vertical three-dimensional semiconductor memory device , comprising:a memory block comprising at least one memory hole formed through a stack of alternating layers of control gate layers and dielectric layers, wherein the memory hole is filled with a plurality of materials forming at least one memory cell; andat least one trench formed through the stack so as to define part of a boundary of the memory block, wherein a sidewall of the trench comprises the control gate layers each having at least a portion that is in part laterally recessed relative to vertically adjacent dielectric layers, and wherein the trench is filled with an electrically conductive material.2. The memory device of claim 1 , wherein the control gate layers comprise semiconductor layers claim 1 , and wherein the electrically conductive material comprises a metallic material.3. The memory device of claim 1 , wherein the electrically conductive material comprises one or more of tungsten claim 1 , tungsten nitride claim 1 , tantalum claim 1 , tantalum nitride claim 1 , ...

SELECT DEVICE FOR MEMORY CELL APPLICATIONS

The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device. 1. A memory cell , comprising: a first electrode having a particular geometry;', 'a first heater formed on the first electrode;', 'a semiconductor material formed on the first heater;', 'a second heater formed on the semiconductor material; and', 'a second electrode having the particular geometry formed on the second heater; and, 'a select device includinga storage element coupled in series to the select device.2. The memory cell of claim 1 , wherein a width of the semiconductor material is less than approximately 20 nanometers.3. The memory cell of claim 1 , wherein a width of the particular geometry is based on an operating voltage associated with the memory cell.4. The memory cell of claim 1 , wherein a composition of the semiconductor material is based on an operating voltage associated with the memory cell.5. The memory cell of claim 1 , wherein the select device is configured to support bi-directional current flow therethrough.6. The memory cell of claim 1 , wherein the particular geometry is a circular geometry.7. The memory cell of claim 1 , wherein the particular geometry is a quasi-square geometry.8. A memory cell claim 1 , comprising: a first heater;', 'a first electrode on the first heater;', 'a semiconductor material on the first electrode;', 'a second electrode on the semiconductor material; and', 'a second heater on the second electrode; and, 'a select device includinga storage element coupled in series to the select device.9. The memory cell of claim 8 , wherein a vacuum is ...

THERMAL DISPERSION LAYER IN PROGRAMMABLE METALLIZATION CELL

Some embodiments relate to a memory device. The memory device includes a programmable metallization cell random access memory (PMCRAM) cell. The programmable metallization cell comprises a dielectric layer disposed over a bottom electrode, the dielectric layer contains a central region. A conductive bridge is formable and erasable within the dielectric layer and the conductive bridge is contained within the central region of the dielectric layer. A metal layer is disposed over the dielectric layer. A heat dispersion layer is disposed between the bottom electrode and the dielectric layer. 1. A memory device , comprising:a bottom electrode;a dielectric layer disposed over the bottom electrode;a top electrode disposed over the dielectric layer, wherein a conductive bridge is selectively formable within the dielectric layer to couple the bottom electrode to the top electrode; anda heat dispersion layer disposed between the bottom electrode and the dielectric layer.2. The memory device of claim 1 , wherein the heat dispersion layer is comprised of a material having a thermal conductivity greater than 100 W/m−K.3. The memory device of claim 1 , wherein the heat dispersion layer is comprised of aluminum nitride claim 1 , silicon carbide claim 1 , beryllium oxide claim 1 , or boron nitride.4. The memory device of wherein the memory device is configured to switch between a high-resistance state and a low-resistance state;wherein, when in the high-resistance state, a conductive pillar is disposed within a central region of the dielectric layer, the conductive pillar having a bottom surface in contact with an upper surface of the heat dispersion layer and having a top surface spaced apart from the top electrode by an upper portion of the dielectric layer; andwherein, when in the low-resistance state, the conductive pillar remains disposed within the central region of the dielectric layer and a conductive bridge is formed to extend through the upper portion of the dielectric ...

RESISTIVE RANDOM-ACCESS MEMORY WITH PROTECTED SWITCHING LAYER

Resistive RAM (RRAM) devices having increased reliability and related manufacturing methods are described. Greater reliability of RRAM cells over time can be achieved by avoiding direct contact of metal electrodes with the device switching layer. 1. A resistive random-access memory (RRAM) device comprising:an intermediate first layer that includes a switching region with added switching species of at least one different material;a device layer of a semiconductor material at one side of the intermediate layer and includes a first doped region, and a substrate layer of a semiconductor material at an opposite side of the first layer and comprises a second doped region;electrodes that are spaced from said switching region and contact said first and second doped regions; andwherein said switching region is configured to switch between higher and lower resistivity states in response to a switching voltage without having been conditioned with a higher, breakdown voltage.2. The RRAM device of claim 1 , further including one or more active electronic circuits formed in one or both of said device and substrate layers.3. The RRAM device of claim 2 , in which said one or more active electronic circuits are formed only at said device layer.4. The RRAM device of claim 2 , in which said one or more active electronic circuits are formed only at said substrate layer.5. The RRAM device of claim 2 , in which at least one of said electrodes has a contact that extends through said device layer and said intermediate layer to said second doped region but is spaced from said switching region.6. The RRAM device of claim 2 , in which said intermediate layer and said device and substrate layers comprise a single chip and said switching region and first and second doped regions are configured as plural claim 2 , individually addressed resistive memory elements.7100. The RRAM device of claim 6 , in which said resistive memory elements are characterized by a lifetime of million or more switching ...

VARIABLE RESISTANCE MEMORY

A variable resistance memory according to the present embodiment includes a memory cell including an ion source electrode including metal atoms, an opposite electrode, an amorphous silicon film formed between the ion source electrode and the opposite electrode, and a polysilicon film formed between the amorphous silicon film and the ion source electrode. 1. (canceled)2. A variable resistance memory , comprisinga memory cell including:an ion source electrode including metal atoms;an opposite electrode; anda variable resistance film provided between the ion source electrode and the opposite electrode, and comprising a first film and a second film, the first film being provided between the ion source electrode and the second film, the first film having a crystal grain boundary and the second film being amorphous, and concentration of the metal atoms in the first film is higher than concentration of the metal atoms in the second film.3. The variable resistance memory according to claim 2 , wherein a thickness of the first film is thicker than a thickness of the second film.4. The variable resistance memory according to claim 2 , wherein the second film includes microcrystal.5. The variable resistance memory according to claim 2 , wherein the second film includes a first amorphous layer and a second amorphous layer provided between the first amorphous layer and the opposite electrode claim 2 , a grain size in the second amorphous layer being larger than a grain size in the first amorphous layer.6. The variable resistance memory according to claim 5 , wherein the first and second amorphous layers contain microcrystal.7. The variable resistance memory according to claim 5 , further comprising:a first microcrystal layer provided between the first film and the first amorphous layer; anda second microcrystal layer provided between the first amorphous layer and the second amorphous layer.8. The variable resistance memory according to claim 7 , wherein the grain size in the ...

LIQUID MIXTURE AND METHOD FOR ETCHING A SUBSTRATE USING THE LIQUID MIXTURE

A liquid mixture for etching a substrate includes acetic acid in a range of 15 to 70 mass. % of the liquid mixture, nitric acid in a range of 5 to 50 mass. % of the liquid mixture, sulfuric acid in a range of 8 to 50 mass. % of the liquid mixture, and water in a range of 0 to 30 mass. % of the liquid mixture. 17-. (canceled)8. A method for etching a substrate , comprising:providing the substrate, wherein the substrate comprises a first exposed material and a second exposed material, wherein the first exposed material comprises tantalum oxide, and wherein the second exposed material is different than the first exposed material;treating the substrate using a plasma or a halogen species during processing, wherein a portion of the first exposed material is plasma-damaged or contaminated by the halogen species; anddispensing a liquid mixture onto the substrate to etch the plasma-damaged or contaminated portion of the first exposed material and a portion of the second exposed material from the substrate, acetic acid in a range of 15 to 70 mass. % of the liquid mixture;', 'nitric acid in a range of 5 to 50 mass. % of the liquid mixture;', 'sulfuric acid in a range of 8 to 50 mass. % of the liquid mixture; and', 'water in a range of 0 to 30 mass. % of the liquid mixture., 'wherein the liquid mixture includes'}9. (canceled)10. The method of claim 8 , wherein the substrate comprises a resistive random access memory cell.11. The method of claim 8 , further comprising prior to dispensing the liquid mixture:arranging the substrate on a spin chuck; androtating the substrate using the spin chuck.12. The method of further comprising mixing the liquid mixture with hydrofluoric acid prior to dispensing the liquid mixture.13. The method of claim 12 , wherein the concentration of the hydrofluoric acid is in a range from 0.05 to 1 mass. % of the liquid mixture.14. The method of claim 12 , wherein the concentration of the hydrofluoric acid is in a range from 0.1 to 0.5 mass. % of the ...

RRAM CELL WITH PMOS ACCESS TRANSISTOR

In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device. A first voltage is provided to a source terminal of the PMOS transistor, and a second voltage is provided to a bulk terminal of the PMOS transistor. The second voltage is larger than the first voltage. A third voltage is provided to an upper electrode of the RRAM device. The third voltage is larger than the first voltage. 1. A method of operating a resistive random access memory (RRAM) cell , comprising:turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device;providing a first voltage to a source terminal of the PMOS transistor;providing a second voltage to a bulk terminal of the PMOS transistor, wherein the second voltage is larger than the first voltage; andproviding a third voltage to an upper electrode of the RRAM device, wherein the third voltage is larger than the first voltage.2. The method of claim 1 , wherein the first voltage has a value that is substantially equal to zero.3. The method of claim 1 , wherein the third voltage is larger than the second voltage.4. The method of claim 1 , wherein the second voltage is larger than a drain voltage at the drain terminal of the PMOS transistor.5. The method of claim 1 , wherein providing the third voltage to the upper electrode causes an initial conductive filament to be formed within the RRAM device.6. The method of claim 5 , further comprising:performing a reset operation by turning on the PMOS transistor while providing a non- zero reset voltage to the bulk terminal.7. The method of claim 1 , wherein providing the third voltage to the upper electrode causes a conductive filament to be reformed within the RRAM device.8. The method of claim 1 , wherein the third voltage is more than twice as large as the second voltage.9 ...

RESISTIVE MEMORY CELL HAVING A COMPACT STRUCTURE

The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material. 1. A memory cell comprising:a selection transistor having a control gate and a first conduction terminal; a semiconductor substrate,', 'a first insulating layer covering the semiconductor substrate, and', 'a semiconductor active layer covering the insulating layer, the control gate being formed on the active layer and having a lateral flank,, 'a variable-resistance element connected to the first conduction terminal, the selection transistor and variable-resistance element being formed in a wafer that includesa second insulating layer covering the lateral flank of the control gate,a first trench formed through the active layer at a lateral flank of the active layer, along the lateral flank of the gate, and reaching the first insulating layer, wherein the variable-resistance element includes a layer of variable-resistance material positioned in the first trench along the lateral flank of the active layer, anda trench conductor formed in the first trench and against a lateral flank of the layer of variable-resistance material along the lateral flank of the active layer.2. The memory cell according to claim 1 , comprising adjacent trench isolations claim 1 , in which ...

INTERCONNECTION FOR MEMORY ELECTRODES

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level. 1. (canceled)2. An apparatus , comprising:a first access line and a second access line extending in a same direction, wherein at least a portion of the first access line extends beyond a portion of the second access line, and wherein the first access line comprises a first jog segment and the second access line comprises a second jog segment; anda connector coupled with the first jog segment, or the second jog segment, or both.3. The apparatus of claim 2 , further comprising:a socket region comprising a first socket coupled with the first access line and a second socket coupled with the second access line, wherein the first access line extends beyond a boundary of the socket region, and wherein the second access line is located entirely within the boundary of the socket region.4. The apparatus of claim 2 , wherein a distance between the first jog segment and the second jog segment is greater than a distance between another portion of the first access line and another portion of the second access line.5. The apparatus of claim 2 , further comprising:a third access line extending in a different direction than the first access line and the second access line, wherein at least a portion of the third access line intersects at least a portion of the first access line, at least a portion of the second access line, or both.6. The apparatus of claim 2 , wherein the first access line and the second access line are formed at a first vertical level of a stack.7. The apparatus of claim 6 , further comprising:a second vertical level of the stack comprising a fourth access line and a fifth access line extending in a second direction.8. ...

RESISTANCE VARIABLE MEMORY DEVICE WITH NANOPARTICLE ELECTRODE AND METHOD OF FABRICATION

A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle. 1. An apparatus , comprising:a processor; a first electrode;', 'an aluminum layer in contact with the first electrode, the aluminum layer comprising at least one nanochannel that extends through the aluminum layer to the first electrode;', 'at least one nanoparticle in contact with the aluminum layer, within the at least one nanochannel, or both;', 'a first germanium selenide layer in contact with the aluminum layer and the at least one nanoparticle; and', 'a second electrode in contact with the first germanium selenide layer., 'a memory circuit configured to communicate with the processor, the memory circuit comprising2. The apparatus of claim 1 , further comprising:a layer of nanoparticle material in contact with the first germanium selenide layer, wherein a thickness of the layer of nanoparticle material is the same as a thickness of the at least one nanochannel in the aluminum layer.3. The apparatus of claim 1 , further comprising:a metal chalcogenide layer in contact with the first germanium selenide layer; anda second germanium selenide layer in contact with the metal chalcogenide layer.4. The apparatus of claim 3 , further comprising:a metal layer in contact with the second germanium selenide layer, wherein at least a portion of the metal layer comprises silver; anda third germanium selenide layer in contact with the metal layer.5. The apparatus of claim 4 , wherein the metal chalcogenide layer comprises a chalcogenide glass.6. The apparatus of claim 5 , wherein the chalcogenide glass comprises at least a portion of the metal chalcogenide layer.7. The apparatus of claim 1 , wherein the first electrode and the second electrode each comprise at least one of tungsten ...

HALIDE SEMICONDUCTOR MEMRISTOR AND NEUROMORPHIC DEVICE

Disclosures of the present invention describe a halide semiconductor memristor that is suitable for being as an artificial synapse. The halide semiconductor memristor comprises a first electrode layer, an active layer and a second electrode layer, wherein the active layer comprises a first oxide semiconductor film formed on the first electrode layer, a halide semiconductor film formed on the first oxide semiconductor film, and a second oxide semiconductor film formed on the halide semiconductor film Moreover, a variety of experimental data have proved that, this halide semiconductor memristor is indeed suitable for being adopted as a plurality of artificial synapses that are used in manufacture of a neuromorphic device, and exhibits many advantages, including: capable of being driven by a low operation voltage, having a multi-stage adjustable resistance state, and a wide dynamic range of the switching resistance states. 1. A halide semiconductor memristor , being suitable for being as an artificial synapse , and comprising:a first electrode layer; a first oxide semiconductor film formed on the first electrode layer, having a first conduction band minimum (CBM) level, a first fermi level and a first valence band minimum (VBM) level;', 'a halide semiconductor film formed on the first oxide semiconductor film, having a second CBM level, a second fermi level and a second VBM level; and', 'a second oxide semiconductor film formed on the halide semiconductor film, having a third CBM level, a third fermi level and a third VBM level; and, 'an active layer, comprisinga second electrode layer formed on the second oxide semiconductor film;wherein the first CBM level of the first oxide semiconductor film is deeper than the second CBM level of the halide semiconductor film, the first fermi level of the first oxide semiconductor film being deeper than the second fermi level of the halide semiconductor film, and the first VBM level of the first oxide semiconductor film being ...

All around electrode for novel 3D RRAM applications

A resistive switching memory device can include three or more electrodes interfacing a switching layer, including a top electrode, a bottom electrode, and a side electrode. The top and bottom electrodes can be used for forming conductive filaments and for reading the memory device. The side electrode can be used to control the resistance state of the switching layer. 1. A resistive switching memory structure comprising:a substrate; wherein the dielectric layer is operable as a resistive switching layer,', 'wherein the dielectric layer has a bottom surface facing the substrate, a top surface opposite the bottom surface, and a side surface;, 'a dielectric layer above the substrate,'}a first electrode facing the bottom surface;a second electrode facing the top surface;a third electrode interfacing the side surface;2. A resistive switching memory structure as inwherein the dielectric layer comprises a metal oxide material.3. A resistive switching memory structure as inwherein the first or second electrode interfaces the bottom or top electrode, respectively.4. A resistive switching memory structure as in further comprisinga current limiter element disposed between the first electrode and the bottom surface.5. A resistive switching memory structure as in further comprisinga current limiter element disposed between the second electrode and the top surface.6. A resistive switching memory structure as inwherein the third electrode interfaces the dielectric layer at two opposite sides or at all sides around the dielectric layer.7. A resistive switching memory structure as inwherein the third electrode is separated from the first or second electrode by an insulator layer.8. A resistive switching memory structure as inwherein a lateral dimension of the dielectric layer is smaller than a lateral dimension of the first or second electrode.9. A resistive switching memory structure as inwherein the dielectric layer comprises a vertical interface,wherein the vertical interface is ...

METHODS OF FORMING RESISTIVE MEMORY ELEMENTS

A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described. 1. A method of forming a resistive memory element , comprising:forming a switchable resistivity material over an electrode, the switchable resistivity material comprising one or more of a metal oxide and a chalcogenide;{'sub': x', 'x', 'x', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y', 'x', 'y, 'forming a buffer material over the switchable resistivity material, the buffer material comprising longitudinally extending, columnar grains of one or more of TiN, TaN, WN, TiNC, TaNC, WNC, TiNB, TaNB, WNB, TiNSi, TaNSi, and WNSi;'}forming a material over the buffer material, the material comprising a chalcogen and one or more of Cu, Ag, and Al; andforming another electrode over the material.2. The method of claim 1 , wherein forming a switchable resistivity material over an electrode comprises forming one or more of SiO claim 1 , AlO claim 1 , HfO claim 1 , HfSiO claim 1 , ZrO claim 1 , ZrSiO claim 1 , TiO claim 1 , TiSiO claim 1 , TaO claim 1 , TaSiO claim 1 , NbO claim 1 , NbSiO claim 1 , VO claim 1 , VSiO claim 1 , WO claim 1 , WSiO claim 1 , MoO claim 1 , MoSiO claim 1 , CrO claim 1 , and CrSiOover the electrode.3. The method of claim 1 , wherein forming a buffer material over the switchable resistivity material comprises forming the buffer material to further comprise one or more of O claim 1 , S claim 1 , Se claim 1 , and Te.4. The method of claim 1 , wherein forming a buffer material over the switchable resistivity material comprises forming the buffer material to have a thickness ...

TOP ELECTRODE FOR DEVICE STRUCTURES IN INTERCONNECT

Some embodiments relate to an integrated circuit device, which includes a bottom electrode, a dielectric layer, and top electrode. The dielectric layer is disposed over the bottom electrode. The top electrode is disposed over the dielectric layer, and an upper surface of the top electrode exhibits a recess. A via is disposed over the top electrode. The via makes electrical contact with only a tapered sidewall of the recess without contacting a bottom surface of the recess. 1. An integrated circuit device , comprising:a bottom electrode;a dielectric layer disposed over the bottom electrode;a top electrode disposed over the dielectric layer, wherein an upper surface of the top electrode comprises a tapered recess; anda via disposed over the top electrode, wherein the via establishes electrical contact with an inner sidewall of the tapered recess but not with a central bottom surface of the tapered recess.2. The integrated circuit device of claim 1 , further comprising:a dielectric material arranged under the via and contacting the central bottom surface of the tapered recess of the top electrode.3. The integrated circuit device of claim 2 , wherein the dielectric material further comprises outer sidewalls that contact a bottom inner sidewall of the tapered recess under the via.4. The integrated circuit device of claim 1 , further comprising:sidewall spacers disposed over the bottom electrode and along outer sidewalls of the top electrode.5. The integrated circuit device of claim 1 , wherein the top electrode comprises:a central upper electrode portion having a first thickness; anda peripheral upper electrode portion having a second thickness that differs from the first thickness.6. The integrated circuit device of claim 5 , wherein the first thickness is less than the second thickness.7. The integrated circuit device of claim 5 , wherein the first thickness is half of or less than half of the second thickness.8. The integrated circuit device of claim 1 , wherein the ...

Device switching using layered device structure

A resistive switching device. The device includes a first electrode comprising a first metal material overlying the first dielectric material and a switching material comprising an amorphous silicon material. The device includes a second electrode comprising at least a second metal material. In a specific embodiment, the device includes a buffer material disposed between the first electrode and the switching material. The buffer material provides a blocking region between the switching material and the first electrode so that the blocking region is substantially free from metal particles from the second metal material when a first voltage is applied to the second electrode.

MULTIPLE (MULTI-) LEVEL CELL (MLC) NON-VOLATILE (NV) MEMORY (NVM) MATRIX CIRCUITS FOR PERFORMING MATRIX COMPUTATIONS WITH MULTI-BIT INPUT VECTORS

Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors are disclosed. An MLC NVM matrix circuit includes a plurality of NVM storage string circuits that each include a plurality of MLC NVM storage circuits each containing a plurality of NVM bit cell circuits each configured to store 1-bit memory state. Thus, each MLC NVM storage circuit stores a multi-bit memory state according to memory states of its respective NVM bit cell circuits. Each NVM bit cell circuit includes a transistor whose gate node is coupled to a word line among a plurality of word lines configured to receive an input vector. Activation of the gate node of a given NVM bit cell circuit in an MLC NVM storage circuit controls whether its resistance is contributed to total resistance of an MLC NVM storage circuit coupled to a respective source line. 1. A multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuit , comprising:a plurality of word lines configured to receive a multi-bit input vector represented by an input voltage on each word line among the plurality of word lines;a plurality of bit lines, each bit line among the plurality of bit lines configured to receive a corresponding line voltage;a plurality of source lines; and a gate node coupled to a corresponding word line among the plurality of word lines; and', 'each NVM bit cell circuit configured to couple its resistance to a source line among the plurality of source lines coupled to its respective MLC NVM storage circuit in response to the input voltage applied to the corresponding word line coupled to the gate node., 'each NVM bit cell circuit among the plurality of NVM bit cell circuits in a respective MLC NVM storage circuit having a resistance representing a stored memory state, and comprising, 'each MLC NVM storage circuit among the plurality of MLC NVM storage circuits comprising a plurality of NVM bit cell circuits each ...

Memory Cells, Non-Volatile Memory Arrays, Methods Of Operating Memory Cells, Methods Of Writing To And Writing From A Memory Cell, And Methods Of Programming A Memory Cell

In one aspect, a method of operating a memory cell includes using different electrodes to change a programmed state of the memory cell than are used to read the programmed state of the memory cell. In one aspect, a memory cell includes first and second opposing electrodes having material received there-between. The material has first and second lateral regions of different composition relative one another. One of the first and second lateral regions is received along one of two laterally opposing edges of the material. Another of the first and second lateral regions is received along the other of said two laterally opposing edges of the material. At least one of the first and second lateral regions is capable of being repeatedly programmed to at least two different resistance states. Other aspects and implementations are disclosed.

Three dimensional memory array with select device

Three dimensional memory arrays and methods of forming the same are provided. An example three dimensional memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines such that the at least one conductive extension intersects each of the plurality of first conductive lines. Storage element material is arranged around the at least one conductive extension, and a select device is arranged around the storage element material. The storage element material is radially adjacent an insulation material separating the plurality of first conductive lines, and the plurality of materials arranged around the storage element material are radially adjacent each of the plurality of first conductive lines.

STRUCTURES INCORPORATING AND METHODS OF FORMING METAL LINES INCLUDING CARBON

Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element. The memory cell stack further includes an electrode interposed between the at least one of the upper and lower conductive lines and the closer of the first and second active elements. 1. A method , comprising:forming a lower conductive line extending in a first direction by patterning a lower conductive material over a substrate;forming an upper conductive line extending in a second direction by patterning an upper conductive material over the lower conductive line;forming a memory cell between the lower conductive line and the upper conductive line, the memory cell including at least one active element, wherein the lower conductive line and the at least one active element are patterned in the first direction using a single mask process, and the upper conductive line and the at least one active element are patterned in the second direction using a single mask process, such that the at least one active element is isolated in both first and second directions after forming the memory cell; andwherein the upper conductive line, ...

RESISTIVE RANDOM ACCESS MEMORY DEVICE EMBEDDING TUNNEL INSULATING LAYER AND MEMORY ARRAY USING THE SAME AND FABRICATION METHOD THEREOF

A resistive random access memory device is provided with a tunneling insulator layer between a resistance change layer and a bottom electrode. Thus, it is possible: to raise the selection (on/off) ratio by the current of a direct tunneling induced by low voltage in the unselected cell and the current of an F-N tunneling induced by high voltage in the selected cell, to efficiently suppress the leakage current in the read operation, to make a low current operation less μA level by controlling the thickness of the tunneling insulator layer, and to be simultaneously fabricated together with circuit devices by forming the bottom electrodes (word lines) with a semiconductor material. 1. A resistive random access memory device comprising:a bottom electrode formed of a semiconductor material implanted with impurity ions;a tunneling insulator layer formed on the bottom electrode;a resistance change layer formed on the tunneling insulator layer; anda top electrode formed on the resistance change layer.2. The resistive random access memory device of claim 1 ,{'sub': '2', 'wherein the resistance change layer is formed of a high dielectric (high-k) material having a higher dielectric constant than silicon oxide (SiO) film, and wherein the tunneling insulator layer is formed of a silicon oxide film or a low dielectric (low-k) material having a lower dielectric constant than the silicon oxide film and has a thin thickness less than that of the resistance change layer.'}3. The resistive random access memory device of claim 1 ,wherein the semiconductor material is silicon and the resistance change layer is formed of material having traps.4. The resistive random access memory device of claim 3 ,wherein the bottom electrode is implanted with p-type impurity ions,{'sub': '2', 'wherein the tunneling insulator layer is formed of one of SiO, carbon-doped silicon dioxide, porous silicon dioxide and HSQ, and'}{'sub': 1-x', 'x', '3', '3, 'wherein the resistance change layer is formed of one ...

Shaping reram conductive filaments by controlling grain-boundary density

Filament size and shape in a ReRAM stack can be controlled by doping layers of a variable-resistance stack to change the crystallization temperature. This changes the density of the grain boundaries that form during annealing and provide minimal-resistance paths for the migration of charged defects. Hf, Zr, or Ti decreases the crystallization temperature and narrows the filament, while Si or N increases the crystallization temperature and widens the filament. Tapered filaments are of interest: The narrow tip requires little energy to break and re-form, enabling the cell to operate at low power, yet the wider body and base are insensitive to entropic behavior of small numbers of defects, enabling the cell to retain data for long periods.

MEMRISTOR STRUCTURE WITH A DOPANT SOURCE

A memristor including a dopant source is disclosed. The structure includes an electrode, a conductive alloy including a conducting material, a dopant source material, and a dopant, and a switching layer positioned between the electrode and the conductive alloy, wherein the switching layer includes an electronically semiconducting or nominally insulating and weak ionic switching material. A method for fabricating the memristor including a dopant source is also disclosed. 1. A memristor , including:an electrode;a conductive alloy including a conducting material, a dopant source material, and a dopant; anda switching layer positioned between the electrode and the conductive alloy, wherein the switching layer includes an electronically semiconducting or nominally insulating and weak ionic switching material;{'sub': 'x', 'wherein the switching layer comprises a binary oxide M1O, where M is selected from the group consisting of transition metal oxides and metal oxides.'}2. The memristor of claim 1 , wherein the switching layer is a single layer structure claim 1 , a bi-layer structure or a multi-layer structure.3. The memristor of wherein the switching layer or a part thereof is to form a switching channel.4. The memristor of claim 1 , wherein the electrode and the conducting material include a material selected from the group consisting of aluminum claim 1 , copper claim 1 , gold claim 1 , molybdenum claim 1 , niobium claim 1 , palladium claim 1 , platinum claim 1 , ruthenium claim 1 , ruthenium oxide claim 1 , silver claim 1 , tantalum claim 1 , tantalum nitride claim 1 , titanium nitride claim 1 , tungsten claim 1 , and tungsten nitride.5. The memristor of claim 1 , wherein:the switching layer includes an oxide and the dopant is oxygen.6. The memristor of claim 1 , wherein the dopant source material is soluble in the conducting material claim 1 , the dopant is soluble in the dopant source material claim 1 , and the free energy of formation of a compound including the ...

NONVOLATILE MEMORY TRANSISTOR AND DEVICE INCLUDING THE SAME

Provided are nonvolatile memory transistors and devices including the nonvolatile memory transistors. A nonvolatile memory transistor may include a channel element, a gate electrode corresponding to the channel element, a gate insulation layer between the channel element and the gate electrode, an ionic species moving layer between the gate insulation layer and the gate electrode, and a source and a drain separated from each other with respect to the channel element. A motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode. A threshold voltage changes according to the motion of the ionic species. The nonvolatile memory transistor has a multi-level characteristic. 1. A nonvolatile memory transistor comprising:a channel element;a gate electrode corresponding to the channel element;a gate insulation layer between the channel element and the gate electrode;an ionic species moving layer between the gate insulation layer and the gate electrode; anda source and a drain separated from each other with respect to the channel element, wherein a motion of an ionic species at the ionic species moving layer occurs according to a voltage applied to the gate electrode, wherein a threshold voltage changes according to the motion of the ionic species, and wherein the nonvolatile memory transistor has a multi-level characteristic.2. The nonvolatile memory transistor of claim 1 , wherein the ionic species moving layer comprises a variable resistance material.3. The nonvolatile memory transistor of claim 1 , wherein the ionic species moving layer comprises a bipolar memory layer.4. The nonvolatile memory transistor of claim 1 , wherein the ionic species moving layer comprises at least one of PrCaMnO (PCMO) claim 1 , Ti oxide claim 1 , Ta oxide claim 1 , Ni oxide claim 1 , Zn oxide claim 1 , W oxide claim 1 , Co oxide claim 1 , Nb oxide claim 1 , TiNi oxide claim 1 , LiNi oxide claim 1 , InZn oxide claim 1 , V oxide claim ...

MAGNESIUM ION BASED SYNAPTIC DEVICE

A method of fabricating a synaptic device is provided. The method includes forming a channel layer between a first terminal and a second terminal. The channel layer varies in resistance based on a magnesium concentration in the channel layer. The method further includes forming an electrolyte layer. The electrolyte layer includes a magnesium ion conductive material. A third terminal is formed over the electrolyte layer and applies a signal to the electrolyte layer and the channel layer. 1. A synaptic device , comprising:a channel layer disposed between a first terminal and a second terminal in a stacked configuration, wherein the channel layer is configured to vary in resistance based on a magnesium concentration in the channel layer;an electrolyte layer disposed on the channel layer and configured to conduct magnesium ions with the channel layer in accordance with an applied input signal; anda third terminal disposed on the electrolyte layer and configured to apply a signal to the electrolyte layer.2. The synaptic device of claim 1 , wherein the channel layer comprises one or more metal oxides.3. The synaptic device of claim 1 , wherein the electrolyte layer comprises a magnesium ion conductive material.4. The synaptic device of claim 3 , wherein the magnesium ion conductive material comprises one of Mg(BH)(NH) claim 3 , Mg(En)(BH) claim 3 , Mg(En)(BH) claim 3 , MgZrPO+ZrO(PO)and MgZr(PO).5. The synaptic device of claim 1 , further comprising a magnesium reservoir layer disposed between the electrolyte layer and the third terminal and configured to transport magnesium ions under an applied input signal.6. The synaptic device of claim 5 , wherein the magnesium reservoir layer comprises metal oxides or carbon-based compounds.7. The synaptic device of claim 1 , wherein the third terminal comprises one or more of aluminum claim 1 , copper claim 1 , platinum claim 1 , gold claim 1 , tungsten claim 1 , titanium claim 1 , carbon claim 1 , nitrogen claim 1 , TiN claim 1 , ...

SWITCHING BLOCK CONFIGURATION BIT COMPRISING A NON-VOLATILE MEMORY CELL

A configuration bit for a switching block routing array comprising a non-volatile memory cell is provided. By way of example, the configuration bit and switching block routing array can be utilized for a field programmable gate array, or other suitable circuit(s), integrated circuit(s), application specific integrated circuit(s), electronic device or the like. The configuration bit can comprise a switch that selectively connects or disconnects a node of the switching block routing array. A non-volatile memory cell connected to the switch can be utilized to activate or deactivate the switch. In one or more embodiments, the non-volatile memory cell can comprise a volatile resistance switching device connected in serial to a gate node of the switch, configured to trap charge at the gate node to activate the switch, or release the charge at the gate node to deactivate the switch. 1a non-volatile switch comprising an input node, an output node and a control gate, the input node connected to a first conductive line of a switching block routing array and the output node connected to a second conductive line of the switching block routing array;a volatile switch having a first contact and a second contact, the second contact is conductively connected to the control gate of the non-volatile switch; anda program circuit configured to selectively provide a voltage from a voltage source to the first contact of the volatile switch.. A circuit, comprising: This application for patent is a continuation of and claims priority to U.S. application Ser. No. 15/469,179, titled SWITCHING BLOCK CONFIGURATION BIT COMPRISING A NON-VOLATILE MEMORY CELL and filed Mar. 24, 2017, which is hereby incorporated by reference herein in its entirety and for all purposes.U.S. application Ser. No. 14/717,185 entitled “NON-VOLATILE MEMORY CELL UTILIZING VOLATILE SWITCHING TWO TERMINAL DEVICE AND A MOS TRANSISTOR” and filed May 20, 2015, U.S. application Ser. No. 14/588,185 entitled “SELECTOR DEVICE FOR ...

Logic integrated circuit and semiconductor device

An object of the present invention is to provide a logic integrated circuit that increases reliability of configuration information held in a switch while maintaining high tamper resistance and a small chip area. The logic integrated circuit according to the present invention includes: a three-terminal resistance change switch including a first resistance change switch and a second resistance change switch connected in series; a reading circuit which reads first data based on a resistance state of the first resistance change switch and second data based on a resistance state of the second resistance change switch; and a first error detection circuit which compares the first data with the second data and issue an output based on a result of the comparison.

Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Including Resistance Change Material and Method of Operating

Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described. 137-. (canceled)38. A semiconductor memory cell comprising:a silicon controlled rectifier device comprising a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said cell;a nonvolatile memory comprising a resistance change element configured to store data stored in said silicon controlled rectifier device upon transfer thereto;a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type.39. The semiconductor memory cell of claim 38 , wherein said resistance change element comprises a phase change material.40. The semiconductor memory cell of claim 38 , wherein said resistance change element comprises a metal-oxide-metal system.41. The semiconductor memory cell of claim 38 , wherein said silicon controlled rectifier device comprises a substrate region having said first conductivity type.42. The semiconductor memory cell of claim 41 , wherein said substrate region is connected to an anode terminal.43. The semiconductor memory cell of claim 38 , wherein said nonvolatile memory stores said data stored in said silicon controlled rectifier device upon loss of power to said cell claim 38 , wherein said cell is configured to perform a shadowing process wherein said ...

Current Forming Of Resistive Random Access Memory (RRAM) Cell Filament

A memory device includes a metal oxide material disposed between and in electrical contact with first and second conductive electrodes, and an electrical current source configured to apply one or more electrical current pulses through the metal oxide material. For each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse to form a conductive filament in metal oxide material. 1. A method of forming a conductive filament in metal oxide material disposed between and in electrical contact with first and second conductive electrodes , the method comprising:applying one or more electrical current pulses through the metal oxide material;wherein for each of the one or more electrical current pulses, an amplitude of the electrical current increases over time during the electrical current pulse.2. The method of claim 1 , wherein for each of the one or more of the electrical current pulses claim 1 , the amplitude of the electrical current increases in discrete steps.3. The method of claim 2 , wherein for each of the one or more of the electrical current pulses claim 2 , a number of the discrete steps exceeds that of any of the one or more of the electrical current pulses preceding the electrical current pulse.4. The method of claim 1 , wherein for each of the one or more of the electrical current pulses claim 1 , a maximum of the electrical current amplitude exceeds that of any of the one or more of the electrical current pulses preceding the electrical current pulse.5. The method of claim 1 , wherein for each of the one or more of the electrical current pulses claim 1 , a duration of the one electrical current pulse exceeds that of any of the one or more of the electrical current pulses preceding the electrical current pulse.6. The method of claim 1 , wherein all of the one or more of the electrical current pulses have a same duration.7. The method of claim 1 , wherein for each of the one ...

ELECTRONIC DEVICE COMPRISING SEMICONDUCTOR MEMORY USING METAL ELECTRODE AND METAL COMPOUND LAYER SURROUNDING SIDEWALL OF THE METAL ELECTRODE

This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a lower electrode, a variable resistance element over the lower electrode, an upper electrode disposed over the variable resistance element and including metal, and a metal compound layer configured to surround a side of the upper electrode. The metal compound layer includes a compound of the metal of the upper electrode. 117-. (canceled)18. A method of manufacturing an electronic device comprising semiconductor memory , comprising:forming a material layer for forming a variable resistance element over a substrate;forming a metal layer over the material layer;forming a mask pattern over the metal layer;forming a metal layer pattern by etching the metal layer using the mask pattern as an etch barrier;transforming an external part of the metal layer pattern, corresponding to a specific width from an external side of the metal layer pattern, into a metal compound layer by performing surface treatment on the metal layer pattern to have a low etch rate as an etch barrier; andetching the material layer using the metal layer pattern and the metal compound layer as an etch barrier to form a variable resistance element having an external side aligned with an external side of the metal compound layer.19. The method of claim 18 , wherein the forming of the material layer includes forming a sequentially stack structure including a first magnetic layer claim 18 , a tunnel barrier layer claim 18 , and a second magnetic layer.20. The method of claim 18 , wherein the forming of the material layer comprises forming a metal oxide layer.21. The method of claim 18 , wherein the forming of the material layer comprises forming a phase change material layer.22. The method of claim 18 , wherein the surface treatment is performed using plasma treatment or thermal ...

Memory Cells and Methods of Forming Memory Cells

Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate material includes stabilizing species corresponding to one or both of carbon and boron. The memory cell also has a switching material over and directly against the intermediate material, an ion reservoir material over the switching material, and a second electrode over the ion reservoir material. Some embodiments include methods of forming memory cells. 132-. (canceled)33. A memory cell , comprising:a first electrode comprising titanium;an intermediate material over and directly against the first electrode, the intermediate material comprising stabilizing species corresponding to one or both of carbon and boron;a switching material over and directly against the intermediate material;an ion reservoir material over the switching material;a second electrode over the ion reservoir material, the second electrode comprising tungsten; andwherein the intermediate material comprises a gradient of stabilizing species concentration, with said concentration being lowest directly adjacent the first electrode and being highest directly adjacent the switching material.34. The memory cell of wherein the intermediate material comprises a thickness within a range of from greater than 0 angstroms to less than or equal to about 50 angstroms.35. The memory cell of wherein the intermediate material comprises a thickness within a range of from greater than or equal to about 10 angstroms to less than or equal to about 50 angstroms.36. The memory cell of wherein a surface of the intermediate material directly against the switching material comprises a total concentration of said stabilizing species of from about 15 atomic percent to about 100 atomic percent.37. The memory cell of wherein a surface of the intermediate material directly against the switching material comprises a total concentration of said stabilizing species of from ...

TOP ELECTRODE FOR DEVICE STRUCTURES IN INTERCONNECT

Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess. 1. An integrated circuit device , comprising:a resistive random access memory (RRAM) cell comprising a top electrode and a bottom electrode separated by a RRAM dielectric layer, wherein the top electrode of the RRAM cell has a recess in its upper surface; anda via over the RRAM cell, wherein the via contacts the top electrode within the recess.2. The integrated circuit device of claim 1 , further comprising:a blocking layer arranged within a lower portion of the recess and arranged directly under the via.3. The integrated circuit device of claim 1 , wherein the RRAM cell further comprises:sidewall spacers disposed over the bottom electrode and along outer sidewalls of the top electrode.4. The integrated circuit device of claim 1 , wherein the top electrode comprises:a peripheral top electrode portion having a peripheral upper surface; anda central top electrode portion circumscribed by the peripheral top electrode portion, the central top electrode portion having a central upper surface that is recessed relative to the peripheral upper surface.5. The integrated circuit device of claim 4 , wherein the via has outer via sidewalls that directly contact inner sidewalls of the top electrode which extend downwardly from the peripheral upper surface to the central upper surface.6. The integrated circuit device of claim 5 , further comprising:a blocking layer arranged under the via and having a bottom surface that contacts the central upper surface of the top electrode, the blocking layer having outer sidewalls that contact the inner sidewalls of the top electrode.7. The integrated ...

THERMAL MANAGEMENT OF SELECTOR

A non-volatile memory device that limits the temperature excursion of a selector during operation to enhance the cycling life of the non-volatile memory device. A selector, in line with a memory element, may be degraded with repeated temperature excursions as current passes through a stack during the read/write process. The selector changes from an amorphous state to become crystalline thus reducing the life of a memory device. The memory device includes a word line, a bit line disposed perpendicular to the word line, a stack—including a memory element, a selector, and a spacer—disposed between the word line and bit line, and one or more insulating layers surrounding an outer surface of the stack disposed between the word line and bit line. By surrounding the selector with a high thermal conductive heat-sink material, heat is directed away from the selector helping maintain the selector's amorphous state longer. 14-. (canceled)5. The memory device of claim 30 , wherein the spacer layer comprises a material selected from the group consisting of TiN claim 30 , TaN claim 30 , TiSiN claim 30 , TiAlN claim 30 , Co claim 30 , Ni claim 30 , and Cu.6. The memory device of claim 30 , wherein the bit line and word line comprises a material selected from the group consisting of Cu claim 30 , Al claim 30 , and W.7. The memory device of claim 30 , wherein the stack further comprises one or more electrode contacts claim 30 , the electrode contacts comprising a material selected from the group consisting of Ti claim 30 , Ta claim 30 , W claim 30 , Al claim 30 , Cr claim 30 , Zr claim 30 , Nb claim 30 , Mo claim 30 , Hf claim 30 , B claim 30 , C claim 30 , carbon intermixed with other elements claim 30 , conductive nitrides claim 30 , and combinations thereof.8. The memory device of claim 30 , wherein the memory element is selected from the group consisting of PCM claim 30 , RRAM claim 30 , MRAM and other temperature-generating memory elements.9. (canceled)10. The memory device of ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a bottom metal layer, a resistive random access memory (ReRAM) cell structure, and an upper metal layer. The bottom metal layer is located above the substrate. The ReRAM cell structure is formed on the bottom metal layer. The ReRAM cell structure includes a bottom electrode, a memory cell layer, a top electrode, and a spacer. The memory cell layer is formed on the bottom electrode. The top electrode is formed on the memory cell layer. The spacer is formed on two sides of the bottom electrode, the memory cell layer and the top electrode. The upper metal layer is electrically connected to and directly contacting the top electrode. 1. A semiconductor device , comprising:a bottom metal layer located above the substrate; a bottom electrode;', 'a memory cell layer formed on the bottom electrode;', 'a top electrode formed on the memory cell layer; and', 'a spacer formed on two sides of the bottom electrode, the memory cell layer and the top electrode; and, 'a resistive random access memory (ReRAM) cell structure formed on the bottom metal layer, comprisingan upper metal layer electrically connected to and directly contacting the top electrode.2. The semiconductor device according to claim 1 , further comprising:an inter-metal dielectric formed on the bottom metal layer, wherein the ReRAM cell structure and the upper metal layer are formed within the inter-metal dielectric.3. The semiconductor device according to claim 2 , wherein the inter-metal dielectric has a thickness of 2500-3500 Å.4. The semiconductor device according to claim 2 , further comprising:a via formed in the inter-metal dielectric and located at a lateral side of the ReRAM cell structure, wherein the upper metal layer is electrically connected to the bottom metal layer through the via.5. The semiconductor device according to claim 4 , wherein the via has a height of 1000-1500 Å.6. The ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer. 1a plurality of first wiring lines arranged in a first direction and having as their longitudinal direction a second direction intersecting the first direction;a plurality of second wiring lines arranged in the second direction and having the first direction as their longitudinal direction;a plurality of first variable resistance elements respectively provided at intersections of the first wiring lines and the second wiring lines; anda first contact extending in a third direction intersecting the first direction and second direction, one end of the first contact being connected to the second wiring line,the other end of the first contact and a surface intersecting the first direction of the first contact being covered by a first conductive layer.. A semiconductor memory device, comprising: This application is a continuation of and claims the benefit of priority under 35 U.S.C. § 120 from U.S. application Ser. No. 15/791,514 filed Oct. 24, 2017, which is a continuation of U.S. application Ser. No. 15/077,026 filed Mar. 22, 2016 (now U.S. Pat. No. 9,812,502 issued Nov. 7, 2017 ...

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

A semiconductor device includes a memory block including a transistor region and a memory region. A variable resistance layer of the memory region acts as a gate insulating layer in the transistor region. 120-. (canceled)21. A method for fabricating a semiconductor device , comprising:forming an interlayer dielectric defining a transistor region and a memory region;forming a plurality of gate electrodes on the interlayer dielectric in the transistor region and forming a plurality of first conductive lines on the interlayer dielectric in the memory region;forming a first insulating layer on the interlayer dielectric;forming a second insulating layer on the first insulating layer; andforming a first electrode and a second electrode on the second insulating layer in the transistor region to overlap a portion of the gate electrode and forming a plurality of second conductive lines crossing over the first conductive lines in the memory region.22. The method of claim 21 , further comprising:exposing the first insulating layer in the memory region by selectively etching the second insulating layer, after the forming of the second insulating layer.23. The method of claim 21 , further comprising:dividing the second insulating layer of the transistor region and the second insulating layer of the memory region by selectively etching the second insulating layer, after the forming of the second insulating layer.2423. The method of claim 21 , further comprising:dividing the first insulating layer of the transistor region and the first insulating layer of the memory region by selectively etching the first insulating layer, after the forming of the second insulating layer.25. The method of claim 21 , wherein the first insulating layer and the second insulating layer comprise an oxide layer claim 21 , and the oxide layer includes a plurality of oxygen vacancies.26. The method of claim 25 , wherein the second insulating layer comprises at least one material selected from the group ...

PROGRAMMABLE RESISTANCE MEMORY ELEMENTS WITH ELECTRODE INTERFACE LAYER AND MEMORY DEVICES INCLUDING THE SAME

A memory element can include a first electrode comprising at least a first element; a second electrode formed of a conductive material; and a memory layer comprising a memory material programmable between different resistance states. The first element can be ion conductible within the memory material. A second electrode can include an interface layer in contact with the memory layer. The interface layer being formed by inclusion of at least one modifier element not present in a remainder of the second electrode and not ion conductible within the memory material. 1. A memory element , comprising:a first electrode comprising at least a first element;a second electrode formed of a conductive material; anda memory layer disposed between the first electrode and a second electrode, the memory layer comprising a memory material programmable between different resistance states, the first element being ion conductible within the memory material; whereinthe second electrode includes an interface layer on a surface of the second electrode in contact with the memory layer, the interface layer formed by inclusion of at least one modifier element not present in a remainder of the second electrode, the modifier element not being ion conductible within the memory material.2. The memory element of claim 1 , wherein:the modifier element is a non-metal.3. The memory element of claim 2 , wherein:the modifier element is nitrogen.4. The memory element of claim 2 , wherein:the modifier element is oxygen.5. The memory element of claim 4 , wherein:the second electrode comprises a metal; andthe interface layer comprises an oxide of the metal.6. The memory element of claim 2 , wherein:the modifier element is a semiconductor that is not included in the memory material.7. The memory element of claim 1 , wherein:the interface layer has a thickness less than one half the thickness of the memory layer.8. A memory element claim 1 , comprising:a first electrode comprising at least a first element;a ...

MEMORY CELLS INCLUDING A METAL CHALCOGENIDE MATERIAL AND RELATED METHODS

A method of forming a metal chalcogenide material. The method comprises introducing a metal precursor and a chalcogenide precursor into a chamber, and reacting the metal precursor and the chalcogenide precursor to form a metal chalcogenide material on a substrate. The metal precursor is a carboxylate of an alkali metal, an alkaline earth metal, a transition metal, a post-transition metal, or a metalloid. The chalcogenide precursor is a hydride, alkyl, or aryl precursor of sulfur, selenium, or tellurium or a silylhydride, silylalkyl, or silylaryl precursor of sulfur, selenium, or tellurium. Methods of forming a memory cell including the metal chalcogenide material are also disclosed, as are memory cells including the metal chalcogenide material. 1. A memory cell , comprising:a dielectric material over a first electrode;a conductive material in an opening in the dielectric material;an active material over the conductive material and the dielectric material;an ion source material conformally formed over the active material, the ion source material comprising a metal chalcogenide material comprising antimony (Sb), bismuth (Bi), copper (Cu), gallium (Ga), germanium (Ge), gold (Au), indium (In), lead (Pb), nickel (Ni), palladium (Pd), silver (Ag), tin (Sn), or zinc (Zn) as the metal and sulfur, selenium, or tellurium as the chalcogen and the metal chalcogenide material excluding SbTe, GeTe, GeSbTe, ZnTe, BiTe, ZnSe, BiSe, InSe, and CuSe; anda second electrode over the ion source material.2. The memory cell of claim 1 , wherein the ion source material comprises a copper telluride material.3. The memory cell of claim 1 , wherein the ion source material comprises a metal chalcogenide material having a purity of greater than about 99%.4. The memory cell of claim 1 , wherein an upper surface of the conductive material in the opening is coplanar with an upper surface of the dielectric material.5. The memory cell of claim 1 , wherein the dielectric material isolates at least a ...

Memory Cells and Methods of Forming Memory Cells

Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state. 1. A method of forming a memory cell , comprising:depositing multiple layers of different composition relative to one another over a first electrode;merging the layers to form a switching region having a combined composition from the layers; andforming a second electrode over the switching region.2. The method of wherein the layers are formed utilizing one or more of ALD claim 1 , CVD and PVD.3. The method of wherein the layers are formed to thicknesses within a range of from greater than 0 angstroms to less than or equal to about 20 angstroms utilizing ALD.4. The method of wherein the layers comprise hafnium oxide and silicon oxide.5. The method of wherein the layers comprise hafnium oxide and aluminum oxide.6. The method of wherein the layers comprise aluminum oxide and silicon oxide.7. A method of forming a memory cell claim 1 , comprising:forming a first portion of a switching region over a first electrode;forming a second portion of the switching region over the first portion, with the second portion being formed by atomic layer deposition to a thickness within a range of from greater than 0 angstroms to less than or equal to about 20 ...

RESISTIVE RANDOM ACCESS MEMORY DEVICE

A resistive random access memory device includes a first electrode; a solid electrolyte made of metal oxide extending onto the first electrode; a second electrode able to supply mobile ions circulating in the solid electrolyte made of metal oxide to the first electrode to form a conductive filament between the first and second electrodes when a voltage is applied between the first and second electrodes; an interface layer including a transition metal from groups 3, 4, 5 or 6 of the periodic table and a chalcogen element; the interface layer extending onto the solid electrolyte made of metal oxide, the second electrode extending onto the interface layer. 1. A method of manufacturing a resistive random access memory device , the method comprising:forming a first electrode;forming, on the first electrode, a solid electrolyte made of metal oxide extending at least partially onto the first electrode;forming, on the solid electrolyte made of metal oxide, an interface layer; depositing, on the solid electrolyte made of metal oxide, a layer comprising a chalcogen element and a soluble conductive element;', 'depositing, on the layer comprising the chalcogen element and the soluble conductive element, a layer comprising a transition metal from groups 3, 4, 5 or 6 of the periodic table;', 'thermal annealing for at least partially diffusing the transition metal into the layer comprising the chalcogen element and the soluble conductive element, and for obtaining the interface layer; and, 'forming, on the interface layer, a soluble second electrode, the second electrode being configured to supply mobile ions circulating in the solid electrolyte made of metal oxide to the first electrode to form a conductive filament between the first and second electrodes when a voltage is applied between the first and second electrodes, wherein forming the interface layer comprises'}wherein forming the second electrode comprises depositing, on the interface layer, an ion source layer comprising ...

DIMENSION CONTROL FOR RAISED LINES

Methods, systems, and devices for dimension control for raised lines are described. For example, the techniques described herein may be used to fabricate raised lines (e.g., orthogonal raised lines). The lines may be fabricated such that an overall area of each line is consistent. In some examples, the techniques may be applied to form memory cells across multiple memory tiles, multiple memory arrays, and/or multiple wafers such that each memory cell comprises a consistent overall area. To form the lines and/or memory cells, a material associated with a desired properties may be deposited after performing a first cut. Due to the properties associated with the material, a width of the second cut may be affected, thus resulting in more uniform lines and/memory cells. 1. (canceled)2. An apparatus , comprising:a first pillar comprising a first memory cell coupled with a first conductive line and a second conductive line that each comprise a first conductive material;a second pillar comprising a second memory cell coupled with the second conductive line and a third conductive line that comprises the first conductive material; anda second conductive material below the second conductive line, at least a portion of the second conductive material extending below an upper surface of the first pillar and an upper surface of the second pillar at a location between the first pillar and the second pillar.3. The apparatus of claim 2 , further comprising:a dielectric material between the first pillar and the second pillar, wherein the portion of the second conductive material extends below at least a portion of the dielectric material.4. The apparatus of claim 2 , wherein the portion of the second conductive material has a first dimension equal to a distance between the first pillar and the second pillar and a second dimension equal to a width of the first memory cell claim 2 , the second memory cell claim 2 , or both.5. The apparatus of claim 4 , wherein the portion of the second ...

INTERCONNECT STRUCTURE, SEMICONDUCTOR DEVICE, METHOD OF OPERATING ACTIVE ELEMENT, METHOD OF MANUFACTURING INTERCONNECT STRUCTURE, METHOD OF USING INTERCONNECT STRUCTURE, METHOD OF CONTROLLING INTERCONNECT RESISTANCE OF INTERCONNECT STRUCTURE, METHOD OF EVALUATING INTERCONNECT STRUCTURE, METHOD OF EVALUATING DEVICE, METHOD OF DRIVING DEVICE, AND EVALUATION DEVICE

An interconnect structure according to the present disclosure includes: an interconnect layer containing a metal element as a main component and extending in a direction; a metal layer opposite to the interconnect layer, and a solid electrolyte layer between the interconnect layer and the metal layer. The solid electrolyte layer encloses the interconnect layer at least in a cross-sectional view taken along a plane orthogonal to the direction. The interconnect layer and the metal layer are electrically insulated from each other by the solid electrolyte layer. 1. An interconnect structure , comprising:an interconnect layer containing a metal element as a main component and extending in a direction;a metal layer opposite to the interconnect layer; anda solid electrolyte layer between the interconnect layer and the metal layer, the solid electrolyte layer enclosing the interconnect layer at least in a cross-sectional view taken along a plane orthogonal to the direction, whereinthe interconnect layer and the metal layer are electrically insulated from each other by the solid electrolyte layer.2. The interconnect structure according to claim 1 , whereinin the cross-sectional view, the interconnect layer has a pair of side surfaces opposite to each other and a bottom surface, andboth the metal layer and the solid electrolyte layer are opposite to each of the pair of side surfaces and the bottom surface.3. The interconnect structure according to claim 1 , whereinin the cross-sectional view, the interconnect layer has a circular or oval shape.4. The interconnect structure according to claim 3 , whereinthe interconnect layer serves as a columnar contact plug.5. The interconnect structure according to claim 1 , whereinin the cross-sectional view, an entire periphery of the interconnect layer is covered by the solid electrolyte layer, andin the cross-sectional view, an entire periphery of the solid electrolyte layer is covered by the metal layer.6. The interconnect structure ...

RESISTIVE SWITCHING MEMORY DEVICE BASED ON MULTI-INPUTS

A resistive switching memory device according to an exemplary embodiment includes: a first electrode; a second electrode formed to be separated from the first electrode; and an insulating layer formed near the first electrode and the second electrode, and changed to one of a high resistance state and a low resistance state when a conductive filament is controlled by a change of external humidity or a voltage applied through the first electrode or the second electrode. 1. A resistive switching memory device comprising:a first electrode;a second electrode formed to be separated from the first electrode; andan insulating layer formed near the first electrode and the second electrode, and changed to one of a high resistance state and a low resistance state when a conductive filament is controlled by a change of external humidity or a voltage applied through the first electrode or the second electrode.2. The resistive switching memory device of claim 1 , whereinwhen the external humidity becomes equal to or greater than a predetermined write humidity value, the insulating layer is changed to the low resistance state as the conductive filament is formed by allowing hydrogen ions that increase corresponding to conductivity of hydrogen ions increasing on the insulating layer to lower an oxidization/reduction potential of metal ions.3. The resistive switching memory device of claim 2 , whereinin the low resistance state, the insulating layer maintains the low resistance state when the external humidity changes to one humidity value in a range of a predetermined erase humidity value to the write humidity value.4. The resistive switching memory device of claim 3 , whereinwhen the external humidity becomes equal to or less than the erase humidity value, the conductive filament becomes disconnected and the insulating layer is changed to the high resistance state.5. The resistive switching memory device of claim 1 , whereinwhen a positive voltage that is equal to or greater than ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a first insulation layer, a second insulation layer disposed on the first insulation layer and having an opening on an upper surface of the second insulation layer, a first electrode embedded in the second insulation layer and having an end exposed at the opening, a variable-resistance layer disposed on the first electrode and the second insulation layer in at least one region inside and around the opening, and a second electrode disposed on the variable-resistance layer. The opening and the second electrode are formed in a shape stretched in at least one axial direction. 1. A semiconductor device comprising:a first insulation layer;a second insulation layer disposed on the first insulation layer and having an opening on an upper surface of the second insulation layer;a first electrode embedded in the second insulation layer and having an end that is exposed at the opening;a variable-resistance layer disposed on the first electrode and the second insulation layer in at least one region inside and around the opening; anda second electrode that is disposed on the variable-resistance layer, whereinthe opening and the second electrode are formed in a shape stretched in at least one axial direction.2. The semiconductor device according to claim 1 , whereinthe variable-resistance layer is an ion conductive layer capable of conducting ions of a metal constituting the first electrode.3. The semiconductor device according to claim 1 , wherein at least one of a formation region of the opening and an opening region of the second electrode is elliptical.4. The semiconductor device according to claim 1 , wherein at least one of a formation region of the opening and an opening region of the second electrode is rectangular.5. The semiconductor device according to claim 1 , comprising the first electrode at two locations claim 1 , whereinthe first electrodes at the two locations are disposed to face each other with an interval.6. The semiconductor ...

TOP-ELECTRODE BARRIER LAYER FOR RRAM

Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell including a top-electrode barrier layer configured to block the movement of nitrogen or some other suitable non-metal element from a top electrode of the RRAM cell to an active metal layer of the RRAM cell. Blocking the movement of non-metal element may be prevent formation of an undesired switching layer between the active metal layer and the top electrode. The undesired switching layer would increase parasitic resistance of the RRAM cell, such that top-electrode barrier layer may reduce parasitic resistance by preventing formation of the undesired switching layer.

LOW VOLTAGE EMBEDDED MEMORY HAVING CATIONIC-BASED CONDUCTIVE OXIDE ELEMENT

Low voltage embedded memory having cationic-based conductive oxide elements is described. For example, a material layer stack for a memory element includes a first conductive electrode. A cationic-based conductive oxide layer is disposed on the first conductive electrode. The cationic-based conductive oxide layer has a plurality of cation vacancies therein. A second electrode is disposed on the cationic-based conductive oxide layer. 1. A non-volatile memory device , comprising:a first conductive electrode;a cationic-based conductive oxide layer disposed on the first conductive electrode; anda second electrode disposed on the cationic-based conductive oxide layer;a transistor electrically connected to the first or the second electrode, a source line, and a word line; anda bit line electrically coupled with the other of the first or the second electrode.2. The non-volatile memory device of claim 1 , wherein the cationic-based conductive oxide layer has a plurality of cation vacancies therein.3. The non-volatile memory device of claim 1 , wherein the cationic-based conductive oxide layer comprises a material having cation-based mobility.4. The non-volatile memory device of claim 3 , wherein the material having cation-based mobility has lithium (Li) claim 3 , sodium (Na) or silver (Ag) mobility.5. The non-volatile memory device of claim 4 , wherein the material having cation-based mobility has lithium (Li) mobility and is selected from the group consisting of LiCoO claim 4 , LiMnO claim 4 , LiTiO claim 4 , LiNiO claim 4 , LiNbO claim 4 , LiN:H and LiTiS.6. The non-volatile memory device of claim 4 , wherein the material having cation-based mobility has sodium (Na) mobility and is Na β-alumina.7. The non-volatile memory device of claim 4 , wherein the material having cation-based mobility has silver (Ag) mobility and is selected from the group consisting of AgI claim 4 , RbAgIand AgGeAsS.8. The non-volatile memory device of claim 1 , wherein the resistivity of the ...

Memory cells, semiconductor devices including the memory cells, and methods of operation

Memory cells are disclosed, which cells include a cell material and an ion-source material over the cell material. A discontinuous interfacial material is included between the cell material and the ion-source material. Also disclosed are fabrication methods and semiconductor devices including the disclosed memory cells.

CONTROLLING COMPOSITION OF MULTIPLE OXIDES IN RESISTIVE SWITCHING LAYERS USING ATOMIC LAYER DEPOSITION

A method of fabricating a resistive random access memory (ReRAM) cell may include forming a set of nanolaminate structures over an electrode, such that each structure includes at least one first element oxide layer and at least one second element oxide layer. The overall set is operable as a resistive switching layer in a ReRAM cell. In this set, an average atomic ratio of the first element to the second element is different in at least two nanolaminate structures. This ratio may be less in nanolaminate structures that are closer to electrodes than in the middle nanolaminate structures. Alternatively, this ratio may increase from one end of the set to another. The first element may be less electronegative than the second elements. The first element may be hafnium, while the second element may be one of zirconium, aluminum, titanium, tantalum, or silicon. 1. A device comprising: 'wherein the first layer is operable as a first electrode;', 'a first layer comprising a first conductive material,'} 'wherein the second layer is operable as a second electrode; and', 'a second layer comprising a second conductive material,'} wherein the third layer is operable as a variable resistance layer switchable between a high resistance state and a low resistance state,', 'wherein the third layer comprises a first nanolaminate structure and a second nanolaminate structure,', 'wherein each of the first nanolaminate structure comprises a first oxide of a first element and a second oxide of a second element, and', 'wherein an average atomic ratio of the second element to the first element in the first nanolaminate structure is greater than an average atomic ratio of the second element to the first element in the second nanolaminate structure., 'a third layer disposed between the first layer the second layer,'}2. The device of claim 1 , wherein the average atomic ratio of the second element to the first element in the first nanolaminate structure is determined by a number of layers ...

System and Device Including Memristor Material

A system may include a first conductive plate configured at least to receive an input signal. The system may include a second conductive plate configured at least to output an output signal. The system may further include a memristor material positioned between the first conductive plate and the second conductive plate. 1. A system , comprising:a first conductive plate configured at least to receive an input signal;a second conductive plate configured at least to output an output signal; anda memristor material positioned between the first conductive plate and the second conductive plate.2. The system of claim 1 , wherein the memristor material comprises at least one of: at least one metal sulfide claim 1 , at least one metal selenide claim 1 , at least one metal telluride claim 1 , at least one metal nitride claim 1 , at least one metal phosphite claim 1 , or at least one metal arsenide.3. The system of claim 1 , wherein the memristor material abuts a first surface area of the first conductive plate claim 1 , wherein the memristor material abuts a second surface area of the second conductive plate claim 1 , wherein the first surface area and the second surface area are different.4. The system of claim 3 , wherein opposing faces of the first and second conductive plates have different surface areas.5. The system of claim 3 , further comprising a blocking material positioned between the first conductive plate and the second conductive plate claim 3 , the blocking material abutting the memristor material and one of the first conductive plate or the second conductive plate.6. The system of claim 1 , further comprising a transfer rate modification material claim 1 , the transfer rate modification material positioned between the first conductive plate and the second conductive plate claim 1 , wherein at least a portion of the transfer rate modification material abuts the memristor material claim 1 , wherein the transfer rate modification material provides a shift in a ...

PROGRAMMABLE METALLIZATION CELL WITH ALLOY LAYER

An embodiment includes a programmable metallization cell (PMC) memory comprising: a top electrode and a bottom electrode; a metal layer between the top and bottom electrodes; and a solid electrolyte (SE) layer between the metal layer and the bottom electrode; wherein (a) the metal layer includes an alloy of first and second metals, and (b) metal ions from the first metal form a conductive path in the SE layer when the top electrode is positively biased and disband the conductive path when the top electrode is negatively biased. Other embodiments are described herein. 1. A programmable metallization cell (PMC) memory comprising:a top electrode and a bottom electrode;a metal layer between the top and bottom electrodes; anda solid electrolyte (SE) layer between the metal layer and the bottom electrode;wherein the metal layer includes an alloy of first and second metals.2. The memory of comprising a barrier layer between the metal layer and the top electrode.3. The memory of claim 2 , wherein the metal layer directly contacts the SE layer.4. The memory of claim 3 , wherein:the first metal is selected from the group comprising copper, silver, and nickel and the second metal is selected from the group comprising palladium, platinum, tungsten, cobalt, and aluminum.5. The memory of claim 4 , wherein metal ions from the first metal form a conductive path in the SE layer when the top electrode is positively biased and disband the conductive path when the top electrode is negatively biased.6. A memory comprising:a top electrode and a bottom electrode;a metal layer between the top and bottom electrodes; anda solid electrolyte (SE) layer between the metal layer and the bottom electrode;wherein the metal layer includes at least one metal and at least one member selected from the group comprising copper, silver, and nickel.7. The memory of comprising a barrier layer between the metal layer and the top electrode.8. The memory of claim 7 , wherein the metal layer directly contacts ...

Method to Manufacture Highly Conductive Vias and PROM Memory Cells by Application of Electric Pulses

A vertical interconnect via having a first array of first metal interconnect wires extending along a first lateral direction made from a first material and a second array of second interconnect wires extending along a second lateral direction made from a second material. An intersection defined by the first array and the second array, wherein each intersection of the first array and the second array defines a metal-insulator-metal structure. The said metal-insulator-metal structure transforms to metal-metal-metal structure upon an application of electric pulse. 17-. (canceled)8. A method of forming an electrical connection in the metallization backend of an assembled integrated circuit post manufacture of the integrated circuit comprising steps of:providing a first electrode made of a first material and adapted to function as a terminal;providing a second electrode made of a second material and adapted to function as a terminal;providing an insulator layer between said first and said second electrodes; andapplying a voltage or current to one of said electrodes to create an active electrode while said other electrode is grounded, said voltage or current causes ions consisting of the material of the ungrounded electrode to form a conductor that electrically connects said electrodes.9. The method of wherein said active electrode is copper claim 8 , silver or nickel claim 8 , and said grounded electrode includes inert metals such as platinum claim 8 , iridium claim 8 , tungsten claim 8 , or rhodium.10. The method of wherein said conductor has a substantially consistent cross section.11. The method of wherein said conductor is irreversible when a subsequent voltage or current is applied.12. A method of forming an electrical connection in the metallization backend of an assembled integrated circuit post manufacture of the integrated circuit comprising steps of:providing a first array of electrodes made of a first material and said electrodes adapted to function as one or ...

NONVOLATILE MEMORY ELEMENT AND METHOD FOR MANUFACTURING THE SAME

A nonvolatile memory element includes a first and a second electrode layers, and a variable resistance layer provided between the first and the second electrode layers and having a resistance value reversibly changing according to application of an electrical pulse, wherein the variable resistance layer includes a first variable resistance layer contacting the first electrode layer and comprising an oxygen-deficient first metal oxide, and a second variable resistance layer contacting the first variable resistance layer and comprising a second metal oxide having a smaller oxygen deficiency than the first metal oxide, and including host layers and an inserted layer between each of adjacent pairs of the host layers, wherein the second metal oxide of the inserted layer has a larger oxygen deficiency than the second metal oxide of the host layer, and the first metal oxide has a larger oxygen deficiency than the second metal oxide of the host layer. 1. A nonvolatile memory element comprising:a first electrode layer;a second electrode layer; anda variable resistance layer which is provided between the first electrode layer and the second electrode layer and has a resistance value which reversibly changes according to application of an electrical pulse,wherein the variable resistance layer includes a first variable resistance layer which is in contact with the first electrode layer and comprises an oxygen-deficient first metal oxide, and a second variable resistance layer which is in contact with the first variable resistance layer, comprises a second metal oxide, and includes a plurality of host layers and an inserted layer provided between each of adjacent pairs of the host layers, the second metal oxide having a degree of oxygen deficiency smaller than a degree of oxygen deficiency of the first metal oxide, anda degree of oxygen deficiency of the second metal oxide of the inserted layer is larger than a degree of oxygen deficiency of the second metal oxide of the host ...

Methods of Using A Two Terminal Multi-Layer Thin Film Resistance Switching Device With A Diffusion Barrier

An electric-pulse-induced-resistance change device (EPIR device) is provided which is a resistance switching device. It has a buffer layer inserted between a first active resistance switching layer and a second active resistance switching layer, with both active switching layers connected to electrode layers directly or through additional buffer layers between the active resistance switching layers and the electrodes. This device in its simplest form has the structure: electrode-active layer-buffer layer-active layer-electrode. The second active resistance switching layer may, in the alternative, be an ion donating layer, such that the structure becomes: electrode-active layer-buffer layer-ion donating layer-electrode. The EPIR device is constructed to mitigate the retention challenge. 1. A method of using a two terminal multi-layer thin film resistance switching device comprising:providing a two terminal multi-layer thin film resistance switching device comprising:a first electrode;a second electrode;first and second active switching layers between the first and second electrodes; anda buffer layer between the first and second active switching layers;applying an electrical pulse between the first and second electrodes to create an electrical field or to inject an electrical current in the active resistance switching layers greater than a threshold electric field value that changes the resistance of the device;and using the thin film resistance switching device as a resistive random access memory device.2. The method of wherein the thin film resistance switching device is used as a variable resistor in electronic circuits.3. The method of wherein the thin film resistance switching device is used as a sensor.4. The method of wherein the duration of the electrical pulse ranges from about 1 msec to about 1 nsec.5. The method of wherein the magnitude of the electrical pulse ranges from about 1 V to about 10 V.6. The method of wherein a DC signal is applied to the device ...

SWITCHING DEVICE, AND RESISTIVE RANDOM ACCESS MEMORY INCLUDING THE SAME AS A SELECTION DEVICE

A switching device includes a first electrode, a switching layer having a non-memory characteristic, and a second electrode that are disposed over a substrate. The switching layer includes an oxide of a first atom or a nitride of the first atom, and a second atom is doped in the oxide or the nitride. The second atom forms a trap site trapping a conductive carrier in the switching layer when a voltage having an absolute value that is smaller than an absolute value of a predetermined threshold voltage is applied between the first and the second electrodes. The second atom forms a moving path through which the conductive carrier moves between the first electrode and the second electrode when a voltage having an absolute value that is greater than an absolute value of a predetermined threshold voltage is applied between the first and the second electrodes. 1. A switching device , comprising:a first electrode, a switching layer having a non-memory characteristic, and a second electrode that are disposed over a substrate,wherein the switching layer includes an oxide of a first atom or a nitride of the first atom, and a second atom doped in the oxide or the nitride, andwherein the second atom forms a trap site trapping a conductive carrier in the switching layer when a voltage having an absolute value that is smaller than an absolute value of a predetermined threshold voltage is applied between the first and the second electrodes, andwherein the second atom forms a moving path through which the conductive carrier moves between the first electrode and the second electrode when a voltage having an absolute value that is greater than an absolute value of a predetermined threshold voltage is applied between the first and the second electrodes.2. The switching device of claim 1 , wherein the oxide of the first atom comprises silicon oxide or metal oxide.3. The switching device of claim 2 , wherein the metal oxide includes at least one selected from aluminum oxide claim 2 , ...

SWITCHING ELEMENT, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

In the cases of performing programming by forming a two-terminal-type variable resistance element on a semiconductor device, it has been difficult to control the programming, and malfunctions have often occurred. This switching element includes at least a first variable resistance element, a second variable resistance element, a first rectifying element, and a second rectifying element, one end of the first variable resistance element and one end of the second variable resistance element are respectively connected to one end of the first rectifying element and one end of the second rectifying element, and each of the rectifying elements has two terminals. 1. A switching element comprising: a first variable-resistance element , a second variable-resistance element , a first rectifying element , and a second rectifying element , whereineach of the first rectifying element and the second rectifying element is a two-terminal element, andone end portion of the first variable-resistance element and one end portion of the second variable-resistance element are connected to one end portion of the first rectifying element and one end portion of the second rectifying element.2. The switching element according to claim 1 , whereinthe switching element is to be inserted in a signal path, andinput and output are performed through unconnected terminals of the first variable-resistance element and the second variable-resistance element, and resistance states of the first variable-resistance element and the second variable-resistance element are controlled through unconnected terminals of the first rectifying element and the second rectifying element.3. The switching element according to claim 1 , whereinprogramming of the first variable-resistance element is performed through the second rectifying element, andprogramming of the second variable-resistance element is performed through the first rectifying element.4. The switching element according to claim 1 , whereineach of the ...

RESISTIVE MEMORY CELL WITH INTRINSIC CURRENT CONTROL

Providing for a two-terminal memory cell having intrinsic current limiting characteristic is described herein. By way of example, the two-terminal memory cell can comprise a particle donor layer having a moderate resistivity, comprised of unstable or partially unstable metal compounds. The metal compounds can be selected to release metal atoms in response to an external stimulus (e.g., an electric field, a voltage, a current, heat, etc.) into an electrically-resistive switching medium, which is at least in part permeable to drift or diffusion of the metal atoms. The metal atoms form a thin filament through the switching medium, switching the memory cell to a conductive state. The moderate resistivity of the particle donor layer in conjunction with the thin filament can result in an intrinsic resistance to current through the memory cell at voltages above a restriction voltage, protecting the memory cell from excessive current. 1. A method for an electronic device having a non-volatile memory cell , comprising:applying a program signal across a first electrode and a second electrode of the non-volatile memory cell;providing from a particle donor layer adjacent to the second electrode to an electrically-resistive switching layer disposed between the particle donor layer and the first electrode, current-carrying particles in response to the program signal;beginning formation of a conductive filament in the electrically-resistive switching layer in response to the current-carrying particles from the particle donor layer and to the program signal;wherein the particle donor layer maintains a first resistance during the beginning formation of the conductive filament;completing formation of the conductive filament in the electrically-resistive switching layer in response to the current-carrying particles from the particle donor layer and to the program signal; andwherein the particle donor layer changes resistance from the first resistance to the second resistance in ...

MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

A memory device according to an embodiment includes an ion metal layer, an opposing electrode, and a resistance change layer. The ion metal layer contains a first metal and a second metal. The resistance change layer is disposed between the ion metal layer and the opposing electrode. The first metal is able to move repeatedly through an interior of the resistance change layer. The concentration of the first metal in a central portion of the ion metal layer is higher than the concentration of the first metal in an end portion of the ion metal layer. 1. A memory device , comprising:an ion metal layer containing a first metal and a second metal;an opposing electrode; anda resistance change layer disposed between the ion metal layer and the opposing electrode, the first metal being able to move repeatedly through an interior of the resistance change layer,the concentration of the first metal in a central portion of the ion metal layer being higher than the concentration of the first metal in an end portion of the ion metal layer.2. The memory device according to claim 1 , wherein the concentration of the second metal in the end portion of the ion metal layer is higher than the concentration of the second metal in the central portion of the ion metal layer.3. The memory device according to claim 1 , wherein the concentration of oxygen in the end portion of the ion metal layer is higher than the concentration of oxygen in the central portion of the ion metal layer.4. The memory device according to claim 1 , wherein the concentration of nitrogen in the end portion of the ion metal layer is higher than the concentration of nitrogen in the central portion of the ion metal layer.5. The memory device according to claim 1 , wherein the second metal has a property of oxidizing more easily than the first metal.6. The memory device according to claim 1 , wherein the second metal has a property of nitriding more easily than the first metal.7. The memory device according to claim 1 ...

MEMORY ELEMENT WITH ION SOURCE LAYER AND MEMORY DEVICE

A method of making memory element, including: a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer containing an oxide, and the resistance change layer being provided on the first electrode side, and an ion source layer in a stacking structure of two or more of a unit ion source layer, the unit ion source layer including a first layer and a second layer, the first layer containing one or more of chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se) and an easy-to-move element that is easy to move in the memory layer, and having a density distribution of the easy-to-move element from the first electrode to the second electrode, and the second layer containing a difficult-to-move element that is difficult to move in the memory layer. 1. A method , comprising forming a first electrode , a memory layer , and a second electrode in this order , wherein the memory layer includes:(a) a resistance change layer containing an oxide,(b) an ion source layer in comprising a stacking structure of two or more of a unit ion source layers, each unit ion source layer including a first layer and a second layer, the first layer containing (i) chalcogen elements of tellurium (Te), sulfur (S), or selenium (Se) or any combination of them and (ii) an easy-to-move element that is easy to move in the memory layer, the first layer having a non-uniform distribution of the easy-to-move element from the first electrode to the second electrode, the second layer containing a difficult-to-move element that is difficult to move in the memory layer, the easy-to-move element being able to diffuse more easily into the memory layer than the difficult-to-move element.2. The method according to claim 1 , wherein the unit ion source layer includes the first layer and the second layer in this order from the first electrode side.3. The method according to claim 1 , wherein the unit ion source layer includes the second layer ...

INTERCONNECTION FOR MEMORY ELECTRODES

Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level. 1. (canceled)2. An apparatus , comprising: a plurality of memory cells; and', a first electrode line of the plurality of electrode lines terminates at a first socket region; and', 'a second electrode line of the plurality of electrode lines terminates at a second socket region; and, 'a plurality of electrode lines each coupled with one or more of the plurality of memory cells, the plurality of electrode lines each extending in a first direction, wherein], 'a memory array comprisinga vertical connector coupled with the second electrode line, wherein the vertical connector is within the first socket region.3. The apparatus of claim 2 , further comprising:a second vertical connector; a third electrode line of the second plurality of electrode lines terminates at a third socket region; and', 'a fourth electrode line of the second plurality of electrode lines terminates at a fourth socket region; and, 'a second plurality of electrode lines each coupled with one or more of the plurality of memory cells, the second plurality of electrode lines each extending in a second direction, wherein, 'wherein the memory array further comprises'}wherein the second vertical connector is coupled with the fourth electrode line and is within the third socket region.4. The apparatus of claim 3 , wherein:the second electrode line crosses at least two boundaries of the first socket region; and the fourth electrode line crosses at least two boundaries of the third socket region.5. The apparatus of claim 3 , further comprising:a first driver coupled with the vertical connector and the second electrode line, wherein the first driver is included in a ...

AL-W-O STACK STRUCTURE APPLICABLE TO RESISTIVE RANDOM ACCESS MEMORY

An Al-W-O stack structure applicable to a resistive random access memory according to an embodiment of the invention comprises a tungsten top electrode, a tungsten oxide layer formed on the tungsten lower electrode, an aluminum oxide layer formed on the tungsten oxide layer and an aluminum top electrode formed on the aluminum oxide layer. The invention utilizes the different properties of two metals, namely aluminum and tungsten in bonding with oxygen ions, to obtain a resistive random access memory with more stable performances, lower power consumption and larger high resistance-low resistance ratio. 1. An Al-W-O stack structure applicable to a resistive random access memory , comprising:a tungsten bottom electrode;a tungsten oxide layer formed on the tungsten lower electrode;an aluminum oxide layer formed on the tungsten oxide layer; andan aluminum top electrode formed on the aluminum oxide layer.2. The Al-W-O stack structure applicable to the resistive random access memory according to claim 1 , characterized in that the tungsten oxide layer is formed in a thermal oxidation way.3. The Al-W-O stack structure applicable to the resistive random access memory according to claim 1 , characterized in that a thickness of the tungsten oxide layer is 30-70 nm.4. The Al-W-O stack structure applicable to the resistive random access memory according to claim 1 , characterized in that the aluminum oxide layer is formed in a contact type oxidation way.5. The Al-W-O stack structure applicable to the resistive random access memory according to claim 1 , characterized in that a temperature of the contact type oxidation is 400-500° C. claim 1 , and a time of the contact type oxidation is 50-200 s.6. The Al-W-O stack structure applicable to the resistive random access memory according to claim 1 , characterized in that a thickness of the aluminum oxide layer is 3-10 nm. The present application is a national filing in the U.S. Patent & Trademark Office of PCT/CN2014/078496 filed May ...

SEMICONDUCTOR DEVICES, HYBRID TRANSISTORS, AND RELATED METHODS

A semiconductor device is disclosed. The semiconductor device includes a hybrid transistor including a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a low bandgap high mobility material relative to the channel material that is high bandgap low mobility material. Memory arrays, semiconductor devices, and systems incorporating memory cells, and hybrid transistors are also disclosed, as well as related methods for forming and operating such devices. 1. A semiconductor device , comprising: a gate electrode;', 'a drain material;', 'a source material; and', 'a channel material operatively coupled between the drain material and the source material, wherein the source material and the drain material include a low bandgap high mobility material relative to the channel material that is high bandgap low mobility material., 'a hybrid transistor including2. The semiconductor device of claim 1 , wherein the source material and the drain material include a doped semiconductor material.3. The semiconductor device of claim 2 , wherein the channel material includes an oxide semiconductor material.4. The semiconductor device of claim 3 , wherein the oxide semiconductor material includes ZTO claim 3 , IGZO claim 3 , IZO claim 3 , ZnOx claim 3 , InOx claim 3 , In2O3 claim 3 , SnO2 claim 3 , TiOx claim 3 , ZnxOyNz claim 3 , MgxZnyOz claim 3 , InxZnyOz claim 3 , InxGayZnzOa claim 3 , ZrxInyZnzOa claim 3 , HfxInyZnzOa claim 3 , SnxInyZnzOa claim 3 , AlxSnyInzZnaOd claim 3 , SixInyZnzOa claim 3 , ZnxSnyOz claim 3 , AlxZnySnzOa claim 3 , GaxZnySnzOa claim 3 , ZrxZnySnzOa claim 3 , InGaSiO.5. The semiconductor device of claim 4 , wherein the doped semiconductor material is selected from the group consisting of Si claim 4 , GE claim 4 , SiGe claim 4 , SiCo claim 4 , and TMD.6. The semiconductor device of claim 3 , wherein the channel material ...

RESISTANCE CHANGE DEVICE, MANUFACTURING METHOD FOR THE SAME, AND STORAGE APPARATUS

A resistance change device includes a first resistance change layer that occludes and discharges ions of at least one type, and resistance of the first resistance change layer, changes in accordance with an amount of the ions in such a manner that the resistance decreases when the ions are discharged and the resistance increases when the ions are occluded; a second resistance change layer that occludes and discharges the ions, and resistance of the second resistance change layer changes in accordance with the amount of the ions in such a manner that the resistance increases when the ions are discharged and the resistance decreases when the ions are occluded; and an ion conductive layer that carries the ions and is provided between the first resistance change layer and the second resistance change layer. 1. A resistance change device comprising:a first resistance change layer that occludes and discharges ions of at least one type, and resistance of the first resistance change layer changes in accordance with an amount of the ions in such a manner that the resistance decreases when the ions are discharged and the resistance increases when the ions are occluded;a second resistance change layer that occludes and discharges the ions, and resistance of the second resistance change layer changes in accordance with the amount of the ions in such a manner that the resistance increases when the ions are discharged and the resistance decreases when the ions are occluded; andan ion conductive layer that carries the ions and is provided between the first resistance change layer and the second resistance change layer.2. The resistance change device according to claim 1 ,wherein the ions discharged from the first resistance change layer pass through the Ion conductive layer to be occluded in the second resistance change layer, andthe ions discharged from the second resistance change layer pass through the ion conductive layer to be occluded in the first resistance change layer.3. ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

According to one embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer separated from the first conductive layer in a first direction, a resistance change layer provided between the first and second conductive layers, a third conductive layer, a fourth conductive layer and a first intermediate layer. The third conductive layer is arranged with the first conductive layer in a second direction crossing the first direction. The fourth conductive layer is arranged with the second conductive layer in a direction crossing the first direction. The fourth conductive layer is arranged with the third conductive layer in the first direction. The fourth conductive layer is electrically connected with the third conductive layer. The first intermediate layer is provided between a portion of the third conductive layer and a portion of the fourth conductive layer. 1. A semiconductor memory device comprising:a first conductive layer;a second conductive layer separated from the first conductive layer in a first direction;a first resistance change layer provided between the first conductive layer and the second conductive layer;a third conductive layer arranged with the first conductive layer in a second direction crossing the first direction, the third conductive layer containing a material contained in the first conductive layer;a fourth conductive layer arranged with the second conductive layer in a direction crossing the first direction, the fourth conductive layer being arranged with the third conductive layer in the first direction, electrically connected with the third conductive layer, and containing a material contained in the second conductive layer; anda first intermediate layer provided between a portion of the third conductive layer and a portion of the fourth conductive layer and containing a material contained in the first resistance change layer.2. The device according to claim 1 , further comprising a fifth conductive ...

VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

A variable resistanvce memory device may include a plurality of first conductive lines extending in a first direction, a plurality of second conductive lines extending in a second direction, a plurality of memory cells, each memory cell at a respective intersection, with respect to a top down view, between a corresponding one of the first conductive lines and a corresponding one of the second conductive lines, each memory cell comprising a variable resistance structure and a switching element sandwiched between a top electrode and a bottom electrode, and a first dielectric layer filling a space between the switching elements of the memory cells. A top surface of the first dielectric layer is disposed between bottom and top surfaces of the top electrodes of the memory cells. 1. A variable resistance memory device , comprising:a plurality of first conductive lines extending in a first direction;a plurality of second conductive lines extending in a second direction;a plurality of memory cells, each memory cell at a respective intersection, with respect to a top down view, between a corresponding one of the first conductive lines and a corresponding one of the second conductive lines, each memory cell comprising a variable resistance structure and a switching element sandwiched between a top electrode and a bottom electrode; anda first dielectric layer filling a space between the switching elements of the memory cells,wherein a top surface of the first dielectric layer is disposed between bottom and top surfaces of the top electrodes of the memory cells.2. The variable resistance memory device of claim 1 , further comprising a second dielectric layer on the first dielectric layer and filling a space between the top electrodes of the memory cells claim 1 ,wherein the first dielectric layer has a dielectric constant less than a dielectric constant of the second dielectric layer.3. The variable resistance memory device of claim 2 , wherein the first dielectric layer ...

SCALED NANOTUBE ELECTRODE FOR LOW POWER MULTISTAGE ATOMIC SWITCH

A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal. 1. A switch containing device comprising:a carbon nanotube present on a substrate to provide a first electrode of the switch;a dielectric for cation transportation present on the first electrode; anda second electrode comprised of a metal present on a surface of the dielectric for cation transportation that is opposite the surface of the dielectric for cation transportation that is in contact with the first electrode.2. The switch of claim 1 , wherein the carbon nanotube is a single wall carbon nanotube (SWCNT)31. The switch of claim 1 , wherein the carbon nanotube has a diameter D ranging from 1 nm to 2 nm.4. The switch of claim 1 , wherein the carbon nanotube has a length that ranges from about 0.5 nanometers to about 10 microns.5. The switch of claim 1 , wherein the carbon nanotube is present within a trench defined by sidewalls of silicon oxide.6. The switch of claim 1 , wherein the carbon nanotube is present on a hafnium containing layer.7. The switch of claim 1 , wherein the carbon nanotube is present on a hafnium containing layer within a trench claim 1 , wherein the carbon nanotube is aligned with by chemical recognition.8. The switch of claim 1 , wherein the dielectric for cation transportation has a composition selected from the group consisting of GeSe claim 1 , GeS claim 1 , CuS claim 1 , CuO claim 1 , AgS claim 1 , and SiO.9. The switch of claim 1 , wherein the first electrode is of said metal having a composition selected from the group consisting of silver (Ag) claim 1 , copper (Cu) claim 1 , ...

RESISTIVE MEMORY CROSSBAR ARRAY EMPLOYING SELECTIVE BARRIER LAYER GROWTH

A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a barrier layer over at least one conductive line of the plurality of conductive lines, the barrier layer directly contacting an entire upper surface of the at least one conductive line, and forming a RRAM stack including a bottom electrode, a high-k dielectric layer, and a top electrode over the barrier layer. 1. A method for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array , the method comprising:forming a plurality of conductive lines within an interlayer dielectric (ILD);forming a refractory metal barrier layer over at least one conductive line of the plurality of conductive lines; andforming a RRAM stack;wherein upper surface areas of the refractory metal barrier layer remain exposed after formation of outer spacers.2. The method of claim 1 , wherein the refractory metal barrier layer directly contacts an entire upper surface of the at least one conductive line.3. The method of claim 1 , wherein the RRAM stack includes a bottom electrode claim 1 , a metal-containing oxide layer claim 1 , and a top electrode over the refractory metal barrier layer.4. The method of claim 3 , further comprising forming an encapsulation layer over the RRAM stack before formation of the outer spacers.5. The method of claim 4 , further comprising etching the encapsulation layer to form the outer spacers adjacent the RRAM stack.6. The method of claim 5 , further comprising forming a low-k dielectric layer over the RRAM stack.7. The method of claim 6 , further comprising forming a plurality of sacrificial layers over the low-k dielectric layer.8. The method of claim 7 , further comprising selectively recessing the plurality of sacrificial layers to create an opening in alignment with the RRAM stack.9. The method ...

RESISTIVE MEMORY CROSSBAR ARRAY EMPLOYING SELECTIVE BARRIER LAYER GROWTH

A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a barrier layer over at least one conductive line of the plurality of conductive lines, the barrier layer directly contacting an entire upper surface of the at least one conductive line, and forming a RRAM stack including a bottom electrode, a high-k dielectric layer, and a top electrode over the barrier layer. 1. A semiconductor structure for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array , the semiconductor structure comprising:a plurality of conductive lines disposed within an interlayer dielectric (ILD);a refractory metal barrier layer disposed over at least one conductive line, the refractory metal barrier layer directly contacting an entire upper surface of the at least one conductive line; anda RRAM stack disposed over the refractory metal barrier layer, the RRAM stack including a bottom electrode, a high-k dielectric layer, and a top electrode.2. The semiconductor structure of claim 1 , wherein the refractory metal barrier layer includes tantalum nitride (TaN).3. The semiconductor structure of claim 1 , wherein the bottom electrode includes titanium nitride (TiN).4. The semiconductor structure of claim 1 , wherein the top electrode includes titanium nitride (TiN).5. The semiconductor structure of claim 1 , wherein spacers are formed adjacent the RRAM stack.6. The semiconductor structure of claim 5 , wherein the spacers directly contact a top surface of the refractory metal barrier layer.7. The semiconductor structure of claim 6 , wherein the spacers include silicon nitride (SiN).8. The semiconductor structure of claim 7 , wherein a via is formed over the RRAM stack and is filled with a conductive material.9. The semiconductor structure of claim 8 , wherein the conductive material ...

CONDUCTIVE BRIDGE SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD THEREFOR

The present disclosure provides a conductive bridge semiconductor device and a method of manufacturing the same. The conductive bridge semiconductor device includes a lower electrode, a resistive switching functional layer, an ion barrier layer and an active upper electrode from bottom to top, wherein the ion barrier layer is provided with certain holes through which active conductive ions pass. Based on this structure, the precise designing of the holes on the barrier layer facilitates the modulation of the quantity, size and density of the conduction paths in the conductive bridge semiconductor device, which enables that the conductive bridge semiconductor device can be modulated to be a nonvolatile conductive bridge resistive random access memory or a volatile conductive bridge selector. Based on the above method, ultra-low power nonvolatile conductive bridge memory and high driving-current volatile conductive bridge selector with controllable polarity are completed. 114-. (canceled)15. A conductive bridge semiconductor device , comprising a lower electrode , a resistive switching functional layer , an ion barrier layer and an active upper electrode from bottom to top , wherein the ion barrier layer is provided with certain holes through which active conductive ions pass.16. The conductive bridge semiconductor device according to claim 15 , wherein the conductive bridge semiconductor device is a conductive bridge resistive random access memory claim 15 , the hole in the ion barrier layer is one claim 15 , and a radial size of the hole is between 5 nm and 200 nm.17. The conductive bridge semiconductor device according to claim 16 , wherein the hole is located at a central position of the ion barrier layer.18. The conductive bridge semiconductor device according to claim 16 , wherein the ion barrier layer is made of at least one of the following materials: graphene claim 16 , MoS claim 16 , BN claim 16 , Ti claim 16 , TiW claim 16 , Ta claim 16 , TaSiN claim 16 , ...

MEMORY DEVICE

According to one embodiment, a memory device includes a first electrode, a second electrode and an insulating portion. The first electrode includes an ionizable metal. The second electrode includes a conductive material. The conductive material is more difficult to ionize than the metal. The insulating portion is provided between the first electrode and the second electrode. The insulating portion is made of an insulating material. A space is adjacent to a side surface of the insulating portion between the first electrode and the second electrode. 1. A memory device , comprising:a first electrode including an ionizable metal;a second electrode including a conductive material, the conductive material being more difficult to ionize than the metal; andan insulating portion provided between the first electrode and the second electrode, the insulating portion being made of an insulating material,a space being adjacent to a side surface of the insulating portion between the first electrode and the second electrode.2. The device according to claim 1 , wherein the insulating material includes silicon and nitrogen.3. The device according to claim 1 , wherein the first electrode includes at least one type of metal material selected from the group consisting of silver claim 1 , copper claim 1 , nickel claim 1 , cobalt claim 1 , titanium claim 1 , aluminum claim 1 , and gold.4. The device according to claim 1 , further comprising an insulating layer interposed between the second electrode and the side surface of the insulating portion facing the space.5. The device according to claim 4 , wherein the insulating layer includes silicon or germanium.6. The device according to claim 1 , wherein a filament is formed from the first electrode toward the second electrode on the side surface of the insulating portion facing the space when a voltage is applied to cause the first electrode to be positive and the second electrode to be negative.7. A memory device claim 1 , comprising:a ...

MEMRISTIVE CROSSBAR ARRAY HAVING MULTI-SELECTOR MEMRISTOR CELLS

A memristive crossbar array is described. The crossbar array includes a number of row lines and a number of column lines intersecting the row lines to form a number of cross points. A number of memristor cells are coupled between the row lines and the column lines at the cross points. A memristor cell includes a memristive memory element to store information and multiple selectors electrically coupled to the memristive memory element. The multiple selectors are to provide access to the memristive memory element. 1. A memristive crossbar array , the crossbar array comprising:a number of row lines;a number of column lines intersecting the row lines to form a number of cross points; anda number of memristor cells coupled between the row lines and the column lines at the cross points, a memristor cell comprising:a memristive memory element to store information; andmultiple selectors electrically coupled to the memristive memory element, the multiple selectors to provide access to the memristive memory element.2. The array of claim 1 , wherein the multiple selectors are serially coupled to the memristive memory element.3. The array of claim 1 , wherein the multiple selectors are asymmetric selectors.4. The array of claim 3 , wherein:a first selector is tuned towards a first voltage polarity; anda second selector is tuned towards a second, and opposite, voltage polarity.5. The array of claim 1 , wherein a selector is a volatile selector comprising:a first electrode;a second electrode; andan active region disposed between the first electrode and the second electrode;in which the active region comprises cationic species that aggregate to form a conductive channel between the first electrode and the second electrode when a selecting voltage is applied and that dissipate when the selecting voltage is removed.6. The array of claim 1 , wherein the multiple selectors are non-liner selectors having a nonlinearity of greater than 1 claim 1 ,000.7. A system for accessing ...

MEMORY DEVICE HAVING VIA LANDING PROTECTION

A memory cell with a hard mask and a sidewall spacer of different material is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A hard mask disposed over the top electrode. A sidewall spacer extends upwardly along sidewalls of the switching dielectric, the top electrode, and the hard mask. The hard mask and the sidewall spacer have different etch selectivity. A method for manufacturing the memory cell is also provided. 1. A memory cell , comprising:a bottom electrode disposed over a substrate;a switching dielectric disposed over the bottom electrode and having a variable resistance;a top electrode disposed over the switching dielectric;a hard mask disposed over the top electrode;a sidewall spacer extending upwardly along sidewalls of the switching dielectric, the top electrode, and the hard mask; anda top metallization line surrounded by a top interlayer dielectric layer and coupled to the top electrode through a top electrode via;wherein the hard mask and the sidewall spacer have different etch selectivity;wherein the top electrode via has a bottom that directly contacts an upper surface of the top electrode and a lower sidewall that directly contacts the sidewall spacer along an interface above the top electrode.2. The memory cell of claim 1 , wherein the hard mask is made of silicon carbide and the sidewall spacer is made of silicon nitride.3. The memory cell of claim 1 , wherein the hard mask directly contacts the top electrode.4. The memory cell of claim 1 , wherein a top surface of the sidewall spacer directly contacts the sidewall of the hard mask and is located lower than a top surface of the hard mask.5. The memory cell of claim 1 , further comprising:a bottom metallization line surrounded by a bottom interlayer dielectric layer and coupled to the bottom electrode through a ...

Resistive random access memory device containing replacement word lines and method of making thereof

A method of forming a resistive memory device includes forming an alternating stack of insulating layers and sacrificial material layers that extend along a first horizontal direction over a substrate, forming a laterally alternating sequence of vertical conductive lines and dielectric pillar structures that alternate along the first horizontal direction on sidewalls of the alternating stack, forming lateral recesses by removing the sacrificial material layers selective to the insulating layers, selectively growing resistive memory material portions from physically exposed surfaces of the vertical conductive lines in the lateral recesses, and forming electrically conductive layers over the resistive memory material portions in the lateral recesses.

Storage device and storage unit

A storage device includes: a first electrode; a storage layer including an ion source layer; and a second electrode. The first electrode, the storage layer, and the second electrode are provided in this order. The ion source layer contains a movable element, and has a volume resistivity of about 150 mΩ·cm to about 12000 mΩ·cm both inclusive.

Resistive Memory Cell Having A Spacer Region For Reduced Conductive Path Area / Enhanced Electric Field

A method of forming a resistive memory cell, e.g., CBRAM or ReRAM, includes forming a bottom electrode layer, forming an oxide region of an exposed area of the bottom electrode, removing a region of the bottom electrode layer proximate the oxide region to form a bottom electrode having a pointed tip or edge region. An electrically insulating mini-spacer region is formed adjacent the bottom electrode, and an electrolyte region and top electrode are formed over the bottom electrode and mini-spacer element(s) to define a memory element. The memory element defines a conductive filament/vacancy chain path from the bottom electrode pointed tip region to the top electrode via the electrolyte region. The mini-spacer elements decreases the effective area, or “confinement zone,” for the conductive filament/vacancy chain path, which may improve the device characteristics, and may provide an improvement over techniques that rely on enhanced electric field forces. 1. A method of forming a resistive memory cell , comprising:forming a bottom electrode layer on a substrate;oxidizing an exposed region of the bottom electrode layer to form an oxide region;removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a sidewall and a pointed tip region at a top of the sidewall adjacent the oxide region;depositing a spacer layer over at least the pointed tip region of the bottom electrode and the adjacent oxide region;removing a portion of the spacer layer such that a spacer region remains laterally adjacent the sidewall of the bottom electrode;forming an electrolyte region and a top electrode over at least the spacer region, the pointed tip region of the bottom electrode, and the adjacent oxide region, such that the electrolyte region is arranged between the top electrode and the pointed tip region of the bottom electrode.2. The method according to claim 1 , wherein a direct path between the pointed tip region of the bottom ...

MEMORY COMPONENT, MEMORY DEVICE, AND METHOD OF OPERATING MEMORY DEVICE

A memory component including first and second electrodes with a memory layer therebetween, the memory layer having first and second memory layers, the first memory layer containing aluminum and a chalcogen element of tellurium, the second memory layer between the first memory layer and the first electrode and containing an aluminum oxide and at least one of a transition metal oxide and a transition metal oxynitride having a lower resistance than the aluminum oxide. 1. A memory device comprising:a first electrode;a second electrode; anda memory layer between the first and second electrodes, 'the memory layer includes (a) a first memory layer an ion source material, and (b) a second memory layer between the first memory layer and the first electrode and containing an aluminum oxide and a transition metal oxide, a transition metal oxynitride, or both.', 'wherein,'}2. The memory device of claim 1 , wherein the second memory layer has a first sublayer made of at least one of a transition metal oxide or a transition metal oxynitride and a second sublayer containing the aluminum oxide as its main component claim 1 , the second sublayer being between the first sublayer and the first electrode.3. The memory device of claim 1 , wherein the first memory layer contains a chalcogen element selected from the group consisting of tellurium (Te) claim 1 , sulfur (S) and selenium (Se).4. The memory device of claim 3 , wherein the aluminum oxide and the transition metal oxide claim 3 , the transition metal oxynitride claim 3 , or both are present in the first sub layer of the second memory layer in a mixed state.5. The memory device of claim 1 , wherein the transition metal oxide or the transition metal oxynitride is at least one oxide or oxynitride of a transition metal selected from the group consisting of titanium (Ti) claim 1 , zirconium (Zr) claim 1 , hafnium (Hf) claim 1 , vanadium (V) claim 1 , niobium (Nb) claim 1 , tantalum (Ta) claim 1 , chromium (Cr) claim 1 , molybdenum ( ...

PHYSICAL UNCLONABLE FUNCTIONS THROUGH LOCALLY ENHANCED DEFECTIVITY

A physical unclonable function (PUF) includes multiple logic gates and multiple random signal generation circuits connected to the logic gates, wherein, in at least a subset of the logic gates, each logic gate includes an input having a logic value that is specified by at least one of the random signal generation circuits. Each of the random signal generation circuits includes a random hard-defect feature, such as a random hard-defect shorted path. 1. A physical unclonable function , comprising:a plurality of logic gates; anda plurality of random signal generation circuits connected to the logic gates;wherein, in at least a subset of the logic gates, each logic gate includes an input having a logic value that is specified by at least one of the random signal generation circuits.2. The physical unclonable function of claim 1 , wherein each of the random signal generation circuits includes a random hard-defect feature.3. The physical unclonable function of claim 2 , wherein each random hard-defect feature has a fixed connectivity state that specifies one of a plurality of distinct logic values.4. The physical unclonable function of claim 2 , wherein at least one random hard-defect feature includes a transistor including a carbon nanotube with metallic chirality.5. The physical unclonable function of claim 2 , wherein at least one random hard-defect feature includes a memristor in a low resistance state.6. The physical unclonable function of claim 2 , wherein at least one random hard-defect feature includes multiple merged vias.7. The physical unclonable function of claim 2 , wherein at least one random hard-defect feature includes a transistor including a gate oxide having a conducting path through the gate oxide.8. The physical unclonable function of claim 1 , wherein at least one of the random signal generation circuits includes a capacitor and a random hard-defect feature connected in parallel with the capacitor.9. The physical unclonable function of claim 1 , ...

SELECTORS WITH OXIDE-BASED LAYERS

A selector with an oxide-based layer includes an oxide-based layer that has a first region and a second region. The first region contains a metal oxide in a first oxidation state, and the second region contains the metal oxide in a second oxidation state. The first region also forms a part of each of two opposite faces of the oxide-based layer. 1. A selector , comprising an oxide-based layer , wherein:the oxide-based layer comprises a first region having a metal oxide in a first oxidation state and a second region having the metal oxide in a second oxidation state; andthe first region forms a part of each of two opposite faces of the oxide-based layer.2. The selector of claim 1 , wherein the second region has two pads sandwiching the first region in a lateral direction of the oxide-based layer.3. The selector of claim 1 , wherein the metal oxide in the second oxidation state is less conducting than the metal oxide in the first oxidation state.4. The selector of claim 1 , wherein the selector exhibits nonlinear current-voltage behavior in a voltage range of interest.5. The selector of claim 1 , wherein the metal oxide has a metal selected from the group consisting of Nb claim 1 , V claim 1 , Ti claim 1 , W claim 1 , Ta claim 1 , Mo claim 1 , Zn claim 1 , and Cr.6. The selector of claim 1 , wherein the metal oxide has Nb claim 1 , the first oxidation state is NbO claim 1 , and the second oxidation state is NbO.7. A memory device claim 1 , comprising a selector with an oxide-based layer coupled to a memristor claim 1 , wherein:the oxide-based layer comprises a first region having a metal oxide in a first oxidation state and a second region having the metal oxide in a second oxidation state;the first region forms a part of each of two opposite faces of the oxide-based layer;the metal oxide in the second oxidation state is less conducting than the metal oxide in the first oxidation state; andthe memristor is coupled to at least a portion of the first region of the ...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

A nonvolatile semiconductor memory device includes a memory cell array. The memory cell array includes conducting layers, semiconductor layers, variable resistance films, and first wirings. The conducting layers are laminated in a first direction perpendicular to a substrate, and extend in a second direction parallel to the substrate. The semiconductor layers extend in the first direction. The variable resistance films are disposed at intersection points of the conducting layers and the semiconductor layers. Each first wiring is opposed to the semiconductor layer via a gate insulating film. The first wirings extend in the first direction. Each variable resistance film has a first thickness at a first part. The first thickness is in a direction from the conducting layers to the semiconductor layer. The variable resistance film has a second thickness at a second part. The second part is far from the substrate more than the first part. The second thickness is smaller than the first thickness. 1. A nonvolatile semiconductor memory device , comprisinga memory cell array that includes a plurality of memory cell s, wherein a plurality of conducting layers laminated at predetermined pitches in a first direction perpendicular to a substrate, the plurality of conducting layers extending in a second direction parallel to the substrate;', 'a semiconductor layer extending in the first direction;', 'a variable resistance film disposed at intersection points of the plurality of conducting layers and the semiconductor layer; and', 'a first wiring opposed to the semiconductor layer via a gate insulating film, the first wiring extending in the first direction,, 'the memory cell array includesthe variable resistance film has a first thickness at a first part, the first thickness being in a direction from the plurality of conducting layers to the semiconductor layer, andthe variable resistance film has a second thickness at a second part, the second part being further from the ...

Memristors and method for fabricating memristors

There are disclosed memristors and memristor fabrication methods. A memristor may include a stack of four functional elements including, in sequence, a first electrode, a barrier layer, an oxygen-deficient switching layer, and a second electrode.

NOVEL RESISTIVE RANDOM ACCESS MEMORY DEVICE

A memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle. 1. A memory device , comprising:a dielectric fin formed over a substrate;a memory cell disposed along and directly contacting a first sidewall of the dielectric fin, the memory cell comprising: a first conductor layer, a selector layer, a resistive material layer, and a second-conductor layer, wherein each of the first conductor layer, the selector layer, the resistive material layer, and the second conductor layer directly contact the first sidewall; anda capping layer disposed along and directly contacting each of the first conductor layer, the selector layer, the resistive material layer, and the second conductor layer along a second sidewall of the memory cell opposite the first sidewall of the dielectric fin,wherein the first conductor layer, the selector layer, the resistive material layer, and the second conductor layer each comprises upper and lower boundaries, and at least one of the upper and lower boundaries of each layer is tilted away from the first sidewall of the dielectric fin by an angle.2. The memory device of claim 1 , wherein the resistive material layer presents a variable resistance value.3. The memory device of claim 1 , wherein the angle is less than about 90 degrees.4. The memory device of claim 1 , wherein the memory cell further comprises:a third conductor layer, disposed between the first and second conductor layers, the third conductor layer directly contacting the first sidewall of ...

INTEGRATED CIRCUIT DEVICES BASED ON METAL ION MIGRATION AND METHODS OF FABRICATING SAME

The disclosed technology generally relates to integrated circuit (IC) devices and more particularly to IC devices based on metal ion migration, and to manufacturing of the IC devices. In one aspect, a method of manufacturing an integrated electronic circuit, which includes at least one component based on metal ion migration and reduction, allows improved control of an amount of the metal which is incorporated into the component. This amount is produced from a metal supply layer and transferred into a container selectively with respect to the rest of the component. The container is configured as part of an electrolyte portion or active electrode in the final component. The method is compatible with two-dimensional and three-dimensional configurations of the component. 1. A method of manufacturing an integrated electronic circuit which includes at least one component based on metal ion migration and reduction , the method comprising:providing a metal and a first material different from the metal and capable of containing ions or atoms of the metal, and providing at least one second material so that each second material is electrically insulating and has a capacity of containing the metal ions or metal atoms which is less than that of the first material;forming on a substrate of the integrated circuit a container comprising at least one portion of the first material and a boundary portion comprising at least one portion of the at least one second material, wherein the container and the boundary portion are next to each other;depositing a supply layer over the container and the boundary portion, the supply layer containing ions or atoms of the metal, such that a path from the supply layer to the container is available for some of the ions or atoms of the metal;activating a movement of some of the ions or atoms of the metal in the supply layer into at least part of the container selectively with respect to the boundary portion;removing the supply layer, while leaving ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films. 1forming a plurality of stacked films to extend in a first direction to be respectively stacked on a plurality of first interconnects extending in the first direction, each of the plurality of stacked films including a variable resistance film;forming a first inter-layer insulating film in a first region between the stacked films;forming a second inter-layer insulating film in a second region having a wider width than the first region;forming a plurality of second interconnects on the stacked films, on the first inter-layer insulating film, and on the second inter-layer insulating film to extend in a second direction crossing the first direction; andetching the stacked films and the first inter-layer insulating film under a space between the second interconnects,the second inter-layer insulating film under the space between the second interconnects being etched at an etching rate lower than an etching rate of the first inter-layer insulating film in the etching of the stacked films and the first inter-layer insulating film.. A method for manufacturing a semiconductor memory device, comprising: This application is a ...

MEMORY DEVICE AND METHOD FOR DRIVING SAME

A memory device includes a first interconnect extending in a first direction, a second interconnect extending in a second direction crossing the first direction, a third interconnect extending in a third direction crossing a plane including the first direction and the second direction, a fourth interconnect extending in the third direction, a semiconductor member, a first resistance change film, and a second resistance change film. The semiconductor member is connected between a first end of the second interconnect and the first interconnect. The first resistance change film is connected between a side surface of the second interconnect and the third interconnect. The second resistance change film is connected between a second end of the second interconnect and the fourth interconnect. 1. A memory device comprising:a first interconnect extending in a first direction;a second interconnect extending in a second direction crossing the first direction;a third interconnect extending in a third direction crossing a plane including the first direction and the second direction;a fourth interconnect extending in the third direction;a semiconductor member connected between a first end of the second interconnect and the first interconnect;a first resistance change film connected between a side surface of the second interconnect and the third interconnect; anda second resistance change film connected between a second end of the second interconnect and the fourth interconnect.2. The device according to claim 1 , whereinthe first end and the second end are both ends in the second direction of the second interconnect, andthe side surface is a surface facing the first direction of the second interconnect.3. The device according to claim 1 , further comprising:an electrode placed on the first direction side of the semiconductor member and extending in the third direction.4. The device according to claim 1 , wherein a nonlinear resistance layer having a resistance value depending on ...

RESISTIVE RANDOM ACCESS MEMORY CELL STRUCTURE

A system including a resistive element of a memory cell and a device to access the resistive element of the memory cell. The resistive element includes (i) a first electrode, and (ii) a second electrode. The device includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact. One or more of the first contact and the second contact of the device is respectively connected to one or more of the first electrode and the second electrode of the resistive element via a third contact. A size of the third contact decreases from the one or more of the first contact and the second contact of the device to the one or more of the first electrode and the second electrode of the resistive element of the memory cell. 1. A system comprising:a resistive element of a memory cell, wherein the resistive element includes (i) a first electrode, and (ii) a second electrode; anda device to access the resistive element of the memory cell, wherein the device includes (i) a first terminal connected to a first contact, and (i) a second terminal connected to a second contact,wherein one or more of the first contact and the second contact of the device is respectively connected to one or more of the first electrode and the second electrode of the resistive element via a third contact,wherein a size of the third contact decreases from the one or more of the first contact and the second contact of the device to the one or more of the first electrode and the second electrode of the resistive element of the memory cell.2. The system of claim 1 , wherein the third contact has a shape of a pyramid or a cone.3. The system of claim 1 , wherein the third contact is partially etched to reduce a volume of the third contact.4. The system of claim 1 , wherein:the third contact includes (i) a first surface in contact with the one or more of the first contact and the second contact of the device, and (ii) a second surface in contact with the one or more of ...

SEMICONDUCTOR MEMORY DEVICE

According to an embodiment, a semiconductor memory device comprises: a first wiring line; a memory string connected to this first wiring line; and a plurality of second wiring lines connected to this memory string. In addition, this memory string comprises: a first semiconductor layer connected to the first wiring line; a plurality of second semiconductor layers connected to this first semiconductor layer; and a variable resistance element connected between this second semiconductor layer and the second wiring line. Moreover, of the first semiconductor layer and the plurality of second semiconductor layers, one includes a semiconductor of a first conductivity type, and the other includes a semiconductor of a second conductivity type. 1. A semiconductor memory device , comprising:a first wiring line;a memory string connected to the first wiring line; anda plurality of second wiring lines connected to the memory string,the memory string comprising:a first semiconductor layer connected to the first wiring line;a plurality of second semiconductor layers connected to the first semiconductor layer; anda variable resistance element connected between the second semiconductor layer and the second wiring line,the first semiconductor layer including a semiconductor of a first conductivity type, andthe plurality of second semiconductor layers including a semiconductor of a second conductivity type.2. The semiconductor memory device according to claim 1 , further comprisinga select gate transistor connected between the first wiring line and the memory string,wherein the select gate transistor comprises a channel body including a semiconductor of the first conductivity type.3. The semiconductor memory device according to claim 1 , further comprisinga sense amplifier configured capable of connection to the second wiring line.4. The semiconductor memory device according to claim 1 , further comprising:a series resistance; anda driver configured capable of connection to the second ...

CONDUCTIVE BRIDGE MEMORY SYSTEM AND METHOD OF MANUFACTURE THEREOF

A conductive bridge memory system and method of manufacture thereof including: providing a dielectric layer having a hole on a bottom electrode, the hole over the bottom electrode; forming an ionic source layer in the hole and over the bottom electrode including: depositing a reactivation layer over the bottom electrode, depositing a first ion source layer on the reactivation layer, depositing another of the reactivation layer on the first ion source layer, depositing a second ion source layer on the another of the reactivation layer; and forming an upper electrode on the ionic source layer. 1. A method of manufacture of a conductive bridge memory system comprising:providing a dielectric layer having a hole on a bottom electrode, the hole over the bottom electrode; depositing a reactivation layer over the bottom electrode,', 'depositing a first ion source layer on the reactivation layer,', 'depositing another of the reactivation layer on the first ion source layer,', 'depositing a second ion source layer on the another of the reactivation layer; and, 'forming an ionic source layer in the hole and over the bottom electrode includingforming an upper electrode on the ionic source layer.2. The method as claimed in further comprising forming a resistance change layer in the hole and on the bottom electrode.3. The method as claimed in wherein depositing the first ion source layer includes:depositing an early transition metal; anddepositing a chalcogen.4. The method as claimed in wherein depositing the second ion source layer includes:depositing a late transition metal; anddepositing a chalcogen.5. The method as claimed in wherein depositing the reactivation layer includes:depositing an early main group metal; anddepositing a chalcogen.7. The method as claimed in further comprising connecting a transistor to the bottom electrode.8. The method as claimed in wherein depositing the first ion source layer includes:depositing zirconium; anddepositing tellurium.9. The method as ...

SOLID ELECTROLYTE FOR RERAM

A composition comprising 2. The composition according to claim 1 , wherein the ratio of the diffusion coefficient of M3 in the composition to the diffusion coefficient of M2 in the composition is at least 1000:1.3. The composition according to claim 1 , wherein the total concentration of alkaline metals and alkaline-earth metals is below 100 ppm claim 1 , based on the total weight of the composition.4. The composition according to claim 3 , wherein the total concentration of metals different from M1 claim 3 , M2 and M3 is below 100 ppm claim 3 , based on the total weight of the composition.5. The composition according to claim 1 , wherein the valence state of M1 is +III claim 1 , +IV or +V.6. The composition according to claim 1 , wherein M1 is selected from Si claim 1 , Hf claim 1 , Ta claim 1 , Zr claim 1 , Ti claim 1 , Al claim 1 , W or Ge.7. The composition according to claim 1 , wherein M2 is selected from the group consisting of B claim 1 , Al claim 1 , Ga claim 1 , In claim 1 , Tl claim 1 , Sc claim 1 , Y claim 1 , La claim 1 , Ac or mixtures thereof.8. The composition according to claim 1 , wherein M3 is selected from the group consisting of Ag or Cu.9. The composition according to claim 1 , whereinthe amount of M2 is 0.01 to 25 atom % based on the entirety of metals present in the composition; andthe amount of M3 is 0.01 to 10 atom % based on the entirety of metals present in the composition.11. A process for the production of the composition according to claim 1 , wherein the composition is prepared by atomic layer deposition (ALD) or chemical vapor deposition (CVD).12. The process of wherein the composition is prepared by ALD and the thickness of the layer is 1 to 100 nm.13. A method of using the product obtained by the process according to as a sputtering target for physical vapor deposition (PVD) processes.14. A method of using the composition according to as a resistive switching element.15. The composition according to wherein the atomic ratio of M1 ...

PROGRAMMABLE INTERPOSERS FOR ELECTRICALLY CONNECTING INTEGRATED CIRCUITS

Programmable interposers for connecting integrated circuits, methods for programming programmable interposers, and integrated circuit packaging are provided. The programmable interposers are electrically reconfigurable to allow custom system-in-package (SiP) operation and configuration, field configurability, and functional obfuscation for secure integrated circuits fabricated in non-trusted environments. The programmable interposer includes, in one implementation, an interposer substrate and a programmable metallization cell (PMC) switch. The PMC switch is formed on the interposer substrate and is coupled between a signal input and a signal output. The PMC switch is electrically configurable between a high resistance state and a low resistance state. 1. A programmable interposer for electrically connecting integrated circuits , the programmable interposer comprising:an interposer substrate; anda programmable metallization cell (PMC) switch formed on the interposer substrate and coupled between a signal input and a signal output, wherein the PMC switch is electrically configurable between a high resistance state and a low resistance state.2. The programmable interposer of claim 1 , further comprising a configuration controller coupled to the PMC switch and configured to set the PMC switch in the low resistance state or the high resistance state.3. The programmable interposer of claim 2 , wherein the PMC switch is a first PMC switch claim 2 , wherein the programmable interposer further comprising a second PMC switch claim 2 , wherein the configuration controller is further configured to set the second PMC switch in the low resistance state or the high resistance state.4. The programmable interposer of claim 1 , wherein the PMC switch includes a PMC element having:an insulating material,an ion conductor formed at least partially within the insulating material,an oxidizable electrode positioned proximate to the ion conductor, andan indifferent electrode positioned ...