WRITE VERIFY METHOD FOR RESISTIVE RANDOM ACCESS MEMORY

Write verify methods for resistance random access memory (RRAM) are provided. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state and applying a forward resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance value less than a selected lower resistance limit value. The method also includes applying a reverse resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance values is greater than a selected upper resistance limit value. The reverse resetting voltage pulse has a second polarity being opposite the first polarity. 1. A write verify method for resistance random access memory (RRAM) , the method comprising:providing a RRAM cell having a high resistance state, the high resistance state having a range of resistance values;applying a forward resetting voltage pulse across the RRAM cell if any of a range of high resistance state resistance values is less than a selected lower resistance limit value, the forward resetting voltage pulse having a first polarity; andapplying a reverse resetting voltage pulse across the RRAM cell if any of the range of high resistance state resistance values is greater than a selected upper resistance limit value, the reverse resetting voltage pulse having a second polarity being opposite the first polarity.2. A method according to claim 1 , wherein each successive forward resetting voltage pulse has a lower voltage level than a preceding pulse.3. A method according to claim 1 , wherein each successive forward resetting voltage pulse has a lower voltage duration than a preceding pulse.4. A method according to claim 1 , wherein each successive reverse resetting voltage pulse has a lower voltage level than a preceding pulse.5. A method according to claim 1 , wherein each successive reverse resetting voltage pulse has a lower voltage ...

PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING

Methods for making a programmable metallization memory cell are disclosed. 1. A programmable metallization memory cell comprising:an active electrode;an inert electrode; andan internal layer between the active electrode and the inert electrode, the internal layer comprising a fast ion conductor material and an apertured layer comprising a plurality of apertures defined by an electrically insulating material, the plurality of apertures extend between the active electrode and the inert electrode and the fast ion conductor material fill the plurality of apertures, the fast ion conductor material including superionic clusters present within the plurality of apertures.2. The memory cell of wherein the electrically insulating material comprises a dielectric material.3. The memory cell of wherein the fast ion conductor material comprises a chalcogenide material.4. The memory cell of wherein the fast ion conductor material comprises a germanium selenide material.5. The memory cell of wherein the apertured layer is adjacent the active electrode.6. The memory cell of wherein the apertured layer is adjacent the inert electrode.7. The memory cell of wherein the apertured layer is adjacent the active electrode and the inert electrode.8. The memory cell of wherein the plurality of apertures each have an aperture diameter of about 10 nm.9. A programmable metallization memory cell comprising:an active electrode;an inert electrode; andan internal layer between the active electrode and the inert electrode, the internal layer comprising a fast ion conductor material layer and an apertured layer comprising a plurality of apertures defined by an electrically insulating material, the apertured layer separating the fast ion conductor material layer and the active electrode the plurality of apertures defining at least a portion of a columnar superionic cluster within the fast ion conductor material.10. The memory cell of wherein the electrically insulating material comprises a dielectric ...

FLUX PROGRAMMED MULTI-BIT MAGNETIC MEMORY

An apparatus and associated method for a non-volatile memory cell, such as a multi-bit magnetic random access memory cell. In accordance with various embodiments, a first magnetic tunnel junction (MTJ) is adjacent to a second MTJ having a magnetic filter. The first MTJ is programmed to a first logical state with a first magnetic flux while the magnetic filter absorbs the first magnetic flux to prevent the second MTJ from being programmed. 1. A memory cell comprising a first magnetic tunnel junction (MTJ) adjacent a second MTJ having a magnetic filter , the first MTJ being programmed to a first logical state with a first magnetic flux while the magnetic filter absorbs the first magnetic flux to prevent the second MTJ from being programmed.2. The memory cell of claim 1 , wherein the absorption of the first magnetic flux saturates the magnetic filter and induces a transition from magnetically insulative to conductive.3. The memory cell of claim 1 , wherein the first and second MTJs are concurrently programmed by a second magnetic flux that is greater than a predetermined valued.4. The memory cell of claim 3 , wherein the first magnetic flux is below the predetermined value.5. The memory cell of claim 1 , wherein the magnetic flux is generated by current passing through a word line that is noncontactingly adjacent to the MTJs.6. The memory cell of claim 5 , wherein the first and second MTJs each extend along a long axis that is perpendicular to the flow of current along the word line.7. The memory cell of claim 1 , wherein the magnetic filter is a soft magnetic material that has a low coercivity.8. The memory cell of claim 1 , wherein the first and second MTJs are each coupled to a read line on a top surface and a source plane on a bottom surface.9. The memory cell of claim 8 , wherein the source plane is connected to a selection device that selectively allows reading of the first and second MTJs.10. The memory cell of claim 1 , wherein the first MTJ has a different ...

Magnetic Memory Cell With Multi-Level Cell (MLC) Data Storage Capability

Method and apparatus for writing data to a magnetic memory element, such as a spin-torque transfer random access memory (STRAM) memory cell. In accordance with various embodiments, a multi-level cell (MLC) magnetic memory cell stack has first and second magnetic memory elements connected to a first control line and a switching device connected to a second control line. The first memory element is connected in parallel with the second memory element, and the first and second memory elements are connected in series with the switching device. The first and second memory elements are further disposed at different non-overlapping elevations within the stack. Programming currents are passed between the first and second control lines to concurrently set the first and second magnetic memory elements to different programmed resistances. 1. An apparatus comprising a multi-level cell (MLC) magnetic memory cell stack having first and second magnetic memory elements connected to a first control line and a switching device connected to a second control line , the first memory element connected in parallel with the second memory element , the first and second memory elements each further connected in series with the switching device between the first and second control lines and disposed at respective out-of-plane axial elevations within the stack , wherein programming currents are passed between the first and second control lines to concurrently set the first and second magnetic memory elements to different programmed resistances.2. The apparatus of claim 1 , in which the first magnetic memory element is precessed to a selected magnetic orientation responsive to application of a write current through the cell having a first current density claim 1 , and the second magnetic memory element requires application of a write current through the cell having a higher claim 1 , second current density before precessing to the selected magnetic orientation.3. The apparatus of claim 1 , in ...

SPIN-TORQUE MEMORY WITH UNIDIRECTIONAL WRITE SCHEME

Spin torque magnetic memory elements that have a pinned layer, two free layers, and a current-blocking insulating layer proximate to at least one of the free layers. The resistive state (e.g., low resistance or high resistance) of the memory elements is altered by passing electric current through the element in one direction. In other words, to change from a low resistance to a high resistance, the direction of electric current is the same as to change from a high resistance to a low resistance. The elements have a unidirectional write scheme. 1. A memory element comprising: a first ferromagnetic free layer; and', 'a barrier layer; and, 'the first magnetic element comprising, 'a first magnetic element,'} the first ferromagnetic free layer;', 'a second ferromagnetic free layer;', 'a non magnetic spacer; and', 'an insulator layer having a via therethrough,, 'the second magnetic element comprising, 'a second magnetic element'}wherein the first magnetic element and the second magnetic element are configured in series.2. The memory element according to claim 1 , wherein the first magnetic element further comprises a pinned ferromagnetic layer.3. The memory element according to claim 2 , wherein the barrier layer is positioned between the pinned ferromagnetic layer and the first ferromagnetic free layer.4. The memory element according to claim 1 , wherein the non magnetic spacer layer comprises a metallic material.5. The memory element according to claim 1 , wherein the non magnetic spacer is positioned between the first ferromagnetic free layer and the second ferromagnetic free layer; and the insulator layer is positioned between the non magnetic spacer layer and the second ferromagnetic free layer.6. The memory element according to claim 5 , wherein the via has material from the non magnetic spacer layer therein.7. The memory element according to claim 5 , wherein the via has material from the second ferromagnetic free layer therein.8. The memory element according to ...

MRAM DIODE ARRAY AND ACCESS METHOD

A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode. 1. A memory unit comprising:a magnetic tunnel junction data cell electrically coupled to a bit line and a source line, the magnetic tunnel junction data cell configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell;a first diode electrically between the magnetic tunnel junction data cell and the source line; anda second diode electrically between the magnetic tunnel junction data cell and the source line, the first diode and second diode in parallel electrical connection, and having opposing forward bias directionswherein the source line and bit line is configured to be precharged to a specified precharge voltage level, the precharge voltage being less than a threshold voltage of the first diode and second diode.2. A memory unit according to claim 1 , wherein the specified precharge voltage level is in a range from 40 to 60% of a write voltage.3. A memory unit according to claim 1 , wherein the memory unit does not include a transistor electrically between the bit line and the source line.4. A memory unit according to claim 1 , wherein the first diode provides current to ...

PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING

Programmable metallization memory cells include an electrochemically active electrode, an inert electrode and an internal layer between the electrochemically active electrode and the inert electrode. The internal layer having a fast ion conductor material and an apertured layer having a plurality of apertures defined by an electrically insulating material. Each aperture defines at least a portion of a column of fast ion conductor material having superionic clusters. 1. A programmable metallization memory cell comprising:a first electrode in electrical contact with a bit line, the first electrode comprising an electrochemically active metal layer;a second electrode in electrical contact with a word line, the bit line being orthogonal to the word line; andan internal layer between the electrochemically active metal layer and the second electrode, the internal layer comprising a fast ion conductor material and an apertured layer comprising a plurality of apertures defined by an electrically insulating material, each aperture defines at least a portion of a column of fast ion conductor material having superionic clusters.2. The memory cell of wherein the electrically insulating material comprises a dielectric material.3. The memory cell of wherein the fast ion conductor material comprises a chalcogenide material.4. The memory cell of wherein the fast ion conductor material comprises a germanium selenide material.5. The memory cell of wherein the apertured layer is in contact with the electrochemically active metal layer.6. The memory cell of wherein the apertured layer is in contact with the inert electrode.7. The memory cell of wherein the apertured layer is in contact with the electrochemically active metal layer and the inert electrode.8. The memory cell of wherein the plurality of apertures each have an aperture diameter of about 20 to 50 nm.9. A programmable metallization memory cell comprising:an electrochemically active electrode;an inert electrode; andan ...

MEMORY WITH SEPARATE READ AND WRITE PATHS

A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell. 1. A memory unit comprising:a giant magnetoresistance cell electrically coupled between a write bit line and a write source line, a write current passing through the giant magnetoresistance cell switches the giant magnetoresistance cell between a high resistance state and a low resistance state; anda magnetic tunnel junction data cell electrically coupled between a read bit line and a read source line, the magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell;wherein the read source line and the write source line is a common source line and the read bit line is separately addressable from the write bit line and a write transistor is electrically coupled between the source line and the giant magnetoresistance cell, and a read transistor is electrically coupled between the source line and the magnetic tunnel junction data cell.2. A memory unit according to claim 1 , wherein the magnetic tunnel junction data cell comprises a free magnetic layer separated from a ...

Magnetic sensing device with reduced shield-to-shield spacing

A magnetic sensor assembly includes first and second shields each comprised of a magnetic material. The first and second shields define a physical shield-to-shield spacing. A sensor stack is disposed between the first and second shields and includes a seed layer adjacent the first shield, a cap :layer adjacent the second shield, and a magnetic sensor between the seed layer and the cap layer. At least a portion of the seed layer and/or the cap layer comprises a magnetic material to provide an effective shield-to-shield spacing of the magnetic sensor assembly that is less than the physical shield-to-shield spacing.

Single sensor element that is naturally differentiated

A differentiated sensor includes a pair of magnetic layers having magnetization directions that are substantially antiparallel in a quiescent state. At least one of the magnetic layers is a free layer. A spacer layer is disposed between the pair of magnetic layers.

Mram cells including coupled free ferromagnetic layers for stabilization

A free ferromagnetic data storage layer of an MRAM cell is coupled to a free ferromagnetic stabilization layer, which stabilization layer is directly electrically coupled to a contact electrode, on one side, and is separated from the free ferromagnetic data storage layer, on an opposite side, by a spacer layer. The spacer layer provides for the coupling between the two free layers, which coupling is one of: a ferromagnetic coupling and an antiferromagnetic coupling.

Spin-torque memory with unidirectional write scheme

Spin torque magnetic memory elements that have a pinned layer, two free layers, and a current-blocking insulating layer proximate to at least one of the free layers. The resistive state (e.g., low resistance or high resistance) of the memory elements is altered by passing electric current through the element in one direction. In other words, to change from a low resistance to a high resistance, the direction of electric current is the same as to change from a high resistance to a low resistance. The elements have a unidirectional write scheme.

Memory with separate read and write paths

A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.

Non-volatile multi-bit memory with programmable capacitance

Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region. A first insulating layer is over the substrate. A first solid electrolyte cell is over the insulating layer and has a capacitance that is controllable between at least two states and is proximate the source region. A second solid electrolyte cell is over the insulating layer and has a capacitance or resistance that is controllable between at least two states and is proximate the drain region. An insulating element isolates the first solid electrolyte cell from the second solid electrolyte cell. A first anode is electrically coupled to the first solid electrolyte cell. The first solid electrolyte cell is between the anode and the insulating layer. A second anode is electrically coupled to the second solid electrolyte cell. The second solid electrolyte cell is between the anode and the insulating layer. A gate contact layer is over the substrate and between the source region and drain region and in electrical connection with the first anode and the second anode. The gate contact layer is electrically coupled to a voltage source.

Transducing head with reduced side writing

A transducing head has a main pole and at least one magnetic element (such as a return pole or a shield) which provides a potential return path for a magnetic field produced by the main pole. The magnetic element is spaced from the main pole. The magnetic element is formed at least in part of a magnetic material having a material property that reduces side writing at the magnetic element.

MRAM Cells Including Coupled Free Ferromagnetic Layers for Stabilization

A free ferromagnetic data storage layer of an MRAM cell is coupled to a free ferromagnetic stabilization layer, which stabilization layer is directly electrically coupled to a contact electrode, on one side, and is separated from the free ferromagnetic data storage layer, on an opposite side, by a spacer layer. The spacer layer provides for the coupling between the two free layers, which coupling is one of: a ferromagnetic coupling and an antiferromagnetic coupling.

Transducing head including a magnetic element exhibiting varying permeability

A transducing head has a main pole and at least one magnetic element (such as a return pole or a shield) which provides a potential return path for a magnetic field produced by the main pole. The magnetic element is spaced from the main pole. The magnetic element has a first edge closest to the main pole and a second edge furthest from the main pole. Permeability of the magnetic element increases from the first edge to the second edge.

Nonvolatile programmable logic gates and adders

Spin torque magnetic logic device having at least one input element and an output element. Current is applied through the input element(s), and the resulting resistance or voltage across the output element is measured. The input element(s) include a free layer and the output element includes a free layer that is electrically connected to the free layer of the input element. The free layers of the input element and the output element may be electrically connected via magnetostatic coupling, or may be physically coupled. In some embodiments, the output element may have more than one free layer.

Programmable metallization memory cells via selective channel forming

Methods for making a programmable metallization memory cell are disclosed.

Magnetoresistive device having specular sidewall layers

A multilayered magnetoresistive device includes a specular layer positioned on at least one sidewall and a copper layer positioned between the specular layer and the sidewall.

Write verify method for resistive random access memory

Write verify methods for resistance random access memory (RRAM) are provided. The methods include applying a reset operation voltage pulse across a RRAM cell to change a resistance of the RRAM cell from a low resistance state to a high resistance state. Then the method includes applying a forward resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance value less than a selected lower resistance limit value. This step is repeated until the high resistance state resistance value is greater than the lower resistance limit value. The method also includes applying a reverse resetting voltage pulse across the RRAM cell if the RRAM cell has a high resistance state resistance values is greater than a selected upper resistance limit value. The reverse resetting voltage pulse has a second polarity being opposite the first polarity. This step is repeated until all the high resistance state resistance value is less than the upper resistance limit value.

St-ram magnetic element configurations to reduce switching current

In order to increase an efficiency of spin transfer and thereby reduce the required switching current, a current perpendicular to plane (CPP) magnetic element for a memory device includes either one or both of a free magnetic layer, which has an electronically reflective surface, and a permanent magnet layer, which has perpendicular anisotropy to bias the free magnetic layer.

Programmable metallization memory cells via selective channel forming

Methods for making a programmable metallization memory cell are disclosed.

Short bridge phase change memory cells

Random access memory cells having a short phase change bridge structure and methods of making the bridge structure via shadow deposition. The short bridge structure reduces the heating efficiency needed to switch the logic state of the memory cell. In one particular embodiment, the memory cell has a first electrode and a second electrode with a gap therebetween. The first electrode has an end at least partially non-orthogonal to the substrate and the second electrode has an end at least partially non-orthogonal to the substrate. A phase change material bridge extends over at least a portion of the first electrode, over at least a portion of the second electrode, and within the gap. An insulative material encompasses at least a portion of the phase change material bridge.

Magnetic oscillator with multiple coherent phase output

Apparatus to generate signals with multiple phases are described. The apparatus includes a fixed multilayer stack providing a varying magnetic field and at least two sensors adjacent the fixed multilayer stack to sense the varying magnetic field and generate at least two output signals. The frequency of the output signals can be tuned by an input current.

Memory with separate read and write paths

A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.

Non-volatile memory cell with enhanced filament formation characteristics

Method and apparatus for constructing a non-volatile memory cell, such as a modified RRAM cell. In some embodiments, a memory cell comprises a resistive storage layer disposed between a first electrode layer and a second electrode layer. Further in some embodiments, the storage layer has a localized region of decreased thickness to facilitate formation of a conductive filament through the storage layer from the first electrode to the second electrode.

Magnetic recording head with clad coil

Non-volatile memory cell with enhanced filament formation characteristics

Method and apparatus for constructing a non-volatile memory cell, such as a modified RRAM cell. In some embodiments, a memory cell comprises a resistive storage layer disposed between a first electrode layer and a second electrode layer. Further in some embodiments, the storage layer has a localized region of decreased thickness to facilitate formation of a conductive filament through the storage layer from the first electrode to the second electrode.

Short bridge phase change memory cells and method of making

Random access memory cells having a short phase change bridge structure and methods of making the bridge structure via shadow deposition. The short bridge structure reduces the heating efficiency needed to switch the logic state of the memory cell. In one particular embodiment, the memory cell has a first electrode and a second electrode with a gap therebetween. The first electrode has an end at least partially non-orthogonal to the substrate and the second electrode has an end at least partially non-orthogonal to the substrate. A phase change material bridge extends over at least a portion of the first electrode, over at least a portion of the second electrode, and within the gap. An insulative material encompasses at least a portion of the phase change material bridge.

Magnetic floating gate memory

An apparatus includes at least one memory device including a floating gate element and a magnetic field generator that operably applies a magnetic field to the memory device. The magnetic field directs electrons in the memory device into the floating gate element.

Band engineered high-k tunnel oxides for non-volatile memory

A non-volatile memory cell that has a charge source region, a charge storage region, and a crested tunnel barrier layer that has a potential energy profile which peaks between the charge source region and the charge storage region. The tunnel barrier layer has multiple high-K dielectric materials, either as individual layers or as compositionally graded materials.

Magnetic sensing device with reduced shield-to-shield spacing

A magnetic sensor assembly includes first and second shields each comprised of a magnetic material. The first and second shields define a physical shield-to-shield spacing. A sensor stack is disposed between the first and second shields and includes a seed layer adjacent the first shield, a cap layer adjacent the second shield, and a magnetic sensor between the seed layer and the cap layer. At least a portion of the seed layer and/or the cap layer comprises a magnetic material to provide an effective shield-to-shield spacing of the magnetic sensor assembly that is less than the physical shield-to-shield spacing.