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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 3021. Отображено 100.
04-04-2013 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

Номер: US20130082231A1
Автор: Hada Hiromitsu, Miyamura Makoto, Tada Munehiro
Принадлежит: NEC Corporation

A semiconductor device includes multilayer interconnects and two variable resistance elements () that are provided among the multilayer interconnects and that include first electrodes (), second electrodes (), and variable resistance element films () that are each interposed between first electrodes () and respective second electrodes (). Either the first electrodes () or the second electrodes () of the two variable resistance elements () are unified. 1. A semiconductor device comprising:multilayer interconnects; andtwo variable resistance elements that are provided among said multilayer interconnects and that include first electrodes, second electrodes, and a variable resistance element film that is interposed between these electrodes,wherein the electrode types of said first electrodes or the electrode types of said second electrodes of said two variable resistance elements are unified.2. The semiconductor device according to claim 1 , wherein said two variable resistance elements comprise bipolar variable resistance elements and are connected in a series.3. The semiconductor device according to claim 1 , wherein:said two variable resistance elements comprise an electrical element that is provided in a signal path;the same-polarity electrodes of said two variable resistance elements are connected together; andin the two unconnected electrodes of said two variable resistance elements, one electrode comprises an input terminal and the other electrode comprises an output terminal.4. The semiconductor device according to claim 3 , further comprising a crossbar switch that takes said electrical element as a switch element.5. The semiconductor device according to claim 1 , wherein:said two variable resistance elements comprise bipolar variable resistance elements;said first electrodes contain a material that comprises a supply source of metal ions;said second electrodes are made up of a material that is less prone to ionization than said first electrodes; andsaid ...

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Номер записи: 1
09-05-2013 дата публикации

NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY DEVICE, AND MANUFACTURING METHOD FOR THE SAME

Номер: US20130112935A1
Автор: Hayakawa Yukio, Himeno Atsushi, Mikawa Takumi, Sorada Haruyuki
Принадлежит:

A nonvolatile memory element according to the present invention includes a first metal line; a plug formed on the first metal line and connected to the first metal line; a stacked structure including a first electrode, a second electrode, and a variable resistance layer, the stacked structure being formed on a plug which is connected to the first electrode; a second metal line formed on the stacked structure and directly connected to the second electrode; and a side wall protective layer which covers the side wall of the stacked structure and has an insulating property and an oxygen barrier property, wherein part of a lower surface of the second metal line is located under an upper surface of the stacked structure. 1. A nonvolatile memory element which includes a first electrode , a second electrode , and a variable resistance layer (i) which is interposed between the first electrode and the second electrode , and (ii) comprises an oxygen-deficient metal oxide , and (iii) which reversibly changes between a high resistance state and a low resistance state in which a resistance value lower than a resistance value in the high resistance state , according to an electrical signal applied between the first electrode and the second electrode ,the nonvolatile memory element comprising:a first metal line;a stacked structure which is formed above the first metal line, and includes the first electrode, the second electrode, and the variable resistance layer, one of the first electrode and the second electrode being electrically connected to the first metal line;a second metal line which is formed on the stacked structure, and is directly connected, without use of a plug, to the other of the first electrode and the second electrode; anda side wall protective layer which covers a side wall of the stacked structure without covering an upper surface of the stacked structure, the side wall protective layer having an insulating property and an oxygen barrier property,wherein part of ...

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Номер записи: 2
09-05-2013 дата публикации

RESISTANCE CHANGE ELEMENT AND MANUFACTURING METHOD THEREFOR

Номер: US20130112936A1
Автор: Kawashima Yoshio, Mitani Satoru, TAKAGI Takeshi, Takahashi Ichirou, WEI Zhiqiang
Принадлежит: Panasonic Corporation

A variable resistance element including: a first electrode; a second electrode; and a variable resistance layer having a resistance value which reversibly changes according to electrical signals applied, wherein the variable resistance layer includes a first variable resistance layer comprising a first oxygen-deficient transition metal oxide, and a second variable resistance layer comprising a second transition metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first transition metal oxide layer, the second electrode has a single needle-shaped part at the interface with the second variable resistance layer, and the second variable resistance layer is interposed between the first variable resistance layer and the second electrode, is in contact with the first variable resistance layer and the second electrode, and covers the needle-shaped part. 1. A variable resistance element comprising: a first electrode; a second electrode; and a variable resistance layer interposed between the first electrode and the second electrode and is in contact with the first electrode and the second electrode , the variable resistance layer having a resistance value which reversibly changes according to electrical signals applied between the first electrode and the second electrode ,wherein the variable resistance layer is formed by stacking a first variable resistance layer comprising a first oxygen-deficient transition metal oxide, and a second variable resistance layer comprising a second transition metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first transition metal oxide,the second electrode has a single needle-shaped part protruding toward the second variable resistance layer,the second variable resistance layer is interposed between the first variable resistance layer and the second electrode, is in contact with the first variable resistance layer and the second electrode, and covers ...

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Номер записи: 3
16-05-2013 дата публикации

RESISTIVE RANDOM ACCESS MEMORY CELL AND MEMORY

Номер: US20130119341A1
Автор: Liu Ming, Liu Qi, Long Shibing, Lv Hangbing
Принадлежит: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

A Resistive Random Access Memory (RRAM) cell and a memory are disclosed. In one embodiment, the RRAM cell comprises a two-state resistor and a resistive switching memory cell connected in series. The two-state resistor can supply relatively large currents under both positive and negative voltage polarities. As a result, it is possible to reduce leakage paths in a crossbar array of memory cells, and thus to suppress reading crosstalk. 1. A Resistive Random Access Memory (RRAM) cell comprising a two-state resistor and a resistive switching memory cell connected in series ,wherein the two-state resistor comprises a lower conductive electrode, a two-state resistor functionality layer, and a middle conductive electrode, andwherein the two-state resistor functionality layer comprises an n-p-n junction or a p-n-p junction consisted of any one or more of doped Si, Ge, GaAs, InP, and SiGe.2. The RRAM cell according to claim 1 , wherein in the two-state resistor functionality layer claim 1 , the n-p-n junction or the p-n-p junction has a doping concentration of about 1×10cm-about 1×10cm.3. The RRAM cell according to claim 2 , wherein the n-p-n junction comprises an n-p-n Si nanowire.4. The RRAM cell according to claim 1 , wherein the two-state resistor functionality layer has a thickness of about 10 nm-about 500 nm claim 1 , is doped by means of thermal diffusion or ion implantation claim 1 , and is deposited by means of Chemical Vapor Deposition claim 1 , Atom Layer Deposition claim 1 , or Molecule Beam Epitaxy.5. The RRAM cell according to claim 1 , wherein{'sub': '1', 'the two-state resistor comes into a low-resistance state from a high-resistance state when a forward sweeping voltage reaches a forward ON voltage V, and keeps this low-resistance state in a forward direction,'}{'sub': 1', '2', '1', '2, 'when the sweeping voltage is swept back from V, the two-state resistor keeps the low-resistance state until the sweeping voltage becomes lower than V, at which point the two ...

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Номер записи: 4
16-05-2013 дата публикации

MEMORY DEVICE, SEMICONDUCTOR STORAGE DEVICE, METHOD FOR MANUFACTURING MEMORY DEVICE, AND READING METHOD FOR SEMICONDUCTOR STORAGE DEVICE

Номер: US20130121063A1
Автор: Mikawa Takumi, TSUJI Kiyotaka
Принадлежит:

A memory device that can prevent degradation in characteristics of a diode and the destruction due to the miniaturization includes: a substrate; first electrodes, a second electrode, and a third electrode that are stacked above the substrate; a variable resistance layer between the first and second electrodes; and a non-conductive layer between the second and third electrodes. The variable resistance layer includes a high-concentration variable resistance layer closer to the first electrodes, and a low-concentration variable resistance layer closer to the second electrode and having an oxygen concentration lower than that of the high-concentration variable resistance layer. The second and third electrodes and the non-conductive layer comprise the diode, and the first and second electrodes and the variable resistance layer comprise variable resistance elements, a total number of which is equal to that of the first electrodes. 1. A memory device , comprising:a substrate;a plurality of first electrodes, a second electrode, and a third electrode that are stacked above the substrate;a variable resistance layer formed in an island shape between the first electrodes and the second electrode; anda non-conductive layer formed between the second electrode and the third electrode,wherein the variable resistance layer includes a high-concentration variable resistance layer located closer to the first electrodes, and a low-concentration variable resistance layer located closer to the second electrode, the low-concentration variable resistance layer having an oxygen concentration lower than an oxygen concentration of the high-concentration variable resistance layer,the second electrode, the non-conductive layer, and the third electrode comprise a diode,the second electrode, the third electrode, the variable resistance layer, and the non-conductive layer are formed across the first electrodes,the first electrodes, the variable resistance layer, and the second electrode comprise a ...

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Номер записи: 5
23-05-2013 дата публикации

RESISTIVE RADOM ACCESS MEMORY DEVICE, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR OPERATING THE SAME

Номер: US20130128653A1
Автор: Chen Yuansha, Gao Bin, KANG Jinfeng, Liu Lifeng, LIU Xiaoyan, Sun Bing
Принадлежит: PEKING UNIVERSITY

A resistive random access memory device, a method for manufacturing the resistive random access memory device, and a method for operating the resistive random access memory device are disclosed. The resistive random access memory device includes a resistive switching memory element including two electrodes and a layer of variable-resistance material between the two electrodes, wherein the layer of variable-resistance material exhibits bipolar resistive switching behavior; and a Schottky diode including a metal layer and a p-doped semiconductor layer which contact each other, wherein the metal layer of the Schottky diode is coupled to one of the two electrodes of the resistive switching memory element. The present disclosure provides the resistive random access memory device operating in bipolar resistive switching scheme. 1. A resistive random access memory device , comprising:a resistive switching memory element including two electrodes and a layer of variable-resistance material between the two electrodes, wherein the layer of variable-resistance material exhibits bipolar resistive switching behavior; anda Schottky diode including a metal layer and a p-doped semiconductor layer which contact each other,wherein the metal layer of the Schottky diode is coupled to one of the two electrodes of the resistive switching memory element.2. The resistive random access memory device according to claim 1 , wherein the layer of variable-resistance material is made of at least one selected from a group consisting of NiO claim 1 , TiO claim 1 , HfO claim 1 , ZrOand ZnO.3. The resistive random access memory device according to claim 1 , wherein the metal layer of the Schottky diode has a thickness of about 10-100 nm.4. The resistive random access memory device according to claim 1 , wherein the p-doped semiconductor layer of the Schottky diode is a p-doped polysilicon layer.5. The resistive random access memory device according to claim 4 , wherein the p-doped polysilicon layer ...

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Номер записи: 6
30-05-2013 дата публикации

VARIABLE-RESISTANCE MATERIAL MEMORIES AND METHODS

Номер: US20130134378A1
Автор: Liu Jun
Принадлежит: MICRON TECHNOLOGY, INC.

Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes include the formation of the bottom spacer electrodes as well as the variable-resistance material memory spacer cells. Devices include the variable-resistance memory cells. 1. An apparatus comprising:a first electrode disposed upon a semiconductive substrate;a variable resistance material coupled to the first electrode, wherein a first minor-axis surface of the first electrode forms an interface with the variable resistance material; anda second electrode coupled to the variable resistance material.2. The apparatus of claim 1 , wherein the variable resistance material is selected from a group consisting of an alloy claim 1 , a quasi-metal composition claim 1 , a metal oxide claim 1 , and a chalcogenide.3. The apparatus of claim 1 , wherein a second minor-axis surface of the first electrode forms an interface with a contact pad.4. The apparatus of claim 3 , wherein the contact pad is coupled to a buried digit line.5. The apparatus of claim 1 , wherein the second electrode is common to a number of first electrodes.6. An apparatus comprising:a first electrode disposed upon a semiconductive substrate;a variable resistance material coupled to the first electrode, wherein a first minor-axis surface of the variable resistance material forms an interface with the first electrode; anda second electrode coupled to the variable resistance material.7. The apparatus of claim 6 , wherein a second minor-axis surface of the variable resistance material forms an interface with the second electrode.8. The apparatus of claim 7 , wherein a third minor-axis surface of the variable resistance material forms an interface with a contact pad.9. The apparatus of claim 6 , wherein the second electrode is common to a number of first electrodes.10. An apparatus comprising:a first electrode disposed ...

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Номер записи: 7
30-05-2013 дата публикации

RESISTIVE MEMORY USING SIGE MATERIAL

Номер: US20130134379A1
Автор: Lu Wei
Принадлежит: Crossbar, Inc.

A resistive memory device includes a first electrode; a second electrode having a polycrystalline semiconductor layer that includes silicon; a non-crystalline silicon structure provided between the first electrode and the second electrode. The first electrode, second electrode and non-crystalline silicon structure define a two-terminal resistive memory cell. 1. A memory device having a crossbar array , the memory device comprising:a first array of first electrodes extending along a first direction;a second array of second electrodes extending along a second direction, each second electrode having a polycrystalline semiconductor layer including silicon;a non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array,wherein each intersection of the first array and the second array defines a two-terminal resistive memory cell.2. The memory device of claim 1 , wherein the non-crystalline silicon structure includes amorphous silicon claim 1 , and the polycrystalline semiconductor layer includes a polycrystalline silicon-germanium.3. The memory device of claim 1 , wherein the first array of the first electrodes are provided over the non-crystalline silicon structure claim 1 , and the second array of the second electrodes are provided below the non-crystalline silicon structure claim 1 , andwherein the first array of the first electrodes include silver, the non-crystalline silicon structure includes amorphous silicon, and the second array of the second electrodes includes polycrystalline silicon-germanium.4. The memory device of claim 3 , wherein the polycrystalline silicon-germanium has comprises least 60% Ge.5. The memory device of claim 4 , wherein the polycrystalline silicon-germanium has comprises least 70% Ge claim 4 , andwherein the polycrystalline silicon-germanium is formed by using a deposition temperature of no more than 450° C.6. The memory device of claim 4 , ...

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Номер записи: 8
06-06-2013 дата публикации

RESISTIVE-SWITCHING MEMORY ELEMENT

Номер: US20130140511A1
Автор: Chiang Tony, Lang Chi-I, Phatak Prashant
Принадлежит: INTERMOLECULAR, INC.

A resistive-switching memory element is described. The memory element includes a first electrode, a porous layer over the first electrode including a point defect embedded in a plurality of pores of the porous layer, and a second electrode over the porous layer, wherein the nonvolatile memory element is configured to switch between a high resistive state and a low resistive state. 1. A resistive-switching nonvolatile memory element comprising:a first electrode;a resistive-switching porous layer over the first electrode including a plurality of point defects embedded in a plurality of pores of the porous layer; anda second electrode over the porous layer;wherein the nonvolatile memory element is configured to switch between a high resistive state and a low resistive state.2. The nonvolatile memory element of claim 1 , wherein the porous layer includes at least one of carbon and silicon.3. The nonvolatile memory element of claim 1 , wherein the plurality of point defects includes a material selected from the group consisting of a transition-metal claim 1 , nickel claim 1 , titanium claim 1 , zirconium claim 1 , hafnium claim 1 , silicon claim 1 , and germanium.4. The nonvolatile memory element of claim 1 , wherein the plurality of point defects comprises less than ten atomic percent of the porous layer.5. The nonvolatile memory element of claim 1 , wherein the plurality of point defects comprises less than one atomic percent of the porous layer.6. The nonvolatile memory element of claim 1 , wherein the second electrode includes a material selected from the group consisting of a titanium-containing material claim 1 , a tungsten-containing material claim 1 , and a tantalum-containing material.7. The nonvolatile memory element of claim 1 , further comprising an adhesion layer between the porous layer and the second electrode claim 1 , the adhesion layer having a first density greater than a second density of the porous layer.8. The nonvolatile memory element of claim 1 , ...

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Номер записи: 9
06-06-2013 дата публикации

NONVOLATILE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME

Номер: US20130140515A1
Автор: Kawashima Yoshio, Mikawa Takumi, Takahashi Ichirou
Принадлежит:

A method of manufacturing a nonvolatile memory element, the method including: forming a first lower electrode layer, a current steering layer, and a first upper electrode layer; forming a second lower electrode layer, a variable resistance layer, and a second upper electrode layer on the first upper electrode layer; patterning the second upper electrode layer, the variable resistance layer, and the lower electrode layer; patterning the first upper electrode layer, the current steering layer, and first lower electrode layer to form a current steering element, using the second lower electrode layer as a mask by use of etching which is performed on the second lower electrode layer at an etching rate lower than at least etching rates at which the second upper electrode layer and the variable resistance layer are etched; and forming a variable resistance element which has an area smaller than the area of the current steering element. 1. A method of manufacturing a nonvolatile memory element which includes a current steering element and a variable resistance element , the method comprising:forming a first lower electrode layer on a substrate;forming a current steering layer on the first lower electrode layer;forming a first upper electrode layer on the current steering layer;forming a second lower electrode layer on the first upper electrode layer;forming a variable resistance layer comprising a metal oxide on the second lower electrode layer;forming a second upper electrode layer on the variable resistance layer;forming a mask on the second upper electrode layer, and patterning the second upper electrode layer, the variable resistance layer, and the second lower electrode layer; andforming the current steering element including the first lower electrode layer, the current steering layer, and the first upper electrode layer by patterning layers lower than the second lower electrode layer by use of etching which is performed on the second lower electrode layer at an ...

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Номер записи: 10
13-06-2013 дата публикации

CIRCUIT AND SYSTEM OF USING FINFET FOR BUILDING PROGRAMMABLE RESISTIVE DEVICES

Номер: US20130148409A1
Автор: Chung Shine C.
Принадлежит:

Junction diodes or MOS devices fabricated in standard FinFET technologies can be used as program selectors or One-Time Programmable (OTP) element in a programmable resistive device, such as interconnect fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCRAM, CBRAM, or RRAM. The MOS or diode can be built on at least one fin structure or at least one active region that has at least one first active region and a second active region. The first and the second active regions can be isolated by a dummy MOS gate or silicide block layer (SBL) to construct a diode. 1. A programmable resistive memory , comprising: a resistive element;', 'at least one fin structure coupled to the resistive element, the at least one fin structure being a semiconductor structure and including at least a first active region and a second active region, the first active region having a first type of dopant, and the second active region having the first type of dopant or the second type of dopant; and', 'a gate provided over at least a portion of the at least one fin structure, the gate being provided between or adjacent both the first and second active regions,, 'a plurality of programmable resistive cells, at least one of the programmable resistive cells comprisingwherein at least a portion of the first and second active regions residing in a common well or on an isolated substrate.2. A programmable resistive memory as recited in claim 1 , wherein an insulator material is provided between the gate and the at least a portion of the at least one fin structure.3. A programmable resistive memory as recited in claim 1 , wherein the resistive element is coupled to a first supply voltage line claim 1 , and wherein the first active region is coupled to the resistive element claim 1 , the second active region is coupled to a second supply voltage line claim 1 , and the MOS gate is coupled to a third supply voltage line.4. A programmable resistive memory as recited in claim 3 ...

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Номер записи: 11
20-06-2013 дата публикации

HORIZONTALLY ORIENTED AND VERTICALLY STACKED MEMORY CELLS

Номер: US20130153853A1
Автор: Marsh Eugene P., Quick Timothy A.
Принадлежит: MICRON TECHNOLOGY, INC.

Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material. 1. A memory device , comprising: a memory cell material;', 'a first electrode adjacent a first side of the memory cell material; and', 'a second electrode adjacent a second side of the memory cell material., 'at least two vertically stacked memory cells, wherein the memory cells include2. The memory device of claim 1 , wherein the first side is opposite the second side.3. The memory device of claim 1 , wherein the memory cells include an insulator material adjacent a top and a bottom of the memory cell material.4. The memory device of claim 3 , wherein the insulator material is a nitride dielectric material.5. The memory device of claim 1 , wherein the memory cells are self-aligned memory cells.6. The memory device of claim 1 , wherein the first electrode includes an access device contact.7. The memory device of claim 1 , wherein the second electrode includes a metal material.8. A memory device claim 1 , comprising: a memory cell material;', 'an access device contact adjacent a first side of the memory cell material; and', 'a metal material adjacent a second side of the memory cell material., 'a first vertical stack of memory cells and a second vertical stack of memory cells, wherein the memory cells in the first and second vertical stacks include9. The memory device of claim 8 ...

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Номер записи: 12
04-07-2013 дата публикации

RESISTIVE RANDOM ACCESS MEMORY DEVICE

Номер: US20130168634A1
Автор: LEE Jae-Yeon
Принадлежит: SK HYNIX INC.

A resistive memory device includes a lower electrode disposed on a substrate, first and second resistance layers respectively disposed on opposite sides of the lower electrode and exhibiting resistance variation at different voltages, respectively, and an upper electrode disposed on and the first and second resistance layers. 1. A resistive memory device comprising:a lower electrode disposed on a substrate;first and second resistance layers respectively disposed on opposite sides of the lower electrode and exhibiting resistance variation at different voltages, respectively; andan upper electrode disposed on the first and second resistance layers.2. The resistive memory device of claim 1 , wherein the first and second resistance layers are disposed on opposite sides of the lower electrode that include upper opposite edges of the lower electrode.3. The resistive memory device of claim 1 , wherein the first and second resistance layers are formed of different materials.4. The resistive memory device of claim 1 , wherein the first and second resistance layers are formed of the same kind of material with respectively different thicknesses or respectively different sizes of contact areas with the lower electrode or the upper electrode.5. The resistive memory device of claim 1 , wherein the first and second resistance layers are composed of at least one selected from a metal oxide layer claim 1 , a PCMO (PrCaMnO claim 1 , 0 Подробнее

Номер записи: 13
11-07-2013 дата публикации

Integrated Circuitry, Methods of Forming Memory Cells, and Methods of Patterning Platinum-Containing Material

Номер: US20130175495A1
Автор: Andrey V. Zagrebelny, Chet E. Carter
Принадлежит: Micron Technology Inc

Some embodiments include methods of patterning platinum-containing material. An opening may be formed to extend into an oxide. Platinum-containing material may be formed over and directly against an upper surface of the oxide, and within the opening. The platinum-containing material within the opening may be a plug having a lateral periphery. The lateral periphery of the plug may be directly against the oxide. The platinum-containing material may be subjected to polishing to remove the platinum-containing material from over the upper surface of the oxide. The polishing may delaminate the platinum-containing material from the oxide, and may remove the platinum-containing material from over the oxide with an effective selectivity for the platinum-containing material relative to the oxide of at least about 5:1. Some embodiments include methods of forming memory cells. Some embodiments include integrated circuitry having platinum-containing material within an opening in an oxide and directly against the oxide.

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Номер записи: 14
22-08-2013 дата публикации

Method for Forming Metal Oxides and Silicides in a Memory Device

Номер: US20130214238A1
Автор: Chiang Tony P., Minvielle Tim, Pramanik Dipankar, YAMAGUCHI Takeshi
Принадлежит:

Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300° C. to about 600° C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600° C. to about 850° C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process. 1. A method for fabricating a resistive switching memory device , the method comprising: 'wherein the lower electrode comprises silicon;', 'providing a substrate comprising a lower electrode,'} the metallic layer comprises one of hafnium or zirconium,', 'the metallic layer having a lower portion facing the lower electrode and an upper portion facing away from the lower electrode;, 'forming a metallic layer on the lower electrode,'} 'wherein forming the metal oxide layer comprises heating the metallic layer to a temperature of less than 600° C. and exposing the metallic layer to an activated oxygen source; and', 'forming a metal oxide layer from the upper portion of the metallic layer,'} 'wherein forming the metal silicide layer comprises heating the metallic layer and the lower electrode to a temperature of greater than 600° C. and transferring a portion of the silicon from the lower electrode and into the lower portion of the metallic layer.', 'forming a metal silicide layer from the lower portion of the metallic layer,'}2. The method of claim 1 , ...

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Номер записи: 15
22-08-2013 дата публикации

METHOD FOR MANUFACTORING A CARBON-BASED MEMORY ELEMENT AND MEMORY ELEMENT

Номер: US20130214239A1
Автор: Caimi Daniele, Eleftheriou Evangelos S., Pozidis Charalampos, Rossel Christophe P., Sebastian Abu
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method for manufacturing a resistive memory element includes providing a storage layer comprising a resistance changeable material, said resistance changeable material comprising carbon; providing contact layers for contacting the storage layer, wherein the storage layer is disposed between a bottom contact layer and a top contact layer; and doping the resistance changeable material with a dopant material. 1. A method for manufacturing a resistive memory element comprising:providing a storage layer comprising a resistance changeable material, said resistance changeable material comprising carbon;providing contact layers for contacting the storage layer, wherein the storage layer is disposed between a bottom contact layer and a top contact layer; anddoping the resistance changeable material with a dopant material.2. The method of claim 1 , wherein a resistance change of the storage layer is induced electro-thermally by Joule heating for programming the resistive memory element.3. The method of claim 1 , wherein the dopant material comprises a transition metal.4. The method of claim 1 , wherein the resistance changeable material is amorphous carbon.5. The method of claim 4 , wherein the dopant material is hydrogen or nitrogen to perform one or more of: rearranging an atomic order of the resistance changeable material claim 4 , and inducing the creation of additional sp-hybridized carbon in the resistance changeable material.6. The method of claim 4 , wherein the resistance changeable material comprises more sp-hybridized carbon than sp-hybridized carbon.7. The method of claim 1 , further comprising:annealing the resistance changeable material at a predetermined temperature over a predetermined annealing time for rearranging an atomic order of the resistance changeable material.8. A resistive memory element comprising a bottom contact layer claim 1 , a top contact layer and a storage layer disposed between the bottom contact layer and the top contact layer claim 1 , ...

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Номер записи: 16
22-08-2013 дата публикации

Memory Device with a Textured Lowered Electrode

Номер: US20130214240A1
Автор: Pramanik Dipankar
Принадлежит: Intermolecular Inc.

Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack. 1. A method for forming a memory device , the method comprising:providing a substrate comprising a lower electrode;forming a silicon oxide layer over the lower electrode;forming metallic particles over the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer;forming troughs in the lower electrode through the silicon oxide layer between the metallic particles,removing the metallic particles and the silicon oxide layer to reveal peaks between the troughs; andforming a metal oxide film stack over the lower electrode,wherein the metal oxide film stack comprises a resistive switching layer.2. The method of claim 1 , wherein the resistive switching layer comprises hafnium oxide.3. The method of claim 2 , wherein forming the metal oxide film stack comprises forming the resistive switching layer using an atomic layer deposition (ALD) technique.4. The method of claim 1 , wherein the metal oxide film stack comprises one of aluminum oxide claim 1 , titanium oxide claim 1 , hafnium ...

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Номер записи: 17
22-08-2013 дата публикации

Resistive-Switching Nonvolatile Memory Elements

Номер: US20130217200A1
Автор: Barstow Sean, Chiang Tony P., Kumar Pragati, Malhotra Sandra G.
Принадлежит: Intermolecular Inc.

Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer. 1. A method of fabricating a resistive switching nonvolatile memory element , the method comprising:forming a first conductive layer comprising a metal nitride having a most prevalent metal;forming a resistive switching layer over the first conductive layer; andforming a second conductive layer over the resistive switching layer;wherein the resistive switching layer comprises a first sub-layer and a second sub-layer;wherein the first sub-layer and the second sub-layer have different compositions; andwherein at least one of the first sub-layer and the second sub-layer comprises a non-stoichiometric metal oxide comprising the most prevalent metal.2. The method of claim 1 , wherein the first conductive layer comprises one of titanium nitride claim 1 , tungsten nitride claim 1 , niobium nitride claim 1 , titanium aluminum nitride claim 1 , tungsten aluminum nitride claim 1 , or niobium aluminum nitride.3. The method of claim 1 , wherein the forming of the first conductive layer comprises one of physical vapor deposition claim 1 , chemical vapor deposition claim 1 , ...

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Номер записи: 18
29-08-2013 дата публикации

VARIABLE RESISTIVE MEMORY DEVICE

Номер: US20130221306A1
Автор: CHO Pulunsol, Kim Yong-Kwan, LEE Ho-joong, NAM Ki-hyung
Принадлежит:

A variable resistive memory device capable of reducing contact resistance by including a contact layer having low contact resistance, the variable resistive memory device including a substrate comprising an active region; a gate line on the substrate; a first contact layer electrically connected to the active region; a memory cell contact plug electrically connected to the first contact layer; and a variable resistive memory cell electrically connected to the memory cell contact plug, wherein the first contact layer has less contact resistance with respect to the active region than the memory cell contact plug. 1. A variable resistive memory device comprising:a substrate including an active region;a gate line on the substrate;a first contact layer electrically connected to the active region;a memory cell contact plug electrically connected to the first contact layer; anda variable resistive memory cell electrically connected to the memory cell contact plug,wherein the first contact layer has less contact resistance with respect to the active region than the memory cell contact plug.2. The variable resistive memory device of claim 1 , wherein the first contact layer is buried in the substrate.3. The variable resistive memory device of claim 1 , wherein a top surface of the first contact layer is level with a top surface of the gate line.4. The variable resistive memory device of claim 1 , wherein a bottom surface of the first contact layer is level with the top surface of the gate line.5. The variable resistive memory device of claim 1 , wherein the first contact layer is between the gate lines.6. The variable resistive memory device of claim 1 , wherein the first contact layer is on an area between the gate lines.7. The variable resistive memory device of claim 1 , wherein the first contact layer includes a metal silicide material.8. The variable resistive memory device of claim 1 , further comprising:a second contact layer electrically connected to the active ...

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Номер записи: 19
05-09-2013 дата публикации

MEMORY DEVICE

Номер: US20130228736A1
Автор: Arayashiki Yusuke, Fujii Shosuke, HAIMOTO Takashi, INOKUMA Hideki, Ishikawa Takayuki, MATSUSHITA Daisuke, MIYAGAWA Hidenori, Nishi Yoshifumi, TAKASHIMA Akira
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a memory device includes a first electrode, a second electrode, and a variable resistance film. The variable resistance film is connected between the first electrode and the second electrode. The first electrode includes a metal contained in a matrix made of a conductive material. A cohesive energy of the metal is lower than a cohesive energy of the conductive material. A concentration of the metal at a central portion of the first electrode in a width direction thereof is higher than concentrations of the metal in two end portions of the first electrode in the width direction. 1. A memory device , comprising:a first electrode;a second electrode; anda variable resistance film connected between the first electrode and the second electrode,the first electrode including a metal contained in a matrix made of a conductive material, a cohesive energy of the metal being lower than a cohesive energy of the conductive material,a concentration of the metal at a central portion of the first electrode in a width direction of the first electrode being higher than concentrations of the metal in two end portions of the first electrode in the width direction.2. The device according to claim 1 , wherein a concentration profile of the metal in the width direction of the first electrode has a maximum value at the central portion in the width direction.3. The device according to claim 2 , wherein the maximum value is not less than 1×10atoms/cm.4. The device according to claim 2 , wherein distances from a position of the maximum value of the concentration profile to two ends of the first electrode in the width direction are not less than 0.2 times a width of the first electrode.5. The device according to claim 1 , wherein the first electrode is an interconnect extending in a first direction claim 1 , and the second electrode is an interconnect extending in a second direction crossing the first direction.6. The device according to claim 1 , wherein the metal ...

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Номер записи: 20
05-09-2013 дата публикации

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SAME

Номер: US20130228737A1
Автор: Fukumizu Hiroyuki, Nojiri Yasuhiro, Sekine Katsuyuki
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to an embodiment, a nonvolatile semiconductor memory device comprises memory cells in each of which are series-connected: a variable resistance element including a metal oxide; an electrode including a polysilicon layer and a SiGe layer formed between the polysilicon layer and the metal oxide; and a bipolar type current rectifying element. 1. A nonvolatile semiconductor memory device , comprising memory cells in each of which are series-connected:a variable resistance element including a metal oxide;an electrode including a polysilicon layer and a SiGe layer formed between the polysilicon layer and the metal oxide; anda bipolar type current rectifying element.2. The nonvolatile semiconductor memory device according to claim 1 , including:first lines; andsecond lines intersecting the first lines,wherein the memory cells are connected between the first lines and the second lines.3. The nonvolatile semiconductor memory device according to claim 1 , whereinthe polysilicon layer includes Ge,a concentration of Ge in the SiGe layer is two or more times higher than a concentration of Ge in the polysilicon layer.4. The nonvolatile semiconductor memory device according to claim 1 , wherein5-40 atomic % of Ge is included in the SiGe layer.5. The nonvolatile semiconductor memory device according to claim 1 , whereina film thickness of the SiGe layer is 2-4 nm.6. The nonvolatile semiconductor memory device according to claim 1 , whereina film thickness of the electrode is 5-30 nm.7. The nonvolatile semiconductor memory device according to claim 1 , whereinthe SiGe layer is connected to a surface of the variable resistance element acting as a negative electrode in a setting operation and acting as a positive electrode in a resetting operation.8. A nonvolatile semiconductor memory device including a plurality of memory cell arrays that are stacked claim 1 , the memory cell arrays each including: first lines; second lines intersecting the first lines; and memory cells ...

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Номер записи: 21
12-09-2013 дата публикации

Memory Diodes

Номер: US20130234098A1
Автор: ROTHSCHILD Avner
Принадлежит: Technion Research & Development Foundation Ltd.

A memory cell (C), including a first non-insulator (C) and a second non-insulator (C), different from the first non-insulator. The second non-insulator forms a junction (C) with the first non-insulator. The cell further includes a first electrode (C) which is connected to the first non-insulator and a second electrode (C) which is connected to the second non-insulator. At least one of the first and second non-insulators is chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and has an ionic transference number less than 1 and greater than or equal to 0.5. 1. A memory cell , comprising:a first non-insulator;a second non-insulator, different from the first non-insulator, forming a junction with the first non-insulator;a first electrode connected to the first non-insulator; anda second electrode connected to the second non-insulator, wherein at least one of the first and second non-insulators is chosen from a group consisting of a solid electrolyte and a mixed ionic electronic conductor and has an ionic transference number less than 1 and greater than or equal to 0.5.2. The cell according to claim 1 , wherein the first non-insulator and the second non-insulator are selected so that the junction acts as a diode.3. The cell according to claim 1 , wherein at least one of the first and the second non-insulators is selected from a group comprising a p-type material having a preponderance of holes claim 1 , an n-type material having a preponderance of electrons claim 1 , and an i-type claim 1 , intrinsic material.4. The cell according to claim 3 , wherein one of the first and the second non-insulators comprises a metal.5. The cell according to claim 1 , wherein the cell is configurable into one of two different stable states.6. The cell according to claim 5 , wherein the cell is configured into one of the two different states in response to applying one of a forward and a reverse current to the cell.7. The cell according to claim 5 , ...

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Номер записи: 22
12-09-2013 дата публикации

NONVOLATILE MEMORY CELLS HAVING PHASE CHANGEABLE PATTERNS THEREIN FOR DATA STORAGE

Номер: US20130234100A1
Автор: Ahn Dong-ho, An Hyeong-Geun, Ha Yong-ho, Jang Jun-Young, Ko Han-Bong, LEE Gyeo-Re, LIM Dong-Won, Lim Young-Soo, Park Joon-Sang, Park Young-Lim
Принадлежит:

Phase change memory devices can have bottom patterns on a substrate. Line-shaped or L-shaped bottom electrodes can be formed in contact with respective bottom patterns on a substrate and to have top surfaces defined by dimensions in x and y axes directions on the substrate. The dimension along the x-axis of the top surface of the bottom electrodes has less width than a resolution limit of a photolithography process used to fabricate the phase change memory device. Phase change patterns can be formed in contact with the top surface of the bottom electrodes to have a greater width than each of the dimensions in the x and y axes directions of the top surface of the bottom electrodes and top electrodes can be formed on the phase change patterns, wherein the line shape or the L shape represents a sectional line shape or a sectional L shape of the bottom electrodes in the x-axis direction. 1. A memory device , comprising:a word line on a substrate;a diode on the word line;a bottom electrode on the diode, the bottom electrode having an L-shape when viewed in cross section;an interlayer insulating layer in contact with a first side portion of the bottom electrode;a first insulating pattern in contact with a second side portion of the bottom electrode;a second insulating pattern in contact with a third side portion of the bottom electrode;a phase changeable pattern on the bottom electrode; anda bit line on the phase changeable pattern.2. The memory device of claim 1 , wherein an interface between the phase changeable pattern and the bottom electrode has a line shape when viewed from a plan perspective.3. The memory device of claim 2 , wherein a longitudinal direction of the interface between the phase changeable pattern and the bottom electrode is parallel to a longitudinal direction of the bit line.4. The memory device of claim 1 , wherein a top surface of the bottom electrode is in contact with the phase changeable pattern.5. The memory device of claim 4 , wherein the top ...

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Номер записи: 23
12-09-2013 дата публикации

Nanoscale switching device with an amorphous switching material

Номер: US20130234103A1
Автор: Gilberto Medeiros Ribeiro, Jianhua Yang, R. Stanley Williams
Принадлежит: Hewlett Packard Development Co LP

Nanoscale switching devices are disclosed. The devices have a first electrode of a nanoscale width; a second electrode of a nanoscale width; and a layer of an active region disposed between and in electrical contact with the first and second electrodes. The active region contains a switching material capable of carrying a significant amount of defects which can trap and de-trap electrons under electrical bias. The switching material is in an amorphous state. A nanoscale crossbar array containing a plurality of the devices and a method for making the devices are also disclosed.

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Номер записи: 24
12-09-2013 дата публикации

VIA FORMATION FOR CROSS-POINT MEMORY

Номер: US20130235655A1
Автор: Tang Stephen
Принадлежит: MICRON TECHNOLOGY, INC.

Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device. 1. A memory device , comprising:a first plurality of electrically conductive lines oriented in a first direction on a first level;a second plurality of electrically conductive lines oriented in a second direction on a second level; andone or more electrically conductive vias having a width substantially the same as that of the electrically conductive lines of the first plurality of electrically conductive lines, the vias extending from the first level to the second level between lines of the first and second pluralities of electrically conductive lines.2. The memory device of claim 1 , further comprising an array of memory cells positioned between the first plurality of electrically conductive lines and the second plurality of electrically conductive lines.3. The memory device of claim 2 , wherein the array of memory cells comprises an array of phase change memory cells configured as a cross-point array.4. The memory device of claim 3 , wherein the cross-point array comprises an array of selector devices positioned between the array of phase change memory cells and the second plurality of electrically conductive lines.5. The memory device of claim 4 , wherein the first plurality of electrically conductive lines comprise word-lines for the array of memory cells.6. The memory device of claim 5 , wherein the second plurality of electrically conductive lines comprise bit-lines for the array of memory cells.7. A system claim 5 , comprising: a first plurality of electrically conductive lines oriented in a first direction on a first level,', 'a second plurality of electrically conductive lines oriented in a second direction on a second level,', 'one or more electrically ...

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Номер записи: 25
19-09-2013 дата публикации

NON-VOLATILE MEMORY INCLUDING MULTILAYER MEMORY CELLS AND METHOD OF FABRICATING THE SAME

Номер: US20130240823A1
Автор: KWON Euipil
Принадлежит:

A non-volatile memory and a method of fabricating the same, more particularly, a non-volatile memory in which memory cells each includes an anti-fuse and a diode or a variable resistor and a diode are stacked in a multilayer laminate structure without increasing a horizontal area, to effectively utilize a vertical space and thereby significantly increase a degree of integration so that the memory cells are able to be highly integrated and perform high-speed operation, and a method of fabricating the non-volatile memory. 1. A non-volatile memory , whereina plurality of semiconductor layers are stacked on a semiconductor substrate to form a multilayered semiconductor layer, a plurality of interlayer insulating layers are respectively formed between the semiconductor substrate and the lowest one of the semiconductor layers and between the semiconductor layers,a plurality of first step height cells and a plurality of second step height cells having a different step height than the first step height cells are formed on the semiconductor substrate or on each semiconductor layer of the multilayered semiconductor layer, each of the first step height cells and the second step height cells is configured to have one of a first multilayer laminate structure including a conductive layer (a first electrode)—a variable resistor (an intermediate layer)—a conductive layer (a second electrode)—a semiconductor layer, a second multilayer laminate structure including the conductive layer (the first electrode)—the variable resistor (the intermediate layer)—the semiconductor layer (the second electrode), and a third multilayer laminate structure including the conductive layer (the first electrode)-an insulating layer (the intermediate layer)—the conductive layer (the second electrode)—the semiconductor layer, and a fourth multilayer laminate structure including the conductive layer (the first electrode)—the insulating layer (the intermediate layer)—the semiconductor layer (the second ...

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Номер записи: 26
19-09-2013 дата публикации

Integrated Circuitry, Switches, and Methods of Selecting Memory Cells of a Memory Device

Номер: US20130240827A1
Автор: Sandhu Gurtej S.
Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include switches that have a graphene structure connected to a pair of spaced-apart electrodes. The switches may further include first and second electrically conductive structures on opposing sides of the graphene structure from one another. The first structure may extend from one of the electrodes, and the second structure may extend from the other of the electrodes. Some embodiments include the above-described switches utilized as select devices in memory devices. Some embodiments include methods of selecting memory cells. 125-. (canceled)26. A switch comprising:a graphene structure extending vertically between a first electrode and a second electrode;first and second electrically conductive structures horizontally displaced from the graphene structure and configured to provide an electric field across the graphene structure, wherein the first electrically conductive structure is conductively coupled to one of the electrodes, and wherein the second electrically conductive structure is conductively coupled to the other of the electrodes.27. The switch of claim 26 , wherein the first electrically conductive structure is an electrically conductive projection extending from the first electrode claim 26 , and wherein the second electrically conductive structure is an electrically conductive projection extending from the second electrode.28. The switch of claim 26 , wherein the graphene structure comprises two layers of graphene; the individual layers having thicknesses of from about 1 nanometer to about 5 nanometers.29. A switch comprising:a first electrode spaced from a second electrode;first and second graphene structures conductively connected to both of the first and second electrodes;a first electrically conductive projection extending from the first electrode and being on one side of the first graphene structure;a second electrically conductive projection extending from the second electrode, being between the first and second graphene structures ...

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Номер записи: 27
26-09-2013 дата публикации

SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THE SAME

Номер: US20130248804A1
Автор: KAWAI Murato
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A semiconductor storage device according to an embodiment includes a first conductive layer, a variable resistance layer, an electrode layer, a first liner layer, a stopper layer, and a second conductive layer. The variable resistance layer is provided above the first conductive layer. The electrode layer contacts an upper surface of the variable resistance layer. The first liner layer contacts the upper surface of the electrode layer. The stopper layer contacts the upper surface of the first liner layer. The second conductive layer is provided above the stopper layer. The first liner layer is made of a material having a property for canceling an influence of an orientation of a lower layer of the first liner layer, the property of the first liner layer being superior compared with that of the stopper layer. 1. A semiconductor storage device comprising:a first conductive layer;a variable resistance layer provided above the first conductive layer;an electrode layer contacting an upper surface of the variable resistance layer;a first liner layer contacting an upper surface of the electrode layer;a stopper layer contacting an upper surface of the first liner layer; anda second conductive layer provided above the stopper layer,the first liner layer being made of a material having a property for canceling an influence of an orientation of a lower layer of the first liner layer, the property of the first liner layer being superior compared with that of the stopper layer.2. The semiconductor storage device according to claim 1 , wherein the first liner layer is made of one of tungsten nitride claim 1 , tungsten silicon claim 1 , and amorphous silicon.3. The semiconductor storage device according to claim 1 , further comprising:an inter-layer insulator contacting a side surface of the variable resistance layer, a side surface of the electrode layer, a side surface of the first liner layer, and a side surface of the stopper layer; anda second liner layer contacting an upper ...

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Номер записи: 28
26-09-2013 дата публикации

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20130248811A1
Автор: Ren Wanchun
Принадлежит:

This invention discloses a semiconductor device and its manufacturing method. According to the method, a stop layer is deposited on a step-shaped bottom electrode, and then a first insulating layer is deposited through a high aspect ratio process. A first chemical mechanical polishing is performed until the stop layer. A second chemical mechanical polishing is then performed to remove the upper horizontal portion of the bottom electrode. Then, a phase-change material can be formed on the vertical portion of the bottom electrode to form a phase-change element. Through arranging a stop layer, the chemical mechanical polishing process is divided into two stages. Thus, during the second chemical mechanical polishing process preformed on the bottom electrode, polishing process can be precisely controlled to avoid the unnecessary loss of the bottom electrode. 1. A semiconductor device comprising:a substrate;an L-shaped electrode disposed above the substrate, said electrode having a vertical portion and a lower horizontal portion;a first insulating layer; and an L-shaped stop layer disposed between the electrode and the first insulating layer, said L-shaped stop layer having a horizontal portion overlaying said lower horizontal portion of said electrode and a vertical portion;said L-shaped stop layer and said first insulating layer having different chemical mechanical polishing selectivity ratios.2. The semiconductor device according to wherein said L-shaped stop layer comprises at least one of amorphous carbon claim 1 , AlO claim 1 , SiCNH claim 1 , TiO claim 1 , HfO claim 1 , TaOand SiN.3. The semiconductor device according to wherein said L-shaped stop layer has a thickness ranging from 200 Å to 1000 Å.4. The semiconductor device according to wherein said first insulating layer comprises silicon oxide.5. The semiconductor device according to further comprising: a phase-change material overlaying the vertical portion of said electrode.6. The semiconductor device ...

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Номер записи: 29
26-09-2013 дата публикации

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130248813A1
Автор: Fujii Satoru, Ito Satoru, Mikawa Takumi
Принадлежит: Panasonic Corporation

Provided is a nonvolatile semiconductor memory device including a variable resistance element in which a parasitic resistance between the lower electrode and the variable resistance layer included in the variable resistance element is reduced. The nonvolatile semiconductor memory device includes: a substrate; and a variable resistance element formed on the substrate, wherein the variable resistance element includes a lower electrode layer formed on the substrate, a variable resistance layer formed on the lower electrode layer, and an upper electrode layer formed on the variable resistance layer, the lower electrode layer includes at least a first conductive layer and a second conductive layer which is formed on the first conductive layer and is in contact with the variable resistance layer, and the first conductive layer includes an oxidatively degraded layer which is formed on an upper surface of the first conductive layer due to oxidization of the first conductive layer. 1. A variable resistance nonvolatile semiconductor memory device comprising:a substrate; anda variable resistance element formed on the substrate, having a resistance value which changes in response to application of an electric pulse, and holding the changed resistance value,wherein the variable resistance element includes (i) a lower electrode layer formed on the substrate, (ii) a variable resistance layer formed on the lower electrode layer and comprising a metal oxide, and (iii) an upper electrode layer formed on the variable resistance layer,the lower electrode layer includes at least a first conductive layer and a second conductive layer which is formed on the first conductive layer and is in contact with the variable resistance layer, andthe first conductive layer includes an oxidatively degraded layer which is formed on an upper surface of the first conductive layer due to oxidization of the first conductive layer.2. The nonvolatile semiconductor memory device according to claim 1 ,wherein ...

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Номер записи: 30
26-09-2013 дата публикации

Nonvolatile memory element and nonvolatile memory device

Номер: US20130250658A1
Автор: Koji Katayama, Satoru Mitani, Shunsaku Muraoka, Takeshi Takagi, Zhiqiang Wei
Принадлежит: Panasonic Corp

A nonvolatile memory device includes: a first electrode; a second electrode; and a variable resistance layer which includes: a first oxide layer including a first metal oxide; a second oxide layer located between and in contact with the first oxide layer and a second electrode including a second metal oxide and having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first oxide layer; and a local region located in the first oxide layer and the second oxide layer, having contact with the second electrode and no contact with the first electrode, and having a degree of oxygen deficiency higher than the degree of oxygen deficiency of the second oxide layer and different from the degree of oxygen deficiency of the first oxide layer.

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Номер записи: 31
03-10-2013 дата публикации

NONVOLATILE MEMORY ELEMENT AND METHOD OF MANUFACTURING THE SAME

Номер: US20130256623A1
Автор: KIM Eun-Mi, Nakagawa Takashi, OTANI Yuichi
Принадлежит:

The present invention provides a nonvolatile memory element, in a nonvolatile memory element having a variable resistance layer possessing a stacked structure, in which the variable resistance layer has a high resistance change ratio, and a method of manufacturing the same. The nonvolatile memory element according to one embodiment of the present invention includes a first electrode, a second electrode, and a variable resistance layer which is interposed between the first electrode and second electrode and in which the resistance value changes into at least two different resistance states. The variable resistance layer possesses a stacked structure having a first metal oxide layer containing Hf and O, and a second metal oxide layer that is provided between the first metal oxide layer and at least one of the first electrode and the second electrode and contains Al and O. 1. A nonvolatile memory element comprising:a first electrode;a second electrode; anda variable resistance layer that is interposed between the first electrode and the second electrode and in which a resistance value thereof changes into at least two different resistance states,wherein the variable resistance layer possesses a stacked structure having a first metal oxide layer containing Hf and O and a second metal oxide layer that is provided between the first metal oxide layer and at least one of the first electrode and the second electrode and contains Al and O,wherein a molar ratio of Hf and O (O/Hf) of the first metal oxide layer has a composition range represented by 0.30 to 1.90, and a molar ratio of Al and O (O/Al) of the second metal oxide layer has a composition range represented by 1.0 to 2.2,wherein the first electrode and the second electrode are made of a titanium nitride film,wherein each of film compositions of the titanium nitride films (a N/Ti ratio) of the first and second electrodes is 1.15 or more, andwherein each of film densities of the titanium nitride films of the first and ...

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Номер записи: 32
10-10-2013 дата публикации

RESISTANCE CHANGE MEMORY AND MANUFACTURING METHOD THEREOF

Номер: US20130264535A1
Автор: SONEHARA Takeshi
Принадлежит:

According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, and a cell unit which is provided between the first interconnect line and the second interconnect line and which includes a non-ohmic element and a memory element, the non-ohmic element including a conductive layer provided on at least one of first and second ends of the cell unit and a silicon portion provided between the first and second ends, the memory element being connected to the non-ohmic element via the conductive layer and storing data in accordance with a reversible change in a resistance state, wherein the non-ohmic element includes a first silicon germanium region in the silicon portion. 118-. (canceled)19. A resistance change memory comprising:a first interconnect line extending in a first direction;a second interconnect line extending in a second direction intersecting with the first direction; anda cell unit which is provided between the first interconnect line and the second interconnect line and which includes a non-ohmic element and a memory element, the non-ohmic element including a conductive layer provided on at least one of first and second ends of the cell unit and a silicon portion provided between the first and second ends, the memory element being connected to the non-ohmic element via the conductive layer and storing data in accordance with a reversible change in a resistance state,wherein the non-ohmic element includes a P-type silicon layer and an N-type silicon layer provided in the silicon portion and a first silicon germanium region provided in the N-type silicon layer.20. The resistance change memory according to claim 19 , whereinthe first silicon germanium region is contacting to the conductive layer.21. The resistance change memory according to claim 19 , whereinan intrinsic silicon region is provided between the ...

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Номер записи: 33
17-10-2013 дата публикации

MICROELECTRONIC DEVICE WITH PROGRAMMABLE MEMORY, INCLUDING A LAYER OF DOPED CHALCOGENIDE THAT WITHSTANDS HIGH TEMPERATURES

Номер: US20130270505A1
Автор: Dahmani Faiz
Принадлежит:

A microelectronic device with programmable memory () includes a first metallic electrode () deposited at least in part on a substrate (), a doped chalcogenide layer () deposited on the first metallic electrode () and a second metallic electrode () deposited on the doped chalcogenide layer (). The device further has an intermediate layer () positioned between the first metallic electrode () and the doped chalcogenide layer (), the intermediate layer () being a layer of a metallic element having the following properties a and b: a) a coefficient of thermal conductivity greater than or equal to 60 W/m·K; and b) mechanical stress less than or equal to −1600 MPa. 1. A microelectronic device with programmable memory , comprising:a first metallic electrode deposited at least in part on a substrate;a doped chalcogenide layer deposited on the first metallic electrode; anda second metallic electrode deposited on the doped chalcogenide layer;Wherein said device further comprises an intermediate layer positioned between the first metallic electrode and the doped chalcogenide layer, said intermediate layer being a layer of a metallic element having the following properties a and b:a. a coefficient of thermal conductivity greater than or equal to 60 W/m·K; andb. mechanical stress less than or equal to −1600 MPa.2. A device according to claim 1 , wherein the metallic element of the intermediate layer is ruthenium (Ru).3. A device according to claim 1 , wherein the thickness of the intermediate layer lies in the range 3 nm to 7 nm.4. A device according to claim 1 , wherein the intermediate layer is directly in physical contact with the first metallic electrode and with the doped chalcogenide layer.5. A device according to claim 1 , wherein the intermediate layer is a diffusion barrier.6. A device according to claim 1 , wherein the microelectronic device does not include an intermediate layer positioned between the doped chalcogenide layer and the second metallic electrode.7. A ...

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Номер записи: 34
17-10-2013 дата публикации

VARIABLE RESISTANCE MEMORY DEVICES AND METHOD OF FORMING THE SAME

Номер: US20130270507A1
Автор: Kang Mansug, PARK JeongHee
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A variable resistance memory device includes a lower electrode on a substrate, a variable resistance pattern on the lower electrode, and an upper electrode on the variable resistance pattern. The upper electrode is in contact with at least a sidewall of the variable resistance pattern. 1. A variable resistance memory device , comprising:a lower electrode on a substrate;a variable resistance pattern on the lower electrode; andan upper electrode on the variable resistance pattern, the upper electrode being in contact with at least a sidewall of the variable resistance pattern.2. The variable resistance memory device as claimed in claim 1 , wherein a top surface of the variable resistance pattern is higher than a bottom surface of the upper electrode.3. The variable resistance memory device as claimed in claim 1 , further comprising a mold layer adjacent to the variable resistance pattern claim 1 , an upper portion of the variable resistance pattern protruding above a top surface of the mold layer.4. The variable resistance memory device as claimed in claim 3 , wherein the upper electrode is in contact with an entirety of sidewalls of the variable resistance pattern that protrude above the top surface of the mold layer.5. The variable resistance memory device as claimed in claim 3 , wherein:the variable resistance pattern is one of a plurality of variable resistance patterns arranged in the mold layer, andupper portions of the variable resistance patterns that protrude above the mold layer are connected to each other in a first direction.6. The variable resistance memory device as claimed in claim 5 , further comprising a first spacer between the mold layer and the lower electrode claim 5 , the lower electrode being in the mold layer claim 5 , being under the variable resistance pattern claim 5 , and having an L-shaped cross section.7. The variable resistance memory device as claimed in claim 6 , further comprising:a filling insulating layer between the variable ...

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Номер записи: 35
24-10-2013 дата публикации

VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Номер: US20130277637A1
Автор: Kim Byeung Chul
Принадлежит:

A variable resistance memory device has memory cells that are operated by Joule's heat and which are highly thermally efficient. Conductive patterns are formed on a substrate; sacrificial patterns exposing a portion of the top surface of each of the conductive patterns are formed on the conductive patterns, lower electrodes are formed by etching upper portions of the conductive patterns using the sacrificial patterns as an etching mask, then mold patterns are formed on the lower electrodes and cover exposed sidewall surfaces of the sacrificial patterns, and then the sacrificial patterns are replaced with variable resistance patterns. 1. A variable resistance memory device comprising:a substrate;lower electrodes disposed on the substrate;patterns having variable resistance disposed on the lower electrodes and in contact therewith; andupper electrodes disposed on the variable resistance patterns,wherein each of the lower electrodes has at least first and second upwardly facing surfaces located at different heights in the device, and sidewall surfaces terminating at the first upwardly facing surface,the first upwardly facing surface of each of the lower electrodes is the top surface of the lower electrodes and contacts the variable resistance patterns disposed thereon, andat least one of the sidewall surfaces of each of the lower electrodes is aligned with a sidewall surface of the variable resistance patterns disposed thereon.2. The variable resistance memory device of claim 1 , wherein each of the lower electrodes has a third upwardly facing surface located at a different height in the device than each of the first and second surfaces thereof.3. The variable resistance memory device of claim 1 , wherein the area of the first upwardly facing surface of each of the lower electrodes is substantially equal to the area of contact between the lower electrodes and the variable resistance patterns disposed thereon.4. The variable resistance memory device of claim 1 , wherein ...

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Номер записи: 36
24-10-2013 дата публикации

Memristive Element and Electronic Memory Based on Such Elements

Номер: US20130277638A1
Автор: Franger Sylvain, Moradpour Alexandre, Revcolevschi Alexandre, Salot Raphael, Schneegans Olivier
Принадлежит:

The invention relates to a memristive element (M) formed by: a first electrode (); a second electrode (); and an active region () making direct electrical contact with said first and second electrodes, characterized in that said active region essentially consists of a thin film of an insertion compound containing at least one alkali metal, said compound being an oxide or chalcogenide of at least one transition metal and being able to conduct both electrons and ions. Non-volatile electronic memory formed from a plurality of such memristive elements. 1. A memristive element (M) formed by:a first electrode;a second electrode; andan active region making direct electrical contact with said first and second electrodes,wherein said active region comprises a thin film of an insertion compound of at least one alkali metal, made of an oxide or chalcogenide of at least one transition metal, exhibiting conductivity that is both electronic and ionic in nature.2. The memristive element as claimed in claim 1 , in which said thin film is deposited on a surface of said first electrode.3. The memristive element as claimed in claim 1 , in which said first electrode is chosen from a surface of a degenerate semiconductor substrate and a metallic film deposited on an insulating substrate.4. The memristive element as claimed in claim 1 , in which said second electrode is formed by a metallic film deposited on said thin film.5. The memristive element as claimed in claim 1 , in which said thin film has a polycrystalline or amorphous structure.6. The memristive element as claimed in claim 1 , in which said thin film is 10 μm or less in thickness.7. The memristive element as claimed in claim 1 , in which said insertion compound of at least one alkali metal claim 1 , made of an oxide or chalcogenide of at least one transition metal claim 1 , has the following formula:{'br': None, 'sub': x', '1', 'v', '2', 'w', '3', 'y', '4', 'z', 'β, 'A(M)(M)(M)(M)B'} A represents one or more alkali metals;', ...

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Номер записи: 37
24-10-2013 дата публикации

HETERO-SWITCHING LAYER IN A RRAM DEVICE AND METHOD

Номер: US20130279240A1
Автор: Jo Sung Hyun
Принадлежит:

A non-volatile memory device structure includes first electrodes comprising conductive silicon-containing material, a plurality of resistive switching material stacks comprising first resistive switching material and second resistive switching material overlying the first electrode, wherein the first resistive switching material comprises a first resistance switching voltage and the second resistive switching material comprises a second resistance switching voltage less than the first amplitude, second electrodes comprising metal material overlying and electrically coupled to the plurality of resistive switching material stacks, wherein a plurality of memory elements are formed from the first plurality of electrodes, the plurality of resistive switching material stacks, and the second plurality of electrodes. 1. A non-volatile memory device structure comprising:a first plurality of electrodes, wherein each electrode from the first plurality of electrodes comprises a conductive silicon-containing material;a plurality of resistive switching material stacks overlying the plurality of first electrodes, wherein each resistive switching material stack from the plurality of resistive switching material stacks comprises a first resistive switching material and a second resistive switching material, wherein the second resistive switching material overlies the first electrode, wherein the first resistive switching material overlies and contacts the second resistive switching material, wherein the first resistive switching material is characterized by a first switching voltage having a first amplitude, wherein the second resistive switching material is characterized by a second switching voltage having a second amplitude, wherein the second amplitude is less than the first amplitude;a second plurality of electrodes, wherein each electrode from the second plurality of electrodes comprises a metal material overlying and electrically coupled to first resistive switching material ...

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Номер записи: 38
31-10-2013 дата публикации

VARIABLE RESISTIVE ELEMENT, METHOD FOR PRODUCING THE SAME, AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING THE VARIABLE RESISTIVE ELEMENT

Номер: US20130285005A1
Автор: TAMAI Yukio
Принадлежит: SHARP KABUSHIKI KAISHA

A variable resistive element configured to reduce a forming voltage while reducing a variation in forming voltage among elements, a method for producing it, and a highly integrated nonvolatile semiconductor memory device provided with the variable resistive element are provided. The variable resistive element includes a resistance change layer (first metal oxide film) and a control layer (second metal oxide film) having contact with a first electrode sandwiched between the first electrode and a second electrode. The control layer includes a metal oxide film having a low work function (4.5 eV or less) and capable of extracting oxygen from the resistance change layer. The first electrode includes a metal having a low work function similar to the above metal, and a material having oxide formation free energy higher than that of an element included in the control layer, to prevent oxygen from being thermally diffused from the control layer. 1. A variable resistive element comprisinga first metal oxide film which is an oxide film of a first metal and sandwiched between a first electrode and a second electrode, whereinthrough a forming process, a resistance state between the first and second electrodes of the variable resistive element is changed from an initial high resistance state before the forming process to a variable resistance state,the resistance state in the variable resistance state is changed between two or more different resistance states by applying an electric stress between the first electrode and the second electrode of the variable resistive element in the variable resistance state, and one resistance state after the change is used for storing information,a control layer containing oxygen is inserted between the first electrode and the first metal oxide film, and formed of a second metal capable of extracting oxygen from the first metal oxide film to prevent oxygen from being thermally diffused from the first metal oxide film to the first electrode,the ...

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Номер записи: 39
31-10-2013 дата публикации

NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20130285255A1
Автор: NITTA Hiroyuki
Принадлежит:

According to the nonvolatile memory device in one embodiment, contact plugs connect between second wires and third wires in a memory layer and a first wire connected to a control element. Drawn wire portions connect the second wires and the third wires with the contact plug. The drawn wire portion connected to the second wires and the third wires of the memory layer is formed of a wire with a critical dimension same as the second wires and the third wires and is in contact with the contact plug on an upper surface and both side surfaces of the drawn wire portion. 117-. (canceled)18. A nonvolatile memory device comprising:a nonvolatile memory cell formed in a memory cell region;a first wire formed in a contact forming region adjacent to the memory cell region;second wires that extend in a first direction from the memory cell region to the contact forming region, and disposed at a different layer than the first wire, and including a first line portion extending in a second direction crossing the first direction in the contact forming region, and including a second line portion extending in the first direction in the memory cell region; anda contact plug contacting the first line portion and connecting to the second wires and the first wire;wherein a width of the first line portion is equal to a width of the second line portion, and the contact plug contacts an upper surface and first side surfaces of the first line portion.19. The nonvolatile memory device according to claim 18 , wherein an inter-layer dielectric film is formed under the second line portion claim 18 , and a first side surface of the inter-layer dielectric film contacts the contact plug.20. The nonvolatile memory device according to claim 18 , wherein the inter-layer dielectric film contacts the first wire.21. The nonvolatile memory device according to claim 18 , wherein a width of the contact plug in the first direction is wider than the width of the first line portion.22. The nonvolatile memory ...

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Номер записи: 40
31-10-2013 дата публикации

BIPOLAR SWITCHING MEMORY CELL WITH BUILT-IN "ON" STATE RECTIFYING CURRENT-VOLTAGE CHARACTERISTICS

Номер: US20130286712A1
Автор: Liu Jun, Sandhu Gurtej
Принадлежит:

A memory array is disclosed having bipolar current-voltage (IV) resistive random access memory cells with built-in “on” state rectifying IV characteristics. In one embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/semiconductor stack that forms a Schottky diode when switched to the “on” state. In another embodiment, a bipolar switching resistive random access memory cell may have a metal/solid electrolyte/tunnel barrier/electrode stack that forms a metal-insulator-metal device when switched to the “on” state. Methods of operating the memory array are also disclosed. 1. A memory device , comprising: a semiconductor;', 'a solid electrolyte disposed directly on the semiconductor; and', 'a metal disposed on the electrolyte, wherein the metal comprises a metal ion source., 'a resistive random access memory (RRAM) cell, including2. The memory device of claim 1 , wherein the semiconductor comprises GaP claim 1 , Ge claim 1 , GaSe claim 1 , InP claim 1 , GaAs claim 1 , InGaP claim 1 , ZnTe claim 1 , Si claim 1 , Ge claim 1 , ZnS claim 1 , SiC claim 1 , GaTe claim 1 , InGaAs claim 1 , SrTiO(STO) claim 1 , PrCaMnO (PCMO) claim 1 , Ca3Si claim 1 , CrSix claim 1 , RUSi claim 1 , or any combination thereof.3. The memory device of claim 1 , wherein the solid electrolyte comprises doped chalcogenide glass of formula AxBy claim 1 , where B is selected from among S claim 1 , Se and Te and mixtures thereof claim 1 , and where A includes at least one element from the group of B claim 1 , Al claim 1 , Ga claim 1 , In claim 1 , or Tl claim 1 , from the group of C claim 1 , Si claim 1 , Ge claim 1 , Sn claim 1 , Pb claim 1 , from the group of N claim 1 , P claim 1 , As claim 1 , Sb claim 1 , Bi claim 1 , or from the group of F claim 1 , Cl claim 1 , Br claim 1 , I claim 1 , or At of the periodic table and with the dopant being selected from among the group of Ag claim 1 , Au claim 1 , Pt claim 1 , Cu claim 1 , Cd claim 1 , Ir claim 1 , ...

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Номер записи: 41
07-11-2013 дата публикации

PHASE CHANGE MEMORY CELL AND FABRICATION METHOD THEREOF

Номер: US20130292629A1
Автор: Feng Songlin, LI Ying, LIU Bo, Song Zhitang, Zhang Ting, Zhong Min
Принадлежит:

The present invention provides a phase change memory cell and fabrication method thereof, wherein said phase change memory cell comprises a semiconductor substrate, a first electrode layer, a phase change material layer, a second electrode layer and an extraction electrode, as well as a high resistance material layer used to prevent said phase change material layer from over-corrosion during the chemical mechanical polishing process, and wherein said high resistance material layer has a resistance ten or more times that of the phase change material layer and can be used to prevent phase change material layer from over-corrosion during the chemical mechanical polishing process and thus enhance the memory performance and the yield of phase change memory cell. 1. A phase change memory cell , comprising a semiconductor substrate , and a first electrode layer , a phase change material layer and a second electrode layer that are sequentially located on said semiconductor substrate , and an extraction electrode located on said semiconductor substrate; characterized by also comprising a high resistance material layer used to prevent said phase change material layer from over-corrosion during the chemical mechanical polishing process , wherein said high resistance material layer has a resistance ten or more times that of the phase change material layer.2. The phase change memory cell according to claim 1 , characterized in that said high resistance material layer is located between said first electrode layer and said phase change material layer claim 1 , or located on the extraction electrode of said first electrode layer.3. The phase change memory cell according to claim 1 , characterized in that said high resistance material layer is made of any one of the following: simple substance of main group IV claim 1 , V and VI claim 1 , alloy claim 1 , oxide claim 1 , nitride claim 1 , carbide claim 1 , nitrogen oxide.4. The phase change memory cell according to claim 1 , ...

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Номер записи: 42
07-11-2013 дата публикации

Multi-Layered Phase-Change Memory Device

Номер: US20130292631A1
Автор: Chang Chih-Chung, Chin Tsung-Shune, Chu Yung-Ching
Принадлежит: FENG CHIA UNIVERSITY

The invention discloses a phase-change memory device structure and the materials used. The structure includes a substrate; a single or multiple sandwich-memory-unit(s); a first and a second electrode electrically connecting to the first and the second sides of the sandwich-memory-units and a dielectric layer used as the insulator required by the memory device. The sandwich-memory-unit composes of a memory-layer, thinner than 30 nm, sandwiched between an upper and a lower barrier-layers. The barrier-layer is either an electrical conductor in case of vertical memory-cells or an electrical insulator in case of parallel memory-cells. The sandwich-memory-unit is characteristic of increased crystallization temperature of at least 50° C. as the thickness of the memory-layer is reduced from 15 to 5 nm; and the volume change of the memory-layer is less than 3% during phase change. The thickness and memory-material in each sandwich-memory-unit can be different in the multiple sandwich-memory-units. 1. An multi-layered phase-change memory device comprises:a substrate;a single or multiple sandwich-memory-unit(s) disposed on the substrate comprising: 'a barrier layer disposed on top and bottom surfaces of the memory-layer respectively, resulting the single or multiple sandwich-memory-unit(s) forming a three-layered barrier-layer/memory-layer/barrier-layer structure, wherein material of the memory-layer is a pure element or a doped single-element-phase, crystallization is at least 100° C. as the thickness of the memory-layer is 15 nanometer (nm), crystallization is at least 150° C. as the thickness is reduced from 15 nm to 5 nm; the material of the memory-layer and is characteristic of a less than 3% volume change during phase-change;', 'a memory-layer 'comprising of a first electrode and a first electrical conductive barrier layer, the first electrode assembly-layer settled next to and electrically connected with the single or multiple sandwich-memory-unit(s);', 'a first ...

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Номер записи: 43
07-11-2013 дата публикации

Resistive Switching Memory Element Including Doped Silicon Electrode

Номер: US20130292632A1
Автор: Chiang Tony P., Miller Michael, Phatak Prashant B., Wu Wen
Принадлежит:

A resistive switching memory is described, including a first electrode comprising doped silicon having a first work function, a second electrode having a second work function that is different from the first work function by between 0.1 and 1.0 electron volts (eV), a metal oxide layer between the first electrode and the second electrode, the metal oxide layer switches using bulk-mediated switching using unipolar or bipolar switching voltages for switching from a low resistance state to a high resistance state and vice versa. 1. A non-volatile resistive-switching memory element comprising:a first electrode having a first work function;a second electrode having a second work function differing from the first work function of the first electrode by between 0.1 and 1.0 electron volts (eV); anda metal oxide switching layer provided between the first electrode and the second electrode,wherein the metal oxide switching layer is configured to switch between a low resistance state and a high resistance state based on bulk-mediated switching, andwherein the switching is caused by applying unipolar or bipolar switching voltages to the non-volatile resistive-switching memory element.2. The non-volatile resistive-switching memory element of claim 1 , wherein switching using unipolar switching voltages comprises applying voltages with a same polarity to switch the metal oxide switching layer between the low resistance state and the high resistance state.3. The non-volatile resistive-switching memory element of claim 1 , wherein switching using unipolar switching voltages comprises applying voltage pulses with a same polarity to switch the metal oxide switching layer between the low resistance state and the high resistance state.4. The non-volatile resistive-switching memory element of claim 1 , wherein switching using bipolar switching voltages comprises applying voltages with opposite polarities to switch the metal oxide switching layer between the low resistance state and the ...

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Номер записи: 44
21-11-2013 дата публикации

Memory Cells

Номер: US20130306930A1
Автор: Sills Scott E.
Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include memory cells. A memory cell may contain a switching region and an ion source region between a pair of electrodes. The switching region may be configured to reversibly retain a conductive bridge, with the memory cell being in a low resistive state when the conductive bridge is retained within the switching region and being in a high resistive state when the conductive bridge is not within the switching region. The memory cell may contain an ordered framework extending across the switching region to orient the conductive bridge within the switching region, with the framework remaining within the switching region in both the high resistive and low resistive states of the memory cell. 1. A memory cell , comprising:a switching region and an ion source region between a pair of electrodes; the switching region being configured to reversibly retain a conductive bridge; the memory cell being in a low resistive state when the conductive bridge is retained within the switching region and being in a high resistive state when the conductive bridge is not within the switching region; andan ordered framework extending across the switching region to orient the conductive bridge within the switching region; the framework remaining within the switching region in both the high resistive and low resistive states of the memory cell.2. The memory cell of wherein the ion source region comprises one or both of silver and copper.3. The memory cell of wherein the ion source region comprises copper and tellurium.4. The memory cell of wherein the framework comprises one or more of GeS claim 1 , GeSe claim 1 , SiO claim 1 , ZrO claim 1 , TiO claim 1 , TaO claim 1 , HfO claim 1 , AlO claim 1 , WO claim 1 , SnO claim 1 , NbO claim 1 , ZrTiO claim 1 , ZrWO claim 1 , AITiO claim 1 , VO claim 1 , MoO claim 1 , NiO claim 1 , YO claim 1 , ReO claim 1 , MnO claim 1 , FeO claim 1 , SiAlO claim 1 , SiTiO; where the listed compositions are described in terms of principle ...

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Номер записи: 45
21-11-2013 дата публикации

Sidewall Thin Film Electrode with Self-Aligned Top Electrode and Programmable Resistance Memory

Номер: US20130306931A1
Автор: LUNG HSIANG-LAN
Принадлежит: MACRONIX INTERNATIONAL CO., LTD.

A memory device includes an array of electrodes that includes thin film plates of electrode material. Multilayer strips are arranged as bit lines over respective columns in the array of electrodes, including a layer of memory material and a layer of top electrode material. The multilayer strips have a primary body and a protrusion having a width less than that of the primary body and is self-aligned with contact surfaces on the thin film plates. Memory material in the protrusion contacts surfaces on the distal ends of thin film plates of electrodes in the corresponding column in the array. The device can be made using a damascene process in self-aligned forms over the contact surfaces. 1. A memory device comprising:an electrode comprising a plate of electrode material, the plate having a proximal end and distal end having a contact surface with a contact areas, so that the area of the contact surface is determined by thickness of the plate at the contact surface and width of the plate at the contact surface; anda stack including a layer of memory material in contact with the contact surface, and a layer of top electrode material in contact with the layer of memory material, the stack having a primary body and a protrusion having a width less than that of the primary body, memory material in the protrusion contacting contact surface on the distal end of plate.2. The device of claim 1 , wherein the stack comprises or is in contact with a bit line.3. The device of claim 1 , wherein the protrusion is self-aligned with the contact surface of the corresponding plate.4. The device of claim 1 , wherein the protrusion extends through a form through insulating material claim 1 , the form being aligned with the contact surface of the plate.5. The device of claim 1 , wherein the plate has a shape including a first segment having a first width at the proximal end and extending toward the distal end to an intermediate position between the proximal and distal ends claim 1 , and a ...

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Номер записи: 46
21-11-2013 дата публикации

NONVOLATILE RESISTANCE CHANGE ELEMENT

Номер: US20130306932A1
Автор: Fujii Shosuke, MIYAGAWA Hidenori, Yamauchi Takashi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode, a semiconductor layer and a first layer. The first electrode includes at least one of Ag, Ni, Co, Al, Zn, Ti, and Cu. The semiconductor layer is sandwiched between the first and second electrodes. The first layer is provided between the second electrode and the semiconductor layer and contains an element included in the semiconductor layer and at least one of Ag, Ni, and Co. 1. A nonvolatile resistance change element comprising:a first electrode comprising at least one of Ag, Ni, Co, Al, Zn, Ti, and Cu;a second electrode;a semiconductor layer sandwiched between the first and second electrodes; anda first layer which is provided between the second electrode and the semiconductor layer and comprises an element included in the semiconductor layer and at least one of Ag, Ni, and Co.2. The nonvolatile resistance change element according to claim 1 , further comprisinga second layer which is provided between the first and second electrodes and comprises one of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film.3. The nonvolatile resistance change element according to claim 2 , whereinthe second layer is positioned between the semiconductor layer and the first layer.4. The nonvolatile resistance change element according to claim 3 , further comprisinga third layer which is provided between the first layer and the second electrode and comprises one of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film.5. The nonvolatile resistance change element according to claim 3 , whereinthe at least one of Ag, Ni, and Co comprised in the first layer has a concentration distribution which has a peak between the semiconductor layer and the second electrode.6. The nonvolatile resistance change element according to claim 2 , whereinthe second layer is positioned between the first layer and the second electrode.7. The ...

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Номер записи: 47
28-11-2013 дата публикации

RESISTIVE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20130313507A1
Автор: LEE Yu-Jin, Song Seok-Pyo
Принадлежит: SK HYNIX INC.

A resistive memory device includes a lower electrode formed on a substrate, a resistive layer formed on the lower electrode, and an upper electrode on the resistive layer, wherein a lower portion of the upper electrode is narrower than an upper portion of the upper electrode. 1. A resistive memory device comprising:a lower electrode formed over a substrate;a sacrificial layer formed over the lower electrode;a resistive layer buried in the sacrificial layer over the lower electrode; andan upper electrode formed over the resistive layer,wherein a top surface of the upper electrode protrudes higher than top surfaces of the resistive layer and the sacrificial layer.2. The resistive memory device of claim 1 , further comprising:a selection element formed on the upper electrode; anda selection electrode formed on the selection element.3. The resistive memory device of claim 1 , wherein the upper electrode has a pillar shape in which a lower portion is narrower than an upper portion and the resistive layer surrounds a sidewall and the lower portion of the upper electrode.4. The resistive memory device of claim 3 , wherein the upper electrode has a stepped sidewall having a width that is narrower at a lower portion thereof.5. The resistive memory device of claim I wherein the top surface of the resistive layer is substantially the same as the top surface of the sacrificial layer.6. The resistive memory device of claim 1 , wherein the entire top surface of the upper electrode protrudes above the entire top surfaces of the resistive layer and the sacrificial layer.7. The resistive memory device of claim 1 , wherein the top surface of the upper electrode has a rounded profile.8. The resistive memory device of claim further comprising:a selection element over the upper electrode; anda selection electrode over the upper electrode, wherein the selection element and the selection electrode are configured to select the resistive memory device formed by the lower electrode, the ...

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Номер записи: 48
28-11-2013 дата публикации

Bipolar Multistate Nonvolatile Memory

Номер: US20130313509A1
Автор: Chiang Tony P.
Принадлежит:

Embodiments generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching capacity by using multiple layers of variable resistance layers. In one embodiment, the resistive switching element comprises at least three layers of variable resistance materials to increase the number of logic states. Each variable resistance layer may have an associated high resistance state and an associated low resistance state. As the resistance of each variable resistance layer determines the digital data bit that is stored, the multiple variable resistance layers per memory element allows for additional data storage without the need to further increase the density of nonvolatile memory devices. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. 1. A multistate nonvolatile memory element comprising:a first layer operable as a first variable resistance layer;a second layer operable as a second variable resistance layer; anda third layer operable as a third variable resistance layer;wherein the first layer, the second layer, and the third layer are interconnected in series within the multistate nonvolatile memory element;wherein the first layer is configured to switch between a first low resistance state and a first high resistive state;wherein the second layer is configured to switch between a second low resistance state and a second high resistance state;wherein the third layer is configured to switch between a third low resistance state and a third high resistance state;wherein at least two of the first layer, the second layer, and the third layer comprises lanthanum oxide; andwherein the multistate nonvolatile memory element is switchable between at least four different stable resistive ...

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Номер записи: 49
12-12-2013 дата публикации

SWITCHING DEVICE AND MEMORY DEVICE INCLUDING THE SAME

Номер: US20130328006A1
Автор: HWANG Yun-Taek, YI Jae-Yun
Принадлежит: SK HYNIX INC.

A switching device includes a first electrode, a bipolar tunneling layer, and a second electrode. The bipolar tunneling layer is formed on the first electrode and includes a plurality of dielectric layers having different dielectric constants. The second electrode is formed on the bipolar tunneling layer. 110-. (canceled)11. A memory device comprising:a plurality of conductive lines intersecting each other; anda memory cell formed between the conductive lines at the intersections of the conductive lines and having a switching unit and a memory unit connected in series to each other,wherein the switching unit comprises a bipolar tunneling layer having a first dielectric layer, a second dielectric layer and a third dielectric layer that are stacked sequentially,wherein the first to third dielectric layers provide a bidirectional current path.12. The memory device of claim 11 , wherein the switching unit further comprises first and second electrodes claim 11 ,wherein the bipolar tunneling layer is interposed between the first and second electrodes.13. The memory device of claim 12 , wherein the memory unit comprises:a third electrode connected to one of the first and second electrodes of the switching unit;a variable resistance layer connected to the third electrode; anda fourth electrode connected to the variable resistance layer.14. The memory device of claim 13 , wherein the second electrode and the third electrode are formed of the same material to replace each other.15. The memory device of claim 13 , wherein the memory unit comprises a material having a resistance that varies according to voltage or current applied to the third electrode and the fourth electrode.16. (canceled)17. The memory device of claim 11 , wherein the second dielectric layer has a higher dielectric constant than the first dielectric layer and the third dielectric layer.18. The memory device of claim 17 , wherein the dielectric constant of the first dielectric layer and the dielectric ...

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Номер записи: 50
12-12-2013 дата публикации

NONVOLATILE RESISTANCE CHANGE ELEMENT

Номер: US20130328008A1
Автор: FUJI Shosuke, MIYAGAWA Hidenori, TAKASHIMA Akira
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode and a first layer. The first electrode includes a metal element. The second electrode includes an n-type semiconductor. The first layer is formed between the first electrode and the second electrode and includes a semiconductor element. The first layer includes a conductor portion made of the metal element. The conductor portion and the second electrode are spaced apart. 1. A nonvolatile resistance change element comprising:a first electrode comprising a metal element;a second electrode comprising an n-type semiconductor; anda first layer formed between the first electrode and the second electrode, the first layer including a conductor portion made of the metal element, and the conductor portion and the second electrode being spaced apart, the first layer including one of amorphous silicon, polysilicon, silicon oxide, and silicon nitride.2. The element according to claim 1 , further comprising a second layer formed between the first layer and the second electrode claim 1 , and which suppresses invasion of the conductor portion.3. The element according to claim 1 , further comprising a second layer formed between the first layer and the second electrode claim 1 , and the second layer includes one of a silicon oxide film claim 1 , a silicon oxynitride film claim 1 , and a silicon nitride film.4. The element according to claim 2 , wherein a diffusion coefficient for the metal element in the second layer is smaller than that of the first layer.5. The element according to claim 2 , wherein the second layer comprises the same material as that of the first layer claim 2 , and differs from the first layer comprising the semiconductor element in one of a density claim 2 , the number of dangling bonds claim 2 , and the number of defects.6. The element according to claim 1 , wherein an impurity concentration of the n-type semiconductor comprised in the second ...

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Номер записи: 51
19-12-2013 дата публикации

STORAGE DEVICE AND STORAGE UNIT

Номер: US20130334489A1
Автор: Ikarashi Minoru, Ohba Kazuhiro, Sei Hiroaki, Sone Takeyuki
Принадлежит:

A storage device includes: a first electrode; a storage layer including an ion source layer; and a second electrode. The first electrode, the storage layer, and the second electrode are provided in this order. The ion source layer contains a movable element, and has a volume resistivity of about 150 mΩ·cm to about 12000 mΩ·cm both inclusive. 1. A storage device , comprising:a first electrode;a storage layer including an ion source layer; anda second electrode,the first electrode, the storage layer, and the second electrode being provided in this order,wherein the ion source layer contains a movable element, and has a volume resistivity of about 150 mΩ·cm to about 12000 mΩ·cm both inclusive.2. The storage device according to claim 1 , wherein the ion source layer has the volume resistivity of about 450 mΩ·cm to about 3000 mΩ·cm both inclusive.3. The storage device according to claim 1 , wherein the movable element is positively or negatively ionized by application of an electric field.4. The storage device according to claim 3 , wherein the ion source layer contains claim 3 , as the movable element positively ionized claim 3 , one or more elements selected from a group consisting of Group 3 elements claim 3 , Group 4 elements claim 3 , and Group 5 elements of the Periodic Table.5. The storage device according to claim 4 , wherein the movable element positively ionized is one of titanium (Ti) claim 4 , zirconium (Zr) claim 4 , and hafnium (Hf).6. The storage device according to claim 3 , wherein the ion source layer contains claim 3 , as the movable element negatively ionized claim 3 , one or more elements selected from Group 16 elements of the Periodic Table.7. The storage device according to claim 6 , wherein the movable element negatively ionized is one of sulfur (S) claim 6 , selenium (Se) claim 6 , and tellurium (Te).8. The storage device according to claim 1 , wherein the ion source layer is free from aluminum (Al) and copper (Cu).9. The storage device according ...

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Номер записи: 52
19-12-2013 дата публикации

Transition Metal Oxide Bilayers

Номер: US20130334490A1
Автор: Gopal Vidyut, Hashim Imran, Minvielle Tim, Pham Hieu, Wang Yun, YAMAGUCHI Takeshi, Yang Hong Sheng
Принадлежит:

Embodiments of the invention include nonvolatile memory elements and memory devices comprising the nonvolatile memory elements. Methods for forming the nonvolatile memory elements are also disclosed. The nonvolatile memory element comprises a first electrode layer, a second electrode layer, and a plurality of layers of an oxide disposed between the first and second electrode layers. One of the oxide layers has linear resistance and substoichiometric composition, and the other oxide layer has bistable resistance and near-stoichiometric composition. Preferably, the sum of the two oxide layer thicknesses is between about 20 Å and about 100 Å, and the oxide layer with bistable resistance has a thickness between about 25% and about 75% of the total thickness. In one embodiment, the oxide layers are formed using reactive sputtering in an atmosphere with controlled flows of argon and oxygen. 1. A nonvolatile memory element comprising:a first layer operable as a first electrode;a second layer operable as a second electrode;{'sup': 1', '2, 'sub': w', 'x', 'y, 'a third layer comprising MeMeSiO, between the first layer and the second layer; and'}{'sup': 1', '2, 'sub': a', 'b', 'c', 'd, 'a fourth layer comprising MeMeSiObetween the first layer and the second layer;'}{'sup': 1', '2, 'wherein Meand Meare metals;'}wherein w≧0, x≧0, y≧0, z>0, a≧0 , b≧0, c≧0, and d>0;wherein at least one of w, x, or y>0;wherein at least one of a, b, or c>0;wherein one of the third layer or the fourth layer has a linear resistance and a sub-stoichiometric composition; andwherein another one of the third layer or the fourth layer has a bistable resistance and a near-stoichiometric composition.2. The nonvolatile memory element of claim 1 , wherein one of the third layer or the fourth layer comprises nitrogen.3. The nonvolatile memory element of claim 1 , wherein the third layer and the fourth layer comprise nitrogen.4. The nonvolatile memory element of claim 1 , wherein the one of the third layer or ...

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Номер записи: 53
19-12-2013 дата публикации

Methods for Forming Nickel Oxide Films for Use With Resistive Switching Memory Devices

Номер: US20130334491A1
Автор: Chiang Tony P., Lang Chi-I, Sun Zhi-Wen Wen, Tong Jinhong
Принадлежит: Intermolecular Inc.

Methods for forming a NiO film on a substrate for use with a resistive switching memory device are presenting including: preparing a nickel ion solution; receiving the substrate, where the substrate includes a bottom electrode, the bottom electrode utilized as a cathode; forming a Ni(OH)film on the substrate, where the forming the Ni(OH)occurs at the cathode; and annealing the Ni(OH)film to form the NiO film, where the NiO film forms a portion of a resistive switching memory element. In some embodiments, methods further include forming a top electrode on the NiO film and before the forming the Ni(OH)film, pre-treating the substrate. In some embodiments, methods are presented where the bottom electrode and the top electrode are a conductive material such as: Ni, Pt, Ir, Ti, Al, Cu, Co, Ru, Rh, a Ni alloy, a Pt alloy, an Ir alloy, a Ti alloy, an Al alloy, a Cu alloy, a Co alloy, a Ru alloy, and an Rh alloy. 1. A resistive switching memory element , comprising:a first conductive layer;a nickel oxide layer formed on the first conductive layer; anda second conductive layer formed above the nickel oxide layer;wherein the first and second conductive layers are operable as electrodes;wherein a resistance of the nickel oxide layer is switchable between two different values by applying a voltage across the electrodes; andwherein the nickel oxide layer is formed by electrochemical deposition.2. The resistive switching memory element of claim 1 , wherein the first conductive layer comprises at least one of nickel claim 1 , platinum claim 1 , iridium claim 1 , titanium claim 1 , aluminum claim 1 , copper claim 1 , cobalt claim 1 , ruthenium claim 1 , rhenium claim 1 , or their alloys.3. The resistive switching memory element of claim 1 , wherein the first conductive layer is formed by at least one of physical vapor deposition claim 1 , chemical vapor deposition claim 1 , atomic layer deposition claim 1 , electrochemical plating claim 1 , or electroless deposition.4. The ...

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Номер записи: 54
19-12-2013 дата публикации

RESISTIVE MEMORY DEVICE AND MEMORY APPARATUS AND DATA PROCESSING SYSTEM HAVING THE SAME

Номер: US20130336042A1
Автор: Hong Kwon, KANG Se Hun, KU Ja Chun, Lee Keun
Принадлежит: SK HYNIX INC.

A resistive memory device operable with low power consumption and a memory apparatus and data processing system including the same are provided. The resistive memory includes a chalcogenide compound containing 10 to 60 wt % (atomic weight) of selenium (Se) or tellurium (Te). 1. A memory device , comprising:a lower electrode to be electrically connected an access device;a data storage node, including a variable resistive material layer, to be heated by the lower electrode, the variable resistive material layer comprising a chalcogenide compound comprising 10 to 60 wt % (atomic weight) of selenium (Se) or tellurium (Te); andan upper electrode connected to the data storage node.2. The memory device of claim 1 , where the chalcogenide compound further comprises:antimony (Sb), germanium (Ge), silicon (Si) tin (Sn), or indium (in), in combination with the Se or the Te.3. The memory device of claim 1 , where the chalcogenide compound further comprises:at least two of antimony (Sb), germanium (Ge), silicon (Si), tin (Sn), or indium (In), in combination with the Se or the Te.4. The memory device of claim 1 , where the chalcogenide compound further comprises:a tin-antimony-selenium (Sn—Sb—Se) compound, where an amount of the Sn is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Se is 10 to 60 wt %.5. The memory device of claim 1 , where the chalcogenide compound further comprises:a germanium-antimony-selenium (Ge—Sb—Se) compound, where an amount of the Ge is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt %, and an amount of the Se is 10 to 60 wt %.6. The memory device of claim 1 , where the chalcogenide compound further comprises:a tin-antimony-tellurium Sn—Sb—Te) compound, where an amount of the Sn is 1.0 to 25.5 wt %, an amount of the Sb is 10 to 90 wt % and an amount of the Te is 10 to 60 wt %.7. The memory device of claim 1 , where the chalcogenide compound further comprises:a silicon-antimony-tellurium (Si—Sb—Te) compound, where an ...

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Номер записи: 55
26-12-2013 дата публикации

RESISTIVE MEMORY AND FABRICATING METHOD THEREOF

Номер: US20130341583A1
Автор: CHIEN WEI-CHIH, LEE MING-HSIU
Принадлежит: MACRONIX INTERNATIONAL CO., LTD.

A resistive memory and a fabricating method thereof are provided. The resistive memory includes first and second electrodes, a variable resistance material layer, a first dielectric layer, and a second dielectric layer. The first electrode includes a first portion and a second portion. The second electrode is disposed opposite to the first electrode. The variable resistance material layer includes a sidewall and first and second surfaces opposite to each other, wherein the first surface is connected with the first portion of the first electrode and the second surface is electrically connected with the second electrode. The second portion surrounds the sidewall of the variable resistance material layer and is connected with the first portion. The first dielectric layer is disposed between the first and the second electrodes. The second dielectric layer is disposed between the variable resistance material layer and the second portion of the first electrode. 1. A resistive memory , comprising:a first electrode having a first portion and a second portion;a second electrode disposed opposite to the first electrode;a variable resistance material layer having a sidewall, a first surface, and a second surface opposite to the first surface, wherein the first surface of the variable resistance material layer is connected with the first portion of the first electrode, the second surface of the variable resistance material layer is electrically connected with the second electrode, and the second portion surrounds the sidewall of the variable resistance material layer and is connected with the first portion;a first dielectric layer disposed between the first electrode and the second electrode; anda second dielectric layer disposed between the variable resistance material layer and the second portion of the first electrode.2. The resistive memory according to claim 1 , wherein a material of the first portion is different from a material of the second portion claim 1 , and a ...

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Номер записи: 56
26-12-2013 дата публикации

Memory Structures, Memory Arrays, Methods of Forming Memory Structures and Methods of Forming Memory Arrays

Номер: US20130341586A1
Автор: Sills Scott E.
Принадлежит: MICRON TECHNOLOGY, INC.

Some embodiments include methods of forming memory structures. An electrically insulative line is formed over a base. Electrode material is deposited over the line and patterned to form a pair of bottom electrodes along the sidewalls of the line. Programmable material is formed over the bottom electrodes, and a top electrode is formed over the programmable material. The bottom electrodes may each contain at least one segment which extends at angle of from greater than 0° to less than or equal to about 90° relative to a planar topography of the base. Some embodiments include memory structures having a bottom electrode extending upwardly from a conductive contact to a programmable material, with the bottom electrode having a thickness of less than or equal to about 10 nanometers. Some embodiments include memory arrays and methods of forming memory arrays. 117-. (canceled)18. A memory structure , comprising:a bottom electrode extending upwardly from a conductive contact to programmable material;a top electrode over the programmable material; andwherein the bottom electrode has a thickness of less than or equal to about 10 nanometers.19. The memory structure of wherein the bottom electrode consists of titanium nitride.20. The memory structure of wherein the bottom electrode thickness is less than or equal to about 5 nanometers.21. The memory structure of wherein the bottom electrode thickness is less than or equal to about 3 nanometers.22. The memory structure of wherein the bottom electrode thickness is within a range of from about 1 nanometer to about 5 nanometers.23. The memory structure of wherein the conductive contact is within a base; wherein the bottom electrode extends substantially orthogonally relative to a planar topography of the base; and wherein the top electrode extends substantially parallel to the planar topography of the base.24. The memory structure of wherein the conductive contact is within a base; wherein the bottom electrode extends at an angle ...

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Номер записи: 57
02-01-2014 дата публикации

Reduction of forming voltage in semiconductor devices

Номер: US20140001431A1
Автор: Chiang Tony P., Kumar Pragati, Phatak Prashant B., Wang Yun
Принадлежит: Intermolecular Inc.

This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (ReRAM) approaches to provide a memory device with more predictable operation. In particular, the forming voltage required by particular designs may be reduced through the use of a barrier layer, a reverse polarity forming voltage pulse, a forming voltage pulse where electrons are injected from a lower work function electrode, or an anneal in a reducing environment. One or more of these techniques may be applied, depending on the desired application and results. 1. A memory cell comprising:a first conductive layer operable as an electrode;a second conductive layer operable as an electrode;a semiconductor layer between the first conductive layer and the second conductive layer; anda defect access layer between the first conductive layer and the semiconductor layer;wherein a work function of the first conductive layer is higher than a work function of the second conductive layer; andwherein the defect access layer increases an effective work function of the first conductive layer.2. The memory cell of claim 1 , wherein the first conductive layer comprises a non-noble material.3. The memory cell of claim 1 , wherein the first conductive layer comprises titanium nitride claim 1 , silicon claim 1 , or a silicide.4. The memory cell of claim 1 , wherein the defect access layer is less than about 50 Å thick.5. The memory cell of claim 1 , wherein the defect access layer is less than about 20 Å thick.6. The memory cell of claim 1 , wherein the defect access layer is less than about 25% as thick as the semiconductor layer.7. The memory cell of claim 1 , wherein the defect access layer comprises aluminum oxide.8. The memory cell of claim 1 , wherein the defect access layer contacts the semiconductor layer and the first conductive layer; and wherein the defect access layer promotes adhesion between the ...

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Номер записи: 58
23-01-2014 дата публикации

VARIABLE RESISTANCE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20140021432A1
Автор: LEE Sung-Hoon
Принадлежит: SK HYNIX INC.

A method for fabricating a variable resistance memory device includes forming an insulating layer having a trench extending in a first direction over a substrate, forming first electrode conductive layers on both sidewalls of the trench, forming island-shaped first electrodes by patterning the conductive layers in a second direction crossing the first direction, forming variable resistance patterns over the first electrodes, and forming second electrodes over the variable resistance patterns. 1. A method for fabricating a variable resistance memory device , comprising:forming an insulating layer having a trench extending in a first direction over a substrate;forming first electrode conductive layers on both sidewalls of the trench;forming island-shaped first electrodes by patterning the conductive layers in a second direction crossing the first direction;forming variable resistance patterns over the first electrodes; andforming second electrodes over the variable resistance patterns.2. The method of claim 1 , wherein the forming of the first electrode conductive layers comprises:forming a conductive material along the entire surface of a structure having the trench formed therein; andblanket-etching the conductive material.3. The method of claim 1 , further comprising claim 1 , after the forming of the first electrodes:forming an insulating material to cover a structure having the first electrodes formed therein; andperforming a planarization process until the first electrode is exposed.4. The method of claim 1 , wherein each of the variable resistance patterns has a larger width than each of the first electrodes in the first and second directions.5. The method of claim 4 , wherein the forming of the variable resistance patterns is performed by a mask and etch process.6. The method of claim 1 , wherein the forming of the variable resistance patterns and the forming of the second electrodes comprise:sequentially forming a variable resistance material layer and a ...

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Номер записи: 59
23-01-2014 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20140021436A1
Автор: YASUTAKE Nobuaki
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A memory cell comprises a diode layer, a variable resistance layer, a first electrode layer. The diode layer functions as a rectifier element. The variable resistance layer functions as a variable resistance element. The first electrode layer is provided between the variable resistance layer and the diode layer. The first electrode layer comprises a titanium nitride layer configured by titanium nitride. Where a first ratio is defined as a ratio of titanium atoms to nitrogen atoms in a first region in the titanium nitride layer and a second ratio is defined as a ratio of titanium atoms to nitrogen atoms in a second region which is in the titanium nitride layer and is nearer to the variable resistance layer than is the first region, the second ratio is larger than the first ratio. 120-. (canceled)21. A semiconductor memory device , comprising memory cells disposed between a first line and a second line and including a variable resistance element , the memory cells comprising:a first electrode layer provided between the variable resistance element and the first line,the first electrode layer including a titanium nitride layer configured by titanium nitride, and, when a first ratio is defined as a ratio of titanium atoms to nitrogen atoms in a first region in the titanium nitride layer and a second ratio is defined as a ratio of titanium atoms to nitrogen atoms in a second region which is in the titanium nitride layer and is nearer to the variable resistance element than is the first region, the second ratio being larger than the first ratio.22. The semiconductor memory device according to claim 21 , wherein the titanium nitride layer comprises:a first titanium nitride layer configured to have more nitrogen atoms than titanium atoms in a unit volume; anda second titanium nitride layer provided between the first titanium nitride layer and the variable resistance element and configured to have more titanium atoms than nitrogen atoms in a unit volume.23. The semiconductor ...

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Номер записи: 60
30-01-2014 дата публикации

VARIABLE RESISTIVE ELEMENT, AND ITS MANUFACTURING METHOD

Номер: US20140027703A1
Автор: Hosoi Yasunari, ISHIHARA Kazuya, NAKANO Takashi, Ohnishi Tetsuya, Shibuya Takahiro
Принадлежит: Xenogenic Development Limited Liability Company

A variable resistive element comprising a configuration that an area of an electrically contributing region of a variable resistor body is finer than that constrained by an upper electrode or a lower electrode and its manufacturing method are provided. A bump electrode material is formed on a lower electrode arranged on a base substrate. The bump electrode material is contacted to a variable resistor body at a surface different from a contact surface to the lower electrode. The variable resistor body is contacted to an upper electrode at a surface different from a contact surface to the bump electrode material. Thus, a cross point region between the bump electrode material (the variable resistor body) and the upper electrode becomes an electrically contributing region of the variable resistor body, and then an area thereof can be reduced compared with that of the region regarding the conventional variable resistive element. 1. A method comprising:depositing an electrode material onto a substrate to layer a first electrode film and form a lower electrode;forming a first insulating film on the lower electrode, wherein the first insulating film has an open portion at a top surface of the lower electrode;forming a bump electrode material contacting at least a partial region of the lower electrode and extending upward along an inner sidewall of the open portion;forming a variable resistor body at the bump electrode material; anddepositing an electrode material to layer a second electrode film and form an upper electrode.2. The method of claim 1 , wherein said forming a bump electrode material comprises:forming an electrode film for the bump electrode material by depositing an electrically-conductive material onto the open portion and the first insulating film;depositing a second insulating film onto the electrode film for the bump electrode material;removing the second insulating film until a top surface of the electrode film for the bump electrode material is exposed; ...

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Номер записи: 61
30-01-2014 дата публикации

METHODS OF FORMING PHASE-CHANGE MEMORY DEVICES AND DEVICES SO FORMED

Номер: US20140027704A1
Автор: HWANG Youngnam
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Phase-change memory devices are provided. A phase-change memory device may include a substrate and a conductive region on the substrate. Moreover, the phase-change memory device may include a lower electrode on the conductive region. The lower electrode may include a metal silicide layer on the conductive region, and a metal silicon nitride layer including a resistivity of about 10 to about 100 times that of the metal silicide layer. Moreover, the lower electrode may include a metal oxide layer between the metal silicon nitride layer and the metal silicide layer. The metal oxide layer may include a resistivity that is greater than that of the metal silicide layer and less than the resistivity of the metal silicon nitride layer. The phase-change memory device may also include a phase-change layer and an upper electrode on the lower electrode. 1. A phase-change memory device , comprising:a substrate;a conductive region on the substrate; a metal silicide layer on the conductive region;', 'a metal silicon nitride layer comprising a resistivity of about 10 to about 100 times that of the metal silicide layer; and', 'a metal oxide layer between the metal silicon nitride layer and the metal silicide layer, the metal oxide layer comprising a resistivity that is greater than that of the metal silicide layer and less than the resistivity of the metal silicon nitride layer; and, 'a lower electrode on the conductive region, the lower electrode comprisinga phase-change layer and an upper electrode on the lower electrode.2. The device of claim 1 , wherein a metal constituent of the metal oxide layer comprises a diffusion metal constituent of the a metal silicide layer diffused into the metal oxide layer.3. The device of claim 2 , wherein the metal oxide layer comprises at least one of a titanium oxide layer claim 2 , a tantalum oxide layer claim 2 , a tungsten oxide layer and a zirconium oxide layer. This U.S. non-provisional patent application is a divisional of and claims ...

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Номер записи: 62
13-02-2014 дата публикации

Resistive-Switching Nonvolatile Memory Elements

Номер: US20140042384A1
Автор: Barstow Sean, Chiang Tony P., Kumar Pragati, Malhotra Sandra G.
Принадлежит: Intermolecular Inc.

Nonvolatile memory elements including resistive switching metal oxides may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer. 1. A resistive switching nonvolatile memory element , comprising:a first conductive layer comprising a metal nitride;a second conductive layer; anda layer of non-stoichiometric metal oxide between the first conductive layer and the second conductive layer;wherein the first conductive layer contains a most prevalent metal;wherein the layer of non-stoichiometric metal oxide contains the most prevalent metal;wherein the layer of non-stoichiometric metal oxide is operable as a resistive switching layer;wherein the layer of non-stoichiometric metal oxide comprises a first sublayer and a second sublayer; andwherein the first sublayer and the second sublayer differ in material composition.2. The nonvolatile resistive switching memory element of claim 1 , wherein the most prevalent metal is selected from the group consisting of a transition metal claim 1 , Al claim 1 , Ti claim 1 , V claim 1 , Cr claim 1 , Mn claim 1 , Zr claim 1 , Nb claim 1 , Mo claim 1 , Hf claim 1 , Ta claim 1 , and W.3. The nonvolatile resistive switching memory element of claim 1 , wherein the first conductive layer and the second conductive ...

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Номер записи: 63
27-02-2014 дата публикации

RESISTIVE MEMORY DEVICE CAPABLE OF PREVENTING DISTURBANCE AND METHOD FOR MANUFACTURING THE SAME

Номер: US20140054537A1
Автор: HONG Sung Bin, KIM Myoung Sub, LEE Se Ho, Lee Seung Yun, PARK Hae Chan, SEO Jung Won
Принадлежит: SK HYNIX INC.

A resistive memory device capable of preventing disturbance is provided. The resistive memory device includes a lower electrode formed on a semiconductor substrate, a variable resistor disposed on the lower electrode, an upper electrode disposed on the variable resistor, and an interlayer insulating layer configured to insulate the variable resistor. The interlayer insulating layer may include an air-gap area in at least a portion thereof. 1. A resistive memory device , comprising:a lower electrode formed on a semiconductor substrate;a variable resistor disposed on the lower electrode;an upper electrode disposed on the variable resistor; andan interlayer insulating layer configured to insulate the variable resistor,wherein the interlayer insulating layer includes an air-gap area in at least a portion thereof.2. The resistive memory device of claim 1 , further comprising a spacer surrounding an outer circumference of the variable resistor.3. The resistive memory device of claim 2 , wherein the air-gap area is configured to surround the spacer.4. The resistive memory device of claim 2 , wherein the air-dap area is formed to have a width smaller than that of the spacer.5. The resistive memory device of claim 2 , wherein the air-dap area is formed to have a width larger than that of the spacer.6. The resistive memory device of claim 1 , further comprising a switching device disposed between the semiconductor substrate and the lower electrode.7. The resistive memory device of claim 6 , further comprising a protection spacer formed on a sidewall of the switching device.8. A resistive memory device claim 6 , comprising:a lower electrode formed on a semiconductor substrate;a first variable resistor disposed on the lower electrode;a spacer surrounding an outer circumference of the variable resistor;an upper electrode disposed on the variable resistor; andan air-gap area adjacent to the first variable resistor and configured to insulate the first variable resistor.9. The ...

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Номер записи: 64
06-03-2014 дата публикации

SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SAME

Номер: US20140061566A1
Автор: NODA Kotaro
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A semiconductor storage device according to an embodiment includes a first conductive layer, a variable resistance layer, an electrode layer, a first liner layer, a stopper layer, and a second conductive layer. The first liner layer is configured by a material having a property for canceling an influence of an orientation of a lower layer of the first liner layer, the property of the first liner layer being superior compared with that of the stopper layer. The stopper layer is acted upon by an internal stress in a compressive direction at room temperature. 1. A semiconductor storage device comprising:a first conductive layer;a variable resistance layer provided above the first conductive layer;an electrode layer contacting an upper surface of the variable resistance layer;a first liner layer contacting an upper surface of the electrode layer;a stopper layer contacting an upper surface of the first liner layer; anda second conductive layer provided above the stopper layer,the first liner layer being configured by a material having a property for canceling an influence of an orientation of a lower layer of the first liner layer, the property of the first liner layer being superior compared with that of the stopper layer, andthe stopper layer being acted upon by an internal stress in a compressive direction at room temperature.2. The semiconductor storage device according to claim 1 , whereinthe stopper layer is made of tungsten, andthe first liner layer is made of amorphous silicon or tungsten silicide.3. The semiconductor storage device according to claim 1 , whereinthe second conductive layer is acted upon by an internal stress in a compressive direction at room temperature.4. The semiconductor storage device according to claim 3 , further comprising a second liner layer between the stopper layer and the second conductive layer.5. The semiconductor storage device according to claim 4 , whereinthe second conductive layer is made of tungsten, andthe second liner layer ...

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Номер записи: 65
06-03-2014 дата публикации

NONVOLATILE MEMORY ELEMENT, NONVOLATILE MEMORY DEVICE, AND METHODS OF MANUFACTURING THE SAME

Номер: US20140061573A1
Автор: Mikawa Takumi, Murase Hideaki
Принадлежит: Panasonic Corporation

A nonvolatile memory element includes: a lower electrode formed above a substrate; a first variable resistance layer formed above the lower electrode and comprising a first metal oxide; a second variable resistance layer formed above the first variable resistance layer and comprising a second metal oxide having a degree of oxygen deficiency lower than a degree of oxygen deficiency of the first metal oxide; and an upper electrode formed above the second variable resistance layer. A single step is formed in an interface between the first variable resistance layer and the second variable resistance layer. The second variable resistance layer is formed to cover the step and have, above the step, a bend covering the step. The bend, seen from above, has only one corner in a surface of the second variable resistance layer. 120-. (canceled)21. A method of manufacturing a nonvolatile memory element , the method comprising:forming a lower electrode above a substrate;forming a first variable resistance layer above the lower electrode, the first variable resistance layer comprising a first metal oxide and having a single step in a surface;forming a second variable resistance layer to cover the step of the first variable resistance layer and have, above the step, a bend that covers the step, the second variable resistance layer comprising a second metal oxide having a degree of oxygen deficiency that is lower than a degree of oxygen deficiency of the first metal oxide; andforming an upper electrode above the second variable resistance layer,wherein in the forming of a first variable resistance layer, the step is formed so that the step is at most a single step and, as seen from above, has only one corner in the surface of the first variable resistance layer.22. The method of manufacturing a nonvolatile memory element according to claim 21 ,wherein in the forming of a first variable resistance layer, the step is formed so that, as seen from above, the corner of the step is ...

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Номер записи: 66
06-03-2014 дата публикации

Combinatorial Approach for Screening of ALD Film Stacks

Номер: US20140065788A1
Автор: Albert Lee, Jason Wright, Tony P. Chiang
Принадлежит: Intermolecular Inc

In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner.

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Номер записи: 67
20-03-2014 дата публикации

Methods For Selective Etching Of A Multi-Layer Substrate

Номер: US20140077147A1
Автор: Fulgenico Frederick Carlos, Shao ShouQian, Tong Jinhong
Принадлежит: Intermolecular Inc.

A method is disclosed for the selective etching of a multi-layer metal oxide stack comprising a platinum layer on a TiN layer on an HfOor ZrOlayer on a substrate. In some embodiments, the method comprises a physical sputter process to selectively etch the platinum layer, followed by a plasma etch process comprises CHFand oxygen to selectively etch the TiN, HfOor ZrOlayers with respect to the substrate. 1. A method for patterning a metal oxide stack comprising:etching a first layer using a physical sputter etch process, wherein the first layer is operable as a capping layer for the metal oxide stack, and wherein the first layer comprises platinum;{'sub': 2', '2', '3, 'etching a second layer and a third layer using a plasma etch process, wherein the third layer is disposed under the second layer, wherein the second layer is disposed under the first layer, wherein the second layer is operable as an electrode layer for the metal oxide stack, wherein the second layer comprises TiN, wherein the third layer is operable as a metal oxide layer for the metal oxide stack, wherein the third layer comprises HfOor ZrO, and wherein the plasma etch process comprises CHFand oxygen.'}2. A method as in wherein the physical sputter etch process comprises an RF power less than about 500 W.3. A method as in wherein the physical sputter etch process comprises an argon flow rate less than about 120 sccm.4. A method as in wherein the physical sputter etch process comprises an RF power about 250 W and an argon flow rate about 60 sccm.5. A method as in wherein the thickness of the capping layer is less than about 40 nm.6. A method as in wherein the plasma etch process comprises an RF power less than about 1000 W.7. A method as in wherein the plasma etch process comprises a CHFflow rate less than about 25 sccm claim 1 , and an Oflow rate less than about 12 sccm.8. A method as in wherein the plasma etch process comprises an argon flow rate less than about 120 sccm claim 1 , a CHFflow rate less ...

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Номер записи: 68
20-03-2014 дата публикации

RRAM CELL WITH BOTTOM ELECTRODE(S) POSITIONED IN A SEMICONDUCTOR SUBSTRATE

Номер: US20140077148A1
Автор: Liu Wenhu, Ng Chee Mang, Pey Kin-Leong, Raghavan Nagarajan
Принадлежит:

Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode. A method of making a resistance random access memory device is disclosed that includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device. 127.-. (canceled)28. A resistance random access memory device , comprising:a semiconducting substrate;a metal silicide top electrode positioned above said substrate;a single metal silicide bottom electrode formed at least partially in said substrate, wherein at least a portion of said single bottom electrode is positioned below an entire width of said top electrode; andat least one insulating layer positioned between said top electrode and said single bottom electrode, wherein the at least one layer of insulating material is adapted to breakdown when an operating voltage is applied to said top electrode so as to thereby allow formation of at least one conductive path that extends through said at least one layer ...

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Номер записи: 69
27-03-2014 дата публикации

METHOD, SYSTEM, AND DEVICE FOR PHASE CHANGE MEMORY SWITCH WALL CELL WITH APPROXIMATELY HORIZONTAL ELECTRODE CONTACT

Номер: US20140085974A1
Автор: Pellizzer Fabio, Tortorelli Innocenzo
Принадлежит: MICRON TECHNOLOGY, INC.

Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode. 1. A memory device , comprising: a selector;', 'an “L” shaped storage component; and', an approximately vertical portion;', 'a lower approximately horizontal leg portion, wherein the lower approximately horizontal leg portion is in contact with the electrode, and wherein the approximately vertical portion extends vertically from the lower approximately horizontal leg portion to an additional electrode positioned above the storage cell., 'an electrode positioned between the selector and the “L” shaped storage component, the electrode electrically coupling the selector and the “L” shaped storage component, the “L” shaped storage component comprising], 'a storage cell comprising2. The memory device of claim 1 , wherein a first width of the approximately vertical portion of the L-shaped storage component in a first direction is equal to about a thickness of a storage component material formed on an approximately vertical wall of a first trench formed in a dielectric material.3. The memory device of claim 2 , wherein a second width of the approximately vertical portion of the L-shaped storage component in a second direction is equal to about a distance between two adjacent additional trenches formed in one or more materials of the memory device claim 2 , wherein the first trench is substantially orthogonal to the two adjacent additional trenches.4. The memory device of ...

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Номер записи: 70
10-04-2014 дата публикации

Resistive memory device fabricated from single polymer material

Номер: US20140097395A1
Автор: Husam N. Alshareef, Mahmoud N. Almadhoun, Mohd Adnan KHAN, Unnat S. Bhansali
Принадлежит: Saudi Basic Industries Corp

A polymer-based device comprising a substrate; a first electrode disposed on the substrate; an active polymer layer disposed on and in contact with the first electrode; and a second electrode disposed on and in contact with the active polymer layer, wherein the first and the second electrodes are organic electrodes comprising a doped electroconductive organic polymer, the active polymer layer comprises the electroconductive organic polymer of the first and the second electrodes, and the first and the second electrodes have conductivity at least three orders of magnitude higher than the conductivity of the active polymer layer.

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Номер записи: 71
10-04-2014 дата публикации

MEMRISTIVE DEVICES AND MEMRISTORS WITH RIBBON-LIKE JUNCTIONS AND METHODS FOR FABRICATING THE SAME

Номер: US20140097398A1
Автор: Cho Hans S., Nickel Janice H., Yang Jianhua
Принадлежит:

Memristive devices, memristors and methods for fabricating memristive devices are disclosed. In one aspect, a memristor includes a first electrode wire and a second electrode wire. The second electrode wire and the first electrode wire define an overlap area. The memristor includes an electrode extension in contact with the first electrode wire and disposed between the first and second electrode wires. At least one junction is disposed between the second electrode wire and the electrode extension. Each junction contacts a portion of the electrode extension and has a junction contact area with the second electrode wire, and the sum total junction contact area of the at least one junction is less than the overlap area. 1. A memristor comprising:a first electrode wire;a second electrode wire, wherein the second electrode wire and the first electrode wire define an overlap area;an electrode extension in contact with the first electrode wire and disposed between the first and second electrode wires; andat least one junction, wherein each junction contacts a portion of the electrode extension and has a junction contact area with the second electrode wire such that the sum total junction contact area of the at least one junction is less than the overlap area between the first and second electrodes.2. The memristor of claim 1 , wherein the electrode extension further comprises a base in contact with the first electrode wire and at least one sidewall that extends from the base to a plane between the first and second electrode wires claim 1 , wherein the thickness of each sidewall defines the thickness of one of the at least one junctions.3. The memristor of claim 1 , wherein the electrode extension further comprises a base and at least one sidewall that extends from the base to a plane between the first and second electrode wires claim 1 , the base and the at least one sidewall in contact with the first electrode wire and the thickness of each sidewall defines the thickness ...

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Номер записи: 72
10-04-2014 дата публикации

PHASE CHANGE MEMORY STRUCTURES AND METHODS

Номер: US20140097399A1
Автор: Tang Sanh D.
Принадлежит: MICRON TECHNOLOGY, INC.

Methods, devices, and systems associated with phase change material memory are described herein. In one or more embodiments, a method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions. 119.-. (canceled)20. A memory cell , comprising:a first electrode;a phase change material, wherein the phase change material contacts the first electrode in an opening between a number of insulator regions, and wherein the contact area between the first electrode and the phase change material is defined by a distance between the number of insulator regions; anda second electrode, wherein the top electrode is over the phase change material.21. The memory cell of claim 20 , wherein the phase change material contacts the first electrode in a self-aligned opening between the number of insulator regions.22. The memory device of claim 20 , wherein the spacers are on the number of insulator regions and further define the distance between the number of insulator regions.23. The memory device of claim 20 , wherein the number of insulator regions include spacers with contoured surfaces.24. The memory device of claim 20 , wherein an amount of phase change material in the memory device is defined by the distance ...

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Номер записи: 73
01-01-2015 дата публикации

PHASE-CHANGE MEMORY CELLS

Номер: US20150001457A1
Автор: Krebs Daniel, Sebastian Abu
Принадлежит:

Phase-change memory cells for storing information in a plurality of programmable cell states. A phase-change component is located between first and second electrodes for applying a read voltage to the phase-change component to read the programmed cell state. The component includes opposed layers of phase-change material extending between the electrodes. A core component extends between the electrodes in contact with respective inner surfaces of the opposed layers. An outer component extends between the electrodes in contact with respective outer surfaces of the opposed layers. At least one of the core and outer component is formed of electrically-conductive material and is arranged to present, to a cell current produced by the read voltage, a lower-resistance current path than the amorphous phase of the phase-change material in any of said cell states. The current path has a length dependent on size of the amorphous phase in the opposed layers. 1. A phase-change memory cell for storing information in a plurality of programmable cell states , the memory cell comprising:a phase-change component, of phase-change material, located between a first and a second electrode for applying a read voltage to the phase-change component to read the programmed cell state, the phase-change component having opposed layers of said phase-change material extending between the first and second electrodes;a core component extending between the first and second electrodes in contact with respective inner surfaces of said opposed layers; andan outer component extending between the electrodes in contact with respective outer surfaces of said opposed layers,wherein at least one of the core component and the outer component is formed of an electrically-conductive material and is arranged to present, to a cell current produced by the read voltage, a lower-resistance current path than an amorphous phase of said phase-change material in any of said programmed cell states, said lower-resistance ...

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Номер записи: 74
01-01-2015 дата публикации

SELF-ALIGNED CROSS-POINT PHASE CHANGE MEMORY-SWITCH ARRAY

Номер: US20150001458A1
Автор: Kau DerChang, LEE Jong Won, Spadini Gianpaolo
Принадлежит:

Subject matter disclosed herein relates to a memory device, and more particularly to a self-aligned cross-point phase change memory-switch array and methods of fabricating same. 1. A memory device comprising:a plurality of substantially parallel memory structures, each of the plurality of substantially parallel memory structures comprising a phase change memory layer between a first memory electrode layer and a second memory electrode layer; anda plurality of substantially parallel switch structures over and intersecting with the plurality of substantially parallel memory structures, each of the plurality of substantially parallel switch structures comprising a phase change switch layer,wherein the phase change switch layer extends to at least two memory cells of the memory device, andwherein the first memory electrode layer and the second memory electrode layer are located substantially at cross-points of the plurality of substantially parallel memory structures and the plurality of substantially parallel switch structures.2. The memory device of claim 1 , wherein the phase change memory layer is located substantially at cross-points of the plurality of substantially parallel memory structures and the plurality of substantially parallel switch structures.3. The memory device of claim 1 , wherein the plurality of substantially parallel switch structures and the plurality of substantially parallel memory structures are on horizontal levels between a first plurality of electrically conductive lines and a second plurality of electrically conductive lines claim 1 , wherein the first plurality of electrically conductive lines and the second plurality of electrically conductive lines are configured to interconnect memory cells of the memory device.4. The memory device of claim 3 , wherein the first plurality of electrically conductive lines is in contact with the plurality of substantially parallel memory structures and comprises a first plurality of metal lines claim 3 , ...

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Номер записи: 75
01-01-2015 дата публикации

PHASE CHANGE MEMORY CELL WITH LARGE ELECTRODE CONTACT AREA

Номер: US20150001459A1
Автор: BrightSky Matthew J., Lam Chung H., LI Jing, Schrott Alejandro G., Sosa Cortes Norma E.
Принадлежит:

A phase change memory cell and a method for fabricating the phase change memory cell. The phase change memory cell includes a bottom electrode and a first non-conductive layer. The first non-conductive layer defines a first well, a first electrically conductive liner lines the first well, and the first well is filled with a phase change material in the phase change memory cell. A second non-conductive layer is deposited above the first non-conductive layer. A second well is defined by the second non-conductive layer and positioned directly above the first well. A second electrically conductive liner lines at least one wall of the second well such that the second electrically conductive liner is not in physical contact with the first electrically conductive liner. Furthermore, the phase change material is deposited in the second well. 1. A phase change memory cell comprising:a bottom electrode;a first non-conductive layer deposited above the bottom electrode;a first well defined by the first non-conductive layer and positioned directly above the bottom electrode;a first electrically conductive liner at least partially lining the first well such that the first electrically conductive liner is in electrical contact with the bottom electrode; anda phase change material deposited in the first well such that the phase change material is in electrical contact with the first electrically conductive liner;a second non-conductive layer deposited above the first non-conductive layer; anda second well defined by the second non-conductive layer and positioned directly above the first well;a second electrically conductive liner lining at least one wall of the second well such that the second electrically conductive liner is not in physical contact with the first electrically conductive liner; andwherein the phase change material is deposited in the second well.2. The phase change memory cell of claim 1 , further comprising:a top electrode; andwherein the first electrically ...

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Номер записи: 76
06-01-2022 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20220005869A1
Автор: Cho JungHyun, KIM Song Yi
Принадлежит:

A semiconductor memory device is disclosed. The device may include a device isolation layer in a substrate to define first and second active portions, a first contact on the substrate, first and second memory cells spaced apart from the first contact in a first direction by first and second distances, respectively, first and second conductive lines connected to the first and second memory cells, respectively, and extending in a second direction, and first and second selection transistors respectively connected to the first and second conductive lines. A length of a bottom surface of a first gate electrode of the first selection transistor overlapping the first active portion in a third direction may be different from a length of a bottom surface of a second gate electrode of the second selection transistor overlapping the second active portion in the third direction. 1. A semiconductor memory device , comprising:a device isolation layer provided in a substrate to define a first active portion and a second active portion;a first contact disposed on the substrate;a first memory cell and a second memory cell, which are spaced apart from the first contact in a first direction by a first distance and a second distance, respectively;a first conductive line connected to the first memory cell and extending in a second direction crossing the first direction;a second conductive line connected to the second memory cell and extending in the second direction;a first selection transistor connected to the first conductive line and including the first active portion; anda second selection transistor connected to the second conductive line and including the second active portion,wherein the first selection transistor comprises a first gate electrode crossing the first active portion in a third direction, the third direction being the same as or different from the second direction,the second selection transistor comprises a second gate electrode crossing the second active portion in ...

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Номер записи: 77
06-01-2022 дата публикации

LOW CURRENT RRAM-BASED CROSSBAR ARRAY CIRCUITS IMPLEMENTED WITH INTERFACE ENGINEERING TECHNOLOGIES

Номер: US20220006008A1
Автор: GE NING, Zhang Minxian
Принадлежит: TETRAMEM INC.

Interface engineering technologies relating to low current RRAM-based crossbar array circuits are disclosed. An apparatus, in some implementations, includes: a substrate; a bottom electrode formed on the substrate; a first geometric confining layer formed on the bottom electrode. The first geometric confining layer comprises a first plurality of pin-holes. The apparatus further comprises a base oxide layer formed on the first geometric confining layer and connected to a first top surface of the bottom electrode via the first pin-holes; and a top electrode formed on the base oxide layer. The base oxide layer comprises one of: TaO, HfO, TiO, ZrO, or a combination thereof; the first geometric confining layer comprises AlO, SiO, SiN, YO, GdO, SmO, CeO, ErO, or a combination thereof. 1. An apparatus comprising:a substrate;a bottom electrode formed on the substrate;a first geometric confining layer formed on the bottom electrode, wherein the first geometric confining layer comprises a first plurality of pin-holes;a base oxide layer formed on the first geometric confining layer and connected to a first top surface of the bottom electrode via the first pin-holes; and{'sub': x', 'x', 'x', 'x', '2', '3', '2', '3', '4', '2', '3', '2', '3', '2', '3', '2', '2', '3, 'a top electrode formed on the base oxide layer, wherein the base oxide layer comprises one of: TaO, HfO, TiO, ZrO, or a combination thereof, and wherein the first geometric confining layer comprises AlO, SiO, SiN, YO, GdO, SmO, CeO, ErO, or a combination thereof.'}2. The apparatus as claimed in claim 1 , wherein the base oxide layer is at least three times as thick as the first geometric confining layer.3. The apparatus as claimed in claim 1 , further comprising:a second geometric confining layer formed on the base oxide layer, wherein the second geometric confining layer comprises a second plurality of pin-holes, and the top electrode is formed on the second geometric confining layer and is connected to a second top ...

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Номер записи: 78
05-01-2017 дата публикации

Three-Dimensional Array of Re-Programmable Non-Volatile Memory Elements Having Vertical Bit Lines and a Single-Sided Word Line Architecture

Номер: US20170004881A1
Автор: Samachisa George, Yan Tianhong
Принадлежит:

A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. 1. A data memory , comprising:a plurality of non-volatile re-programmable memory elements arranged in a three dimensional pattern defined by rectangular coordinates along x, y and z directions and with a plurality of parallel planes stacked in the z direction on top of a semiconductor substrate;a plurality of first conductive lines elongated in the z direction through the plurality of planes and arranged in a two dimensional rectangular array of rows in the x direction and columns in the y-direction;a plurality of second conductive lines elongated in the x-direction across each of the planes and spaced apart in they-direction between and separated from the first plurality of conductive lines in each of the planes, wherein the first and second conductive lines cross adjacent each other at a plurality of locations across each of the planes, the plurality of second conductive lines forming pairs of adjacent second conductive lines, wherein each non-volatile re-programmable memory element is connected between a corresponding first conductive line and a corresponding second conductive line crossing each other at an associated location of the plurality of locations; anda plurality of select devices arranged to individually couple a selected row of first conductive lines to respective sensing circuits via a plurality of third conductive lines,wherein, for each of the pairs of adjacent second conductive lines, each second conductive line is connected to only one corresponding row of first conductive line such that both of the ...

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Номер записи: 79
05-01-2017 дата публикации

ELECTRONIC DEVICE

Номер: US20170005137A1
Автор: KIM Kyung-Wan
Принадлежит:

An electronic device may include a semiconductor memory. The semiconductor memory may include a stack in which a plurality of dielectric layers and a plurality of first electrodes are alternately stacked over a substrate in a vertical direction relative to the substrate; a hole pattern passing through the stack in the vertical direction and having a polygonal shape when viewed in a plan view; a plurality of second electrodes disposed on respective sidewalls of the hole pattern; and a plurality of variable resistance layers interposed between the plurality of second electrodes and the plurality of horizontal electrodes. 1. An electronic device including a semiconductor memory , the semiconductor memory comprising:a stack in which a plurality of dielectric layers and a plurality of first electrodes are alternately stacked over a substrate in a vertical direction relative to the substrate;a hole pattern passing through the stack in the vertical direction and having a polygonal shape when viewed in a plan view;a plurality of second electrodes disposed on respective sidewalls of the hole pattern; anda plurality of variable resistance layers interposed between the plurality of second electrodes and the plurality of horizontal electrodes.2. The electronic device of claim 1 , wherein the second electrodes extend in the vertical direction and contact the substrate.3. The electronic device of claim 1 , wherein the variable resistance layers include a transition metal oxide claim 1 , a perovskite-based material claim 1 , a phase change material claim 1 , a chalcogenide-based material claim 1 , a ferroelectric material claim 1 , or a ferromagnetic material.4. The electronic device of claim 1 , wherein the first electrodes and the second electrodes include any one transition metal or nitride selected from the group consisting of TiN claim 1 , Pt claim 1 , W claim 1 , TaN claim 1 , Ir claim 1 , Ni claim 1 , Cu claim 1 , Ta claim 1 , Ti claim 1 , Hf claim 1 , Zr claim 1 , and a ...

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Номер записи: 80
05-01-2017 дата публикации

ELECTRONIC DEVICE

Номер: US20170005138A1
Автор: KIM Kyung-Wan
Принадлежит:

An electronic device includes a semiconductor memory. The semiconductor memory includes a line-type first electrode layer having at least one protrusion and extending in a first direction, and a plurality of memory elements, each memory element including a variable resistance layer and a second electrode, the variable resistance layers of the memory elements being disposed over a top surface and two parallel side surfaces of the protrusion, respectively, the two parallel side surfaces of the protrusion being arranged in the first direction, the second electrodes of the memory elements being disposed over the variable resistance layers of the memory elements, respectively. 1. An electronic device comprising a semiconductor memory , the semiconductor memory comprising:a line-type first electrode layer having at least one protrusion and extending in a first direction; anda plurality of memory elements, each memory element comprising a variable resistance layer and a second electrode, the variable resistance layers of the memory elements being disposed over a top surface and two parallel side surfaces of the protrusion, respectively, the two parallel side surfaces of the protrusion being arranged in the first direction, the second electrodes of the memory elements being disposed over the variable resistance layers of the memory elements, respectively.2. The electronic device of claim 1 , wherein the first electrode comprises:a line-type body part extending in the first direction; anda plurality of protrusions arranged over the line-type body part so as to be spaced away from each other at predetermined intervals in the first direction.3. The electronic device of claim 2 , wherein each of the variable resistance layers of the memory elements that are disposed over the two parallel side surfaces of the protrusion further includes an additional portion extending along a top surface of the line-type body part in the first direction by a predetermined width from a ...

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Номер записи: 81
05-01-2017 дата публикации

ELECTRONIC DEVICE

Номер: US20170005139A1
Автор: Lee Tae-Young
Принадлежит:

This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes a semiconductor memory, and the semiconductor memory includes a variable resistance structure including a material having a resistance that is changed by formation or dissipation of conductive filaments; and a Magnetic Tunnel Junction (MTJ) structure inserted in the variable resistance structure and comprising a first magnetic layer having a pinned magnetization direction, a second magnetic layer having a variable magnetization direction, and a tunnel dielectric layer interposed between the first magnetic layer and the second magnetic layer. 120-. (canceled)21. An electronic device , comprising: (1) a first variable resistance structure including a first material having a resistance that is changed by formation or dissipation of one or more conductive filaments or passages in the first material in response to a first control signal applied to the first material;', '(2) a Magnetic Tunnel Junction (MTJ) structure comprising a first magnetic layer having a pinned magnetization direction, a second magnetic layer having a variable magnetization direction, and a tunnel dielectric layer interposed between the first magnetic layer and the second magnetic layer, the MTJ structure being coupled to the first variable resistance structure by having the first magnetic layer in contact with the first variable resistance structure, wherein the MTJ structure exhibits a first MTJ resistance state when magnetizations of the first and second magnetic layers are parallel to each other and a second, different MTJ resistance state when magnetizations of the first and second magnetic layers are anti-parallel to each other; and', '(3) a second variable resistance structure including a second material having a resistance that is changed by formation or dissipation of one or more conductive filaments or passages in the second material in response to a second ...

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Номер записи: 82
05-01-2017 дата публикации

VARIABLE RESISTOR, NON-VOLATILE MEMORY DEVICE USING THE SAME, AND METHOD OF FABRICATING THEREOF

Номер: US20170005262A1
Автор: HWANG Cheol Seong, Yoon Jung Ho
Принадлежит:

Provided are a semiconductor technique, and more particularly, to a variable resistor, a non-volatile memory device using the same, and a method of fabricating the same. The variable resistor may include a first electrode including titanium (Ti); a second electrode for forming a Schottky barrier; and a stacked structure including an oxygen-deficient hafnium oxide film (HfO, 0 Подробнее

Номер записи: 83
05-01-2017 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Номер: US20170005264A1
Автор: MASUOKA Fujio, Nakamura Hiroki
Принадлежит:

The present invention provides a memory structure including a resistance-changing storage element, which enables a reset operation with a reset gate and in which cross-sectional areas of a resistance-changing film and a lower electrode in a current-flowing direction can be decreased. The semiconductor device of the present invention comprises a first pillar-shaped semiconductor layer, a gate insulating film formed around the first pillar-shaped semiconductor layer, a gate electrode made of a metal and formed around the gate insulating film, a gate line made of a metal and connected to the gate electrode, a second gate insulating film formed around an upper portion of the first pillar-shaped semiconductor layer, a first contact made of a second metal and formed around the second gate insulating film, a second contact which is made of a third metal and which connects an upper portion of the first contact to an upper portion of the first pillar-shaped semiconductor layer, a second diffusion layer formed in a lower portion of the first pillar-shaped semiconductor layer, a pillar-shaped insulating layer formed on the second contact, a resistance-changing film formed around an upper portion of the pillar-shaped insulating layer, a lower electrode formed around a lower portion of the pillar-shaped insulating layer and connected to the resistance-changing film, a reset gate insulating film that surrounds the resistance-changing film, and a reset gate that surrounds the reset gate insulating film. 1a seventh step of depositing a second interlayer insulating film, forming a contact hole, depositing a fourth metal and a nitride film,removing portions of the fourth metal and the nitride film on the second interlayer insulating film to form a pillar-shaped nitride film layer and a lower electrode in the contact hole, the lower electrode surrounding a bottom portion of the pillar-shaped nitride film layer and the pillar-shaped nitride film layer,etching back the second interlayer ...

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Номер записи: 84
13-01-2022 дата публикации

METHOD OF FORMING MULTI-BIT RESISTIVE RANDOM ACCESS MEMORY CELL

Номер: US20220013718A1
Автор: YANG PO-YU
Принадлежит: UNITED MICROELECTRONICS CORP.

A multi-bit resistive random access memory cell includes a plurality of bottom electrodes, a plurality of dielectric layers, a top electrode and a resistance layer. The bottom electrodes and the dielectric layers are interleaved layers, each of the bottom electrodes is sandwiched by the dielectric layers, and a through hole penetrates through the interleaved layers. The top electrode is disposed in the through hole. The resistance layer is disposed on a sidewall of the through hole and is between the top electrode and the interleaved layers, thereby the top electrode, the resistance layer and the bottom electrodes constituting a multi-bit resistive random access memory cell. The present invention also provides a method of forming the multi-bit resistive random access memory cell. 1. A method of forming a multi-bit resistive random access memory cell , comprising:sequentially forming a first dielectric layer, a first bottom electrode, a second dielectric layer, a second bottom electrode, a third dielectric layer, a third bottom electrode and a fourth dielectric layer on a layer;performing a first etching process to pattern the fourth dielectric layer, the third bottom electrode, the third dielectric layer, the second bottom electrode, the second dielectric layer, the first bottom electrode and the first dielectric layer to forma through hole in the first dielectric layer, the first bottom electrode, the second dielectric layer, the second bottom electrode, the third dielectric layer, the third bottom electrode and the fourth dielectric layer; andforming a resistance layer conformally covering a sidewall of the through hole and filling a top electrode in the through hole, thereby the multi-bit resistive random access memory cell being formed.2. The method of forming the multi-bit resistive random access memory cell according to claim 1 , wherein the steps of forming the resistance layer conformally covering the sidewall of the through hole and filling the top ...

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Номер записи: 85
13-01-2022 дата публикации

Low current rram-based crossbar array circuit implemented with switching oxide engineering technologies

Номер: US20220013720A1
Автор: Minxian Zhang, Ning Ge
Принадлежит: Tetramem Inc

Switching oxide engineering technologies relating to low current RRAM-based crossbar array circuits are disclosed. An apparatus, in some implementations, includes: a substrate; a bottom electrode formed on the substrate; a switching oxide stack formed on the bottom electrode. The switching oxide stack includes one or more base oxide layers and one or more discontinuous oxide layers alternately stacked; An apparatus further includes a top electrode formed on the switching oxide stack. The base oxide layer includes TaO x , HfO x , TiO x , ZrO x , or a combination thereof. The discontinuous oxide layer includes Al 2 O 3 , SiO 2 , Si 3 N 4 , Y 2 O 3 , Gd 2 O 3 , Sm 2 O 3 , CeO 2 , Er 2 O 3 , or the combination thereof.

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Номер записи: 86
13-01-2022 дата публикации

PLANAR RESISTIVE RANDOM-ACCESS MEMORY (RRAM) DEVICE WITH A SHARED TOP ELECTRODE

Номер: US20220013723A1
Автор: Dutta Ashim, Sharma Saumya, Yang Chih-Chao, Zhou Tianji
Принадлежит:

Embodiments of the present invention are directed to forming a planar Resistive Random Access Memory (RRAM) device with a shared top electrode. In a non-limiting embodiment of the invention, a first trench having a first width and a second trench having a second width less than the first width are formed in a dielectric layer. A bottom liner is formed on sidewalls of the first trench. The bottom liner pinches off the second trench. A top liner is formed on sidewalls of the bottom liner in the first trench. The top liner is formed such that a portion of the bottom liner at a bottommost region of the first trench remains exposed. The exposed portion of the bottom liner is removed, and a memory cell material is formed in the first trench. 1. A method for forming a semiconductor device , the method comprising:forming a first trench having a first width and a second trench having a second width less than the first width in a dielectric layer;forming a bottom liner on sidewalls of the first trench, the bottom liner pinching off the second trench;forming a top liner on sidewalls of the bottom liner in the first trench, the top liner formed such that a portion of the bottom liner at a bottommost region of the first trench remains exposed;removing the exposed portion of the bottom liner; andforming a memory cell material in the first trench.2. The method of claim 1 , wherein the top liner does not fill the second trench due to pinch off.3. The method of claim 2 , wherein an air gap is formed between the top liner and the bottom liner in the second trench.4. The method of claim 1 , wherein the first width is more than 10 nm and the second width is less than 10 nm.5. The method of claim 1 , wherein removing the exposed portion of the bottom liner comprises etching the bottom liner selective to the top liner.6. The method of claim 5 , wherein the top liner comprises a conductive material having etch selectivity with respect to a wet etch chemistry used to remove the exposed ...

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Номер записи: 87
07-01-2016 дата публикации

SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR PRODUCING THE SAME

Номер: US20160005792A1
Автор: HASE Takashi, Ikarashi Nobuyuki, Kawahara Jun, TAKEUCHI Kiyoshi, Ueki Makoto
Принадлежит:

Provided is a semiconductor memory device (resistance random access memory element) improved in properties. A Ru film is formed as a film of a lower electrode by sputtering, and a Ta film is formed thereonto by sputtering. Next, the Ta film is oxidized with plasma to oxidize the Ta film. In this way, a compound TaOis produced and further Ru is diffused into the compound to form a layer (variable resistance layer) in which Ru is diffused into the compound TaO. Such an incorporation of a metal (such as Ru) into a transition metal oxide TMO (such as TaO) makes it possible to form electron conductive paths additional to filaments to lower the filaments in density and thickness. Thus, the memory element can be restrained from undergoing OFF-fixation, by which the element is not easily lowered in resistance, to be improved in ON-properties. 1. A semiconductor memory device , comprising:a first electrode;a second electrode; anda variable resistance layer arranged between the first and second electrodes;wherein the variable resistance layer comprises an oxide layer of a first metal, and a second metal contained in the oxide layer of the first metal,wherein the first metal is a transition metal; andwherein the second metal is a metal that produces an electronic level inside a band gap of the oxide layer of the first metal.2. The semiconductor memory device according to claim 1 ,{'sub': 2', '5', '2', '2, 'wherein the oxide layer of the first metal comprises at least one selected from the group consisting of TaO, ZrO, and HfO.'}3. The semiconductor memory device according to claim 2 ,wherein the second metal is selected from the group consisting of Ru, Re, Ir, Os, and Nb.4. The semiconductor memory device according to claim 3 ,wherein the content by percentage of the second metal is from 1 to 20% by atom of the first metal in the oxide layer of the first metal.5. The semiconductor memory device according to claim 1 ,wherein the variable resistance layer is over the first ...

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Номер записи: 88
07-01-2016 дата публикации

MEMORY ELEMENT WITH A REACTIVE METAL LAYER

Номер: US20160005793A1
Автор: CHEVALLIER CHRISTOPHE J., Hsia Steve Kuo-Ren, KINNEY WAYNE, Longcor Steven, RINERSON DARRELL, Sanchez John, SWAB PHILIP F.S., Ward Edmond R.
Принадлежит:

A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO-LSCoO or LaNiO-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays. 1. A re-writeable non-volatile memory device , comprising: a first terminal,', 'a second terminal,', 'a first layer of a conductive metal oxide (CMO), and', 'a second layer in direct contact with the first layer, the second layer and the first layer operative to store at least one-bit of data as a plurality of resistive states,, 'a re-writeable non-volatile two-terminal memory element (ME) comprising tantalum, the ME including'}the first and second layer are electrically in series with each other and with the first and second terminals.2. The re-writeable non-volatile memory device of claim 1 , wherein the first layer includes a first lattice structure and the second layer includes a second lattice structure that substantially matches the first lattice structure.3. The re-writeable non-volatile memory device of claim 1 , wherein the direct contact between the first layer and the second layer is operative to impart a non-linear I-V characteristic to the ME.4. The re-writeable non-volatile memory device of claim 1 , wherein the ME includes a non-linear I-V characteristic for ...

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Номер записи: 89
07-01-2016 дата публикации

SEMICONDUCTOR DEVICE AND DIELECTRIC FILM

Номер: US20160005961A1
Автор: INO Tsunehiro
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a ferroelectric film or a ferrielectric film provided between the first conductive layer and the second conductive layer, the ferroelectric film or the ferrielectric film including hafnium oxide containing at least one first element selected from Zn, Mg, Mn, Nb, Sc, Fe, Cr, Co, In, Li and N. 1. A semiconductor device comprising:a first conductive layer;a second conductive layer; anda ferroelectric film or a ferrielectric film provided between the first conductive layer and the second conductive layer, the ferroelectric film or the ferrielectric film including hafnium oxide containing at least one first element selected from Zn, Mg, Mn, Nb, Sc, Fe, Cr, Co, In, Li and N.2. The device according to claim 1 , whereinthe hafnium oxide contains at least one second element selected from Si, Ti, Zr, Al, and Y.3. The device according to claim 2 , whereinthe second element is contained at 1 atom % or more and 5 atom % or less in the hafnium oxide.4. The device according to claim 1 , whereinthe first element is contained at 1 atom % or more and 10 atom % or less in the hafnium oxide.5. The device according to claim 1 , whereina compressive stress is applied in a thickness direction of the ferroelectric film or the ferrielectric film.6. The device according to claim 1 , whereinthe hafnium oxide includes third orthorhombic hafnium oxide.7. The device according to claim 1 , whereinthe first element is Zn, Mg, Mn, or Nb.8. The device according to claim 1 , whereinthe first element is Fe, Cr, Co, or In.9. The device according to claim 1 , whereinthe first element is N.10. A semiconductor device comprising:a first conductive layer;a second conductive layer; anda ferroelectric film or a ferrielectric film provided between the first conductive layer and the second conductive layer, the ferroelectric film or the ferrielectric film including hafnium oxide, a compressive ...

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Номер записи: 90
07-01-2016 дата публикации

Memory Cells, Methods of Forming Memory Cells and Methods of Forming Memory Arrays

Номер: US20160005962A1
Автор: Liu Jun, Zahurak John K.
Принадлежит:

Some embodiments include memory cells which have multiple programmable material structures between a pair of electrodes. One of the programmable material structures has a first edge, and another of the programmable material structures has a second edge that contacts the first edge. Some embodiments include methods of forming an array of memory cells. First programmable material segments are formed over bottom electrodes. The first programmable material segments extend along a first axis. Lines of second programmable material are formed over the first programmable material segments, and are formed to extend along a second axis that intersects the first axis. The second programmable material lines have lower surfaces that contact upper surfaces of the first programmable material segments. Top electrode lines are formed over the second programmable material lines. 19-. (canceled)10. A memory cell , comprising at least two programmable material structures directly between a pair of electrodes; a first of the programmable material structures having a first edge that extends primarily along a first axis; a second of the programmable material structures having a second edge that is directly against the first edge , and that extends primarily along a second axis that intersects the first axis; and wherein:the second programmable material structure is over the first programmable material structure;the first edge is an upper edge of the first programmable material structure;the second edge is a lower edge of the second programmable material structure;the second material structure has an upper edge in opposing relation to its lower edge;the memory cell includes a third programmable material structure that has a lower edge which is over the upper edge of the second programmable material structure;the third programmable material structure has an upper edge in opposing relation to its lower edge; andthe memory cell includes a fourth programmable material structure that has a ...

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Номер записи: 91
07-01-2016 дата публикации

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

Номер: US20160005963A1
Автор: KIM Seong-hyun
Принадлежит:

An electronic device includes a semiconductor memory that includes: an inter-layer dielectric layer including a hole over a substrate; a first nitride layer disposed on sidewalls of the hole; a selector disposed in a bottom portion of the hole and over the first nitride layer on the sidewalls of the hole; a stacked structure including a variable resistance pattern disposed over a lower structure including the selector; and a second nitride layer disposed in an upper portion and on sidewalls of the stacked structure. 1. An electronic device comprising a semiconductor memory that comprises:an inter-layer dielectric layer disposed over a substrate and including a hole therein;a first nitride layer disposed over sidewalls of the hole;a selector disposed over the bottom of the hole and over the first nitride layer in the hole;a stacked structure including a variable resistance pattern disposed over a lower structure including the selector; anda second nitride layer disposed over a top surface and sidewalls of the stacked structure.2. The electronic device according to claim 1 , wherein the semiconductor memory further comprises:a contact plug penetrating the inter-layer dielectric layer and contacting the substrate and disposed below the first nitride layer and the selector in the hole.3. The electronic device according to claim 1 , wherein the semiconductor memory further comprises:a conductive line disposed over the substrate and being in contact with the selector.4. The electronic device according to claim 1 , wherein the semiconductor memory further comprises:a conductive line disposed over the substrate; anda contact plug for coupling the conductive line to the selector.5. The electronic device according to claim 1 , wherein the second nitride layer has higher nitrogen density than the first nitride layer.6. The electronic device according to claim 1 , wherein the selector includes one among selection elements such as a Metal Insulator Transition (MIT) layer claim 1 ...

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Номер записи: 92
07-01-2016 дата публикации

SILICON BASED NANOSCALE CROSSBAR MEMORY

Номер: US20160005964A1
Автор: Jo Sung Hyun, Kim Kuk-Hwan, Lu Wei
Принадлежит:

The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials. 1. A semiconductor device comprising:a semiconductor substrate;a first array of electrodes disposed above the semiconductor substrate, wherein the first array of electrodes comprise a first metal-containing material, wherein the first metal is selected from a group consisting of: aluminum, nickel, platinum and tungsten;a second array of electrodes disposed above the first array of electrodes, wherein the second array of electrodes are oriented at an angle with respect to the first array of electrodes, wherein the first array of electrodes and the second array of electrodes overlap at a plurality of intersections, wherein the second array of electrodes comprises a second metal-containing material; anda plurality of resistive switching nanostructures disposed between the first array of electrodes and the second array of electrodes, wherein each resistive switching nanostructure provides a contact point between the first array of electrodes and the second array of electrodes at exactly one intersection from the plurality of intersections, wherein the plurality of resistive switching nanostructures comprises an undoped silicon-containing material having a number of defect sites; andwherein particles of the first metal derived from the first metal-containing material are diffused within defect sites of at least one resistive switching nanostructure from the plurality of resistive ...

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Номер записи: 93
07-01-2016 дата публикации

MEMORY CELLS HAVING A FIRST SELECTING CHALCOGENIDE MATERIAL AND A SECOND SELECTING CHALCOGENIDE MATERIAL AND METHODS THEROF

Номер: US20160005965A1
Автор: Redaelli Andrea
Принадлежит:

The present disclosure includes memory cells and methods of forming the same. The memory cells disclosed herein can include a first selecting chalcogenide material, a second selecting chalcogenide material, and a storage material. 1. A memory cell , comprising:a first selecting chalcogenide material;a second selecting chalcogenide material; anda storage material formed between the first selecting chalcogenide material the second selecting chalcogenide material.2. The memory cell of claim 1 , further comprising a first electrode material claim 1 , wherein the first selecting chalcogenide material is formed on a first electrode material.3. The memory cell of claim 2 , further comprising a second electrode material formed between the first selecting chalcogenide material and the storage material.4. The memory cell of claim 3 , further comprising a third electrode material formed between the second selecting chalcogenide material and the storage material.5. The memory cell of claim 4 , further comprising a fourth electrode material claim 4 , wherein the fourth electrode material is formed on the second selecting chalcogenide material.6. The memory cell of claim 1 , wherein the first selecting chalcogenide material has a thickness that is equal to a thickness of the second selecting chalcogenide material.7. The memory cell of claim 1 , wherein the first selecting chalcogenide material has a thickness that is greater than a thickness of the second selecting chalcogenide material.8. The memory cell of claim 1 , wherein the first selecting chalcogenide material has a thickness that is less than a thickness of the second selecting chalcogenide material.9. The memory cell of claim 1 , wherein the storage material comprises a storage chalcogenide material.10. The memory cell of claim 1 , wherein the first selecting chalcogenide material comprises a first material and the second selecting chalcogenide material comprises a second material that is a same material as the first ...

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Номер записи: 94
07-01-2016 дата публикации

APPARATUSES INCLUDING ELECTRODES HAVING A CONDUCTIVE BARRIER MATERIAL AND METHODS OF FORMING SAME

Номер: US20160005967A1
Автор: GOTTI ANDREA, LENGADE SWAPNIL A., MELDRIM JOHN M.
Принадлежит:

Apparatuses and methods of manufacture are disclosed for phase change memory cell electrodes having a conductive barrier material. In one example, an apparatus includes a first chalcogenide structure and a second chalcogenide structure stacked together with the first chalcogenide structure. A first electrode portion is coupled to the first chalcogenide structure, and a second electrode portion is coupled to the second chalcogenide structure. An electrically conductive barrier material is disposed between the first and second electrode portions. 1. A method of manufacturing a memory cell , comprising:forming a first chalcogenide structure;forming a first electrode portion over the first chalcogenide structure;forming an electrically conductive barrier material over the first electrode portion;forming a second electrode portion over the electrically conductive barrier material; andforming a second chalcogenide structure over the second electrode portion.2. The method of claim 1 , wherein the first chalcogenide structure claim 1 , the first electrode portion claim 1 , the barrier material claim 1 , the second electrode portion claim 1 , and the second chalcogenide structure together define a stack with a substantially uniform cross section.3. The method of claim 1 , wherein the electrically conductive barrier material has a larger cross section than at least one of the first and second electrode portions.4. The method of claim 1 , wherein the first chalcogenide structure is formed over a first access line and a first access line electrode is disposed between the first access line and the first chalcogenide structure.5. The method of claim 4 , further comprising forming a second access line electrode over the second chalcogenide structure and a second access line over the second access line electrode.6. The method of claim 1 , wherein the barrier material comprises silicon claim 1 , and the barrier material is formed in situ with the second electrode portion.7. The ...

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Номер записи: 95
07-01-2021 дата публикации

MEMORY DEVICE AND A METHOD FOR FORMING THE MEMORY DEVICE

Номер: US20210005251A1
Автор: TAN Juan Boon, Tan Shyue Seng, Toh Eng Huat, Wang Lanxiang
Принадлежит:

A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. Second, third, and fourth voltage lines may each be electrically coupled to a conductivity region. Resistive units may be arranged between the third voltage line and the conductivity region electrically coupled to the third voltage line, and between the fourth voltage line and the conductivity region electrically coupled to the fourth voltage line. A resistance adjusting element may have at least a portion arranged between one of the resistive units and one of the conductivity regions. An amount of the resistance adjusting element between the first resistive unit and the conductivity region electrically coupled to the third voltage line may be different from that between the second resistive unit and the conductivity region electrically coupled to the fourth voltage line. 1. A memory device comprising:a substrate comprising a first conductivity region and a second conductivity region at least partially arranged within the substrate, and a channel region arranged between the first conductivity region and the second conductivity region;a first voltage line arranged over the channel region;a second voltage line electrically coupled to the first conductivity region;a third voltage line electrically coupled to one of the conductivity regions; anda fourth voltage line electrically coupled to one of the conductivity regions;a first resistive unit arranged between the third voltage line and the conductivity region to which the third voltage line is electrically coupled, and a second resistive unit arranged between the fourth voltage line and the conductivity region to which the fourth voltage line is electrically coupled;a resistance adjusting element having at least a portion arranged between one of the resistive units and one of the conductivity regions;wherein an amount of the resistance adjusting element between the ...

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Номер записи: 96
02-01-2020 дата публикации

Phase change memory device with reduced read disturb and method of making the same

Номер: US20200005863A1
Автор: Michael Grobis, Ward Parkinson, Zhaoqiang BAI
Принадлежит: SanDisk Technologies LLC

A method of operating a phase change memory device includes flowing a write current of a first polarity through a phase change memory element of a selected phase change memory cell, and flowing a read current of a second polarity opposite to the first polarity through the phase change memory element of the selected phase change memory cell. A first junction between the phase change memory element and a first electrode and a second junction between the phase change memory element and a second electrode exhibit asymmetric thermoelectric heat generation during the step of flowing the write current.

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Номер записи: 97
04-01-2018 дата публикации

RESISTIVE RANDOM ACCESS MEMORY (ReRAM) DEVICE

Номер: US20180006088A1
Автор: Gibson Gary, Min Kyung, Sheng Xia
Принадлежит:

One example includes a resistive random access memory (ReRAM) device. The device includes a set of electrodes to receive a voltage. The device also includes a memristor element to at least one of store and readout a memory state in response to a current that flows through the ReRAM device in response to the voltage. The device further includes a selector element having a dynamic current-density area with respect to the voltage. 1. A resistive random access memory (ReRAM) device comprising:a set of electrodes to receive a voltage;a memristor element to at least one of store and readout a memory state in response to a current that flows through the ReRAM device in response to the voltage; anda selector element having a dynamic current-density area with respect to the voltage.2. The device of claim 1 , wherein the memristor element comprises a switching layer claim 1 , wherein the selector element comprises a resistive layer and a barrier layer claim 1 , each of the barrier layer and the resistive layer having the dynamic current-density area.3. The device of claim 2 , wherein the resistive layer and the barrier layer have a cross-sectional area with respect to an axis extending between the set of electrodes that is greater than at least one of a cross-sectional area of the switching layer and a floating electrode that interconnects the switching layer and the resistive layer.4. The device of claim 2 , wherein the set of electrodes comprises a first electrode that is separated from the resistive layer by the barrier layer claim 2 , wherein a portion of each of the first electrode claim 2 , the resistive layer claim 2 , and the barrier layer extend along an axial length parallel to the axis extending between the set of electrodes relative to remaining respective portions of each of the first electrode claim 2 , the resistive layer claim 2 , and the barrier layer claim 2 , such that the portion of the barrier layer interconnects the portion of the first electrode and the ...

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Номер записи: 98
04-01-2018 дата публикации

MEMORY DEVICE

Номер: US20180006216A1
Автор: ASAO Yoshiaki, KAMATA Yoshiki, KUNISHIMA Iwao, Morota Misako
Принадлежит:

A memory device according to an embodiment includes a first conductive layer, a second conductive layer, a third conductive layer intersecting the first conductive layer and the second conductive layer, and a resistance change layer including a first region which is provided between the first conductive layer and the third conductive layer and has a superlattice structure, a second region which is provided between the second conductive layer and the third conductive layer and has the superlattice structure, and a third region which is provided between the first region and the second region. The third region includes at least one element selected from the group consisting of O, F, C, P, B, N, H, Bi, Cd, Zn, Ga, Se, Al, S, Be, In, and Pb. Concentration of the at least one element in the third region is higher than that in the first region and the second region. 1. A memory device comprising:a first conductive layer extending in a first direction;a second conductive layer extending in the first direction;a third conductive layer intersecting the first conductive layer and the second conductive layer, the third conductive layer extending in a second direction crossing the first direction; anda resistance change layer including a first region provided between the first conductive layer and the third conductive layer, a second region provided between the second conductive layer and the third conductive layer, and a third region provided between the first region and the second region, the first region having a superlattice structure, the second region having a superlattice structure, the third region including at least one element selected from the group consisting of oxygen (O), fluorine (F), carbon (C), phosphorous (P), boron (B), nitrogen (N), hydrogen (H), bismuth (Bi), cadmium (Cd), zinc (Zn), gallium (Ga), selenium (Se), aluminum (Al), sulfur (S), beryllium (Be), indium (In), and lead (Pb), concentration of the at least one element in the third region being higher ...

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Номер записи: 99
04-01-2018 дата публикации

MEMORY CELL STRUCTURES

Номер: US20180006218A1
Автор: Sills Scott E.
Принадлежит:

The present disclosure includes memory cell structures and method of forming the same. One such memory cell includes a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode, a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode, and a storage element between the first electrode and the electrode contact portion of the second electrode. 1. A memory cell , comprising:a first electrode having sidewalls angled less than 90 degrees in relation to a bottom surface of the first electrode;a second electrode, including an electrode contact portion of the second electrode, having sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode, wherein the second electrode is over the first electrode; anda storage element between the first electrode and the electrode contact portion of the second electrode.2. The memory cell of claim 1 , wherein an electrode contact portion of the second electrode has sidewalls angled less than 90 degrees in relation to the bottom surface of the first electrode.3. The memory cell of claim 1 , wherein the first electrode has a trapezoidal cross-sectional area and sidewalls that are selected from the group consisting of straight claim 1 , concave claim 1 , or convex.4. The memory cell of claim 3 , wherein a top surface of the trapezoidal cross-sectional area of the first electrode is an electrode contact portion of the first electrode and is in contact with the storage element.5. The memory cell of claim 1 , wherein the first electrode has a triangular cross-sectional area and sidewalls that are selected from the group consisting of straight claim 1 , concave claim 1 , or convex.6. The memory cell of claim 1 , wherein the storage element includes a resistance variable ...

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Номер записи: 100