Аналого-цифровой преобразователь

Изобретение относится к измерительной технике, в частности к аналого-цифровым преобразователям, и может быть использовано в цифровых системах для измерения и контроля аналоговых величин. Технический результат заключается в расширении функциональных возможностей, повышении точности и быстродействия и снижении сложности схемы. Расширение функциональных возможностей заключается в обеспечении возможности аналого-цифрового преобразования не только однополярных положительных, но также однополярных отрицательных и двуполярных сигналов. Устройство содержит: делитель опорного напряжения; М мультиплексоров; М компараторов напряжения; регистр; генератор тактовых импульсов; триггер; формирователь кодов, блок определения знака и инвертирования отрицательных напряжений, в состав которого входят аналоговый инвертор, компаратор, два аналоговых ключа. 5 ил., 1 табл.

Anordnung und Verfahren zur Analog-Digital-Wandlung

Der Erfindung, welche eine Anordnung und ein Verfahren zur Analog-Digital-Wandlung betrifft, liegt die Aufgabe zugrunde, ein Verfahren und eine zugehörige Schaltungsanordnung anzugeben, womit eine Wandlung einer oder mehrerer Eingangsspannungen mittels einer einstellbaren oder auswählbaren Wandlerkennlinie erreicht und der Einfluss von Fertigungstoleranzen oder alterungsbedingter Veränderungen innerhalb der analogen Grundbestandteile verringert wird. Diese Aufgabe wird anordnungsseitig dadurch gelöst, dass der erste Eingang mit einer ersten und einer zweiten Eingangs-Wandlerstufe verbunden ist, dass die Ausgänge der Wandlerstufen jeweils mit einem Eingang einer nachgeschalteten Pulsregistrierungsanordnung verbunden sind, dass die Ausgänge der Pulsregistrierungsanordnung mit je einem Eingang eines Zählers oder Flankendetektors verbunden sind, dass die Ausgänge der Zähler oder Flankendetektoren mit einer gemeinsamen Summationsstufe verbunden sind, dass der Ausgang der Summationsstufe mit ...

Analog/digital conversion device

According to the analog/digital conversion device of the invention, an auxiliary circuit (11, 12, 97) is provided at the junction of the sampling capacitance (90) and the invertor (93), with the result that the potential at the junction reaches the terminal potential at high speed; this is similar to a switching device which is set such that the voltage can be applied by a source voltage. The conversion accuracy is thus not impaired and the analog/digital conversion time is shortened, even when the reference clock pulse (84a) is set to higher speeds. ...

Signalwandler und Verfahren zum Betreiben eines Signalwandlers

Die Erfindung bezieht sich auf einen Signalwandler und ein Verfahren zum Betreiben eines Signalwandlers, mit: Durchführen einer Analog-Digital-Wandlung eines analogen Eingangssignals, was das Vergleichen des analogen Eingangssignals mit einem analogen Vergleichssignal umfasst; Ermitteln, ob das analoge Eingangssignal eine vorgegebene maximale oder minimale Schwelle übersteigt, was das Vergleichen des analogen Eingangssignals mit einem analogen Schwellensignal umfasst; wobei das analoge Vergleichssignal und das analoge Schwellensignal durch denselben Digital-Analog-Wandler erzeugt werden.

Reference voltage circuit allowing fast power-up

A reference voltage circuit, e.g. for an integrated circuit analog-to-digital converter, includes a band gap circuit 2, and a first field effect transistor 4 coupling the band gap circuit 2 to a bypass capacitor 5. A second field effect transistor 7 couples the capacitor 5 to a non-inverting input 9 of the buffer circuit 8. Transistors 4, 7 are turned on, e.g. during conversations, during which time the first transistor 4 and the capacitor 5 coact to filter high frequency noise produced by the band gap circuit 2, and to apply a precise reference voltage to the non-inverting input 9 of the buffer circuit 8. The transistors 4, 7 are turned off during power down to isolate the capacitor 5 and preserve its charge, so that the capacitor does not need to be charged up when the transistors 4, 7 are turned back on. A second bypass capacitor and third and fourth field effect transistors may be used at the output of the buffer circuit 8 to produce a reference voltage (see Fig. 2). ...

ANALOGUE SIGNAL PROCESSING SYSTEM

... 1,253,978. Analog/digital converter. MICRO CONSULTANTS Ltd. 11 Nov., 1969 [20 Nov., 1968], no. 54996/68. Heading G4H. In an analogue/digital converter of the type in which the unknown analogue input current I 0 is successively modified by subtracting reference currents I 1 , I 3 , I 5 a current detector detects the direction of flow of current after each modification and controls the application of a current I 2 (equal to I 1 ), I 4 (equal to I 3 ) if the flow is negative. Each detector also supplies a digital output bit in accordance with the direction of current flow. In the embodiment of Fig. 1 I 1 = 2I 3 = 4I 5 so that the output is binary coded. A binary coded output may also be obtained by using equal current sources and feeding the current through an amplifier of gain 2 before each modification (Fig. 4, not shown). The currents I 2 , I 4 are fed via transistor or diode switches controlled by the current detectors 1, 2 which are preferably differential amplifiers.

ADC circuitry

Multiple-path analogue to digital converters are known. The present invention relates to a multi-path ADC circuitry in which the paths may operate as independent converters. An ADC circuit 200 has first and second conversion paths 201a, 201b for converting analogue signals to digital and is operable in first and second modes. In the first mode, the first and second conversion paths are connected to respective first and second input nodes 202a, 202b to receive and convert full scale first and second analogue input signals Ain1, Ain2 to separate digital outputs Dout1, Dout2. In the second mode, the first and second conversion paths are both connected to the first input node 202a, to convert the first analogue input signal Ain1 to respective first and second digital signals, and the first and second conversion paths are configured for processing different signal levels of the first analogue input signal. A selector 207 selects the first digital signal or the second digital to be output as ...

ELECTRONIC CONTROL DEVICE

Coding equipment for p.c.m. systems

... 1,109,048. Analogue to digital converters. STANDARD TELEPHONES & CABLES Ltd. 21 June, 1966, No. 27602/66. Heading G4H. In a P.C.M. system the coder comprises a plurality of bi-stable coding elements, 1-64, each having a different weight, means (junction A) for generating a signal representing the difference between the analogue value and the sum of the weights of those coding elements set, a bi-stable feedback element set when the analogue signal is exceeded to generate a feedback signal, and means for applying the difference signal and the feedback signal (if any) with the correct polarity to the coding elements. A damped oscillatory waveform is superimposed on the combined difference and feedback signal and the coding elements set sequentially until a balance is reached. The signal from the feedback element, which appears when the analogue input is exceeded, is applied to the inverted difference signal at B so that some of the lower-valued elements are switched off. The difference signal ...

High speed optical analogue to digital converter and digital optical wavemeter

METHOD AND APPARATUS FOR CONVERTING SPECTRAL AND LIGHT INTENSITY VALUES

ANALOG MULTI-RESPONSE TESTER

Elektrische Anlage zur störungsfreien und formgetreuen Übertragung von Wellen, insbesondere zum Fernsprechen.

Apparat zur Umwandlung von Ziffernkode-Signalen in Signale entsprechender Amplitude

Analog-Digital-Wandler

Measurement of average value of electric signal - is effected by integrating output of voltage to frequency counter

The average value of an electrical signal may be obtained by converting it to a frequency and integrating to obtain the value with practically no error. A voltage to be measured is applied to the input of a voltage to frequency converter (1) whose frequency output passes to a gate (2) controlled by the frequency divided (7) output of an oscillator (6). The gate output is frequency counted (3) during the time the gate is open. The counter input corresponds to the sum of the periods and to the integral of the signal input voltage. This is divided by the time period to obtain and display (4) the average value. Periodic inputs are synchronised with the oscillator frequency by using a divider (9) and a second counter (11) with display (12).

Décodeur non linéaire

Einrichtung zur Umwandlung von digitalen Signalen in positive und negative Strom- bzw. Spannungswerte

Strahleinstellvorrichtung

Signal sensing circuit

A signal sensing circuit converts a received current input into a voltage output and provides the voltage output to an analog-to-digital converter (ADC) to generate a digital output signal. The voltage output is associated with a circuit having a first reference impedance, and a reference voltage of the ADC is associated with a circuit having a second reference impedance, wherein the circuit having the first reference impedance and the circuit having the second reference impedance are formed by the same material, so that the ratio between the changes in the current input and the changes in the value of the digital output signal is a constant.

DEVICE OF CODING HAS INTERPOLATION

DIGITAL MAGNETO-OPTICAL CURRENT-MEASURING INSTRUMENTS

Device of installation of beam for cathode rays

Analogical-in-numerical converter

Device of translation of information intended for the conversion of numerical information

Process and apparatus for the analog-to-digital translation of measurements or telemetries

Device for the production of a modulation in code of pulsations

Improvements with the systems of restitution per cathode-ray tube

numerical scale coded in the shape of rule or disc, for the ordering of the machines operators

ANALOGUE TO DIGITAL CONVERTER

DEVICE OF CODING HAS INTERPOLATION

Comparator circuit, a/d conversion circuit, and display device

Disclosed is a comparator circuit having: a first switch unit that selectively picks up a signal voltage; a second switch unit that selectively picks up a control waveform; a differential amplifier, the non-inverting input terminal of which is connected to the output terminals of the first switch unit and the second switch unit; a capacitance unit, one terminal of which is connected to the inverting input terminal of the differential amplifier, and the other terminal of which is supplied with a reference voltage; and a third switch unit that selectively provides a short-circuit between the inverting input terminal and the output terminal of the differential amplifier.

MULTIPLEXERINGSANORDNING

Voltage level detection circuit and voltage level detection method

In the circuit for detecting the voltage level of an analog signal, a conversion circuit converts an analog signal to digital signals by comparing the voltage level of the analog signal with a plurality of reference potentials. A filter circuit matches timings of at least either rising edges or falling edges of the digital signals with each other. This prevents malfunction in the voltage level detection.

CURRENT INJECTION FOR FAST RAMP START-UP DURING ANALOG-TO-DIGITAL OPERATIONS

An example method for fast ramp start-up during analog to digital conversion (ADC) includes opening a feedback bypass switch coupled to an amplifier to initiate an ADC operation, providing an injection current pulse to an inverting input of the amplifier, where the non-inverting input is coupled to a feedback bypass switch, integrating a first reference current coupled to the inverting input of the amplifier, where the integrating of the first reference current occurs due to the opening of the feedback bypass switch, and providing a reference voltage in response to the injection current pulse, the integrating of the first reference current, and a reference voltage coupled to a non-inverting input of the amplifier, where a level of the reference voltage is increased at least at initiation of the ADC operation in response to the injection current pulse.

Digital-to-analog converter, analog-to-digital converter, and semiconductor device

A DA conversion device includes the following elements. A higher-bit current source cell portion includes uniformly weighted higher-bit current source cells to generate an identical constant current. A lower-bit current source cell portion includes a lower-bit current source cells that are weighted to generate 1/two-to-the-power-of-certain-numbers constant currents. A constant current source selection controller includes a lower-bit controller having a scaler that uses clocks scaled down to 1/two-to-the-power-of-certain-numbers to select the lower-bit current source cells, and a higher-bit controller having shift registers and using a signal indicating a carry bit or a borrow bit used in the lower-bit controller to sequentially activate shift outputs of the shift registers, and uses the shift outputs to select the higher-bit current source cells. Constant current outputs of the selected current source cells are added and output so that an output current corresponding to the digital input ...

Analog to digital converter with internal timer

An analog-to-digital converter includes circuitry for receiving an analog input and converting the input to a digital signal; and non-transitory control circuitry configured for: receiving a sampling time; receiving a conversion time; determining a power up time from at least one sleep mode; and causing the digital-to-analog converter to enter into the at least one sleep mode if the sum of the power up time and conversion time is less than the sampling time.

SMART ELECTRONIC SWITCH

A circuit may include an electronic switch that has a load current path coupled between an output node and a supply node and that is configured to connect or disconnect the output node and the supply node in accordance with a drive signal. Further, the circuit includes a monitoring circuit that is configured to receive a current sense signal, which represents the load current passing through the load current path, and that is further configured to determine a protection signal based on the current sense signal, a state of the monitoring circuit, and at least one wire parameter. The wire parameter characterizes a wire that is—during operation—connected to the output node, and the protection signal is indicative of whether to disconnect the output node from supply node. Further, the circuit includes a protection circuit connected to the monitoring circuit. 1. A circuit comprising:an electronic switch having a load current path coupled between an output node and a supply node and configured to connect or disconnect the output node and the supply node in accordance with a drive signal;a monitoring circuit configured to receive a current sense signal representing the load current passing through the load current path and to determine a protection signal based on the current sense signal, a state of the monitoring circuit, and at least one wire parameter that characterizes a wire operably connected to the output node, the protection signal being indicative of whether to disconnect the output node from the supply node; anda protection circuit connected to the monitoring circuit and configured to store the state of the monitoring circuit in one or more registers included in the protection circuit,wherein the protection circuit is configured to receive a logic supply potential at an input node, and includes a supply circuit configured to provide a temporary supply for the protection circuit when a supply potential received at an input node deviates from an internal supply ...

Analog-to-digital conversion circuit and method having quick tracking mechanism

The present invention discloses an analog-to-digital conversion circuit having quick tracking mechanism is provided. A positive and a negative capacitor arrays receive a positive and a negative input voltages and output a positive and a negative output voltages. A first and a second comparators performs comparison thereon respectively according to and not according to a reference voltage to generate a first and a second comparison results. A control circuit does not perform level-shifting when a difference between the positive and the negative output voltages is not within a predetermined range. The control circuit assigns the positive and the negative capacitor arrays a voltage up-tracking direction and a voltage down-tracking direction respectively to switch a capacitor enabling combination with digital codes according to the second comparison result, and outputs the digital codes as a digital output signal when the positive and the negative output voltages equal.

D=A converter for PCM signals - has input register and switched resistor network producing bipolar analog signals directly

Digital signal code words are converted into positive and negative currents or voltages at the receiver of a PCM communications network. A single shift register receives the words and a single resistance network produces the bipolar analog output signals. The network comprises series and shunt resistors. The shunt resistors in the network can each be switched to one of three reference voltages. The switches are controlled by the register via memories and gates.

ANALOG TO DIGITAL CONVERTER

VERGLEICHSSCHALTUNGSANORDNUNG

SYSTEM ZUR QUANTISIERUNG EINES ANALOGEN SIGNALS MIT EINER BRÜCKE VON DIODEN MIT RESONANTEM TUNNELEFFEKT

Improvements in or relating to electrical signalling systems

... 968,990. Pulse code modulation systems. BRITISH TELECOMMUNICATIONS RESEARCH Ltd. Aug. 23, 1961 [Aug. 23, 1960], No. 29138/60. Heading H4L. Hyperbolic encoding or decoding is effected, using a linear encoder or decoder, by varying the value of the comparison current or voltage supplied thereto in accordance with the signal input. Encoding. A signal current S2, Fig. 2, to be encoded is fed by a buffer circuit TR1, TR2, both to a transistor TR3 and to the linear encoder LE2. In combination with resistors R1, R2 the transistor TR3 determines the proportion of the signal current which is added to the reference (comparison) current supply SC before it is fed to the encoder. The circuit of Fig. 2 is suitable for inputs of one polarity only. For input signal currents of either polarity, Fig. 4, the input signal I passes through one or other of transistors VT1, VT2 depending on its polarity. VT1, if operative, reverses, with VT5, the direction of the current so that the signal current passed by ...

IMPROVEMENTS IN OR RELATING TO POSITIONAL DISPLACEMENT TRANSDUCER ARRANGEMENTS

... 1,205,554. Transducers. NATIONAL RESEARCH DEVELOPMENT CORP. 19 Dec., 1967 [22 Sept., 1966], No. 42391/66. Heading G4H. A multidigital encoder, mechanically coupled to a movable object and including for the least significant digit section an optical grating from which cyclic A.C. signals are derived, the zero closings of these signals controlling the subsequent interrogation of more significant digit sections of the encoder, generates an alarm signal if a change occurs in one of the digital sections when the next lower section is on a value at which it is inappropriate for a change to occur. In the embodiment described particularly for use in the transducers of Specifications 1,169,698 and 1,161,561, the 0, 4, 5, 9, outputs of each stage are connected via an OR gate G1, G4, G7 (Fig. 1) to an AND gate G2, G5, G8. Each AND gate also receives the output from an associated OR gate G3, G6, G9 receiving a signal when level detector W2, W3, W4 detects a change in the signal from encoder E2, E3, ...

SYSTEM FOR PROVIDING A DIGITAL REPRESENTATION OF AN ANALOGUE FREQUENCY OF AN UNKNOWN SIGNAL

... 1394551 Digital measurement of frequency BENDIX CORP 30 April 1973 20465/73 Heading G4H A circuit for measuring the frequency f x of a signal comprises a zero crossing detector 10, the period of the output of which varies with the frequency f x , gates 14, 18 for receiving a reference frequency signal, a flip-flop 12 for enabling the gates to transmit the reference frequency signal for the period of the detector 10 to counters 22, 24 and control gates 16, 20 for transferring the counts stored in the counters to a digital to analogue converter 26. The circuit may be part of a sonar system in which the signal of frequeney f x is the signal reflected from a moving object. The output pulses from the flip-flop 12 alternately open the pairs of gates 14, 16 and 18, 20 to supply the digital measurement of the frequency stored in the counters 22, 24 to the converter 26. The output of the converter may be supplied to a meter, Fig. 4 (not shown), via a low pass filter and to a comparator, the reference ...

SIGNAL TRANSFORMATION SYSTEM

Electric signalling systems

... 535,860. Radio signalling; valve circuits. STANDARD TELEPHONES & CABLES, Ltd. (Materiel Telephonique Soc. Anon.). Oct. 23, 1939, No. 28480.' [Class 40 (v)] [Also in Group XXXIX] A complex wave such as speech, is transmitted by arranging a finite number of graded predetermined amplitudes to cover the amplitude range, and transmitting the instantaneous amplitudes of the wave, at predetermined intervals, in the form of signals representing the nearest predetermined amplitude above or below said instantaneous amplitudes. In general, the signals comprise n different signal elements transmitted over each of m channels. The channels may comprise different carrier frequencies or may be obtained by using a distributer system, and the signal elements may comprise amplitude, frequency or phase modulation of the carrier, or impulses or intervals between impulses of different duration. The two embodiments described, comprise firstly a single channel system in which the signal elements consist of pulses ...

A is/d converter circuit with error correction

Die vorliegende Erfindung betrifft eine Schaltung zur Verarbeitung von zumindest einem Mess- oder Steuersignal insbesondere für einen Schaltregler (3) zum Betreiben von einem oder mehreren Leuchtmitteln (2), aufweisend einen Analog-Digital-Wandler (5) zum Wandeln eines analogen Mess- oder Steuersignals in ein digitales Mess- bzw. Steuersignal und zum Wandeln eines analogen Referenzsignals in ein digitales Referenzsignal, und eine Fehlerkorrektureinrichtung (6) zum Beseitigen oder Verringern eines bei der analog/digital Wandlung auftretenden Fehlers in dem digitalen Mess- bzw. Steuersignal auf der Grundlage einer Abweichung zwischen dem analogen Referenzsignal und dem digitalen Referenzsignal.

PROCEDURE AND SYSTEM FOR THE QUANTIZATION OF A SIMILAR SIGNAL WITH A CLOCKED PAIR DIODES WITH RESONANT TUNNEL EFFECT

CCD ANALOG TO DIGITAL CONVERTER

Ad (analog-to-digital) conversion circuit, micro-controller, and method of adjusting sampling time

An AD (analog-to-digital) conversion circuit includes a sample hold circuit configured to apply an analog input voltage input through an input terminal to a capacitor array formed of a plurality of capacitors so that the analog input voltage is accumulated in the capacitor array until a sampling time set is elapsed; a comparator circuit configured to sequentially retrieve the analog input voltage accumulated in each of the capacitors of the capacitor array, and to compare the analog input voltage with a reference voltage defined in advance to generate a digital signal; and a sampling time adjusting circuit configured to measure a period of time when a voltage on an input side of the sample hold circuit reaches a threshold value defined in advance relative to the reference voltage, and to set a time determined according to the period of time as the sampling time. Therefore, the circuit can an input impedance value automatically set the sampling time with an input impedance value varying ...

Digital indicator of the angular positions of trees whose maximum swing angle is lower than 360 U beg.

Optical sliding gauge for analog-to-digital converters

Encoder for pulse transmissions to frequency modulation

Parallel analogue-digital converter - for digital measurement of analogue electrical signals using series of comparators

Digital-to-analog converter with fiberoptics

Improvements in Successive Approximation Analogue to Digital Converters

Process of analogical data conversion into numerical data

Analogical device of storage

A method for converting under digital form, using contacts, the analogical angular position of a system of trees with mutual couplings kinematics and devices for the implementation of this process

UNITS HAS CHARGE-COUPLED DEVICES

Comparator circuit and analog to digital converter

A comparator circuit is applied to comparing an input voltage and a reference voltage to generate a comparison result. The comparator circuit includes a resistor circuit, a current-source circuit and a transistor-switching circuit. The resistor circuit receives first and second input voltages of the input voltage. The current-source circuit provides a first current and a second current, and the first current, the second current, and the resistor circuit generate the reference voltage. The transistor-switching circuit generates the comparison result at its output according to a first control voltage and a second control voltage at its input. The current-source circuit and the resistor circuit generate the first control voltage according to the first current and first input voltage, and generate the second control voltage according to the second current and the second input voltage.

COMPARATOR SYSTEM HAVING INTERNAL INPUT OFFSET VOLTAGE

Implementations of a comparator system may include a first transistor including a gate where the gate is configured to be coupled to a resistor-capacitor (RC) noise filter coupled to a resistor. The first transistor may be included in a PMOS differential pair. A first offset resistor may be coupled to the source of the first transistor and to a source of a second transistor included in the PMOS differential pair. A second offset resistor may be coupled between the first transistor and the second transistor. A voltage difference between a first back gate bias voltage of the first transistor and a second back gate bias voltage of the second transistor may indicate a current value through the resistor.

System and method for common mode calibration in an analog to digital converter

A conversion circuit increases a gain of an analog-to-digital converter (ADC) preamplifier by minimizing a common mode offset voltage between an input signal and a reference signal. The feedback controller circuit calibrates an input common mode voltage to mitigate a common mode offset voltage. Reduction of the common mode offset voltage increases the gain of the ADC preamplifier. In an example, the method is executed during a hold phase of a track-and-hold circuit that transmits the input signal to the ADC.

LATCH CIRCUIT, DOUBLE DATA RATE RING COUNTER BASED ON THE LATCH CIRCUIT, HYBRID COUNTING DEVICE, ANALOG-DIGITAL CONVERTING DEVICE, AND CMOS IMAGE SENSOR

Disclosed are a latch circuit receiving a negative output of a next stage latch circuit as a feedback input, a double data rate (DDR) ring counter based on the latch circuit to perform DDR counting of pulse periods and reduce the number of toggles, a hybrid counting device counting lower-bit portion by using the latch-based DDR ring counter and upper-bit portion by using a binary counter, and an analog-to-digital converting device and a CMOS image sensor employing the hybrid counting device. A double data rate ring counter may include a plurality of latches coupled in a ring type. The plurality of latches may include positive-edge-triggered latches and negative-edge-triggered latches arranged alternately. A current stage latch receives an output of a previous latch stage to shift to a next latch stage according to a counter clock, receives an output of the next latch stage to check a data shift to the next latch stage, and falls to a low level if the data shift is checked.

REPROGRAMMABLE QUANTUM PROCESSOR ARCHITECTURE INCORPORATING CALIBRATION LOOPS

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences ...

QUANTUM SHIFT REGISTER INCORPORATING BIFURCATION

A novel and useful controlled quantum shift register for transporting particles from one quantum dot to another in a quantum structure. The shift register incorporates a succession of qdots with tunneling paths and control gates. Applying appropriate control signals to the control gates, a particle or a split quantum state is made to travel along the shift register. The shift register also includes ancillary double interaction where two pairs of quantum dots provide an ancillary function where the quantum state of one pair is replicated in the second pair. The shift register also provides bifurcation where an access path is split into two or more paths. Depending on the control pulse signals applied, quantum dots are extended into multiple paths. Control of the shift register is provided by electric control pulses. An optional auxiliary magnetic field provides additional control of the shift register.

Common-mode insensitive sampler

An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node Vcmi. An alternative, switched-capacitor-based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi.

SINGLE SLOPE AD CONVERTER CIRCUIT PROVIDED WITH COMPARTOR FOR COMPARING RAMP VOLTAGE WITH ANALOG INPUT VOLTAGE

A single slope AD converter circuit includes a comparator that compares a ramp voltage varying with a predetermined slope as time elapses with an analog input voltage, a counter that counts a predetermined clock in parallel with the comparing process of the comparator, and a controller that outputs a clock count value corresponding to elapsed time when the ramp voltage is smaller than the analog input voltage, as an AD converted first digital value. The comparator compares the ramp voltage with a predetermined first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted second digital value. 1. A single slope AD converter circuit , comprising:a comparator configured to compare a ramp voltage varying with a predetermined slope as time elapses with an analog input voltage;a counter configured to count a predetermined clock in parallel with the comparing process of the comparator, anda controller configured to output a clock count value corresponding to elapsed time when the ramp voltage is smaller than the analog input voltage, as an AD converted first digital value, wherein(A) the comparator compares the ramp voltage with a predetermined first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted second digital value,(B) the comparator compares the ramp voltage with a predetermined second reference voltage different from the first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted third digital value, and(C) the controller divides one of a difference between the first and second digital values, and a difference between the first and third digital values, by a ...

Highly secure and extensive scan testing of integrated circuits

In one embodiment, an integrated circuit chip has an input/output (I/O) interface and programmable fabric. The I/O interface restricts access to scan testing of the chip by requiring (1) a specific scan-testing instruction, (2) a specific manufacturing key, and (3) a specific fabric pattern value from a specific set of registers in the programmed fabric. In addition or alternatively, the I/O interface has circuitry that enables scan testing of most of the logic of the I/O interface itself, including the logic being driven by the JTAG TAP state register.

АНАЛОГО-ЦИФРОВОЙ ПРЕОБРАЗОВАТЕЛЬ

Изобретение относится к вычислительной технике и может быть использовано при создании быстродействующих устройств обработки информации. Техническим результатом изобретения является повышение быстродействия преобразования в позиционный двоичный код электрических аналоговых сигналов. Такой результат обеспечивается за счет того, что аналого-цифровой преобразователь состоит из N-выходного делителя напряжения и (N+1) разрядных блоков, выходы которых являются выходами АЦП, при этом N-й разрядный блок содержит электронный ключ, блок вычитания, повторитель напряжения и компаратор в режиме нуль-индикации, а в каждый предшествующий ему разрядный блок введен еще один электронный ключ, при этом нулевой разрядный блок состоит из одного электронного ключа. 1 ил.

ANALAOGUI-TO-DIGITAL CONVERTERS AND DIGITAL-TO-ANALOGUE CONVERTERS

Multi-level quantizers and analogue-to-date-digital converters

Transducer

... 1,100,630. Magnetic storage apparatus. INTERNATIONAL BUSINESS MACHINES CORPORATION. 10 Nov., 1965 [25 Nov., 1964], No. 47598/65, Heading H3B. [Also in Division G3] A transducer comprises a core 32 of square loop permanent magnetic material surrounded by two coils which receive raise or lower pulses to cause a change in the remanent magnetism of the polepiece. An armature 65 is biased towards the polepiece by a spring 67 and between the armature and polepiece is a semiconductor pressure sensitive strain element 69. The pressure on the strain element is a function of the spring and the attraction between the armature and polepiece. The strain element is the active element of a bridge 47 so that the output at terminals 70, 71 is proportional to the permanent magnetism of polepiece 32.

SYSTEM FOR THE QUANTIZATION OF A SIMILAR SIGNAL WITH A BRIDGE OF DIODES WITH RESONANT TUNNEL EFFECT

PROCEDURE AND ARRANGEMENT FOR THE DIGITIZATION OF A TENSION

MORE QUANTISIERER, ENCODERS WITH SUCH QUANTISIERER AND SUCH A CONVERTER AN INTEGRATION OF ULTRABREITBANDEMPFÄNGER

ANALOG-TO-DIGITAL CONVERTER

ANALOGUE TO DIGITAL CONVERTERS

ANALOG TO DIGITAL CONVERTER

INTERPOLATIVE ENCODER FOR SUBSCRIBER LINE AUDIO PROCESSING CIRCUIT APPARATUS

IMAGING DEVICE COMPRISING A CIRCUIT FOR ANALOG-DIGITAL CONVERSION BY MEANS OF THE INJECTION OF A QUANTITY OF CHARGES THAT VARIES AS A FUNCTION OF THE NUMBER OF PREVIOUS INJECTIONS

L'invention se situe dans le domaine des dispositifs imageurs comprenant un détecteur (11) générant des charges électriques sous l'effet d'un rayonnement photonique incident, et un circuit de conversion analogique-numérique (12) formant des moyens de lecture de la quantité de charges électriques générée. Le circuit de conversion analogique-numérique (12) comprend : un comparateur (122) apte à basculer en fonction de la comparaison entre un potentiel (Va) sur un nud d'intégration (A) et un potentiel de seuil prédéterminé (Vseuil), un compteur (123) s'incrémentant à chaque basculement du comparateur, un circuit d'injection de contre-charges (124) injectant une quantité Qc de contre-charges sur le nud d'intégration (A) à chaque basculement du comparateur, et des moyens de commande (125) déterminant la quantité Qc de contre-charges injectée. Le circuit de conversion analogique-numérique (12) se caractérise en ce que les moyens de commande (125) déterminent la quantité Qc de contre-charges injectée ...

NARROWBAND ANALOG NOISE CANCELLATION

A method, including receiving an input analog signal containing noise at a specific noise frequency and digitizing the input analog signal to form a digitized signal. The method also includes recovering a first amplitude and a first phase of the noise from the digitized signal, and generating an analog correction signal at the specific noise frequency. The analog correction signal has a second amplitude equal to the first amplitude and a second phase opposite to the first phase. The method further includes summing the input analog signal with the analog correction signal to generate an output analog signal.

ANALOG-TO-DIGITAL CONVERTER

FET COMPARATOR CIRCUITRY

A comparator circuit for operation at video rate signals includes input switches to alternately couple a reference and a signal potential to a summing capacitor. The capacitor is coupled to the input of a first inverting amplifier. The amplifier includes a switch between input and output terminals for selectively autozeroing the amplifier. The amplifier is direct coupled to the input of a second inverting amplifier having an autozero circuit exclusive of a connection to the input of the second amplifier. Timing circuitry for controlling the autozero function is arranged to minimize the effects of clocking transients upsetting the autozeroed potentials thereby reducing the response time and enhancing the sensitivity of the comparator.

Voltage signal to time signal converter

Low-noise digital communication system - converts amplitudes into digital signals using clock pulse counter and comparator

Digital-To-Analog Converter

Nonlinear decoder with discontinuous characteristic

System of treatment of information

Improvements in or relating to Pulse Code Modulation Encoders and Decoders

The cumulative type Decoder

Measuring device of the distortion of the telegraphic signals

DIGITAL-TO-ANALOG CONVERTER, ANALOG-TO-DIGITAL CONVERTER, AND SEMICONDUCTOR DEVICE

A DA conversion device includes the following elements. A higher-bit current source cell portion includes uniformly weighted higher-bit current source cells to generate an identical constant current. A lower-bit current source cell portion includes a lower-bit current source cells that are weighted to generate 1/two-to-the-power-of-certain-numbers constant currents. A constant current source selection controller includes a lower-bit controller having a scaler that uses clocks scaled down to 1/two-to-the-power-of-certain-numbers to select the lower-bit current source cells, and a higher-bit controller having shift registers and using a signal indicating a carry bit or a borrow bit used in the lower-bit controller to sequentially activate shift outputs of the shift registers, and uses the shift outputs to select the higher-bit current source cells. Constant current outputs of the selected current source cells are added and output so that an output current corresponding to the digital input signal is obtained. 1. A digital-to-analog conversion device comprising:a higher-bit current source cell portion including a plurality of higher-bit current source cells that are uniformly weighted to generate an identical constant current;a lower-bit current source cell portion including a plurality of lower-bit current source cells that are weighted to generate constant currents which are 1/two-to-the-power-of-certain-numbers of the constant current generated by the higher-bit current source cells; anda constant current source selection controller operable to select the higher-bit current source cells of the higher-bit current source cell portion and the lower-bit current source cells of the lower-bit current source cell portion in accordance with a data value of a digital input signal,wherein the constant current source selection controller includes a lower-bit controller and a higher-bit controller, and the lower-bit controller includes a scaler that performs a scaling operation ...

AD CONVERSION CIRCUIT AND IMAGING APPARATUS

An AD conversion circuit includes a reference signal generation unit, which generates a reference signal, a comparison unit, which ends a comparison process at a timing at which the reference signal has satisfied a predetermined condition with respect to the analog signal, a first path in which a signal is transferred through each of n delay units, a clock signal generation unit, which outputs a lower-order phase signal, a latch unit, which latches the lower-order phase signal, a higher-order count unit including a first counter circuit, which acquires a higher-order count value by performing a count operation using a signal output from any one of the delay units, a calculation unit, which generates a lower-order count signal, and a lower-order count unit, which acquires a lower-order count value by performing the count operation using the lower-order count signal. 1. An analog-to-digital (AD) conversion circuit comprising:a reference signal generation unit configured to generate a reference signal that increases or decreases with the passage of time;a comparison unit configured to compare an analog signal serving as an AD conversion target with the reference signal and end a comparison process at a timing at which the reference signal has satisfied a predetermined condition with respect to the analog signal;a clock signal generation unit configured to have an oscillation circuit formed by n (n is an odd number greater than or equal to 3) delay units and including a first path in which a signal is transferred through each of the n delay units and a second path in which a signal is transferred by bypassing some of the n delay units, and output a lower-order phase signal including a plurality of signals output from the plurality of delay units;a latch unit configured to latch the lower-order phase signal at a timing related to the end of the comparison process;a higher-order count unit including a first counter circuit configured to acquire a higher-order count value ...

ANALOG-TO-DIGITAL CONVERTER

The present invention provides an analog-to-digital converter, which comprises an integration circuit, a threshold signal generating circuit, a main comparison circuit, a sub comparison circuit, a counter, and a decoder. The integration circuit integrates an input signal and produces an integration signal. The threshold signal generating circuit generates a main threshold signal and a plurality of sub threshold signals. The main comparison circuit produces a plurality of main comparison signals according the integration signal and the main threshold signal. The sub comparison circuit produces a plurality of sub comparison signals according to the integration signal and the plurality of sub threshold signals. The counter counts the plurality of main comparison signals and produces a first counting signal. The decoder decodes the plurality of sub comparison signals and produces a second count signal. The first count signal and the second count signal are used for producing a digital signal. 1. An analog-to-digital converter , comprising:an integration circuit, integrating an input signal for producing an integration signal;a threshold signal generating circuit, generating a main threshold signal and a plurality of sub threshold signals;a main comparison circuit, producing a plurality of main comparison signals according to said integration signal and said main threshold signal;a sub comparison circuit, producing a plurality of sub comparison signals according to said integration signal and said plurality of sub threshold signals;a counter, counting said plurality of main comparison signals for producing a first counting signal; anda decoder, decoding said plurality of sub comparison signals for producing a second counting signal;where said first counting signal and said second counting signal are used for producing a digital signal.2. The analog-to-digital converter of claim 1 , and further comprising:a latch, latching said first counting signal and said second ...

TIME DETECTION CIRCUIT, AD CONVERTER, AND SOLID STATE IMAGE PICKUP DEVICE

A time detection circuit may include: a delay unit configured to have a plurality of delay units, each of which delays and outputs an input signal, and start an operation at a first timing relating to an input of a first pulse; a latch unit configured to latch logic states of the plurality of delay units; a count unit configured to perform a count operation based on a clock output from one of the plurality of delay units; a count latch unit configured to latch a state of the count unit; and a latch control unit configured to enable the latch unit at a second timing relating to an input of a second pulse and cause the latch unit and the count latch unit to execute a latch at a third timing at which a predetermined time has elapsed from the second timing. 1. A time detection circuit comprising:a delay unit configured to have a plurality of delay units, each of which delays and outputs an input signal, and start an operation at a first timing relating to an input of a first pulse;a latch unit configured to latch logic states of the plurality of delay units;a count unit configured to perform a count operation based on a clock output from one of the plurality of delay units;a count latch unit configured to latch a state of the count unit; anda latch control unit configured to enable the latch unit at a second timing relating to an input of a second pulse and cause the latch unit and the count latch unit to execute a latch at a third timing at which a predetermined time has elapsed from the second timing.2. The time detection circuit according to claim 1 , wherein the delay unit is an annular delay circuit in which the plurality of delay units are connected in an annular shape.3. The time detection circuit according to claim 1 , further comprising:a comparison unit configured to receive an analog signal and a reference signal that increases or decreases with the passage of time and output a comparison signal when the reference signal has satisfied a predetermined ...

LASER OPTICAL TOUCH CONTROL MODULE ANALOG-TO-DIGITAL CONVERSION SYSTEM AND METHOD OF THE SAME

A laser optical touch control module includes a light emitting part with a laser light source and a light receiving part with a position sensor. A laser beam is emitted from the laser light source and reflected by a wide angle optical element. Thus a light fan of the reflected light is larger than 90 degrees to form a wide angle linear light beam. The position of a touch control widget is obtained by a sensor of the light receiving part that detects the linear light beam blocked and reflected by the touch control widget. An analog-to-digital conversion system includes a variable reference level generator that calculates to generate a variable reference level according to different variances. Then the sensor output data is converted into a digital signal based on the reference voltage level by a digital comparator and the digital signal is output to a processor. 2. The module as claimed in claim 1 , wherein the light path of the light emitting part and the light path of the light receiving part are arranged horizontally and transversely.3. The module as claimed in claim 1 , wherein the wide angle optical element is a line generator optics.4. The module as claimed in claim 1 , wherein the light emitting part and the light receiving part are mounted in a housing with an opening to form an assembly.5. The module as claimed in claim 1 , wherein a micro lens is disposed on a sensing surface of the position sensor so that the reflected laser beam formed due to the touch control widget in contact with surface of the display is concentrated on the sensing surface.6. A laser optical touch control module disposed on one side of a display for providing optical positioning input function to form an optical touch control display contacted by a touch control widget comprising a light emitting part and a light receiving part; whereina laser beam is emitted from a laser light source of the light emitting part and is reflected by a wide angle optical element so that a light fan of ...

ANALOG-DIGITAL CONVERTER, ANALOG-DIGITAL CONVERSION METHOD, IMAGE PICKUP DEVICE, METHOD OF DRIVING THE SAME, AND CAMERA

An analog-digital converter includes: comparators disposed to correspond to analog signals which are converted into digital signals and configured to compare a voltage value of the analog signal, which is converted into the digital signal, with a voltage value of a predetermined reference signal; counters disposed to correspond to the comparators and configured to count a count value at the time point when the comparison process of the corresponding comparator is finished; and a determiner configured to determine a time point when all the comparators finish their comparison processes. 116-. (canceled)17. An analog-digital converter comprising:comparators that compare a voltage value of an analog signal with a reference signal;counters that count a count value at a time point of a comparison process of a corresponding comparator;a voltage value storage that stores as a maximum voltage value a voltage value which is greater by a predetermined voltage than the voltage value of the analog signal having the maximum voltage value among analog signals converted into digital signals at a previous time and stores as a minimum voltage value a voltage value which is smaller by a predetermined voltage than the voltage value of the analog signal having the minimum voltage value among the analog signals converted into the digital signals at the previous time; anda reference signal generator that generates a down-count reference signal having as an initial voltage value the maximum voltage value stored in the voltage value storage or generates an up-count reference signal having as an initial voltage value the minimum voltage value stored in the voltage value storage.18. The analog-digital converter according to claim 17 , further comprising:a determiner configured to determine a time point when all the comparators finish their comparison processes.19. The analog-digital converter according to claim 17 , wherein each comparator compares a voltage value of the analog signal claim ...

COMPARATOR, ANALOG-TO-DIGITAL CONVERTOR, SOLID-STATE IMAGING DEVICE, CAMERA SYSTEM, AND ELECTRONIC APPARATUS

A comparator includes a first amplifier, a second amplifier, and a level holding part. The first amplifier includes differential-pair transistors and outputs a signal of a level corresponding to a comparison result from a first output node. The differential-pair transistors compare a reference voltage with a potential of an input signal. The second amplifier gain up the signal output from the first output node of the first amplifier and outputs the signal from a second output node. The level holding part holds a level of the second output node at a predetermined level. The second amplifier includes a transistor for amplification and a transistor for a current source. The level holding part holds the level of the second output node of the second amplifier such that the transistor for the current source does not fall into a level at which a saturated operation condition is not satisfied. 1. A comparator , comprising: 'the differential-pair transistors serving as a comparison part configured to compare a reference voltage with a potential of an input signal;', 'a first amplifier including differential-pair transistors and configured to output a signal of a level corresponding to a comparison result from a first output node,'}a second amplifier configured to gain up the signal output from the first output node of the first amplifier and output the signal from a second output node; and the second amplifier including', 'a transistor for amplification connected between the second output node and a power supply or a reference potential source and', 'a transistor for a current source connected between the second output node and the reference potential source or the power supply,', 'the level holding part holding the level of the second output node of the second amplifier such that the transistor for the current source of the second amplifier does not fall into a level at which a saturated operation condition is not satisfied., 'a level holding part configured to hold a level ...

AD (ANALOG-TO-DIGITAL) CONVERSION CIRCUIT, MICRO-CONTROLLER, AND METHOD OF ADJUSTING SAMPLING TIME

An AD (analog-to-digital) conversion circuit includes a capacitor array formed of a plurality of capacitors; a sample hold circuit configured to apply an analog input voltage input through an input terminal to the capacitor array so that the analog input voltage is accumulated in the capacitor array until a sampling time set is elapsed; a comparator circuit configured to sequentially retrieve the analog input voltage accumulated in each of the capacitors of the capacitor array, and to compare the analog input voltage with a reference voltage defined in advance to generate a digital signal; and a sampling time adjusting circuit configured to measure a period of time when a voltage on an input side of the sample hold circuit reaches a threshold value defined in advance relative to the reference voltage, and to set a time determined according to the period of time as the sampling time. 1. An AD (analog-to-digital) conversion circuit , comprising:a capacitor array formed of a plurality of capacitors;a sample hold circuit configured to apply an analog input voltage input through an input terminal to the capacitor array so that the analog input voltage is accumulated in the capacitor array until a sampling time set is elapsed;a comparator circuit configured to sequentially retrieve the analog input voltage accumulated in each of the capacitors of the capacitor array, said comparator circuit being configured to compare the analog input voltage with a reference voltage defined in advance to generate a digital signal; anda sampling time adjusting circuit configured to measure a period of time when a voltage on an input side of the sample hold circuit, which increases according to an adjustment voltage input from an external device connected to the input terminal, reaches a threshold value defined in advance relative to the reference voltage, said sampling time adjusting circuit being configured to set a time determined according to the period of time thus measured as the ...

Signal sensing circuit

A signal sensing circuit converts a received current input into a voltage output and provides the voltage output to an analog-to-digital converter (ADC) to generate a digital output signal. The voltage output is associated with a circuit having a first reference impedance, and a reference voltage of the ADC is associated with a circuit having a second reference impedance, wherein the circuit having the first reference impedance and the circuit having the second reference impedance are formed by the same material, so that the ratio between the changes in the current input and the changes in the value of the digital output signal is a constant.

AUDIO DEVICE SWITCHING WITH REDUCED POP AND CLICK

This document discusses, among other things, apparatus and methods including an analog-to-digital controller (ADC) configured to receive an enable signal and to provide an ADC output signal to control logic, wherein the control logic is configured to provide a control voltage to a control input of a switch. In an example, the control voltage includes the ADC output signal when the ADC output signal is below a first threshold or above a second threshold. In certain examples, the control logic is configured to transition the control voltage from the first threshold to the second threshold when the ADC output signal is between the first and second thresholds. 1. An apparatus comprising:an analog-to-digital controller (ADC) configured to receive an enable signal and to provide an ADC output signal including a plurality of voltage steps depending on the value of the enable signal; andcontrol logic configured to receive the ADC output signal and to provide a control voltage to a control input of a switch,wherein the control voltage includes the ADC output signal when the ADC output signal is below a first threshold or above a second threshold, andwherein the control logic is configured to transition the control voltage from the first threshold to the second threshold when the ADC output signal is between the first and second thresholds.2. The apparatus of claim 1 , including the switch including first and second terminals and the control input.3. The apparatus of claim 1 , including:a capacitor coupled between an input of the ADC and ground.4. The apparatus of claim 1 , including:a series resistor-capacitor (RC) circuit coupled to an input of the ADC.5. The apparatus of claim 1 , wherein the switch includes an audio switch configured to switch an audio signal between the first and second terminals.6. The apparatus of claim 1 , wherein the switch includes a transistor including a gate claim 1 , a source claim 1 , and a drain claim 1 ,wherein the control input includes the ...

SOLID-STATE IMAGING DEVICE, IMAGING DEVICE, ELECTRONIC EQUIPMENT, A/D CONVERTER AND A/D CONVERSION METHOD

In a reference signal comparison AD conversion scheme, a reference signal SLP_ADC and each of P and D phases of a pixel signal voltage Vare compared. A count clock CKcnt is counted based on the comparison result. The counting result data is converted into signal data Dsig, i.e., the difference between the P and D phases, which is also subjected to CDS. At this time, the n-bit AD conversion is performed on each of the P and D phases of the pixel signal voltage V, followed by summation for digital integration. This prevents any possible detrimental effects that may be caused by summation in the analog domain. Although the signal data becomes W times greater, noise will likely become √W times greater. This alleviates the problem of random noise resulting from AD conversion such as quantizing noise and circuit noise that do not exist in the analog domain, thus reducing the noise. 1. An electronic apparatus , comprising:an imaging lens; 'an analog to digital (A/D) conversion unit, the A/D conversion unit', 'a solid-state imaging device, wherein the solid-state imaging device receives light guided by the imaging lens onto the solid-state imaging device, the solid-state imaging device including a reference signal generation section that generates a reference signal whose level changes gradually;', 'a comparison section the compares the reference signal and a target analog signal; and', 'a counter section that performs a counting based on a count clock and a result of the comparison of the reference signal and the target analog signal, the A/D conversion unit obtaining digital data of the target analog signal based on output data of the counter section,', 'a drive control section that controls the reference signal generation section and the A/D conversion unit to perform a digital integration that repeats an n-bit A/D conversion on the target analog signal W times, where W is a positive integer equal to or greater than 2,', 'the solid-state imaging device further comprising ...

A/D CONVERSION CIRCUIT AND SOLID-STATE IMAGING DEVICE

An A/D conversion circuit and a solid-state imaging device are able to reduce current consumption, and two input terminals of a NAND element included in a latch circuit receive a corresponding one of a plurality of clock signals and an enable signal. The enable signal is not input to the NAND element before an end timing of A/D conversion, and is input to the NAND element at the end timing of the A/D conversion and at a timing at which latching is performed. The latch circuit latches no clock signal when the enable signal is not input. 1. An A/D conversion circuit comprising:a reference signal generation portion that generates a reference signal that increases or decreases with lapse of time from a predetermined start timing;a comparison portion that compares an analog signal with the reference signal, and outputs a comparison signal at an end timing at which the reference signal satisfies a predetermined condition with respect to the analog signal;a phase shift portion that outputs a plurality of clock signals having different phases from one another in response to a time change from the start timing;a latch portion including a plurality of latch units, each of the plurality of latch units latching a corresponding one of the plurality of clock signals after a predetermined time lapses from an end timing based on the comparison signal; andan operation portion that generates a digital signal according to a signal held in the latch portion,wherein each of the plurality of latch units includes a logic element having a first input terminal and a second input terminal,wherein the first input terminal receives the corresponding one of the plurality of clock signals,wherein the second input terminal does not receive an enable signal before the end timing based on the comparison signal and receives the enable signal at the end timing based on the comparison signal and at a timing at which the latch portion performs latching, andwherein each of the plurality of latch units ...

SOLID-STATE IMAGING DEVICE AND CAMERA SYSTEM

A solid-state imaging device and a camera system are provided. The solid-state imaging device capable of performing an intermittent operation includes a pixel unit and a pixel signal readout unit for reading out a pixel signal from the pixel unit in units of a plurality of pixels for each column. The pixel signal readout circuit includes a plurality of comparators and a plurality of counters whose operations are controlled by outputs of the comparators. Each of the comparators includes an initializing switch for determining an operating point for each column at a start of row operation, and is configured so that an initialization signal to be applied to the initializing switch is controlled independently in parallel only a basic unit of the initialization signal used for a horizontal intermittent operation, and the initializing switch is held in an off-state at a start of non-operating row. 16-. (canceled)7. An image data processing circuit comprising:a plurality of analog-to-digital converters, each respectively configured to convert an analog signal to a digital signal, each of the plurality of analog-to-digital converters including;a comparator unit configured to compare the analog signal with a reference voltage to output a determination signal;a storing unit configured to store a digital signal corresponding to the analog signal based on the determination signal;wherein an initializing switch sets an initial operating point before analog-to-digital conversion operation is initiated, and an intermittent operation includes at least one non-operating analog-to-digital converter,a first group of the initializing switches corresponding to operating analog-to-digital converters is in an ON state; anda second group of the initializing switches corresponding to non-operating analog-to-digital converters is periodically in an OFF-state, and further wherein the second group of initializing switches are selectively turned off during an image data thinning mode.8. An ...

ANALOGUE-TO-DIGITAL CONVERTER

An apparatus and method for regulating analogue-to-digital converters. First and second input signals are received at controlled oscillator circuitry which generates respective first and second pulse streams with pulse rates based on the relevant input signal. Difference circuitry determines the difference in number of pulses of the first and second pulse streams and outputs a first digital signal. Circuitry also determines a signal independent value based on the number of pulses of the first and/or second pulse streams. In one embodiment this value is the sum or average of the number of pulses of the first and second pulse streams. This value can be used to calibrate for any variation in transfer characteristic of the oscillator circuitry. In one embodiment this value is compared to a reference value and a regulation signal passed to control circuitry to regulate the operation of the oscillation circuitry. 1. An analogue-to-digital converter for receiving a differential analogue input signal comprising first and second input analogue signals , wherein said first and second analogue input signals exhibit equal and opposite modulations about a reference signal level , the converter comprising;controlled oscillator circuitry for generating first and second pulse streams with pulse rates dependent on the first and second input signals respectively; 'regulation circuitry for generating a regulation signal for modulating the operating conditions of the analogue-to-digital', 'difference circuitry, responsive to a clock signal, for generating a first digital signal based on the difference in number of pulses of the first and second pulse streams; and'}wherein the regulation circuitry is configured to generate a first value based on the number of pulses of the first and/or second pulse streams; andsaid the regulation signal is based on the first value.2. An analogue-to-digital converter as claimed inwherein the regulation circuitry is configured to generating said ...

COUNTER, COUNTING METHOD, AD CONVERTER, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC DEVICE

A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value includes a first latch circuit that latches the input clock, a second latch circuit that latches an output from the first latch circuit, a holding section that holds data of the 0th bit of a count value, and a correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit. 1. A counter configured to perform counting at both edges of an input clock to output an additional value or a subtraction value for a previous count value and a next count value , comprising:a first latch circuit that latches the input clock;a second latch circuit that latches an output from the first latch circuit;a holding section that holds data of the 0th bit of a count value; anda correction section that performs count correction on data of the first and subsequent bits of the count value on the basis of an output of the second latch circuit and an output of the holding section.2. The counter according to claim 1 ,wherein, when it is determined on the basis of clock latch data of the next count value which is the output of the second latch circuit and data of the 0th bit of the previous count value which is the output of the holding section that count correction is to be performed on the data of the first and subsequent bits of the count value, the correction section performs count correction on the data of the first and subsequent bits of the count value by giving a pulse to an input clock in a state where the first latch circuit is put into a through state.3. The counter according to claim 1 , further comprising:a generation section that generates data of the 0th bit of the next count value on the basis of clock latch data of the next count value which is an output of the second latch circuit and data of the 0th bit ...

Analogue to Digital Converter

Measures are provided for performing direct radio-frequency to digital conversion. A radio-frequency input signal is compared with a plurality of reference voltages to generate a plurality of comparison signals, each comparison signal corresponding to one of the plurality of reference voltages. One or more of the plurality of generated comparison signals are first filtered to generate a first filtered signal. One or more of the plurality of generated comparison signals are second filtered to generate a second filtered signal. A digital output signal is generated at least on the basis of the first filtered signal and the second filtered signal. 1. A method of performing direct radio-frequency to digital data component conversion , the method comprising:comparing a radio-frequency input signal with a plurality of reference voltages to generate a plurality of comparison signals, each comparison signal corresponding to one of the plurality of reference voltages;first filtering one or more of the plurality of generated comparison signals to generate a first filtered signal;second filtering one or more of the plurality of generated comparison signals to generate a second filtered signal; andgenerating a digital output signal at least on the basis of the first filtered signal and the second filtered signal, wherein the first filtering and the second filtering act to isolate a data component of the radio-frequency input signal.2. A method according to claim 1 , wherein the first filtering is performed on a first subset of the plurality of generated comparison signals and the second filtering is performed on a second claim 1 , different claim 1 , subset of the plurality of generated comparison signals.3. A method according to claim 1 , wherein each comparison signal in the plurality of generated comparison signals corresponds to a different one of the plurality of reference voltages.4. A method according to claim 1 , comprising sampling the plurality of comparison signals at ...

AD CONVERSION CIRCUIT AND SOLID-STATE IMAGE PICKUP DEVICE

An AD conversion circuit includes: a comparison unit that receives an analog signal and a reference signal, compares voltages of the signals, and outputs a first comparison signal; a signal generation unit that outputs a second comparison signal for switching a logic state, and outputs a third comparison signal that is a result of a logic operation on the first comparison signal and the second comparison signal; a control unit that outputs an enable signal; a clock generation unit that outputs first to nclock signals having different phases; a latch unit that includes first to nlatch units, each of the first to nlatch units including an input terminal, a first control terminal, a second control terminal, and an output terminal, and latches a logic state of the one of the first to nclock signals; and a count unit that performs a count operation. 1. An analog-to-digital (AD) conversion circuit comprising:a comparison unit configured to receive an analog signal and a reference signal that increases or decreases with passage of time, the comparison unit being configured to compare voltages of the analog signal and the reference signal, the comparison unit being configured to output a first comparison signal at a first timing at which the voltages of the analog signal and the reference signal have a predetermined relationship;a signal generation unit configured to output a second comparison signal for switching a logic state at a second timing at which a predetermined time has elapsed from the first timing, the signal generation unit being configured to output a third comparison signal that is a result of a logic operation on the first comparison signal and the second comparison signal;a control unit configured to output an enable signal at least between a timing relating to a comparison start of the comparison unit and the second timing;{'sup': 'th', 'a clock generation unit configured to output first to n(n is a natural number equal to or greater than 2) clock signals ...

Ad conversion circuit and solid-state imaging apparatus

An AD conversion circuit and a solid-state imaging apparatus reduce the occurrence of errors in encoding a lower phase signal while securing a degree of freedom of selection of a count clock. A detection circuit performs an operation of detecting logic states of m (m is a natural number of 2 or more) lower phase signals in a signal group that a plurality of lower phase signals latched by the latch unit is arranged, while selecting the m lower phase signals in a predetermined order so that the order thereof becomes the same as the order of the signal group and outputs a state detection signal at the time of detecting that the logic states of the m lower phase signals are in a predetermined logic state in the detection operation. The predetermined order is defined depending on a predetermined signal and an encoding method.

AD CONVERSION CIRCUIT AND SOLID-STATE IMAGE PICKUP DEVICE

An AD conversion circuit may include: a reference signal generation unit generating a reference signal increasing or decreasing with passage of time; a comparison unit including a first comparison circuit and a second comparison circuit comparing an analog signal to be subjected to an AD conversion with the reference signal; a clock generation unit including a delay circuit in which a plurality of delay units are connected to one another, and outputting a first lower phase signal and a second lower phase signal based on clock signals output from each of the plurality of delay units; a latch unit including a first latch circuit latching a logical state of the first lower phase signal and a second latch circuit latching a logical state of the second lower phase signal; and a counting unit performing counting based on the second lower phase signal output from the clock generation unit. 1. An AD conversion circuit comprising:a reference signal generation unit configured to generate a reference signal increasing or decreasing with passage of time;a comparison unit that includes a first comparison circuit and a second comparison circuit, each of which compares an analog signal to be subjected to an AD conversion with the reference signal;a clock generation unit that includes a delay circuit in which a plurality of delay units are connected to one another, the clock generation unit outputting a first lower phase signal and a second lower phase signal based on clock signals that are output from each of the plurality of delay units;a latch unit that includes a first latch circuit and a second latch circuit, the first latch circuit being configured to latch a logical state of the first lower phase signal that is output from the clock generation unit, the second latch circuit being configured to latch a logical state of the second lower phase signal that is output from the clock generation unit; anda counting unit configured to perform counting based on the second lower phase ...

Imaging Device Comprising a Circuit for Analog-Digital Conversion by Means of the Injection of a Quantity of Charges that Varies as a Function of the Number of Previous Injections

In the field of imaging devices comprising a detector generating electric charges in response to incident photon radiation, and an analog-to-digital conversion circuit forming means for reading the quantity of electric charges generated, an analog-to-digital conversion circuit comprises: a comparator which can switch depending on the comparison between a potential on an integration node and a predetermined threshold potential, a counter incrementing with each switch of the comparator, a counter-charge injection circuit injecting a quantity Qc of counter-charges on the integration node with each switch of the comparator, and control means which determine the quantity Qc of counter-charges injected. The analog-to-digital conversion circuit is characterized in that the control means determine the quantity Qc of counter-charges injected as a function of a value of the counter. 1. An analog-to-digital conversion circuit for an imaging device comprising a detector generating electric charges in response to incident photon radiation , the electric charges leading to a variation of an integration potential on an integration node , the analog-to-digital conversion circuit comprising:a comparator which can switch depending on the comparison between the integration potential and a predetermined threshold potential,a counter connected to an output of the comparator and incrementing with each switch of the comparator,a counter-charge injection circuit injecting a quantity Qc of counter-charges at the integration node with each switch of the comparator, andmeans for controlling the counter-charge injection circuit which determine the quantity Qc of counter-charges injected,wherein the control means determine the quantity Qc of counter-charges injected as a function of a value of the counter.2. The circuit as claimed in claim 1 , wherein the control means are configured to make the quantity Qc vary each time the value of the counter reaches one or more predetermined threshold ...

INTEGRATOR, AD CONVERTER, AND RADIATION DETECTION DEVICE

An integrator according to an embodiment includes first and second nodes, first to fifth switches, first and second main integration capacitors, and a first subsidiary integration capacitor. The first (second, third, fourth, fifth) switch has one end connected to a first (third, first, fourth, first) node and the other end connected to a third (second, fourth, second, fifth) node. The first main integration capacitor has one end connected to the third node and the other end connected to a standard voltage line. The second main integration capacitor has one end connected to the fourth node and the other end connected to the standard voltage line. The first subsidiary integration capacitor that has one end connected to the fifth node and the other end connected to the standard voltage line. 1. An integrator comprising:a first node that receives a signal current;a second node that outputs a voltage;a first switch that has one end connected to the first node and the other end connected to a third node;a second switch that has one end connected to the third node and the other end connected to the second node;a first main integration capacitor that has one end connected to the third node and the other end connected to a standard voltage line;a third switch that has one end connected to the first node and the other end connected to a fourth node;a fourth switch that has one end connected to the fourth node and the other end connected to the second node;a second main integration capacitor that has one end connected to the fourth node and the other end connected to the standard voltage line;a fifth switch that has one end connected to the first node and the other end connected to a fifth node; anda first subsidiary integration capacitor that has one end connected to the fifth node and the other end connected to the standard voltage line.2. The integrator according to claim 1 , further comprising:a sixth switch that has one end connected to the first node and the other end ...

Adjustable and buffered reference for adc resolution and accuracy enhancements

An analog to digital converter (ADC) core; a reference voltage generator coupled to an input of the ADC core; a bandgap reference coupled to the reference voltage generator; and a window comparator configured to control a selected reference voltage range generated by the reference voltage generator and received by the ADC core.

PHOTOELECTRIC CONVERSION APPARATUS AND IMAGE CAPTURING SYSTEM

In a first sensitivity level, an AD converter performs AD conversion selectively using, in accordance with the level of the analog signal, any one of a first reference signal and a second reference signal that have mutually different slopes, and in a second sensitivity level that is different from the first sensitivity level, the AD converter performs AD conversion only using a third reference signal. 1. A photoelectric conversion apparatus comprising:a plurality of pixels;a plurality of analog signal output units each configured to output an analog signal in accordance with a signal which is produced by and is output from a corresponding one of the plurality of pixels; anda plurality of analog-to-digital (AD) converters provided to correspond to the plurality of analog signal output units and configured to perform AD conversion by comparing a ramp signal with the analog signal output from the analog signal output units, whereinthe photoelectric conversion apparatus has a first operation mode where the imaging sensitivity level is a first sensitivity level and a second mode where the imaging sensitivity level is a second sensitivity level different from the first sensitivity level,in the first operation mode, each of the plurality of AD converters uses a third ramp signal having a third slope to perform the AD conversion for the analog signal having a third signal level lower than a second threshold value, and uses a fourth ramp signal having a fourth slope different from the third slope to perform the AD conversion for the analog signal having a fourth signal level higher than the second threshold valuein the second operation mode, each of the plurality of AD converters uses a third ramp signal having a third slope to perform the AD conversion for the analog signal having a third signal level lower than a second threshold value, and uses a fourth ramp signal having a fourth slope different from the third slope to perform the AD conversion for the analog signal ...

SPECTRALLY EFFICIENT DIGITAL LOGIC (SEDL) ANALOG TO DIGITAL CONVERTER (ADC)

Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for analog-to-digital converters (ADC) and digital-to-analog converters (DAC). An ADC circuit comprises a plurality of comparators configured to receive an analog input signal and compare the analog input signal to a predetermined reference signal, an encoder, and a spectrally-efficient circuit. A DAC circuit includes an integrator circuit, a clocked comparator circuit, a pulse generator, and a combiner circuit. The clocked comparator circuit receives the logic state of each SEDL pulse. The pulse generator receives the logic state and generates a scaled SEDL pulse for each input SEDL pulse. A combiner circuit combines the outputs from the pulse generator and determines analog value corresponding to the input values. 1. An analog-to-digital converter (ADC) comprising:a plurality of comparators, wherein each comparator is configured to receive an analog input signal and to compare the analog input signal to a predetermined reference signal to identify a value of the input signal, and in response to the analog input signal being greater than the reference signal the comparator provides an output having a first value, and in response to the analog input signal being less than the reference signal the comparator provides an output having a second different value;an encoder configured to receive the output signal from each comparator and in response thereto to provide at least one of a plurality of bits at an output as a digital value depending upon one of the plurality of values input to the encoder; anda spectrally-efficient-based sequential circuit configured to assess a state of the digital value and to provide an output pulse having a sequentially-efficient shaped pulse.2. The ADC of claim 1 , wherein ...

SPECTRALLY EFFICIENT DIGITAL LOGIC (SEDL) DIGITAL TO ANALOG CONVERTER (DAC)

Spectrally-efficient digital logic (SEDL) techniques implement spectrally-efficient pulses (e.g., Gaussian-shaped pulses) in lieu of conventional square waveforms to improve electromagnetic, radio frequency, and other unwanted emissions. The SEDL techniques can be used for analog-to-digital converters (ADC) and digital-to-analog converters (DAC). An ADC circuit comprises a plurality of comparators configured to receive an analog input signal and compare the analog input signal to a predetermined reference signal, an encoder, and a spectrally-efficient circuit. A DAC circuit includes an integrator circuit, a clocked comparator circuit, a pulse generator, and a combiner circuit. The clocked comparator circuit receives the logic state of each SEDL pulse. The pulse generator receives the logic state and generates a scaled SEDL pulse for each input SEDL pulse. A combiner circuit combines the outputs from the pulse generator and determines analog value corresponding to the input values. 1. A digital-to-analog converter (DAC) circuit comprising:an integrator circuit having an input configured to receive an input signal provided from a plurality of spectrally-efficient shaped digital logic (SEDL) pulses, with each SEDL pulse representing one or more bits of the input signal and wherein the integrator circuit is configured to determine a logic state represented by each of the plurality of SEDL pulses;a clocked comparator circuit coupled to the integrator circuit and configured to receive the logic state of each SEDL pulse and in response thereto, to provide a clocked comparator circuit signal at an output thereof;a pulse generator having a first input coupled to an output of the integrator circuit and a second input coupled to an output of the clocked comparator circuit, wherein, in response to receiving a logic state and a clocked comparator circuit signal, the pulse generator generates a scaled SEDL pulse for each input signal SEDL pulse;a combiner circuit coupled to the ...

TIME DOMAIN RATIOMETRIC READOUT INTERFACES FOR ANALOG MIXED-SIGNAL IN MEMORY COMPUTE CROSSBAR NETWORKS

A circuit configured to compute matrix multiply-and-add calculations that includes a digital-to-time converter configured to receive a digital input and output a signal proportional to the digital input and modulated in time-domain associated with a reference time, a memory including a crossbar network, wherein the memory is configured to receive the time modulated signal from the digital-to-time converter and output a weighted signal scaled in response to network weights of the crossbar network and the time modulated input signal, and an output interface in communication with the crossbar network and configured to receive its weighted output signal and output a digital value proportional to at least the reference time using a time-to-digital converter. 1. A circuit configured to compute matrix multiply-and-add calculations , comprising:a digital-to-time converter configured to receive a digital input and output a signal proportional to the digital input and modulated in time-domain associated with a reference time;a memory including a crossbar network, wherein the memory is configured to receive the time modulated signal from the digital-to-time converter and output a weighted signal scaled in response to network weights of the crossbar network and the time modulated signal; andan output interface in communication with the crossbar network and configured to receive its weighted output signal and output a digital value proportional to at least the reference time using a time-to-digital converter.2. The circuit of claim 1 , wherein the circuit includes a reference clock associated with the digital-to-time converter and the time-to-digital converter.3. The circuit of claim 1 , wherein the network weights include one or more electrical elements configured to scale the signal proportional to the digital input and modulated in time domain.4. The circuit of claim 1 , wherein the circuit includes an integrator for accumulation of the weighted signal scaled in response to ...

CURRENT COUNTING ANALOG-TO-DIGITAL CONVERTER FOR LOAD CURRENT SENSING INCLUDING DYNAMICALLY BIASED COMPARATOR

In one embodiment, a circuit comprises first and second capacitors configured to receive a sense current in first and second modes, respectively. A comparator is coupled to the first capacitor to compare a voltage of the first capacitor to a reference voltage and generate a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode. The comparator is coupled to the second capacitor to compare a voltage of the second capacitor to the reference voltage and generate the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode. A reset circuit discharges the first capacitor in the second mode and the second capacitor in the first mode in response to the count signal. A counter increments a count of a number of occurrences of the count signal. 1. A circuit comprising:a first capacitor configured to receive a sense current in a first mode;a second capacitor configured to receive a sense current in a second mode;a comparator coupled to the first capacitor to compare a voltage of the first capacitor to a reference voltage and generate a count signal in response to the voltage of the first capacitor reaching the reference voltage in the first mode and coupled to the second capacitor to compare a voltage of the second capacitor to the reference voltage and generate the count signal in response to the voltage of the second capacitor reaching the reference voltage in the second mode;a reset circuit to discharge the first capacitor in the second mode and to discharge the second capacitor in the first mode in response to the count signal; anda counter incrementing a count of a number of occurrences of the count signal.2. The circuit of further comprising a switch circuit to couple the first capacitor to the comparator in the first mode and couple the second capacitor to the comparator in the second mode.3. The circuit of wherein the reset circuit comprises a first switch ...

FRONT-END RECEIVING CIRCUIT AND METHOD FOR THE SAME

A front-end receiving circuit includes a first input terminal receiving a first signal, a second input terminal receiving a second signal, a comparator, a first sampling switch, a first sampling shifting circuit and a control circuit. The first sampling switch is coupled between the first input terminal and the first comparator input terminal. The first sample shifting circuit includes a first capacitor, a first reference voltage source, and a second reference voltage source. In a sampling mode, the control circuit is configured to control the first sampling switch and the second sampling switch to be turned on, and control the first shifting switch to be turned off. In a shifting mode, the control circuit is configured to control the first sampling switch and the second sampling to be turned off, and control the first shifting switch to be turned on. 1. A front-end receiving circuit connected to a back-end circuit , comprising:a first input terminal configured to receive a first signal;a second input terminal configured to receive a second signal;a comparator having a first comparator input terminal and a second comparator input terminal respectively connected to the first input terminal and the second input terminal;a first sampling switch connected between the first input terminal and the first comparator input terminal; a first capacitor having one end connected between the first sampling switch and the first comparator input terminal;', 'a first reference voltage source connected to another end of the first capacitor through a second sampling switch; and', 'a second reference voltage source connected to the another end of the first capacitor through a first shifting switch; and, 'a first sampling shifting circuit, which includesa control circuit, configured to be electrically and respectively coupled to the first sampling switch, the second sampling switch and a control end of the first shifting switch, to control the first sampling switch, the second sampling ...

Device for converting analogue signals into digital signals

Method and device for converting analogue signals, of a plurality of pathways, into digital signals. A common circuit ( 2, 3 ) generates first analogue signals corresponding to high-order bits of digital signals For each pathway, a first means compares the first analogue signals with the signal to be converted. A first means ( 18 ) stores high-order bits corresponding to the value of a first analogue signal close to the signal to be converted. A means ( 9 ) stores the deviation between the analogue signal to be converted and said first detected value. A generator means ( 11, 12 ) generates a predetermined number of second analogue signals. A second means compares by successive approximations said second analogue signals with said deviation. A means ( 20 ) stores said low-order bits corresponding to the results arising from said second means of comparison. A means ( 22 ) assembles said high-order bits and said low-order bits.

Mixed-Domain Circuit with Differential Domain-Converters

A mixed-domain circuit has a differential pair of Digital-to-Time Converters (DTCs), one receiving a reference clock and the other receiving a feedback clock. A Time-to-Digital Converter (TDC) compares outputs from the differential pair of DTCs and generates a digital error value that controls a digital loop filter that controls a Digitally-Controlled Oscillator (DCO) that generates an output clock. A Multi-Modulus Divider (MMD) generates the feedback clock. An accumulated modulation from a delta-sigma modulator is compared to the digital error value by a Least-Mean Square (LMS) correlator to adjust supply voltage or current sources in the pair of DTCs to compensate for errors. A capacitor in each DTC has a charging time adjusted by the accumulated modulation. The DTC can be reduced to a Time-to-Voltage Converter (TVC) and the analog voltages on the capacitors input to an Analog-to-Digital Converter (ADC) to generate the digital error value. 1. A mixed-domain circuit comprising:a first converter having a first input in a first domain, for generating a first output in a second domain;a second converter having a second input in the first domain, for generating a second output in the second domain;wherein the first domain is selected from the group consisting of a time domain, and a digital domain;wherein the second domain is selected from the group consisting of a time domain, a digital domain, and a voltage domain;wherein the first converter is matched to the second converter, wherein a signal injected to both the first input and to the second input adjusts the first output and adjusts the second output by a substantially same amount when a same adjustment signal is applied to both the first converter and to the second converter;wherein the second domain and the first domain are different domains;a differential converter that receives the first output from the first converter, and that receives the second output from the second converter, for generating an error ...

PHOTOELECTRIC CONVERSION APPARATUS AND IMAGE CAPTURING SYSTEM

In a first sensitivity level, an AD converter performs AD conversion selectively using, in accordance with the level of the analog signal, any one of a first reference signal and a second reference signal that have mutually different slopes, and in a second sensitivity level that is different from the first sensitivity level, the AD converter performs AD conversion only using a third reference signal. 1. (canceled)2. A photoelectric conversion apparatus in which a sensitivity level is settable , the photoelectric conversion apparatus comprising:a ramp signal supply unit configured to supply a ramp signal; andan analog-to-digital (AD) converter into which an analog signal based on light incident on a pixel and the ramp signal are input, and configured to perform analog-to-digital (AD) conversion on the analog signal by comparing the analog signal and the ramp signal,wherein in the AD conversion in a first sensitivity level, the ramp signal supply unit outputs a first number of ramp signals having different slopes to the AD converter, andwherein in the AD conversion in a second sensitivity level different from the first sensitivity level, the ramp signal supply unit outputs a second number, smaller than the first number, of ramp signals having different slopes or only one ramp signal to the AD converter.3. The photoelectric conversion apparatus according to claim 2 , wherein the second sensitivity level is higher than the first sensitivity level.4. The photoelectric conversion apparatus according to claim 3 , wherein a ramp signal to be used for the AD conversion in the second sensitivity level includes a ramp signal having a smallest slope among the first number of ramp signals.5. The photoelectric conversion apparatus according to claim 3 , wherein a ramp signal to be used for the AD conversion in the second sensitivity level includes a ramp signal having a smaller slope than a slope of any of the first number of ramp signals.6. The photoelectric conversion ...

DOUBLE DATA RATE COUNTER, AND ANALOG-TO-DIGITAL CONVERTER AND CMOS IMAGE SENSOR USING THE SAME

A Double Data Rate (DDR) counter includes an input clock control portion suitable for generating a first clock corresponding to a state of a input clock based on a counter enable signal, and an LSB control portion suitable for holding a least significant bit based on the counter enable signal and successively performing a counting operation on the first clock in multiple sections. 1. A Double Data Rate DDR counter , comprising:an input clock control portion suitable for generating a first clock corresponding to a state of a input clock based on a counter enable signal; anda Least Significant Bit (LSB) control portion suitable for holding an LSB based on the counter enable signal and successively performing a counting operation on the first clock in multiple sections.2. The DDR counter of claim 1 , wherein the input clock control portion detects the state of a neighboring clock of the input clock based on a first edge of the counter enable signal and inverts or non-inverts the input clock based on a detected state of the neighboring clock.3. The DDR counter of claim 1 , wherein the input clock control portion includes:a counting section determination block suitable for receiving the input clock and the counter enable signal and determining a counting section;a clock sampling block suitable for sampling the state of the input clock based on the counter enable signal; anda first inversion/non-inversion block suitable for inverting or non-inverting an output of the counting section determination block based on a clock sampling result obtained from the clock sampling block and outputting the first clock to the LSB control portion.4. The DDR counter of claim 3 , wherein the input clock control portion further includes:a third inversion/non-inversion block suitable for inverting or non-inverting a cross-correlation double sampling output based on a control signal and outputting the counter enable signal.5. The DDR counter of claim 3 , wherein the counting section ...

Signal converter and method for operating a signal converter

In accordance with an embodiment, a method for operating a signal converter includes converting an analog input signal to a digital output signal, comprising by comparing the analog input signal to an analog comparison signal, and detecting whether the analog input signal exceeds a predetermined maximum or minimum threshold by comparing the analog input signal to an analog threshold signal. The analog comparison signal and the analog threshold signal are generated by a same digital-to-analog converter.

SEMICONDUCTOR INTEGRATED CIRCUIT, CURRENT CONTROL METHOD, AD CONVERTER, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC SYSTEM

A semiconductor integrated circuit includes: a plurality of current sources including a first transistor individually connected to a power source line and a bias line; and a plurality of bias blocks including a second transistor configured to constitute a current mirror circuit together with the first transistor, and to divide a reference current to be a reference of the current sources so that the reference current flows through the bias line. 1. A semiconductor integrated circuit comprising:a plurality of current sources including a first transistor individually connected to a power source line and a bias line; anda plurality of bias blocks including a second transistor configured to constitute a current mirror circuit together with the first transistor, and to divide a reference current to be a reference of the current sources so that the reference current flows through the bias line.2. The semiconductor integrated circuit according to claim 1 ,wherein a number of the bias blocks disposed is two.3. The semiconductor integrated circuit according to claim 2 ,wherein a ratio of a reference current configured to flow through the bias line by one of the bias blocks to a reference current configured not to flow through the bias line by the other of the bias blocks is 1:3.4. The semiconductor integrated circuit according to claim 2 ,wherein the first transistor includes a PMOS transistor, anda gate of the PMOS transistor is connected to the bias line, and a source thereof is connected to the power source line, and a drain thereof is connected to an output terminal.5. The semiconductor integrated circuit according to claim 2 ,wherein the first transistor includes an NMOS transistor, anda gate of the NMOS transistor is connected to the bias line, and a source thereof is connected to the power source line, and a drain thereof is connected to an output terminal.6. The semiconductor integrated circuit according to claim 1 ,wherein the semiconductor integrated circuit is a DA ...

A/D CONVERTER, SOLID-STATE IMAGING DEVICE, METHOD FOR DRIVING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS

An A/D converter includes a reference voltage generating circuit that generates a reference voltage of a ramp waveform in which a voltage value changes with time, a gray code generating circuit that outputs a gray code based on a same reference clock as the reference voltage generating circuit, a comparison circuit that compares the reference voltage with an input voltage, a latch circuit that holds a count value of the gray code based on an output signal of the comparison circuit, a code conversion circuit that serially converts the count value of the gray code held in the latch circuit into a binary code, and a calculation processing circuit that stores a count value of the binary code output from the code conversion circuit, and performs calculation processing based on the stored count value of the binary code and a next input count value of the binary code. 1. An A/D converter comprising:a ramp voltage circuit that generates a ramp voltage based on a reference clock, the ramp voltage having a ramp waveform which monotonically changes with time, the reference clock having a periodical waveform;a gray code circuit that outputs a reference gray code based on the reference clock, the reference gray code being a gray code converted from the ramp voltage;a comparison circuit that outputs a comparison signal according to comparing the reference voltage with an input analog voltage;a latch circuit that holds a counted gray code that is the reference gray code held based on the comparison signal;a code conversion circuit that serially converts the counted gray code into an original binary code; anda calculation circuit that stores a calculated binary code, the calculated binary code is calculated from first binary code and the second binary code, the first binary code being the original binary code corresponding to one of the input analog voltage, and the second binary code being the original binary code corresponding to another of the input analog voltage.2. The A/D ...

Image sensor, method of controlling image sensor, and electronic device

Provided is an image sensor including: a pixel section configured to include a plurality of pixels arranged therein; and an AD conversion unit configured to perform analog-to-digital (AD) conversion on a pixel signal on the basis of a result of comparison between a first voltage of a signal, which is obtained by adding, via capacitances, the pixel signal of the pixel and a reference signal that linearly changes in a direction opposite to the pixel signal, with a second voltage serving as a reference.

ANALOG-TO-DIGITAL CONVERTER AND SOLID-STATE IMAGE SENSOR

[Object] To prevent code skipping in decoding. 1. An analog-to-digital converter that is disposed for at least one column or at least one of unit pixels , and converts input analog signals into digital signals , the analog-to-digital converter comprising:a comparator that compares voltage of the analog signals with a reference voltage of which a voltage value varies in accordance with a reference clock;a low-order bit latch unit that latches a digital code corresponding to the reference clock as a low-order bit, triggered by output of the comparator being inverted;a high-order bit counter unit that counts one or both of edges of a control signal corresponding to the reference clock, and stops counting of high-order bits, triggered by output of the comparator being inverted;a low-order bit decoding signal latch unit that latches a low-order bit decoding signal corresponding to the reference clock; anda signal processing unit that compares a value of the low-order bit decoding signal that has been latched and a value of a least significant bit of the high-order bits to detect code skipping, and corrects the detected code skipping.2. The analog-to-digital converter according to claim 1 ,wherein the signal processing unit detects the code skipping in a case where the value of the low-order bit decoding signal and the value of the least significant bit differ, and corrects the detected code skipping.3. The analog-to-digital converter according to claim 1 ,wherein the signal processing unit detects the code skipping in a case where the value of the low-order bit decoding signal and the value of the least significant bit are equal, and corrects the detected code skipping.4. A solid-state image sensor claim 1 , comprising:a pixel portion that converts incident light into analog signals;{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'the analog-to-digital converter according to , that converts the analog signals into digital signals; and'}a vertical signal line for ...

SYSTEM FOR RNS BASED ANALOG-TO-DIGITAL CONVERSION AND INNER PRODUCT COMPUTATION

A system is proposed for forming the inner product of an input signal having a number of signal entries, with a pre-known vector. Each signal entry is represented in an RNS format. The residue for each modulus is represented as a string in which the number of components taking a first value is equal to the residue. Corresponding components of the strings for different input entries are used to obtain a summation value, and the summation values are accumulated. Since the components of the string are not associated with weight values, the accumulation of the summation values can be performed without using a scaling accumulator. Furthermore, an ADC is proposed which uses the input signal to generate an RNS representation of the signal based on a plurality of moduli. For each modulus, there is a corresponding Residue Number System (RNS) converter which includes a number of zero-crossing-based folding circuits equal to the modulus, and a comparator for each zero-crossing based folding circuit. The output of the comparators is used to form the RNS representation. This ADC is efficient in terms of the number of comparators it uses. Optionally, the RNS representation may be converted into a different digital representation. 112-. (canceled)13. An analog-to-digital converter for converting an analog input signal into a digital signal , the analog-to-digital converter comprising a residue number system (RNS) converter for converting the input signal into a digital RNS representation based on a plurality of relatively prime moduli , andwherein the RNS converter comprises for each said modulus:a number of zero-crossing based folding circuits equal to the modulus, and configured to compare the input signal against a set of reference voltages to produce comparison outputs, the zero-crossing based folding circuits generating respective outputs as a function of the input signal based on a plurality of respective waveforms comprising zero-crossings at respective subsets of the ...

GAIN CALIBRATION OF ADC RESIDUE AMPLIFIERS

A device for gain calibration of an analog-to-digital converter (ADC) residue amplifier includes a digital-to analog converter (DAC) configured to convert a digital signal to an analog signal. The DAC includes a calibration capacitor that can be used in the gain calibration of the ADC residue amplifier. A flash ADC, including a plurality of comparators and an additional comparator, generates the digital signal. The additional comparator provides a threshold voltage approximately in a middle point of a nominal subrange. The nominal subrange comprises a portion of a voltage range corresponding to threshold voltages of two adjacent comparators of the plurality of comparators. 1. A device for gain calibration of an analog-to-digital converter (ADC) residue amplifier , the device comprising:a digital-to analog converter (DAC) configured to convert a digital signal to an analog signal, the DAC including a calibration means configured for being used in the gain calibration of the ADC residue amplifier; anda flash ADC configured to generate the digital signal, the flash ADC including a plurality of comparators and an additional comparator,wherein a count of the plurality of comparators is equal to a number of output bits of the flash ADC and the additional comparator is configured to provide a threshold voltage approximately in a middle point of a nominal subrange, wherein the nominal subrange comprises a portion of a voltage range corresponding to threshold voltages of two adjacent comparators of the plurality of comparators.2. The device of claim 1 , wherein the flash ADC is configured to generate the digital signal by conversion to digital of a sample of an input signal.3. The device of claim 2 , wherein the device comprises a part of a stage of a pipeline ADC that includes the ADC residue amplifier that is configured to amplify a residue signal.4. The device of claim 3 , wherein the residue signal is created by subtraction of the analog signal from the sample of the ...

EXCESS LOOP DELAY COMPENSATION (ELC) FOR AN ANALOG TO DIGITAL CONVERTER (ADC)

In one embodiment, a circuit includes a quantizer configured to convert an analog input signal to a digital signal. The quantizer includes a first feedback path including a first digital to analog converter (DAC) coupled from an output of the quantizer to a summing junction that is coupled to an input of the quantizer. The first feedback path converts the digital signal to a first corresponding analog value for combining with the analog input signal at the summing junction. Also, the quantizer includes a plurality of excess loop delay (ELD) compensation paths coupled to the summing junction configured to compensate for excess loop delay from a second feedback path coupled from the output of the quantizer to input of the quantizer via a loop filter. Second DACs in the second feedback path convert the digital signal to a second corresponding analog value for combining with the analog input signal. 1. A circuit comprising:a quantizer configured to convert an analog input signal to a digital signal, the quantizer comprising:a first feedback path including a first digital to analog converter (DAC) coupled from an output of the quantizer to a summing junction that is coupled to an input of the quantizer, wherein the first feedback path converts the digital signal to a first corresponding analog value for combining with the analog input signal at the summing junction; anda plurality of excess loop delay (ELD) compensation paths coupled to the summing junction configured to compensate for excess loop delay from a second feedback path coupled from the output of the quantizer to input of the quantizer, wherein a set of second DACs in the second feedback path convert the digital signal to a second corresponding analog value for combining with the analog input signal.2. The circuit of claim 1 , wherein the plurality of ELD compensation paths are programmable to compensate for different excess loop delays.3. The circuit of claim 2 , wherein the plurality of ELD compensation ...

RECORDING DEVICE AND RECORDING METHOD

To allow a time-series change among signal values to be recorded easily for a process of recording the respective time-series values of input signals, a recording device includes: a determination reference value obtaining section configured to obtain a determination reference value on a basis of signal values during a reference time period, the reference time period being a predetermined time period after a start of input of time-series signal values, the determination reference value indicating a feature of the signal values during the reference time period, and a recording control section configured to (i) obtain information on a recording start condition on a basis of the determination reference value, the recording start condition indicating whether, as compared to the signal values during the reference time period, there has been a large change among signal values after the reference time period has elapsed, and (ii) start recording signal values in response to the recording start condition becoming satisfied. 1. A recording device , comprising:a determination reference value obtaining section configured to obtain a determination reference value on a basis of signal values during a reference time period, the reference time period being a predetermined time period after a start of input of time-series signal values, the determination reference value indicating a feature of the signal values during the reference time period, anda recording control section configured to (i) obtain information on a recording start condition on a basis of the determination reference value, the recording start condition indicating whether, as compared to the signal values during the reference time period, there has been a large change among signal values after the reference time period has elapsed, and (ii) start recording signal values in response to the recording start condition becoming satisfied.2. The recording device according to claim 1 , whereinthe determination reference ...

Semiconductor device and ad conversion device

A semiconductor device includes an AD conversion unit that performs AD conversion on an input signal based on a reference voltage to be supplied, a reference voltage detection unit that detects the reference voltage supplied to the AD conversion unit, and a control unit that corrects a result of the AD conversion by the AD conversion unit in accordance with the reference voltage detected by the reference voltage detection unit. Thereby, AD conversion can be performed accurately even when a reference voltage varies.

MULTI-LEVEL QUANTIZERS AND ANALOGUE-TO-DIGITAL CONVERTERS

An analogue-to-digital converter employs one or more reference ladders for generating reference voltages with which to compare the analogue signal for quantization. Selected impedances of the reference ladder can be dynamically decoupled from the input signal in dependence on the value of the output signal in order to reduce headroom in the reference ladders, thus making possible accurate quantization in low-voltage applications. 1. An analogue-to-digital converter , comprising:one or more reference ladders coupled to receive an analogue input signal to be quantized, each reference ladder comprising a plurality of impedances, and a current source providing a reference current through the plurality of impedances, a plurality of nodes being interleaved with the plurality of impedances;a switching arrangement, for coupling and decoupling one or more of the plurality of impedances from the input signal;a plurality of comparators, each comparator coupled to receive signals from respective nodes of the one or more reference ladders, and to provide an output comparison signal;an output, configured to receive the plurality of output comparison signals and to output a digital quantized signal corresponding to the input signal; andcontrol logic, configured to control the switching arrangement in dependence on the quantized signal.2. An analogue-to-digital converter , comprising:one or more reference ladders coupled to receive an input signal to be quantized, each reference ladder comprising a plurality of impedances, and a current source providing a reference current through the plurality of impedances, a plurality of nodes being interleaved with the plurality of impedances;a switching arrangement, for coupling and decoupling one or more of the plurality of impedances from the input signal;a plurality of comparators, each comparator coupled to receive signals from respective nodes of the one or more reference ladders, and to provide an output comparison signal;an output, ...

RECONFIGURABLE LOGIC GATES USING CHAOTIC DYNAMICS

The present invention provides apparatuses and methods for chaos computing. For example, a chaos-based logic block comprises an encoding circuit block, at least one chaotic circuit block, a bias voltage generating circuit block, and a threshold circuit block. The encoding circuit block converts a plurality of digital inputs to an analog output. The plurality of digital inputs may comprise at least one data input and at least one control input. At least one chaotic circuit block is configured to iterate converting an input signal to an output signal by feeding the output signal to at least one chaotic circuit as the input signal at each iteration. The bias voltage generating circuit block converts a plurality of binary control inputs to a bias voltage. The threshold circuit block compares the output signal with a predetermined threshold, thereby generating a digital signal. 1. A chaos-based logic block for chaos computing , comprising:an encoding circuit block converting a plurality of digital inputs to an analog output, the plurality of digital inputs comprising at least one data input and at least one control input;at least one chaotic circuit block coupled to the encoding circuit block, the at least one chaotic circuit block is configured to iterate converting an input signal to an output signal by feeding the output signal to the at least one chaotic circuit as the input signal at each iteration;a bias voltage generating circuit block coupled to the at least one chaotic circuit block, converting a plurality of binary control inputs to a bias voltage; anda threshold circuit block coupled to the at least one chaotic circuit block, comparing the output signal with a predetermined threshold to generate a digital signal.2. The chaos-based logic block of the claim 1 , wherein the at least one chaotic circuit block is initialized by the analog output.3. The chaos-based logic block of the claim 1 , wherein the at least one chaotic circuit block receives the bias voltage ...

Micro Analog Sensor Circuit and System

The present disclosure is directed to a system implementing a sensor. A sensing system is implemented in a functional circuit block that is coupled to a global supply voltage node. The sensing system includes a power converter circuit configured to generate a regulated voltage level on a local supply node using the voltage present on the global supply voltage node. The system also includes a sensor circuit coupled to receive the regulated voltage node, wherein the sensor is configured to compare corresponding parameters of different ones of a number of subset of device at a plurality of different time points and generate a plurality of comparison results. The comparisons generate an analog signal that is proportional to the operating parameter. An analog-to-digital converter (ADC) is coupled to receive the analog signal and generate a plurality of bits corresponding thereto. 1. An apparatus , comprising:a functional circuit block coupled to a global power supply node;a power converter circuit configured to generate a regulated voltage level on a local power supply node using the voltage level of the global power supply node, wherein the regulated voltage level is greater than the voltage level of an input power supply node; compare corresponding parameters of different ones of a plurality of subsets of the plurality of devices at a plurality of time points to generate a plurality of comparison results; and', 'generate an analog signal using the plurality of comparison results, wherein the analog signal is proportional to an operating parameter associated with the functional circuit block; and, 'a sensor circuit coupled to the local power supply node, wherein the sensor circuit includes a plurality of devices, and wherein the sensor circuit is configured toan analog-to-digital converter (ADC) circuit coupled to the local power supply node, wherein the analog-to-digital converter circuit is configured to generate a plurality of bits using the analog signal.2. The ...

PHASE DETECTING CIRCUIT FOR INTERCHAIN LOCAL OSCILLATOR (LO) DIVIDER PHASE ALIGNMENT

Certain aspects of the present invention provide methods and apparatus for detecting phase shift between signals, such as local oscillating signals in adjacent transceiver paths. One example circuit for phase detection generally includes a mixer configured to mix a first input signal having a first frequency with a second input signal having a second frequency to produce an output signal having frequency components at the sum of and the difference between the first and second frequencies; a filter connected with the mixer and configured to remove one of the frequency components at the sum of the first and second frequencies, thereby leaving a DC component; and an analog-to-digital converter (ADC) (e.g., a comparator) connected with the filter and configured to determine whether the first input signal is in-phase or out-of-phase with the second input signal based on a comparison between the DC component and a reference signal. 1. A circuit for phase detection , comprising:a mixer configured to mix a first input signal having a first frequency with a second input signal having a second frequency to produce an output signal having frequency components at the sum of and the difference between the first frequency and the second frequency, wherein the first frequency is the same as the second frequency;a filter connected with the mixer and configured to remove one of the frequency components at the sum of the first frequency and the second frequency, thereby leaving a direct current (DC) component; andan analog-to-digital converter (ADC) connected with the filter and configured to determine whether the first input signal is in-phase or out-of-phase with the second input signal based on a comparison between the DC component and a reference signal.2. The circuit of claim 1 , wherein the first claim 1 , second claim 1 , and output signals are differential signals.3. The circuit of claim 2 , wherein the filter comprises a capacitor to shunt a first output signal and a second ...

CONDITIONAL CORRELATED MULTIPLE SAMPLING SINGLE SLOPE ANALOG-TO-DIGITAL CONVERTER, AND ASSOCIATED IMAGE SENSOR SYSTEM AND METHOD

A conditional correlated multiple sampling (CCMS) single slope (SS) analog-to-digital converter (ADC) is provided. The CCMS SS ADC includes a comparator, arranged to compare an analog signal with a ramp signal and generate a comparison result; and a CCMS control circuit, arranged to determine a swing of the ramp signal according to a magnitude of the analog signal. An image sensor system using the CCMS SS ADC and a method of CCMS SS analog-to-digital conversion are also disclosed. 1. A conditional correlated multiple sampling (CCMS) single slope (SS) analog-to-digital converter (ADC) , comprising:a comparator, arranged to compare an analog signal with a ramp signal and generate a comparison result; anda CCMS control circuit, arranged to determine the ramp signal according to a magnitude of the analog signal.2. The CCMS SS ADC of claim 1 , further comprising a switch for selectively outputting one of a first ramp signal and a second ramp signal as the ramp signal according to the determination produced by the CCMS control circuit claim 1 , wherein the first ramp signal has a first swing greater than a second swing of the second ramp signal.3. The CCMS SS ADC of claim 2 , wherein when the magnitude of the analog signal is not smaller than a predefined value claim 2 , the CCMS control circuit determines to select the first ramp signal to act as the ramp signal; when the magnitude of the analog signal is smaller than the predefined value claim 2 , the CCMS control circuit determines to select the second ramp signal to act as the ramp signal.4. The CCMS SS ADC of claim 1 , wherein a ratio of a cycle time of the first ramp signal over a cycle time of the second ramp signal is greater than 1.5. The CCMS SS ADC of claim 4 , wherein when the CCMS control circuit determines to select the first ramp signal to act as the ramp signal claim 4 , the comparator compares the analog signal with the ramp signal for once claim 4 , and when the CCMS control circuit determines to select ...

ANALOG-DIGITAL CONVERTER, SOLID-STATE IMAGE SENSOR, AND ELECTRONIC APPARATUS

An analog-digital converter includes: a first comparator configured to make a comparison between a pixel voltage and a first reference voltage, the pixel voltage being a signal voltage outputted from a pixel including an photoelectric conversion element, the pixel voltage corresponding to electric charge generated by the photoelectric conversion element; a second comparator configured to make a comparison between the pixel voltage and a second reference voltage; and a voltage follower configured to connect an input terminal for the first reference voltage of the first comparator and an input terminal for the second reference voltage of the second comparator through a switch. 1. An analog-digital converter comprising:a first comparator configured to make a comparison between a pixel voltage and a first reference voltage, the pixel voltage being a signal voltage outputted from a pixel including an photoelectric conversion element, the pixel voltage corresponding to electric charge generated by the photoelectric conversion element;a second comparator configured to make a comparison between the pixel voltage and a second reference voltage; anda voltage follower configured to connect an input terminal for the first reference voltage of the first comparator and an input terminal for the second reference voltage of the second comparator through a switch.2. The analog-digital converter according to claim 1 , whereinthe voltage follower includes a first voltage follower configured to output a voltage inputted to the input terminal for the first reference voltage of the first comparator to the input terminal for the second reference voltage of the second comparator and a second voltage follower configured to output a voltage inputted to the input terminal for the second reference voltage of the second comparator to the input terminal for the first reference voltage of the first comparator.3. The analog-digital converter according to claim 1 ,wherein the first and second ...

A/D CONVERTER, SOLID-STATE IMAGING DEVICE AND CAMERA SYSTEM

An A/D converter includes: plural comparators to which reference voltages as ramp waves different from each other are supplied, which are configured to compare the supplied reference voltages with an analog input signal; and plural latches arranged so as to correspond to the plural comparators, which are configured to count comparison time of the corresponding comparators, to stop counting when an outputs of the comparator is inverted and to store the count value, wherein the plural reference voltages are off set by an arbitrary voltage at the same time point. 1plural comparators to which reference voltages as ramp waves different from each other are supplied, the plural comparators being configured to compare the supplied reference voltages with an analog input signal,wherein the plural reference voltages are offset by an arbitrary voltage at a same point in time.. An A/D converter comprising: This is a Continuation Application of U.S. patent application Ser. No. 13/707, 151, filed on Dec. 6, 2012, which is a Continuation Application of U.S. patent application Ser. No. 12/659,799, filed on Mar. 22, 2010, now U.S. Pat. No. 8,358,349, issued on Jan. 22, 2013, which claims priority from Japanese Patent Application JP 2009-100604 filed with the Japanese Patent Office on Apr. 17, 2009 the entire contents of which being incorporated herein by reference.1. Field of the InventionThe present invention relates to an A/D converter which can be applied to a solid-state imaging device typified by a CMOS image sensor, a solid-state imaging device and a camera system.2. Description of the Related ArtAs for the CMOS image sensor, the same manufacturing process as common CMOS-type integrated circuits can be used for the manufacture thereof as well as driving can be performed by a single power source, and further, an analog circuit and a logic circuit using the CMOS process can be mixed on the same chip.Accordingly, the CMOS image sensor has plural big advantages such that the ...

SIGNAL CONVERSION USING STATE SENSITIVE DEVICE ARRAYS

An analog to digital conversion device and method utilizing an array of state sensitive cells. A gate timing component selectively exposes each cell to an analog input signal to effect a change in the exposed cell's state. Upon shielding the cell from exposure, the state change is ascertained by a cell measurement component to determine a digital value representative of the input signal amplitude at exposure. 1. An analog to digital conversion device , the device comprising:a plurality of state sensitive memristor cells, each adapted to selectively receive an analog input signal for conversion;a gate timing control component adapted to selectively determine which of the plurality of state sensitive cells is to receive the analog input signal at a given time; anda cell measurement control component adapted to measure the change in the resistance of each of the plurality of state sensitive cells and to convert the measured change to a digital value representative of the received analog input signal amplitude.2. (canceled)3. The device of claim 1 , wherein the gate timing control component is adapted to selectively allow sequential state sensitive cells to receive the analog input signal at a predetermined regular time interval.4. The device of claim 1 , wherein the gate timing control component is adapted to selectively allow sequential state sensitive cells to receive the analog input signal at an adaptable variable time interval.5. The device of claim 1 , the cell measurement control component further comprising:an analog to digital converter adapted to measure the change in the voltage drop across each of the plurality of state sensitive cells.6. The device of claim 1 , the cell measurement control component further comprising:a comparator circuit, a constant current circuit, and a counter circuit adapted to measure and compare an electrical resistance change of each of the plurality of state sensitive cells after receiving the analog input signal with the ...

Analog-to-digital converter for a capacitive adiabatic logic circuit

An analog-to-digital converter for an adiabatic logic circuit, including at least one variable-capacitance cell, the cell including first and second main terminals and at least one control terminal insulated from its first and second main terminals and capable of receiving a control voltage to vary the capacitance between its first and second main terminals between a low value and a high value, wherein: the cell has its first main terminal coupled to a node of application of a variable periodic converter power supply voltage; the cell has its second main terminal coupled to a node for supplying a binary output signal of the converter; and the cell receives on its first control terminal an analog input voltage of the converter.

REPROGRAMMABLE QUANTUM PROCESSOR ARCHITECTURE INCORPORATING QUANTUM ERROR CORRECTION

A novel and useful quantum computing machine architecture that includes a classic computing core as well as a quantum computing core. A programmable pattern generator executes sequences of instructions that control the quantum core. In accordance with the sequences, a pulse generator functions to generate the control signals that are input to the quantum core to perform quantum operations. A partial readout of the quantum state in the quantum core is generated that is subsequently re-injected back into the quantum core to extend decoherence time. Access gates control movement of quantum particles in the quantum core. Errors are corrected from the partial readout before being re-injected back into the quantum core. Internal and external calibration loops calculate error syndromes and calibrate the control pulses input to the quantum core. Control of the quantum core is provided from an external support unit via the pattern generator or can be retrieved from classic memory where sequences of commands for the quantum core are stored a priori in the memory. A cryostat unit functions to provide several temperatures to the quantum machine including a temperature to cool the quantum computing core to approximately 4 Kelvin.

ANALOG-TO-DIGITAL CONVERTER FOR IMAGE PIXELS

One or more analog-to-digital converters and methods for analog-to-digital conversion are provided. The analog-to-digital converter comprises a ramp generator and a direct current (DC) generator respectively configured to apply a ramp voltage waveform and a DC voltage waveform to a comparator. During a pixel signal level conversion, a first portion of the ramp voltage waveform is applied to the comparator. A control circuit then makes a determination regarding an output of the comparator. If the output corresponds to a first output, or first logic state, the ramp voltage generator applies a second portion of the ramp voltage waveform to the comparator. If the output corresponds to a second output, or second logic state, the DC generator adjusts the DC voltage waveform applied to the comparator. 1. A method for analog-to-digital conversion , comprising:applying a first portion of a ramp voltage waveform to a comparator;making a first determination regarding an output of the comparator responsive to the applying a first portion of a ramp voltage waveform; 'applying a second portion of the ramp voltage waveform to the comparator; and', 'when, based upon the first determination, the output corresponds to a first output 'adjusting a voltage of a direct current (DC) voltage waveform applied to the comparator.', 'when, based upon the first determination, the output corresponds to a second output different than the first output2. The method of claim 1 , comprising:making a second determination regarding the output of the comparator responsive to the adjusting; and 'applying the second portion of the ramp voltage waveform to the comparator.', 'when, based upon the second determination, the output corresponds to the first output3. The method of claim 2 , comprising: 'adjusting, again, the voltage of the DC voltage waveform.', 'when, based upon the second determination, the output corresponds to the second output4. The method of claim 1 , the applying a first portion of a ramp ...

Analog-to-Digital Converters and Image Sensor Having the Same

An analog-to-digital converter includes a comparator, a switch, and a counter circuit. The comparator is configured to generate a comparison signal by comparing an analog signal received through a first signal line and a reference signal received through a second signal line. The switch is coupled between the first signal line and the comparator. The switch is open before the analog signal is applied to the first signal line to disconnect the first signal line from the comparator, and is closed after the analog signal is applied to the first signal line to provide the analog signal to the comparator. The counter circuit is configured to generate a digital signal corresponding to the analog signal by performing a count operation in synchronization with a count clock signal based on the comparison signal. 1. An analog-to-digital converter , comprising:a comparator configured to generate a comparison signal by comparing an analog signal received through a first signal line and a reference signal received through a second signal line;a switch coupled between the first signal line and the comparator, the switch being open before the analog signal is applied to the first signal line to disconnect the first signal line from the comparator, the switch being closed after the analog signal is applied to the first signal line to provide the analog signal to the comparator; anda counter circuit configured to generate a digital signal corresponding to the analog signal by performing a count operation in synchronization with a count clock signal based on the comparison signal.2. The analog-to-digital converter of claim 1 , wherein the switch is open during a transient period in which the analog signal is applied to the first signal line such that a voltage of the first signal line is changed claim 1 , and is closed after the voltage of the first signal line is stabilized at a voltage corresponding to the analog signal.3. The analog-to-digital converter of claim 1 , wherein the ...

BATTERY CHARGER, VOLTAGE MONITORING DEVICE AND SELF-DIAGNOSIS METHOD OF REFERENCE VOLTAGE CIRCUIT

A battery charger includes a battery cell, a reference voltage generating section, an A/D converting section including an A/D converter and a control section. The reference voltage generating section includes a first reference voltage circuit generating a first reference voltage and a second reference voltage circuit generating a second reference voltage equal to the first reference voltage. To diagnose the A/D converter, the first reference voltage circuit is used. To diagnose the first reference voltage circuit, a second A/D conversion value obtained by A/D converting a second divided voltage of the second reference voltage via the A/D converter using the first reference voltage is compared with a first reference value obtained by A/D converting a first divided voltage of the first reference voltage via the A/D converter using the first reference voltage when the first reference voltage circuit is normal. 1. A battery charger comprising:a first reference voltage generating circuit that outputs a first reference voltage and a first divided voltage generated by dividing the first reference voltage;a second reference voltage generating circuit that outputs a second reference voltage and a second divided voltage generated by dividing the second reference voltage;an A/D converter that includes a reference voltage input section and an A/D conversion voltage input section; anda switching section that supplies the first reference voltage or the second reference voltage to the reference voltage input section and that supplies one of the first divided voltage, the second divided voltage and a voltage from a battery cell to the A/D conversion voltage input section.2. A battery charger according to claim 1 , further comprising a control section claim 1 ,wherein when the battery cell is monitored, the control section controls the switching section to supply the first reference voltage to the reference voltage input section and to supply the voltage from the battery cell to the ...

REFERENCE SIGNAL GENERATING CIRCUIT, AD CONVERSION CIRCUIT, AND IMAGING DEVICE

A reference signal generating circuit, an AD conversion circuit, and an imaging device are provided. A clock generating unit includes a delay section including delay units, each of which delays an input signal and outputs a delayed signal, and outputs a low-order phase signal based on a signal output from the delay section. A high-order current source cell unit includes high-order current source cells, each of which generates the same constant current. A low-order current source cell unit includes low-order current source cells weighted to generate constant currents having current values that differ by a predetermined proportion of a current value of the constant current generated by the high-order current source cell. Selection of the high-order current source cell is performed based on a clock obtained by dividing a clock based on the low-order phase signal. 1. A reference signal generating circuit , comprising:a clock generating unit that comprises a delay section including delay units, each of which delays an input signal and outputs a delayed signal, and configured to output a low-order phase signal based on a signal output from the delay section;a high-order current source cell unit that comprises high-order current source cells, each of which generates the same constant current;a low-order current source cell unit that comprises low-order current source cells weighted to generate constant currents having current values that differ by a predetermined proportion of a current value of the constant current generated by the high-order current source cell;an adding unit configured to add the constant currents output from the high-order current source cell unit and the low-order current source cell unit; anda converting unit configured to convert an electric current obtained by addition by the adding unit into a voltage, and outputs the voltage,wherein selection of the high-order current source cell is performed based on a clock obtained by dividing a clock based on ...

ANALOG TO DIGITAL CONVERTER

An analog-to-digital converter (“ADC”) has an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal. A second ADC stage is coupled to the first ADC stage and is configured to convert the analog residue signal to a second digital value. At least one of the first ADC stage and the second ADC stage includes a first sub-stage configured to convert an analog signal to a first number of bits of a digital value representing the analog signal, and a second sub-stage configured to convert the analog signal to a second number of bits of the digital value, where the second number of bits is greater than the first number of bits. A controller is coupled to the first and second ADC stages and configured to combine the first digital value and the second digital value into a digital output signal representing the analog input voltage signal. 1. An analog-to-digital converter (“ADC”) , comprising:an input terminal configured to receive an analog input voltage signal;a first ADC stage coupled to the input terminal and configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal;an amplifier receiving the analog residue signal output by the first ADC stage, wherein the amplifier is configured to apply a predetermined gain to the analog residue signal and output the amplified analog residue signal;a second ADC stage coupled to the amplifier to receive the amplified analog residue signal, and configured to convert the amplified analog residue signal to a second digital value;at least one of the first ADC stage and the second ADC stage including a first sub- ...

ANALOG TO DIGITAL CONVERTER

An analog-to-digital converter (“ADC”) has an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal. A second ADC stage is coupled to the first ADC stage and is configured to convert the analog residue signal to a second digital value. At least one of the first ADC stage and the second ADC stage includes a first sub-stage configured to convert an analog signal to a first number of bits of a digital value representing the analog signal, and a second sub-stage configured to convert the analog signal to a second number of bits of the digital value, where the second number of bits is greater than the first number of bits. A controller is coupled to the first and second ADC stages and configured to combine the first digital value and the second digital value into a digital output signal representing the analog input voltage signal. 1. An analog-to-digital converter (“ADC”) , comprising:an input terminal configured to receive an analog input voltage signal;a first ADC stage coupled to the input terminal and configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal;the first ADC stage including a first sub-stage coupled to the input terminal and configured to convert the analog input signal to a first number of bits of the first digital value;the first ADC stage including a second sub-stage coupled to the input terminal and configured to convert the analog input signal to a second number of bits of the first digital value, the second sub-stage configured to output the analog residue signal;a second ADC stage coupled to the first ADC stage and ...

ANALOG TO DIGITAL CONVERTER

An analog-to-digital converter (“ADC”) has an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal. A second ADC stage is coupled to the first ADC stage and is configured to convert the analog residue signal to a second digital value. At least one of the first ADC stage and the second ADC stage includes a first sub-stage configured to convert an analog signal to a first number of bits of a digital value representing the analog signal, and a second sub-stage configured to convert the analog signal to a second number of bits of the digital value, where the second number of bits is greater than the first number of bits. A controller is coupled to the first and second ADC stages and configured to combine the first digital value and the second digital value into a digital output signal representing the analog input voltage signal. 1. An analog-to-digital converter (“ADC”) , comprising:an input terminal configured to receive an analog input voltage signal;a first ADC stage coupled to the input terminal and configured to output a first digital value corresponding to the analog input voltage signal and an analog residue signal corresponding to a difference between the first digital value and the analog input signal;a second ADC stage coupled to the first ADC stage and configured to convert the analog residue signal to a second digital value, wherein the second ADC stage includes a first sub-stage configured to convert the analog residue signal to a first number of bits of the second digital value representing the analog reside signal, and a second sub-stage configured to convert the analog residue signal to a second number of bits of the second digital value, where the second number of bits is ...

AN ANALOGUE-TO-DIGITAL CONVERTER (ADC)

There is provided a dual-slope analog-to-digital converter (ADC), comprising an input signal terminal, configured to provide an analog signal, and a reference signal terminal, configured to provide a predetermined reference signal. The ADC further comprises an integrator, that is operatively coupled to said input signal terminal and said reference signal terminal via a first switch unit, said first switch unit being configured to selectively connect and disconnect said integrator to and from any one of said input signal terminal and said reference signal terminal. In addition, a voltage supply is operatively coupled to said integrator and configured to selectively provide at least one first supply voltage to said integrator via a second switch unit, a comparator is operatively coupled to an output of said integrator at a first comparator input and a predetermined threshold voltage at a second comparator input, configured to provide an actuation signal at a comparator output in accordance with a predetermined comparator logic, and a controller is adapted to control any one of said first switch unit and said second switch unit. The ADC is further adapted to provide a first voltage to said integrator from said voltage supply, so as to integrate over a first time period a first current corresponding to one of said reference signal and said analog signal, and, following said first time period, to provide a second voltage to said integrator from said voltage supply, so as to integrate over a second time period a second current corresponding to the other one of said reference signal and said analog signal, in order to generate a digital output signal corresponding to said analog signal, and wherein said first current and said second current flow in the same direction during respective said first time period and said second time period. 1. A dual-slope analogue-to-digital converter (ADC) , comprising:an input signal terminal, configured to provide an analogue signal, and a ...

Solid-state imaging device, electronic apparatus, and ad converter

The present technology relates to a solid-state imaging device, an electronic apparatus, and an AD converter that are capable of suppressing the occurrence of an error in AD conversion results. The solid-state imaging device includes a pixel section having a plurality of pixels, a comparator for comparing a pixel signal outputted from the pixels with a reference signal, and a counter for counting the time of comparison made by the comparator. The comparator includes a first amplifier for comparing the pixel signal with the reference signal, a second amplifier that has a first transistor and amplifies an output signal of the first amplifier, and a second transistor having the same polarity as the first transistor. A gate of the second transistor is connected to an output end of the first amplifier, and a source and a drain of the second transistor are connected to the same fixed potential as a source of the first transistor. The present technology is applicable, for example, to a CMOS image sensor.

Analog to Digital Converter

An analog to digital converter includes an analog input and a voltage comparator coupled to the analog input for comparing a voltage at the analog input to a digitally synthesized waveform. A digital to analog converter (DAC) generates the digitally synthesized waveform. The DAC includes a plurality of capacitors selectively connected in parallel wherein the period between the selection of capacitors is less than the settling time of the voltage across the capacitors.

TIME DOMAIN A/D CONVERTER GROUP AND SENSOR DEVICE USING THE SAME

A time domain A/D converter group includes a plurality of individual A/D converters, each of the individual A/D converters is connected to a reference signal generation circuit to generate a first reference signal for sweeping in a full scale range and a second reference signal for repeating plurality of times to sweep in a limited voltage range, and each of the individual A/D converters includes a reference voltage selection circuit for switching the first reference signal or the second reference signal, a comparator for comparing an input signal with the first reference signal or the second reference signal, for generating a comparison output signal, an internal A/D converter for performing an A/D conversion using the comparison output signal from the comparator, and an accumulation adder-subtractor for outputting an average signal of A/D conversion values obtained from the A/D conversion when the second reference signal is selected. 1. A time domain A/D converter group comprising a plurality of individual A/D converters ,wherein each of the individual A/D converters is connected to a reference signal generation circuit to generate a first reference signal for sweeping in a full scale range and a second reference signal for repeating plurality of times to sweep in a limited voltage range,wherein each of the individual A/D converters comprises,a reference voltage selection circuit for switching the first reference signal or the second reference signal output from the reference signal generation circuit,a comparator for comparing an input signal with the first reference signal or the second reference signal in accordance with a selection by the reference voltage selection circuit, for generating a comparison output signal,an internal A/D converter for performing an A/D conversion using the comparison output signal from the comparator, andan accumulation adder-subtracter for outputting an average signal of A/D conversion values obtained from the A/D conversion when ...

TIME DOMAIN A/D CONVERTER GROUP AND SENSOR DEVICE USING THE SAME

A time domain A/D converter group includes a plurality of individual A/D converters, each of the individual A/D converters is connected to a reference signal generation circuit to generate a first reference signal for sweeping in a full scale range and a second reference signal for repeating plurality of times to sweep in a limited voltage range, and each of the individual A/D converters includes a reference voltage selection circuit for switching the first reference signal or the second reference signal, a comparator for comparing an input signal with the first reference signal or the second reference signal, for generating a comparison output signal, an internal A/D converter for performing an A/D conversion using the comparison output signal from the comparator, and an accumulation adder-subtractor for outputting an average signal of A/D conversion values obtained from the A/D conversion when the second reference signal is selected. 1. A time domain analog-to-digital (A/D) converter group comprising:a plurality of comparators for comparing an input signal and a reference signal,a plurality of internal A/D converters for obtaining A/D conversion values from comparison output signals from the plurality of comparators, anda plurality of delay locked loop circuits for dividing a cycle of a master clock that supplies a clock to an entire integrated circuit and outputting a multiphase clock with different timings,wherein the plurality of internal A/D converters perform A/D conversion using the multiphase clock.2. The time domain A/D converter group according to claim 1 ,wherein the plurality of internal A/D converters comprises a plurality of latches for holding a logic state of the multiphase clock at a timing given by the comparison output signal.3. The time domain A/D converter group according to claim 1 , further comprising a logic circuit for synthesizing a plurality of clocks corresponding to gray code from the multiphase clock.4. The time domain A/D converter ...

COMPARATOR CIRCUIT, A/D CONVERSION CIRCUIT, AND DISPLAY APPARATUS

A comparator circuit according to the present disclosure includes: a first switch section that selectively takes in a signal voltage; a second switch section that selectively takes in a control waveform; a differential amplifier including a non-inverted input end connected to each of output ends of the first switch section and the second switch section; a capacity section including one end connected to an inverted input end of the differential amplifier and the other end supplied with a reference voltage; and a third switch section that selectively short-circuits the inverted input end and an output end of the differential amplifier. 1. A comparator circuit , comprising:a first switch section that selectively takes in a signal voltage;a second switch section that selectively takes in a control waveform;a capacity section including one end connected to each of output ends of the first switch section and the second switch section;a differential amplifier including an inverted input end connected to the other end of the capacity section and a non-inverted input end supplied with a reference voltage; anda third switch section that selectively short-circuits the inverted input end and an output end of the differential amplifier.2. The comparator circuit according to claim 1 ,wherein the reference voltage is a fixed voltage.3. The comparator circuit according to claim 1 ,wherein the control waveform has a voltage variation of sawtooth waveform.4. The comparator circuit according to claim 1 , whereinthe first switch section and the third switch section are driven by switch control pulses having the same phase, andthe second switch section is driven by a switch control pulse having a phase opposite to that of the first switch section and the third switch section.5. The comparator circuit according to claim 1 , further comprisinga current supply section that is connected to the output end of the differential amplifier and supplies a current according to an output of the ...

COMPARATOR AND ANALOG-TO-DIGITAL CONVERTER USING THE SAME

A comparator includes a first amplification unit suitable for differentially amplifying a pixel signal and a ramp signal, a second amplification unit suitable for amplifying a signal outputted from the first amplification unit and outputting a comparison result, a current control unit suitable for controlling a current flow in response to the comparison result and a current compensation and noise removal unit suitable for compensating for current and removing noise under control of the current control unit. 1. A comparator comprising:a first amplification unit suitable for differentially amplifying a pixel signal and a ramp signal;a second amplification unit suitable for amplifying a signal outputted from the first amplification unit and outputting a comparison result;a current control unit suitable for controlling a current flow in response to the comparison result; anda current compensation and noise removal unit suitable for compensating for current and removing noise under control of the current control unit.2. The comparator of claim 1 , wherein the current control unit comprises:a first transistor that is turned on or off in response to the comparison result; anda second transistor suitable for controlling a current flow between the current control unit and the current compensation and noise removal unit according to a turn-on or turn-off state of the first transistor.3. The comparator of claim 2 , wherein the second transistor includes a replica circuit having the same characteristics as a third transistor provided in the second amplification unit.4. The comparator of claim 2 , wherein the current compensation and noise removal unit comprises:a fourth transistor suitable for compensating for current and removing noise through a current increase/decrease flow, which is opposite to a current decrease/increase flow of the second amplification unit, in response to the turn-on or turn-off state of the first transistor.5. The comparator of claim 4 , wherein the ...

High Resolution Analog to Digital Converter (ADC) with Improved Bandwidth

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to s of kHz (e.g., 200-300 kHz), or even higher. 1. An analog to digital converter (ADC) comprising:a capacitor that is operably coupled to a load and configured to produce a load voltage based on charging by a load current and a digital to analog converter (DAC) output current, wherein the ADC is coupled to the load via a single line;a current sensor that is operably coupled and configured to sense a quantization noise current that is based on the load current and the DAC output current and to generate a signal that is representative of the quantization noise current; receive the load voltage via a first input of the comparator;', 'receive a reference voltage via a second input of the comparator; and', 'compare the load voltage to the reference voltage to generate a comparator output signal;, 'a comparator operably coupled and configured toa digital circuit that is operably coupled to the comparator and configured to process the comparator output signal to generate a first digital output signal that is representative of a difference between the load voltage and the reference voltage;memory that stores operational instructions;one or ...

SIGMA-DELTA MODULATOR WITH TRIMMED REFERENCE VOLTAGE FOR QUANTIZER

A sigma delta modulator includes a first circuit that receives an analog signal and provides an intermediate signal and a first quantizer signal and further includes a first quantizer that receives the first quantizer signal and provides a first quantizer output. Also included are a second input circuit that receives the intermediate signal and provides a second quantizer signal and a second quantizer that receives the second quantizer signal and provides a second quantizer output. The first quantizer includes a programmable circuit having a first reference and a negative of the first reference, a first comparator having a first input coupled to the first quantizer signal, a second input coupled to the first reference and a second comparator having a second input coupled to the first quantizer signal a second input coupled to the negative. The first and second comparators have outputs that form the output of the first quantizer. 1. A sigma delta modulator , comprising:a first input circuit that receives an analog signal and provides an intermediate signal and a first quantizer signal;a first quantizer that receives the first quantizer signal and provides a first quantizer output;a first output circuit that has an input that receives the first quantizer output and provides a first processed signal to a summer;a second input circuit that receives the intermediate signal and provides a second quantizer signal;a second quantizer that receives the second quantizer signal and provides a second quantizer output; anda second output circuit that has an input that receives the second quantizer output and provides a second processed signal to the summer, a programmable reference voltage circuit having a first reference output and a negative of the first reference output;', 'a first comparator having a first input coupled to the first quantizer signal, a second input coupled to the first reference output, and an output as a first portion of the first quantizer output; and', 'a ...

ANALOG-TO-DIGITAL CONVERSION IN PIXEL ARRAYS

An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N≧2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled. 1. An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level and a secondanalog signal level comprising: an input for receiving a ramp signal;', 'an input for receiving at least one clock signal;', 'a set of N counters, where N≧2, wherein the N counters are arranged to use N clock signals which are offset in phase from one another;, 'at least one input for receiving the first analog signal level and the second analog signal level;'}a control stage which is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level and the second analog signal level; andan output stage for outputting the digital value which is a function of values accumulated by the N counters during a period when they are enabled.2. An analog-to-digital converter according to wherein the set of N counters is divided into a first sub-set of counters and a second sub-set of counters claim 1 , and wherein the control stage is arranged to enable the first sub-set of counters or the second sub-set of counters.3. An analog-to-digital converter according to wherein the ...

A/D CONVERTER, SOLID-STATE IMAGE SENSOR AND IMAGING SYSTEM

An A/D converter includes a comparator configured to compare an input voltage and a reference signal changing monotonically with respect to time and output a comparison result signal indicating a comparison result, a pulse signal generation circuit configured to generate a pulse signal in accordance with the comparison result signal, a counting unit configured to receive a first clock signal, and to count the first clock signal from a start of changing a level of the reference signal to when a level of the comparison result signal is changed, and a latch unit configured to latch the pulse signal at a timing which is defined by a plurality of clock signals including a second clock signal in phase with the first clock signal and a third clock signal having a different phase from that of the second clock signal. 1. An A/D converter comprising:a comparator configured to compare an input voltage and a reference signal changing monotonically with respect to time, and output a comparison result signal indicating a comparison result;a pulse signal generation circuit configured to generate a pulse signal in accordance with the comparison result signal;a counting unit configured to receive a first clock signal, and to count the first clock signal from a start of changing a level of the reference signal to when a level of the comparison result signal is changed; anda latch unit configured to latch the pulse signal at a timing which is defined by a plurality of clock signals including a second clock signal in phase with the first clock signal and a third clock signal having a different phase from that of the second clock signal.2. The converter according to claim 1 , wherein digital data having an output signal from the counting unit as upper digit data and an output signal from the latch unit as lower digit data is output.3. The converter according to claim 1 , wherein a pulse width of the pulse signal is larger than a minimum value of a phase difference between the second ...

COMPARATOR CIRCUIT, A/D CONVERSION CIRCUIT, AND DISPLAY APPARATUS

A comparator circuit according to the present disclosure includes: a first switch section that selectively takes in a signal voltage; a second switch section that selectively takes in a control waveform; a differential amplifier including a non-inverted input end connected to each of output ends of the first switch section and the second switch section; a capacity section including one end connected to an inverted input end of the differential amplifier and the other end supplied with a reference voltage; and a third switch section that selectively short-circuits the inverted input end and an output end of the differential amplifier. 1. A comparator circuit , comprising:a first switch section;a second switch section;a capacity section that includes a first end and a second end, wherein the first end of the capacity section is connected to each of an output end of the first switch section and an output end of the second switch section;a differential amplifier that includes:an inverted input end connected to the second end of the capacity section, anda non-inverted input end supplied with a reference voltage; anda third switch section configured to selectively short-circuit the inverted input end and an output end of the differential amplifier.2. The comparator circuit according to claim 1 , wherein the reference voltage is a fixed voltage.3. The comparator circuit according to claim 1 , wherein the second switch section is configured to selectively receive a control waveform.4. The comparator circuit according to claim 1 , whereineach of the first switch section and the third switch section is driven by a first switch control pulse that has a first phase, andthe second switch section is driven by a second switch control pulse that has a second phase opposite to the first phase.5. The comparator circuit according to claim 1 , further comprisinga current supply section connected to the output end of the differential amplifier, wherein the current supply section is ...

CONDITIONAL CORRELATED MULTIPLE SAMPLING SINGLE SLOPE ANALOG-TO-DIGITAL CONVERTER, AND ASSOCIATED IMAGE SENSOR SYSTEM AND METHOD

A conditional correlated multiple sampling (CCMS) single slope (SS) analog-to-digital converter (ADC) is provided. The CCMS SS ADC includes a comparator, arranged to compare an analog signal with a ramp signal and generate a comparison result; and a CCMS control circuit, arranged to determine a swing of the ramp signal according to a magnitude of the analog signal. An image sensor system using the CCMS SS ADC and a method of CCMS SS analog-to-digital conversion are also disclosed. 1. An analog-to-digital converter (ADC) , comprising:a comparator, arranged to compare an analog signal with a ramp signal and generate a comparison result;a switch, including a first ramp input terminal and a second ramp input terminal arranged to receive a first ramp signal and a second ramp signal respectively, wherein the first ramp signal has a first swing greater than a second swing of the second ramp signal;a control circuit, coupled to the comparator and the switch, the control circuit being arranged to receive a signal, and a time period of an assertion of the signal representing a programmable small-swing signal detection region, wherein the control circuit controls the switch to output the first ramp signal or the second ramp signal as the ramp signal according to a magnitude of the analog signal and the time period of the assertion of the signal representing the programmable small-swing signal detection region; andan arithmetic operator arranged to obtain an averaged comparison result based on the comparison result.2. The ADC of claim 1 , wherein when the magnitude of the analog signal is not smaller than a predefined value corresponding to the time period of the assertion of the signal representing the programmable small-swing signal detection region claim 1 , the control circuit selects the first ramp signal to act as the ramp signal; when the magnitude of the analog signal is smaller than the predefined value corresponding to the time period of the assertion of the signal ...

Dual-Path Analog to Digital Converter

Methods and apparatus for processing a signal comprise at least one circuit configured to generate a measured signal during a measured time period and a reference signal during a reference time period. Also included is at least one dual- or multi-path analog-to-digital converter comprising at least a first processing circuit configured to process the measured signal, at least a second processing circuit configured to process the reference signal, and a third processing circuit configured to process both the measured signal and the reference signal. 1. An apparatus comprising:at least one circuit configured to generate a measured signal during a measured time period and a reference signal during a reference time period; andat least one multi-path analog-to-digital converter comprising at least a first processing circuit configured to process the measured signal and a second processing circuit configured to process the reference signal and a third processing circuit configured to process both the measured signal and the reference signal.2. The apparatus of wherein the measured time period and the reference time period are alternating time periods.3. The apparatus of further comprising a control circuit configured to enable the first processing circuit during the measured time period and to enable the second processing circuit during the reference time period.4. The apparatus of wherein the analog-to-digital converter comprises at least one integrator circuit.5. The apparatus of wherein the first processing circuit comprises a first capacitor and the second processing circuit comprises a second capacitor.6. The apparatus of wherein the at least one circuit configured to generate the measured signal and the reference signal comprises at least one magnetic field sensing element.7. The apparatus of wherein the at least one magnetic field sensing element comprises a Hall effect element claim 6 , a magnetoresistive element claim 6 , or both.8. The apparatus of further ...

GENERATING AN ENTROPY SIGNAL

A method includes using an analog-to-digital converter (ADC) to provide an entropy signal at an output of the ADC. The method includes controlling a reference signal to the ADC to cause an internal noise level of the ADC to correspond to more than one least significant bit (LSB) of the ADC. 1. A method comprising:using an analog-to-digital converter (ADC) to provide an entropy signal at an output of the ADC; andcontrolling a reference signal to the ADC to cause an internal noise level of the ADC to correspond to more than one least significant bit (LSB) of the ADC.2. The method of claim 1 , wherein using the ADC to provide the entropy signal comprises coupling at least one signal input of the ADC to ground.3. The method of claim 1 , wherein controlling the reference signal comprises controlling the reference signal to amplify a noise of the ADC.4. The method of claim 3 , wherein using the ADC to provide the entropy signal is associated with a first mode of operation claim 3 , the method further comprising:using the ADC in a second mode of operation to convert an analog input signal provided to the ADC to a digital output signal, the reference signal is regulated to a first level for the second mode of operation, and', 'controlling the reference signal comprises regulating the reference signal to a second level greater than the first level for the first second mode of operation., 'wherein5. The method of claim 4 , further comprising operating switches to select either the first mode of operation or the second mode operation.6. The method of claim 1 , further comprising generating a pseudo random number based at least in part on the entropy signal.7. The method of claim 6 , further comprising performing a cryptographic function based at least in part on the pseudo random number.8. An apparatus comprising:an analog-to-digital converter (ADC) having a reference input;a first voltage source to provide a first voltage;a second voltage source to provide a second voltage ...

SEMICONDUCTOR INTEGRATED CIRCUIT AND IMAGE SENSOR CIRCUIT

The semiconductor integrated circuit includes a first converting circuit that receives the input analog signal, analog-to-digital converts the input analog signal and outputs a resulting first digital signal. The semiconductor integrated circuit includes an amplifier circuit that receives a reference analog signal, which is obtained by the first converting circuit digital-to-analog converting the first digital signal, and the input analog signal and outputs an amplified signal responsive to the difference between the reference analog signal and the input analog signal. The semiconductor integrated circuit includes a second converting circuit that analog-to-digital converts the amplified signal and outputs a resulting second digital signal. The semiconductor integrated circuit includes an output circuit that outputs an output signal obtained by a calculation of the first digital signal and the second digital signal. 1. A semiconductor integrated circuit , comprising:a first converting circuit that receives the input analog signal, analog-to-digital converts the input analog signal and outputs a resulting first digital signal;an amplifier circuit that receives a reference analog signal, which is obtained by the first converting circuit digital-to-analog converting the first digital signal, and the input analog signal and outputs an amplified signal responsive to the difference between the reference analog signal and the input analog signal;a second converting circuit that analog-to-digital converts the amplified signal and outputs a resulting second digital signal; andan output circuit that outputs an output signal obtained by a calculation of the first digital signal and the second digital signal.2. The semiconductor integrated circuit according to claim 1 , wherein the first converting circuit comprises:a digital-to-analog converting circuit that digital-to-analog converts the first digital signal and outputs the reference analog signal;a comparator that receives ...

ANALOG-TO-DIGITAL CONVERTER FOR A MULTI-CHANNEL SIGNAL ACQUISITION SYSTEM

An analog-to-digital converter (ADC) for a multi-channel signal acquisition system, a signal acquisition system, a method of generating a digital output code from an analog input signal, and a method of converting a plurality of analog signals to a digital signal are provided. The ADC comprises a sample-and-hold (S/H) circuit operable to receive an analog input signal for each input channel; a digital-to-analog converter (DAC) common to all input channels; a comparator for each input channel configured to receive an output signal from the S/H circuit of the respective input channel, and an output signal from the DAC, for generating a comparison result of the two signals at each conversion cycle of the comparator; and a successive approximation register (SAR) common to all input channels and configured to generate, for each input channel, a digital output code based on the comparison results received from the respective comparator. 1. An analog-to-digital converter (ADC) for a multi-channel signal acquisition system , the ADC comprising:a sample-and-hold (S/H) circuit for each input channel, and operable to receive a respective analog input signal for each input channel;a digital-to-analog converter (DAC) common to all input channels;a comparator for each input channel, said comparator configured to receive an output signal from the S/H circuit of the respective input channel as a first input signal, and an output signal from the DAC as a second input signal, for generating a comparison result at each conversion cycle of the comparator; anda successive approximation register (SAR) common to all input channels and configured to generate, for each input channel, a digital output code based on the comparison results received from the respective comparator.2. The ADC as claimed in claim 1 , wherein the SAR is further configured to generate control signals based on the comparison result at each conversion cycle of the comparator claim 1 , for controlling switches in the ...

Single-ended Linear Current Operative Analog to Digital Converter (ADC) with Thermometer Decoder

A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher. 1. An analog to digital converter (ADC) comprising:a capacitor operably coupled to a load and configured to produce a load voltage based on charging by a load current and a digital to analog converter (DAC) output current, wherein the ADC is coupled to the load via a single line;processing circuitry operably coupled to the capacitor, wherein, when enabled, the processing circuitry configured to generate a digital output signal based on the load voltage;a thermometer decoder operably coupled to the processing circuitry, wherein, when enabled, the thermometer decoder configured to process the digital output signal to generate thermometer code output symbols based on a thermometer code; andat least one of a plurality of PNP BJTs (Positive-Negative-Positive Bipolar Junction Transistors) or a plurality of NPN BJTs (Negative-Positive-Negative Bipolar Junction Transistors) operably coupled to the thermometer decoder, wherein, when enabled, the at least one of the plurality of PNP BJTs or the plurality of NPN BJTs configured to generate at least one of a source current or a sink current based ...

ANALOG-TO-DIGITAL CONVERTER AND IMAGE SENSOR

An analog-to-digital converter has a comparator to compare, within a predetermined period, an input signal with a ramp signal or with a triangle wave signal, a first counter to count up or down in accordance with a logic of a signal that indicates a comparison result of the comparator within the predetermined period, a count value storage to sequentially store count values of the first counter whenever the logic of the signal that indicates a comparison result of the comparator changes within the predetermined period, a second counter to count the number of times the logic of the signal that indicates a comparison result of the comparator changes, and an arithmetic module to output a value obtained by adding up the count values stored in the count value storage and dividing the added-up value by a count value of the second counter. 1. An analog-to-digital converter comprising:a comparator to compare, within a predetermined period, an input signal with a ramp signal whose signal level monotonically increases or monotonically decreases with time, or with a triangle wave signal that alternately repeats monotonic increase and monotonic decrease with time;a first counter to count up or down in accordance with a logic of a signal that indicates a comparison result of the comparator within the predetermined period;a count value storage to sequentially store count values of the first counter whenever the logic of the signal that indicates a comparison result of the comparator changes within the predetermined period;a second counter to count the number of times the logic of the signal that indicates a comparison result of the comparator changes; andan arithmetic module to output a value obtained by adding up the count values stored in the count value storage and dividing the added-up value by a count value of the second counter, as an analog-to-digital conversion value of the input signal.2. The converter of claim 1 , the ramp signal has a signal level that monotonically ...

CIRCUITS AND METHODS PROVIDING BANDGAP CALIBRATION FOR MULTIPLE OUTPUTS

A method and an apparatus to provide bandgap calibration for multiple outputs are disclosed. In one implementation, a computing chip includes a bandgap current generator; a first adjustable current output coupled to the bandgap current generator; a second adjustable current output coupled to the bandgap current generator; a first switch selectively coupling the first adjustable current output to a calibration circuit and to a first analog-to-digital converter (ADC); and a second switch selectively coupling the second adjustable current output to a load on the computing chip and to the ADC. 1. A computing chip comprising:a bandgap current generator;a first adjustable current output coupled to the bandgap current generator;a second adjustable current output coupled to the bandgap current generator;a first switch configured to selectively couple the first adjustable current output to an external device and to a first analog-to-digital converter (ADC) on the computing chip; anda second switch configured to selectively couple the second adjustable current output to a load on the computing chip and to the ADC.2. The computing chip of claim 1 , wherein the load on the computing chip comprises a second analog-to-digital converter (ADC).3. The computing chip of claim 1 , wherein the load on the computing chip comprises a low drop out (LDO) voltage regulator.4. The computing chip of claim 1 , further comprising a feedback loop from the first ADC to the second adjustable current output.5. The computing chip of claim 1 , wherein the first adjustable current output comprises a current digital-to-analog converter (DAC).6. The computing chip of claim 1 , further comprising:a third switch configured to selectively couple the first ADC to a reference load.7. The computing chip of claim 1 , wherein the second switch comprises a switching network having a third switch coupling the second adjustable current output to the load on the computing chip and a fourth switch coupling the ...

DOUBLE DATA RATE COUNTER, AND ANALOG-TO-DIGITAL CONVERTER AND CMOS SENSOR INCLUDING THE SAME

A double data rate (DDR) counter includes a first control block suitable for toggling a counter clock according to a count mode signal and a previous state value of a sampling block; a second control block suitable for determining whether to toggle a clock signal inputted to a counting block corresponding to an (LSB+1) bit or higher; a third control block suitable for determining an enable period of the counting block; the sampling block suitable for sampling a state of the clock signal and outputting an LSB value, when an input signal transits; and the counting block suitable for performing counting according to output signals of the second and third control blocks and outputting a counter output signal having the (LSB+1) bit or higher. 1. A double data rate (DDR) counter comprising:a first control block suitable for toggling a counter clock according to a count mode signal and a previous state value of a sampling block;a second control block suitable for determining whether to toggle a clock signal inputted to a counting block corresponding to an (LSB+1) bit or higher;a third control block suitable for determining an enable period of the counting block;said sampling block suitable for sampling a state of the clock signal and outputting an LSB value when an input signal transits; andsaid counting block suitable for performing counting according to output signals of the second and third control blocks and outputting a counter output signal having the (LSB+1) bit or higher.2. The DDR counter of claim 1 , wherein the first and second control blocks determine whether to toggle the clock signal between first and second counting operations.3. The DDR counter of claim 1 , wherein the counting block performs counting at rising edges of the clock signal from the (LSB+1) bit during a first counting operation claim 1 , and performs counting at falling edges of the clock signal from the (LSB+1) bit during a second counting operation.4. The DDR counter of claim 1 , wherein the ...

Solid-state imaging device and camera system

A solid-state imaging device and a camera system are provided. The solid-state imaging device capable of performing an intermittent operation includes a pixel unit and a pixel signal readout unit for reading out a pixel signal from the pixel unit in units of a plurality of pixels for each column. The pixel signal readout circuit includes a plurality of comparators and a plurality of counters whose operations are controlled by outputs of the comparators. Each of the comparators includes an initializing switch for determining an operating point for each column at a start of row operation, and is configured so that an initialization signal to be applied to the initializing switch is controlled independently in parallel only a basic unit of the initialization signal used for a horizontal intermittent operation, and the initializing switch is held in an off-state at a start of non-operating row.

CURRENT INJECTION FOR FAST RAMP START-UP DURING ANALOG-TO-DIGITAL OPERATIONS

An example method for fast ramp start-up during analog to digital conversion (ADC) includes opening a feedback bypass switch coupled to an amplifier to initiate an ADC operation, providing an injection current pulse to an inverting input of the amplifier, where the non-inverting input is coupled to a feedback bypass switch, integrating a first reference current coupled to the inverting input of the amplifier, where the integrating of the first reference current occurs due to the opening of the feedback bypass switch, and providing a reference voltage in response to the injection current pulse, the integrating of the first reference current, and a reference voltage coupled to a non-inverting input of the amplifier, where a level of the reference voltage is increased at least at initiation of the ADC operation in response to the injection current pulse. 1. A method , comprising:opening, in response to a first control signal, a feedback bypass switch coupled to an amplifier to initiate an analog-to-digital conversion (ADC) operation;providing, by a current injection circuit, an injection current pulse to an inverting input of the amplifier, wherein the non-inverting input is coupled to the feedback bypass switch;integrating a first reference current coupled to the inverting input of the amplifier, wherein the integrating of the first reference current occurs due to the opening of the feedback bypass switch; andproviding, by the amplifier, a reference voltage in response to the injection current pulse, the integrating of the first reference current, and a reference voltage coupled to a non-inverting input of the amplifier,wherein a level of the reference voltage is increased at least at initiation of the ADC operation at least in response to the injection current pulse.2. The method of claim 1 , further comprising:generating, by the current injection circuit, an injection current in response to a second control signal, wherein the second control signal determines a ...

Quantizer

In one embodiment the quantizer includes a signal-to-phase converter configured to generate a phase signal according to an input signal and a phase difference digitization block configured to generate a quantization output according to differentiated samples of the phase signal, where the phase signal generated by the signal-to-phase converter has a sinusoidal shape. 1. A quantizer comprising:a signal-to-phase converter configured to generate a phase signal according to an input signal; anda phase difference digitization block configured to generate a quantization output according to differentiated samples of the phase signal, where the phase signal generated by the signal-to-phase converter has a sinusoidal shape.2. The quantizer of claim 1 , wherein the signal-to-phase converter is configured to generate a multiplicity of phase signals according to the input signal claim 1 , and wherein the phase difference digitization block is configured to generate a multiplicity of quantization outputs according to differentiated samples of the phase signals.3. The quantizer of claim 2 , wherein the signal-to-phase converter comprises one controllable oscillator with a differential phase output.4. The quantizer of claim 2 , wherein the signal-to-phase converter comprises two controllable oscillators each with a non-differential phase output.5. The quantizer of claim 2 , wherein the signal-to-phase converter comprises at least one controllable oscillator with a differential circuit structure.6. The quantizer of claim 1 , wherein the phase difference digitization block comprises:a sampler configured to sample the phase signal and generate a quantized phase signal; anda phase differentiator coupled to the sampler and configured to generate the quantization output by differentiating the quantized phase signal(s).7. The quantizer of claim 1 , wherein the signal-to-phase converter is a voltage or current controlled sinus oscillator.8. The quantizer of claim 1 , wherein the signal-to ...

ANALOG-TO-DIGITAL CONVERTER CONFIGURED TO OPERATE AT HIGH SPEED AND IMAGE SENSOR INCLUDING THE SAME

Provided is an image sensor including a pixel array including a plurality of pixels and an analog-to-digital converter (ADC) configured to compare a reference voltage with an analog voltage output by the pixel array and latch and decode a comparison result. The ADC is controlled in response to clock information and a counter clock, which are obtained by expanding and encoding a master clock. 1. An image sensor comprising:a pixel array including a plurality of pixels; and generate a comparison result by comparing a reference voltage with an analog voltage output by the pixel array,', 'latch and decode the comparison result, and', 'generate encoded clock information and a counter clock by expanding and encoding the master clock., 'an analog-to-digital converter (ADC) configured to receive a master clock, the ADC configured to,'}2. The image sensor of claim 1 , wherein the ADC comprises:comparators configured to compare the reference voltage with the analog voltage output by the pixel array and output the comparison result;a control signal generator configured to generate the encoded clock information and the counter clock in response to the master clock; andlatches configured to latch in response to the encoded clock information and the counter clock to latch the comparison result.3. The image sensor of claim 2 , wherein the control signal generator comprises:a first latch controller configured to expand the master clock, generate a multi-phase clock, and provide the encoded clock information to at least one of the latches as a first latch control signal; anda second latch controller configured to provide a second latch control signal to at least one of the latches, the second latch control signal sequentially increasing in response to the master clock.4. The image sensor of claim 3 , wherein the first latch controller comprises:a delay locked loop (DLL) circuit configured to generate a multi-phase clock having a phase difference in response to the master clock;a ...

AD CONVERTER, AD CONVERSION DEVICE, PHOTOELECTRIC CONVERSION APPARATUS, IMAGING SYSTEM, AND AD CONVERSION METHOD

In a case where a magnitude of an analog signal falls below a first threshold value, a comparator compares the analog signal with a first reference signal so as to obtain a p-bit digital signal. In a case where the magnitude of the analog signal exceeds the first threshold value, the comparator compares the analog signal with a second reference signal, which has a higher rate of change relative to time than the first reference signal, so as to obtain a q-bit digital signal, where q is less than p. 1. An AD converter configured to convert an analog signal to a digital signal ,wherein a magnitude of the analog signal is compared with a first threshold value, and(a) in a case where the magnitude of the analog signal falls below the first threshold value, the analog signal is converted to a p-bit digital signal, or(b) in a case where the magnitude of the analog signal exceeds the first threshold value, the analog signal is converted to a q-bit digital signal, where q is less than p.2. The AD converter according to claim 1 , wherein the analog signal is compared with a reference signal of which a signal level varies so as to convert the analog signal to the digital signal.3. The AD converter according to claim 2 ,wherein the analog signal is compared with a rate of change of a first reference signal relative to time so as to convert the analog signal to the p-bit digital signal, andwherein the analog signal is compared with a rate of change of a second reference signal relative to time so as to convert the analog signal to the q-bit digital signal, the rate of change of the second reference signal relative to time being higher than the rate of change of the first reference signal relative to time.4. The AD converter according to claim 3 , wherein the first threshold value is a signal level that is lower than a maximum value of the second reference signal.5. The AD converter according to claim 3 , wherein claim 3 , in a case where the rate of change of the second ...

FLASH ADC SHUFFLING

A flash ADC circuit may include a reference ladder providing reference signals and a plurality of comparators, each providing an output based on a comparison of a pair of input signals to a pair of reference signals. At least one pair of the comparators may receive the same pair of reference signals with a different orientation of the reference signals at each of the comparators. The flash ADC may include a switch network for swapping the pair of reference signals between the pair of comparators. 1. A flash analog-to-digital circuit , comprising:a reference ladder providing reference signals;a plurality of comparators, each providing an output based on a comparison of a pair of input signals to a pair of reference signals, at least one pair of the comparators receiving the same pair of reference signals with a different orientation of the reference signals at each of the comparators; anda switch network for swapping the pair of reference signals between the pair of comparators.2. The circuit of claim 1 , wherein the plurality of comparators include a plurality of pairs of comparators claim 1 , each pair of comparators receiving a different pair of reference signals from the reference ladder.3. The circuit of claim 2 , wherein the switch network swaps the pair of reference signals between the pair of comparators in each pair of comparators.4. The circuit of claim 2 , wherein the switch network randomly selects in which pairs of comparators to perform the swapping of the pair of reference signals between the pair of comparators.5. The circuit of claim 2 , wherein the switch network selects a different set of pairs of comparators in which to perform the swapping of the pair of reference signals claim 2 , each time the input signals are sampled by the comparators.6. The circuit of claim 2 , wherein:the outputs of the comparators are coupled to corresponding unit elements of a digital-to-analog converter; andthe switch network performs shaping of mismatch between the ...

CIRCUIT ARRANGEMENT AND METHOD FOR OPERATING AN ANALOG-TO-DIGITAL CONVERTER

Circuit arrangement, including a first resistor, a second resistor, a current source and an analog-to-digital converter. The second resistor is thermally coupled to the first resistor. The current source is coupled to the second resistor. The analog-to-digital converter is configured to receive a first voltage measured via the first resistor as a voltage to be digitized, and is configured to receive a second voltage measured via the second resistor as a reference voltage of the analog-to-digital converter. 1. A circuit arrangement , comprising:a first resistor;a second resistor thermally coupled to the first resistor;a current source coupled to the second resistor; andan analog-to-digital converter configured to receive a first voltage measured via the first resistor as a voltage to be digitized, and to receive a second voltage measured via the second resistor as a reference voltage of the analog-to-digital converter.2. The circuit arrangement of claim 1 ,wherein the first resistor and the second resistor are made of the same material.3. The circuit arrangement of claim 1 , copper;', 'polysilicon;', 'aluminum; and', 'gold., 'wherein the first resistor and the second resistor are made of a material selected from a group consisting of4. The circuit arrangement of claim 1 ,wherein the first resistor and the second resistor are monolithically integrated in a same semiconductor chip.5. The circuit arrangement of claim 4 ,wherein the first resistor and the second resistor are formed in at least one metallization layer of the semiconductor chip.6. The circuit arrangement of claim 5 ,wherein a metallization layer of the first resistor and a metallization layer of the second resistor are arranged adjacent to each other in one of a vertical and a horizontal manner.7. The circuit arrangement of claim 6 ,wherein the metallization layer of the first resistor has a thickness that is at least 10 times greater than a thickness of the metallization layer of the second resistor.8. ...

Analog-to-digital converters

An analog-to-digital converter ADC may be provided. The ADC may include a current driving circuit. The current driving circuit may include an additive current driving circuit and a subtractive current driving circuit configured for adjusting a voltage level of a node. The ADC may include a comparison circuit including a plurality of comparators. Each of the plurality of comparators may be configured to compare a voltage level of the node with a reference voltage.

FLASH ANALOG-TO-DIGITAL CONVERTER CALIBRATION

An analog-to-digital converter (ADC) is a device that can include a reference shuffler and a loop filter. An ADC can achieve better performance with incremental adjustment of a pointer of the reference shuffler, changing coefficients of the loop filter, and storing calibration codes of the ADC in a non-volatile memory. By incrementally adjusting a pointer of the reference shuffler, a calibration can be performed more efficiently than with a random adjustment of the pointer. By temporarily changing the loop filter coefficients, a greater amount of activity can be introduced into the loop filter. This activity can allow the calibration to proceed more efficiently. By storing the calibration codes in a non-volatile memory, a search space for calibration codes can be reduced. Thus, a calibration can occur more quickly, and the calibration itself can be improved. 1. A system for calibrating an analog-to-digital converter , the system comprising: a comparator that compares the analog input to a reference voltage, and', 'a reference shuffler that shuffles a reference for the reference voltage of the comparator, the comparator to convert the analog input to digital data based on the reference;, 'the analog-to-digital converter, which receives an analog input and includes'}an RMS meter that measures a power of the digital data;calibration logic that calibrates the analog-to-digital converter based on the power of the digital data; anda nonvolatile memory that stores a calibration code for the analog-to-digital converter.2. The system of claim 1 , wherein the calibration logic stores the calibration code to the nonvolatile memory.3. The system of claim 1 , wherein the calibration logic retrieves the calibration code from the nonvolatile memory.4. The system of claim 1 , wherein the calibration logic determines whether the power of the digital data is less than a predetermined value.5. The system of claim 1 , wherein the calibration logic determines a calibration code that ...

Solid state imaging device and method of driving solid state imaging device

A solid state imaging device includes a pixel circuit 102 configured to generate a pixel signal by photoelectric conversion, a reference signal generation circuit 115 configured to generate a reference signal which changes in level with time, and a plurality of comparators configured to, based on the reference signal generated by the reference signal generation circuit, compare a plurality of reference signals being given offset voltages differing from each other, with the pixel signal, or compare a plurality of pixel signals being given offset voltages differing from each other, with the reference signal.

Microcontroller With Digital Delay Line Analog-to-Digital Converters And Digital Comparators

Embodiments of the present disclosure include a microcontroller with a processor core, memory, and a plurality of peripheral devices including a differential digital delay line analog-to-digital converter (ADC). The ADC includes differential digital delay lines and circuit comprising a set of delay elements included in the differential digital delay lines configured to generate data representing an analog to digital conversion of an input. The microcontroller also includes a digital comparator coupled with an output of the ADC and an associated register, wherein at least one output of the digital comparator is configured to directly control another peripheral of the plurality of peripherals.

ANALOG-TO-DIGITAL CONVERTER AND IMAGE SENSOR

An analog-to-digital converter has a sampler to hold a sampled signal, an input signal predictor to generate a prediction signal at predetermined timing before a signal level of a ramp signal that monotonically increases or monotonically decreases with time crosses a signal level of the sampled signal, a comparator to compare signal levels of the ramp signal and the sampled signal to output a comparison signal showing whether the signal level of the ramp signal is larger than the signal lever of the sampled signal, a first counter to perform a count operation in synchronism with a first clock signal within a period from start of a comparison operation by the comparator to generation of the prediction signal, and a second counter to perform a count operation in synchronism with a second clock signal. 1. An analog-to-digital converter comprising:a sampler to hold a sampled signal obtained by sampling an input signal for each specific time;an input signal predictor to generate a prediction signal at predetermined timing before a signal level of a ramp signal that monotonically increases or monotonically decreases with time crosses a signal level of the sampled signal;a comparator to compare signal levels of the ramp signal and the sampled signal to output a comparison signal showing whether the signal level of the ramp signal is larger than the signal lever of the sampled signal;a first counter to perform a count operation in synchronism with a first clock signal within a period from start of a comparison operation by the comparator to generation of the prediction signal; anda second counter to perform a count operation in synchronism with a second clock signal having a higher frequency than the first clock signal after the generation of the prediction signal and to increase or decrease a count value in accordance with the comparison signal.2. The converter of claim 1 , wherein the input signal predictor comprises a bias signal generator to generate a bias signal ...

ANALOGUE-TO-DIGITAL CONVERTER

An analogue-to-digital converter for converting an analogue input signal into a digital output signal, the analogue-to-digital converter including two conversion paths, each configured to receive a version of the analogue input signal and convert it into a digital bit stream, a first feedback loop configured to provide feed-back, to both paths, that is indicative of a difference between the digital bit streams output by the two paths, and a second feedback loop configured to feed-back, to both paths, that is indicative of an average of the digital bit streams output by the two paths. 1. An analogue-to-digital converter for converting an analogue input signal into a digital output signal , the analogue-to-digital converter comprising:two conversion paths, each configured to receive a version of the analogue input signal and convert it into a digital bit stream;a first feedback loop configured to provide feed-back, to both paths, that is indicative of a difference between the digital bit streams output by the two paths; anda second feedback loop configured to feed-back, to both paths, that is indicative of an average of the digital bit streams output by the two paths.2. The analogue-to-digital converter as claimed in claim 1 , a first one of the conversion paths being configured to apply a positive gain to its version of the analogue input signal.3. The analogue-to-digital converter as claimed in claim 1 , a second one of the conversion paths being configured to apply a negative gain to its version of the analogue input signal.4. The analogue-to-digital converter as claimed in claim 1 , comprising a selection unit configured to form the digital output signal by alternately selecting between the digital bit streams output by the two conversion paths.5. The analogue-to-digital converter as claimed in claim 3 , the selection unit being configured to invert the digital bit stream output by the second conversion path before selecting it to form the digital output signal.6. ...

SENSING AN EXTERNAL STIMULUS USING A GROUP OF CONTINUOUS-TIME NYQUIST RATE ANALOG-TO-DIGITAL CONVERTERS IN A ROUND-ROBIN MANNER

Facilitating a reduction in sensor system latency, circuit size, and current draw utilizing a group of continuous-time Nyquist rate analog-to-digital converters (ADCs) in a round-robin manner is presented herein. A sensor system can comprise a group of sensors that generate respective sensor output signals based on an external excitation of the sensor system; a multiplexer that facilitates a selection, based on a sensor selection input, of a sensor output signal of the respective sensor output signals corresponding to a sensor of the group of sensors; a sense amplifier comprising a charge or voltage sensing circuit that converts the sensor output signal to an analog output signal; and a continuous-time Nyquist rate analog-to-digital converter of the group of continuous-time Nyquist rate ADCs that converts the analog output signal to a digital output signal representing at least a portion of the external excitation of the sensor system. 1. A sensor system , comprising:a group of sensors that generate respective sensor output signals based on an external excitation of the sensor system;a multiplexer that facilitates a selection, based on a sensor selection input, of a sensor output signal of the respective sensor output signals corresponding to a sensor of the group of sensors;a sense amplifier comprising a charge or voltage sensing circuit that converts the sensor output signal to an analog output signal; anda continuous-time Nyquist rate analog-to-digital converter (ADC) of a group of continuous-time Nyquist rate ADCs that converts the analog output signal to a digital output signal representing at least a portion of the external excitation of the sensor system.2. The sensor system of claim 1 , wherein the sensor comprises an accelerometer claim 1 , a gyroscope claim 1 , a magnetic sensor claim 1 , a pressure sensor claim 1 , or a microphone.3. The sensor system of claim 1 , wherein the charge or voltage sensing circuit comprises a charge-to-voltage (C2V) converter ...

Bulk Driven Low Swing Driver

A circuit is presented to reduce power while transmitting high speed signals across a long length of wire on an integrated circuit. A PMOS is used as a low swing driver, where the PMOS is connected between the driver's output and ground. The gate of the PMOS is also set to ground, while the input signal is connected to the bulk. The output is then transmitted over the signal path to an analogue receiver, where both single ended and differential embodiments are presented. For a single ended version, a reference voltage for the receiver can be provided by a second, similarly connected PMOS whose bulk has an input signal at an intermediate level of input swing at the transmitter PMOS. 1. A circuit for the high speed transfer of a digital signal over a data path , comprising:an analog receiver circuit connected to receive a first intermediate analog signal and generate therefrom a digital output signal;an intermediate signal path connected to the analog receiver circuit to supply the first intermediate analog signal thereto; and a first current source connected between a voltage supply and the first output node to supply a fixed current level thereto; and', 'a first PMOS device connected between the first output node and ground, wherein a gate of the first PMOS device is set to ground and the digital input signal is connected to a bulk input of the first PMOS device., 'a first transmitter circuit connected to receive a digital input signal and having a first output node connected to the intermediate signal path to provide the first intermediate analog signal thereto, the first transmitter circuit including2. The circuit of claim 1 , wherein the analog receiver circuit includes a difference amplifier having a first input connected to receive the first intermediate analog signal and a second input connected to receive a first reference voltage.3. The circuit of claim 2 , further comprising: a second current source connected between the voltage supply and a node from which ...

HIGH SPEED DATA TRANSFER FOR ANALOG-TO-DIGITAL CONVERTERS

This disclosure describes techniques for transferring data from an analog-to-digital converter (ADC) to a host device. The techniques may determine whether an ADC is operating in a quiet conversion time period, and selectively deactivate a digital data output of the ADC when the ADC is operating in the quiet conversion time period. This may allow an ADC to transfer data during both the conversion and acquisition phases of the ADC (rather than just during the acquisition phase), thereby increasing the data throughput of the ADC for a given transfer clock speed. The techniques may further allow data to be transferred during the conversion phase of an ADC without requiring a host device to be aware of the quiet conversion time period requirements of the ADC. In this way, the data throughput of an ADC data transfer may be increased with relatively little additional complexity added to a host device. 1. An analog-to-digital converter (ADC) comprising:an analog input lead;a digital output lead;a conversion circuit having an analog input coupled to the analog input lead, and a digital output;a quiet conversion time period determination circuit coupled to the conversion circuit, the quiet conversion time period determination circuit having a quiet conversion time period notification output; andan output circuit having a data input coupled to the digital output of the conversion circuit, a control input coupled to the quiet conversion time period notification output of the quiet conversion time period determination circuit, and a data output coupled to the digital output lead.2. The ADC of claim 1 , wherein the digital output lead forms a digital output for the ADC claim 1 , and wherein the output circuit is configured to selectively activate and deactivate the digital output based on whether the ADC is operating in the quiet conversion time period.3. The ADC of claim 2 , further comprising:an input clock lead configured to receive a clock signal,wherein the output circuit ...

SINGLE PHASE ANALOG COUNTER FOR A DIGITAL PIXEL

An analog counter circuit for use with a digital pixel includes: an input; an output; a first stage electrically coupled to the input that is charged to an initial charge voltage; a second stage that includes an accumulating charge storage device; and a charge transfer device between the first and second stages that includes a transfer voltage. The charge transfer device allows charge from the first stage to pass to the second stage and be accumulated on the accumulating charge storage device as long as a voltage at a node in the first stage is greater than the transfer voltage. 1. An analog counter circuit for use with a digital pixel , the analog counter circuit comprising:an input;an output;a first stage electrically coupled to the input that is charged to an initial charge voltage;a second stage that includes an accumulating charge storage device; anda charge transfer device between the first and second stages that includes a transfer voltage, wherein the charge transfer device allows charge from the first stage to pass to the second stage and be accumulated on the accumulating charge storage device as long as a voltage at a node in the first stage is greater than the transfer voltage.2. The analog counter circuit of claim 1 , wherein when a RESET signal is received at the input transitions from a low level to a high level claim 1 , the voltage at the node rises from the initial charge voltage to a charge voltage claim 1 , wherein the charge voltage is a sum of the initial charge voltage and an amplitude of the RESET signal.3. The analog counter circuit of claim 2 , wherein the transfer device includes an input connected to the first stage and an output connected to the second stage.4. The analog counter circuit of claim 3 , wherein the transfer device includes a gate that is connected to a gate bias voltage claim 3 , wherein the transfer voltage is a sum of the gate bias voltage and a threshold voltage of the transfer device.5. The analog counter circuit of ...

Time-Based Delay Line Analog-to-Digital Converter With Variable Resolution

Embodiments of the present disclosure include a differential digital delay line analog-to-digital converter (ADC), comprising differential digital delay lines including series coupled delay cells, wherein a delay time of a first delay line is controlled by a first input of the ADC and a delay time of a second delay line is controlled by a second input of the ADC. The ADC includes a pair of bypass multiplexers coupled at a predefined node location in the series coupled delay cells, latches each coupled with the series coupled delay cells, a converter circuit coupled with the plurality of latches configured to convert data from the latches into an output value of the ADC, and logic circuits configured to select data from the series coupled delay cells to the latches depending on a selected resolution of the differential digital delay line analog-to-digital converter. 118-. (canceled)19. A differential digital delay line analog-to-digital converter (ADC) , comprising:differential digital delay lines comprising a plurality of series coupled delay cells, wherein a delay time of a first delay line is related to a first voltage at an input of the ADC and a delay time of a second delay line is related to a second voltage at the input of the ADC;a first bypass circuit communicatively coupled at a predefined node location in the series coupled delay cells;a plurality of storage circuits each coupled with the series coupled delay cells;a converter circuit coupled with the plurality of storage circuits configured to convert data from the storage circuits into an output value of the ADC; anda plurality of logic circuits configured to select data from the storage circuits depending on a selected resolution of the differential digital delay line analog-to-digital converter.20. The ADC of claim 19 , wherein the first bypass circuit includes a multiplexer.21. The ADC of claim 19 , wherein the first bypass circuit is placed at a 50% point of the series coupled delay cells.22. The ADC ...