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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 16368. Отображено 100.
05-01-2012 дата публикации

System and method for multi-dimensional encoding and decoding

Номер: US20120001778A1
Принадлежит: Individual

A system and method for decoding multi-dimensional encoded data. A set of multi-dimensional encoded data may be received encoding each input bit in a set of input bits by multiple different component codes in multiple different encoding dimensions. The multi-dimensional data may potentially have errors. A map may be used to locate each set of intersection bits that encode the same input bit by multiple unsolved component codes. The unsolved component codes may be decoded using one or a plurality of tested error correction hypotheses that yields a decoding success, where each hypothesis correcting a different set of intersection bits for a different input bit. The successful hypothesis may be applied for correcting the multi-dimensional encoded data.

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05-01-2012 дата публикации

Data processing apparatus and method

Номер: US20120002739A1
Автор: Jean-Luc Peron
Принадлежит: Sony Europe Ltd

A data processing apparatus maps input symbols to be communicated onto a predetermined number of carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM carrier signals. The interleaver memory reads-out the data symbols on to the OFDM carriers to effect the mapping, the read-out being in a different order than the read-in, and the order being determined from a set of addresses. The set of addresses are generated from an address generator. The address generator includes a linear feedback shift register and a permutation circuit.

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12-01-2012 дата публикации

Method for encoding data with double-interlaced parity symbols, for a radio infrastructure, and associated codec

Номер: US20120008706A1
Принадлежит: Alcatel Lucent SAS

A method is dedicated to encoding data that must be transmitted by means of a wave-based transmission infrastructure, and comprises i) a step consisting of creating in parallel M first matrices having T rows and C columns with subsets of data from B successive received bursts, the subsets of data from each burst being distributed within at least two successive first matrices, ii) a step consisting of creating in parallel M second matrices each having T rows and N columns with parity symbols resulting from encoding the data that is respectively contained in the rows of each of the M first matrices, iii) a step consisting of creating in parallel M first matrices having K rows and C columns with parity symbols resulting from encoding the data that is respectively contained in the columns of each of the M first matrices, and iv) a step consisting of distributing by interlacing, firstly, J subsets of parity symbols from each second matrix into J successive sets, and secondly P subsets of parity symbols from each third matrix into P of these successive sets, and of placing into each of the successive sets the respective data from the successive received bursts.

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16-02-2012 дата публикации

Bitwise reliability indicators from survivor bits in viterbi decoders

Номер: US20120042228A1
Принадлежит: NXP BV

Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.

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01-03-2012 дата публикации

Radio communication device and radio communication method

Номер: US20120051307A1
Автор: Isamu Yoshii, Lei Huang
Принадлежит: Panasonic Corp

To improve the frequency diversity effect by preventing the related bits in the encoded data from being biased to the specified carrier in the case of performing the multicarrier operation. A modulated symbol sequence is segmented in a data segmentation section ( 116 ), and the segmented modulated symbol blocks are mapped on a plurality of carriers in a segment mapping section ( 120 ). The data segmentation section ( 116 ) groups each of K parts in the modulated symbol sequence into the same number of N groups, cyclically shifts the N groups for the respective parts of any (K−1) parts with shift amounts which differ among the parts, and substitutes the cyclically-shifted groups of the plurality of parts in the modulated symbol sequence with one another among the parts to segment the groups into a plurality of blocks.

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01-03-2012 дата публикации

Apparatus and method for transmitting and receiving data in a communication or broadcasting system using linear block code

Номер: US20120051460A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided is a method for transmitting data in a communication or broadcasting system using a linear block code by generating a codeword by encoding input information data bits, interleaving the codeword; outputting modulation signal-constituting bits by bit-mapping the interleaved codeword using a bit-mapping table predetermined depending on a modulation scheme and a coding rate, outputting a modulation signal by modulating the modulation signal-constituting bits and transmitting the modulation signal via a transmit antenna.

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01-03-2012 дата публикации

Data Rearrangement for Decoder

Номер: US20120054579A1
Автор: Petros Oikonomakos
Принадлежит: Nokia Oyj

There is provided a solution for rearranging data to a decoder of a receiver. The solution comprises receiving data, writing the data to one or more memory slots in parts, first in an ascending order of addresses and then in a descending order of addresses. The solution further comprises reading the full memory slots in a descending order of addresses and forwarding the read data to the decoder.

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08-03-2012 дата публикации

Decoder based data recovery

Номер: US20120060074A1
Автор: Engling Yeo
Принадлежит: MARVELL WORLD TRADE LTD

Systems, methods, and other embodiments associated with decoder based data recovery are described. According to one embodiment, an apparatus includes a decoder configured to perform a decoding process on codewords to verify that the codewords meet coding constraints. The decoder includes a recovery unit configured to store recovery instructions for performing a modified decoding process. The recovery unit is further configured to execute the stored recovery instructions when a decoded codeword fails to meet the coding constraints.

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29-03-2012 дата публикации

Digital Television Transmitter/Receiver and Method of Processing Data in Digital Television Transmitter/Receiver

Номер: US20120076226A1
Принадлежит: LG ELECTRONICS INC

A digital television (DTV) transmitter and a method of processing known data in the DTV transmitter are disclosed. The method of processing known data in a digital television (DTV) transmitter includes generating a known data sequence, trellis-encoding the known data sequence, the trellis-encoded known data sequence having upper, middle, and lower bits, wherein at least one of the upper, middle, and lower bits has an m-sequence property, and mapping the trellis-encoded known data sequence into one of 2-level, 4-level, and 8-level data sequences, wherein the mapped data sequence has substantially an m-sequence property, wherein a data sequence has an m-sequence property when a peak value among auto-correlation values of the data sequence having a length of N is 1 and all the off-peak auto-correlation values are −1/N.

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29-03-2012 дата публикации

Cache with Multiple Access Pipelines

Номер: US20120079204A1
Принадлежит: Texas Instruments Inc

Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.

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05-04-2012 дата публикации

Data recovery using outer codewords stored in volatile memory

Номер: US20120084627A1
Принадлежит: Apple Inc

Systems and methods are disclosed for data recovery using outer codewords stored in volatile memory. Outer codewords can be associated with one or more horizontal portions or vertical portions of a non-volatile memory (“NVM”). In some embodiments, an NVM interface of an electronic device can program user data to a super block of the NVM. The NVM interface can then determine if a program disturb has occurred in the super block. In response to detecting that a program disturb has occurred in the super block, the NVM interface can perform garbage collection on the super block. The NVM interface can then use outer codewords associated with the super block to recover from any uncorrectable error correction code errors detected in the super block.

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12-04-2012 дата публикации

Rate adjustment apparatus and a rate adjustment method

Номер: US20120089891A1
Автор: Shunji Miyazaki
Принадлежит: Fujitsu Ltd

A rate adjustment apparatus includes a calculating section to calculate a number of outputs where bits of input data are sequentially output when a number of times of puncturing of the input data to be punctured is smaller than a number of remaining bits after puncturing, and a processing section to sequentially output bits of the input data and puncture the bits of the input data based on the number of outputs calculated by the calculating section.

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19-04-2012 дата публикации

Transmission Apparatus Reception Apparatus and Communication System

Номер: US20120096336A1
Принадлежит: Individual

To improve performance of a decoder even in a system with the coder configuration determined by inserting a doping bit sequence known between a transmission apparatus and a reception apparatus in an information bit sequence to transmit, the transmission apparatus is a transmission apparatus that transmits radio signals to the reception apparatus, and is provided with a doping section 23 that inserts a doping bit sequence which is known between the transmission apparatus and the reception apparatus in an information bit sequence to transmit to the reception apparatus, coding sections 11 a , 11 b that performerror-correcting coding on a bit sequence with the doping bit sequence inserted therein, a puncturing section that performs puncturing on a bit sequence subjected to the error-correcting coding, and a wireless transmission section 24 that transmits a bit sequence subjected to the puncturing.

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26-04-2012 дата публикации

Shift register, electronic device, control method and software program product

Номер: US20120099696A1
Автор: Jurgen Geerlings
Принадлежит: NXP BV

Disclosed is a shift register ( 200, 400 ) comprising an input ( 205 ), an output ( 230 ) and a plurality of register cells ( 210 ) serially connected between the input and the output, each register cell being connected to a neighboring cell via a node, wherein at least some of said nodes comprise a multiplexer ( 220 ) having an output coupled to the downstream register cell and a plurality of inputs, each of said plurality of inputs being coupled to a different upstream register cell such that different length sections of the shift register can be selectively bypassed, the shift register further comprising a set of parallel IO channels ( 230, 410 ) facilitating conversion between interleaved and de-interleaved data, each of said channels being coupled to a different one of said nodes, the number of parallel IO channels being smaller than the total number of register cells in the shift register.

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17-05-2012 дата публикации

Coding apparatus, coding method, decoding apparatus, decoding method, program and transmission system

Номер: US20120124455A1
Принадлежит: Sony Corp

Disclosed herein is a coding apparatus, including: a calculation section adapted to calculate, based on information of a transmission object, a linear code to be used for error detection of the information; a production section adapted to produce coded data including a plurality of sets of the information and the linear code calculated by the calculation section; and a transmission section adapted to transmit the coded data to a reception apparatus.

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24-05-2012 дата публикации

Error correction code decoding device

Номер: US20120131410A1
Автор: Masao Orio
Принадлежит: Renesas Electronics Corp

An error correction code decoding device comprises a first memory having a memory space like a matrix, a first decoding unit writing a first information into the first memory along a first direction, a second decoding unit reading the first information from the first memory along a second direction and a plurality of turbo decoders included in the second decoding unit, and differentiating access timing to a same row or same column with each other.

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14-06-2012 дата публикации

Encoding module, apparatus and method for determining a position of a data bit within an interleaved data stream

Номер: US20120147988A1
Принадлежит: Individual

An encoding module comprises an inverse interleaving module arranged to: determine an initial location index within an interleaving matrix for a data bit; and perform bit reverse ordering (BRO) on a column index value for the initial location index for the data bit to obtain a BRO column index value for the data bit. The inverse interleaving module is further arranged to calculate a number of valid interleaving matrix addresses preceding a location index for the data bit following bit reverse ordering; and determine a position of the data bit within the interleaved data stream based on the calculated number of valid addresses.

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28-06-2012 дата публикации

Method for scheduling distributed virtual resource blocks

Номер: US20120163350A1
Принадлежит: LG ELECTRONICS INC

A method for transmitting downlink data using resource blocks at a base station in a wireless mobile communication system includes transmitting downlink data mapped to physical resource blocks (PRBs) to a user equipment, wherein indexes of virtual resource blocks (VRBs) are mapped to indexes of the PRBs for a first slot and a second slot of a subframe, and the indexes of the PRBs for the second slot are shifted with respect to the indexes of the PRBs for the first slot based on a predetermined gap, and wherein a predetermined offset is applied to an index of a PRB when the index of the PRB is equal to or greater than a predetermined threshold.

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05-07-2012 дата публикации

Decoding device, decoding method, and program

Номер: US20120173954A1
Автор: Hiroyuki Yamagishi
Принадлежит: Sony Corp

A decoding device includes: a determination unit that determines whether or not a decoding ending condition is satisfied at an interval shorter than an interval of one decoding process in repeated decoding and ends the process in the middle of the one decoding process in a case where the decoding ending condition is satisfied.

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12-07-2012 дата публикации

Apparatus and method for wireless communication

Номер: US20120177096A1
Принадлежит: Fujitsu Ltd

In a wireless communication method, a first wireless communication apparatus transmits through a first wireless resource to a second wireless communication apparatus a first signal generated from a second signal for use in processing performed by the second wireless communication apparatus and a third signal for use in error checking of the second signal. The second wireless communication apparatus detects a second wireless resource to be used in the processing on the basis of the first signal, and performs the processing by using the second signal and the detected second wireless resource. For the detection, a section of the first signal corresponding to the second wireless resource is scrambled, or the first signal is scrambled with a scrambling sequence corresponding to the second wireless resource, or the bit order in at least part of the first signal is changed in a manner corresponding to the second wireless resource.

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02-08-2012 дата публикации

Memory Attribute Sharing Between Differing Cache Levels of Multilevel Cache

Номер: US20120198166A1
Принадлежит: Texas Instruments Inc

The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.

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02-08-2012 дата публикации

Soft decoding systems and methods for flash based memory systems

Номер: US20120198314A1
Автор: Gregory Burd, Xueshi Yang
Принадлежит: MARVELL WORLD TRADE LTD

Systems and methods for decoding data using a decoder that includes a primary decoder and an auxiliary decoder are provided. A codeword is retrieved from a storage device. A primary decoder attempts to decode the codeword using hard data associated with the codeword. If the primary decoder fails, an indication of the failure may be received by a decoder controller, which activates an auxiliary decoder. The auxiliary decoder attempts to decode the codeword using either hard data or soft data associated with the codeword. The primary decoder is designed to consume less power, consume less silicon area, and have a higher throughput than the auxiliary decoder. The primary decoder is configured to have a higher probability of successfully decoding a codeword, stored in the storage device, in the first attempt to decode the codeword, than failing and requiring the auxiliary decoder to decode the codeword.

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09-08-2012 дата публикации

Transmission device

Номер: US20120204083A1
Принадлежит: Fujitsu Ltd

A method in a communication system, where a systematic code obtained by systematic encoding of information bits having dummy bits inserted and by deletion of the dummy bits from results of the systematic encoding is transmitted. On a receiving side, the deleted dummy bits are inserted into the received systematic code and then decoded. The method includes: deciding a size of dummy bits for insertion into information bits; segmenting the information bits into a number of code blocks when a bit size of the information bits is greater than a stipulated size; inserting dummy bits into each block of the segmented information bits in conformity with a dummy bit insertion pattern; performing systematic encoding of each block of the information bits into which the dummy bits are inserted, and deleting the dummy bits from the results of the systematic encoding to generate a systematic code.

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23-08-2012 дата публикации

Soft-decision non-binary ldpc coding for ultra-long-haul optical transoceanic transmissions

Номер: US20120216093A1
Принадлежит: NEC Laboratories America Inc

Methods and systems for soft-decision non-binary low-density parity-check (LDPC) coding for ultra-long-haul optical transoceanic transmissions are provided. A receiver includes one or more maximum a posteriori (MAP) equalizers configured to decode one or more symbols of an encoded input stream to provide one or more symbol log-likelihood ratios (LLRs). One or more LLR estimators are configured to estimate the log-likelihood ratios of the one or more symbol LLRs to provide one or more bit LLRs. One or more non-binary LDPC decoders are configured to decode the input stream using the one or more bit LLRs to recover an original input stream.

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30-08-2012 дата публикации

Semiconductor memory device and method of controlling the same

Номер: US20120221918A1
Принадлежит: Hironori Uchikawa, Shinichi Kanno

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

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13-09-2012 дата публикации

Joint preamble and code rate identifier in a mobile dtv system

Номер: US20120230437A1
Принадлежит: Citta Richard W, Ivonete Markman

A joint preamble and code rate identifier flag in a reserved portion of a data field synchronization segment in a digital television (DTV) data field identifies the presence of preamble training data in a forward error correction (FEC) encoded portion of the DTV data field. The identifier flag also indicates the code rate used for the data field. The data field synchronization segment is not FEC encoded, thereby allowing detection of the identifier flag without FEC decoding. The detection at a receiver of the identifier flag in a DTV data field allows receiver elements, such as an equalizer and a FEC decoder, to more readily obtain and utilize the preamble training data, thereby enhancing reception and/or simplifying receiver design.

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27-09-2012 дата публикации

Subset transform interleaver

Номер: US20120242518A1
Автор: Timothy J. Martin
Принадлежит: Viasat Inc

Digital communications interleavers re-order the bits of a data coding block in a way that can be described by a table of indices that map the original order to the interleaved order. Conventional interleavers include index table interleavers, which store an index table ahead of operation and algorithmic Interleavers, which generate the indices during operation. Described herein are a new class of interleavers: Subset Transform Interleavers. A subset of generator outputs is selected and processed to create the interleaver indices. The selection is determined apriori and the selection results are stored in a Subset Usage Table. During operation, the generator is operated again and the Subset Usage Table entries determine which generator outputs are used. The generator may be a pseudo-random number generator. Implementations can use an Indexes Remaining Table, which can additionally be manipulated during operation such that it returns to an initialized state after each block interleaving process.

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27-09-2012 дата публикации

Error correction method and device

Номер: US20120246537A1
Принадлежит: Mitsubishi Electric Corp

Provided is an error correction method for an optical communication system that transmits a transmission frame formed of information data added with an overhead and an error correction code, the error correction method including adjusting a size of an FEC redundant area of an FEC frame for storing client signals of different signal types in accordance with the client signals so that transmission rates of the FEC frame for the respective client signals have an approximately N-multiple relationship (N is a positive natural number). With this, it is possible to obtain an error correction method and device capable of providing a high-quality and high-speed optical communication system without performance degradation caused by jitter or the like and with the common use of circuits having a reduced circuit scale.

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04-10-2012 дата публикации

Software Defined Radio for Universal Demodulation of Digital and Analog TV Signals

Номер: US20120249888A1
Принадлежит: Saankhya Labs Pvt Ltd

A Software Defined Radio (SDR) subsystem capable of supporting a multiple communication standards and platforms for modulation, demodulation and trans-modulation of an input signal is provided. The SDR subsystem includes a Signal Conditioning Cluster (SCC) unit that includes a signal conditioning CPU adapted for sample based signal processing, a Signal Processing Cluster (SPC) unit that includes a signal processing CPU adapted for block based signal processing, and a Channel Codec Cluster (CCC) unit that performs a channel encoding or a channel decoding operation.

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04-10-2012 дата публикации

Modulator and modulation method

Номер: US20120254701A1
Принадлежит: Panasonic Corp

A transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased. An encoding part subjects transport data to a block encoding process to form block encoded data. A modulating part modulates the block encoded data to form data symbols; and an arranging (interleaving) part arranges (interleaves) the block encoded data in such a manner that the intra-block encoded data of the encoded blocks, which include their respective single different data symbol, get together, and then supplies the arranged (interleaved) block encoded data to the modulating part. In this way, there can be provided a transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased.

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11-10-2012 дата публикации

Four-dimensional non-binary ldpc-coded modulation schemes for ultra high-speed optical fiber communication

Номер: US20120260142A1
Принадлежит: NEC Laboratories America Inc

Systems and methods are disclosed for communicating signals, by receiving a K-symbol-long input block from a 2 m -ary source channel; encoding the input block into a 2 m -ary non-binary low-density parity-check (LDPC) codeword of length N; and mapping each 2 m -ary symbol to a point in a signal constellation comprised of 2 m points, wherein a non-binary LDPC code is used as the component code for forward error correction in a coded modulation scheme capable of achieving optical fiber communication at rates beyond 100 Gb/s.

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11-10-2012 дата публикации

Method of decoding content data blocks, corresponding computer program product and decoding device

Номер: US20120260143A1
Принадлежит: Canon Inc

When decoding a set of symbols to be decoded, several data blocks representative of the set of symbols to be decoded are received by a decoding node of a communications network. The data blocks are encoded using an error correction code enabling a decoding by erasure. The decoding node performs the following steps: first selecting at least one of the data blocks, first determining first erasures, and checking whether the number of the first erasures is below a given threshold. In a case the check is positive, the decoding node performs first decoding by erasure of the set of symbols to be decoded. In a case the check is negative, the decoding node performs second selecting of at least one of the data blocks, second determining second erasures, and second decoding by erasure of the set of symbols to be decoded from the second erasures.

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18-10-2012 дата публикации

Method of error floor mitigation in low-density parity-check codes

Номер: US20120266040A1
Автор: Jon HAMKINS

A digital communication decoding method for low-density parity-check coded messages. The decoding method decodes the low-density parity-check coded messages within a bipartite graph having check nodes and variable nodes. Messages from check nodes are partially hard limited, so that every message which would otherwise have a magnitude at or above a certain level is re-assigned to a maximum magnitude.

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25-10-2012 дата публикации

Encoding and decoding methods and apparatus for use in a wireless communication system

Номер: US20120269282A1
Принадлежит: Qualcomm Inc

The claimed subject matter relates to encoding and decoding information in a wireless communication system using soft-demodulation and interleaving of concatenated code received in a strip channel. A set of symbols is received containing a plurality of information bits, dividing the received set of symbols into a plurality of subsets of symbols, each subset corresponding to the input of an inner code demodulation selecting a set of initial a priori values of the inner code demodulation for each subset of symbols, and demodulating each subset of symbols, using the initial a priori values of the subset of symbols and an inner code generator matrix, to generate a plurality of first soft information values as the output of the inner code demodulation.

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01-11-2012 дата публикации

Apparatus for encoding and decoding, data storage apparatus and method for encoding and decoding

Номер: US20120274487A1
Автор: Yosuke Kondo
Принадлежит: Toshiba Corp

According to one embodiment, an apparatus for encoding and decoding includes an encoder configured to generate integrated parity data for data obtained by combining first data with second data. The encoder includes a first generator, a second generator, and a third generator. The first generator generates parity data for the first data using a first check matrix with a predetermined regularity. The second generator generates parity data for the second data using a second check matrix with a regularity that is exclusive and different from the first check matrix. The third generator generates the integrated parity data by integrating the parity data generated by the first generator with the parity data generated by the second generator.

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08-11-2012 дата публикации

Decoding method and device for concatenated code

Номер: US20120284584A1
Принадлежит: ZTE Corp

Disclosed are a decoding method and device for concatenated code, for the decoding of concatenated code composed of low density parity code (LDPC) and Reed-Solomon (RS) code. The method includes: carrying out LDPC soft decision iterative decoding on bit de-interleaved data flow, and carrying out check decision on LDPC codeword obtained from decoding by using a check matrix; carrying out de-byte-interleave on an information bit of the LDPC codeword obtained from decoding and converting check information of the LDPC codeword into puncturing information of RS codeword; selecting a decoding mode according to the puncturing information of the RS codeword to carry out RS decoding. By way of the solution of the present invention, the RS decoding performance can be improved without increasing the computation complexity, thus greatly improving the receiving performance of the CMMB terminal as compared to the conventional method.

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15-11-2012 дата публикации

Managing Bandwidth Allocation in a Processing Node Using Distributed Arbitration

Номер: US20120290756A1
Принадлежит: Texas Instruments Inc

Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate arbitration point is associated with each target resource. An access priority value is assigned to each requester. An arbitration contest is performed for access to a first target resource by requests from two or more of the requesters using a first arbitration point associated with the first target resource to determine a winning requester. The request from the winning requester is forwarded to a second target resource. A second arbitration contest is performed for access to the second target resource by the forwarded request from the winning requester and requests from one or more of the plurality of requesters using a second arbitration point associated with the second target resource.

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15-11-2012 дата публикации

Apparatus and method for transmitting and receiving data in communication system

Номер: US20120290887A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An apparatus and a method for transmitting and receiving a signal in a communication system are provided. The method includes checking a type of the signal to be transmitted; determining a number of puncture bits according to the type of the signal; and puncturing an encoded signal to be transmitted according to the number of puncture bits.

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06-12-2012 дата публикации

Method and apparatus for interleaving data in a mobile communication system

Номер: US20120307819A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An interleaving method to which time-first-mapping is applied in a mobile communication system is provided. The interleaving method includes writing coded bits into an interleaver on a row-by-row basis, and reading the coded bits written in the interleaver on a column-by-column basis, wherein the coded bits are written by groups having a size according to a modulation order

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13-12-2012 дата публикации

Transmitter and method for transmitting data block in wireless communication system

Номер: US20120314801A1

Provided are a transmitter and a method for transmitting a data block in a wireless communication system. The method comprises the following steps: deciding the number of bits (s) and encoders (NES) to allocate to one axis of a signal constellation; encoding an information bit based on the s and the NES and generating a coded block; parsing the coded block based on the s and the NES and generating a plurality of frequency sub-blocks; and transmitting the plurality of frequency sub-blocks to a receiver.

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13-12-2012 дата публикации

Transmitter and method for transmitting data block in wireless communication system

Номер: US20120314802A1

Provided are a transmitter and a method for transmitting a data block in a wireless communication system. The method comprises the following steps: encoding an information bit and generating a block coded with an NCBPSS bit; generating two sub-blocks by parsing the coded block; and transmitting the two sub-blocks to the transmitter. By preventing the bits that are contiguous to the encoding block from having continuous identical reliabilities on a signal constellation, the deterioration of the decoding performance of the transmitter can be prevented.

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13-12-2012 дата публикации

Memory controller and non-volatile storage device

Номер: US20120317458A1
Принадлежит: Panasonic Corp

A non-volatile storage device includes one or more non-volatile memories for storing data, and a memory controller for carrying out the control of the non-volatile memory. The non-volatile memory includes the plurality of blocks, which are erase units, and the block includes the plurality of pages, which are write units of data, in each of the blocks at least one set of pages existing which include at least two pages sharing one word line. The memory controller configures a plurality of error correcting groups, each including at least one data page, which is a page for storing data, and at least one error correcting code page for storing a code for error correcting calculation of the data page, and assigns a page of a separate word line with respect to each of the data page and the error correcting page in the same error correcting group.

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27-12-2012 дата публикации

Systems and Methods for Non-Binary Decoding

Номер: US20120331370A1
Принадлежит: LSI Corp

Various embodiments of the present invention provide systems and methods for data processing. A data processing circuit is disclosed that includes: a data detector circuit, a first symbol constrained arrangement circuit, and a second symbol constrained arrangement circuit. The data detector circuit is operable to apply a data detection algorithm to a combination of a first input data set and a decoded data set to yield a detected output that includes a number of non-binary symbols. The first symbol constrained arrangement circuit is operable to receive the detected output and to re-arrange the detected output in accordance with a first arrangement algorithm to yield a re-arranged output. The bits for at least one non-binary symbol from the detected output are maintained together in the re-arranged output. The second symbol constrained arrangement circuit is operable to receive a second input data set and to re-arrange the second data input in accordance with a second arrangement algorithm to yield the decoded data set. The bits for at least one non-binary symbol from the second input data set are maintained together in the decoded data set output.

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03-01-2013 дата публикации

Systems and methods for receiving and transferring video information

Номер: US20130002965A1
Принадлежит: Broadcom Corp

Devices and methods for receiving, processing and formatting digital video. The devices may include a single semiconductor chip on which is imprinted a radio frequency signal tuner module and a display interface module. The display interface module may be configured to receive programming information from the radio frequency signal tuner module. The display interface module may be configured to communicate the programming information to a digital video recorder. The radio frequency tuner module may include a first radio frequency input channel and a second radio frequency input channel. The radio frequency signal tuner module may include a system oscillator and a phase-locked loop (“PLL”) circuit configured to generate a clock signal. The phase-locked loop circuit may be configured to transmit the signal to the display interface module and to any other suitable modules on the chip.

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03-01-2013 дата публикации

Error correcting code decoding device, error correcting code decoding method and error correcting code decoding program

Номер: US20130007568A1
Автор: Toshihiko Okamura
Принадлежит: NEC Corp

Provided is an error correction code decoding apparatus capable of performing a decoding process efficiently for various interleaver sizes while suppressing an increase in apparatus size. The error correction code decoding apparatus includes: a simultaneous decoding selection unit configured to select whether a first and a second elementary codes are to be subjected to simultaneous decoding depending on a size of an interleaver; a reception information storage unit configured to store reception information at a position in accordance with a selection result from the simultaneous decoding selection unit; an external information storage unit configured to store external information corresponding to each of the first and the second elementary codes at a position in accordance with the selection result from the simultaneous decoding selection unit; and a soft-input soft output decoding unit including a plurality of soft-input soft-output decoders that perform soft-input soft-output decoding on each of divided blocks of the first and the second elementary codes in parallel, the soft-input soft output decoding unit configured to repeat decoding of the first elementary code and the second elementary code when simultaneous decoding is not selected by the simultaneous decoding selection unit, and configured to repeat simultaneous decoding of the first and the second elementary codes when simultaneous decoding is selected by the simultaneous decoding selection unit.

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10-01-2013 дата публикации

Channel coding method of variable length information using block code

Номер: US20130010879A1
Принадлежит: LG ELECTRONICS INC

A channel coding method of variable length information using block code is disclosed. A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A-10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of minimum Hamming distance.

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10-01-2013 дата публикации

Low Density Parity Check (LDPC) Encoded Higher Order Modulation

Номер: US20130010897A1
Принадлежит: Broadcom Corp

A method and apparatus is disclosed to map a sequence of data to Quadrature Amplitude Modulation (QAM) constellation symbols. The method and apparatus encodes only a portion of the sequence of data and leaves a remaining portion of the sequence of data unencoded. The encoded portion of the sequence of data and the remaining unencoded portion of the sequence of data are then mapped into modulation symbols of the QAM constellation. The encoded portion of the sequence of data selects subsets of the QAM constellation, and the remaining unencoded portion of the sequence of data determines a specific modulation symbol within each subset of the QAM constellation.

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10-01-2013 дата публикации

Continuously interleaved error correction

Номер: US20130013972A1
Автор: Tim Coe
Принадлежит: Vitesse Semiconductor Corp

Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow, considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes.

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10-01-2013 дата публикации

Data encoding in solid state storage devices

Номер: US20130013974A1
Принадлежит: International Business Machines Corp

Methods and apparatus are provided for encoding input data for recording in s-level storage of a solid state storage device, where s f 2. Input data words are encoded in groups of M input data words in accordance with first and second BCH codes to produce, for each group, a set of M first codewords of the first BCH code. The set of M first codewords is produced such that at least one predetermined linear combination of the M first codewords produces a second codeword of the second BCH code, this second BCH code being a sub-code of the first BCH code. The sets of M first codewords are then recorded in the s-level storage. If each of the first and second codewords comprises N q-ary symbols where q=p k , k is a positive integer and p is a prime number, the q-ary code alphabet can be matched to the s-ary storage by ensuring that q and s are u th and v th powers respectively of a common base r, where u and v are positive integers and k f u, whereby p (k/u)v =s.

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31-01-2013 дата публикации

Receivers for COFDM digital television transmissions

Номер: US20130028336A1
Автор: Allen LeRoy Limberg
Принадлежит: Individual

A receiver of COFDM digital television signals includes an inner decoder for iterative soft-decision decoding of concatenated convolutional coding (CCC) and an outer decoder for Reed-Solomon (RS) coding. The receiver generates error flags for identifying code symbols to be erased before the output symbols from the inner decoder are byte de-interleaved and supplied to the outer decoder. Generation of those flags depends on soft decoding results from the inner decoder. The method of locating errors ascribes to each byte supplied to the outer decoder for RS coding the highest lack-of-confidence level specified by the soft data bits associated with that byte. The method is described as being extended to locate byte errors in plural-dimension cross-interleaved Reed-Solomon codes (CIRC) apt to be employed in DTV broadcasting to mobile and handheld receivers.

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31-01-2013 дата публикации

Time varying data permutation apparatus and methods

Номер: US20130031437A1
Принадлежит: Cortina Systems Inc

Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.

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07-02-2013 дата публикации

Method for improving performance in raid systems

Номер: US20130036340A1
Автор: Kenneth Day, Kevin Kidney
Принадлежит: LSI Corp

A method for computing and storing parity information in a RAID system includes dividing each segment in a stripe into a data block and a parity block, and storing in each parity block, parity information for a limited number of other data blocks in the stripe. A method for rebuilding data in a RAID system includes rebuilding the data from parity information and storing the rebuilt data on reserve portions of the remaining disks in the system.

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14-02-2013 дата публикации

Communications system using adaptive orthogonal frequency division multiplexing

Номер: US20130039397A1
Принадлежит: Sony Corp

In a communications device a grouping unit uses channel state information when mapping data bits to a plurality of different constellation groups. Each constellation group is assigned to another modulation scheme. A plurality of sub-carriers is assigned to none or one of the constellation groups and each modulation uses another one of the constellation groups. The communications device includes at least one scalable interleaver unit, wherein each interleaver unit is assigned to one of the constellation groups and interleaves the assignment of data bits mapped to each constellation group and the sub-carriers that carry a symbol information derived from the data bits. As an example, the interleaver unit performs frequency interleaving by interleaving, at constellation level, the sub-carriers that carry the symbol information.

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28-02-2013 дата публикации

End-to-end data protection supporting multiple crc algorithms

Номер: US20130055053A1
Принадлежит: International Business Machines Corp

A method for providing end-to-end data protection while supporting multiple cyclic-redundancy-check (CRC) algorithms is disclosed. In one embodiment, such a method includes receiving, from a first host device, a data block protected by a first CRC. The first CRC is generated using a first CRC algorithm. The method checks the integrity of the data block using the first CRC and the first CRC algorithm. The method then computes a second CRC for the data block using a second CRC algorithm different from the first CRC algorithm. The method then stores the data block, the first CRC, and the second CRC on a storage medium, such as magnetic tape. A corresponding apparatus is also disclosed.

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14-03-2013 дата публикации

Systems and Methods for Generating Predictable Degradation Bias

Номер: US20130063835A1
Принадлежит: LSI Corp

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit and a bias calculation circuit. The data detector circuit is operable to apply a data detection algorithm to a first data set to yield a first series of soft decision data, and to apply the data detection algorithm to a second data set to yield a second series of soft decision data. The bias calculation circuit operable to calculate a series of bias values based at least in part on the first series of soft decision data and the second series of soft decision data. The series of bias values correspond to a conversion between the first series of soft decision data and the second series of soft decision data.

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04-04-2013 дата публикации

Iterative decoding method for encoded signal and iterative decoding apparatus for encoded signal

Номер: US20130086443A1
Автор: Shunji Miyazaki
Принадлежит: Fujitsu Ltd

A iterative decoding method for iteratively carrying out a decoding process for an encoded segmented and signal transmitted in a plurality of (N cb ) sub blocks for each predetermined block unit includes storing a number of (n cb ) sub blocks smaller than the number (N cb ) of the sub blocks; and successively and iteratively carrying out a decoding process for each of the stored (n cb ) sub blocks within a specified time period determined based on the number (n cb ).

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04-04-2013 дата публикации

SOVA SHARING DURING LDPC GLOBAL ITERATION

Номер: US20130086446A1
Автор: Ng Kin Man, Yeung Kwok W.
Принадлежит: Link_A_Media Devices Corporation

Decoding is performed on input data to obtain first decoded data using a first error correction decoder. If decoding by a second error correction decoder on the first decoded data fails, decoding is performed using an output of the second decoder and using the first decoder. A reservation request is sent from the second error correction decoder to a memory prior to completion of the decoding on the first decoded data. Space is reserved in the memory in response to receiving the reservation request from the second decoder. 1. A system for decoding information , comprising: perform error correction decoding on input data to obtain first decoded data; and', 'in the event error correction decoding by a second error correction decoder on the first decoded data fails, perform error correction decoding using an output of the second error correction decoder;, 'a first error correction decoder configured to perform the error correction decoding on the first decoded data; and', 'send, to a memory, a reservation request prior to completion of the error correction decoding on the first decoded data; and, 'the second error correction decoder configured tothe memory, wherein the memory is configured to reserve space in the memory in response to receiving the reservation request from the second error correction decoder.2. The system of claim 1 , wherein the first error correction decoder includes a Viterbi decoder.3. The system of claim 1 , wherein the second error correction decoder includes a low-density parity-check (LDPC) decoder.4. The system of claim 1 , wherein the memory is further configured to store the first decoded data in the event the second error correction decoder is occupied when the first decoded data is output by the first error correction decoder.5. The system of claim 1 , further comprising a second memory configured to store the input data in the event the first error correction decoder is occupied when the input data is received.6. The system of claim 1 , ...

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11-04-2013 дата публикации

LOW COMPLEXITY MAXIMUM LIKELIHOOD DETECTION OF CONCATENATED SPACE CODES FOR WIRELESS APPLICATIONS

Номер: US20130089162A1
Принадлежит:

Good transmission characteristics are achieved in the presence of fading with a transmitter that employs a trellis coder followed by a block coder. Correspondingly, the receiver comprises a Viterbi decoder followed by a block decoder. Advantageously, the block coder and decoder employ time-space diversity coding which, illustratively, employs two transmitter antennas and one receiver antenna. 1. An apparatus comprising:a trellis encoder that generates a first symbol and a second symbol; anda block encoder coupled to receive the first and second symbol and generate a block of symbols, the block of symbols including the first symbol, the second symbol, a complex conjugate of the first symbol and a negative complex conjugate of the second symbol; andwherein the complex conjugate of the first symbol and the first symbol are coupled to be transmitted over different ones of a first and a second antenna and the second symbol and the negative complex conjugate of the second symbol are coupled to be transmitted over different ones of the first and the second antenna.2. The apparatus as recited in further comprising the first and second antennas.3. The apparatus as recited in wherein the first and second symbols are transmitted during a first time interval over different ones of the first and second antennas and the complex conjugate of the first symbol and the negative complex conjugate of the second symbol are transmitted during a second time interval over different ones of the first and second antennas.4. A method comprising:trellis encoding received data to generate a first symbol and a second symbol;block encoding the first and second symbols to generate a block of symbols that includes the first and second symbols, a negative complex conjugate of the second symbol, and a complex conjugate of the first symbol; andsupplying the block of symbols for transmission over a plurality of antennas.5. The method as recited in wherein the plurality of antennas comprises a first and ...

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11-04-2013 дата публикации

FEEDBACK SIGNALING ERROR DETECTION AND CHECKING IN MIMO WIRELESS COMMUNICATION SYSTEMS

Номер: US20130091401A1
Автор: Pan Kyle Jung-Lin
Принадлежит: INTERDIGITAL TECHNOLOGY CORPORATION

A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit. 1. A method implemented in a wireless transmit receive unit (WTRU) for providing feedback with error correction , the method comprising:determining feedback information, wherein the feedback information comprises at least one of a channel quality index (CQI) or a precoding matrix index (PMI);attaching Cyclic Redundancy Check (CRC) bits to the feedback information;applying a turbo coding scheme to user data bits to produce turbo coded user data bits;applying a convolutional coding scheme to the feedback information and CRC bits to produce convolutional coded feedback information and CRC bits; andtransmitting the convolutional coded feedback information and CRC bits with the turbo coded user data bits over a data type channel.2. The method as in claim 1 , wherein the data type channel is a Physical Uplink Shared Channel (PUSCH).3. The method as in claim 1 , wherein the convolutional coded feedback information and CRC bits are transmitted in a single Transmission Time Interval (TTI).4. The method as in claim 3 , wherein the convolutional coded feedback information and CRC bits and the turbo coded user data bits are transmitted in the same TTI.5. The method as in claim 1 , wherein the PMI is a sub-band PMI.6. The method as in claim 1 , wherein the PMI is a wideband PMI.7. The method as in claim 1 , further comprising:applying a channel coding scheme to at least one Hybrid Automatic Retransmission Request (HARQ) acknowledgment/non-acknowledgement (ACK/NACK) bit to produce at least one coded HARQ ACK/NACK bit; andtransmitting the at least one coded HARQ ACK/NACK bit with the convolutional coded feedback information and CRC bits and with the turbo coded user data bits over the data type channel.8. The method as in claim 7 , further ...

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11-04-2013 дата публикации

STRONG SINGLE AND MULTIPLE ERROR CORRECTING WOM CODES, CODING METHODS AND DEVICES

Номер: US20130091402A1

Preferred embodiments of the invention provide WOM coding methods and electronic devices with error correcting codes that provide single, double and triple error correction. Preferred codes of the invention also the following property: if the code corrects two/three errors it has two/three parts of redundancy bits. For double error correction, if only one part of the redundancy bit has no errors then it is possible to correct one error. For triple error correction, if only one/two parts of the redundancy bits have no errors then it is possible to correct one/two errors. Preferred methods of the invention use codes that correct/detect a single, two and three cell-erasures. A preferred method of the invention applies a code that has three roots, ah a2, a3, each of which is a primitive element and where every pair of roots generates a double error correcting code. Methods of the invention further provide and utilize codes utilitizing a triple error correcting WOM code that can correct an arbitrary number of errors. 1. A method for encoding WOM (write only once) data , the method comprising steps of:receiving an original data vector that is WOM encoded by an arbitrary WOM code;determining a set of redundancy data for the data vector;forming a new data vector that is defined by the original data vector and the redundancy data;writing the new data vector to memory.2. The method of claim 1 , further comprising WOM encoding the redundancy data prior to said step of forming a new data vector.3. The method of claim 2 , wherein said step of WOM encoding comprising WOM encoding using a WOM code that it different than the arbitrary WOM code of the original data vector.4. The method of claim 2 , wherein said forming further comprising calculating a syndrome of the new data vector and encoding the syndrome in an encoding map that is used for said WOM encoding of the redundancy data.5. The method of claim 4 , wherein the syndrome comprises a Hamming code or a shortened Hamming code ...

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11-04-2013 дата публикации

COMPUTATIONALLY EFFICIENT CONVOLUTIONAL CODING WITH RATE-MATCHING

Номер: US20130091407A1
Автор: Cheng Jung-Fu
Принадлежит: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)

An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate. 1. An error coding circuit comprising:a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits;an interleaver circuit for interleaving parity bits within each group of parity bits, wherein the interleaver circuit is configured to order parity bits such that odd parity bits precede even parity bits within each group of parity bits; anda rate-matching circuit for outputting a selected number of said interleaved parity bits ordered by group to obtain a desired code rate.2. The error coding circuit of claim 1 , wherein said interleaver circuit implements a reverse bit-reversal order interleaver for column permutation.3. The error coding circuit of claim 1 , wherein said interleaver circuit implements a cyclically-shifted bit-reversal order interleaver for column permutation.4. The error coding circuit of claim 1 , wherein said interleaver circuit implements a modulo-offset bit-reversal order interleaver for column permutation.5. The error coding circuit of claim 1 , further comprising a channel interleaver following the rate-matching circuit6. An error coding circuit comprising:a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits;an interleaver circuit for interleaving parity bits within each group of parity bits; anda rate-matching circuit for outputting a selected number of said interleaved parity bits ordered by group to obtain a desired code rate, wherein said rate-matching circuit is configured to puncture parity bits, when the encoder produces more bits than needed to match a ...

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18-04-2013 дата публикации

Apparatus and method for transmitting/receiving forward error correction packet in mobile communication system

Номер: US20130094502A1
Автор: Sung-hee Hwang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An apparatus and method for transmitting/receiving a Forward Error Correction (FEC) packet in a mobile communication system are provided. In the FEC packet transmission method, an FEC packet transmission apparatus transmits an FEC delivery block to an FEC packet reception apparatus. The FEC delivery block includes N payloads. Each of the N payloads includes a payload header. Each payload header included in each of C payloads among the N payloads includes packet oriented header information and an FEC delivery block oriented header information fragment. The packet oriented header information is applied to a related payload, and the FEC delivery block oriented header information fragment is generated by fragmenting FEC delivery block oriented header information applied to the N payloads.

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18-04-2013 дата публикации

Encoding apparatus and encoding method in data communication system

Номер: US20130097470A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An encoding method and apparatus in a data communication system are provided. The method includes inputting a source block including a plurality of source payloads, converting the source block to an information block including a plurality of information payloads according to an Information Block Generation (IBG) mode selected from a plurality of IBG modes, transmitting a delivery block generated by adding a parity block generated by encoding the information block according to a selected encoding scheme to the source block to a receiver, and transmitting information indicating the selected IBG mode to the receiver.

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25-04-2013 дата публикации

Error-Correcting Encoding Apparatus

Номер: US20130104008A1
Автор: LI Jifeng
Принадлежит: FUJITSU LIMITED

An apparatus for encoding source data, that includes a first encoder configured to encode the source data to produce first additional data; and a randomizing unit configured to randomize the source data to produce randomized data; and a second encoder configured to encode the randomized data to produce second additional data; and a selector configured to select a number of bits from the first and second additional data to produce first selected data and second selected data, wherein the number of selected bits is selected based upon a data length of an output sequence determined by a transmission frame format, and wherein the data length of the output sequence is variable. 1. An apparatus for encoding source data , comprising:a first encoder configured to encode the source data to produce first additional data;a randomizing unit configured to randomize the source data to produce randomized data;a second encoder configured to encode the randomized data to produce second additional data; anda selector configured to select a number of bits from the first and second additional data to produce first selected data and second selected data, wherein the number of selected bits is selected based upon a data length of an output sequence determined by a transmission frame format, and wherein the data length of the output sequence is variable.2. An apparatus for encoding source data , comprising:an encoder configured to encode the source data using a convolutional code to produce an additional data; anda selector configured to select a number of bits from the additional data to produce selected data, wherein the number of selected bits is selected based upon a data length of an output sequence determined by a transmission frame format, and wherein the data length of the output sequence is variable.3. An apparatus for encoding source data , comprising:a first encoder configured to encode the source data using a convolutional code to produce first additional data;a second encoder ...

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02-05-2013 дата публикации

CHANNEL DECODING METHOD AND DECODER FOR TAIL-BITING CODES

Номер: US20130111305A1

A channel decoding method and decoder are disclosed. The decoding method is based on a Circular Viterbi Algorithm (CVA), rules out impossible initial states one by one through iterations according the received soft information sequence, and finally finds the global optimal tail-biting path. In the present invention, all impossible iterations are ruled out through multiple iterations, and only the initial state having most likelihood with the received sequence survives. The algorithm is finally convergent to an optimal tail-biting path to be output. In addition, the method also updates a metric of a maximum likelihood tail-biting path (MLTBP) or rules out impossible initial states through the obtained surviving tail-biting path, thereby effectively solving the problem that the algorithm is not convergent due to a circular trap, providing a practical optimal decoding algorithm for a tail-biting convolutional code, reducing the complexity of an existing decoding scheme, and saving the storage space. 1. A channel decoding method , comprising:{'sub': path,0', '0', '0', 'MLTBP', 'MLTBP', '0', 'path,L', 'state', 'path,L, 'sup': i', 'O', 'O', '1', '1, 'S101: during the first iteration, i.e. i=1, initializing the metric M(S) of the surviving path that enters state s at position 0 to 0, where s∈S, Sindicates the state space at position 0, and i indicates the number of iterations; setting the metric of the optimal maximum likelihood tail-biting path (MLTBP) Pto 0, that is, letting M=0; performing an MVA, and searching for MLTBP in current iteration; for all s∈S, setting the state metric of state s to be equal to M(s), that is, letting M(s)=M(s);'}{'sub': MLTBP', 'MLTBP', 'MLTBP', 'MLTBP', 'MLTBP', 'MLTBP', 'MLTBP', 'MLTBP', 'MLTBP, 'sup': i', 'i', 'O', 'i', 'O', 'O', 'O', '1', 'i, 'S102: if the net path metric Mof P(s′,s′) found in current iteration is greater than the metric M, that is, M>M, updating (P, M) with (P(s′,s′),M);'}{'sub': L', 'L', 'state', 'MLTBP', 'state', ' ...

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23-05-2013 дата публикации

2d product code and method for detecting false decoding errors

Номер: US20130132794A1
Автор: Chuck Rumbolt, Wally Haas
Принадлежит: Altera Canada Ltd

The present invention discloses a method and apparatus for performing forward error correction with a multi-dimensional Bose Ray-Chaudhuri Hocquenghem (BCH) product code, and a method for detecting false decoding errors in frame-based data transmission systems.

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23-05-2013 дата публикации

SEMICONDUCTOR STORAGE DEVICE, METHOD OF CONTROLLING THE SAME, AND ERROR CORRECTION SYSTEM

Номер: US20130132795A1
Автор: Yamaga Akira
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code). 1. A semiconductor storage device comprising:a first error-correction-code generating unit that generates a first error correction code for each first unit data included in first data and for first unit data included in second data;a second error-correction-code generating unit that generates a second error correction code for a set of data which includes at least one first unit data from first data and one first unit data from second data; anda memory that can store therein at least the first data and second data.2. The semiconductor storage device according to claim 1 , wherein levels of error correction capabilities are provided in a descending order where the second error correction code is greater than the first error correction code.3. The semiconductor storage device according to claim 1 , further comprising an error-detection-code generating unit that generates an error detection code for first unit data included in first data and for first unit data included in second data.4. The semiconductor storage device according to claim 1 , wherein the memory comprises a first group of memory cells and a first word line claim 1 , and the first group of memory cells being commonly connected to the first word line claim 1 , wherein first data and first error correction code each generated for first data are stored in the first group of memory cells.5. The semiconductor storage device according to claim 1 , further comprising:a first error correcting unit that performs a ...

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30-05-2013 дата публикации

DETECTION, AVOIDANCE AND/OR CORRECTION OF PROBLEMATIC PUNCTURING PATTERNS IN PARITY BIT STREAMS USED WHEN IMPLEMENTING TURBO CODES

Номер: US20130139040A1
Принадлежит: INTERDIGITAL TECHNOLOGY CORPORATION

Detecting, avoiding and/or correcting problematic puncturing patterns in parity bit streams used when implementing punctured Turbo codes is achieved without having to avoid desirable code rates. This enables identification/avoidance of regions of relatively poor Turbo code performance. Forward error correction comprising Turbo coding and puncturing achieves a smooth functional relationship between any measure of performance and the effective coding rate resulting from combining the lower rate code generated by the Turbo encoder with puncturing of the parity bits. In one embodiment, methods to correct/avoid degradations due to Turbo coding are implemented by puncturing interactions when two or more stages of rate matching are employed. 1. A method of performing rate matching , the method comprising:interleaving a first bit stream to produce an interleaved first bit stream;interleaving a second bit stream to produce an interleaved second bit stream;interleaving a third bit stream to produce an interleaved third bit stream;buffering the interleaved first bit stream, the interleaved second bit stream and the interleaved third bit stream in a virtual buffer; andperforming rate matching on at least one output of the virtual buffer.2. The method of wherein the interleaved first bit stream claim 1 , the interleaved second bit stream and the interleaved third bit stream are buffered on a condition that the number of bits of the interleaved first bit stream claim 1 , the interleaved second bit stream and the interleaved third bit stream is not larger than a size of the virtual buffer.3. The method of claim 2 , further comprising:buffering a portion of the interleaved first bit stream, the interleaved second bit stream and the interleaved third bit stream in the virtual buffer on a condition that the number of bits of the interleaved first bit stream, the interleaved second bit stream and the interleaved third bit stream is larger than a size of the virtual buffer.4. The ...

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30-05-2013 дата публикации

METHOD AND SYSTEM FOR CYCLIC REDUNDANCY CHECK

Номер: US20130139041A1
Автор: KOSAKOWSKI Martin
Принадлежит: RESEARCH IN MOTION LIMITED

The present disclosure describes a method, performed by a data processor comprising a cyclic redundancy check (CRC) module configured for calculating CRC remainders for encoded data and a comparator comprising a shift register, for making a cyclic redundancy check of an encoded data record of bit length L, in which at least A bits of the record represent content data and at least B bits represent check data. A system for performing a cyclic redundancy check is also described. 1. A system for processing electromagnetic signals representing convolutionally encoded data streams , the system comprising:at least one processor configured to execute a trellis search of a convolutionally encoded data stream of bit length L, where L is an integer;a survivor memory unit configured to store decision bit data representing results of the trellis search, the stored decision bit data for a first D bits of the convolutionally encoded data stream, where D is an integer greater than zero and less than L, being re-orderable by the at least one processor according to the results of the trellis search for the first D bits of the convolutionally encoded data stream; anda cyclic redundancy check (CRC) module configured to a perform cyclic redundancy check on a decoded data record outputted from the survivor memory unit.2. The system of claim 1 , wherein the survivor memory unit comprises:at least one (D×N)-bit data register configured for storage of the decision bit data for the first D bits of the convolutionally encoded data stream; andat least one random access memory store configured for storage of the decision bit data for a subsequent L−D bits of the convolutionally encoded data stream.3. The system of claim 1 , wherein the survivor memory unit further comprises at least one LIFO register for output of the stored decision bit data.4. The system of claim 1 , wherein the CRC module comprises:a CRC remainder calculator configured to calculate a CRC remainder based on a first A bits of ...

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06-06-2013 дата публикации

Systems, Methods and Devices for Multi-Tiered Error Correction

Номер: US20130145229A1
Принадлежит:

An error control encoding system produces a codeword from a data word, where the resulting codeword includes the data word and three or more parity segments produced using the data word. The system includes a first encoder to encode the data word in two or more first data segments in order to produce two or more first parity segments, where each of the two or more first data segments includes a respective sequential portion of the data word. The system includes a second encoder to encode the data word in one or more second data segments in order to produce a corresponding one or more second parity segments, where each of the one or more second data segments includes a respective sequential portion of the data word, and each of the one or more second data segments also includes a sequential portion of the data included in a plurality of the two or more first data segments. Further, the system includes a controller configured to provide the two or more first data segments of the data word to the first encoder for encoding and to provide the one or more second data segments of the data word to the second encoder for encoding. 1. An error control encoding system operable to produce a codeword from a data word , where the resulting codeword includes the data word and three or more parity segments produced using the data word , the system comprising:a first encoder to encode the data word in two or more first data segments in order to produce two or more first parity segments, wherein each of the two or more first data segments includes a respective sequential portion of the data word;a second encoder to encode the data word in one or more second data segments in order to produce a corresponding one or more second parity segments, wherein each of the one or more second data segments includes a respective sequential portion of the data word, and each of the one or more second data segments also includes a sequential portion of the data included in a plurality of the two or ...

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06-06-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME

Номер: US20130145230A1
Принадлежит: KABUSHIKI KAISHA TOSHIBA

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code. 1. A storage device comprising:a nonvolatile semiconductor memory configured to store a plurality of first correcting codes to respectively correct errors in a plurality of first data blocks, a second correcting code to correct errors in a second data block which comprises the first data blocks, and the second data block, whereinwhen data is read out from the nonvolatile semiconductor memory, a first error correction processing is performed first by using the first correcting code,if the first error correction processing is unsuccessful, a second error correction processing is performed by using the second correcting code, andif the first error correction processing is successful, the second error correction processing is not performed.2. The device according to claim 1 , further comprising:a first corrector configured to correct errors in the first data blocks using the first correcting codes; anda second corrector configured to correct errors in the second data block using the second correcting code.3. The device according to claim 1 , wherein the nonvolatile semiconductor memory is a NAND flash memory.4. A storage device comprising:a nonvolatile semiconductor memory configured to ...

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06-06-2013 дата публикации

Wireless Transmission Reliability

Номер: US20130145236A1
Автор: Steven D. Baker
Принадлежит: Welch Allyn Inc

A method for performing error correction during a transmission of physiological data includes two or more data packets that are sent from a first electronic computing device to a second electronic computing device. Each of the data packets includes physiological data. Each of the data packets has a first packet size. Each of the data packets includes error correction information. The error correction information for each of the two or more packets is distributed across the two or more data packets.

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06-06-2013 дата публикации

ENCODING AND DECODING IN FLASH MEMORIES USING CONVOLUTIONAL-TYPE LOW PARITY DENSITY CHECK CODES

Номер: US20130145238A1
Принадлежит: LSI Corporation

Methods and apparatus are provided for encoding and decoding in flash memories using convolutional-type low parity density check codes. A plurality of bits to be stored on a flash memory device are encoded using a convolutional-type low density parity check code, such as a spatially coupled low density parity check code. The encoded pages or portions thereof can be decoded independently of other pages. In one embodiment, an encoded page is decoded jointly with one or more additional pages in the same wordline or a different wordline. 1. A method for encoding data for storage on a flash memory device , comprising:obtaining a plurality of bits to be stored on said flash memory device; andencoding said plurality or bits for storage as a page on said flash memory device using a convolutional-type low density parity check code.2. The method of claim 1 , further comprising the step of storing said encoded page on said flash memory device.3. The method of claim 1 , wherein said convolutional-type low density parity check code comprises a spatially coupled low density parity check code.4. The method of claim 1 , wherein said encoded page is decoded independently of other pages.5. The method of claim 1 , wherein a portion of said encoded page is decoded independently of other pages.6. The method of claim 1 , wherein said encoded page is decoded jointly with one or more additional pages in a wordline of said flash memory device.7. The method of claim 1 , wherein said encoded page is decoded jointly with one or more additional pages in at least one additional wordline of said flash memory device.8. The method of claim 1 , further comprising the step of encoding a plurality of pages in a wordline of said flash memory device in an incremental manner as user data becomes available by saving an encoder state until desired pages are encoded.9. The method of claim 1 , wherein said encoding step further comprises the step of encoding one or more parity bits in a parity area of said ...

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13-06-2013 дата публикации

RECEIVING/TRANSMITTING SYSTEM AND DATA PROCESSING METHOD IN THE RECEIVING/TRANSMITTING SYSTEM

Номер: US20130151933A1
Принадлежит: LG ELECTRONICS INC.

According to one embodiment, a transmitting system includes: a randomizer for randomizing mobile service data; a processor for Serial Concatenated Convolutional Coding (SCCC) outer-encoding the randomized mobile service data; a first formatter for forming a first data group including the SCCC outer-encoded mobile service data; a deinterleaver for deinterleaving data of the first data group to output a second data group comprising data packets including a portion of the deinterleaved data, wherein the data packets are spaced at least one data packet apart; and a trellis encoder for trellis encoding the deinterleaved data. 1. A transmitting system comprising:a randomizer for randomizing mobile service data;a processor for Serial Concatenated Convolutional Coding (SCCC) outer-encoding the randomized mobile service data;a first formatter for forming a first data group including the SCCC outer-encoded mobile service data;a deinterleaver for deinterleaving data of the first data group to output a second data group comprising data packets including a portion of the deinterleaved data, wherein the data packets are spaced at least one data packet apart; anda trellis encoder for trellis encoding the deinterleaved data.2. The transmitting system of claim 1 , wherein the first formatter inserts Reed-Solomon (RS) parity data place holders and MPEG header data place holders in the first data group.3. The transmitting system of claim 2 , further comprising:a second formatter for removing the RS parity data place holders in the second data group and replacing the MPEG header place holders in the second data group with MPEG header data to output mobile service data packets.4. The transmitting system of claim 3 , further comprising:an RS encoder for performing a non-systematic RS encoding process on the mobile service data packets and inserting 20 bytes of RS parity data at a pre-determined parity byte location within each of the mobile service data packets.5. The transmitting system ...

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20-06-2013 дата публикации

Systems and methods for changing decoding parameters in a communication system

Номер: US20130156118A1
Автор: Christopher H. Dick
Принадлежит: Xilinx Inc

A communication system includes an iterative multi-stage decoder that may be dynamically configured to achieve a particular bit-error-rate. In one embodiment, a circuit comprises a first decoder block and a second decoder block to decode data received over a communication channel. A control circuit may change a number of iterations performed by the decoder blocks to decode received data based on a specified bit error rate and a detected signal-to-noise ratio of said received data. The number of computational units used in the decoders may be changed dynamically to achieve desired system performance. In one embodiment, resources are allocated based on a system initiating the connection. Programmable circuits are used in some embodiments to reconfigure the multi-stage decoder.

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20-06-2013 дата публикации

System and method for frequency diversity

Номер: US20130156124A1
Принадлежит: Qualcomm Inc

A system and method for frequency diversity uses interleaving in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes. Subcarriers of one or more interlaces are interleaved in a bit reversal fashion and the one or more interlaces are interleaved in the bit reversal fashion.

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04-07-2013 дата публикации

MEMORY CONTROLLER, DATA STORAGE DEVICE, AND MEMORY CONTROLLING METHOD

Номер: US20130173986A1
Принадлежит:

A memory controller includes a first error detection code generator for generating a first error detection code for data received from a host, a controller to write the data and the first error detection code to nonvolatile memory and to read the data and the first error detection code from the nonvolatile memory, an error detector to perform an error detection based on the data and the first error detection code that are read from the nonvolatile memory, a second error detection code generator to generate a second detection error code based on the data read from the nonvolatile memory, and a mismatch code generator to generate a mismatch code signaling the presence of an error in the data, wherein either the second error detection code or the mismatch code is selected based on the error detection and sent to the host. 1. A memory controller for a nonvolatile memory , comprising:a first error detection code generator to generate a first error detection code associated with data received from a host;a controller for writing the data and the first error detection code to the nonvolatile memory, and for reading the data and the first error detection code from the nonvolatile memory when the data is requested to be read by the host;an error detector that performs an error detection based on the data and the first error detection code which are read from the nonvolatile memory;a second error detection code generator to generate a second error code based on the data read from the nonvolatile memory; anda mismatch code generator to generate a mismatch code signaling the presence of errors in the data read from the nonvolatile memory,wherein either the second error detection code or the mismatch code is selected and added to the data read from the nonvolatile memory and sent to the host with the data read from the nonvolatile memory.2. The memory controller according to claim 1 , whereinthe second error detection code is selected when no error is detected by the error ...

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18-07-2013 дата публикации

Joint encoding and decoding methods for improving the error rate performance

Номер: US20130185610A1
Принадлежит: KING SAUD UNIVERSITY

Joint encoding and decoding methods for improving the error rate performance are described. In one aspect, the systems and methods determine values and positions of L desired symbols. In encoding unit receives data symbols for encoding. The encoding unit calculates, responsive to receiving the data symbols, values and positions of H help symbols. The encoding unit inserts the help symbols into the data symbols at respective help symbols positions, thereby generating new data symbols. Encoding unit encodes the new data symbols to produce a codeword C′ that contains the L desired symbols. The codeword C′ is communicated to a decoder that is instructed to explore some or all L desired symbols in C′.

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18-07-2013 дата публикации

Systems, methods, apparatus and computer program products for highly reliable file delivery using compound and braided fec encoding and decoding

Номер: US20130185613A1
Автор: Weimin Fang
Принадлежит: KenCast Inc

Systems, methods, apparatus and computer program products provide highly reliable file delivery using a combination of packet-level FEC on source data packets which are arranged in matrices, where encoding is performed on both rows and columns or on rows, columns and diagonals.

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18-07-2013 дата публикации

SOFT OUTPUT VITERBI DETECTOR WITH ERROR EVENT OUTPUT

Номер: US20130185615A1
Принадлежит: Link_A_Media Devices Corporation

A first sequence of states associated with a surviving path and a second sequence of states associated with a non-surviving path are determined. A possible error event is determined based at least in part on the first sequence of states and the second sequence of states. The first sequence of states is replaced with the second sequence of states by applying the possible error event to the first sequence of states. 1. A system for processing information , including: determine a first sequence of states associated with a surviving path;', 'determine a second sequence of states associated with a non-surviving path; and', 'determining a possible error event based at least in part on the first sequence of states and the second sequence of states; and, 'a Viterbi detector configured toa decoder configured to replace the first sequence of states with the second sequence of states by applying the possible error event to the first sequence of states.2. The system recited in claim 1 , wherein: determine a third sequence of states associated with a second non-surviving path;', 'is determine a second possible error event based at least in part on the first sequence of states and the third sequence of states;', 'determine a first reliability associated with the second sequence of states; and', 'determine a second reliability associated with the third sequence of states; and, 'the Viterbi detector is further configured to select between the second sequence of states and the third sequence of states based at least in part on the first reliability and the second reliability; and', 'in the event the third sequence of states is selected, replace the first sequence of states with the third sequence of states by applying the second possible error event to the first sequence of states, wherein replacing the first sequence of states with the second sequence of states is performed in the event the second sequence of states is selected., 'the decoder is further configured to3. The system ...

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18-07-2013 дата публикации

METHOD AND DEVICE FOR IMPLEMENTING VITERBI DECODING

Номер: US20130185616A1
Автор: Yuan Wei
Принадлежит:

The disclosure provides a method and device for implementing Viterbi decoding. The method comprises the following steps: calculating branch path measurement values of received code words and reference code words; parallel accumulating the branch path measurement values and measurement values corresponding to states to obtain accumulated values according to a state transition diagram, selecting a maximum accumulated value as a new measurement value of a next state, and saving all survival path selection results until data for decoding ends; and starting traceback from a final state to obtain decoded data according to the survival path selection results. In the disclosure, by modifying the traditional serial or serial-parallel mixed mode for calculating accumulated path measurement values to a multi-path fully-parallel calculation mode, the throughput rate of the system data is improved, and the decoding delay is merely in us level. In the disclosure, the traditional mode of sliding window traceback is also changed, traceback whose depth is tow times of the encoding length is only once, but the second section traceback data in the traceback depth is only valid. The accumulated values and state measurement values needn't to be stored, the method is simple and efficient, and the performance of the system is also improved. 1. A method for implementing Viterbi decoding , comprising:calculating branch path measurement values of received code words and reference code words;parallel accumulating the branch path measurement values and measurement values corresponding to states to obtain accumulated values according to a state transition diagram, selecting a maximum accumulated value as a new measurement value of a next state, and saving all survival path selection results until data for decoding ends; andstarting traceback from a final state to obtain decoded data according to the survival path selection results.2. The method for implementing Viterbi decoding according to ...

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25-07-2013 дата публикации

Joint source channel decoding using parameter domain correlation

Номер: US20130188758A1
Автор: Robert W. Zopf
Принадлежит: Broadcom Corp

Methods, systems, and apparatuses are provided for performing joint source channel decoding in a manner that exploits parameter domain correlation. Redundancy in speech coding and packet field parameters is exploited to generate conditional probabilities that a decoder utilizes to perform joint source channel decoding. The conditional probabilities are based upon correlations of parameters of a current frame with parameters of the same or other frames or historical parameter data. Parameter domain correlation provides significant channel decoding improvement over prior bit domain solutions. Also provided are methods, systems, and apparatuses for utilizing received statistics of monitored data bits from which conditional probabilities are generated to perform channel decoding. The techniques described may be implemented at the decoder side and thus do not interfere with transmission standards.

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25-07-2013 дата публикации

ERROR CORRECTING CODES FOR INCREASED STORAGE CAPACITY IN MULTILEVEL MEMORY DEVICES

Номер: US20130191697A1
Принадлежит: MICRON TECHNOLOGY, INC.

Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, data may be programmed and/or read from a matrix of nonvolatile memory cells with concatenated encoding/decoding schemes. In some embodiments, a calculation module may determine an actual bit per cell value of a given combination of parameters of a nonvolatile memory device. Still other embodiments may be described and claimed. 1. An apparatus comprising:a matrix of memory cells; anda calculation system configured to select an error correction code scheme based at least in part on a first number of non-parity information bits that the matrix is capable of storing, a second number of parity cells of the matrix, and a third number of non-parity cells of the matrix.2. The apparatus of claim 1 , wherein the matrix comprises nonvolatile memory cells.3. The apparatus of claim 2 , wherein the nonvolatile memory cells are configured to have more than two cell states.4. The apparatus of claim 1 , wherein the calculation system determines the third number of non-parity cells of the matrix based at least in part on the first number of non-parity information bits that the matrix is capable of storing and a bit per cell value of the matrix.5. The apparatus of claim 1 , wherein the calculation system determines the second number of parity cells of the matrix based at least in part on the first number of non-parity information bits that the matrix is capable of storing claim 1 , a number of distributions of the cells of the matrix claim 1 , the error correction code scheme claim 1 , and a bit per cell value of the matrix.6. The apparatus of claim 1 , wherein the calculation system determines a number of bits that are capable of being corrected per error correction code block based at least in part on a target device error rate of the matrix and a bit error rate associated with a number of distributions of the cells of the matrix ...

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01-08-2013 дата публикации

Symbol Flipping Data Processor

Номер: US20130198580A1
Принадлежит: LSI Corp

Various embodiments of the present invention provide systems and methods for a symbol flipping data processor. For example, a symbol flipping data processor is disclosed that includes a data decoder in the symbol flipping data processor operable to perform error checking calculations, and a data detector in the symbol flipping data processor operable to perform symbol flipping in the data detector based at least in part on the error checking calculations, wherein the output of the data processor is generated at least in part based on the symbol flipping in the data detector.

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01-08-2013 дата публикации

SUPERCHARGED CODES

Номер: US20130198582A1
Принадлежит: BROADCOM CORPORATION

A system and method is provided for encoding k input symbols into a longer stream of n output symbols for transmission over an erasure channel such that the original k input symbols can be recovered from a subset of the n output symbols without the need for any retransmission. A symbol is a generic data unit, consisting of one or more bits, that can be, for example, a packet. The system and method utilize a network of erasure codes, including block codes and parallel filter codes to achieve performance very close to the ideal MDS code with low encoding and decoding computational complexity for both small and large encoding block sizes. This network of erasure codes is referred to as a supercharged code. The supercharged code can be used to provide packet-level protection at, for example, the network, application, or transport layers of the Internet protocol suite. 1. A method for erasure coding of input symbols that form messages , comprising:implementing at least three block coding operations that respectively provide a first, second, and third set of code words based on the messages;implementing at least two filter coding operations that respectively provide a fourth and fifth set of code words based on the first set of code words;modifying an order in which bits of the first set of code words are taken into account for at least one of the two filter coding operations; andparallel concatenating the second, third, fourth, and fifth sets of code words to form encoded symbols for transmission over an erasure channel.2. The method of claim 1 , further comprising:implementing a repetition coding operation that respectively repeats the second and third sets of code words some number of times before the second and third sets of code words are parallel concatenated with the fourth and fifth sets of code words.3. The method of claim 1 , wherein the second claim 1 , third claim 1 , fourth claim 1 , and fifth sets of code words are parallel concatenated using an exclusive or ...

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01-08-2013 дата публикации

TURBO CODE PARALLEL INTERLEAVER AND PARALLEL INTERLEAVING METHOD THEREOF

Номер: US20130198592A1
Автор: WANG Yi
Принадлежит: ZTE CORPORATION

A Turbo code parallel interleaver and a parallel interleaving method are disclosed by the disclosure. The Turbo code parallel interleaver comprises: an interleaving unit, configured to generate a column address for parallel-reading data and a row address of each row of data being row-interleaved, input the column address and the column address after delay to a CB matrix unit, input the row address of each row to a switching output unit, and input the row address of each row after delay to a switching input unit; a switching output unit, configured to receive the data of each row output by the CB matrix unit, perform the inter-row interleaving for the data of each row according to the row address of each row, and input the interleaved data to a parallel MAP unit for the MAP computing; and a switching input unit. 1. A Turbo code parallel interleaver , comprising:an interleaving unit, configured to generate a column address for parallel-reading data and a row address of each row for row-interleaving the read data, input the column address to a Code Block (CB) matrix unit as a read address, input the column address after delay to the CB matrix unit as a write address, input the row address of each row to a switching output unit, and input the row address of each row after delay to a switching input unit;the switching output unit, configured to receive data of each row output by the CB matrix unit, perform inter-row interleaving for the read data of each row according to the row address of each row, and input the interleaved data to a parallel Maximum A Posteriori (MAP) unit for MAP computing, wherein the data of each row is read by the CB matrix unit according to the read address; andthe switching input unit, configured to receive the row address of each row after delay from the interleaving unit, perform the inter-row interleaving for the data of each row output by the parallel MAP unit after the MAP computing according to the row address after delay, and write the ...

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01-08-2013 дата публикации

Methods for Viterbi Decoder Implementation

Номер: US20130198594A1
Принадлежит:

Disclosed is a method for selecting a design option for a Viterbi decoder model. In some embodiments, the method includes deriving a set of design options for a Viterbi decoder model by differentiating at least one design parameter, where the at least one design parameter comprises at least a first value for a look-ahead parameter. The method further includes performing an evaluation of each design option in the set of design options in a multi-dimensional design space and, based on the evaluation of each design option, selecting a design option in the set of design options that (i) satisfies a predetermined energy efficiency constraint and (ii) yields at least a second value for the look-ahead parameter, wherein the second value is greater than the first value and satisfies a predetermined area budget. 1. A method comprising: the at least one design parameter comprises at least a first value for a look-ahead parameter, and', 'the look-ahead parameter indicates a number of trellis stages combined in a single step of a Viterbi decoding process of the Viterbi decoder model;, 'deriving a set of design options for a Viterbi decoder model by differentiating at least one design parameter, whereinperforming an evaluation of each design option in the set of design options in a multi-dimensional design space;based on the evaluation of each design option, selecting a design option in the set of design options that (i) satisfies a predetermined energy efficiency constraint and (ii) yields at least a second value for the look-ahead parameter, wherein the second value is greater than or equal to the first value and satisfies a predetermined area constraint for an area of the design space.2. The method of claim 1 , wherein the multi-dimensional design space comprises a three-dimensional design space.3. The method of claim 1 , wherein performing the evaluation of each design option comprises performing a logic synthesis towards a technology-dependent description.4. The method of ...

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08-08-2013 дата публикации

Soft decision value generation circuit

Номер: US20130205184A1
Принадлежит: Mitsubishi Electric Corp

A soft decision value generation circuit capable of reducing amount of calculation and hardware scale for generating a soft decision value. The soft decision value generation circuit includes: a phase rotation unit rotating phases of received symbols after coherent detection; addition units calculating, by using the phase-rotated received symbols, absolute values of soft decision values for soft decision value candidates restricted in advance; minimum value selection units selecting minimum values out of the absolute values of the soft decision values; sign reflection units reflecting, based on the phases of the received symbols after the phase rotation, sign information to the minimum values; and soft decision value correction units multiplying outputs of the sign reflection units by a coefficient depending on a noise variance value and an amplitude value of a modulation symbol.

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15-08-2013 дата публикации

Transmission stream generating device for generating transmission stream which additional data is stuffed in a payload area of a packet, digital broadcast transmitting/receiving device for transmitting/receiving the transmission stream, and methods thereof

Номер: US20130208777A1
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A transmission stream (TS) generating apparatus includes an adaptor which receives general data and generates a stream having a plurality of packets, and which provides adaptive field in some of the plurality of packets, and an inserter which inserts additional data into all the payload areas of some of the plurality of packets that are not provided with the adaptive fields. Because additional data is transmitted, without requiring adaptive field header in certain packet, a data transmission rate is increased.

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15-08-2013 дата публикации

Reduced complexity non-binary ldpc decoding algorithm

Номер: US20130212451A1
Принадлежит: Stec Inc

A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component.

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22-08-2013 дата публикации

Interleaving method and deinterleaving method

Номер: US20130216001A1
Автор: Mihail Petrov
Принадлежит: Panasonic Corp

An interleaving method performed by a transmitter for a communication system with quasi-cyclic low-density parity-check codes, spatial multiplexing, and T transmit antennas is used for applying permutation to N cyclic blocks of a codeword in order to map bits of the permutated cyclic blocks onto T constellation words constituting multiple spatial-multiplexing blocks from the codeword. Each cyclic block consists of Q bits.

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22-08-2013 дата публикации

METHOD FOR STOPPING ITERATION IN AN ITERATIVE TURBO DECODER AND AN ITERATIVE TURBO DECODER

Номер: US20130219241A1
Автор: Grubeck Hans
Принадлежит: ZTE WISTRON TELECOM AB

The present document discloses a method for stopping iteration in an iterative Turbo decoder and an iterative Turbo decoder. Hard decisions from the two convolutional decoders of the iterative Turbo decoder are used simultaneously to determining when to stop the iteration in the iterative Turbo decoder. 4. The method of claim 3 , wherein in the step of determining whether A(j) or D(j) is zero at j>1 claim 3 , or a(j)>0 and N(j)=Mat j>1 claim 3 , if both A(j) and D(j) are nonzero at j>1 and a(j)≦0 or N(j)≠Mat j>1 claim 3 , the method further comprising:{'sub': b', 'b', 'c', 'c, 'claim-text': wherein b(j) is calculated by: b(j)=B(j)−B(j−1), where j=3, 4, . . . ;', {'sub': 'b', 'wherein Mis any one among 0, 1, 2, . . . , 9;'}, {'sub': 'b', 'wherein N(j) is the number of ascending ordered disjunct connected sets of j:s preceding j, where b(j) for the last element in each set is negative, and b(j) for the preceding elements of the set are zero or positive and includes at least one positive value;'}, 'wherein c(j) is calculated by: c(j)=C(j)−C(j−1), where j=3, 4, . . . ;', {'sub': 'c', 'wherein Mis any one among 0, 1, 2, . . . , 9;'}, {'sub': 'c', 'wherein N(j) is the number of ascending ordered disjunct connected sets of j:s preceding j, where c(j) for the last element in each set is negative, and c(j) for the preceding elements of the set are zero or positive and includes at least one positive value;'}], 'determining whether b(j)>0 and N(j)=Mat j>2 or c(j)>0 and N(j)=Mat j>2,'}and{'sub': b', 'b', 'c', 'c, 'stopping the iteration if b(j)>0 and N(j)=M, or c(j)>0 and N(j)=M.'}6. The method of claim 2 , wherein the iteration step j has a maximum number of j claim 2 , if the iteration is not stopped at j Подробнее

22-08-2013 дата публикации

Multi-processing architecture for an lte turbo decoder (td)

Номер: US20130219242A1
Принадлежит: LSI Corp

An apparatus comprising a decoder circuit and a memory. The decoder circuit may be configured to generate a single address signal to read a first parity data signal, a second parity data signal and read and/or write systematic information data, a first a-priori-information signal and a second a-priori-information signal. The decoder circuit (i) reads the first parity data signal, the systematic information data and the first a-priori-information during even half-iterations of a decoding operation and (ii) reads the second parity data, the systematic information data and the second a-priori-information during odd half-iterations of the decoding operation. The memory may be configured to store the systematic information data and the first and second a-priori-information signals such that each are accessible by the single address signal.

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29-08-2013 дата публикации

Impulse and/or burst noise signal to noise ratio (SNR) aware concatenated forward error correction (FEC)

Номер: US20130227373A1
Принадлежит: BROADCOM CORPORATION

Impulse and/or burst noise signal to noise ratio (SNR) aware concatenated forward error correction (FEC). Adaptive processing is performed on a signal based on one or more effects which may deleteriously modify a signal. For example, based on a modification of a signal to noise ratio (SNR) associated with one or more impulse or burst noise events, which may be estimated, different respective processing may be performed selectively to differently affected bits associated with the signal. For example, two respective SNRs may be employed: a first SNR for one or more first bits, and a second SNR for one or more second bits. For example, as an impulse or burst noise event may affect different respective bits of a codeword differently, and adaptive processing may be made such that different respective bits of the codeword may be handled differently. 1. An apparatus , comprising:an input to receive a signal from a communication channel;a demodulator to process the signal to generate a plurality of bits in a parallel format and to extract at least a first bit that is inner coded and at least a second bit that is not inner coded there from;at least one parallel to serial processor to arrange the plurality of bits in the parallel format and to generate a serial bit stream;an inner decoder to receive the serial bit stream and to process the at least the first bit for combination with the at least the second bit to generate an inner decoded signal;a deinterleaver to process the inner decoded signal to generate a deinterleaved signal; andan outer decoder to process the deinterleaved signal to generate at least one hard decision associated with at least one of the at least the first bit and the at least the second bit; and wherein:at least one of the at least the first bit and the at least the second bit adaptively decoded by at least one of the inner decoder and the outer decoder based on a modified signal to noise ratio (SNR) associated with at least one impulse or burst noise ...

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05-09-2013 дата публикации

Systems and Methods for Out of Order Data Reporting

Номер: US20130232155A1
Принадлежит: LSI Corp

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for out of order reporting of results from data processing.

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12-09-2013 дата публикации

Apparatuses and methods for combining error coding and modulation schemes

Номер: US20130238952A1
Автор: Chandra C. Varanasi
Принадлежит: Micron Technology Inc

Methods and apparatuses for combining error coding and modulation schemes are described herein. One or more methods include encoding data using linear error correcting code, modulating the encoded data, writing the modulated data to memory, and decoding the written data using a Viterbi algorithm and a linear error correcting code decoder.

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12-09-2013 дата публикации

SYSTEMS AND METHODS FOR NETWORK CODING USING CONVOLUTIONAL CODES

Номер: US20130238962A1
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A network coding method includes receiving a plurality of message packets each having a packet length. Encoding the plurality of message packets by applying a convolutional code across symbols in corresponding positions of the plurality of message packets obtaining a number of encoded packets. The number of encoded packets obtained being more than the number of message packets. 1. A network coding method , comprising:receiving, by a processor, a plurality of message packets each having a packet length;encoding the plurality of message packets by applying a convolutional code across symbols in corresponding positions of the plurality of message packets to obtain a number of encoded packets, wherein the number of encoded packets is more than the number of message packets.2. The method of wherein the encoded packets are forwarded to a transmitter.3. The method of wherein the convolutional code is applied to a concatenated block of the plurality of message packets equal to a coding depth.4. The method of wherein the coding depth is one.5. The method of wherein the coding depth is greater than one.6. The method of further comprising:adding, by the processor, pad bits to the end of all message packets shorter than a longest message packet to make all message packets equal in length.7. A wireless communication device comprising:a packet receiver to receive a plurality of message packets; anda convolutional encoder to apply a convolutional code across symbols in corresponding positions of the plurality of message packets to obtain a number of encoded packets.8. The wireless communication device of wherein the number of encoded packets is larger than the number of message packets.9. The wireless communication device of wherein the convolutional code is applied to a concatenated block of the plurality of message packets equal to a coding depth.10. The wireless communication device of wherein the coding depth is one.11. The wireless communication device of wherein the coding ...

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19-09-2013 дата публикации

Integer and Half Clock Step Division Digital Variable Clock Divider

Номер: US20130243148A1
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A clock divider is provided that is configured to divide a high speed input clock signal by an odd, even or fractional divide ratio. The input clock may have a clock cycle frequency of 1 GHz or higher, for example. The input clock signal is divided to produce an output clock signal by first receiving a divide factor value F representative of a divide ratio N, wherein the N may be an odd or an even integer. A fractional indicator indicates the divide ratio is N.5 when the fractional indicator is one and indicates the divide ratio is N when the fractional indicator is zero. F is set to 2(N.5)/2 for a fractional divide ratio and F is set to N/2 for an integer divide ratio. A count indicator is asserted every N/2 input clock cycles when N is even. The count indicator is asserted alternately N/2 input clock cycles and then 1+N/2 input clock cycles when N is odd. One period of an output clock signal is synthesized in response to each assertion of the count indicator when the fractional indicator indicates the divide ratio is N.5. One period of the output clock signal is synthesized in response to two assertions of the count indicator when the fractional indicator indicates the divide ratio is an integer.

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19-09-2013 дата публикации

Data processing device and data processing method

Номер: US20130246883A1
Принадлежит: Sony Corp

A data processing device and a data processing method that can readily process control data having its PAPR improved. In a transmission device, a padder pads control data necessary for demodulation with zeros as dummy data, and a scrambler scrambles the padded control data (post-padding control data). A replacement unit replaces scrambled dummy data in the scrambled post-padding control data with the dummy data, and a BCH encoder and an LDPC encoder perform BCH encoding and LDPC encoding as error correction encoding on the replacement data obtained through the replacement. A shortening unit performs shortening by deleting the dummy data contained in the LDPC code and puncturing the parity bits of the LDPC code. The device can be applied in cases where control data is subjected to error correction encoding and is then transmitted, for example.

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19-09-2013 дата публикации

DECODING METHOD AND APPARATUS FOR NON-BINARY, LOW-DENSITY, PARITY CHECK CODES

Номер: US20130246894A1
Принадлежит:

Building and using sub-sets of configurations sets are provided to compute the check-nodes update by using a particular representation of the input messages, called here-after trellis-EMS (T-EMS). In a main aspect, the system provides a decoding method to compute doutput vectors of a non-binary parity-check (NBPC) equation decoding unit used for LDPC check codes defined in a NB space. 1. A decoding method to compute doutput vectors of a non-binary parity-check (NBPC) equation decoding unit used for LDPC check codes defined in a NB space , comprising:{'sub': 'c', 'converting reliability vector messages of dinput vectors of a NBPC equation decoding unit to reliability vector messages of a delta domain, computed in logarithm-form with a value of maximum reliability as a reference for the corresponding conversion of an input vector to the delta domain reliability vector;'}determining one or more minimum values among each and every collection of the delta domain input vector entries corresponding respectively to each and every possible non-zero state of the NB space;storing in a final state (FS) storage, for respectively each and every possible non-zero state of the NB space, one or more minimum values and indicia of minimum values locations in an extra compressed state, called FS as above;computing a FS reliability, for each and every possible non-zero state of the NB space, as a result of a selection either of the minimum value of the considered non-zero state of the NB space, or of a combination sum of at least two minimum values stored in the FS storage;setting the FS reliability for the zero state of the NB space as zero; and{'sub': 'c', 'computing the doutput vectors of reliabilities in a delta domain representation, based on the minimum values and indicia of minimum values locations stored in the FS storage and the FS reliabilities.'}2. The decoding method of claim 1 , further comprising storing FS reliabilities in the FS storage and accessing them from FS storage ...

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