ПЕРЕМЕЖИТЕЛЬ ТУРБОКОДА, ИСПОЛЬЗУЮЩИЙ ЛИНЕЙНЫЕ КОНГРУЭНТНЫЕ ПОСЛЕДОВАТЕЛЬНОСТИ

Изобретение относится к области кодирования для коммуникационных систем и может быть применено, в частности, к перемежителям для турбокодеров. Его использование позволяет получить технический результат в виде повышения производительности канала передачи и уменьшения количества ошибок при передаче данных и их последующем декодировании. Технический результат достигается за счет того, что турбокодер содержит первый кодер, выполненный с возможностью приема множества входных битов последовательно и генерирования из него множества выходных символов, перемежитель, выполненный с возможностью приема множества входных битов последовательно, причем перемежитель содержит множество ячеек хранения битов, расположенных в матрице строк и столбцов, и генератор линейной конгруэнтной последовательности, выполненный с возможностью псевдослучайного генерирования последовательности для тасования битов в каждой строке перемежителя, и второй кодер, выполненный с возможностью приема множества перемежающихся битов ...

НОВАЯ СТРУКТУРА КОДОВОЙ КОМБИНАЦИИ ДЛЯ ПЕРЕДАЧИ ФРЕЙМОВ И ДАННЫХ В СИСТЕМАХ С МНОЖЕСТВОМ НЕСУЩИХ

Заявленное изобретение относится к устройству передачи, предназначенному для передачи сигналов в системе с множеством несущих на основе структуры фрейма. Технический результат - гибкая настройка на любую требуемую часть полосы пропускания передачи и малое содержание служебных данных. Для этого каждый фрейм содержит, по меньшей мере, одну кодовую комбинацию сигналов и одну или больше кодовых комбинаций данных, упомянутое устройство передачи содержит средство формирования фрейма, выполненное с возможностью размещения данных сигналов в упомянутой, по меньшей мере, одной кодовой комбинации сигналов во фрейме, и размещает данные и, по меньшей мере, один пилотный сигнал в упомянутой одной или больше кодовых комбинациях данных во фрейме, в результате чего длина каждой из упомянутых одной или больше кодовых комбинаций данных в направлении частоты равна или составляет кратное минимальной длины кодовой комбинации данных, средство преобразования, выполненное с возможностью преобразования упомянутой ...

УСТРОЙСТВО УПРАВЛЕНИЯ СВЯЗЬЮ, УСТРОЙСТВО РАДИОСВЯЗИ, СПОСОБ УПРАВЛЕНИЯ СВЯЗЬЮ, СПОСОБ РАДИОСВЯЗИ И ПРОГРАММА

Изобретение относится к области сотовой связи. Технический результат изобретения заключается в периодическом распределении другого устройства чередования в интервал, имеющий контролируемую продолжительность, продолжительность интервала периодического распределения другого устройства чередования является управляемо изменяемой величиной. Устройство управления связью содержит схему, выполненную с возможностью связи с устройством радиосвязи системы связи, использующей неортогональный мультидоступ, периодического распределения другого устройства чередования, используемого для неортогонального мультидоступа, посредством устройства радиосвязи в интервале, управляемого изменения продолжительности интервала периодического распределения другого устройства чередования, используемого для неортогонального мультидоступа, на основании информации, полученной от устройства радиосвязи и обозначающей состояние устройства радиосвязи. 3 н. и 17 з.п. ф-лы, 7 табл., 19 ил.

СПОСОБ АДАПТИВНОГО КАНАЛЬНОГО КОДИРОВАНИЯ И УСТРОЙСТВО ДЛЯ ЕГО ОСУЩЕСТВЛЕНИЯ

Изобретение относится к способам и устройствам адаптивного канального кодирования для систем связи. Предложен канальный кодер, имеющий сверточные кодеры, подключенные параллельно или последовательно. Канальный кодер содержит первый кодер для кодирования входных информационных битов, перемежитель, имеющий запоминающее устройство и генератор индексов, для изменения порядка информационных битов согласно заданному способу, второй кодер для кодирования выходного сигнала перемежителя, первое и второе устройства завершения для завершения блоков данных входных и выходных информационных битов первого и второго кодеров, генератор остаточных битов для запоминания остаточных битов, используемых в завершении блока данных, и контроллер, и переключатель для управления изложенной выше процедурой. Технический результат, достигаемый при реализации заявленной группы изобретений, состоит в обеспечении разных скоростей кодирования и снижения сложности декодера. 10 с. и 32 з.п. ф-лы, 13 ил., 9 табл.

СПОСОБ И УСТРОЙСТВО ДЛЯ КОДИРОВАНИЯ И ДЕКОДИРОВАНИЯ ДАННЫХ

Изобретение относится к кодированию и декодированию данных, в частности к способу и устройству для выбора размеров перемежителя для турбокодов. Во время работы принимается блок информации размера K. Определяется размер K' перемежителя, который связан с K'', где K'' - из набора размеров, причем этот набор размеров содержит K''=ap×f, pmin≤p≤pmax, fmin≤f≤fmax, где а - целое число, и f - постоянное целое число между fmin и fmax, р принимает целочисленные значения между pmin и pmax, a>1, pmax>pmin, pmin>1. Во входной блок размера K' вставляется блок информации размера K с использованием битов-заполнителей, если требуется. С использованием исходного входного блока и перемеженного входного блока выполняется кодирование с использованием турбокодера для получения блока кодового слова. Этот блок кодового слова передается через канал. Технический результат - обеспечение высокого уровня параллельной обработки без конфликтов при обращении к памяти турбоперемежителя. 2 н. и 7 з.п. ф-лы, 6 ил., 1 табл ...

ПЕРЕМЕЖИТЕЛЬ В ГРУППОВОМ СПЕКТРЕ

Изобретение относится к перемежающему средству или перемежителю для системы мобильной телесвязи с многостанционным доступом с кодовым разделением (МДКР), и в частности к перемежителю в групповом спектре для каналов прямой передачи и пейджинга. Технический результат - обеспечение улучшенного перемежителя в групповом спектре для каналов прямой передачи и пейджинга с уменьшенной емкостью памяти перемежения и более простой конструкцией. В перемежителе схема по модулю 16 делит индекс на число 16, причем индекс выбирается из множества последовательных индексов 0-383, соответствующих входным данным, и обеспечивает остаток от деления этого индекса. Инвертор битов проводит инверсию битов на выходе схемы по модулю 16 и определяет позицию столбца для записи в данных с проведенным перемежением. Схема частного по модулю 16 вырабатывает частное от деления индекса на число 16. Кодовый преобразователь имеет таблицу строк, по которой частное соответственно соотносится с позицией строки, чтобы записать его ...

УСТРОЙСТВО БЕСПРОВОДНОЙ СВЯЗИ, СПОСОБ БЕСПРОВОДНОЙ СВЯЗИ И ПРОГРАММА

Изобретение относится к технике связи и может использоваться в устройствах беспроводной связи. Технический результат состоит в повышении пропускной способности передачи. Для этого способ беспроводной связи способен усовершенствовать технологию беспроводной связи, относящейся к IDMA. Обеспечивается устройство беспроводной связи, содержащее: блок беспроводной связи, осуществляющий беспроводную связь с другим устройством беспроводной связи, используя мультидоступ с разделением каналов посредством чередования (IDMA); и контроллер, управляющий длиной чередования в процессе чередования для IDMA посредством блока беспроводной связи. 6 н. и 15 з.п. ф-лы, 43 ил., 5 табл.

ПРИЕМНОЕ УСТРОЙСТВО, СПОСОБ ПРИЕМА, ПРОГРАММА И ПРИЕМНАЯ СИСТЕМА

Изобретение относится к приемному устройству, способу приема, носителю записи и приемной системе для выполнения процесса временного деперемежения, пригодного для приемников, совместимых с DVB-T.2. Техническим результатом является обеспечение возможности одновременного приема данных и сигналов управления одним и тем же устройством. Приемное устройство, соответствующее стандарту Т.2 цифрового телевещания, известному как DVB-T2, выполненное с возможностью выполнения декодирования кодов низкой плотности с контролем четкости (НПКЧ) для магистралей физического уровня (МФУ) (PLC), обозначающих потоки данных, и уровня 1 (L1), представляющего параметры передачи физического уровня. Приемное устройство включает в себя устройство декодирования НПКЧ, выполненное с возможностью того, что, когда сигнал кодированных НПКЧ данных и сигнал управления кодированной НПКЧ передачей передаются мультиплексированными, упомянутое устройство декодирования НПКЧ может декодировать как сигнал данных, так и сигнал управления ...

СПОСОБЫ И УСТРОЙСТВО ДЛЯ ФОРМИРОВАНИЯ МНОЖЕСТВА КОНТРОЛЬНЫХ ЗНАЧЕНИЙ ЦИКЛИЧЕСКОГО ИЗБЫТОЧНОГО КОДА (CRC)

... 1. Способ осуществления связи, содержащий ! вычисление контрольного значения циклического избыточного кода для транспортного блока на основе транспортного блока информационных бит путем использования выбранного порождающего многочлена для контрольного значения циклического избыточного кода; ! сегментацию транспортного блока по меньшей мере на один кодовый блок; ! вычисление по меньшей мере одного контрольного значения циклического избыточного кода для кодового блока на основе по меньшей мере одного кодового блока путем использования выбранного порождающего многочлена для контрольного значения циклического избыточного кода, причем одно контрольное значение циклического избыточного кода для кодового блока вычисляют на основе одного соответствующего кодового блока; и ! передачу по меньшей мере одного кодового блока и по меньшей мере одного контрольного значения циклического избыточного кода для кодового блока по меньшей мере через одну передающую антенну, причем информационные биты в транспортном ...

ДИНАМИЧЕСКОЕ ПЕРЕМЕЖЕНИЕ ПОТОКОВ И ДОСТАВКА НА ОСНОВЕ ПОДПОТОКОВ

... 1. Способ передачи потока содержимого в системе связи, включающей в себя, по меньшей мере, один передатчик и, по меньшей мере, один приемник, причем способ содержит этапы, на которых ! формируют соединение между приемником и первым передатчиком; !принимают в приемнике первый поток содержимого, передаваемый от первого передатчика, при этом первый поток содержимого содержит начальную величину перемежения; и ! регулируют величину перемежения, содержащегося в первом потоке содержимого, во время передачи первого потока содержимого, независимо от структуры исходных блоков первого потока содержимого. ! 2. Способ по п.1, в котором начальная величина перемежения в первом потоке содержимого сконфигурирована так, что нет начального перемежения в первом потоке содержимого. ! 3. Способ по п.1, в котором величина перемежения в первом потоке содержимого регулируется от начальной величины до величины установившегося режима. ! 4. Способ по п.3, в котором перемежение в первом потоке содержимого линейно переходит ...

УСТРОЙСТВО ДЛЯ ГЕНЕРИРОВАНИЯ КОДОВ В СИСТЕМЕ СВЯЗИ

... 1. Устройство перемежения для генерирования ККТК (квазикомплементарного турбо кода),включающее турбо кодер для генерирования последовательности информационных символов и множества последовательностей символов четности путем кодирования последовательности информационных символов, содержащее перемежитель для перемежения по отдельности последовательности информационных символов и последовательностей символов четности, мультиплексор для генерирования новой последовательности символов четности путем мультиплексирования перемеженных символов соответствующих последовательностей символов четности, и объединитель символов для последовательного объединения перемеженной последовательности информационных символов и новой последовательности символов четности. 2. Устройство перемежения по п.1, в котором перемежитель перемежает по отдельности последовательность информационных символов и множество последовательностей символов четности посредством перемежения ЧОПБ (с частичным обратным порядком битов).

СПОСОБ И УСТРОЙСТВО ДЛЯ ПЕРЕМЕЖЕНИЯ БИТОВ СИГНАЛОВ В СИСТЕМЕ ЦИФРОВОГО ЗВУКОВОГО РАДИОВЕЩАНИЯ

... 1. Способ перемежения битов цифрового сигнала, представляющего данные и/или аудиоданные в системе цифрового звукового радиовещания, который содержит шаги: записи множества битов цифрового сигнала во внутреннюю матрицу; считывания битов из внутренней матрицы; при этом, по меньшей мере, один из шагов записи и считывания выполняется по непоследовательной схеме адресации; и записи битов в выходную матрицу. 2. Способ по п.1, по которому число битов в выходной матрице равно числу битов в кадре передачи цифрового сигнала. 3. Способ по п.1, по которому биты во внутренней матрице располагаются во множестве секторов. 4. Способ по п.3, по которому каждый из секторов содержит множество блоков. 5. Способ по п.3, по которому каждый из секторов содержит группу битов, представляющих логический канал. 6. Способ по п.5, по которому биты в каждом логическом канале скремблируются. 7. Способ радиопередачи цифровой информации, представляющей данные и/или аудиоданные в системе цифрового звукового радиовещания ...

Способ и устройство дл формировани (n,3) кода и (n,4)кода с использованием симплексных кодов

... 1. Устройство для кодирования информационного битового потока с 3 битами в (n, 3) кодовое слово с n кодовыми символами, содержащее симплексный кодер, предназначенный для формирования кодового слова Рида - Маллера первого порядка с (Р+1) кодовыми символами из входного информационного битового потока для n>Р, а также для выкалывания первого кодового символа из (Р+1) кодовых символов Рида - Маллера первого порядка для создания (Р, 3) симплексного кодового слова, перемежитель, предназначенный для перестановки Р кодовых символов (Р, 3) симплексного кодового слова столбцами согласно заданной конфигурации, и повторитель, предназначенный для повторения переставленного столбцами (Р, 3) кодового слова до тех пор, пока число повторяющихся кодов не станет равным n, и для выведения (n, 3) кодового слова с повторяющимися n кодовыми символами. 2. Устройство по п.1, отличающееся тем, что если k=3, то (Р, 3) симплексное кодовое слово переставляется столбцами согласно следующей конфигурации: [S1, S2, S3, ...

УСТРОЙСТВО УПРАВЛЕНИЯ СВЯЗЬЮ, УСТРОЙСТВО РАДИОСВЯЗИ, СПОСОБ УПРАВЛЕНИЯ СВЯЗЬЮ, СПОСОБ РАДИОСВЯЗИ И ПРОГРАММА

УСТРОЙСТВО БЕСПРОВОДНОЙ СВЯЗИ, СПОСОБ БЕСПРОВОДНОЙ СВЯЗИ И ПРОГРАММА

УСТРОЙСТВО БЕСПРОВОДНОЙ СВЯЗИ И СПОСОБ БЕСПРОВОДНОЙ СВЯЗИ

... 1. Устройство беспроводной связи, используемое в системе беспроводной связи для передачи множества потоков, причем устройство беспроводной связи включает в себякодер, выполненный с возможностью кодирования передаваемой битовой последовательности;канальный перемежитель, содержащий субблочный перемежитель для выполнения в отношении кодированных данных субблочного перемежения по субблокам;модулятор, выполненный с возможностью генерирования последовательности модулированных символов из битовой последовательности, выдаваемой из канального перемежителя;преобразователь потоков, выполненный с возможностью преобразования последовательности модулированных символов во множество потоков; ипередатчик, выполненный с возможностью передачи множества потоков, причемпреобразователь потоков выполнен с возможностью последовательного преобразования последовательности модулированных символов во множество потоков в каждом блоке, выдаваемом из канального перемежителя, и изменения способа преобразования потоков ...

Устройство и способ генерировани и декодировани кодов в системе св зи

... 1. Устройство генерирования квазикомплементарных турбо-кодов (ККТК), содержащее турбо-кодер, включающий в себя по меньшей мере один частный кодер для приема потока информационных битов для генерирования потока информационных символов и по меньшей мере одного потока символов четности согласно заданной кодовой скорости, причем каждый из частных кодеров генерирует по меньшей мере один поток символов четности, при этом потоки символов четности из одного частного кодера соответствуют потокам символов четности из другого частного кодера, канальный перемежитель для независимого перемежения потоков информационных символов и потоков символов четности из частных кодеров, последовательного независимого размещения перемеженных символов в потоках соответствующих символов четности из частных кодеров и последовательного комбинирования потока независимо перемеженных информационных символов и потоков последовательно размещенных символов четности, и селектор ККТК для повторения потока, полученного путем ...

СПОСОБ ПЕРЕДАЧИ ДАННЫХ СИГНАЛА В ГЛОБАЛЬНОЙ НАВИГАЦИОННОЙ СПУТНИКОВОЙ СИСТЕМЕ С ИСПОЛЬЗОВАНИЕМ СВЕРТОЧНЫХ КОДОВ С НИЗКОЙ ПЛОТНОСТЬЮ КОНТРОЛЯ ЧЕТНОСТИ И СИСТЕМА ДЛЯ ОСУЩЕСТВЛЕНИЯ ТАКОГО СПОСОБА

... 1. Способ передачи данных сигнала в глобальной навигационной спутниковой системе (GNSS) с использованием сверточных кодов с низкой плотностью контроля четности (LDPC) и алгоритма обмена сообщениями, содержащий:форматирование на передающем конце данных сигнала в множество подкадров;кодирование каждого подкадра данных сигнала в соответствии с матрицей контроля четности, заданной представлением графа Таннера для сверточных кодов LDPC;перемежение кодированных данных сигнала и добавление к ним поля синхрослова для передачи перемеженного блока кодированных данных сигнала через канал связи;обратное перемежение на приемном конце перемеженного блока кодированных данных сигнала после его приема из упомянутого канала связи; идекодирование кодированных данных сигнала по методике обмена сообщениями, чтобы получить данные сигнала, первично переданные на передающем конце.2. Способ по п.1, в котором кодированные данные сигнала перемежают по блокам путем записи в запоминающую матрицу либо по столбцам, либо ...

НОВАЯ СТРУКТУРА КОДОВОЙ КОМБИНАЦИИ ДЛЯ ПЕРЕДАЧИ ФРЕЙМОВ И ДАННЫХ В СИСТЕМАХ С МНОЖЕСТВОМ НЕСУЩИХ

... 1. Устройство (54) передачи, предназначенное для передачи сигналов в системе с множеством несущих на основе структуры фрейма, причем каждый фрейм содержит, по меньшей мере, одну кодовую комбинацию сигналов и одну или больше кодовых комбинаций данных, упомянутое устройство передачи содержит ! средство (59) формирования фрейма, выполненное с возможностью размещения данных сигналов в упомянутой, по меньшей мере, одной кодовой комбинации сигналов во фрейме и размещения данных и, по меньшей мере, одного пилотного сигнала в упомянутой одной или больше кодовых комбинациях данных во фрейме, в результате чего длина каждой из упомянутых одной или больше кодовых комбинаций данных в направлении частоты равна или составляет кратное минимальной длины кодовой комбинации данных, ! средство (60) преобразования, выполненное с возможностью преобразования упомянутой, по меньшей мере, одной кодовой комбинации сигналов и упомянутой одной или больше кодовых комбинаций данных из области частоты в область времени ...

СТРУКТУРА ПЕРЕМЕЖЕНИЯ КАНАЛОВ ДЛЯ СИСТЕМЫ БЕСПРОВОДНОЙ СВЯЗИ

... 1. Способ, который способствует применению гибридной передающей структуры в среде беспроводной связи, содержащий этапы, на которых: ! разбивают блок переноса на множество кодовых блоков; ! разделяют каждый из множества кодовых блоков на два или более соответственных сегментов кодового блока; ! передают соответственный первый сегмент кодового блока, ассоциированный с каждым из множества кодовых блоков, за первый временной интервал субкадра; и ! передают соответственный второй сегмент кодового блока, ассоциированный с каждым кодовым блоком из множества, за второй временной интервал субкадра. ! 2. Способ по п.1, в котором блоком переноса является Протокольный блок данных (PDU) Управления доступом к среде (MAC), предоставляемый физическому уровню для кодирования. ! 3. Способ по п.1, дополнительно содержащий этапы, на которых: ! разбивают блок переноса на четыре кодовых блока; ! разделяют каждый из четырех кодовых блоков на два сегмента кодового блока; ! передают первые четыре сегмента кодового ...

Fehlerkorrekturkoder und Dekoder

MULTIPLEXVERFAHREN UND MULTIPLEXVORRICHTUNG SOWIE VERFAHREN UND VORRICHTUNG ZUR ÜBERTRAGUNG VON DATENSIGNALEN

Vorrichtung zur Erzeugung von Codes in Kommunikationssystemen

Verschachteler und zugeordnete Verfahren

Verfahren zum Erzeugen von Blöcken aus Daten, wobei das Verfahren aufweist: Aufteilen von Daten in ein Spaltenformat aus N Zeilen und M Spalten, wobei das Spaltenformat erzeugt wird, indem Daten zeilenweise in das Format gelesen werden; spaltenweises Auslesen von Daten aus dem Spaltenformat, wobei ein Intervall zwischen aufeinanderfolgend gelesenen Spalten größer ist als 1; Erzeugen eines Blocks aus Daten aus einer Anzahl M der gelesenen Daten; und Zuordnen des Blocks aus Daten zu einer Vielzahl von Unterträgern, die einem Mehrträger-Kommunikationskanal zugewiesen sind, wobei eine Spanne zwischen Unterträgern für benachbarte Blöcke aus Daten größer ist als 3, wobei das Aufteilen von Daten weiter aufweist: Erzeugen einer Anzahl unterschiedlicher Versionen des Spaltenformats, wobei ein jedes einer Anzahl von räumlichen Strömen zugewiesen ist, die erzeugt werden, wobei die Differenz zwischen den Versionen des Spaltenformats eine Frequenzverschiebung in den Spalten zwischen den Versionen ist ...

Iterative Demodulation und Dekodierungeines Mehrpegel-Signals

Wiedergabe von digitalen Medien

Vorrichtung und Verfahren zum Minimieren der durch Puncturing verursachten Ausgangsverzögerung

Eine Vorrichtung und ein Verfahren, bei denen Daten der Größe S in einem Speicher der Größe K, der eine zweidimensionale Matrix aus R Zeilen und C Spalten ist, gespeichert werden und Verschachtelungsindizes I in Übereinstimmung mit einer vorgegebenen Verschachtelungsregel erzeugt werden, um die Daten zufällig aus dem Speicher auszulesen. Falls ein erster Index größer als die Datengröße S ist, wird ein zweiter Index erzeugt und ausgegeben, bevor ungültige Daten, die in dem Speicher an der Stelle des ersten Index gespeichert sind, ausgegeben werden.

Decoding device, decoding method, and receiving apparatus

A DAB receiver channel decoder

A Coded Orthogonal Frequency Division Multiplex (COFDM) cannel decoding apparatus in which the frequency deinterleaving (or bit deinterleaving or symbol deinterleaving) step is merged with the bit-reversing step of the Fast Fourier Transform (FFT) processor (block 1). The combined function may also be combined with certain demodulation function (DQPSK or QAM) (Figure 6). The hardware/software arrangement of the COFDM decoder is simplified and has reduced memory requirements for storing intermediate results. In contrast to conventional arrangements (Figure 1) wherein the decoder performs the steps in the order of FFT processing the demodulation then deinterleaving the proposed arrangement performs FFT processing then deinterleaving before demodulation. The arrangement may be used for example in DAB, DVB-T, DVB-H or DRM systems.

System and method for forward error correction

A forward error correction system (30) for reducing the transmission error in a data transmission is provided. The system comprises an encoder (12) for encoding data, an interleaver (20) for interleaving the encoded data to an output data stream and a first buffer (32a) for storing the interleaved data. A transmitter (14) is operatively associated with the first buffer (32a) for transmitting the interleaved data. A deinterleaver (22) receives and deinterleaves the transmitted interleaved data and a second buffer (32b) operatively coupled with the deinterleaver stores the deinterleaved data. A decoder (16) operatively coupled with the second buffer (32b) decodes the deinterleaved data. The deinterleaved data is decoded without intermediate storage, reducing the storage requirements.

DVB-T2 OFDM interleaver with large symbol sequential write/PR read/PR write/sequential read mode and small symbol sequential write/PR read mode

In DVB-T symbols are interleaved on to OFDM sub-carriers. The existing interleavers write a first symbol to memory sequentially 132 and read it out according to a pseudo-random (PR) pattern 134. The next symbol is immediately written to these PR locations 120 and then read sequentially 126, and so on. The former operation (sequential write/PR read) produces better separation of initially adjacent symbols (Fig. 6). DVB-T2 uses OFDM transmission in 1/2/4/8/16/32k sub-carrier modes and allows switching between these modes. The invention switches interleaving schemes between the DVB-T one above and one where alternate symbols are assigned their own memory area to perform sequential write/PR read (Fig. 10), depending upon whether the number of carriers is less than half the number of memory locations. Thereby maximising symbol separation. The PR pattern is produced by feeding the output of an LFSR through a permutation matrix. The symbol/sub-carrier relationship ...

Interleaving or de-interleaving of data of variable rate

Method and apparatus for configuring a communication channel

Interleaver and de-interleaver systems

Method and apparatus for configuring a communication channel

ERROR DETECTION SYSTEM

Data processing apparatus and method

NESTING WITH ITERATIVE COMPUTATION OF NESTING ADDRESSES

PROCEDURE AND ARRANGEMENT FOR THE EXECUTION OF INTRARAHMENVERSCHACHTELUNG

DEVICE AND PROCEDURE FOR SENDING AND RECEIVING A OFDM OF BROADCAST SIGNAL

DEVICE AND PROCEDURE FOR THE DATA PROCESSING

DEVICE AND PROCEDURE FOR THE DATA PROCESSING

DEVICE FOR SENDING AND RECEIVING A SIGNAL AND A PROCEDURE FOR SENDING AND RECEIVING A SIGNAL

DEVICE AND PROCEDURE FOR THE DATA PROCESSING

PROCEDURE AND DEVICES FOR PRODUCING A PERMUTATION FOR FORWARDING DISTANCE LEAP IN A WIRELESS COMMUNICATION SYSTEM

PROCEDURE AND DEVICE FOR THE DATA NESTING WITH PSEUDO RANDOM NEW SYNCHRONISATION

SYSTEM FOR PROCESSING AND TRANSMISSION OF PCM SIGNALS.

REDUCE FROM SCINTILLATION EFFECTS DURING OPTICAL FREE SPACE TRANSMISSION

NESTING AND TRELLISDEKODIERUNG WITH NICHTKOHÄRENTER DETECTION OVER SEVERAL SYMBOLS AGAINST A POSSIBLE FREQUENZVERSCHIEBUNG

DEVICE AND PROCEDURE FOR TURBOVERSCHALTELUNG

PROCEDURE AND DEVICE FOR THE ALLOCATION OF FOLDING-CODED BITS TO SYMBOLS BEFORE THEIR MODULATION

MORE VERSCHACHTELER AND NESTING PROCEDURES OF A DATA INPUT BIT SEQUENCE WITH USE OF A CODED RECORDING OF SYMBOLS AND ADDITIONAL INFORMATION

Coding method and device

Provided in the application are a coding method and a device. The method comprises the following steps: performing CRC (Cyclic Redundancy Check) coding on a number A of to-be-coded information bits to obtain a first bit sequence, wherein the first bit sequence comprises L number of CRC bits and A number of information bits; performing an interleaving operation on the first bit sequence to obtain a second bit sequence, wherein a first interleaving sequence used in the interleaving operation is obtained according to the longest interleaving sequence supported by the system and a preset rule. The length of the first interleaving sequence is equal to A+L, or a second interleaving sequence used in the interleaving operation is the longest interleaving sequence. the length of the second interleaving sequence is equal to K ...

Data processing device and data processing method

Channel encoding/decoding apparatus and method using parallel contenated low density parity check code

Encoder, decoder, encoding method, and decoding method

An encoder includes: a precoder for encoding an input information object according to a preset encoding scheme and storing the encoded information object in a precoder buffer; a sample number/address generation unit for generating a sample number of each sample and an address, which corresponds to each bit of each sample and the address of the precoder buffer; a multiplexer for selecting a bit of the precoder buffer corresponding to the address generated by the sample number/address generation module; a sampling buffer for storing a bit of each sample output from the multiplexer; a control packet generation module for generating a control packet including information on the sample number generated by the sample number/address generation module; a packet assembling unit for assembling the sample stored in the sampling buffer with the control packet generated by the control data generation module; and a modulation module for modulating the packet output from the packet assembling unit into ...

Method and apparatus for adaptive control of forward error correction codes

Apparatus and method for generating codes in communication system

Method and apparatus for interleaving a data block

Channel interleaving structure for a wireless communication system

Communication control apparatus, radio communication apparatus, communication control method, radio communication method, and program

Provided is a communication control apparatus including a communication unit configured to perform communication with a radio communication apparatus of a communication system in which interleave division multiple access (IDMA) is used, and an interval control unit configured to dynamically change an interval of allocation of an interleaver used for IDMA by the radio communication apparatus.

A communication apparatus and method for a cdma communication system

Method and apparatus for performing rate determination using orthogonal rate-dependent walsh covering codes

Interleaver and deinterleaver for use in a diversity transmission communication system

DIGITAL TELEVISION TRANSMITTER AND METHOD OF CODING DATA IN DIGITAL TELEVISION TRANSMITTER

A pre-processor pre-processes enhanced data packets by coding the enhanced data packets for forward error correction (FEC) and expanding the FEC-coded data packets. A data formatter adds first null data into first place holders within each pre-processed enhanced data packet. A first multiplexer multiplexes the main data packets with the enhanced data packets having the first null data. A holder inserter inserts second null data into second place holders within an enhanced data packet outputted from the first multiplexer. A data interleaver replaces the second null data with parity data. A data generator generates at least one known data sequence. A symbol processor replaces the first null data included in an output of the data interleaver with the known data sequence(s). A non-systematic RS encoder generates the parity data by performing non-systematic RS-coding on an output of the symbol processor, and provides the parity data to the data interleaver.

AN ITERATIVE DECODER AND AN ITERATIVE DECODING METHOD FOR A COMMUNICATION SYSTEM

An iterative decoder and iterative decoding method. In the iterative decoder, a first adder has a first port for receiving information symbols and a second port; a first component decoder is coupled to the first adder, for receiving first parity symbols and decoding the information symbols using the first parity symbols and an output signal of the first adder, a first subtractor has a third port for receiving the output of the first component decoder, and a fourth port; an interleaver coupled to the output of the second adder, for interleaving the decoded information symbols received from the first component decoder, a second component decoder receives the output of the interleaver and second parity symbols and decodes the information symbols of the interleaver output using the received signals; a deinterleaver deinterleaves the output of the second component decoder, a third adder has a fifth port for receiving the output of the deinterleaver and a sixth port for receiving an inversed ...

VSB RECEPTION SYSTEM WITH ENHANCED SIGNAL DETECTION FOR PROCESSING SUPPLEMENTAL DATA

A digital television (DTV) receiver comprises a demodulator configured to demodulate a DTV signal containing first service data multiplexed with second service data. A first decoder is configured to decode the demodulated DTV signal for first error correction, in order to correct errors in the first and second service data that occurred during reception of the DTV signal. A data separator is configured to separate the first service data and the second service data from the decoded DTV signal and a second decoder is configured to further decode the separated first service data for second error correction in order to additionally correct errors in the first service data that occurred during the reception of the DTV signal.

SIGNAL MULTIPLEXING DEVICE AND SIGNAL MULTIPLEXING METHOD USING LAYERED DIVISION MULTIPLEXING

... ²An apparatus and method for multiplexing signals using layered division ²multiplexing are disclosed. A signal multiplexing apparatus according to an ²embodiment of the present invention includes a combiner configured to combine ²a core layer signal and an enhanced layer signal at different power levels, ²and a ²time interleaver configured to perform interleaving applied to both the core ²layer ²signal and the enhanced layer signal.² ...

TERMINAL APPARATUS, BASE STATION APPARATUS, AND COMMUNICATION METHOD

A communication method to be used by a terminal device, the method being provided with a step for separately creating a first encoded bit fk of a transport block, a second encoded bit q0 of control information, and a third encoded bit q1 of a rank indicator, and creating a multiplexed bit gk by multiplexing the first encoded bit fk and the second encoded bit q0, and a step for creating a first sequence hk by multiplexing the multiplexed bit gk and the third encoded bit q1, wherein the location where the third encoded bit q1 is mapped is assigned on the basis of at least one condition among a first condition, a second condition, and a third condition. The first condition is whether the search space where the PDCCH is detected is CSS or USS, the second condition is whether the CRC parity bit added to the DCI format is an RNTI and is scrambled, and the third condition is whether a first method or a second method is used for the first encoded bit.

TURBO INTERLEAVER FOR HIGH DATA RATES

Techniques for supporting high decoding throughput are described. A trans mitter may encode a code block of data bits with a Turbo encoder. A receiver may perform decoding for the code block with a Turbo decoder having multipl e soft-input soft-output (SISO) decoders. A contention-free Turbo interleave r may be used if the code block size is larger than a threshold size. A regu lar Turbo interleaver may be used if the code block size is equal to or smal ler than the threshold size. The contention-free Turbo interleaver reorders the data bits in the code block such that information from the multiple SISO decoders, after interleaving or deinterleaving, can be written in parallel to multiple storage units in each write cycle without encountering memory ac cess contention. The regular Turbo interleaver can reorder the data bits in the code block in any manner without regard to contention-free memory access .

CODE INTERLEAVING FOR WALSH CODES

Communication systems and methods that mitigate false alarms due to Doppl er shift are disclosed. Received message data is mapped to orthogonal Walsh codes, interleaved and scrambled with appropriate PN sequence prior to trans mission. The transmitted message data is descrambled and deinterleaved upon reception. The energies associated with each of the Walsh code from various antennas and/or signal paths are combined to obtain a total energy for each Walsh code. If the total energy of the Walsh code exceeds a certain threshol d it is declared as the received message else an erasure is indicated. As th e data is interleaved prior to transmission, any phase ramp introduced due t o Doppler is transformed into random phase errors upon deinterleaving at the receiver thereby mitigating false alarms.

INTERLEAVER APPARATUS AND RECEIVER FOR A SIGNAL GENERATED BYTHE INTERLEAVER APPARATUS

A convolution interleaver for processing a codeword which is derived from an input block of symbols using a redundancy-adding code (22) and which has more symbols than the input block, where the codeword has a sequence of int erleaving units, each interleaving unit having at least two symbols, compris es an interleaving device (10). The interleaving device alters the sequence of interleaving units in order to obtain an interleaved codeword which has a n altered sequence of interleaving units. In particular, the interleaving de vice does not alter the order of the symbols within an interleaving unit. Ho wever, the order of the interleaving units in the codeword is altered among one another or in respect of a preceding or succeeding codeword.

TIME INTERLEAVER, TIME DEINTERLEAVER, TIME INTERLEAVING METHOD, AND TIME DEINTERLEAVING METHOD

A convolution interleaver, which is included in a time interleaver and performs a convolution interleaving, comprises: a first switch for switching the connection destination of the input of the convolution interleaver to an end of any one of a plurality of branches; FIFO memories disposed in some of the plurality of branches except one branch in such a manner that the number of FIFO memories is different among said some of the plurality of branches; and a second switch for switching the connection destination of the output of the convolution interleaver to the other end of said any one of the plurality of branches. When a plurality of cells, the number of which is equal to the number of code words per frame, have passed, the first and second switches switch said connection destinations in such a manner that the branching of the destinations is performed by repeating the plurality of branches in turn.

PARITY PUNCTURING DEVICE FOR FIXED-LENGTH SIGNALING INFORMATION ENCODING, AND PARITY PUNCTURING METHOD USING SAME

A parity puncturing apparatus and method for fixed length signaling information are disclosed. A parity puncturing apparatus according to an embodiment of the present invention includes memory configured to provide a parity bit string for parity puncturing for the parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, and a processor configured to puncture a number of bits corresponding to a final puncturing size from the rear side of the parity bit string.

METHOD AND APPARATUS FOR ENCODING AND DECODING LOW DENSITY PARITY CHECK

An encoding apparatus is provided. The encoding includes a low density parity check (LDPC) encoder which performs LDPC encoding on input bits based on a parity-check matrix to generate an LDPC codeword formed of 64,800 bits, in which the parity-check matrix includes an information word sub-matrix and a parity sub-matrix, the information word sub-matrix is formed of a group of a plurality of column blocks each including 360 columns, and the parity-check matrix and the information word sub-matrix are defined by various tables which represent positions of value one (1) present in every 360-th column.

TRANSMITTER AND SYSTEM FOR TRANSMITTING/RECEIVING DIGITAL BROADCASTING STREAM AND METHOD THEREOF

A digital broadcasting transmission apparatus and a transmission method are provided. The transmission apparatus includes a plurality of encoders for encoding a plurality of additional data streams, a re-arrangement unit for rearranging the plurality of encoded additional data streams, and a stuffer for inserting the plurality of rearranged additional data streams into a normal data stream.

DIGITAL BROADCASTING TRANSMITTER, DIGITAL BROADCASTING RECEIVER, AND STREAM CONFIGURATION AND METHOD FOR PROCESSING SAME

Disclosed is a stream-processing method for a digital broadcasting transmitter. The method includes configuring streams in which slots including a plurality of blocks are continuously disposed, and encoding and interleaving the streams to be output as transport streams. Here, the configuring of the streams may include placing base data in a predetermined segment of each adjacent slot to form a long training sequence in boundary portions of adjacent slots that are interlocked in a saw-toothed configuration, when slots set in a block expansion mode 00 are continuously disposed to allow entire blocks in a corresponding slot to be used. Accordingly, a digital broadcasting service becomes available in various formats.

METHOD AND APPARATUS FOR MINIMIZING DELAY VARIANCE VIA TIME DIVIDED TRANSMISSIONS

A local area network for connection between a terrestrial cell/packet based network and a time division based point-to-multipoint network comprising a switch (10), an interface (710) including a time stamp processing unit (701) and a frame counter unit (702), means for forming a time marked cell/packet (720), means for assembling into a time division frame (730), and a modem (740) for transmitting time division frame.

INFORMATION DATA MULTIPLEXING TRANSMISSION SYSTEM, MULTIPLEXER AND DEMULTIPLEXER USED THEREFOR, AND ERROR CORRECTING ENCODER AND DECODER

On the transmission side, a multiplexing section estimates the quantities of information from signal processing sections, determines multiplexing codes based on the quantities of information, takes the parity of a determined first multiplexing code, and uses the parity as a second multiplexing code. The multiplexing section then generates two headers (H1) and (H2) by adding a CRC to each multiplexing code, fetches information data of each medium in accordance with the multiplexing codes, incorporates the data in a packet together with the two headers (H1) and (H2) and outputs the packet. On the reception side, error correction decoding is performed by using the header (H2) when the error correction of the header (H1) is impossible, or by using both headers (H1) and (H2) when the error correction of the header (H2) is also impossible.

Anlage zur Übertragung von Nachrichten

MODULE PARALLEL BITS INTERLEAVING

MODULE PARALLEL BITS INTERLEAVING

MODULE PARALLEL BITS INTERLEAVING

СИСТЕМА И ПРОЦЕССОР ПЕРЕМЕЖЕВАНИЯ

Заявлены система и способ для частотного разнесения, которые используют перемежевание. Поднесущие чередования перемежевываются способом реверсирования битов и чередования перемежевываются способом реверсирования битов.

Pseudo product code coding and decoding equipment and method thereof

Method for reducing the memory size and the time required for the correction of errors in a asynchronous time.

Procedure for on one side arranged data communication over trouble-prone communication links and reconstruction of the disturbed bits

PROCEEDED With CORRECT ENCODING Of ERROR, PROCESS OF DECODING AND DEVICES ASSOCIATE.

ENTRELACEUR AND DEVICE OF DECODING OF NUMERIC SIGNALS COMPRISING A TELENTRELACEUR

PROCESS AND DEVICE OF DECODING OF CODES HAVE CASTERS

La présente invention se rapporte à un procédé et à un dispositif (20) de décodage d'une trame pouvant être décomposée en p sous trames composées chacune de k symboles d'information, de n - k premiers symboles de redondance et de n - k derniers symboles de redondance. Le décodage met en oeuvre deux décodeurs (21, 23) élémentaires qui produisent en parallèle des informations extrinsèques (Extrli, Extr2i) relatives respectivement aux symboles d'information et aux symboles d'information entrelacés. Les valeurs des informations extrinsèques (Extr1i, Extr2i) sont affinées par le rebouclage croisé de ces informations en entrée des décodeurs (21, 23).

Information symbol encoding method for use in coded image transmission application, involves completing words corresponding to redundancy symbol such that other formed words is orthogonal to one matrix, and forming code word

La présente invention concerne un procédé de codage de symboles d'information selon un code défini sur un corps de Galois Fq, où q est un entier supérieur à 2 et égal à une puissance d'un nombre premier, et de longueur n = p(q-1), où p > 1. Ce codage est conçu de manière à ce qu'il existe un procédé de décodage correspondant, lui aussi divulgué par l'invention, dans lequel la correction d'erreurs de transmission est essentiellement ramenée à la correction d'erreurs dans p mots de longueur (q-1) codés selon Reed-Solomon. L'invention est particulièrement avantageuse lorsque, par un choix adéquat de paramètres, le code selon l'invention se trouve être un code de géométrie algébrique : dans ce cas, on peut corriger les erreurs de transmission par le procédé déjà mentionné et/ou par un procédé classique moins économique mais plus performant. L'invention concerne également des dispositifs et appareils destinés à mettre en oeuvre ces procédés de codage et de décodage. Application notamment aux ...

PROCEEDED With CORRECT ENCODING Of ERROR, PROCESS OF DECODING AND DEVICES ASSOCIATE.

La présente invention concerne un procédé d'encodage correcteur d'erreur (300) pour encoder en parallèle des données numériques (30) dites sources, se présentant sous la forme d'une trame (102), lesdites données pouvant être classées en N classes (102i), où N est un entier au moins égal à 2. Le procédé d'encodage selon l'invention comprend : - une première étape d'encodage convolutionnel récursif et systématique (3061) de données à encoder, formées par les données de la classe 1 (1021); et - une mise en œuvre des étapes suivantes, pour chaque n variant de 1 à M, où M est un entier positif inférieur ou égal à N-1 : - nème mélange (304n+1) d'un ensemble formé par les données de la classe n+1 (102n+1) et les données systématique d'un encodage précédent ; (n + 1)ème encodage (306n+1) convolutionnel récursif et systématique de données à encoder, formées par le résultat du nème mélange. L'invention concerne également un procédé de décodage de données encodées suivant le procédé d'encodage selon ...

방송 신호 전송 장치, 방송 신호 수신 장치, 방송 신호 전송 방법 및 방송 신호 수신 방법

... 본 발명의 실시예에 따르면, 서비스 데이터를 인코딩하는 인코더; 상기 인코딩된 데이터를 심볼로 매칭하는 심볼 매퍼; 신호 프레임을 생성하는 프레임 빌더; 프리퀀시 인터리빙 시퀀스를 이용하여 상기 신호 프레임 내에 데이터를 프리퀀시 인터리빙하는 프리퀀시 인터리버; 여기서, 상기 프리퀀시 인터리빙 시퀀스는, 메인 시퀀스 및 심볼 오프셋 시퀀스에 기초하여 생성되고, 상기 프리퀀시 인터리빙 시퀀스가 생성되는 과정은, FFT (fast fourier transform )모드에 기반하여 상기 메인 시퀀스를 생성하는 단계; 두 개의 OFDM 심볼들에 대응한 상기 심볼 오프셋 시퀀스를 생성하는 단계; 및 상기 메인 시퀀스와 상기 심볼 오프셋 시퀀스를 이용하여 생성된 제 1 시퀀스의 어드레스를 체크하고, 상기 제 1 시퀀스의 어드레스가 유효한 범위에 있는 경우 상기 유효한 어드레스 범위의 제 1 시퀀스를, 상기 프리퀀시 인터리빙 시퀀스로 출력하는 단계; 를 포함하고, 상기 프레퀀시 인터리빙된 데이터를 OFDM 스킴에 따라 변조하는 변조부; 및 상기 변조된 데이터를 포함하는 방송 신호를 전송하는 전송부;를 포함하는 방송 신호 전송 장치를 제공한다.

비트 인터리버

... 수신 성능의 향상을 도모하기 위한 본 발명의 비트 인터리브 방법은 의사 순회 저밀도 패리티체크 부호화 방식으로 생성된 부호어의 비트를 재배열하는 비트 인터리브 방법으로, 각 순회블록의 비트의 콘스테레이션 어 중의 위치를 결정하는 순회블록 퍼뮤테이션 규칙에 따라서 부호어의 순회블록을 재배열하는 순회블록 퍼뮤테이션 처리와, 순회블록의 재배열 후의 부호어의 비트를 재배열하는 비트 퍼뮤테이션 처리를 포함한다.

Transmitting/receiving system and data processing method

DEMODULATING AND DECODING SYSTEM IN A RECEIVER FOR IMPROVING DEMODULATING AND DECODING PERFORMANCE

PURPOSE: A demodulating and decoding system in a receiver is provided to insert an LLR(Log Likelihood Ratio) value produced by a BCJR(Bahl, Cocke, Jelinek and Raviv) algorithm in a prior demodulating and decoding process. CONSTITUTION: A demodulating and decoding system(100) in a receiver includes a symbol detection unit(110), an LLR(Log Likelihood Ratio) operation unit(120), and a decoding unit(130). The symbol detection unit detects a symbol from first receiving data. The LLR operation unit computes a first LLR value through the detected symbol. According to the computed first LLR value, the decoding unit decodes the first receiving data. COPYRIGHT KIPO 2011 ...

DATA PROCESSING

Data items in a memory list (12) are de- interleaved or interleaved by sorting them to new positions in the list. A flag (f1 - f6) indicates whether an item has been read for sorting and overwriting is not permitted until the contents of a position have been read for sorting. © KIPO & WIPO 2007 ...

방송 신호 송신 장치, 방송 신호 수신 장치, 방송 신호 송신 방법 및 방송 신호 수신 방법

... 본 발명은 방송 신호를 송신하는 장치를 제공한다. 장치는, 서비스 데이터를 인코딩하기 위한 인코더, 적어도 하나의 신호 프레임을 빌드하기 위해 인코딩된 서비스 데이터를 복수의 OFDM 심볼들로 매핑하기 위한 매퍼, OFDM (Orthogonal Frequency Division Multiplex) 방법에 의해 상기 빌드된 적어도 하나의 신호 프레임 내 데이터를 변조하기 위한 모듈레이터, 변조된 데이터를 갖는 방송 신호를 송신하기 위한 송신기를 포함한다.

Data processing apparatus and method

A data processing apparatus maps input symbols to be communicated onto a predetermined number of carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM carrier signals. The interleaver memory reads-out the data symbols on to the OFDM carriers to effect the mapping, the read-out being in a different order than the read-in, and the order being determined from a set of addresses. The set of addresses are generated from an address generator. The address generator includes a linear feedback shift register and a permutation circuit.

Method for encoding data with double-interlaced parity symbols, for a radio infrastructure, and associated codec

A method is dedicated to encoding data that must be transmitted by means of a wave-based transmission infrastructure, and comprises i) a step consisting of creating in parallel M first matrices having T rows and C columns with subsets of data from B successive received bursts, the subsets of data from each burst being distributed within at least two successive first matrices, ii) a step consisting of creating in parallel M second matrices each having T rows and N columns with parity symbols resulting from encoding the data that is respectively contained in the rows of each of the M first matrices, iii) a step consisting of creating in parallel M first matrices having K rows and C columns with parity symbols resulting from encoding the data that is respectively contained in the columns of each of the M first matrices, and iv) a step consisting of distributing by interlacing, firstly, J subsets of parity symbols from each second matrix into J successive sets, and secondly P subsets of parity symbols from each third matrix into P of these successive sets, and of placing into each of the successive sets the respective data from the successive received bursts.

Radio communication device and radio communication method

To improve the frequency diversity effect by preventing the related bits in the encoded data from being biased to the specified carrier in the case of performing the multicarrier operation. A modulated symbol sequence is segmented in a data segmentation section ( 116 ), and the segmented modulated symbol blocks are mapped on a plurality of carriers in a segment mapping section ( 120 ). The data segmentation section ( 116 ) groups each of K parts in the modulated symbol sequence into the same number of N groups, cyclically shifts the N groups for the respective parts of any (K−1) parts with shift amounts which differ among the parts, and substitutes the cyclically-shifted groups of the plurality of parts in the modulated symbol sequence with one another among the parts to segment the groups into a plurality of blocks.

Apparatus and method for transmitting and receiving data in a communication or broadcasting system using linear block code

Provided is a method for transmitting data in a communication or broadcasting system using a linear block code by generating a codeword by encoding input information data bits, interleaving the codeword; outputting modulation signal-constituting bits by bit-mapping the interleaved codeword using a bit-mapping table predetermined depending on a modulation scheme and a coding rate, outputting a modulation signal by modulating the modulation signal-constituting bits and transmitting the modulation signal via a transmit antenna.

Data recovery using outer codewords stored in volatile memory

Systems and methods are disclosed for data recovery using outer codewords stored in volatile memory. Outer codewords can be associated with one or more horizontal portions or vertical portions of a non-volatile memory (“NVM”). In some embodiments, an NVM interface of an electronic device can program user data to a super block of the NVM. The NVM interface can then determine if a program disturb has occurred in the super block. In response to detecting that a program disturb has occurred in the super block, the NVM interface can perform garbage collection on the super block. The NVM interface can then use outer codewords associated with the super block to recover from any uncorrectable error correction code errors detected in the super block.

Shift register, electronic device, control method and software program product

Disclosed is a shift register ( 200, 400 ) comprising an input ( 205 ), an output ( 230 ) and a plurality of register cells ( 210 ) serially connected between the input and the output, each register cell being connected to a neighboring cell via a node, wherein at least some of said nodes comprise a multiplexer ( 220 ) having an output coupled to the downstream register cell and a plurality of inputs, each of said plurality of inputs being coupled to a different upstream register cell such that different length sections of the shift register can be selectively bypassed, the shift register further comprising a set of parallel IO channels ( 230, 410 ) facilitating conversion between interleaved and de-interleaved data, each of said channels being coupled to a different one of said nodes, the number of parallel IO channels being smaller than the total number of register cells in the shift register.

Encoding module, apparatus and method for determining a position of a data bit within an interleaved data stream

An encoding module comprises an inverse interleaving module arranged to: determine an initial location index within an interleaving matrix for a data bit; and perform bit reverse ordering (BRO) on a column index value for the initial location index for the data bit to obtain a BRO column index value for the data bit. The inverse interleaving module is further arranged to calculate a number of valid interleaving matrix addresses preceding a location index for the data bit following bit reverse ordering; and determine a position of the data bit within the interleaved data stream based on the calculated number of valid addresses.

Method for scheduling distributed virtual resource blocks

A method for transmitting downlink data using resource blocks at a base station in a wireless mobile communication system includes transmitting downlink data mapped to physical resource blocks (PRBs) to a user equipment, wherein indexes of virtual resource blocks (VRBs) are mapped to indexes of the PRBs for a first slot and a second slot of a subframe, and the indexes of the PRBs for the second slot are shifted with respect to the indexes of the PRBs for the first slot based on a predetermined gap, and wherein a predetermined offset is applied to an index of a PRB when the index of the PRB is equal to or greater than a predetermined threshold.

Subset transform interleaver

Digital communications interleavers re-order the bits of a data coding block in a way that can be described by a table of indices that map the original order to the interleaved order. Conventional interleavers include index table interleavers, which store an index table ahead of operation and algorithmic Interleavers, which generate the indices during operation. Described herein are a new class of interleavers: Subset Transform Interleavers. A subset of generator outputs is selected and processed to create the interleaver indices. The selection is determined apriori and the selection results are stored in a Subset Usage Table. During operation, the generator is operated again and the Subset Usage Table entries determine which generator outputs are used. The generator may be a pseudo-random number generator. Implementations can use an Indexes Remaining Table, which can additionally be manipulated during operation such that it returns to an initialized state after each block interleaving process.

Software Defined Radio for Universal Demodulation of Digital and Analog TV Signals

A Software Defined Radio (SDR) subsystem capable of supporting a multiple communication standards and platforms for modulation, demodulation and trans-modulation of an input signal is provided. The SDR subsystem includes a Signal Conditioning Cluster (SCC) unit that includes a signal conditioning CPU adapted for sample based signal processing, a Signal Processing Cluster (SPC) unit that includes a signal processing CPU adapted for block based signal processing, and a Channel Codec Cluster (CCC) unit that performs a channel encoding or a channel decoding operation.

Modulator and modulation method

A transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased. An encoding part subjects transport data to a block encoding process to form block encoded data. A modulating part modulates the block encoded data to form data symbols; and an arranging (interleaving) part arranges (interleaves) the block encoded data in such a manner that the intra-block encoded data of the encoded blocks, which include their respective single different data symbol, get together, and then supplies the arranged (interleaved) block encoded data to the modulating part. In this way, there can be provided a transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased.

Method and apparatus for interleaving data in a mobile communication system

An interleaving method to which time-first-mapping is applied in a mobile communication system is provided. The interleaving method includes writing coded bits into an interleaver on a row-by-row basis, and reading the coded bits written in the interleaver on a column-by-column basis, wherein the coded bits are written by groups having a size according to a modulation order

Transmitter and method for transmitting data block in wireless communication system

Provided are a transmitter and a method for transmitting a data block in a wireless communication system. The method comprises the following steps: deciding the number of bits (s) and encoders (NES) to allocate to one axis of a signal constellation; encoding an information bit based on the s and the NES and generating a coded block; parsing the coded block based on the s and the NES and generating a plurality of frequency sub-blocks; and transmitting the plurality of frequency sub-blocks to a receiver.

Transmitter and method for transmitting data block in wireless communication system

Provided are a transmitter and a method for transmitting a data block in a wireless communication system. The method comprises the following steps: encoding an information bit and generating a block coded with an NCBPSS bit; generating two sub-blocks by parsing the coded block; and transmitting the two sub-blocks to the transmitter. By preventing the bits that are contiguous to the encoding block from having continuous identical reliabilities on a signal constellation, the deterioration of the decoding performance of the transmitter can be prevented.

Memory controller and non-volatile storage device

A non-volatile storage device includes one or more non-volatile memories for storing data, and a memory controller for carrying out the control of the non-volatile memory. The non-volatile memory includes the plurality of blocks, which are erase units, and the block includes the plurality of pages, which are write units of data, in each of the blocks at least one set of pages existing which include at least two pages sharing one word line. The memory controller configures a plurality of error correcting groups, each including at least one data page, which is a page for storing data, and at least one error correcting code page for storing a code for error correcting calculation of the data page, and assigns a page of a separate word line with respect to each of the data page and the error correcting page in the same error correcting group.

Continuously interleaved error correction

Continuously interleaved codewords are used in a communication system to provide error correction capability. In general, each codeword shares symbols with both preceding and subsequent codewords, when the codewords are arranged in an order, such that correction of symbols in any one codeword also corrects symbols in another codeword and correction of symbols in any codeword may allow, considering possible corrections of intermediate codewords, for further correction of any codeword in the order of codewords. In one embodiment received information may be arranged in subframes, with each subframe including terminal symbols of a plurality of codewords, each of the plurality of codewords including symbols in multiple subframes.

Receivers for COFDM digital television transmissions

A receiver of COFDM digital television signals includes an inner decoder for iterative soft-decision decoding of concatenated convolutional coding (CCC) and an outer decoder for Reed-Solomon (RS) coding. The receiver generates error flags for identifying code symbols to be erased before the output symbols from the inner decoder are byte de-interleaved and supplied to the outer decoder. Generation of those flags depends on soft decoding results from the inner decoder. The method of locating errors ascribes to each byte supplied to the outer decoder for RS coding the highest lack-of-confidence level specified by the soft data bits associated with that byte. The method is described as being extended to locate byte errors in plural-dimension cross-interleaved Reed-Solomon codes (CIRC) apt to be employed in DTV broadcasting to mobile and handheld receivers.

Time varying data permutation apparatus and methods

Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations.

Communications system using adaptive orthogonal frequency division multiplexing

In a communications device a grouping unit uses channel state information when mapping data bits to a plurality of different constellation groups. Each constellation group is assigned to another modulation scheme. A plurality of sub-carriers is assigned to none or one of the constellation groups and each modulation uses another one of the constellation groups. The communications device includes at least one scalable interleaver unit, wherein each interleaver unit is assigned to one of the constellation groups and interleaves the assignment of data bits mapped to each constellation group and the sub-carriers that carry a symbol information derived from the data bits. As an example, the interleaver unit performs frequency interleaving by interleaving, at constellation level, the sub-carriers that carry the symbol information.

COMPUTATIONALLY EFFICIENT CONVOLUTIONAL CODING WITH RATE-MATCHING

An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate. 1. An error coding circuit comprising:a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits;an interleaver circuit for interleaving parity bits within each group of parity bits, wherein the interleaver circuit is configured to order parity bits such that odd parity bits precede even parity bits within each group of parity bits; anda rate-matching circuit for outputting a selected number of said interleaved parity bits ordered by group to obtain a desired code rate.2. The error coding circuit of claim 1 , wherein said interleaver circuit implements a reverse bit-reversal order interleaver for column permutation.3. The error coding circuit of claim 1 , wherein said interleaver circuit implements a cyclically-shifted bit-reversal order interleaver for column permutation.4. The error coding circuit of claim 1 , wherein said interleaver circuit implements a modulo-offset bit-reversal order interleaver for column permutation.5. The error coding circuit of claim 1 , further comprising a channel interleaver following the rate-matching circuit6. An error coding circuit comprising:a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits;an interleaver circuit for interleaving parity bits within each group of parity bits; anda rate-matching circuit for outputting a selected number of said interleaved parity bits ordered by group to obtain a desired code rate, wherein said rate-matching circuit is configured to puncture parity bits, when the encoder produces more bits than needed to match a ...

Apparatus and method for transmitting/receiving forward error correction packet in mobile communication system

An apparatus and method for transmitting/receiving a Forward Error Correction (FEC) packet in a mobile communication system are provided. In the FEC packet transmission method, an FEC packet transmission apparatus transmits an FEC delivery block to an FEC packet reception apparatus. The FEC delivery block includes N payloads. Each of the N payloads includes a payload header. Each payload header included in each of C payloads among the N payloads includes packet oriented header information and an FEC delivery block oriented header information fragment. The packet oriented header information is applied to a related payload, and the FEC delivery block oriented header information fragment is generated by fragmenting FEC delivery block oriented header information applied to the N payloads.

Encoding apparatus and encoding method in data communication system

An encoding method and apparatus in a data communication system are provided. The method includes inputting a source block including a plurality of source payloads, converting the source block to an information block including a plurality of information payloads according to an Information Block Generation (IBG) mode selected from a plurality of IBG modes, transmitting a delivery block generated by adding a parity block generated by encoding the information block according to a selected encoding scheme to the source block to a receiver, and transmitting information indicating the selected IBG mode to the receiver.

DETECTION, AVOIDANCE AND/OR CORRECTION OF PROBLEMATIC PUNCTURING PATTERNS IN PARITY BIT STREAMS USED WHEN IMPLEMENTING TURBO CODES

Detecting, avoiding and/or correcting problematic puncturing patterns in parity bit streams used when implementing punctured Turbo codes is achieved without having to avoid desirable code rates. This enables identification/avoidance of regions of relatively poor Turbo code performance. Forward error correction comprising Turbo coding and puncturing achieves a smooth functional relationship between any measure of performance and the effective coding rate resulting from combining the lower rate code generated by the Turbo encoder with puncturing of the parity bits. In one embodiment, methods to correct/avoid degradations due to Turbo coding are implemented by puncturing interactions when two or more stages of rate matching are employed. 1. A method of performing rate matching , the method comprising:interleaving a first bit stream to produce an interleaved first bit stream;interleaving a second bit stream to produce an interleaved second bit stream;interleaving a third bit stream to produce an interleaved third bit stream;buffering the interleaved first bit stream, the interleaved second bit stream and the interleaved third bit stream in a virtual buffer; andperforming rate matching on at least one output of the virtual buffer.2. The method of wherein the interleaved first bit stream claim 1 , the interleaved second bit stream and the interleaved third bit stream are buffered on a condition that the number of bits of the interleaved first bit stream claim 1 , the interleaved second bit stream and the interleaved third bit stream is not larger than a size of the virtual buffer.3. The method of claim 2 , further comprising:buffering a portion of the interleaved first bit stream, the interleaved second bit stream and the interleaved third bit stream in the virtual buffer on a condition that the number of bits of the interleaved first bit stream, the interleaved second bit stream and the interleaved third bit stream is larger than a size of the virtual buffer.4. The ...

Wireless Transmission Reliability

A method for performing error correction during a transmission of physiological data includes two or more data packets that are sent from a first electronic computing device to a second electronic computing device. Each of the data packets includes physiological data. Each of the data packets has a first packet size. Each of the data packets includes error correction information. The error correction information for each of the two or more packets is distributed across the two or more data packets.

System and method for frequency diversity

A system and method for frequency diversity uses interleaving in a wireless communication system utilizing orthogonal frequency division multiplexing (OFDM) with various FFT sizes. Subcarriers of one or more interlaces are interleaved in a bit reversal fashion and the one or more interlaces are interleaved in the bit reversal fashion.

Interleaving method and deinterleaving method

An interleaving method performed by a transmitter for a communication system with quasi-cyclic low-density parity-check codes, spatial multiplexing, and T transmit antennas is used for applying permutation to N cyclic blocks of a codeword in order to map bits of the permutated cyclic blocks onto T constellation words constituting multiple spatial-multiplexing blocks from the codeword. Each cyclic block consists of Q bits.

Multi-processing architecture for an lte turbo decoder (td)

An apparatus comprising a decoder circuit and a memory. The decoder circuit may be configured to generate a single address signal to read a first parity data signal, a second parity data signal and read and/or write systematic information data, a first a-priori-information signal and a second a-priori-information signal. The decoder circuit (i) reads the first parity data signal, the systematic information data and the first a-priori-information during even half-iterations of a decoding operation and (ii) reads the second parity data, the systematic information data and the second a-priori-information during odd half-iterations of the decoding operation. The memory may be configured to store the systematic information data and the first and second a-priori-information signals such that each are accessible by the single address signal.

Apparatus and method of transmitting hierarchically modulated signal

An apparatus and a method of transmitting hierarchically modulated signals are provided. The present invention includes: a basic layer symbol generator generating a first layer signal; an enhancement layer symbol generator generating a second layer signal synchronized with the first layer signal and having different signal power; and a hierarchical modulator hierarchically modulating the first layer signal and the second layer signal, wherein the enhancement layer symbol generator performs constellation rotation rotating bundles configured as constellation points formed by the second layer signal based on constellation points of the first layer signal by a predetermined angle. According to the exemplary embodiment of the present invention, it is possible to improve the receiving performance of the second layer signals by applying the constellation rotation technology to the second layer signals in regards of the signal transmission system using the hierarchical modulation technology.

DECODING APPARATUS WITH DE-INTERLEAVING EFFORTS DISTRIBUTED TO DIFFERENT DECODING PHASES AND RELATED DECODING METHOD THEREOF

A decoding apparatus includes a memory device and a decoding circuit. The memory device is arranged for storing a data block with inter-row interleaving in a plurality of data rows of the data block and without intra-row interleaving in each of the data rows. The decoding circuit is coupled to the memory device. The decoding circuit is arranged for accessing the memory device to perform a first decoding operation with inter-row de-interleaving memory access, and accessing the memory device to perform a second decoding operation with intra-row de-interleaving memory access memory access. 1. A decoding apparatus , comprising:a memory device, arranged for storing a data block with inter-row interleaving in a plurality of data rows of the data block and without intra-row interleaving in each of the data rows; anda decoding circuit, coupled to the memory device, the decoding circuit arranged for accessing the memory device to perform a first decoding operation with inter-row de-interleaving memory access, and accessing the memory device to perform a second decoding operation with intra-row de-interleaving memory access memory access.2. The decoding apparatus of claim 1 , wherein the decoding circuit comprises M decoder cores used for parallel decoding when performing the second decoding operation claim 1 , where each of the M decoder cores is arranged for decoding N data bits per cycle claim 1 , and M and N are positive integers; the memory device comprises a plurality of memory banks for storing the data rows; and the inter-row interleaving is configured to ensure that at least M*N valid data bits are always obtained through simultaneously accessing the memory banks.3. The decoding apparatus of claim 2 , wherein M=4 claim 2 , N=2 claim 2 , and a number of the memory banks is equal to 10.4. The decoding apparatus of claim 2 , wherein the M decoder cores access the memory device in a round-robin manner.5. The decoding apparatus of claim 4 , wherein each of the M decoder ...

Combined group ecc protection and subgroup parity protection

A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.

Rate Matching And Channel Interleaving For A Communications System

A method, an apparatus, and a computer program product for matching a rate of data bits to a desired rate by deletion of redundant data bits or repetition of data bits are disclosed. In a non-interleaved matrix of the data bits, a pattern of bits to be deleted or repeated to provide the desired data rate is determined. An address of each bit in the pattern in a manner inverse to the interleaving process is decoded to produce a respective address of the bit in the matrix. The respective bit in the interleaved data bits is deleted or repeated depending upon the respective address. The address decoding is performed in the same manner as a coding of addresses for producing the interleaved data bits from the non-interleaved matrix of the data bits.

METHOD AND APPARATUS FOR A PARAMETERIZED INTERLEAVER DESIGN PROCESS

A parameterized interleaver design process is provided, which optimizes the design for interleavers of any size, and can be completely specified using only a few design parameters. According to the parameterized interleaver design process an interleaver π(i) of a length N is generated. A number of subpermutation masks are defined, and a first intermediate interleaver permutation is partitioned into a number of subgroups, wherein the number of subgroups corresponds with the number of subpermutation masks. Each of the subgroups of the first intermediate interleaver permutation is partitioned into a number of further subgroups, and each of the subpermutation masks is applied to each of the further subgroups of a corresponding subgroup of the first intermediate interleaver permutation, resulting in a corresponding portion of a second intermediate interleaver permutation. The resulting interleaver π(i) is generated based at least in part on the first and second intermediate interleaver permutations. 118-. (canceled) This application claims priority under 35 U.S.C. §119 based on U.S. Provisional Application Ser. No. 61/382,125, filed Sep. 13, 2010, the disclosure of which is incorporated herein by reference in its entirety.The present invention relates to error correction in coding schemes for digital communication systems, and more particularly to design optimization for Interleavers of any size, which can be completely specified using only a few design parameters (i.e. a parameterized interleaver).In communication systems, system performance is aided by error control codes. Nearly all communications systems rely on some form of error control for managing errors that may occur due to noise and other factors during transmission of information through a communication channel. These communications systems can include satellite systems, fiber-optic systems, cellular systems, and radio and television broadcasting systems. Efficient error control schemes implemented at the ...

Correction Data

A method for processing encoded data bits transmitted from a transmitter to a receiver over a lossy communication channel, the method comprising: receiving the encoded data bits over the communication channel, the encoded data bits including redundant data units; decoding the encoded data bits at an error correction decoder, wherein the recovery of lost data is implemented at the error correction decoder using at least one of the redundant data units; determining if at least one data bit is unable to be recovered due to the decoder finding a plurality of candidate bit values for the at least one data bit; receiving information relating to the transmitter; analyzing the plurality of candidate bit values to exclude at least one of the candidate bit values for the at least one data bit using information relating to the transmitter; and resolving the at least one data bit based on the analysis.

Method and apparatus for interleaving data in a mobile communication system

An interleaving method in a mobile communication system is provided. The interleaving method includes encoding a plurality of bits to output encoded bits in a sequence, interleaving the encoded bits based on a modulation order to generate interleaved encoded bits comprising consecutive bits having a size based on the modulation order, the consecutive bits corresponding to consecutive bits of the encoded bits, scrambling the interleaved encoded bits with a scrambling code to generate scrambled bits, and modulating the scrambled bits based on the modulation order to output at least one symbol.

Systems and Methods for Enhanced Bit Correlation Usage

The present invention is related to systems and methods for applying a data decode algorithm to different rotations or modifications of a decoder input as part of data processing.

TIME VARYING DATA PERMUTATION APPARATUS AND METHODS

Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations. 1. An apparatus for permuting data in a data stream , the apparatus comprising:a first permutation element to apply a time varying first permutation to a data stream to generate a first permuted data stream;a block interleaver operatively coupled to the first permutation element, to interleave the first permuted data stream to generate an interleaved data stream; anda second permutation element operatively coupled to the block interleaver, to apply a time varying second permutation to the interleaved data stream to generate a second permuted data stream.2. The apparatus of claim 1 , the first permutation element comprising a first plurality of serially coupled permutation stages claim 1 , and the second permutation element comprising a second plurality of serially coupled permutation stages.3. The apparatus of claim 2 , each of the first plurality of serially coupled permutation stages and the second plurality of serially coupled permutation stages comprising at least one controllable permutation stage claim 2 , each controllable permutation stage being controllable to select claim 2 , from a plurality of different permutation maps claim 2 , a respective permutation map to be applied by each of the at least one controllable permutation stage.4. The apparatus of claim 3 , further comprising:a controller operatively coupled to the at least one controllable permutation stage, to generate a time varying control signal for ...

Receiver

Provided is a BICM-ID technique which suppresses deterioration of decoding characteristics and reduces a calculation amount. A receiver includes a demodulator, a deinterleaver, a decoder, and an interleaver. The demodulator outputs first extrinsic information by using a received signal encoded and interleaved and a priori information. The deinterleaver performs deinterleave processing on the first extrinsic information and outputs second extrinsic information. The decoder outputs third extrinsic information by using the second extrinsic information. The interleaver performs interleave processing on the third extrinsic information and outputs fourth extrinsic information. In the receiver that performs iterative decoding processing by using the fourth extrinsic information as the a priori information, the demodulator includes a generator, a received signal point candidate narrowing-down unit, and a likelihood calculation unit. The generator generates a plurality of received signal point candidates. The received signal point candidate narrowing-down unit narrows received signal point candidates down to those to be used to create the first extrinsic information based on a magnitude of the a priori information and a distance between the plurality of the received signal point candidates and the received signal. The likelihood calculation unit creates the first extrinsic information based on the narrowed-down received signal point candidates, the a priori information, and the received signal. 1. A receiver , comprising:a demodulator configured to receive a signal encoded and interleaved on a transmission side, create first extrinsic information by using the received signal and a priori information, and output the first extrinsic information;a deinterleaver configured to perform deinterleave processing inverse to the interleave processing on the first extrinsic information and output second extrinsic information;a decoder configured to create third extrinsic information by ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A BICM device , comprising:an error-correction coder configured to output a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15;a bit interleaver configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; anda modulator configured to perform 64-symbol mapping after generating the interleaved codeword, {'br': None, 'i': Y', '=X', 'j≦N, 'sub': j', 'π(j)', 'group, '0≦'}, 'wherein the interleaving is performed using the following equation using permutation order{'sub': j', 'j, 'where Xis the j-th bit group, Yis an interleaved j-th bit group, and π(j) is a permutation order for bit group-based interleaving.'}2. The BICM device of claim 1 , wherein the permutation order corresponds to an interleaving sequence represented by the following{'br': None, 'interleaving sequence={74 72 104 62 122 35 130 0 95 150 139 151 133 109 31 59 18 148 9 105 57 132 102 100 115 101 7 21 141 30 8 1 93 92 163 108 52 159 24 89 117 88 178 113 98 179 144 156 54 164 12 63 39 22 25 137 13 41 44 80 87 111 145 23 85 166 83 55 154 20 84 58 26 126 170 103 11 33 172 155 116 169 142 70 161 47 3 162 77 19 28 97 124 6 168 107 60 76 143 121 42 157 65 43 173 56 171 90 131 119 94 5 68 138 149 73 67 53 61 4 86 99 75 36 15 48 177 167 174 51 176 81 120 158 123 34 49 ...

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The method as claimed in claim 1 , wherein the interleaving comprises:splitting the codeword into a plurality of bit groups; andinterleaving the plurality of bit group.3. The method as claimed in claim 1 , wherein the mapping comprises:demultiplexing the bits of the interleaved codeword into parallel streams to generate cells; andmapping the cells onto the constellation points. This application is a Continuation of application Ser. No. 14/716,222 filed May 19, 2015, the disclosure of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) mapper. The role of the QAM mapper is to map different bits output from the channel encoder and interleaved using the Bit Interleaver to QAM cells. Each cell represents a complex number having real and imaginary part. The QAM mapper groups M bits into one cell. Each cell is ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 3/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation. 1. A bit-interleaved coded modulation (BICM) reception method , comprising:performing demodulation corresponding to quadrature phase shift keying (QPSK);performing group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; andrestoring information bits by low-density parity check (LDPC) decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 16200 and a code rate of 3/15,wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception method of claim 1 , wherein the group-unit deinterleaving corresponds to a reverse process of interleaving performed by using a permutation order claim 1 , andthe permutation order corresponds to an interleaving sequence represented by the following interleaving sequence:{15 22 34 19 7 17 28 43 30 32 14 1 11 0 3 9 10 38 24 4 23 18 27 39 29 33 8 2 40 21 20 36 44 12 37 13 35 6 31 26 16 25 42 5 41}.3. The BICM reception method of claim 2 , wherein the parallel factor is 360 claim 2 , and the group includes 360 values.5. An apparatus for transmitting a broadcast signal claim 2 , comprising:a low-density parity check (LDPC) encoder configured to encode a low-density parity check (LDPC ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 5/15 AND 4096-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping. 1. A bit-interleaved coded modulation (BICM) reception device , comprising:a demodulator configured to perform demodulation corresponding to 4096-symbol mapping;a bit deinterleaver configured to perform group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; anda decoder configured to restore information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 64800 and a code rate of 5/15,wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception device of claim 1 , wherein the group-unit deinterleaving corresponds to a reverse process of interleaving performed by using permutation order claim 1 , and {'br': None, 'interleaving sequence={146 89 57 16 164 138 91 78 90 66 122 12 9 157 14 68 112 128 74 45 28 87 158 56 61 168 18 161 95 99 139 22 65 130 166 118 150 49 142 44 36 1 121 6 46 29 88 47 0 58 105 43 80 64 107 21 55 151 8 145 163 7 98 123 17 11 153 136 52 3 13 34 160 102 125 114 152 84 32 97 33 60 62 79 37 129 38 165 71 75 59 144 127 132 104 53 162 103 120 54 155 116 48 77 76 73 113 119 179 177 41 19 92 109 31 143 178 108 39 140 106 40 5 25 81 176 101 124 126 72 111 4 173 156 134 86 174 2 170 35 175 137 15 24 69 ...

PACKET RETRANSMISSION

Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like. 1105.-. (canceled)106. A method of packet retransmission comprising:transmitting or receiving, using a transceiver, a plurality of packets,wherein at least one first packet of the plurality of packets is associated with a first delay requirement,wherein at least one second packet of the plurality of packets is associated with a second delay requirement, andwherein the second delay requirement is lower than the first delay requirement; andtransmitting or receiving, using the transceiver, a message comprising acknowledgement (ACK) information of the at least one first packet,wherein the ACK information is transmitted or received a plurality of times such that the ACK information is transmitted or received in a first DMT symbol and the ACK information is also transmitted or received in a second DMT symbol.107. The method of claim 106 , further comprising passing the at least one second packet when it is received without error to a higher layer without waiting for receipt of other retransmitted packets.108. The method of claim 106 , further comprising passing the at least one first packet when it is received without error to a higher layer without waiting for receipt of other retransmitted packets.109. The method of claim 106 , further comprising waiting for the receipt of other retransmitted packets before passing the at least one first packet a higher layer when they are ...

DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD

A data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 24/30, 25/30, 26/30, 27/30, 28/30, or 29/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The present technology apparatus and method may be applied to LDPC encoding and LDPC decoding. 1an encoding unit configured to encode information bits into an LDPC (Low Density Parity Check) code having a code length of 64800 bits and a code rate of 24/30 on the basis of a parity check matrix of the LDPC code, whereinthe LDPC code includes information bits and parity bits,the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,the information matrix portion is represented by a parity check matrix initial value table, andthe parity check matrix initial value table is a table showing positions of elements of 1 in the information matrix portion in units of 360 columns, including{'b': 1504', '2103', '2621', '2840', '3869', '4594', '5246', '6314', '7327', '7364', '10425', '11934', '12898', '12954}{'b': 27', '1903', '3923', '4513', '7812', '8098', '8428', '9789', '10519', '11345', '12032', '12157', '12573', '12930}{'b': 17', '191', '660', '2451', '2475', '2976', '3398', '3616', '5769', '6724', '8641', '10046', '11552', '12842}{'b': 13', '1366', '4993', '6468', '7689', '8563', '9131', '10012', '10914', '11574', '11837', ' ...

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The receiving apparatus of claim 1 , wherein each of the plurality of groups comprises 360 values.3. The receiving apparatus of claim 1 , wherein π(j) is determined based on at least one of the code length claim 1 , a modulation method and the code rate. This is a continuation of U.S. patent application Ser. No. 15/435,042, filed Feb. 16, 2017, which is a continuation of U.S. patent application Ser. No. 15/130,204, filed on Apr. 15, 2016, issued as U.S. Pat. No. 9,692,454 on Jun. 27, 2017, which is a continuation of U.S. patent application Ser. No. 14/625,862, filed Feb. 19, 2015, issued as U.S. Pat. No. 9,602,137 on Mar. 21, 2017, which claims priority from U.S. Provisional Application No. 61/941,676 filed on Feb. 19, 2014, U.S. Provisional Application No. 62/001,170 filed on May 21, 2014, and Korean Patent Application No. 10-2015-0000671 filed on Jan. 5, 2015. The entire disclosures of the prior applications are considered part of the disclosure of this continuation application, and are hereby incorporated by reference.Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus and an interleaving method thereof, and more particularly, to a transmitting apparatus which processes data and transmits the data, and an interleaving method thereof.In the 21st century information-oriented society, broadcasting communication services are moving into the era of digitalization, ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 2/15 AND 16-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping. 1. A BICM reception device , comprising:a demodulator configured to perform demodulation corresponding to 16-symbol mapping;a bit deinterleaver configured to perform group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; anda decoder configured to restore information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 16200 and a code rate of 2/15,wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception device of claim 1 , wherein the group-unit deinterleaving corresponds to interleaving performed by using permutation order claim 1 , and {'br': None, 'interleaving sequence={5 33 18 8 29 10 21 14 30 26 11 23 27 4 7 6 24 44 38 31 34 43 13 0 15 42 17 2 20 12 40 39 35 32 1 3 41 37 9 25 19 22 16 28 36}.'}, 'the permutation order corresponds to an interleaving sequence represented by the following'}3. The BICM reception device of claim 2 , wherein the 16-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 16 constellations.4. The BICM reception device of claim 2 , wherein the parallel factor is 360 claim 2 , and the group includes 360 values.5. The BICM reception device of claim 4 ...

INTERLEAVING AND MAPPING METHOD AND DEINTERLEAVING AND DEMAPPING METHOD FOR LDPC CODEWORD

An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a parity bits part of the LDPC codeword to obtain interleaved parity bits; splicing an information bit part of the codeword and the interleaved parity bits into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving. 1. A transmitter , comprising:an interleaver performing a first bit interleaving on parity bits in an LDPC codeword to obtain interleaved parity bits, wherein the parity bits contain a first parity bits part and a second parity bits part, and the first bit interleaving is performed on the first parity bits part and the second parity bits part respectively;the interleaver splicing the information bits part in the LDPC codeword and the interleaved parity bits into an LDPC codeword having undergone the first bit interleaving;the interleaver dividing the LDPC codeword having undergone the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding bit interleaving pattern to form an LDPC codeword having undergone second bit interleaving; andthe interleaver dividing the LDPC codeword having undergone the second bit interleaving into two parts, writing the first part into a storage space in order and reading the first part ...

INTERLEAVING AND MAPPING METHOD AND DEINTERLEAVING AND DEMAPPING METHOD FOR LDPC CODEWORD

An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a parity bits part of the LDPC codeword to obtain interleaved parity bits; splicing an information bit part of the codeword and the interleaved parity bits into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving. 1. A transmitter , comprising:a constellation mapper performing, according to a corresponding constellation diagram, constellation mapping on an LDPC codeword which is bit interleaved according to a bit interleaving pattern,wherein for LDPC codewords with different code lengths, code rates and LDPC code matrices tables, such that the capacity of bit interleaved coding and modulation is maximized, matched constellation diagrams and bit interleaving patterns are designed by means of theoretical analysis and optimization.2. The transmitter of claim 1 , whereinthe constellation diagram is distributed non-uniformly in a two-dimensional manner in a single quadrant, and distributed symmetrically in four quadrants.4. The transmitter of claim 3 , whereinthe constellation diagram is applicable to 16-QAM non-uniform constellation mapping,the constellation diagram is applicable to an LDPC codeword with a code length of 16200 bits or 64800 bits, andthe constellation diagram is applicable to an LDPC codeword with a code rate of 4/15 ...

TECHNIQUES FOR EMPLOYING POLAR CODE IN CONNECTION WITH NR (NEW RADIO)

Techniques discussed herein can facilitate polar coding and decoding for NR (New Radio) systems. Various embodiments discussed herein can employ polar coding and/or decoding at UE(s) (User Equipment(s)) and/or gNB(s) (next generation Node B(s)). One example embodiment employable at a UE can comprise processing circuitry configured to determine one or more thresholds for code block segmentation, wherein the one or more thresholds for code block segmentation comprise one or more of a payload threshold (Kseg) or a code rate threshold (Rseg); determine to perform code block segmentation based on the one or more thresholds and at least one of a current payload (K) of an information block or a current code rate (R) for the information block; segment the information block into a plurality of segments; and encode each segment of the plurality of segments via a polar encoder with a code size (N). 128-. (canceled)29. An apparatus configured to be employed in a UE (User Equipment) , comprising:a memory interface; and [{'sub': seg', 'seg, 'determine one or more thresholds for code block segmentation, wherein the one or more thresholds for code block segmentation comprise one or more of a payload threshold (K) or a code rate threshold (R);'}, 'determine to perform code block segmentation based on the one or more thresholds and at least one of a current payload (K) of an information block or a current code rate (R) for the information block;', 'segment the information block into a plurality of segments;', 'encode each segment of the plurality of segments via a polar encoder with a code size (N); and', 'send the one or more thresholds for code block segmentation to a memory via the memory interface., 'processing circuitry configured to30. The apparatus of claim 29 , wherein the code size (N) is one of 64 claim 29 , 128 claim 29 , 256 claim 29 , 512 claim 29 , or 1024.31. The apparatus of claim 29 , wherein the processing circuitry is further configured to generate an associated ...

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 or 12/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code. This is a continuation of U.S. application Ser. No. 14/905,213, filed Jan. 14, 2016, which is a U.S. National Stage Application of International Application No. PCT/JP2015/063250, filed May 8, 2015, which is based on and claims priority to Japanese Application No. 2014-104806, filed May 21, 2014, the entire contents of each of which are incorporated herein by reference.The present technology relates to a data processing device and a data processing method, and more particularly, a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code, for example.Some of the information disclosed in this specification and the drawings was provided by Samsung Electronics Co., Ltd. (hereinafter referred to as Samsung), LG Electronics Inc., NERC, and CRC/ETRI (indicated in the drawings).A low density parity check (LDPC) code has a high error correction capability, and in recent years, the LDPC code has widely been employed in transmission schemes of digital broadcasting such as Digital Video Broadcasting (DVB)-S.2, DVB-T.2, and DVB-C.2 of Europe and the like, or Advanced Television Systems Committee (ATSC) 3.0 of the USA and the like (for example, see Non-Patent Literature 1).From a recent study, it is known that performance near a Shannon limit is obtained from the LDPC code when ...

Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 2/15 and 256-symbol mapping, and bit interleaving method using same

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The apparatus of claim 1 , wherein each of the plurality of groups comprises 360 values.3. The apparatus of claim 1 , wherein the π(j) is determined based on at least one of the code length claim 1 , a modulation method for the mapping and the code rate.5. The method of claim 4 , wherein each of the plurality of groups comprises 360 values.6. The method of claim 4 , wherein the π(j) is determined based on at least one of the code length claim 4 , a modulation method for the mapping and the code rate. This is a continuation of U.S. application Ser. No. 15/639,614 filed Jun. 30, 2017, which is a continuation application of U.S. patent application Ser. No. 14/715,795 filed May 19, 2015, the disclosure of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments relate to a transmitting apparatus and an interleaving method thereof, and more particularly, to a transmitting apparatus which processes and transmits data, and an interleaving method thereof.In the 21st century information-oriented society, broadcasting communication services are moving into the era of digitalization, multi-channel, wideband, and high quality. In particular, as high quality digital televisions, portable multimedia players and portable broadcasting equipment are increasingly used in recent years, there is an increasing demand for methods for supporting various receiving methods ...

TRANSMITTING APPARATUS AND NON-UNIFORM CONSTELLATION MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The apparatus as claimed in claim 1 , wherein the constellation points as defined in the list comprises constellation points in one quadrant claim 1 , andwherein constellation points in remaining quadrants are obtained by indicating each constellation point a which is defined in the list as a*, −a*, and −a, respectively, * indicating complex conjugation. This is a continuation of U.S. application Ser. No. 15/726,806 filed Oct. 6, 2017, which is a continuation of U.S. application Ser. No. 14/715,817 filed on May 19, 2015, now U.S. Pat. No. 9,847,851, the disclosures of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) mapper. The role of the QAM mapper is to map different bits output from the channel encoder and interleaved using the Bit Interleaver to QAM cells. Each cell represents a complex number having real ...

Transmitting device and transmitting method

A loss correction encoding device having an improved capability of loss correction using LDPC-CC includes a rearranging unit that rearranges information data contained in n information packets according to the constraint length Kmax and the encoding rate (q−1)/q of a check polynomial of the loss correction code used in a loss correction encoding unit. Specifically, the rearranging unit rearranges the information data in such a way that continuous Kmax×(q−1) pieces of information data after rearrangement are contained in different information packets. The rearranging unit distributes the information data to information blocks from n information packets, where n satisfies the formula Kmax×(q−1)≤n.

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

The present invention provides a method of transmitting broadcast signals. The method includes, formatting input streams into Data Pipe (DP) data, Low-Density Parity-Check (LDPC) encoding the DP data according to a code rate, bit interleaving the LDPC encoded DP data, mapping the hit interleaved DP data onto constellations, building at least one signal frame including the mapped DP data, and modulating data in the built signal frame by an Orthogonal Frequency Division Multiplexing (OFDM) method and transmitting the broadcast signals having the modulated data, wherein the input streams include Audio/Video (A/V) data and service guide data, and wherein the Audio/Video (A/V) data and service guide data are included in first ISO base media file format (ISOBMFF) files. 114-. (canceled)15. A method of receiving broadcast signals , the method including:receiving the broadcast signals,wherein the broadcast signals are generated by encapsulating and compressing data into link layer packets, Low-Density Parity-Check (LDPC) encoding the data according to a code rate, bit interleaving the LDPC encoded data, mapping the bit interleaved data, building at least one signal frame including the mapped data, and modulating data in the built at least one signal frame by an Orthogonal Frequency Division Multiplexing (OFDM) method; anddecoding the received broadcast signals;wherein a link layer packet includes a link layer packet header and a payload containing an input packet,wherein a packet type of the input packet corresponds to IP(Internet Protocol) packet, or MPEG-2 TS packet,wherein the input packet is segmented and contained as a part of the input packet in the payload, or the input packet is concatenated with another input packet and contained in the payload,wherein the link layer packet header has an information field that indicates whether a segmentation or a concatenation is performed,wherein when the packet type of the input packet corresponds to the IP packet, a header of ...

System and Method for Auto-Detection of WLAN Packets using STF

A method of auto-detection of WLAN packets includes selecting a first Golay sequence from a first pair of Golay complementary sequences associated with first packet type, each Golay sequence of the first pair of Golay complementary sequences being zero correlation zone (ZCZ) sequences with each Golay sequence of a second pair of Golay complementary sequences associated with a second packet type, and transmitting a wireless packet carrying a short training field (STF) that includes one or more instances of the first Golay sequence. 1. A method comprising:receiving a wireless packet comprising a short training field (STF);determining cross-correlations between the STF and a first preamble component sequence from a first set of preamble component sequences associated with a first packet type and between the STF and a second preamble component sequence from a second set of preamble component sequences associated with a second packet type, the first preamble component sequence and the second preamble component sequence having a zero correlation zone (ZCZ) property; anddetermining that the wireless packet is the second packet type when there is a greater correlation between the STF and the second preamble component sequence than between the STF and the first preamble component sequence.2. The method of claim 1 , wherein the first packet type is an Institute of Electrical and Electronics Engineers (IEEE) 802.11ad packet type claim 1 , and the second packet type is an IEEE 802.11ay packet type.3. The method of claim 1 , wherein the ZCZ property is a ZCZ of at least 64 symbol time slots in width.4. The method of claim 1 , wherein the first set of preamble component sequences comprise preamble component sequences Gaand Gb.5. The method of claim 1 , wherein the second set of preamble component sequences comprise preamble component sequences Gaand Gb.6. The method of claim 1 , wherein the second set of preamble component sequences comprise mutual ZCZ sequences.7. The method of ...

APPARATUS AND METHOD FOR SENDING/RECEIVING PACKET IN MULTIMEDIA COMMUNICATION SYSTEM

A method for sending forward error correction (FEC) configuration information by a sending apparatus in a multimedia system is provided. The method includes sending source FEC configuration information for an FEC source packet to a receiving apparatus, wherein the source FEC configuration information includes information related to an FEC source or repair packet that is sent first among at least one FEC source or repair packet if an FEC source or repair packet block includes the at least one FEC source or repair packet. 1. A sending apparatus in a broadcasting system , the sending apparatus comprising:a transmitter; and identify forward error correction (FEC) configuration information,', 'generate an FEC packet including a header, a payload and the FEC configuration information, and', 'send the FEC packet,, 'a controller coupled with the transmitter and configured to control towherein the header includes time stamp (TS) information indicating a TS of the FEC packet,wherein the FEC configuration information includes information related to a first FEC packet that is sent first among one or more FEC packets included in an FEC packet block, andwherein the information related to the first FEC packet includes a value for remaining bits, which exclude a most significant bit (MSB) 1 bit of a TS included in a header of the first FEC packet.2. The sending apparatus of claim 1 , wherein the FEC configuration information follows the payload.3. The sending apparatus of claim 1 , wherein the sending apparatus supports a one-stage FEC coding structure.4. The sending apparatus of claim 1 , wherein the sending apparatus supports a layer aware-forward error correction (LA-FEC) coding structure.5. The sending apparatus of claim 4 , wherein claim 4 , in case that the sending apparatus supports a two-stage FEC coding structure claim 4 , the FEC configuration information includes a TS indicator indicating that the information related to the first FEC packet is for the FEC packet block of ...

Enabling efficient recovery from multiple failures together with one latent error in a storage array

The present invention provides a method and apparatus of managing a storage array. The method comprises: striping the storage array to form a plurality of stripes; selecting F storage chunks from each stripe as local parity chunks, and selecting another L storage chunks from the storage array as global parity chunks; performing (F+L) fault tolerant erasure coding on all data chunks in a stripe to generate (F+L) groups of parity data, and storing F groups of parity data therein into the F local parity chunks; performing cross-stripe operation on another L groups of parity data to generate L groups of global parity data, and storing them into the L global parity chunks, respectively. The apparatus corresponds to the method. With the invention, a plurality of errors in the storage array can be detected and/or recovered to improve fault tolerance and space utilization of the storage array.

SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEVICES VIA A MAIN MEMORY SYSTEM

A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit. 1. (canceled)2. A memory module comprising:one or more memory devices; and a first interface to couple to a host system;', 'a second interface coupled to the one or more memory devices; and', receive a command from the host system;', 'store the command received from the host system in the command buffer;', 'determine whether the command is complete;', 'generate direct memory access (DMA) descriptors in response to the command being complete; and', 'communicate the DMA descriptors on the second interface., 'control circuitry comprising a command buffer, wherein the control circuitry is coupled to the first interface and the second interface, wherein the control circuitry is to], 'a device coupled to the one or more memory devices, the device comprising3. The memory module of claim 2 , wherein the control circuitry comprises:a command processor configured to generate the DMA descriptors; anda buffer check logic configured to determine whether the command is complete.4. The memory module of claim 3 , wherein the buffer check logic is configured to read one or more bits from each portion of a plurality of portions of the command and to determine that the one or more bits read from each portion together match a predetermined pattern.5. The memory module of claim 3 , wherein the buffer check logic is configured to read a first bit and a second bit from each portion of a plurality of portions of the command and to determine that the first bit read from each portion is a non-zero value and the second bit read from each portion is a zero value.6. The memory module ...

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM). 2. The LDPC encoding method of claim 1 , wherein the LDPC codeword comprises a systematic part corresponding to the information bits and having a length of 3240 claim 1 , a first parity part corresponding to a dual diagonal matrix included in the PCM and having a length of 1080 claim 1 , and a second parity part corresponding to an identity matrix included in the PCM and having a length of 11880.3. The LDPC encoding method of claim 2 , wherein the sequence has a number of rows equal to a sum of a value obtained by dividing a length of the systematic part claim 2 , that is claim 2 , 3240 claim 2 , by a circulant permutation matrix (CPM) size corresponding to the PCM claim 2 , that is claim 2 , 360 claim 2 , and a value obtained by dividing a length of the first parity part claim 2 , that is claim 2 , 1080 claim 2 , by the CPM size.4. The LDPC encoding method of claim 3 , wherein the accumulation is performed at parity bit addresses that are updated using the sequence.5. The LDPC encoding method of claim 4 , wherein the accumulation is performed while the rows of the sequence are being repeatedly changed by the CPM size of the PCM. This application is a continuation of and claims priority of U.S. application Ser. No. 14/496,356 filed Sep. 25, 2014, which claims the benefit of Korean Patent Application Nos. 10-2014-0106174 and 10-2014-0120009, filed Aug. 14, 2014 and Sep. 11, 2014, respectively, which are hereby incorporated by reference herein in their entirety.1. ...

TIME AND CELL DE-INTERLEAVING CIRCUIT AND METHOD FOR PERFORMING TIME AND CELL DE-INTERLEAVING

A method for performing time and cell de-interleaving on an interleaved signal including a plurality of cells is provided. The method includes: providing a first memory for storing the cells, the first memory written and read each time in a unit of one cell group, the cell group including K cells, where K is a positive integer greater than 1; providing a second memory for storing the cells read from the first memory; reading the cells from the first memory, and writing the cells to the second memory according to a writing rule of a plurality of permutation rules, K consecutive cells written to the second memory being from the same cell group; and reading the cells from the second memory according to a reading rule of the permutation rules, to cause the cells read from the second memory to be complete with time de-interleaving and cell de-interleaving. 1. A time and cell de-interleaving circuit , located at a signal receiver of a communications system , performing time de-interleaving and cell de-interleaving on an interleaved signal , the interleaved signal comprising a plurality of cells , the time and cell de-interleaving circuit comprising:a first memory, storing the cells;a storage control circuit, controlling an access operation of the first memory, the access operation performed in a unit of one cell group, the cell group comprising K units, where K is a positive integer greater than 1;a second memory, storing the cells read from the first memory; anda rule generating unit, generating a plurality of permutation rules, writing the cells read from the first memory to the second memory according to a writing rule of the permutation rules, and reading the cells from the second memory according to a reading rule of the permutation rules, such that the cells read from the second memory are complete with cell de-interleaving and time de-interleaving.2. The time and cell de-interleaving circuit according to claim 1 , wherein the interleaved signal comprises a ...

POLAR CODE RATE MATCHING METHOD AND POLAR CODE RATE MATCHING APPARATUS

Embodiments of the present invention provide a polar code rate matching method and a polar code rate matching apparatus. The method includes: performing matrix-based BRO interleaving on a non-systematic polar code output by a polar code encoder, to obtain interleaved bits; and determining, based on the interleaved bits, a rate-matched output sequence. According to the embodiments of the present invention, matrix-based BRO interleaving is performed on a non-systematic polar code, to obtain a rate-matched output sequence, so that a sequence structure after interleaving is more random, which can reduce an FER, thereby improving HARQ performance and ensuring reliability of data transmission. 1. A polar polar code rate matching method , comprising:performing matrix-based bit reversal order (BRO) interleaving on a non-systematic polar code output by a polar code encoder, to obtain interleaved bits; anddetermining, based on the interleaved bits, a rate-matched output sequence.2. The method according to claim 1 , wherein performing matrix-based BRO interleaving on the non-systematic polar code output by the polar code encoder claim 1 , to obtain interleaved bits comprises:{'b': 1', '2', '1', '2, 'writing bits of the non-systematic polar code by row to form a first matrix of M rows×M columns wherein M and M are positive integers;'}{'b': '2', 'performing a first substitution operation on a column of the first matrix to obtain a second matrix, wherein the first substitution operation is a BRO operation with a size of M;'}{'b': '1', 'performing a second substitution operation on a row of the second matrix to obtain a third matrix, wherein the second substitution operation is a BRO operation with a size of M; and'}reading bits according to a column of the third matrix, and using the bits as the interleaved bits.3. The method according to claim 1 , wherein performing matrix-based BRO interleaving on a polar code output by a polar code encoder claim 1 , to obtain interleaved bits ...

PARITY CHECK MATRIX GENERATING METHOD, ENCODING APPARATUS, ENCODING METHOD, DECODING APPARATUS AND DECODING METHOD USING THE SAME

A method of low density parity check (LDPC) encoding includes: receiving a plurality of information word bits; LDPC encoding the information word bits using a parity check matrix in which a sum of elements in same positions in a plurality of groups constituting the parity check matrix is less than 2; and generating LDPC codeword bits comprising the information word bits and parity bits as a result of the LDPC encoding, wherein each of the plurality of groups constituting comprises a same number of columns. 1. A method of low density parity check (LDPC) encoding , the method comprising:receiving a plurality of information word bits;LDPC encoding the information word bits using a parity check matrix in which a sum of elements in same positions in a plurality of groups constituting the parity check matrix is less than 2; andgenerating LDPC codeword bits comprising the information word bits and parity bits as a result of the LDPC encoding,wherein each of the plurality of groups constituting comprises a same number of columns.2. The method of claim 1 , wherein a number of the plurality of groups is an integer multiple of a number of bits constituting a modulation symbol to be generated from the LDPC codeword bits.3. The method of claim 2 , wherein bits among the LDPC codeword bits corresponding to different parity check equations constitute the modulation symbol claim 2 , andwherein each of the parity check equations is formed of bits corresponding to columns where 1 exists in a row in the parity check matrix.4. The method of claim 3 , wherein the bits constituting the modulation symbol are separated by a same predetermined interval in the LDPC codeword bits.5. The method of claim 1 , further comprising generating the parity check matrix by:performing row permutation and column permutation on a preset parity check matrix;dividing the parity check matrix, on which the row permutation and the column permutation are performed, into the plurality of groups according to a ...

DTV TRANSMITTING SYSTEM AND METHOD OF PROCESSING BROADCAST DATA

A DTV transmitting system includes an encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The encoder codes enhanced data for error correction, permutes the coded data, and further codes the permuted data for error detection. The randomizer randomizes the coded enhanced data, and the block processor codes the randomized data at an effective coding rate of 1/H. The group formatter forms a group of enhanced data having data regions, and inserts the coded enhanced data into at least one of the data regions. The deinterleaver deinterleaves the group of enhanced data, and the packet formatter formats the deinterleaved data into corresponding data bytes. 1. (canceled)2. A method of processing broadcast data in a broadcast transmitter , the method comprising:receiving enhanced data and adding padding data to the enhanced data;randomizing the enhanced data to which the padding data are added;encoding the randomized enhanced data;first interleaving the encoded enhanced data;second interleaving the first interleaved enhanced data;encoding signaling data for signaling the enhanced data;first interleaving the encoded signaling data;second interleaving the first interleaved signaling data; andtransmitting the second interleaved enhanced data and the second interleaved signaling data through a frame,wherein the frame further includes known data, wherein the known data include a first pattern of known data and a second pattern of known data other than the first pattern of known data, and wherein at least one of the first pattern of known data and the second pattern of known data are used for channel estimation in a broadcast receiver.3. The method of claim 2 , wherein first interleaving the encoded enhanced data performs block interleaving on the encoded enhanced data.4. The method of claim 2 , wherein second interleaving the first interleaved enhanced data performs convolutional interleaving on the first interleaved enhanced data. ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 4/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A bit interleaving method , comprising:storing a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15;generating an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; andoutputting the interleaved codeword, {'br': None, 'i': Y', '=X', 'j≦N, 'sub': j', 'π(j)', 'group, '0≦'}, 'wherein the interleaving is performed using the following equation using permutation order{'sub': π(j)', 'j, 'where λis a π(j)th bit group, Yis an interleaved j-th bit group, and π(j) is a permutation order for bit group-based interleaving.'}2. The bit interleaving method of claim 1 , wherein the permutation order corresponds to an interleaving sequence represented by the following{'br': None, 'interleaving sequence={41 34 32 37 5 8 13 15 30 31 22 25 42 20 23 17 1 40 44 12 6 43 7 29 33 16 11 0 35 4 14 28 21 3 24 19 18 36 10 38 26 2 39 27 9},'}wherein the interleaving sequence is for a case where 64-symbol mapping is employed.3. The bit interleaving method of claim 2 , wherein the 64-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 64 constellations.4. The bit interleaving method of claim 3 , wherein the parallel factor is 360 claim 3 , and the bit group includes 360 bits. This application is a continuation of U.S. application Ser. ...

PARALLEL BIT INTERLEAVER

A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section. 1. A transmitting method for transmitting a codeword generated based on a quasi-cyclic low-density parity check coding scheme , the transmitting method comprising:a cyclic block permutation step of applying a cyclic block permutation process to a codeword made up of N cyclic blocks each consisting of Q bits, to reorder the cyclic blocks in accordance with a cyclic block permutation rule defining a reordering of the cyclic blocks;a bit permutation step of applying a bit permutation process to the codeword after the cyclic block permutation process, to reorder the bits of the codeword in accordance with a bit permutation rule defining a reordering of the bits;a dividing step of dividing the codeword after the bit permutation process into a plurality of constellation words, each of the constellation words being made up of M bits,a modulating step of mapping each constellation word to a modulated signal, anda transmitting step of transmitting a transmitting signal generated from the constellation words, whereinN is a multiple of M,the bit permutation rule defines the reordering of the bits of the codeword after the cyclic block permutation process, the reordering of the bit permutation rule being equivalent to a column-row permutation process including a writing process and a reading process, the bits of the N cyclic blocks being written into a matrix row-by-row during the writing process, the written bits being ...

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals comprises an encoder for encoding service data, a mapper for mapping the encoded service data into a plurality of OFDM (Orthogonal Frequency Division Multiplex) symbols to build at least one signal frame, a frequency interleaver for frequency interleaving data in the at least one signal frame by using a different interleaving-seed which is used for every OFDM symbol pair comprised of two sequential OFDM symbols, a modulator for modulating the frequency interleaved data by an OFDM scheme and a transmitter for transmitting the broadcast signals having the modulated data, wherein the different interleaving-seed is generated based on a cyclic shifting value and wherein an interleaving seed is variable based on an FFT size of the modulating. 120-. (canceled)21. A method comprising:at an electronic device with one or more processors for processing broadcast signals:encoding data for one or more services of the broadcast signals;building a signal frame carrying the encoded data; generating a main sequence, a same main sequence being used for two consecutive symbols to be processed by an OFDM (Orthogonal Frequency Division Multiplexing) scheme;', 'generating a symbol offset, a value of the symbol offset being constant for the two consecutive symbols;', 'generating a sequence based on the main sequence and the symbol offset; and', 'checking a validity of address of the generated sequence to output the interleaving sequence that corresponds to one or more valid addresses;, 'frequency interleaving data in the signal frame by a interleaving sequence that applies to a symbol in the data signal, wherein the interleaving sequence is generated bymodulating frequency interleaved data by the OFDM scheme; andtransmitting broadcast signals carrying modulated data.22. The method of claim 21 , wherein when the frequency interleaving applies to a signal ...

INTERLEAVING AND MAPPING METHOD AND DEINTERLEAVING AND DEMAPPING METHOD FOR LDPC CODEWORD

An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a parity bits part of the LDPC codeword to obtain interleaved parity bits; splicing an information bit part of the codeword and the interleaved parity bits into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving. 1. A transmitter , comprising:an encoder configured to encode, based on a low-density parity-check (LDPC) code with a code rate of 4/15 and a code length of 64,800 bits, input information bits to generate an LDPC codeword, wherein the LDPC codeword comprises an information bit part and a check bit part;an interleaver dividing the LDPC codeword into multiple bit subblocks, and changing an order of the bit subblocks according to a permutation order, so as to provide a bit-interleaved LDPC codeword; anda modulator mapping bits of the bit-interleaved LDPC codeword onto constellation points for irregular 16-quadrature amplitude modulation (QAM);the permutation order is defined as follows:165 8 136 2 58 30 127 64 38 164 123 45 78 17 47 105 159 134 124 147 148 109 67 98 157 57 156 170 46 12 172 29 9 3 144 97 83 151 26 52 10 39 50 104 92 163 72 125 36 14 55 48 1 149 33 110 6 130 140 89 77 22 171 139 112 113 152 16 7 85 11 28 153 73 62 44 135 116 4 61 117 53 111 178 94 81 68 114 173 75 101 88 65 99 126 141 43 15 18 90 35 24 142 ...

Protection Against Side-Channel Attacks

A method is proposed for copying a source array into a target array, wherein both the source array and the target array have at least two elements, wherein each element has a value, in which the elements of the source array are copied into the target array in the sequence of a random permutation, wherein, after a step of copying an element of the source array into the target array, the source array, the target array or the source array and the target array are rotated. A device is also indicated accordingly. 1. A method for copying a source array into a target array , wherein both the source array and the target array have at least two elements , wherein each element has a value , the method comprising:copying the elements of the source array into the target array in the sequence of a permutation, andafter copying an element of the source array into the target array, the source array, the target array or the source array and the target array are permutated.2. The method of claim 1 , in which at least one cyclic shift register is provided for the source array and the target array to store the at least two elements.3. The method of claim 1 , in which a loop is provided which predefines a number of iterations which corresponds to the number of the at least two elements claim 1 , wherein claim 1 , for each iteration claim 1 ,the value is copied from the source array into the target array according to the sequence of the random permutation,the source array and the target array are rotated through a predefined position.4. The method of claim 1 , in which a loop is provided which predefines a number of iterations which corresponds to the number of the at least two elements claim 1 , wherein claim 1 , for each iteration claim 1 ,the value is copied from the source array into the target array according to the sequence of the permutation,the source array is rotated through a first number of positions, wherein the first number is defined by a first digit,the target array is ...

Polar Code Interleaving and Bit Selection

Apparatus and methods are provided for polar code sub-block interleaving and bit selection. In one novel aspect, middle-part interlaced sub-block interleaving is provided for polar code interleaving. In one embodiment, the middle part of the polar code is interlaced and generates the interleaved polar code. In another embodiment, the lower part and the upper part are also sub-block interleaved with the middle-part interlaced method. In another novel, rate-dependent unified bit selection is provided. The bit selection is categorized into three operation categories of repetition, puncturing and the shortening. Each category follows unified bit selection rule with different categories differ only in the access scheme. In one embodiment, the circular buffer is used for bit selection. 1. A method comprising:dividing in sequence a polar code into a lower part, a middle part, and an upper part by a base station, wherein the system polar code has a polar code length N;performing a rate-independent interlaced interleaving for the middle part of the polar code to obtain an interleaved bit sequence; andtransmitting a transmission bit sequence, wherein the transmission bit sequence is generated by a rate-dependent bit selection from the interleaved bit sequence based on an output length E to obtain a transmission bit sequence.2. The method of claim 1 , the bit selection is categorized to bit-selection operations comprising: a repetition operation with E greater than or equal to N claim 1 , a puncturing operation with E smaller than N and a targeted code rate smaller than or equal to a predefined threshold T claim 1 , and a shortening operation with E smaller than N and a targeted code rate greater than T.3. The method of claim 2 , wherein the bit selection operation is the repetition operation claim 2 , and wherein the transmission bit sequence from index 0 to E is selected starting from a lowest index of the interleaved bit sequence and repeated from the lowest index of the ...

COMMUNICATION METHOD AND SYSTEM WITH ON DEMAND TEMPORAL DIVERSITY

The disclosure may provide for a communication method and system. A transmitter of the communication system may include an interleaver and a first encoder for determining parity bits. The transmitter also may include a multiplexer for joining the parity bits with the data. A second encoder may be positioned after the multiplexer for implementing an error correcting code. A receiver of the communication system may include a decoder followed by an interleaver. When errors are detected in received data at the decoder, one or more processors of the receiver may be configured to correct portions of the received data and combine the corrected portions with the received data. 1. A method comprising:receiving, by one or more second processors of a communication device, an input signal;decoding, by the one or more second processors, the input signal to obtain second data;identifying, by the one or more second processors, one or more errors in the input signal and locations of the one or more errors;producing, by the one or more second processors, one or more erasures in the data at the locations of the one or more errors;de-interleaving, by the one or more second processors, the data in the input signal;correcting, by the one or more second processors, the one or more erasures to obtain corrected data; andcombining, by the one or more second processors, the corrected data and the data to form complete corrected data.2. The method of claim 1 , wherein the input signal is an error-corrected claim 1 , multiplexed signal.3. The method of claim 2 , wherein the multiplexed signal includes parity bits multiplexed with second data.4. The method of claim 1 , wherein the corrected data and the data are combined by:receiving an index indicating a location of the one or more erasures; andreplacing portions of the data with portions of the corrected data according to the index.5. The method of claim 1 , wherein correcting the data includes reordering the de-interleaved data.6. The method ...

CHANNEL EQUALIZER AND METHOD OF PROCESSING BROADCAST SIGNAL IN DTV RECEIVING SYSTEM

A channel equalizer includes a first transformer, an estimator, an average calculator, a second transformer, a coefficient calculator, a compensator, and a third transformer. The first transformer converts normal data into frequency domain data, where a known data sequence is periodically repeated in the normal data. The estimator estimates channel impulse responses (CIR) during known data intervals adjacent to each normal data block. The average calculator calculates an average value of the CIRs. The second transformer converts the average value into frequency domain data. The coefficient calculator calculates equalization coefficients using the average value, and the compensator compensates channel distortion of each normal data block using the coefficients. The third transformer converts the compensated data block into time domain data.

BROADCASTING RECEIVER AND BROADCAST SIGNAL PROCESSING METHOD

A digital broadcasting system which is robust against an error when mobile service data is transmitted and a method of processing data are disclosed. The mobile service data is subjected to an additional coding process and the coded mobile service data is transmitted. Accordingly, it is possible to cope with a serious channel variation while applying robustness to the mobile service data.

METHOD OF PERFORMING TWO-DIMENSIONAL INTERLEAVING, AND RECORDING MEDIUM, AND APPARATUS FOR PERFORMING THE SAME

A two-dimensional interleaving method is provided. The two-dimensional interleaving method includes dividing a first page having N×Npixels, N being a natural number, into a plurality of blocks, wherein each of the plurality of blocks includes N×N pixels, rearranging each of the plurality of the blocks of the first page into a second page, wherein each of two index located at same position in two adjacent block of the first page, respectively, is rearranged to have at least a dispersion distance D in the second page, and relocating an index pixel located at same position of each of the plurality of the blocks of the first page into a k-th block of the second page. 1. A two-dimensional interleaving method comprising:{'sup': 2', '2, 'dividing a first page having N×Npixels, N being a natural number, into a plurality of blocks, wherein each of the plurality of blocks includes N×N pixels;'}rearranging each of the plurality of the blocks of the first page into a second page, wherein each of two index located at same position in two adjacent block of the first page, respectively, is rearranged to have at least a dispersion distance D therebetween in the second page; andrelocating an index pixel located at same position of each of the plurality of the blocks of the first page into a k-th block of the second page.3. The two-dimensional interleaving method of claim 2 , wherein [[k/N]+1 claim 2 , k mod N]th-pixel of each and every of the plurality of blocks of the first page is sequentially mapped into the k-th block of the second page in an order of the plurality of blocks of the first page.4. The two-dimensional interleaving method of claim 1 , wherein the relocating further comprise to use a pseudo code.5. The two-dimensional interleaving method of claim 1 , wherein the two-dimensional interleaving method further comprises outputting the second page.6. A computer-readable recording medium recording a computer program for executing the two-dimensional interleaving method ...

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The method as claimed in claim 1 , wherein the interleaving comprises:splitting the codeword into a plurality of bit groups; andinterleaving the plurality of bit group.3. The method as claimed in claim 1 , wherein the mapping comprises:demultiplexing the bits of the interleaved codeword into parallel streams to generate cells; andmapping the cells onto the constellation points. This application is a Continuation of application Ser. No. 14/716,283 filed May 19, 2015, the disclosure of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) mapper. The role of the QAM mapper is to map different bits output from the channel encoder and interleaved using the Bit Interleaver to QAM cells. Each cell represents a complex number having real and imaginary part. The QAM mapper groups M bits into one cell. Each cell is ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 2/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A bit interleaving method , comprising:storing a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15;generating an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; andoutputting the interleaved codeword,wherein the interleaving is performed using the following equation using permutation order:{'sub': j', 'j, 'where Xis the j-th bit group, Yis an interleaved j-th bit group, and π(j) is a permutation order for bit group-based interleaving.'}2. The bit interleaving method of claim 1 , wherein the permutation order corresponds to an interleaving sequence represented by the following{'br': None, 'interleaving sequence={7 11 4 38 19 25 2 43 15 26 18 14 9 29 44 32 0 5 35 10 1 12 6 36 21 33 37 34 3 31 20 16 40 23 41 22 30 39 13 24 17 42 28 8 27},'}wherein the interleaving sequence is for a case where 64-symbol mapping is employed.3. The bit interleaving method of claim 2 , wherein the 64-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 64 constellations.4. The bit interleaving method of claim 3 , wherein the parallel factor is 360 claim 3 , and the bit group includes 360 bits.5. The bit interleaving method of claim 4 , wherein the LDPC codeword is represented by (u claim 4 , u claim 4 , . . . claim 4 , u) ( ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF10/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping. 1. A bit-interleaved coded modulation (BICM) reception device , comprising:a demodulator configured to perform demodulation corresponding to 256-symbol mapping;a bit deinterleaver configured to perform group-unit deinterleaving on interleaved values, the interleaved values generated after the demodulation; anda decoder configured to restore information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving, the deinterleaved values corresponding to a LDPC codeword having a length of 16200 and a code rate of 10/15, wherein the group-unit deinterleaving is performed on a group basis, the size of the group corresponding to a parallel factor of the LDPC codeword.2. The BICM reception device of claim 1 , wherein the group-unit deinterleaving corresponds to a reverse process of interleaving performed by using permutation order claim 1 , and the permutation order corresponds to an interleaving sequence represented by the followinginterleaving sequence ={128 20 18 38 39 2 3 30 19 4 14 36 7 0 25 17 10 6 33 15 8 26 42 24 11 21 23 5 40 41 29 32 37 44 43 31 35 34 22 1 16 27 9 13 12}.3. The BICM reception device of claim 2 , wherein the 256-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 256 constellations.4. The BICM reception device of claim 2 , wherein the parallel factor is 360 claim 2 , and the group includes 360 ...

Apparatus for transmitting and receiving a signal and method of transmitting and receiving a signal

According to one embodiment, a transmitter for transmitting at least one broadcast signal having PLP (Physical Layer Pipe) data includes: a BCH (Bose-Chadhuri-Hocquenghem) encoder configured to BCH encode the PLP data; an LDPC (Low Density Parity Check) encoder configured to LDPC encode the BCH encoded PLP data and output FECFrames (Forward Error Correction Frames); a mapper configured to map data in the FECFrames onto constellations by QAM (Quadrature Amplitude Modulation) schemes; a time-interleaver configured to time-interleave the mapped data; a frame builder configured to build a signal frame including preamble symbols and data symbols; and an OFDM (Orthogonal Frequency Division Multiplexing) modulator configured to modulate data in the signal frame by an OFDM scheme. The PLP data are processed by an LDPC scheme for a long or a short LDPC FECframe. The preamble symbols include signaling information for the time-interleaved PLP data. The data symbols include the time-interleaved PLP data.

Transmitting method including bit group interleaving

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

TIME VARYING DATA PERMUTATION APPARATUS AND METHODS

Multiple data permutation operations in respective different dimensions are used to provide an overall effective data permutation using smaller blocks of data in each permutation than would be used in directly implementing the overall permutation in a single permutation operation. Data that has been permuted in one permutation operation is block interleaved, and the interleaved data is then permuted in a subsequent permutation operation. A matrix transpose is one example of block interleaving that could be applied between permutation operations. 1. A data encoder system comprising:a first permutation apparatus comprising a first time-varying permutation element, the first permutation apparatus being configured to generate a first time-varying stream;a Forward Error Correction (FEC) encoder configured to encode the first time-varying stream to generate an encoded stream; anda second permutation apparatus comprising a second time-varying permutation element, the second time-varying permutation element being configured to generate a second time-varying stream based on the encoded stream.2. The data encoder system of wherein the first permutation apparatus further comprising a block interleaver configured to generate an interleaved data stream claim 1 , the first-time varying stream being generated based on the interleaved data stream.3. The data encoder of wherein the second permutation apparatus comprises a de-interleaver configured to de-interleave the second time-varying stream.4. The data encoder of wherein the first permutation apparatus is configured to process an input data stream.5. The data encoder of wherein the second permutation apparatus is configured to generate an encoded output data stream based on the second-time varying stream.6. The data encoder of wherein the second permutation apparatus further comprises a third time-varying permutation element for performing inverse permutation.7. The data encoder of wherein the first time-varying permutation ...

BUTTERFLY NETWORK ON LOAD DATA RETURN

A method is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. 1. A method of data transformation of an input data word of 2sections , where N is an integer , comprising the steps of:supplying said input data word to a set of N sequential layers of 2 to 1 multiplexers disposed from an input layer to an output layer, wherein: each multiplexer has a first input receiving data of a first corresponding multiplexer of a prior layer, a second input receiving data of a second different corresponding multiplexer of a prior layer, a control input and an output, each multiplexer providing an output corresponding to a selected one of said first input or said second input dependent upon a signal at said control input, andsupplying a same control signal to each control input of each multiplexer of a layer; andoutputting transformed data from said outputs of said multiplexers of said output layer.2. The method of wherein: precalculating an N bit shuffle pattern,', 'precalculating an N bit replicate pattern,', 'precalculating an N bit rotate pattern, and', 'supplying to said control input of each multiplexer of a layer a selected one of 1) a corresponding bit of said precalculated shuffle pattern, 2) a corresponding bit of said precalculated replicate pattern, 3) a corresponding bit of said rotate pattern, 4) an exclusive OR of said corresponding bit of said precalculated shuffle pattern and said corresponding bit of precalculated replicate pattern, 5) an exclusive OR of said corresponding bit of said precalculated shuffle pattern and ...

ERROR CORRECTION DEVICE AND ERROR CORRECTION METHOD

Provided is an error correction device including an encoding circuit configured to encode a plurality of error correction code sequences, in which the encoding circuit includes a plurality of encoding circuits connected in parallel, and is configured to execute encoding processing for the plurality of error correction code sequences through use of all the plurality of encoding circuits by adjusting an output bus width and a frequency of an operation clock with respect to a difference in transmission rate for any payloads input in one or more systems. 1. An error correction device , comprising at least one of:an encoder configured to encode a plurality of error correction code sequences; anda decoder configured to decode the plurality of error correction code sequences,wherein the encoder includes a predetermined plurality of encoders connected in parallel, and is configured to execute encoding processing for the plurality of error correction code sequences through use of all the predetermined plurality of encoders by adjusting an output bus width and a frequency of an operation clock with respect to a difference in transmission rate for any one of a payload input in one system and payloads input in two or more systems, andwherein the decoder includes a predetermined plurality of decoders connected in parallel, and is configured to execute decoding processing for the plurality of error correction code sequences through use of all the predetermined plurality of decoders by adjusting an output bus width and a frequency of an operation clock with respect to a difference in transmission rate for any one of a payload input in one system and payloads input in two or more systems.2. The error correction device according to claim 1 , wherein the plurality of error correction code sequences are subjected to interleaving in units of bit or symbol with respect to a transmission order among data buses to which the plurality of error correction code sequences are input.3. The ...

TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method. 1. An interleaving method of a transmitting apparatus , the method comprising:splitting bits into a plurality of bit groups;interleaving the plurality of bit groups;interleaving the interleaved plurality of bit groups using a plurality of containers to provide an interleaved codeword, each of the plurality of containers comprising a first part and a second part;demultiplexing bits of the interleaved codeword to generate cells;mapping the cells onto constellation points, andtransmitting a signal which is based on the constellation points,wherein a number of bits to be written in the first part is determined based on a number of the plurality of containers and a number of bits of each of the plurality of bit groups, andwherein a number of bits to be written in the second part is determined based on the number of the plurality of containers and the number of the bits of each of the plurality of bit groups.2. The method as claimed in claim 1 , wherein the each of the plurality of bit groups comprises 360 bits.3. The method as claimed in claim 1 , wherein the number of the plurality of containers is equal to a modulation order for the mapping.4. A transmitting apparatus comprising:a group interleaver configured to split bits into a plurality of bit groups and interleave the plurality of bit groups;a block ...

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 3/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. 1. A bit interleaver , comprising:a first memory configured to store a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15;a processor configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; anda second memory configured to provide the interleaved codeword to a modulator for 64-symbol mapping.2. The bit interleaver of claim 1 , wherein the 64-symbol mapping is a Non-Uniform Constellation (NUC) symbol mapping which corresponds to 64 constellations.3. The bit interleaver of claim 2 , wherein the parallel factor is 360 claim 2 , and the bit group includes 360 bits.6. The bit interleaver of claim 5 , wherein the permutation order corresponds to an interleaving sequence represented by the following equation:{'br': None, 'interleaving sequence={19 34 22 6 29 25 23 36 7 8 24 16 27 43 11 35 5 28 13 4 3 17 15 38 20 0 26 12 1 39 31 41 44 30 9 21 42 18 14 32 10 2 37 33 40}'} This application is a continuation of U.S. application Ser. No. 14/717,174, filed May 20, 2015, which claims the benefit of Korean Patent Application Nos. 10-2014-0061874 and 10-2015-0009141, filed May 22, 2014 and Jan. 20, 2015, which are hereby incorporated by reference herein in their entirety.The present disclosure relates generally to an interleaver and, ...

TRANSMITTER APPARATUS AND BIT INTERLEAVING METHOD THEREOF

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. 2. The transmitting method of claim 1 , wherein each of the plurality of bit groups comprises 360 bits.3. The transmitting method of claim 1 , wherein the interleaving further comprises:interleaving the interleaved plurality of bit groups.4. The transmitting method of claim 1 , wherein the π(j) is determined based on at least one of the code length claim 1 , a modulation method for the mapping claim 1 , and the code rate.6. The method of claim 5 , wherein each of the plurality of groups comprises 360 values.7. The method of claim 5 , wherein the π(j) is determined based on at least one of the code length claim 5 , a modulation method for the mapping claim 5 , and the code rate. This is a Continuation of U.S. application Ser. No. 16/460,305 filed Jul. 2, 2019, which is a Continuation of U.S. application Ser. No. 15/686,280 filed Aug. 25, 2017, which is a Continuation of application Ser. No. 14/716,503 filed May 19, 2015, and claims priority from U.S. Provisional Application No. 62/001,160 filed on May 21, 2014 and Korean Patent Application No. 10-2015-0069924 filed on May 19, 2015, the disclosures of which are incorporated herein by reference in their entirety.Apparatuses and methods consistent with exemplary embodiments ...

APPARATUS FOR TIME INTERLEAVING AND METHOD USING THE SAME

An apparatus and method for time interleaving corresponding to hybrid time interleaving mode are disclosed. An apparatus for time interleaving according to an embodiment of the present invention includes a twisted block interleaver configured to perform intra-subframe interleaving corresponding to time interleaving blocks; and a convolutional delay line configured to perform inter-subframe interleaving using an output of the twisted block interleaver. 1. An apparatus for time deinterleaving , comprising:an inverse convolutional delay line configured to perform an inverse process of inter-subframe interleaving which is performed by a convolutional delay line of a transmitter; anda twisted block deinterleaver configured to perform an inverse process of intra-subframe interleaving which is performed by a twisted block interleaver of the transmitter,wherein the inter-subframe interleaving is performed by using an output of the intra-subframe interleaving at the transmitter.2. The apparatus of claim 1 , wherein the intra-subframe interleaving is performed by a column-wise writing operation and a diagonal-wise reading operation.3. The apparatus of claim 1 , wherein the convolutional delay line reads only data cells except for virtual cells from the twisted block interleaver.4. The apparatus of claim 3 , wherein after each row of the data cells is written from the twisted block interleaver claim 3 , the convolutional delay line generates new virtual cells prior to switches moving to a next branch.5. The apparatus of claim 4 , wherein the new virtual cells correspond to a number obtained by subtracting a number (N) of FEC blocks in a time interleaving block of an interleaving frame from a maximum number (N) of the FEC blocks corresponding to the time interleaving block of the interleaving frame for each branch.6. The apparatus of claim 5 , wherein the new virtual cells are not outputted from a time interleaver of the transmitter.7. The apparatus of claim 6 , wherein the ...

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

The present invention provides an apparatus of transmitting broadcast signals, the apparatus including, an encoder for encoding service data, a frame builder for building at least one signal frame by mapping the encoded service data, a modulator for modulating data in the built at lease one signal frame by an Orthogonal Frequency Division Multiplexing, OFDM, scheme and a transmitter for transmitting the broadcast signals having the modulated data. 5. An apparatus of receiving broadcast signals , the apparatus including:a receiver configured to receive the broadcast signals;a demodulator configured to demodulate the received broadcast signals including service data by an Orthogonal Frequency Division Multiplexing (OFDM) scheme; anda Low-Density Parity Check (LDPC) decoder configured to LDPC decode service data based on a matrix,wherein the service data is a codeword having information bits and parity bits, when a length of the codeword is 16200 bits and a code rate of the codeword is 7/15, the matrix is determined based on a following table:{'img': {'@id': 'CUSTOM-CHARACTER-00001', '@he': '7.53mm', '@wi': '135.93mm', '@file': 'US20200021860A1-20200116-P00999.TIF', '@alt': 'text missing or illegible when filed', '@img-content': 'character', '@img-format': 'tif'}}wherein each row of the table corresponds to each group of 360 information bits,wherein each value in the each row represents an address of a parity bit.6. The apparatus of claim 5 ,wherein the LDPC decoder decodes data being updated a parity bit of the codeword which is located in an address of j-th entry in i-th row in the table by accumulating an information bit of the codeword to the parity bit of the codeword, and updated the parity bit.7. A method of receiving broadcast signals claim 5 , the method including:receiving the broadcast signals;demodulating the received broadcast signals including service data by an Orthogonal Frequency Division Multiplexing (OFDM) scheme; andLow-Density Parity Check (LDPC) ...

APPARATUS AND METHOD FOR GENERATING INTERLEAVER INDEX

Disclosed is an apparatus and a method for generating an internal interleaver index of a turbo encoder in parallel. There are effects of reducing the time spent for generating total indexes by generating indexes for a plurality of bits in parallel and improving the resource efficiency and the performance in the hardware implementation by calculating indexes for following bits through the use of an index calculated for a predetermined bit without the use of a multiplier and a divider. 1. An apparatus for generating indexes of an interleaver for input data , the apparatus comprising:a main processor for calculating an index for a predetermined bit of the input data; andan index operator for receiving the index calculated by the main processor, calculating in parallel indexes for bits after the predetermined bit, and deriving a plurality of indexes.2. The apparatus as claimed in claim 1 , wherein the main processor or the index operator calculates the index by using a difference between indexes.3. The apparatus as claimed in claim 1 , wherein the index for the predetermined bit is calculated by an equation (a) of{'br': None, 'i': i+', 'i', 'f', '+f', 'f', '*i', 'K., 'sub': 1', '2', '2, 'Π(1)−Π()=(+2*)mod'}4. The apparatus as claimed in claim 3 , wherein a modular operation of the equation (a) is performed using an adder and a multiplexer.5. The apparatus as claimed in claim 4 , wherein the adder adds a dividend of the modular operation and a sign inverted divisor of the modular operation claim 4 , and the multiplexer receives inputs of a result of the addition and the dividend claim 4 , wherein the multiplexer outputs the dividend when the result of the addition is a negative number and outputs a result of the adder when the result of the adder is a positive number.6. The apparatus as claimed in claim 1 , wherein the main processor calculates indexes for ito i+15bits (i is an integer equal to or larger than 0) of the input data claim 1 , and the index operator ...

Decoding Method, Decoding Apparatus, and Communications System

The present invention provides a decoding method, a decoding apparatus, and a communications system, which implement multi-level coding in a manner combining soft-decision error correction coding and hard-decision error correction coding, implement multi-level decoding in a manner combining soft-decision error correction decoding and hard-decision error correction decoding, so as to integrate advantages of the two manners: compared with a manner in which soft-decision error correction coding and decoding are performed on multiple levels, a manner in which soft-decision error correction coding and decoding are performed on only one level reduces system complexity and resource overhead; and performing hard-decision error correction coding and decoding on other levels on a basis of performing soft-decision error correction coding and decoding on one level ensures gain performance, thereby meeting a gain requirement of a high-speed optical transmission system. 1. A decoding apparatus , comprising a one or more computers including a non-transitory computer-readable medium storing program units executable by the one or more computers , the units including:a primary demapping unit;a soft-decision error correction decoder;a first demapping unit;a first deinterleaver;a first hard-decision error correction decoder; andan output unit;wherein the primary demapping unit is configured to demap information received by the decoding apparatus, and output obtained soft information of a first-level component to the soft-decision error correction decoder;wherein the soft-decision error correction decoder is configured to perform decoding according to the received soft information of the first-level component, and output the decoded soft information of the first-level component;wherein the first demapping unit is configured to demap, by using the soft information of the first-level component that is output by the soft-decision error correction decoder as prior information, the ...

BROADCAST TRANSMITTER AND METHOD OF PROCESSING BROADCAST SERVICE DATA FOR TRANSMISSION

A method of processing broadcast data in a broadcast transmitter. The method can include randomizing broadcast service data, first encoding the randomized broadcast service data to add parity data to the randomized broadcast service data, second encoding the first-encoded broadcast service data at a code rate of D/E (D Подробнее

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder for encoding service data corresponding to each of a plurality of data transmission path, wherein each of the data transmission path carries at least one service component for broadcast services, an encoder for encoding signaling data, wherein the signaling data includes static data and dynamic data, a frame builder for building signal frames, wherein each of signal frames includes the encoded service data and the encoded signaling data, wherein each of signal frames belongs to one of the broadcast services, wherein the static data remain constant in the signal frames belonging to the broadcast service in a duration of a super frame and the dynamic data changes by the signal frames, a modulator for modulating the signal frames by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter for transmitting the broadcast signals carrying the modulated signal frames. 120-. (canceled)21. A Method For Transmitting Broadcast Signals , Comprising:encoding service data corresponding to each of a plurality of data transmission paths;encoding signaling data;padding zero bits to the encoded signaling data, wherein a size of the padded zero bits is related to the variable size of the signaling data;LDPC encoding the zero padded signaling data by appending parity bits;building signal frames, wherein each of signal frames includes the encoded service data and the LDPC encoded signaling data;modulating the signal frames by an OFDM (Orthogonal Frequency Division Multiplex) scheme; andtransmitting the broadcast signals carrying the modulated signal frames.22. The method of claim 21 , wherein the method further comprises:segmenting the signaling data for the encoding.23. The method of claim 22 , wherein the method further comprises:scrambling the segmented signaling data.24. The method of claim 21 , ...

SIGNAL PROCESSING METHOD

A signal method of processing in a receiver a signal that has been encoded and interleaved in a transmitter comprising: receiving a signal, process the signal to obtain a stream of soft metrics representing bit probability of symbols in a predetermined constellation; applying to said soft metric a compression operation that preserves the total length of each group of soft metrics relative to a same constellation symbol; rearranging the stream of compressed soft metrics so as to inverse the interleaving done in the transmitter. 1. A method of compressing a stream of fixed-point representations of soft metrics in a receiver , comprisingdemultiplexing the soft metrics so as to obtain a plurality sub-streams having distinct statistics distributions.applying to each sub-stream an entropy code adapted to its statistic distribution.2. The method of claim 1 , further comprisingreconstruct a transmitted message according to each of the sub-stream which is applied with the entropy code adapted to its statistic distribution.3. The method of claim 1 , comprising a step of quantizing the soft metrics prior to the step of demultiplexing the soft metrics.4. The method of claim 1 , wherein said soft metrics are represented as fixed-point numbers.5. The method of claim 3 , wherein the quantizing operation generates a constant number of bits for each group of soft metrics relative to a same constellation symbol.6. The method of claim 3 , wherein the quantizing operation generates different number of bits for each soft metric relative to a same constellation symbol. This application is a divisional application of and claims the priority benefits of U.S. non-provisional application Ser. No. 14/422,149, filed on Feb. 17, 2015, now allowed. The prior U.S. non-provisional application Ser. No. 14/422,149 is a 371 application of the International PCT application serial no. PCT/EP2012/066286, filed on Aug. 21, 2012. The entirety of each of the above-mentioned patent applications is hereby ...

Signal multiplexing apparatus using layered division multiplexing and signal multiplexing method

An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels to generate a multiplexed signal, a power normalizer configured to reduce power of the multiplexed signal to power corresponding to the core layer signal, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal.

Broadcasting of Digital Video to Mobile Terminals

A method includes processing error correction encoded data by a first processing chain of a transmitter. The processing includes interleaving a first portion of the error correction encoded data with respect to a first interleaving period to generate a first output signal. Interleaving the first portion includes de-multiplexing the first portion among multiple branches having respective delays in accordance with a distribution order and re-multiplexing delayed data from the branches to form the first output signal. The method includes processing the error correction encoded data by a second processing chain of the transmitter without use of interleaving to generate a second output signal. The method includes multiplexing the first output signal and the second output signal into a multiplexed stream. The method also includes transmitting the multiplexed stream from the transmitter over a communication channel to a receiver. 1. A method comprising:processing error correction encoded data by a first processing chain of a transmitter, the processing including interleaving a first portion of the error correction encoded data with respect to a first interleaving period to generate a first output signal, wherein the interleaving the first portion comprises de-multiplexing the first portion among multiple branches having respective delays in accordance with a distribution order and re-multiplexing delayed data from the branches to form the first output signal;processing the error correction encoded data by a second processing chain of the transmitter without use of interleaving to generate a second output signal;multiplexing the first output signal and the second output signal into a multiplexed stream; andtransmitting the multiplexed stream from the transmitter over a communication channel to a receiver.2. The method of claim 1 , further comprising encoding input data with an error correction code encoder of the transmitter to produce the error correction encoded data.3. ...

APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS

A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals comprises an encoder for encoding DP (Data Pipe) data corresponding to each of a plurality of DPs, a mapper for mapping the encoded DP data onto constellations, a time interleaver for time interleaving the mapped DP data at DP level, a frame builder for building at least one signal frame including the time interleaved DP data, a modulator for modulating data in the built at least one signal frame by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter for transmitting the broadcast signals having the modulated data. 114-. (canceled)15. A method for transmitting broadcast signals , the method comprising:encoding service data;mapping the encoded service data to output cells, wherein the cells are included in at least one forward error correction (FEC) block;time interleaving the mapped service data, wherein the time interleaving includes:a column-wise writing the at least one FEC block into at least one time interleaving (TI) block,wherein the at least one TI block includes at least one virtual FEC block,wherein a number of FEC blocks varies in TI blocks; anddiagonal-wise reading cells of the at least one TI block based on a diagonal-wise reading parameter,wherein cells in the at least one virtual FEC block are skipped during the diagonal-wise reading based on cell position;building at least one signal frame including the time interleaved service data;modulating data in the built at least one signal frame by an Orthogonal Frequency Division Multiplex (OFDM) scheme; andtransmitting the broadcast signals having the modulated data.16. The method of claim 15 , wherein the method further includes:wherein the diagonal-wise reading is performed by calculating the cell position based on row and column indexes of TI memory, andwherein slope for the diagonal wise reading is based on the diagonal-wise reading parameter.17. The ...

TRANSMITTER AND PARITY PERMUTATION METHOD THEREOF

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups, and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups so that the puncturer selects parity bits included in the some of the bit groups positioned at the predetermined positions sequentially and selects parity bits included in the remainder of the bit groups without an order. 2. The receiving method of claim 1 , wherein the transmitting apparatus encodes 6480 information bits according to the code rate of 6/15 to generate 9720 parity bits.3. The receiving apparatus of claim 1 , wherein the plurality of groups comprise 45 groups including 0to 44groups.5. The transmitting method of claim 4 , wherein the encoding comprises encoding 6480 information bits based on the code rate of 6/15 to generate 9720 parity bits. This application is a continuation of U.S. application Ser. No. 16/390,393, filed on Apr. 22, 2019, which is a continuation of U.S. application Ser. No. 15/058,318, filed on Mar. 2, 2016, which claims priority from Korean Patent Application No. 10-2015-0137185, filed on Sep. 27, 2015, and U.S. Provisional Application No. 62/127,056, filed on Mar. 2, 2015, the disclosures of which are incorporated herein in by reference in their entireties.Apparatuses and methods consistent with the exemplary embodiments of the inventive concept relate to a transmitter and a parity permutation ...

TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted in a current frame; a parity permutator configured to perform parity-permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups configuring the interleaved parity bits based on a group-wise interleaving pattern including a first pattern and a second pattern; a puncturer configured to puncture some of the parity-permutated parity bits; and an additional parity generator configured to select at least some of the punctured parity bits to generate additional parity bits to be transmitted in a previous frame of the current frame, based on the first pattern and the second pattern, wherein the first pattern determines parity bits to remain after the puncturing and then to be transmitted in the current frame. 1. A receiving method comprising:receiving a signal from a transmitting apparatus;demodulating the signal to generate values based on 64-quadrature amplitude modulation (QAM);inserting predetermined values;splitting the values and the inserted predetermined values into a plurality of groups;deinterleaving some groups among the plurality of groups based on a permutation order to provide deinterleaved plurality of groups in which the some groups are deinterleaved; anddecoding values of the deinterleaved plurality of groups based on a low density parity check (LDPC) code, a code rate of the LDPC code being 6/15 and a code length of the LDPC code being 16200 bits,wherein positions of the inserted predetermined values correspond to positions of parity bits punctured in the transmitting apparatus, andwherein groups having indices of 25, 42, 34, 18, 32, 38, 23, 30, 28, 36 and 41 among the deinterleaved plurality of groups comprise at least a part of the predetermined values.2. The receiving method of claim 1 , wherein a number ...

Apparatus for transmitting data in interleave division multiple access (idma) system

There is provided an apparatus including an acquisition unit that acquires an information block generated from transmission data for a user and subjected to error correction coding, and an interleaving unit that interleaves a bit sequence of the information block using an interleaver unique to the user. The interleaving unit interleaves the bit sequence by interleaving each of two or more partial sequences obtained from the bit sequence.

Additional Bit Freezing For Polar Coding

Examples pertaining to additional bit freezing for polar coding are described. An apparatus performs polar coding to encode a plurality of input subblocks of information bits, frozen bits and optional cyclic redundancy check (CRC) bits to generate a plurality of subblocks of coded bits. The apparatus then transmits at least some of the subblocks of coded bits. In performing the polar coding, the apparatus additionally freezes one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits which decreases polarization gain due to puncturing. 1. A method , comprising:performing, by a processor of an apparatus, polar coding to encode a plurality of input subblocks of information bits, frozen bits and optional cyclic redundancy check (CRC) bits to generate a plurality of subblocks of coded bits; andtransmitting, by the processor, at least some of the subblocks of coded bits, performing encoder input bit mapping and freezing on the plurality of input subblocks;', 'additionally freezing one or more encoder input bit channels; and', 'rate-matching and subblock interleaving the plurality of input subblocks to result in one or more punctured bits, one or more shortened bits, and one or more output bits as the at least some of the subblocks of coded bits that are transmitted., 'wherein the performing of the polar coding comprises2. The method of claim 1 , wherein the performing of the polar coding comprises performing the polar coding in an incremental redundancy hybrid automatic repeat request (IR-HARQ) procedure claim 1 , and wherein the transmitting comprises performing a retransmission in the IR-HARQ procedure.3. The method of claim 1 , wherein the additionally freezing of the one or more encoder input bit channels comprises additionally freezing one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits containing a largest index of punctured bits compared to ...

VIRTUAL NETWORK PRE-ARBITRATION FOR DEADLOCK AVOIDANCE AND ENHANCED PERFORMANCE

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request. 1. An integrated circuit device comprising:a set of processor interfaces;a data path configured to couple the set of processor interfaces to a shared resource; receive a set of requests via the set of processor interfaces;', 'select a first request from among the set of requests for service over the data path;', 'receive a subsequent request after the set of requests is received;', 'select a second request from among the first request and the subsequent request for service over the data path; and', 'cause the data path to service the second request., 'an arbiter circuit coupled to the set of processor interfaces and the data path and configured to2. The integrated circuit device of claim 1 , wherein the arbiter circuit is configured to select the first request based on a first set of criteria and select the second request based on a second set of criteria that is different from the first set of criteria.3. The integrated circuit device of claim 2 , wherein the arbiter circuit is configured to select the first request based on the first set of criteria by:determining a respective credit cost for each ...

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. This application is a Continuation of application Ser. No. 15/705,603, filed Sep. 15, 2017, which is a Continuation of application Ser. No. 14/716,283 filed May 19, 2015, now U.S. Pat. No. 9,787,422, issued Oct. 10, 2017, the disclosures of which are incorporated herein by reference in their entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) mapper. The role of the QAM mapper is to map different bits output from the channel encoder and interleaved using the Bit Interleaver to QAM cells. Each cell represents a complex number having real and imaginary part. The QAM mapper groups M bits into one cell. Each cell is translated into a complex number. M, which is the number of bits per cell, is equal to 2 for QPSK, 4 for 16QAM, 6 for 64QAM, and 8 for 256. It is possible to use a higher QAM size in order to increase a throughput. For example: 1K QAM is a constellation ...