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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 1330. Отображено 100.
11-07-2013 дата публикации

Error correct coding device, error correct coding method, and error correct coding program

Номер: US20130179757A1
Автор: Norifumi Kamiya
Принадлежит: NEC Corp

Disclosed are an encoding apparatus for a quasi-cyclic low-density parity check code for calculating r×m-bit redundant data for information data of length k×m bits (k, m and r are positive integers), and a cyclic addition apparatus including a k×m-bit shift register and exclusive OR. With information data of a length of k×m×L bits (L≦k), a length of (r×m×(L+1)+k×m) bits is calculated as redundant data by adding redundant data of a length of r×m×L bits calculated using the encoding apparatus L times, k×m-bit data calculated by inputting the information data of a length of k×m×L bits to the cyclic addition apparatus, and r×m-bit redundant data calculated by inputting the k×m-bit data to the encoding apparatus.

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Номер записи: 1
22-08-2013 дата публикации

Data packet transmission/reception apparatus and method

Номер: US20130219240A1
Автор: Hyunkoo YANG, Seho Myung, Sunghee Hwang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method and apparatus are provided for recovering data efficiently even when data loss has occurred over a channel or network. The packet transmission method includes arranging a first transmission packet in a source symbol in a first region of a source block; arranging a second transmission packet in a space starting with an empty space of a last source symbol where the first transmission packet is arranged, remaining after arranging the first transmission packet; arranging information related to the second transmission packet in a second region of the source block; performing Forward Error Correction (FEC) encoding on the source block; and transmitting the encoded source block.

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Номер записи: 2
17-10-2013 дата публикации

Sparse superposition encoder and decoder for communications system

Номер: US20130272444A1
Автор: Andrew R. Barron, Antony Joseph
Принадлежит: YALE UNIVERSITY

A computationally feasible encoding and decoding arrangement and method for transmission of data over an additive white Gaussian noise channel with average codeword power constraint employs sparse superposition codes. The code words are linear combinations of subsets of vectors from a given dictionary, with the possible messages indexed by the choice of subset. An adaptive successive decoder is shown to be reliable with error probability exponentially small for all rates below the Shannon capacity.

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Номер записи: 3
21-11-2013 дата публикации

Systems and methods for non-binary ldpc encoding

Номер: US20130311845A1
Автор: Fan Zhang, Shaohua Yang, Zongwang Li
Принадлежит: LSI Corp

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding.

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Номер записи: 4
27-03-2014 дата публикации

Apparatus and method for low density parity check (ldpc) encoding

Номер: US20140089766A1
Автор: Deock Gil Oh, In Ki LEE, Ji Won JUNG, Min Hyuk KIM
Принадлежит: Electronics and Telecommunications Research Institute ETRI

Provided is a low density parity check (LDPC) encoding apparatus and method that may store M registers each including N bits, obtain N×M parity bits by performing a partial parallel operation an N×M number of times with respect to the M registers, and mutually invert subsequent N parity bits periodically, based on previous parity bits for each Nth parity bit of the N×M parity bits, respectively.

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Номер записи: 5
06-01-2022 дата публикации

METHOD AND APPARATUS FOR FAST DECODING LINEAR CODE BASED ON SOFT DECISION

Номер: US20220006472A1
Автор: CHOI Chang Ryoul, JEONG Je Chang
Принадлежит: Industry-University Cooperation Foundation Hanyang University

Disclosed are a method and an apparatus for fast decoding a linear code based on soft decision. The method may comprise sorting received signals in a magnitude order to obtain sorted signals; obtaining hard decision signals by performing hard decision on the sorted signals; obtaining upper signals corresponding to MRBs from the hard decision signals; obtaining a permuted and corrected codeword candidate using the upper signals and an error vector according to a current order; calculating a cost for the current order using a cost function; determining the permuted and corrected codeword candidate as a permuted and corrected codeword according to a result of comparing the calculated cost with a minimum cost; and determining a predefined speeding condition. 1. A method for fast decoding a linear code based on soft decision , the method comprising:sorting received signals in a magnitude order to obtain sorted signals;obtaining hard decision signals by performing hard decision on the sorted signals;obtaining upper signals corresponding to most reliable bases (MRBs) from the hard decision signals;obtaining a permuted and corrected codeword candidate using the upper signals and an error vector defined as a vector having a current order according to a hamming weight;calculating a cost for the error vector using a cost function; anddetermining the permuted and corrected codeword candidate as a permuted and corrected codeword according to a result of comparing the calculated cost with a minimum cost.2. The method according to claim 1 , wherein the obtaining of the permuted and corrected codeword candidate comprises performing a Gaussian elimination to obtain a permuted generator matrix after permuting a generator matrix for a codeword expressed as a vector based on the sorted signals claim 1 , and obtaining the permuted and corrected codeword candidate by multiplying the upper signals and the error vector with the permuted generator matrix.3. The method according to claim 1 , ...

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Номер записи: 6
07-01-2016 дата публикации

Controller device with retransmission upon error

Номер: US20160004594A1
Автор: Frederick A. Ware, Yuanlong Wang
Принадлежит: RAMBUS INC

A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

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Номер записи: 7
01-01-2015 дата публикации

APPARATUS AND METHOD FOR ERROR CORRECTION AND ERROR DETECTION

Номер: US20150007001A1
Автор: Backhausen Ulrich, Badack Christian, Goessel Michael, Kern Thomas, Oberlaender Klaus, Rabenalt Thomas
Принадлежит:

A circuitry comprising a syndrome generator configured to generate a syndrome based on a parity check matrix and a binary word comprising a first set of bits and a second set of bits is provided. For the first set of bits an error correction of correctable bit errors within the first set is provided by the parity check matrix and for the second set of bits an error detection of a detectable bit errors within the second set is provided by the parity check matrix. 1. A syndrome generator for forming an error syndrome of a linear code C of length n with an H-matrix H=(h , . . . , h) of n columns h , . . . , hof m components each such that the H-matrix is an (m , n)-matrix , wherein a codeword v=v , . . . , vof the code C comprises a first subword x , . . . , xof length k+m and a second subword a , . . . , aof length l with n=k+m+l ,{'sup': x', 'x', 'x', 'a', 'a', 'a, 'sub': 1', 'k+m', '1', 'l, 'wherein the code C is configured for correcting 1, . . . , t-bit errors in bits of the first subword and to detect 1, . . . , l bit errors in bits of the second subword so that the columns of the H-matrix H corresponding to the bits of the first subword are forming a first (m, k+m)-sub-matrix H=(h, . . . , h) and so that the columns of the H-matrix H corresponding to the bits of the second subword are forming a second sub-matrix H=(h, . . . , h),'}{'sup': 'x', 'wherein all linear combinations of up to t columns of the first submatrix H, which do not result in the zero vector, are pairwise different, and'}{'sup': 'a', 'sub': 'x', 'wherein all linear combinations of the columns of the second submatrix Hare different from all linear combinations of up to t columns of the first sub-matrix H, which do not result in the zero vector,'}wherein t≧1, k>0, k+m≧4, and l>t+1.2. The syndrome generator according to claim 1 , wherein at least a portion of the first subword x claim 1 , . . . claim 1 , x=u claim 1 , . . . claim 1 , u claim 1 , c claim 1 , . . . claim 1 , cis stored in a memory ...

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Номер записи: 8
04-01-2018 дата публикации

BIT-ERROR RATE FALSE POSITIVE DETECTION SYSTEM AND METHOD

Номер: US20180006662A1
Автор: Gho Gwang-Hyun, HAYES Matthew
Принадлежит:

A communication device can be configured to detect false positives of a decoded signal that have passed error detection. The communication device can include an error detector and a false positive detector. The error detector can detect an error of a decoded signal generated from an encoded signal, and output a payload of the decoded signal in response to the decoded signal passing the error detection. The false positive detector can calculate an estimated bit-error rate (BER) of the encoded signal and a predicted BER of the encoded signal. The false positive detector can determine a false positive of the error detection passing of the decoded signal based on the estimated BER and the predicted BER. 1. A communication device operable to receive an encoded signal , comprising:an error detector configured to detect an error of a decoded signal generated from the encoded signal; anda false positive detector configured to determine a false positive of the decoded signal having passed error detection by the error detector based on an estimated bit-error rate (BER) of the encoded signal and a predicted BER of the encoded signal.2. The communication device of claim 1 , wherein the false positive detector is further configured to calculate the estimated BER based on:a number of bits corrected through decoding of the encoded signal that generates the decoded signal; anda number of bits of the encoded signal.3. The communication device of claim 2 , wherein the false positive detector is configured to calculate the estimated BER based on a ratio of the number of bits corrected and the number of bits of the encoded signal.4. The communication device of claim 2 , wherein the false positive detector is further configured to calculate the predicted BER based on a signal-to-noise ratio (SNR) of the encoded signal.5. The communication device of claim 1 , wherein the false positive detector is further configured to calculate the predicted BER based on a signal-to-noise ratio (SNR) of ...

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Номер записи: 9
04-01-2018 дата публикации

METHODS AND APPARATUS FOR PERFORMING REED-SOLOMON ENCODING BY LAGRANGIAN POLYNOMIAL FITTING

Номер: US20180006664A1
Автор: Finn Simon, Langhammer Martin, Mumtaz Sami
Принадлежит:

An integrated circuit for implementing a Reed-Solomon encoder circuit is provided. The encoder circuit may include partial syndrome calculation circuitry and matrix multiplication circuitry. The partial syndrome calculation circuitry may receive a message and generate corresponding partial syndromes. The matrix multiplication circuitry may receive the partial syndromes and may compute parity check symbols by multiplying the partial syndromes by predetermined Lagrangian polynomial coefficients. The parity check symbol generation step may be performed in one clock cycle or multiple clock cycles. 1. An integrated circuit , comprising:partial syndrome calculation circuitry that receives a message and that generates corresponding partial syndrome values; andmatrix multiplication circuitry that receives the partial syndrome values from the partial syndrome calculation circuitry and that generates corresponding parity symbols.2. The integrated circuit of claim 1 , wherein the matrix multiplication circuitry includes an array of Galois Field multipliers.3. The integrated circuit of claim 2 , wherein the array of Galois Field multipliers comprises constant Galois Field multipliers claim 2 , each of which receives a respective precomputed Lagrangian coefficient.4. The integrated circuit of claim 2 , wherein the array of Galois Field multipliers comprises variable Galois Field multipliers claim 2 , each of which receives varying Lagrangian coefficients.5. The integrated circuit of claim 2 , wherein the matrix multiplication circuitry includes Galois Field adders for summing products generated from the array of Galois Field multipliers.6. The integrated circuit of claim 1 , wherein the partial syndrome calculation circuitry includes a plurality of partial syndrome calculation circuits claim 1 , each of which receives the same message symbols in parallel.7. The integrated circuit of claim 4 , wherein the matrix multiplication circuitry further includes:a plurality of tables that ...

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Номер записи: 10
03-01-2019 дата публикации

POLAR CODE ENCODING METHOD AND DEVICE

Номер: US20190007165A1
Автор: CHEN Jun, Li Bin, Shen Hui
Принадлежит: Huawei Technologies CO.,Ltd.

Disclosed in embodiments of the present disclosure are a polar code encoding method and device. The method includes: utilizing a common information bit set to represent each of m polar code blocks, the polar codes in each polar code block having the same code length and different code rates, and m being greater than or equal to 2; according to the common information bit set corresponding to the polar code block, acquiring an information bit set corresponding to each polar code in the polar code block; and according to the information bit set corresponding to each polar code in the polar code block, conducting polar code encoding on information to be encoded, thus reducing polar code representation overhead, and solving the problem in the prior art of excessively high polar code representation overhead. 1. A channel coding method , performed by a coding device in a communication system , comprising:obtaining K bits of data, wherein K is greater than or equal to 1;obtaining an information bit index set from a common bit index set, wherein the information bit index set comprises K indexes, the common bit index set comprises M indexes, and wherein M is greater than or equal to K;encoding the K bits of data using the information bit index set, to generate a polar code; andoutputting the polar code;wherein polar codes generated by encoding data bits using an information bit index set obtained from the common bit index set have a same code length.2. The method according to claim 1 , wherein the common bit index set is a union of information bit index sets corresponding to all of polar code generated by encoding data bits using an information bit index set obtained from the common bit index set.3. The method according to claim 1 , wherein all of polar code generated by encoding data bits using an information bit index set obtained from the common bit index set corresponding to a group of polar codes claim 1 , the group of polar codes has different code rates.4. The method ...

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Номер записи: 11
12-01-2017 дата публикации

SYSTEM IDENTIFICATION DEVICE

Номер: US20170010861A1
Автор: KANAI Yurika, SAITO Mitsunori
Принадлежит: Mitsubishi Electric Corporation

A system identification device includes: a direct feedthrough term identification unit that receives an impulse response of a dynamic system; a block Hankel matrix generation unit; a singular value decomposition unit that, by singular value decomposition of the block Hankel matrix, outputs a first orthogonal matrix, a second orthogonal matrix, and a singular value; a system dimension determination unit that, on the basis of the first orthogonal matrix, second orthogonal matrix, singular value, and search range, identifies a system matrix other than a direct feedthrough term, and from a comparison of the actual system characteristics and system characteristics calculated on the basis of the system matrix and direct feedthrough term, determines the system dimension; and a system matrix identification unit that identifies a system matrix other than the direct feedthrough term on the basis of the first orthogonal matrix, second orthogonal matrix, singular value, and system dimension. 1: A system identification device receiving an impulse response of a dynamic system to be identified , the system identification device comprising:a direct feedthrough term identification unit that identifies and outputs a direct feedthrough term of a linear discrete-time system delineating the dynamic system from the impulse response;a block Hankel matrix generator that generates and outputs a block Hankel matrix from the impulse response;a singular value decomposition unit that outputs a first orthogonal matrix, a column vector of which corresponds to a left singular vector of the block Hankel matrix, a second orthogonal matrix, a column vector of which corresponds to a right singular vector of the block Hankel matrix, and a singular value of the block Hankel matrix through singular value decomposition of the block Hankel matrix output from the block Hankel matrix generator;a system dimension determination unit that identifies a system matrix excluding the direct feedthrough term in ...

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Номер записи: 12
08-01-2015 дата публикации

STORING DATA IN A DISTRIBUTED STORAGE NETWORK

Номер: US20150012797A1
Автор: BAPTIST ANDREW, LEGGETTE WESLEY, Resch Jason K.
Принадлежит: CLEVERSAFE, INC.

A method begins by a dispersed storage (DS) processing module mapping a set of data partitions to a set of storage regions. For each data partition, the method continues with the DS processing module segmenting the data partition into a plurality of data segments and designating a first data segment. The method continues with the DS processing module generating data storage mapping information. The method continues with the DS processing module encoding the data storage mapping information to produce at least one set of encoded mapping information slices and for each data partition, encoding the plurality of data segments to produce a plurality of sets of encoded data slices. The method continues with the DS processing module outputting the at least one set of encoded mapping information slices and, for each data partition, the plurality of sets of encoded data slices to the DSN for storage therein. 1. A method for execution by a computing device , the method comprises:determining whether to use sequential data segment storage mapping or non-sequential data segment storage mapping for storage of data based on data read/write probabilities of the data; determining an initial set of storage regions of a distributed storage network (DSN) for storing the data;', 'mapping a set of data partitions to the initial set of storage regions, wherein the data is divided into the set of data partitions;', segmenting the data partition into a plurality of data segments; and', 'designating a first data segment of the plurality of data segments;, 'for each data partition of the set of data partitions, the mapping of the set of data partitions to the initial set of storage regions;', 'the plurality of data segments for each data partition of the set of data partitions; and', 'the first data segment for each data partition of the set of data partitions;, 'generating data storage mapping information regarding at least one of, 'encoding, in accordance with a first dispersed storage ...

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Номер записи: 13
11-01-2018 дата публикации

MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY

Номер: US20180011760A1
Автор: Kanno Shinichi
Принадлежит: Toshiba Memory Corporation

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller manages a plurality of namespaces for storing a plurality of kinds of data having different update frequencies. The controller encodes write data by using first coding for reducing wear of a memory cell to generate first encoded data, and generates second encoded data to be written to the nonvolatile memory by adding an error correction code to the first encoded data. The controller changes the ratio between the first encoded data and the error correction code based on the namespace to which the write data is to be written. 1. (canceled)2. A memory system comprising:a nonvolatile memory; anda controller electrically connected to the nonvolatile memory and configured to:manage a plurality of areas of the nonvolatile memory, the areas including a first area for storing a first type of data and a second area for storing a second type of data having a lower update frequency than the first type of data,encode write data by using first coding for reducing wear of a memory cell to generate first encoded data,generate second encoded data by adding an error correction code to the first encoded data, the second encoded data including the first encoded data and the error correction code, andwrite the second encoded data to one of the first area and the second area, whereinwhen the write data is the first type of the data, the first encoded data has a first length, and the error correction code has a second length, andwhen the write data is the second type of the data, the first encoded data has a third length less than the first length and the error correction code has a fourth length greater than the second length.3. The memory system of claim 2 , wherein the encoding the write data includes converting a first code in the write data into another code longer than the first code.4. The memory system of claim 2 , wherein the controller is configured to compress the write ...

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Номер записи: 14
14-01-2016 дата публикации

RELIABLE DATA READING WITH DATA SET SCREENING BY ERROR INJECTION

Номер: US20160013807A1
Автор: BUI Nhan X., MASUDA Setsuko, Tanaka Keisuke, Tsuruta Kazuhiro
Принадлежит:

According to one embodiment, a method for processing data includes determining whether a PES is invalid while reading data from a magnetic medium using at least one data channel, determining whether a PES value is above a first predetermined threshold when the PES is valid, injecting error bits into a data stream in place of corresponding bits of decoded data when the PES is invalid and/or the PES value is above the first predetermined threshold, decoding the data using a run-length limited (RLL) decoder to produce the decoded data based on the data from the magnetic medium, and outputting the data stream. Other methods, systems, and tape drives for processing data using error injection are described in more embodiments. 1. A system for processing data , the system comprising a controller configured to:determine whether a position error signal (PES) is invalid while reading data from a magnetic medium using at least one data channel;determine whether a PES value is above a first predetermined threshold when the PES is valid; andinject error bits into a data stream in place of corresponding bits of decoded data when the PES is invalid and/or the PES value is above the first predetermined threshold.2. The system as recited in claim 1 , wherein the controller is further configured to:read the data from the magnetic medium using the at least one data channel; andreceive the PES and PES value from a servo channel.3. The system as recited in claim 1 , wherein the controller is further configured to:decode the data using a run-length limited (RLL) decoder to produce the decoded data based on the data from the magnetic medium; andoutput the data stream.4. The system as recited in claim 1 , wherein the controller is further configured to decode the data stream using an error correction code (ECC) decoder to further correct remaining errors in the data stream claim 1 , and wherein validity of the PES is determined periodically while reading the data from the magnetic medium ...

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Номер записи: 15
26-01-2017 дата публикации

MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY

Номер: US20170024276A1
Автор: Kanno Shinichi
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller manages a plurality of namespaces for storing a plurality of kinds of data having different update frequencies. The controller encodes write data by using first coding for reducing wear of a memory cell to generate first encoded data, and generates second encoded data to be written to the nonvolatile memory by adding an error correction code to the first encoded data. The controller changes the ratio between the first encoded data and the error correction code based on the namespace to which the write data is to be written. 1. A memory system comprising:a nonvolatile memory; anda controller electrically connected to the nonvolatile memory and configured to:manage a plurality of namespaces for storing a plurality of kinds of data having different update frequencies;encode write data by using first coding for reducing wear of a memory cell to generate first encoded data;generate second encoded data to be written to the nonvolatile memory by adding an error correction code to the first encoded data; andchange a ratio between the first encoded data and the error correction code based on a namespace to which the write data is to be written.2. The memory system of claim 1 , wherein the plurality of namespaces include a first namespace for storing a first type of data claim 1 , and a second namespace for storing a second type of data having a lower update frequency than the first type of data claim 1 , andthe controller is configured to:control the ratio between the first encoded data and the error correction code such that second encoded data including first encoded data having a first length and an error correction code having a second length is obtained, when an ID of the first namespace is associated with the write data; andcontrol the ratio between the first encoded data and the error correction code such that second encoded data including first encoded data ...

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Номер записи: 16
10-02-2022 дата публикации

TRANSMITTER AND PARITY PERMUTATION METHOD THEREOF

Номер: US20220045695A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups, and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups so that the puncturer selects parity bits included in the some of the bit groups positioned at the predetermined positions sequentially and selects parity bits included in the remainder of the bit groups without an order. 2. The receiving method of claim 1 , wherein the transmitting apparatus encodes 6480 information bits according to the code rate of 6/15 to generate 9720 parity bits.3. The receiving apparatus of claim 1 , wherein the plurality of groups comprise 45 groups including 0to 44groups.5. The transmitting method of claim 4 , wherein the encoding comprises encoding 6480 information bits based on the code rate of 6/15 to generate 9720 parity bits. This application is a continuation of U.S. application Ser. No. 16/390,393, filed on Apr. 22, 2019, which is a continuation of U.S. application Ser. No. 15/058,318, filed on Mar. 2, 2016, which claims priority from Korean Patent Application No. 10-2015-0137185, filed on Sep. 27, 2015, and U.S. Provisional Application No. 62/127,056, filed on Mar. 2, 2015, the disclosures of which are incorporated herein in by reference in their entireties.Apparatuses and methods consistent with the exemplary embodiments of the inventive concept relate to a transmitter and a parity permutation ...

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Номер записи: 17
02-02-2017 дата публикации

INTERFACE ADJUSTMENT PROCESSES FOR A DATA STORAGE DEVICE

Номер: US20170031845A1
Автор: TZAFRIR Yonatan
Принадлежит:

A data storage device includes a controller and a memory die. The controller includes a host interface and a memory interface. A method includes receiving a message from a host device via the host interface. The message indicates that the host device is to perform a first adjustment process associated with the host interface. The method further includes performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process. 1. A method comprising: receiving a message from a host device via the host interface, the message indicating that the host device is to perform a first adjustment process associated with the host interface; and', 'performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process., 'in a data storage device that includes a controller and a memory die, wherein the controller includes a host interface and a memory interface, performing by the controller2. The method of claim 1 , wherein the message includes a command that complies with an embedded MultiMedia Card (eMMC) standard.3. The method of claim 1 , wherein the message includes a command that complies with a Serial Advanced Technology Attachment (SATA) standard.4. The method of claim 1 , wherein the message includes a command that complies with a Universal Serial Bus (USB) standard.5. The method of claim 1 , wherein the second adjustment process includes writing data to a memory of the memory die in response to the message indicating that the host device is to initiate the first adjustment process claim 1 , and wherein the second adjustment process includes reading the data from the memory in response to the message indicating that the host device is to initiate the first adjustment process.6. (canceled)7. The method of claim 5 , further comprising:prior to ...

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Номер записи: 18
02-02-2017 дата публикации

COMMUNICATION DEVICE WITH SELECTIVE ENCODING

Номер: US20170031853A1
Автор: Kalamatianos John, Sadowski Greg
Принадлежит: Advanced Micro Devices, Inc.

A communication device includes a data source that generates data for transmission over a bus, and that further includes a data encoder coupled to receive and encode outgoing data. The encoder further includes a coupling toggle rate (CTR) calculator configured to calculate a CTR for the outgoing data, a threshold calculator configured to determine an expected value of the CTR as a threshold value, a comparator configured to compare the calculated CTR to the threshold value wherein the comparison is used to determine whether to perform an encoding step by an encoding block configured to selectively encode said data. A method according to one embodiment includes determining and comparing a CTR and an expected CTR to determine whether to encode the outgoing data. Any one of a plurality different coding techniques may be used including bus inversion. 1. A communication device , comprising:a data source that generates data for transmission over a bus; and a coupling toggle rate (CTR) calculator configured to calculate a CTR for said data;', 'a threshold calculator configured to determine an expected value of said CTR as a threshold value;', 'a comparator configured to perform a comparison of said CTR to said threshold value to determine whether to perform an encoding step; and', 'an encoding block configured to selectively encode said data based on said comparison., 'a data encoder coupled to receive and encode said data that further includes2. The communication device of wherein said encoding block is configured to perform one or more types of encoding including:bus inversion encoding;out of order transmission encoding;temporal signal encoding;spatial signal encoding;SSB-DDR-CG encoding;bus barrel-shift encoding;pulse position modulation encoding;data transmission array encoding; anddictionary based encoding.3. The communication device of wherein said threshold calculator evaluates charging energy that includes switching energy per wire as well as inter-wire coupling to ...

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Номер записи: 19
05-02-2015 дата публикации

Turbo encoding on a parallel processor

Номер: US20150039961A1
Автор: Dheeraj Sreedhar, Jeffrey Haskell Derby
Принадлежит: International Business Machines Corp

Methods and arrangements for parallelizing turbo encoding computations. At least one processor is provided. turbo encoding computations are split into first and second parts. Using at least one processor, the computations of the first part are performed. Thereafter, using the at least one processor, the computations of the second part are performed, the second part correcting output provided by the computations of the first part. One of the first and second parts comprises computations performed in parallel and the other of the first and second parts comprises computations performed not in parallel. Other variants and embodiments are broadly contemplated herein.

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Номер записи: 20
31-01-2019 дата публикации

INTEGRATED PHYSICAL CODING SUBLAYER AND FORWARD ERROR CORRECTION IN NETWORKING APPLICATIONS

Номер: US20190036645A1
Автор: Basso Claude, SONG Cheng Wei, Verplanken Fabrice Jean
Принадлежит:

Techniques are provided for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer. Data is received at a PCS transmit structure from a MAC sublayer, and one or more alignment markers are inserted in the data. FEC encoding is performed, in a first clock domain, on the one or more alignment markers and the data in the PCS transmit structure to generate FEC encoded data. The FEC encoded data is transmitted from the first clock domain with a first clock cycle to a second clock domain with a second clock cycle, and the FEC encoded data is transmitted on one or more physical medium attachment (PMA) lanes to a PCS receive structure. FEC decoding is performed, in the second clock domain, on the FEC encoded data in the PCS receive structure to generate FEC decoded data. 1. A method comprising:receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer;inserting one or more alignment markers in the data;performing FEC encoding, in a first clock domain, on the one or more alignment markers and the data in the PCS transmit structure to generate FEC encoded data;transmitting the FEC encoded data from the first clock domain with a first clock cycle to a second clock domain with a second clock cycle;transmitting the FEC encoded data on one or more physical medium attachment (PMA) lanes to a PCS receive structure; andperforming FEC decoding, in the second clock domain, on the FEC encoded data in the PCS receive structure to generate FEC decoded data.2. The method of claim 1 , wherein performing the FEC encoding comprises performing Reed-Solomon encoding on the one or more alignment markers and the data.3. The method of claim 1 , wherein performing the FEC decoding comprises performing Reed-Solomon decoding on the FEC encoded data.4. The method of claim 1 , wherein performing the FEC encoding comprises performing the FEC encoding on one or more 66-bit PCS blocks.5. The ...

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Номер записи: 21
31-01-2019 дата публикации

PACKET CODING BASED NETWORK COMMUNICATION

Номер: US20190036650A1
Автор: Ho Tracey, Segui John
Принадлежит: Speedy Packets, Inc.

A method for data communication between a first node and a second node over a data path includes determining one or more redundancy messages from data messages at the first node using an error correcting code and transmitting messages from the first node to the second node. The transmitted messages include the data messages and the redundancy messages. The method includes, receiving, at the first node, messages indicative of a rate of arrival at the second node of the messages transmitted from the first node, and receiving messages indicative of successful and unsuccessful delivery of the messages transmitted from the first node to the second node. A first transmission limit and a second transmission limit are maintained according to the received messages. Transmission of messages from the first node to the second node is inhibited according to the maintained first transmission limit, and according to the second transmission limit. 1. A method for data communication between a first node and a second node over a data path coupling the first node and the second node , the method comprising:determining one or more redundancy messages from data messages at the first node using an error correcting code;transmitting messages from the first node to the second node over the data path, the transmitted messages including the data messages and the one or more redundancy messages; receiving messages indicative of a rate of arrival at the second node of the messages transmitted from the first node, and', 'receiving messages indicative of successful and unsuccessful delivery of the messages transmitted from the first node to the second node;, 'receiving messages at the first node from the second node, including'}maintaining a first transmission limit according to the received messages;maintaining a second transmission limit according to the received messages; and 'limiting transmission of messages according to the maintained first transmission limit, and according to the second ...

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Номер записи: 22
30-01-2020 дата публикации

APPARATUSES AND METHODS FOR PIPELINING MEMORY OPERATIONS WITH ERROR CORRECTION CODING

Номер: US20200036396A1
Автор: Fan Yu Peng, Gao En Peng, Li Hong Wen, Liu Zhong Lai, Shang Wei Bing, Zhang Liang, Zhang Yu
Принадлежит: MICRON TECHNOLOGY, INC.

Apparatuses and methods for pipelining memory operations with error correction coding are disclosed. A method for pipelining consecutive write mask operations is disclosed wherein a second read operation of a second write mask operation occurs during error correction code calculation of a first write mask operation. The method may further including writing data from the first write mask operation during the error correction code calculation of the second write mask operation. A method for pipelining consecutive operations is disclosed where a first read operation may be cancelled if the first operation is not a write mask operation. An apparatus including a memory having separate global read and write input-output lines is disclosed. 1. An apparatus comprising:a memory array including a plurality of memory cells;a write driver coupled to the memory array by a global write I/O line, wherein the write driver is configured to provide data to the plurality of memory cells;a data sense amplifier coupled to the memory array by a global read I/O line, wherein the data sense amplifier is configured to receive data stored in the plurality of memory cells;an error control code circuit coupled to the write driver by a local write data line and further coupled to the data sense amplifier by a local read data line, wherein the error control code circuit is configured to receive data from a global write data line and send data via a global read data line; anda control circuit configured to provide control signals to the memory array, write driver, data sense amplifier, and error control circuit, wherein the control circuit is further configured to detect two consecutive write mask operations and pipeline execution of the two consecutive write mask operations, wherein a second write mask operation of the two consecutive write mask operations begins execution before a first write mask operation of the two consecutive write mask operations completes execution.2. The apparatus of ...

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Номер записи: 23
12-02-2015 дата публикации

ENCODING METHOD AND SYSTEM FOR QUASI-CYCLIC LOW-DENSITY PARITY-CHECK CODE

Номер: US20150046768A1
Автор: Hu Junqiang, Wang Ting
Принадлежит:

A method and system are provided. The method includes applying a quasi-cyclic matrix M to an input vector X of encoded data to generate a vector Y. The method further includes applying a matrix Q to the vector Y to generate a vector Z. The method also includes recursively generating, using a processor, parity check bits P for the encoded data from the vector Z and an identity matrix variant I. The encoded data includes quasi-cyclic low-density parity-check code. The identity matrix variant t is composed of Toeplitz sub-matrices. 1. A method , comprising:applying a quasi-cyclic matrix M to an input vector X of encoded data to generate a vector Y;applying a matrix Q to the vector Y to generate a vector Z; andrecursively generating, using a processor, parity check bits P for the encoded data from the vector Z and an identity matrix variant I*,wherein the encoded data comprises quasi-cyclic low-density parity-check code, and the identity matrix variant I* is composed of Toeplitz matrices.2. The method of claim 1 , further comprising combining the encoded data with the parity check bits to form one or more encoded output signals.3. The method of claim 1 , wherein said applying steps are performed using feedback shift registers.4. The method of claim 1 , further comprising receiving a parity check matrix H of quasi-cyclic low-density parity-check code claim 1 , wherein a rank r of the parity check matrix H is less than a number of rows of the parity check matrix H claim 1 , and wherein the quasi-cyclic matrix M is a subset of the parity check matrix H claim 1 , generated by removing at least some circulants from the parity check matrix H7. The method of claim 4 , further comprising generating a matrix D from the at least some circulants removed from the parity check matrix H claim 4 , wherein the at least some circulants that are removed from the parity check matrix H are determined for removal by finding a least number of columns of circulants in the parity check matrix ...

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Номер записи: 24
01-05-2014 дата публикации

Method and apparatus for umbrella coding

Номер: US20140122976A1
Автор: Chung-Jue Chen, Hongtao Jiang, Zhongfeng Wang
Принадлежит: Broadcom Corp

A communication system and a method are disclosed. The communication system includes an encoder configured to encode source data and output an encoded frame including a mother code or a plurality of concatenated daughter codes based on an encoding option. The mother code and the plurality of concatenated daughter codes have a same number of coded data symbols. The mother code includes a first source number of source symbols and a first parity number of parity symbols. The daughter code includes fewer source symbols and fewer parity symbols than the mother code.

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Номер записи: 25
07-02-2019 дата публикации

DYNAMIC RELIABILITY LEVELS FOR STORAGE DEVICES

Номер: US20190044536A1
Автор: KHAN Jawad B., Tickoo Omesh, Trika Sanjeev N., Wu Wei
Принадлежит:

To address the storage needs of applications that work with noisy data (e.g. image, sound, video data), where errors can be tolerated to a certain extent and performance is more critical than data fidelity, dynamic reliability levels enable storage devices capable of storing and retrieving data with varying degrees of data fidelity to dynamically change the degree of data fidelity in response to an application's request specifying reliability level. By allowing the application to specify the reliability level at which its data is stored and retrieved, dynamic reliability levels can increase read/write performance without sacrificing application accuracy. The application can specify reliability levels for different types or units of data, such as different reliability levels for metadata as opposed to data and so forth. 1. An apparatus comprising:a storage controller to control a storage device at which data can be stored and retrieved with varying degrees of data fidelity; andan interface between the storage controller and a host in communication with the storage controller, the interface exposing two or more reliability levels corresponding to two or more of the varying degrees of data fidelity, wherein, responsive to receipt of a request from the host for any one of storing and retrieving data at a specified reliability level, the interface causes the storage controller to:convert the host-specified reliability level to a corresponding degree of data fidelity at which the host's data can be stored and retrieved,command the storage device to satisfy the request at the corresponding degree of data fidelity to which the host-specified reliability level was converted, andreturn a status of the request to the host, the status indicating whether the storage device satisfied the request at the host-specified reliability level.2. The apparatus of claim 1 , wherein the interface exposing two or more reliability levels corresponding to two or more of the varying degrees of ...

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Номер записи: 26
16-02-2017 дата публикации

Systems and methods of memory bit flip identification for debugging and power management

Номер: US20170046218A1
Автор: Alan Young, Chinh Tran, LI ZHANG, Madan Krishnappa, William Bainbridge
Принадлежит: Qualcomm Inc

Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.

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Номер записи: 27
16-02-2017 дата публикации

SYSTEMS AND METHODS OF MEMORY BIT FLIP IDENTIFICATION FOR DEBUGGING AND POWER MANAGEMENT

Номер: US20170046219A1
Автор: BAINBRIDGE WILLIAM, KRISHNAPPA MADAN, Rychlik Bohuslav, TRAN CHINH, YOUNG ALAN, Zhang Li
Принадлежит:

Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences. 1. A method for power management in a system on a chip (“SoC”) , the method comprising:monitoring one or more parameters of the SoC that are associated with bit flips;calculating baseline parity values for data blocks of bits queued to be written to bit cell arrays of the memory component and assigning the baseline parity values to parity bits uniquely associated with the data blocks;writing the data blocks to the bit cell arrays and a buffer of the memory component;for each data block as it is written to the buffer, calculating a write-side parity value;for each data block, comparing its baseline parity value to its write-side parity value;for each data block, if the baseline parity value differs from the write-side parity value, recording the occurrence of a bit flip;based on determining that a rate of bit flip occurrences has exceeded a threshold, adjusting a thermal and power management policy associated with one or more component of the SoC.2. The method of claim 1 , wherein adjusting the thermal and power management policy comprises modifying a temperature threshold associated with a thermally aggressive component collocated on the SoC with the memory component.3. The method of claim 1 , ...

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Номер записи: 28
15-02-2018 дата публикации

DEVICE AND ASSOCIATED METHODOLOY FOR ENCODING AND DECODING OF DATA FOR AN ERASURE CODE

Номер: US20180048333A1
Автор: Nilsson Thomas
Принадлежит: Zebware AB

A method of redundantly encoding data includes formatting the data into columns and rows, and generating first and second sets of projections of the data using an encoding transform. For each set of projections generated, an encoding parameter of the encoding transform is set to a different value. The first and second sets of projections are stored as the encoded data. A decoding method reads settings including an indication of a number of data fragments. The number of data fragments is compared to a number of projections in a first set of projections of the encoded data in order to determine whether to use a first or a second decoding mode. The encoded data is then decoded according to the selected decoding mode and the result is outputted. 1. A method of redundantly encoding data , comprising:receiving, by circuitry, data to be encoded;formatting, by the circuitry, the data into rows and columns;generating, by the circuitry, a first set of projections based on an encoding transform using a first parameter value for an encoding parameter of the encoding transform;generating, by the circuitry, a second set of projections based on the encoding transform using a second parameter value for the encoding parameter that is different from the first parameter value; andstoring the first and second sets of projections as encoded data corresponding to the data received.2. The method of claim 1 , wherein the formatting step includes formatting the data into rows and columns according configuration parameters indicating at least a number of data chunks (k) and a number of parity chunks (m).3. The method of claim 2 , further comprising generating an aligned parity projection package based on the number of parity chunks (m) claim 2 , the aligned parity projection package being stored with the encoded data to allow for multiple pixel solutions per iteration during decoding of the encoded data.4. The method of claim 1 , wherein the encoding transform includes a Mojette Transform ...

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Номер записи: 29
14-02-2019 дата публикации

Interface adjustment processes for a data storage device

Номер: US20190050022A1
Автор: Yonatan Tzafrir
Принадлежит: SanDisk Technologies LLC

A data storage device includes a controller and a memory die. The controller includes a host interface and a memory interface. A method includes receiving a message from a host device via the host interface. The message indicates that the host device is to perform a first adjustment process associated with the host interface. The method further includes performing a second adjustment process associated with the memory interface in response to receiving the message indicating that the host device is to perform the first adjustment process.

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Номер записи: 30
14-02-2019 дата публикации

LARGE OBJECT PARALLEL WRITING

Номер: US20190050292A1
Автор: Gray Adam M., Leggette Wesley B., Resch Jason K.
Принадлежит:

A method includes partitioning a data object into a plurality of data partitions. The method further includes dispersed storage error encoding a first data partition of the plurality of data partitions into a first plurality of sets of encoded data slices. The method further includes generating a first segment allocation table (SAT) regarding storage of the first plurality of sets of encoded data slices in a first set of storage units of the DSN. The method further includes dispersed storage error encoding the first SAT to produce a first set of SAT slices. The method further includes sending the first plurality of sets of encoded data slices and the first set of SAT slices to the first set of storage units. The method further includes updating a directory with information regarding the first SAT. 1. A method comprises:partitioning, by a computing device of a dispersed storage network (DSN), a data object into a plurality of data partitions;dispersed storage error encoding, by the computing device, a first data partition of the plurality of data partitions into a first plurality of sets of encoded data slices;generating, by the computing device, a first segment allocation table (SAT) regarding storage of the first plurality of sets of encoded data slices in a first set of storage units of the DSN;dispersed storage error encoding, by the computing device, the first SAT to produce a first set of SAT slices;sending, by the computing device, the first plurality of sets of encoded data slices and the first set of SAT slices to the first set of storage units; andupdating, by the computing device, a directory with information regarding the first SAT.2. The method of further comprises: a data object attribute;', 'a partitioning scheme lookup; and', 'receiving the partitioning scheme., 'determining, by the computing device, to partition the data object based on one of3. The method of claim 1 , wherein the first SAT comprises:a start segment vault source name entry indicating ...

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Номер записи: 31
03-03-2022 дата публикации

FORWARD ERROR CORRECTION USING NON-BINARY LOW DENSITY PARITY CHECK CODES

Номер: US20220069844A1
Автор: Abrams Stuart, Hadani Ronny, Namboodiri Vamadevan
Принадлежит:

Methods, systems and devices for forward error correction in orthogonal time frequency space (OTFS) communication systems using non-binary low-density parity-check (NB-LDPC) codes are described. One exemplary method for forward error correction includes receiving data, encoding the data via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, modulating the encoded data to generate a signal, and transmitting the signal. Another exemplary method for forward error correction includes receiving a signal, demodulating the received signal to produce data, decoding the data via a NB-LDPC code, wherein the NB-LDPC code is characterized by a matrix with binary and non-binary entries, and providing the decoded data to a data sink. 1. An apparatus for forward error correction , comprising:a processor-implemented encoder configured to encode information bits via a non-binary low density parity check (NB-LDPC) code, wherein the NB-LDPC code is formulated as a matrix with binary and non-binary entries;a modulator configured to modulate, using an orthogonal time frequency space (OTFS) modulation scheme, the encoded information bits to generate a signal; anda transmitter configured to transmit the signal over a channel,wherein a parity matrix H for the NB-LDPC code is based on a binary H matrix, and 'add offsets to entries in a first column and entries in a first row of the binary H matrix such that the first column and the first row contain only identity elements.', 'wherein the binary H matrix is based on a computer search algorithm configured to2. The apparatus of claim 1 , wherein the computer search algorithm is configured to terminate upon a determination that no N-cycles are present in a Tanner graph representation of the binary H matrix claim 1 , and wherein N=4 or N=6.3. The apparatus of claim 1 , wherein the parity check matrix H is represented a H=[H claim 1 , H] claim 1 , where ...

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Номер записи: 32
23-02-2017 дата публикации

DETECTING STORAGE ERRORS IN A DISPERSED STORAGE NETWORK

Номер: US20170052843A1
Автор: Kazi Asimuddin, Resch Jason K.
Принадлежит:

A method includes determining a root cause for a rebuilding request of an encoded data slice of a set of encoded data slices, where the rebuilding request includes a slice name of the encoded data slice corresponding to a slice error. The method further includes establishing a pricing level as a user pricing level when the root cause is a user-centric root cause, and establishing the pricing level as a non-user pricing level when the root cause is a non-user-centric root cause. The method further includes facilitating the rebuilding of the encoded data slice, and generating billing information for the rebuilding based on the pricing level. 1. A method for execution by one or more computing devices of a dispersed storage network (DSN) , the method comprises:determining a root cause for a rebuilding request of an encoded data slice of a set of encoded data slices, wherein the rebuilding request includes a slice name of the encoded data slice corresponding to a slice error;establishing a pricing level as a user pricing level when the root cause is a user-centric root cause;establishing the pricing level as a non-user pricing level when the root cause is a non-user-centric root cause;facilitating the rebuilding of the encoded data slice; andgenerating billing information for the rebuilding based on the pricing level.2. The method of claim 1 , wherein the determining the root cause for the rebuilding request is based on one or more of:an error message;an event log;a query; anda test.3. The method of claim 1 , wherein the slice error comprises at least one of:an indication that the encoded data slice is missing; andan indication that the encoded data slice is associated with an unfavorable integrity value.4. The method of claim 1 , wherein determining that the root cause is the user-centric root cause comprises at least one of:detecting that the encoded data slice is not written in DSN memory;detecting that the encoded data slice was not successfully committed in a write ...

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Номер записи: 33
23-02-2017 дата публикации

FLASH MEMORY CODEWORD ARCHITECTURES

Номер: US20170052844A1
Автор: Camp Charles J., FISHER TIMOTHY J., FRY AARON D., SIMMONS LINCOLN T., Yanes Adalberto G.
Принадлежит:

A flash memory codeword architecture is provided. A non-integer count of logical pages is packed into a codeword payload data container. A codeword payload header is generated. The codeword payload header includes an offset to a first logical page that is packed, at least in part, into the codeword payload data container. The codeword payload data container and the codeword payload header are concatenated to generate a codeword payload. Error-correcting code data is generated based, at least in part, on the codeword payload using a systematic error-correcting code. The codeword payload and error-correcting code data is concatenated to generate a codeword. A physical page is programmed with the codeword. 1. A method for programming flash memory , the method comprising:packing, by one or more storage controllers, a non-integer count of logical pages into a codeword payload data container;generating, by one or more storage controllers, a codeword payload header that includes an offset to a first logical page packed, at least in part, into the codeword payload data container;concatenating, by one or more storage controllers, the codeword payload data container and the codeword payload header to generate a codeword payload;generating, by one or more storage controllers, error-correcting code data based, at least in part, on the codeword payload using a systematic error-correcting code;concatenating, by one or more storage controllers, the codeword payload and error-correcting code data to generate a codeword; andprogramming, by one or more storage controllers, a physical page with the codeword.2. The method of claim 1 , wherein a size of the codeword payload data container is greater than a size of the first logical page claim 1 , and wherein the first logical page does not straddle boundaries of the codeword payload data container.3. The method of claim 2 , wherein the non-integer count of logical pages packed into the codeword payload data container includes a first ...

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Номер записи: 34
13-02-2020 дата публикации

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

Номер: US20200052715A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, LOBETE Daniel Ansorregui, MOUHOUCHE Belkacem, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The receiving apparatus as claimed in claim 1 , wherein the decoder is configured to decode the deinterleaved values based on the LDPC code having a code rate of 4/15.3. The receiving apparatus as claimed in claim 1 , wherein the constellation points in the table comprise constellation points in one quadrant claim 1 , andwherein constellation points in remaining quadrants are obtained by indicating each constellation point a of the constellation points in the table as a*, −a*, and −a, respectively, * indicating complex conjugation. This is a Continuation of U.S. application Ser. No. 15/412,991 filed Jan. 23, 2017, which is a Continuation of U.S. application Ser. No. 14/715,780 filed May 19, 2015 in the United States Patent and Trademark Office, the disclosure of which is incorporated herein by reference in its entirety.Apparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.The current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) ...

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Номер записи: 35
03-03-2016 дата публикации

MEMORY DEVICE AND MEMORY SYSTEM WITH SENSOR

Номер: US20160062825A1
Автор: SHIRATAKE Shinichiro
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to one embodiment, a memory device includes a first address memory storing a first address; a controller which is based on a first interface which transmits a signal serially and outputs a first command in accordance with the first interface; and a memory which stores data in a nonvolatile manner, is based on the first interface, and stores received write data in an address based on the first address when the memory receives the first command. 1. A memory device comprising:memory cells which store data in a nonvolatile manner; receives write data,', 'uses the write data and a first matrix to execute an operation to generate parity,', 'receives read data and parity based on from the read data,', 'uses the read data, the parity based on the read data and a second matrix to generate a syndrome,', 'uses the syndrome to correct an error of the read data,', 'wherein the second matrix includes the first matrix and a unit matrix, and', 'the first matrix comprises components selected such that an XOR of any two columns of the second matrix is different from an XOR of any other two columns and any column of the second matrix; and, 'an error correction circuit whicha controller which writes the write data and the parity based on the write data in memory cells, and supplies the read data and the parity based on the read data from memory cells to the error corrections circuit.2. The device of claim 1 , wherein:the first matrix comprises components in eight rows and eight columns, andthe second matrix comprises components in eight rows and sixteen columns.3. The device of claim 2 , wherein:the write data comprises components in eight rows and one column, andthe error correction circuit multiplies the first matrix and the write data to generate parity of eight rows and one column.4. The device of claim 2 , wherein:the second matrix comprises the first matrix in first to eighth columns and a unit matrix in ninth to sixteenth columns,the read data comprises components in ...

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Номер записи: 36
03-03-2016 дата публикации

RADIATION HARDENING ARCHITECTURAL EXTENSIONS FOR A RADIATION HARDENED BY DESIGN MICROPROCESSOR

Номер: US20160065243A1
Автор: Clark Lawrence T., Patterson Dan Wheeler
Принадлежит: Arizona Board of Regents on behalf of Arizona State University

This disclosure relates generally to processors and methods of operating the same. In particular, this disclosure relates to components for correcting soft errors in a processor. In one embodiment, a processor includes an instruction decoder and an exception handler. The instruction decoder is configured to receive one or more soft error correction instructions and decode the one or more soft error correction instructions. Additionally, an exception handler is configured to execute the one or more soft error correction instructions so as to correct one or more soft errors. In this manner, the processor is capable of correcting soft errors that are the result of radiation strikes. 1. A processor , comprising:an instruction decoder configured to receive one or more soft error correction instructions and decode the one or more soft error correction instructions; andan exception handler configured to execute the one or more soft error correction instructions so as to correct one or more soft errors.2. The processor of wherein the exception handler is configured to execute the one or more soft error correction instructions by implementing software to perform the one or more soft error correction instructions.3. The processor of further comprising a register file and wherein the one or more soft error correction instructions comprise an instruction to restore the register file to a previous state.4. The processor of wherein the previous state is prior to a last instruction retirement.5. The processor of further comprising a dual mode redundant (DMR) register file wherein the one or more software error instructions comprise an instruction to copy data from an uncorrupted instance of the DMR register file to a corrupted instance of the DMR register file.6. The processor of further comprising a dual mode redundant (DMR) structures wherein the one or more soft error correction instructions comprise a read instruction for reading a specific instance of the DMR structures.7. ...

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Номер записи: 37
03-03-2016 дата публикации

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

Номер: US20160065244A1
Автор: Hirayama Yuichi, Michael Lachlan, MUHAMMAD Nabil Sven Loghin, Shinohara Yuji, Yamamoto Makiko
Принадлежит: SONY CORPORATION

In a transmitting device, in interchanging to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a bit b, a bit b, and a bit b are interchanged with a bit y, a bit y, and a bit y, respectively. A position of the interchanged code bit obtained from data transmitted from the transmitting device is returned to an original position. The present technology is applicable to a case of transmitting data using an LDPC code, for example. 130-. (canceled)31. A data processing device comprising:a reverse interchanging unit configured to perform reverse interchange processing for returning a position of an interchanged code bit obtained from data transmitted from a transmitting device to an original position; and an encoding unit configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15, and', 'an interchanging unit configured to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK,, 'a decoding unit configured to decode an LDPC code obtained by the reverse interchange processing, the transmitting device including'}wherein, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and the interchanging unit interchanges{'b': 0', ...

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Номер записи: 38
03-03-2016 дата публикации

MULTIPLE INPUT MULTIPLE OUTPUT COMMUNICATIONS OVER NONLINEAR CHANNELS USING ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING

Номер: US20160065275A1
Автор: Benjo Shimon, Eliaz Amir, Oren Roy, Reuven Ilan, STOPLER Daniel
Принадлежит:

An OFDM receiver comprises a (FEC) decoder and a nonlinearity compensation circuit. The nonlinearity compensation circuit is operable to generate estimates of constellation points transmitted on each of a plurality of subcarriers of a received signal based on soft decisions from the FEC decoder and based on a model of nonlinear distortion introduced by a transmitter from which the received signal was received. The generation of the estimates may be based on a measure of distance between a function of the received signal and a synthesized version of the received signal. The generation of the estimates may comprise iterative processing of symbols of the received signal, and the iterative processing may comprise a plurality of outer iterations and a plurality of inner iterations. 1. A System comprising: [ each of said bins corresponds to a respective one of a plurality of subcarrier and spatial stream combinations; and', 'said estimates are generated based on decoded soft bit decisions generated by said SISO FEC decoder during a previous iteration;, 'said nonlinearity compensation circuit is operable to generate estimates of constellation points transmitted on each of a plurality of bins of a received signal, wherein, 'said SISO FEC decoder is operable to generate soft bit decisions generated from said estimates to generate decoded soft bit decisions for said particular iteration., 'an orthogonal frequency division multiplexing (OFDM) receiver comprising a nonlinearity compensation circuit and a soft-input-soft-output (SISO) forward error correction (FEC) decoder which are operated iteratively, wherein for a particular iteration2. The system of claim 1 , comprising a demapper operable to:generate said soft bit decisions from estimates of said bins; andoutput said generated soft bit decisions for decoding by said SISO FEC decoder.3. The system of claim 1 , comprising a multiple-input-multiple-output (MIMO) equalizer and decoder.4. The system of claim 3 , wherein said ...

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Номер записи: 39
05-03-2015 дата публикации

DECODER FOR LOW-DENSITY PARITY-CHECK CODES

Номер: US20150067440A1
Автор: Anderson Adrian John, Owen Christopher
Принадлежит:

Methods and apparatus for decoding LDPC codes are described. An LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. In an embodiment, a configurable LDPC decoder, which supports many different LDPC codes having any sub-matrix size, comprises several independently addressable memories which are used to store soft decision data for each bit node. The decoder further comprises a number, P, of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is P(where P≧P) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than P*q bits. 1. A configurable LDPC decoder arranged to support multiple different LDPC code structures having any sub-matrix size , comprising:a plurality of independently addressable memories arranged collectively to store soft decision data for each bit node for use in decoding an LDPC code, each memory having a width comprising an amount of data accessible from the memory in a single cycle;a plurality of check node processing systems arranged to operate in parallel and generate updates to the soft decision data;a first shuffling system arranged to pass data from the plurality of independently addressable memories to the plurality of check node processing systems; anda second shuffling system arranged to pass the updates to the soft decision data from the plurality of check node processing systems to the plurality of independently addressable memories,wherein a total width of the plurality of independently addressable memories is larger than a product of a number of check nodes processed in parallel by the check node processing systems and a width of the soft decision data for a bit node.2. A configurable LDPC decoder according to ...

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Номер записи: 40
10-03-2016 дата публикации

MEMORY SYSTEM

Номер: US20160071607A1
Автор: Kanno Shinichi
Принадлежит:

According to one embodiment, a memory system includes a memory and a setting unit. The memory includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory cells, each of which holds an electrical charge. The peripheral circuit is configured to read a value from each memory cell by comparing a quantity of an electrical charge held in the memory cell with a determination threshold. The memory stores first data in the memory cell array. The first data include a plurality of values. The setting unit is configured to change the determination threshold according to the number of values which are different in second data and third data among the plurality of values. The second data are first data before being written to the memory. The third data are first data that have been read from the memory. 1. A memory system comprising:a memory that includes a memory cell array including a plurality of memory cells, each of which holds an electrical charge, and includes a peripheral circuit configured to read a value from each memory cell by comparing a quantity of an electrical charge held in the memory cell with a determination threshold, the memory storing first data in the memory cell array, the first data including a plurality of values; anda setting unit configured to change the determination threshold according to the number of values which are different in second data and third data among the plurality of values, the second data being first data before being written to the memory, and the third data being first data that have been read from the memory.2. The memory system according to claim 1 , wherein the setting unit increases the amount of change of the determination threshold as the number of the values is larger.3. The memory system according to claim 2 , whereinthe peripheral circuit determines whether a quantity of an electrical charge held in each memory cell indicates a first value or indicates a second value, andthe ...

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Номер записи: 41
08-03-2018 дата публикации

INCREMENTAL ERROR DETECTION AND CORRECTION FOR MEMORIES

Номер: US20180069573A1
Автор: SHEPARD Daniel R.
Принадлежит:

A device and method for incrementally updating the error detecting and correcting bits for an error corrected block of data in a cross point memory array is disclosed. When an error corrected block of data is modified, only the modified data bits and the incrementally updated error detecting and correcting bits are changed in the cross point memory device for improved performant and reduced impact to device endurance. 1. A method of error correction in a cross point memory device having a data block arranged in a rectangular pattern , comprising:determining that a number in an individual storage location is incorrect;subtracting the incorrect individual number from the from the data block; andinserting a new number into the data block from which the incorrect individual number has been removed.2. The method of claim 1 , further comprising:calculating a difference between the incorrect number in the individual storage location and the new number.3. The method of claim 2 , further comprising:calculating error detecting numbers, wherein the calculating occurs prior to determining that a number in an individual storage location is incorrect; andcalculating correcting parity numbers, wherein the calculating occurs prior to determining that a number in an individual storage location is incorrect.4. The method of claim 3 , further comprising:calculating new error detecting numbers, wherein the calculating occurs after inserting the new number; andcalculating new correcting parity numbers, wherein the calculating occurs after inserting the new number.5. The method of claim 2 , further comprising:calculating a difference between the incorrect number and the new number; andadding the difference between the incorrect number and the new number to the error detecting numbers and the correcting parity numbers.6. The method of claim 2 , wherein the data block is a nine-number data block.7. The method of claim 1 , further comprising:calculating error detecting numbers, wherein the ...

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Номер записи: 42
28-02-2019 дата публикации

DATA STORAGE DEVICE ENCODING AND INTERLEAVING CODEWORDS TO IMPROVE TRELLIS SEQUENCE DETECTION

Номер: US20190068221A1
Автор: Chen Yiming
Принадлежит:

A data storage device is disclosed comprising a storage medium. First data is encoded into a first codeword comprising a plurality of i-bit symbols, and second data is encoded into a second codeword comprising a plurality of j-bit symbols, wherein i is different than j and a first code rate of the first codeword is less than a second code rate of the second codeword. The first codeword and the second codeword are symbol interleaved to generate an interleaved codeword, and the interleaved codeword is written to the storage medium. 124-. (canceled)25. A controller for use in a data storage device , comprising:a communication interface configured to communicate data with a storage medium of a data storage device; and encode first data into a first codeword comprising a plurality of i-bit symbols;', 'encode second data into a second codeword comprising a plurality of j-bit symbols, wherein i is different than j and wherein a first code rate of the first codeword is less than a second code rate of the second codeword;', 'interleave the first codeword and the second codeword to generate an interleaved codeword; and', 'control the communication interface to write the interleaved codeword to the storage medium., 'a processor in data communication with the communication interface and configured to26. The controller as recited in claim 25 , wherein i is less than j.27. The controller as recited in claim 26 , wherein i is 1.28. The controller as recited in claim 25 , wherein the processor is further configured to:read the interleaved codeword from the storage medium to generate a read signal;sample the read signal to generate signal samples;process the signal samples with a trellis detector to generate a sequence of reliability metrics representing the interleaved codeword;de-interleave the sequence of reliability metrics into a first set of reliability metrics representing the first codeword and a second set of reliability metrics representing the second codeword;decode the ...

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Номер записи: 43
28-02-2019 дата публикации

Method and Apparatus for Encoding Data Using a Polar Code

Номер: US20190068316A1
Автор: Cheng Nan, GE YIQUN, LI Rong, LIU Xiaocheng, Tong Jiajie, Tong Wen, WANG Jian, Wang Jun, ZHANG Gongzheng, ZHANG Huazi, Zhang Qifan
Принадлежит:

Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes polar encoding, with an encoder of the device, information bits and at least one parity bit using the polar code to obtain encoded data, and transmitting the encoded data to another device. The polar code comprises a plurality of sub-channels. The at least one parity bit being placed in at least one of the plurality of sub-channels. The at least one sub-channel is selected from the plurality of sub-channels based on a weight parameter. 1. A method for a device for encoding data with a polar code , the method comprising:polar encoding, with an encoder of the device, information bits and at least one parity bit using the polar code to obtain encoded data, the polar code comprising a plurality of sub-channels, and the at least one parity bit being placed in at least one of the plurality of sub-channels, wherein the at least one sub-channel is selected from the plurality of sub-channels based on a weight parameter; andtransmitting the encoded data to another device.2. The method of claim 1 , wherein the weight parameter comprises a minimal weight.3. The method of claim 2 , wherein the plurality of sub-channels are ordered based on a reliability metric claim 2 , and wherein the at least one sub-channel is selected from a subset of the plurality of ordered sub-channels based on the minimal weight.4. The method of claim 3 , wherein the subset of the plurality of ordered sub-channels comprises K sub-channels claim 3 , where K is an information block length.5. The method of claim 4 , wherein the at least one sub-channel is selected from the subset of K sub-channels such that:if a number of sub-channels selected based on the minimal weight from the subset of K sub-channels is greater than a predetermined value F, F sub-channels are selected based on the minimal weight and in a descending order of the reliability metric from the subset of K sub- ...

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Номер записи: 44
27-02-2020 дата публикации

Polar code encoding and decoding method and apparatus

Номер: US20200067531A1
Автор: Gongzheng ZHANG, Hejia LUO, Jun Wang, Lingchen HUANG, Rong Li, YING Chen, Yunfei Qiao
Принадлежит: Huawei Technologies Co Ltd

Embodiments of this application provide a polar code encoding and decoding method and apparatus. The method includes: obtaining an information bit set from a polar code construction sequence table based on an information bit length and a target code length of to-be-encoded information, where the polar code construction sequence table stores a mapping relationship between an encoding parameter and a construction sequence corresponding to the encoding parameter, the construction sequence is a sequence representing an order of reliability of polarized channels, and the encoding parameter includes at least one of an aggregation level, the target code length, and a mother code length, or the encoding parameter is a maximum mother code length; and performing polarization encoding on the to-be-encoded information based on the to-be-encoded information and the information bit set.

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Номер записи: 45
27-02-2020 дата публикации

ERROR CORRECTION DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME

Номер: US20200067538A1
Автор: JO Myung Jin, KANG Soon Young, Kim Dae Sung, SUNG Wan Je
Принадлежит:

An error correction device includes: a plurality of variable node units each configured to: receive a hard decision bit and a channel reliability value having a first bit-precision; and perform an iteration of a decoding operation on the hard decision bit based on the channel reliability value; a plurality of check node units each configured to: receive one or more reference reliability values having a second bit-precision from one or more variable node units coupled thereto among the plurality of variable node units during the iteration; and transmit, based on the one or more reference reliability values, one or more check reliability values having the second bit-precision to the one or more variable node units coupled thereto, wherein, during the iteration, each of the plurality of variable node units further: receives one or more first check reliability values from one or more check node units coupled thereto among the plurality of check node units; and updates the hard decision bit with reference to the channel reliability value and the one or more first check reliability values by upsizing the first bit-precision of the channel reliability value and the second bit-precision of the one or more first check reliability values. 1. An error correction device comprising:a plurality of variable node units each configured to:receive a hard decision bit and a channel reliability value having a first bit-precision; andperform an iteration of a decoding operation on the hard decision bit based on the channel reliability value;a plurality of check node units each configured to:receive one or more reference reliability values having a second bit-precision from one or more variable node units coupled thereto among the plurality of variable node units during the iteration; andtransmit, based on the one or more reference reliability values, one or more check reliability values having the second bit-precision to the one or more variable node units coupled thereto,wherein, ...

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Номер записи: 46
27-02-2020 дата публикации

CODER AND DECODER USING A QUASI-CYCLIC SEMI-REGULAR LDPC CODE OF SHORT LENGTH FOR LOW CONSUMPTION APPLICATIONS SUCH AS REMOTE READING

Номер: US20200067636A1
Автор: DORNSTETTER Jean-Louis
Принадлежит:

An LDPC (Low-Density Parity Check) code based on a control matrix represented by a Tanner bipartite graph includes 128 variable nodes of the graph and 64 constraint nodes of the graph, the code being wherein each of the constraint nodes of the graph is connected to 7 variable nodes of the graph; each of the cycles of the graph has a length greater than or equal to 6; the minimum distance of the code is equal to or greater than a predefined threshold for minimum distance. 2. The LDPC encoder as claimed in claim 1 , in which said Tanner bipartite graph comprises claim 1 , for each link between a variable node of the protograph and a constraint node of the protograph claim 1 , 16 links between a variable node of the graph and a constraint node of the graph claim 1 , said 16 links being defined by a circular permutation according to an order in the range between 0 and 15.4. The LDPC encoder as claimed in claim 1 , wherein said Tanner bipartite graph comprises a number of cycles of length equal to 6 of less than 640.5. The LDPC encoder as claimed in claim 1 , wherein the code has an error rate at the decoding of less than 50% claim 1 , for a transmission with a signal-to-noise ratio of −1.17 dB.6. The LDPC encoder as claimed in claim 1 , configured for encoding a frame of data comprising remote reading data for water claim 1 , gas or electricity.7. A transmitter configured for transmitting frames of data comprising remote reading data for water claim 1 , gas or electricity claim 1 , encoded by an LDPC encoder as claimed in .9. The LDPC decoder as claimed in claim 8 , in which said Tanner bipartite graph comprises claim 8 , for each link between a variable node of the protograph and a constraint node of the protograph claim 8 , 16 links between a variable node of the graph and a constraint node of the graph claim 8 , said 16 links being defined by a circular permutation according to an order in the range between 0 and 15.11. The LDPC decoder as claimed in claim 8 , ...

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Номер записи: 47
19-03-2015 дата публикации

TRANSMITTING APPARATUS, AND PUNCTURING METHOD THEREOF

Номер: US20150082113A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

There is provided a transmitting apparatus. The transmitting apparatus includes an encoder configured to perform Low Density Parity Check (LDPC) encoding with respect to input data, based on a parity check matrix, a parity interleaver configured to interleave parity bits from among LDPC codewords generated by the LDPC encoding, and a puncturer configured to puncture at least a part of the interleaved parity bits, and the puncturer groups the parity bits based on an interval at which a pattern of columns is repeated in an information word sub matrix constituting the parity check matrix and perform puncturing based on the number of punctured parity bits and a position of punctured parity bit groups from among the grouped parity bit groups. 1. A transmitting apparatus comprising:an encoder configured to perform Low Density Parity Check (LDPC) encoding with respect to input data, based on a parity check matrix;a parity interleaver configured to interleave parity bits from among LDPC codewords generated by the LDPC encoding; anda puncturer configured to puncture at least a part of the interleaved parity bits,wherein the puncturer groups the parity bits based on an interval at which a pattern of columns is repeated in an information word sub matrix constituting the parity check matrix and perform puncturing based on the number of punctured parity bits and a position of punctured parity bit groups from among the grouped parity bit groups.2. The apparatus as claimed in claim 1 , wherein the puncturer determines a position of the punctured parity bit groups based on a predefined puncturing pattern and the number of the punctured parity bits.3. The apparatus as claimed in claim 2 , wherein the puncturer determines the number of the punctured parity bit groups based on a value which divides the number of the punctured parity bits by the interval at which a pattern of columns is repeated and determines a position of the punctured parity bit groups based on the determined number ...

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Номер записи: 48
19-03-2015 дата публикации

Transmitter and signal processing method thereof

Номер: US20150082117A1
Автор: Hong-Sil Jeong, Kyung-Joong Kim, Se-Ho Myung
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A transmitter, a receiver and methods of controlling the transmitter and the receiver are provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to generate an LDPC codeword by performing LDPC encoding on an L1 post signaling; a demux configured to demultiplex a plurality of bits constituting the L1 post signaling of the LDPC codeword; and a modulator configured to modulate the demultiplexed bits.

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Номер записи: 49
19-03-2015 дата публикации

TRANSMITTING APPARATUS AND PUNCTURING METHOD THEREOF

Номер: US20150082118A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

Provided are a transmitting apparatus, a receiving apparatus and methods of puncturing and depuncturing of parity bits. The transmitting apparatus includes: a zero padder configured to pad at least one zero bit to input bits; an encoder configured to generate a Low Density Parity Check (LDPC) codeword by performing LDPC encoding with respect to the bits to which the at least one zero bit is padded; a parity interleaver configured to interleave LDPC parity bits constituting the LDPC codeword; and a puncturer configured to puncture at least a part of the interleaved LDPC parity bits based on a pre-set puncturing pattern. 1. A transmitting apparatus comprising:a zero padder configured to pad at least one zero bit to input bits;an encoder configured to generate a Low Density Parity Check (LDPC) codeword by performing LDPC encoding with respect to the bits to which the at least one zero bit is padded;a parity interleaver configured to interleave LDPC parity bits constituting the LDPC codeword; anda puncturer configured to puncture at least a part of the interleaved LDPC parity bits based on a pre-set puncturing pattern.2. The transmitting apparatus of claim 1 , wherein the encoder generates the LDPC codeword formed of 16200 bits by performing the LDPC encoding at a code rate of 7/15.4. The transmitting apparatus of claim 1 , wherein the puncturer determines at least one parity bit group to be punctured based on the pre-set puncturing pattern claim 1 , from among a plurality of parity bit groups constituting the interleaved LDPC parity bits claim 1 , and punctures at least a part of the interleaved LDPC parity bits included in the determined parity bit group.5. The transmitting apparatus of claim 1 , wherein the puncturer punctures at least a part of the interleaved LDPC parity bits based on a puncturing pattern which differs according to a modulation scheme.14. A method for puncturing at a transmitting apparatus claim 1 , the method comprising:padding at least one zero ...

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Номер записи: 50
15-03-2018 дата публикации

MEMORY SYSTEM AND METHOD

Номер: US20180076829A1
Автор: Kuroda Sumio, Ozawa Yasuyuki, Ueki Katsuhiko
Принадлежит:

A memory system includes a memory that includes a plurality of memory cells, and a controller. During a write operation to write data to the memory cells, the controller encodes first data to be written at a first code rate. During a read operation to read data from the memory cells, the controller decodes second data read from the memory cells at the first code rate. The controller changes the first code rate to a second code rate that is less than the first code rate upon determining that the number of error bits during the read operation of the second data is above a threshold number for error bits or upon determining that the number of memory cells having a threshold voltage that is in a voltage range that includes a read voltage is above a threshold number for memory cells. 1. A memory system , comprising:a memory including a plurality of memory cells; anda controller, whereinthe controller, during a write operation to write data to the memory cells, encodes first data to be written at a first code rate,the controller, during a read operation to read data from the memory cells, decodes second data read from the memory cells at the first code rate, andthe controller changing the first code rate to a second code rate that is less than the first code rate upon determining that the number of error bits during the read operation of the second data is above a first threshold number.2. The system according to claim 1 , wherein claim 1 , during the read operation claim 1 , the controller performs a read of the second data a plurality of times claim 1 , each time using a different read voltage and each time recording a number of error bits claim 1 , and the number of error bits during the read operation is the minimum number of error bits among the recorded numbers.3. The system according to claim 1 , wherein the controller changes the first code rate to a third code rate that is less than the second code rate upon determining that the number of error bits during the ...

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Номер записи: 51
15-03-2018 дата публикации

Method and Apparatus for Encoding Data Using a Polar Code

Номер: US20180076922A1
Автор: Cheng Nan, GE YIQUN, LI Rong, LIU Xiaocheng, Tong Jiajie, Tong Wen, WANG Jian, Wang Jun, ZHANG Gongzheng, ZHANG Huazi, Zhang Qifan
Принадлежит:

Embodiment techniques map parity bits to sub-channels based on their row weights. The row weight for a sub-channel may be viewed as the number of “ones” in the corresponding row of the Kronecker matrix or as a power of 2 with the exponent (i.e. the hamming weight) being the number of “ones” in the binary representation of the sub-channel index (further described below). In one embodiment, candidate sub-channels that have certain row weight values are reserved for parity bit(s). Thereafter, K information bits may be mapped to the K most reliable remaining sub-channels, and a number of frozen bits (e.g. N−K) may be mapped to the least reliable remaining sub-channels. Parity bits may then mapped to the candidate sub-channels, and parity bit values are determined based on a function of the information bits. 1. A method for a device for encoding data , the method comprising:allocating one or more sub-channels for one or more parity bits based on row weights for sub-channels in a subset of a set of sub-channels; andmapping information bits to remaining sub-channels in the set of sub-channels based on a reliability of the remaining sub-channels without mapping the information bits to the one or more sub-channels allocated for the one or more parity bits,encoding the information bits and the one or more parity bits using a polar code to obtain an encoded bit stream; andtransmitting the encoded bit stream.2. The method of claim 1 , wherein the row weight for a sub-channel represents the number of ones in a row of a Kronecker matrix claim 1 , the row corresponding to the sub-channel.3. The method of claim 1 , wherein the row weights comprise at least a minimum row weight.4. The method of claim 3 , wherein allocating one or more sub-channels for one or more parity bits based on row weights for sub-channels in a subset of a set of sub-channels comprises:allocating, for the one or more parity bits, a number of sub-channels having a row weight equal to the minimum row weight in ...

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Номер записи: 52
15-03-2018 дата публикации

FORWARDING DATA AMONGST COOPERATIVE DSTN PROCESSING UNITS OF A MASSIVE DATA INGESTION SYSTEM

Номер: US20180076931A1
Автор: Dhuse Greg R., Gladwin S. Christopher, Grube Gary W., Leggette Wesley B., Markison Timothy W., Resch Jason K.
Принадлежит:

A method begins with receiving data objects. As the data objects are received, the method continues by assigning a data type identifier to each data object based on the data object being a data type. The method continues with sending data objects having a first data type identifier to a first group of computing devices and sending data objects having a second data type identifier to a second group. The method continues with interpreting, by the first group, the data objects having the first data type identifier to sort, based on sorting criteria the data objects into a first processing category and a second processing category. The method continues with dispersed storage error encoding the data objects in the second processing category based on short term storage error encoding parameters to produce pluralities of sets of encoded data slices and sending the slices to storage and execution units. 1. A method for ingesting a large amount of data in a dispersed storage network (DSN) , wherein the method is executed by a plurality of computing devices , wherein the method comprises: assigning a data type identifier of a plurality of data type identifiers to each data object of the data objects based on the data object being a data type of a plurality of data types;', 'sending data objects having a first data type identifier to a first group of computing devices of the plurality of computing devices;', 'sending data objects having a second data type identifier to a second group of computing devices of the plurality of computing devices;, 'as data objects are receivedinterpreting, by the first group of computing devices, the data objects having the first data type identifier to sort, based on sorting criteria, the data objects having the first data type identifier into a first processing category and a second processing category;dispersed storage error encoding, by the first group of computing devices, the data objects in the second processing category based on short term ...

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Номер записи: 53
16-03-2017 дата публикации

Matrix-Based Error Correction and Erasure Code Methods and System and Applications Thereof

Номер: US20170077950A1
Автор: Critchlow Roger, Lachman Ronald, Murphy Timothy S., Ness Stephen, Pavlov Elan, Swartz Robert
Принадлежит:

A distributed data storage system breaks data into n slices and k checksums using at least one matrix-based erasure code based on matrices with invertible submatrices, stores the slices and checksums on a plurality of storage elements, retrieves the slices from the storage elements, and, when slices have been lost or corrupted, retrieves the checksums from the storage elements and restores the data using the at least one matrix-based erasure code and the checksums. In a method for ensuring restoration and integrity of data in computer-related applications, data is broken into n pieces, k checksums are calculated using at least one matrix-based erasure code based on matrices with invertible submatrices, and the n data pieces and k checksums are stored on n+k storage elements or transmitted over a network. If, upon retrieving the n pieces from the storage elements or network, pieces have been lost or corrupted, the checksums are retrieved and the data is restored using the matrix-based erasure code and the checksums. 1. A method for correction of errors during movement of data among first and second computing or storage devices , comprising: quantifying the data as containing n pieces of data;', 'dividing the n pieces into b substantially equal-sized blocks, where the quantity b is less than n and is dependent on an assigned probability of error during data movement;', 'assigning each block of data a quantity k of two or more checksums;', 'moving the blocks of data from a first device to a second device;, 'at the first device receiving the data;', 'at receipt or later retrieval of the data, checking each block for errors using its respective checksums, and correcting all such errors when they number up to k;', 'for blocks that result in detection of errors uncorrectable using the k checksums assigned to each block, performing error checking and correction on a piece-by-piece basis within the error-containing blocks after subtracting out known values,', 'whereby fast ...

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Номер записи: 54
16-03-2017 дата публикации

SENSOR INTERFACE THAT PROVIDES A LONG PACKAGE CRC TO IMPROVE FUNCTIONAL SAFETY

Номер: US20170077952A1
Автор: HAMMERSCHMIDT Dirk, Scherr Wolfgang
Принадлежит:

A data transmission system comprising an Automotive Sensor Network System (ASNS) connected to a plurality of source locations via a common bus, wherein the ASNS is configured to ascertain the source from which the data-frames and first package checksum are received and based on the ascertainment of the source, appropriate decoding methods are used to calculate the ASNS location data-frame checksums and the ASNS location package checksums. A higher order redundancy check is done over a series of data-frames to detect errors in the reception caused by temporary high interference that may exist in the transmission path. 1. An automotive sensor network system comprising:a transceiver configured to receive at least one data-frame and a first package checksum from a source location, wherein the at least one data-frame includes a first data-frame checksum calculated at the source location;a source component configured to generate a determination of the source location from which the at least one data-frame is received;a data-frame decoder component configured to calculate a second data-frame checksum for the at least one data-frame based on the determination of the source and compare the second data-frame checksum with the first data-frame checksum; anda package decoder component configured to calculate a second package checksum for a plurality of the data-frames received from the transceiver based on the source location and compare the second package checksum with the first package checksum.2. The automotive sensor network system of claim 1 , wherein the package decoder component is further configured to update the second package checksum on receiving at least one data-frame from the transceiver.3. The automotive sensor network system of claim 1 , further comprising a look-up table configured to output a data-frame decoding instruction set and a package decoding instruction set based on the determination of the source location by the transceiver.4. The automotive sensor ...

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Номер записи: 55
18-03-2021 дата публикации

CONTROLLER THAT RECEIVES A CYCLIC REDUNDANCY CHECK (CRC) CODE FOR BOTH READ AND WRITE DATA TRANSMITTED VIA BIDIRECTIONAL DATA LINK

Номер: US20210081269A1
Автор: Wang Yuanlong, Ware Frederick A.
Принадлежит:

A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition. 1. (canceled)2. A controller device to control the operation of a solid state memory device , the controller device comprising: transmitter circuitry to transmit command information, and command error detection information associated with the command information, to the solid state memory device; and', 'receiver circuitry to receive a group of read data bits output by the solid state memory device in connection with the command information, the group of read data bits being time multiplexed with read data error-detection information; and,, 'a link interface configurable in a first configuration and a second configuration, the first configuration to be for bidirectional communication via the link interface, the second configuration to be for unidirectional communication via the link interface, wherein the link interface includescircuitry to determine an error condition based on the group of read data bits and the read data error-detection information, the controller device to perform a remedial action in the event that the circuitry determines the error condition. ...

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Номер записи: 56
14-03-2019 дата публикации

FAULTY WORD LINE AND FAULTY BIT LINE INFORMATION IN ERROR CORRECTING CODING

Номер: US20190081640A1
Автор: MOTWANI RAVI H.
Принадлежит: Intel Corporation

One embodiment provides a memory controller. The memory controller includes a memory controller control circuitry, a defect map logic and an error correction circuitry. The memory controller circuitry is to read a codeword from a memory device. The defect map logic is to identify a respective word line (WL) and a respective bit line (BL) for each bit in the codeword based, at least in part, on a memory device map and to determine whether any identified WL and/or any identified BL is faulty based, at least in part, on a defect map. The error correction circuitry is to configure a decode operation if any identified WL and/or any identified BL is faulty. 1. A memory controller comprising:a memory controller control circuitry to read a codeword from a memory device;a defect map logic to identify a respective word line (WL) and a respective bit line (BL) for each bit in the codeword based, at least in part, on a memory device map and to determine whether any identified WL and/or any identified BL is faulty based, at least in part, on a defect map; andan error correction circuitry to configure a decode operation if any identified WL and/or any identified BL is faulty.2. The memory controller of claim 1 , wherein the defect map logic is to determine whether a WL and/or a BL is faulty based claim 1 , at least in part claim 1 , on a respective WL bit error data and/or a respective BL bit error data; and to update the defect map if the WL is faulty and/or the BL is faulty.3. The memory controller of claim 2 , wherein determining whether the WL and/or BL is faulty comprises determining a raw bit error rate (RBER) for the WL and/or the BL.4. The memory controller of claim 1 , wherein the error correction circuitry is to notify the defect map logic if the codeword contains an error bit that is not a faulty bit associated with the identified WL and/or the identified BL.5. The memory controller of claim 1 , wherein to configure the decode operation is based claim 1 , at least in ...

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Номер записи: 57
14-03-2019 дата публикации

DEVICES AND METHODS IMPLEMENTING POLAR CODES

Номер: US20190081646A1
Автор: BELFIORE Jean-Claude, BIOGLIO Valerio, GABRY Frederic, LAND Ingmar
Принадлежит:

Encoder for encoding K information bits into a code word of length N′ on the basis of a polar code of length N, wherein N is a power of 2 and greater than or equal to N′. The encoder comprises a memory storing a plurality of bit indices, wherein the plurality of bit indices comprise a set of N frozen bit indices associated with the polar code of length N, a set of N/2 puncturing bit indices and/or a set of N/2 shortening bit indices and a processor configured to retrieve at least a subset of the plurality of bit indices from the memory, to encode the K information bits using the polar code of length N for obtaining encoded data of length N and to reduce the number of bits of the encoded data to the length N′ for obtaining the code word of length N′. 1. Encoder for encoding K information bits into a code word of length N′ on the basis of a polar code of length N , wherein N is a power of 2 and greater than or equal to N′ , the encoder comprising:a memory storing a plurality of bit indices, wherein the plurality of bit indices comprise a set of N frozen bit indices associated with the polar code of length N, a set of N/2 puncturing bit indices and/or a set of N/2 shortening bit indices;a processor configured to retrieve at least a subset of the plurality of bit indices from the memory, to encode the K information bits using the polar code of length N for obtaining encoded data of length N and to reduce the number of bits of the encoded data to the length N′ for obtaining the code word of length N′.2. The encoder according to claim 1 , wherein the plurality of bit indices further comprise a set of M frozen bit indices associated with a polar code of length M claim 1 , a set of M/2 puncturing bit indices and/or a set of M/2 shortening bit indices claim 1 , wherein M is a power of 2 and smaller than N claim 1 , and wherein the processor is configured to encode the K information bits using the polar code of length M and to reduce the number of bits of the encoded data to ...

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Номер записи: 58
12-03-2020 дата публикации

TRANSMITTER AND PARITY PERMUTATION METHOD THEREOF

Номер: US20200083905A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to group-wise interleave a plurality of bit groups including the parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups at predetermined positions in the bit groups before the group-wise interleaving are positioned serially after the group-wise interleaving and a remainder of the bit groups before the group-wise interleaving are positioned without an order after the group-wise interleaving so that the puncturer selects parity bits included in the some of the bit groups sequentially and selects parity bits included in the remainder of the bit groups without an order. 2. The transmitting method of claim 1 , wherein each of the plurality of bit groups comprises 360 bits.3. The transmitting method of claim 1 , wherein the encoding encodes 3240 information bits to generate 12960 parity bits. This is a continuation of U.S. application Ser. No. 15/058,348 filed Mar. 2, 2016, which claims priority from Korean Patent Application No. 10-2015-0137188 filed on Sep. 27, 2015 and U.S. Provisional Application No. 62/127,014 filed on Mar. 2, 2015, the disclosures of which are incorporated herein in their entirety by reference.Apparatuses and methods consistent with the exemplary embodiments of the inventive concept relate to a transmitter and a parity permutation method thereof, and more particularly, to a transmitter performing parity permutation on parity bits and a parity permutation method thereof.Broadcast communication services in information oriented society of the 21century are entering an era of digitalization, multi-channelization, bandwidth broadening, and high quality. In particular, as a high ...

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Номер записи: 59
31-03-2016 дата публикации

LDPC DECODER WITH EFFICIENT CIRCULAR SHIFTERS

Номер: US20160094245A1
Автор: Ish-Shalom Tomer, Landau Asaf, Tate Yonathan
Принадлежит:

A decoder includes variable-node circuitry, check-node circuitry and a Message Passing (MP) module, which includes multiple configurable partial cyclic shifters that each supports only a partial subset of shift values out of a full range of shift values 0 . . . L−1. The variable-node circuitry and check-node circuitry are configured to exchange messages with one another in accordance with a parity check matrix that represents a respective Quasi-Cyclic (QC)-Low Density Parity Check (LDPC) Error Correcting Code (ECC) and that includes L-by-L sub-matrices, and to process the exchanged messages to decode a given code word that was encoded using the QC-LDPC ECC. The MP module is configured to schedule the variable-node circuitry and check-node circuitry that are interconnected in accordance with a respective sub-matrix to exchange L messages simultaneously by assigning a given partial cyclic shifter to shift the L messages cyclically a number of positions that depends on a structure of the respective sub-matrix.

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Номер записи: 60
29-03-2018 дата публикации

MEMORY SYSTEM INCLUDING A MEMORY DEVICE THAT CAN DETERMINE OPTIMUM READ VOLTAGE APPLIED TO A WORD LINE

Номер: US20180091170A1
Автор: ASAMI Shohei, Hida Toshikatsu
Принадлежит:

A memory system includes a nonvolatile memory including a word line and a plurality of memory cells connected to the word line, and a controller configured to transmit to the nonvolatile memory, a command that causes the nonvolatile memory to search for an optimum read voltage for the plurality of memory cells connected to the word line. 1. A memory system comprising:a nonvolatile memory including a word line and a plurality of memory cells connected to the word line; anda controller configured to transmit to the nonvolatile memory, a command that causes the nonvolatile memory to search for an optimum read voltage for the plurality of memory cells connected to the word line.2. The memory system according to claim 1 , wherein the nonvolatile memory includes a plurality of blocks claim 1 , each of which is a data erasure unit and includes word lines and memory cells connected to the word lines claim 1 , andwhen a response to the transmitted command is received from the nonvolatile memory, the controller determines whether to store data stored in a first block including the plurality of memory cells connected to the word line, in a second block, based on the response.3. The memory system according to claim 2 , wherein the response includes the optimum read voltage and the controller calculates a first difference that is a difference between the optimum read voltage and a preset read voltage claim 2 , and stores the data stored in the first block in the second block when the first difference is larger than a first value.4. The memory system according to claim 2 , wherein when the response to the command from the nonvolatile memory is information indicating that the optimum read voltage was not calculated claim 2 , the controller determines the optimum read voltage by transmitting multiple read requests to the nonvolatile memory claim 2 , calculates a second difference that is a difference between the optimum read voltage determined by the controller and the preset read ...

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Номер записи: 61
21-03-2019 дата публикации

METHODS FOR DATA ENCODING IN DNA AND GENETICALLY MODIFIED ORGANISM AUTHENTICATION

Номер: US20190089372A1
Автор: Jafari Farhad, Mueller Siguna, Roth Don
Принадлежит:

A method is disclosed comprising encoding a message into blocks, determining a collection of DNA symbols for each of the blocks from the encoded message, performing a second encoding of the determined collection of DNA symbols from the encoded message, detecting a presence of errors in the second encoding and establishing an authentication of each block and further using zero-knowledge protocol to securely authenticate the message without disclosing the actual message. 1. A method , comprising:encoding a message into blocks;determining a collection of DNA symbols for each of the blocks from the encoded message;performing a second encoding of the determined collection of DNA symbols from the encoded message;detecting a presence of errors in the second encoding; andestablishing an authentication of each block.2. The method according to claim 1 , wherein the second encoding uses a Huffman encoding.3. The method according to claim 1 , wherein the determining the collection of DNA from the encoded message includes a sequenced number of copies of the message.4. The method according to claim 3 , wherein the sequenced number of copies is amplified.5. The method according to claim 1 , wherein the establishing the authentication of each block includes computing a hash value of each block.6. The method according to claim 1 , wherein the encoding is within an organism.7. A method of encoding data in DNA claim 1 , comprising:obtaining a set of data to be encoded;subdividing the set of data into equal length blocks;converting the subdivided set of data into A, C, G and T DNA components;sequencing a number of copies of the converted set of data; andestablishing an authentication of each of the set of converted data.8. The method of encoding according to claim 7 , wherein each block of the set of data contains an addressing part.9. The method of encoding according to claim 8 , wherein each block of the set of data contains a data part.10. The method of encoding according to claim 7 ...

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Номер записи: 62
21-03-2019 дата публикации

Method and Apparatus for Encoding Data Using a Polar Code

Номер: US20190089481A1
Автор: Cheng Nan, GE YIQUN, LI Rong, LIU Xiaocheng, Tong Jiajie, Tong Wen, WANG Jian, Wang Jun, ZHANG Gongzheng, ZHANG Huazi, Zhang Qifan
Принадлежит:

Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes allocating, from a set of sub-channels, one or more sub-channels for one or more parity bits based on row weights for sub-channels in a subset of sub-channels within the set of sub-channels, mapping information bits to remaining sub-channels in the set of sub-channels based on a reliability of the remaining sub-channels without mapping any of the information bits to the one or more sub-channels allocated for the one or more parity bits, polar encoding the information bits and the one or more parity bits based on at least the mapping of the information bits to the remaining sub-channels to obtain encoded bits, and transmitting the encoded bits to another device. 1. A method for a device for encoding data , the method comprising:allocating, from a set of sub-channels, one or more sub-channels for one or more parity bits based on row weights for sub-channels in a subset of sub-channels within the set of sub-channels;mapping information bits to remaining sub-channels in the set of sub-channels based on a reliability of the remaining sub-channels without mapping any of the information bits to the one or more sub-channels allocated for the one or more parity bits;polar encoding the information bits and the one or more parity bits based on at least the mapping of the information bits to the remaining sub-channels to obtain encoded bits; andtransmitting the encoded bits to another device.2. The method of claim 1 , wherein a row weight for a given sub-channel represents the number of ones in a row of a Kronecker matrix that corresponds to the given sub-channel.3. The method of claim 1 , wherein the row weights upon which the allocation of sub-channels for the one or more parity bits is based includes at least a minimum row weight.4. The method of claim 3 , wherein allocating the one or more sub-channels for the one or more parity bits based on ...

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Номер записи: 63
30-03-2017 дата публикации

SYSTEMS AND METHODS FOR SOFT DATA UTILIZATION IN A SOLID STATE MEMORY SYSTEM

Номер: US20170093427A1
Автор: CAI Yu, Haratsch Erich F., WU Yunxiang
Принадлежит: SEAGATE TECHNOLOGY LLC

Systems and methods relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. An example data processing system includes a first circuit operable to yield a modified soft data set from a data set accessed from a solid state memory device, and a second circuit operable to apply a data decoding algorithm to the modified soft data to yield a decoded output. 1. A data processing system , the system comprising: yield a modified soft data set from a data set accessed from a memory device, the data set including an original soft data having a first number of bits per element, and the modified soft data set having a second number of bits per element;', 'apply a transfer function to yield an interim data set; and', 'force the value of any element of the interim data set that falls outside of a range of the second number of bits per element to equal a nearest extreme of a range to yield the modified soft data set., 'a first circuit operable to2. The data processing system of claim 1 , further comprising a second circuit operable to apply a data decoding algorithm to the modified soft data set to yield a decoded output.3. The data processing system of claim 2 , wherein the data decoding algorithm is a low density parity check decoding algorithm.4. The data processing system of claim 1 , wherein the transfer function is a non-uniform transfer function.5. The data processing system of claim 4 , wherein the non-uniform transfer function is operable to decrease a probability indicated by a first portion of an original soft data corresponding to the data set claim 4 , and to increase a probability indicating by a second portion of the original soft data.6. The data processing system of claim 5 , wherein the first portion of the original soft data exhibits a lower probability than the second portion of the original soft data.7. The data processing system of claim 1 , wherein the data processing system is ...

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Номер записи: 64
19-03-2020 дата публикации

ENCODER, ASSOCIATED ENCODING METHOD AND FLASH MEMORY CONTROLLER

Номер: US20200091939A1
Автор: KUO Shiuan-Hao
Принадлежит:

An encoding method includes: processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the partial parity blocks includes a first portion and a second portion; using a first computing circuit to generate a first calculating result according to the second portion of the partial parity blocks; using the first calculating result to adjust the first portion of the partial parity blocks; performing circulant convolution operations upon the adjusted first portion to generate a first portion of parity blocks; and using a second computing circuit to generate a second portion of the parity blocks according to at least the first portion of parity blocks; wherein the first portion of the parity blocks and the second portion of the parity blocks serve as a plurality of parity blocks generated in response to encoding the data blocks. 2. The encoder of claim 1 , wherein the second portion of partial parity blocks comprises at least two partial parity blocks claim 1 , and each of the first computing circuit and the second computing circuit comprises a circulant convolution operation.41. The encoder of claim 3 , wherein the first portion of parity blocks comprises C parity blocks claim 3 , and the second computing circuit comprises:{'b': 1', '2, 'a third barrel shifter module, arranged to perform operations upon the C parity blocks in order to generate C processed blocks;'}{'b': 2', '2, 'a third circulant convolution computing circuit, coupled to the third barrel shifter module, the third circulant convolution computing circuit arranged to perform circulant convolution operations upon the C processed blocks in order to generate C output blocks; and'}{'b': 2', '2', '2, 'an output circuit, coupled to the third circulant convolution computing circuit, the output circuit arranged to adjust the C output blocks according to the C intermediate blocks in order to generate C parity blocks as the second portion of parity blocks.'}5. The encoder of claim ...

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Номер записи: 65
19-03-2020 дата публикации

Method and Apparatus for Encoding Data Using a Polar Code

Номер: US20200092035A1
Автор: Ge Yigun, LI Rong, LIU Xiaocheng, Tong Jiajie, Tong Wen, Wang Jun, ZHANG Huazi
Принадлежит:

Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes allocating, from a set of sub-channels, one or more sub-channels for one or more parity bits based on row weights for sub-channels in a subset of sub-channels within the set of sub-channels, mapping information bits to remaining sub-channels in the set of sub-channels based on a reliability of the remaining sub-channels without mapping any of the information bits to the one or more sub-channels allocated for the one or more parity bits, polar encoding the information bits and the one or more parity bits based on at least the mapping of the information bits to the remaining sub-channels to obtain encoded bits, and transmitting the encoded bits to another device. 1allocating, from a set of sub-channels, one or more sub-channels for one or more parity bits based on row weights for sub-channels in a subset of sub-channels within the set of sub-channels;mapping information bits to remaining sub-channels in the set of sub-channels based on a reliability of the remaining sub-channels without mapping any of the information bits to the one or more sub-channels allocated for the one or more parity bits;polar encoding the information bits and the one or more parity bits based on at least the mapping of the information bits to the remaining sub-channels to obtain encoded bits; andtransmitting the encoded bits to another device.. A method for a device for encoding data, the method comprising: This patent application is a continuation of U.S. patent Ser. No. 16/163,253, filed on Oct. 17, 2018 and entitled “Method and Apparatus for Encoding Data Using a Polar Code,” which is a continuation of U.S. patent Ser. No. 15/699,967, filed on Sep. 8, 2017 and entitled “Method and Apparatus for Encoding Data Using a Polar Code,” which claims priority to U.S. Provisional Patent Application 62/395,312 filed on Sep. 15, 2016 and entitled “Method and device for ...

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Номер записи: 66
01-04-2021 дата публикации

BASE STATION APPARATUS, TERMINAL APPARATUS, AND COMMUNICATION METHOD

Номер: US20210099250A1
Автор: Takahashi Hiroki, Yamada Ryota, YOSHIMURA Tomoki
Принадлежит:

To improve communication performance such as a throughput and communication efficiency in a system where multiple communication schemes are used. An apparatus includes a transmitter configured to transmit a transmit signal generated from transmission bits, the transmitter including a coding unit configured to generate the transmission bits by coding and rate matching, the coding unit including a first coding unit, a first interleaving unit, a first bit selection unit, a second coding unit, a second interleaving unit, and a second bit selection unit. The first bit selection unit and the second bit selection unit are different in the initial position based on the same redundancy version. 19-. (canceled)10. A communication apparatus comprising turbo coding circuitry , interleaving circuitry , first hit selection circuitry , tow-density parity check (LDPC) coding circuitry , and second bit selection circuitry , whereinthe turbo coding circuitry is configured to produce a first bit sequence at a first coding ratio by taking a transmission bit as input and by using a turbo coding, the first interleaving circuitry is configured to produce a first interleaved bit sequence by interleaving the first bit sequence, the first bit selection circuitry is configured to produce first encoded bit by selecting a first predetermined number of bits of the interleaved hit sequence from a first initial location, the first initial location being determined based on a first redundancy version,the LDPC coding circuitry is configured to produce a second bit sequence at a second coding ratio by taking the transmission bit as input and by using a LDPC coding, the second bit selection circuitry is configured to produce a second encoded bit by selecting a second predetermined number of bits of the second bit sequence from a second initial location, the second initial location being determined based on a second redundancy version,the first redundancy version is one of four, different redundancy ...

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Номер записи: 67
12-05-2022 дата публикации

TRANSMITTER AND METHOD FOR GENERATING ADDITIONAL PARITY THEREOF

Номер: US20220149867A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits to be transmitted to a receiver in a current frame; a repeater configured to repeat, in the LDPC codeword, at least some bits of the LDPC codeword in the LDPC codeword so that the repeated bits are to be transmitted in the current frame; a puncturer configured to puncture some of the parity bits; and an additional parity generator configured to select at least some bits of the LDPC codeword including the repeated bits, and generate additional parity bits to be transmitted in a previous frame of the current frame. 1. A transmitting method of a transmitting apparatus being operable in a mode from among a plurality of modes , the transmitting method comprising:filling information bits with input bits and one or more zero padding bits, if a size of the input bits is less than a size of the information bits,encoding the information bits to generate parity bits based on a low density parity check (LDPC) code,appending one or more parity bits of the generated parity bits between the information bits and the generated parity bits in a predetermined mode from among the plurality of modes,puncturing one or more parity bits from the generated parity bits,calculating a number of additional parity bits based on a number of the generated parity bits,selecting the additional parity bits based on the calculated number, andgenerating a broadcast signal based on a first frame including the additional parity bits and a second frame including remaining parity bits of the generated parity bits after the puncturing and the appended parity bits, andtransmitting the broadcast signal,wherein the first frame is transmitted prior to the second frame.2. The transmitting method of claim 1 , wherein if the number of additional parity bits is less than or equal to a number of the punctured parity bits ...

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Номер записи: 68
13-04-2017 дата публикации

INTERNAL COPY-BACK WITH READ-VERIFY

Номер: US20170102991A1
Автор: Alhussien Abdelhakim, Chen Zhengang, Hanna Stephen, Haratsch Erich F.
Принадлежит: SEAGATE TECHNOLOGY LLC

Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page. 1. A storage device , the storage device comprising:a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page; reading the first SLC page to an internal page buffer;', 'decoding the first SLC page read into the internal page buffer;', 'determining a number of errors contained in the first SLC page based at least in part on the decoding; and', 'verifying whether the number of errors contained in the first SLC page satisfies an error threshold; and, 'the controller, in conjunction with an error correcting code (ECC) decoder, to read-verify the first SLC page, read-verifying the first SLC page comprisingthe controller to transfer the first SLC page to the TLC page according to a result of read-verifying the first SLC page.2. The storage device of claim 1 , comprising:upon detecting no errors in the first SLC page, the controller to program a word line of the TLC page with the first SLC page read into the internal page buffer.3. The storage device of claim 1 , comprising:upon detecting errors in the first SLC page ...

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Номер записи: 69
12-04-2018 дата публикации

METHODS OF CONTROLLING RECLAIM OF NONVOLATILE MEMORY DEVICES, METHODS OF OPERATING STORAGE DEVICES, AND STORAGE DEVICES

Номер: US20180102790A1
Автор: KANG Woo-Hyun, Kim Min-Kyu, OH SHIN-HO
Принадлежит:

In a method of controlling reclaim of a nonvolatile memory device including a plurality of memory blocks, wherein each of the memory blocks includes a plurality of pages, a recovery read operation is performed on first data using an optimal read voltage determined based on the first data, when the first data includes errors which are not correctable, wherein the first data is read from a first page of a first memory block of the memory blocks, and, when the errors of the first data are corrected after the recovery read operation is performed, whether to perform a reclaim of the first page is determined based on threshold voltage distributions of memory cells of the first page, wherein the memory cells are disposed in a region of interest adjacent to the optimal read voltage. 1. A method of controlling reclaim of a nonvolatile memory device including a plurality of memory blocks , wherein each of the memory blocks includes a plurality of pages , the method comprising:performing a recovery read operation on first data using an optimal read voltage determined based on the first data, when the first data includes errors which are not correctable using an error correction code (ECC) operation, wherein the first data is read from a first page of a first memory block of the memory blocks; andwhen the errors of the first data are corrected after the recovery read operation is performed, determining whether to perform a reclaim of the first page based on threshold voltage distributions of memory cells of the first page, wherein the memory cells of the first page are disposed in a region of interest adjacent to the optimal read voltage.2. The method of claim 1 , wherein the optimal read voltage represents a threshold voltage corresponding to a valley of overlapping regions of two program states of a plurality of program states of the memory cells of the first page claim 1 ,wherein the region of interest is a region defined by the optimal read voltage and a first voltage ...

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Номер записи: 70
12-04-2018 дата публикации

STREAMING ALL-OR-NOTHING ENCODING WITH RANDOM OFFSET SUPPORT

Номер: US20180103100A1
Автор: Leggette Wesley B., Resch Jason K.
Принадлежит:

A method comprises dividing a data segment of a data object into a plurality of data chunks. The method continues with all-or-nothing (AONT) encoding each data chunk of the plurality of data chunks to produce a plurality of sets of AONT encoded data pieces. Note a set of AONT encoded data pieces includes T number of AONT encoded data pieces. The method continues by splitting and rearranging the plurality of sets of AONT encoded data pieces to produce the T number of sets of AONT encoded data pieces. The method continues by dispersed storage error encoding the T number of sets of AONT encoded data pieces to produce a set of encoded data slices, which include the T number+an R number of encoded data slices. 1. A method comprises:dividing, by a computing device of a dispersed storage network (DSN), a data segment of a data object into a plurality of data chunks;all-or-nothing (AONT) encoding, by the computing device, each data chunk of the plurality of data chunks to produce a plurality of sets of AONT encoded data pieces, wherein a set of AONT encoded data pieces includes a T number of AONT encoded data pieces;splitting and rearranging, by the computing device, the plurality of sets of AONT encoded data pieces to produce T number of sets of AONT encoded data pieces; anddispersed storage error encoding, by the computing device, the T number of sets of AONT encoded data pieces to produce a set of encoded data slices, wherein the set of encoded data slices includes the T number+an R number of encoded data slices, wherein a first set of AONT encoded data pieces of the plurality of sets of AONT encoded data can be reconstructed from a first section of each of any combination of T number of encoded data slices of the set of encoded data slices, and wherein a first data chunk of the plurality of data chunks can be reconstructed from the first set of AONT encoded data pieces.2. The method of further comprises:reconstructing, by the computing device or another computing device ...

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Номер записи: 71
13-04-2017 дата публикации

Data Unit Retransmission

Номер: US20170104556A1
Автор: Locke Michael Eugene
Принадлежит:

A source node may send a first data unit to a destination node. To send the first data unit, the source node may transmit a modulation pattern over a transmission medium. In some cases, particular data units may correspond to modulation patterns with features that cause errors in transmission. The source node may receive an indication of an error from the destination node. To avoid repeated errors the retransmission, coding circuitry at the source node may alter data within the first data unit to generate a retransmission data unit. The alteration may result in the retransmission data unit corresponding to a modulation pattern different from that of the first data unit. The new modulation pattern may lack the error causing features and reduce the chance of repeated errors. 1. A device including: an input; and', 'modulated output; and, 'modulation circuitry including [ a first bit; and', 'a second bit, where a modulation pattern used by the modulation circuitry to represent the second bits is determined responsive to the first bit;, 'receive, from demodulation circuitry at a destination node, an indication of an error in a first data unit, the first data unit including, 'responsive to the indication, determine to retransmit the first data unit;', 'alter the first data unit to generate a retransmission data unit by changing the first bit to alter the modulation pattern used by the modulation circuitry to represent the second bit; and', 'send the retransmission data unit to the modulation circuitry for transmission via the modulated output., 'coding circuitry including a data unit output coupled to the input of the modulation circuitry, the coding circuitry configured to2. The device of claim 1 , where the coding circuitry is configured to send the retransmission data unit to the modulation circuitry by sending the first bit ahead of the second bit.3. The device of claim 1 , where the first bit includes a bit within a header of the first data unit.4. The device of ...

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Номер записи: 72
26-03-2020 дата публикации

TRANSMISSION METHOD AND RECEPTION DEVICE

Номер: US20200099397A1
Автор: Shinohara Yuji, Yamamoto Makiko
Принадлежит:

The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like. 1. A transmission method comprising:a coding step of performing LDPC coding on a basis of a parity check matrix of an LDPC code having a code length N of 69120 bits and a coding rate r of 2/16;a group-wise interleaving step of performing group-wise interleaving in which the LDPC code is interleaved in units of bit groups of 360 bits; anda mapping step of mapping the LDPC code to one of 1024 signal points of uniform constellation (UC) in 1024QAM on a 10-bit basis, wherein,in the group-wise interleaving, an (i+1)th bit group from a head of the LDPC code is set as a bit group i, and a sequence of bit groups 0 to 191 of the 69120-bit LDPC code is interleaved into a sequence of bit groups178, 39, 54, 68, 122, 20, 86, 137, 156, 55, 52, 72, 130, 152, 147, 12, 69, 48, 107, 44, 88, 23, 181, 174, 124, 81, 59, 93, 22, 46, 82, 110, 3, 99, 75, 36, 38, 119, 131, 51, 115, 78, 84, 33, 163, 11, 2, 188, 161, 34, 89, 50, 8, 90, 109, 136, 77, 103, 67, 41, 149, 176, 134, 189, 159, 184, 153, 53, 129, 63, 160, 139, 150, 169, 148, 127, 25, 175, 142, 98, 56, 144, 102, 94, 101, 85, 132, 76, 5, 177, 0, 128, 45, 162, 92, 62, 133, 30, 17, 9, 61, 70, 154, 4, 146, 24, 135, 104, 13, 185, 79, 138, 31, 112, 1, 49, 113, 106, 100, 65, 10, 83, 73, 26, 58, 114, 66, 126, 117, 96, 186, 14, 40, 164, 158, 118, 29, 121, 151, 168, 183, 179, 16, 105, 125, 190, 116, 165, 80, 64, 170, 140, 171, 173, 97, 60, 43, 123, 71, 182, 167, 95, 145, 141, 187, 166, 87, 143, 15, 74, 111, 157, ...

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Номер записи: 73
20-04-2017 дата публикации

METHOD FOR READING GRAPHICAL INDICATOR, INDICATOR STRUCTURE AND ELECTRONIC APPARATUS THEREOF

Номер: US20170109595A1
Автор: Lee Cheng-Ta
Принадлежит:

A method for reading a graphical indicator is provided. The method includes the following steps. An indicator image including a plurality of graphical micro-units is obtained. According to a portion of the graphical micro-units, a first header part and a first content data part belonging to a first image indicator are obtained. According to another portion of the graphical micro-units, a second header part and a second content data part belonging to a second image indicator are obtained. The graphical micro-units of the first content data part are further used to obtain the indicator data. When a portion of the graphical micro-units in the first content data part is lost, the complete graphical micro-units can be obtained by recovering the lost graphical micro-units of the first content data part according to the graphical micro-units belonging to the first and the second content data parts captured in the indicator image. 1. A method for reading a graphical indicator , adapted to an electronic apparatus to read a graphical indicator in an indicator structure , wherein the graphical indicator comprises a header part and a content data part , the method comprising:obtaining an indicator image comprising a plurality of graphical micro-units;according to a portion of the graphical micro-units, obtaining a first header part and a first content data part belonging to a first graphical indicator; andaccording to another portion of the graphical micro-units, obtaining a second header part and a second content data part belonging to a second graphical indicator,wherein the graphical micro-units belonging to the first content data part are further used to obtain indicator data corresponding to the first graphical indicator, when a portion of the graphical micro-units in the first content data part is lost, the lost graphical micro-units of the first content data part are estimated according to the graphical micro-units belonging to the first content data part and the second ...

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Номер записи: 74
29-04-2021 дата публикации

DATA ENCODING WITH ERROR-CORRECTING CODE PURSUANT TO COLORSPACE SCHEMES

Номер: US20210126658A1
Автор: GOODSITT Jeremy Edward, WALTERS Austin Grant
Принадлежит: Capital One Services, LLC

Techniques to improve storage, transmission and security of data are included. One or more methods, apparatuses, and articles of manufacture employ one or more color-channels, ultraviolet layers, infrared layers, and/or luminance layers to encode data on or along a physical medium, where the encoding includes utilizing one or more of those layers to encode an error-correcting code (ECC), such as a Hamming code with the data. 1. An apparatus , comprising:a memory to store instructions; and 'encode, according to a colorspace, a data and at least one error-correcting code (ECC) on a physical medium or along a transmission medium, wherein the at least one ECC is encoded in at least one of: (i) a color channel of the colorspace, or (ii) an additional channel of the colorspace.', 'processing circuitry, coupled with the memory, operable to execute the instructions, that when executed, cause the processing circuitry to2. The apparatus of claim 1 , wherein the additional channel of the colorspace comprises an ultraviolet channel of the colorspace claim 1 , an infrared channel of the colorspace claim 1 , or a luminance channel of the colorspace.3. The apparatus of claim 2 , wherein the color channel is one of a plurality of color channels of the colorspace.4. The apparatus of claim 3 , wherein the encoding is on the physical medium pursuant to a quad-tree structure.5. The apparatus of claim 3 , wherein the encoding is along the transmission medium claim 3 , wherein the ECC is encoded in the color channel of the colorspace.6. The apparatus of claim 2 , wherein the colorspace comprises at least four color channels including the color channel claim 2 , wherein the at least four color channels includes only the encoded data claim 2 , and wherein the ECC is encoded in all of the ultraviolet channel claim 2 , the infrared channel claim 2 , and the luminance channel.7. The apparatus of claim 6 , wherein the physical medium is a tag claim 6 , wherein the color channels are part of at ...

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Номер записи: 75
11-04-2019 дата публикации

DECODER FOR LOW-DENSITY PARITY-CHECK CODES

Номер: US20190109601A1
Автор: Anderson Adrian John, Owen Christopher
Принадлежит:

Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is P(where P≥P) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than P*q bits. 1. A configurable LDPC decoder comprising:one or more memories arranged collectively to store soft decision data for each bit node for use in decoding an LDPC code and each memory having a width, the width of a memory comprising an amount of data accessible from the memory in a single cycle;a plurality of check node processing systems arranged to operate in parallel and generate updates to the bit node soft decision data;a first shuffling system arranged to pass data from the one or more memories to the plurality of check node processing systems; anda second shuffling system arranged to pass updates to the bit node soft decision data from the plurality of check node processing systems to the one or more memories;wherein each check node processing system generates updates to soft decision data for a bit node using check-to-bit node messages for each check node connected to the bit node and wherein each check-to-bit node message is calculated using a min-sum algorithm and a variable offset, wherein the variable offset is calculated based on differences between lowest-valued bit-to-check message magnitudes.2. The configurable LDPC decoder according to ...

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Номер записи: 76
09-06-2022 дата публикации

FLASH MEMORY APPARATUS AND STORAGE MANAGEMENT METHOD FOR FLASH MEMORY

Номер: US20220182074A1
Автор: HSU Hong-Jung, Yang Tsung-Chieh
Принадлежит: SILICON MOTION, INC.

A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks. 1. A flash memory apparatus , comprising:a flash memory module comprising a plurality of first blocks and at least one second block; anda flash memory controller having a plurality of channels respectively connected to the flash memory module, wherein the flash memory controller is configured to classify data into a plurality of groups, perform an error code encoding operation on the groups of data to generate corresponding parity check code, and write the groups of data and the corresponding parity check code into the plurality of first blocks of the flash memory module according to a randomizer seed rule of the at least one second block;wherein after the groups of data are written into the plurality of first blocks, the flash memory module writes the groups of data and corresponding parity check code from the plurality of first blocks to the at least one second block.2. The flash memory apparatus of claim 1 , wherein the plurality of first blocks are single-level-cell (SLC) block claim 1 , and the at least one second block is a multi-level-cell (SLC) block claim 1 , a triple-level cell (TLC) block or a quad-level cell (QLC) block.3. The flash memory apparatus of claim 1 , wherein the flash ...

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Номер записи: 77
04-05-2017 дата публикации

Temperature dependent multiple mode error correction

Номер: US20170126249A1
Автор: Charles Augustine, James W. Tschanz, Shigeki Tomishima, Shih-Lien L. Lu, Wei Wu
Принадлежит: Intel Corp

In one embodiment, temperature dependent, multiple mode error correction in accordance with one aspect of this disclosure, is employed for a memory circuit containing arrays of memory cells. In one embodiment, a temperature sensor coupled to an array is configured to provide an output signal which is a function of the temperature of the array of memory cells. Multiple mode error correction code (ECC) logic having an input coupled to an output of the temperature sensor, is configured to encode write data and decode read data for the array of memory cells in an error correction code in one of a plurality of error correction modes as a function of the temperature of the array of memory cells. Other aspects are described herein.

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Номер записи: 78
25-04-2019 дата публикации

Error correction code (ecc) operations in memory

Номер: US20190123768A1
Автор: Yingquan Wu
Принадлежит: Micron Technology Inc

Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include generating a codeword based on a number of low density parity check (LDPC) codewords failing a LDPC decoding operation and performing a BCH decoding operation on the codeword.

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Номер записи: 79
27-05-2021 дата публикации

Method for Efficient Erasure Coded Group Management in shared Nothing Storage Clusters

Номер: US20210159914A1
Автор: Paul Joseph Nowoczynski
Принадлежит: Individual

A method that achieves high availability by employing distributed erasure coding instead of distributed replication and preserves and applies the positive attributes of distributed replication to that of distributed erasure coding. The results are improvements and simplifications to the otherwise difficult internal management processes found in distributed, shared-nothing, erasure coding systems. The key positive attributes of the distributed replication method are processing of a user's write request without requiring the presence of some set of adjacent blocks (ie a read-modify-write) and the ability of storage endpoints to perform garbage collection tasks with complete autonomy of one another. The distributed block storage system simultaneously captures the capacity advantages of erasure coding and the positive attributes of fault tolerance management found in data replication.

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Номер записи: 80
12-05-2016 дата публикации

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

Номер: US20160134304A1
Автор: Hirayama Yuichi, Michael Lachlan, MUHAMMAD Nabil Sven Loghin, Shinohara Yuji, Yamamoto Makiko
Принадлежит: SONY CORPORATION

A code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 is interchanged with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK. When 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and a bit b is interchanged with a bit y, a bit b is interchanged with a bit y, and a bit b is interchanged with a bit y 140-. (canceled)41: A data processing device comprising:an encoding unit configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15; andan interchanging unit configured to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK,wherein, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a (#i+1)-th bit from a most significant bit of the 3 bits of code bits is set to a bit b#i, a (#i+1)-th bit from a most significant bit of 3 bits of symbol bits of the one symbol is set to a bit y#i, and the interchanging unit interchanges{'sub': 0', '1, 'a bit bwith a bit y,'}{'sub': 1', '0, 'a bit bwith a bit y, and'}{'sub': 2', '2, 'a bit bwith a bit y,'}wherein the LDPC code includes an information bit and a parity bit,wherein the parity check matrix includes an information matrix part corresponding to the information bit and a parity matrix part corresponding to the parity bit,wherein the information matrix part is shown by a parity check matrix initial ...

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Номер записи: 81
12-05-2016 дата публикации

DATA PACKET TRANSMISSION/RECEPTION APPARATUS AND METHOD

Номер: US20160134393A1
Автор: HWANG Sunghee, MYUNG Seho, YANG Hyunkoo
Принадлежит:

A method and apparatus are provided for recovering data efficiently even when data loss has occurred over a channel or network. The packet transmission method includes arranging a first transmission packet in a source symbol in a first region of a source block; arranging a second transmission packet in a space starting with an empty space of a last source symbol where the first transmission packet is arranged, remaining after arranging the first transmission packet; arranging information related to the second transmission packet in a second region of the source block; performing Forward Error Correction (FEC) encoding on the source block; and transmitting the encoded source block. 1. A packet transmission method comprising:arranging information of a first source packet in a first region of a source block and arranging a first source symbol of the first source packet in a second region of the source block;padding a predetermined value for a predetermined length in the second region of the source block, after the first source symbol of the first source packet;arranging information of a second source packet in the first region of the source block and arranging a second source symbol of the second source packet in a remaining space of the second region;performing Forward Error Correction (FEC) encoding on the source block; andtransmitting the encoded source block,wherein, a remaining space of the first region is padded with a predetermined value after the information of the first source packet and the second source packet are arranged, andwherein a remaining space of the second region is padded with a predetermined value, after the second source symbol is arranged.2. The packet transmission method of claim 1 , wherein a size of the source block is a predetermined value claim 1 , and {'br': None, 'i': T', '≧N', '−R', 'K, '1_Total_Data1/((1_padding)×) . . . ,'}, 'wherein a size of the first region of the source block is a determined minimum integer based on the equation{' ...

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Номер записи: 82
10-05-2018 дата публикации

SEMICONDUCTOR MEMORY DEVICE PERFORMING RANDOMIZATION OPERATION

Номер: US20180131390A1
Автор: Lee Wan Seob
Принадлежит:

Provided herein is a semiconductor memory device. The semiconductor memory device may include a plurality of planes including a plurality of memory cells, read/write circuits coupled to the plurality of planes, respectively, and temporarily storing normal data inputted from an external device, random data, and parity data, and an error correction circuit generating the random data by randomizing the normal data, generating parity data for the random data during a program operation, correcting an error of the random data by using the parity data and de-randomizing the random data during a read operation. 1. A semiconductor memory device comprising:a plurality of planes including a plurality of memory cells;read/write circuits coupled to the plurality of planes, respectively, and temporarily storing normal data inputted from an external device, random data, and parity data; andan error correction circuit generating the random data by randomizing the normal data, generating parity data for the random data during a program operation, correcting an error of the random data by using the parity data and de-randomizing the random data during a read operation.2. The semiconductor memory device according to claim 1 , wherein the planes comprise a plurality of memory blocks including a plurality of pages.3. The semiconductor memory device according to claim 1 , wherein the read/write circuits comprise:a main page buffer group temporarily storing the normal data or the random data and performing the program operation or the read operation on a selected page by using the random data;a spare page buffer group storing the parity data;a repair page buffer group temporarily storing repair data and performing the program operation or the read operation on the selected page by using the repair data;column selection decoders generating column selection signals for transmitting the normal data, the parity data or the random data between the main page buffer group, the spare page buffer ...

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Номер записи: 83
11-05-2017 дата публикации

TRANSMITTING APPARATUS AND MAPPING METHOD THEREOF

Номер: US20170134046A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, LOBETE Daniel Ansorregui, MOUHOUCHE Belkacem, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitting apparatus is disclosed. The transmitting apparatus includes an encoder to perform channel encoding with respect to bits and generate a codeword, an interleaver to interleave the codeword, and a modulator to map the interleaved codeword onto a non-uniform constellation according to a modulation scheme, and the constellation may include constellation points defined based on various tables according to the modulation scheme. 2. The apparatus as claimed in claim 1 , wherein the encoder encodes the input bits according to a code rate of 4/15.3. The apparatus as claimed in claim 1 , wherein the constellation points as defined in the table comprises constellation points in one quadrant claim 1 , andwherein constellation points in remaining quadrants are obtained by indicating each constellation point a which is defined in the table as a*, −a*, and −a, respectively, * indicating complex conjugation. This application is a Continuation of U.S. application Ser. No. 14/715,780 filed May 19, 2015 in the United States Patent and Trademark Office, the disclosure of which is incorporated herein by reference in its entirety.1. FieldApparatuses and methods consistent with exemplary embodiments of the inventive concept relate to transmitting and receiving date using broadcasting, more particularly, to the design of non-uniform constellations used in a Bit Interleaved Coded Modulation (BICM) mapping bits at an output of an encoder and interleaver to complex constellations.2. Description of the Related ArtThe current broadcasting systems consistent with the Digital Video Broadcasting Second Generation Terrestrial (DVB-T2) use a Bit Interleaved and Coded Modulation (BICM) chain in order to encode bits to be transmitted. The BICM chain includes a channel encoder like a Low Density Parity Check (LDPC) encoder followed by a Bit Interleaver and a Quadrature Amplitude Modulation (QAM) mapper. The role of the QAM mapper is to map different bits output from the channel encoder ...

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Номер записи: 84
11-05-2017 дата публикации

CODING METHOD, DECODING METHOD, CODER, AND DECODER

Номер: US20170134047A1
Автор: MURAKAMI Yutaka
Принадлежит:

An encoding method of generating an encoded sequence by performing encoding of a given encoding rate based on a predetermined parity check matrix. The predetermined matrix is either a first parity check matrix or a second parity check matrix. The first parity check matrix corresponds to a low density parity check (LDPC) convolutional code that uses a plurality of parity check polynomials, and the second parity check matrix is generated by performing at least one of row permutation and column permutation on the first parity check matrix. A parity check polynomial satisfying zero of the LDPC convolutional code is expressible by using a specific mathematical expression. 1. (canceled)2. (canceled) This application is based on Japanese Patent Applications No. 2012-223569, No. 2012-223570, No. 2012-223571, No. 2012-223572, and No. 2012-223573, the contents of which are hereby incorporated by reference.The present invention relates to an encoding method, a decoding method, an encoder, and a decoder using low-density parity check convolutional codes (LDPC-CCs) having coding rates no smaller than 1/2 and not satisfying (n−1)/n (where n is an integer no smaller than two), and LDPC-CCs using improved tail-biting schemes (LDPC block codes using LDPC-CC).In recent years, attention has been attracted to a low-density parity-check (LDPC) code as an error correction code that provides high error correction capability with a feasible circuit scale. Because of its high error correction capability and ease of implementation, an LDPC code has been adopted in an error correction coding scheme for IEEE802.11n high-speed wireless LAN systems, digital broadcasting systems, and so forth.An LDPC code is an error correction code defined by low-density parity check matrix H. Furthermore, the LDPC code is a block code having the same block length as the number of columns N of check matrix H (see Non-Patent Literature 1, Non-Patent Literature 2, Non-Patent Literature 3). For example, random LDPC ...

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Номер записи: 85
19-05-2016 дата публикации

ERASURE-CODING EXTENTS IN AN APPEND-ONLY STORAGE SYSTEM

Номер: US20160139980A1
Автор: Cowling James, Mallipeddi Venkata Harish, Modzelewski Kevin P.
Принадлежит:

A data storage system stores sets of data blocks in extents located on storage devices. During operation, the system performs an erasure-coding operation by obtaining a set of source extents, wherein each source extent is stored on a different machine in the data storage system. The system also selects a set of destination machines for storing destination extents, wherein each destination extent is stored on a different destination machine. Next, the system performs the erasure-coding operation by retrieving data from the set of source extents, performing the erasure-coding operation on the retrieved data to produce erasure-coded data, and then writing the erasure-coded data to the set of destination extents on the set of destination machines. Finally, after the erasure-coding operation is complete, the system commits results of the erasure-coding operation to enable the set of destination extents to be accessed in place of the set of source extents. 1. A computer-implemented method , comprising:operating a data storage system that stores sets of data blocks in extents that are located in storage devices, wherein operating the data storage system involves performing an erasure-coding operation by:obtaining a set of source extents to be erasure-coded;selecting a set of destination machines for storing a set of destination extents to during the erasure-coding operation, wherein each destination extent in the set of destination extents is stored on a different machine in the set of destination machines;initializing the set of destination extents on the set of destination machines; retrieving data from the set of source extents,', 'performing an erasure-coding operation on the retrieved data to produce erasure-coded data, and', 'writing the erasure-coded data to the set of destination extents on the set of destination machines; and, 'performing the erasure-coding operation by,'}after the erasure-coding operation is complete, committing results of the erasure-coding ...

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Номер записи: 86
19-05-2016 дата публикации

DATA STORAGE DEVICE AND OPERATING METHOD THEREOF

Номер: US20160139984A1
Автор: LEE Jong Min
Принадлежит:

A data storage device may include a memory device suitable for storing data and reading stored data as read data, and a bit distribution check unit suitable for performing a first error detection operation on the read data, based on a bit distribution of the read data. 1. A data storage device comprising:a memory device suitable for storing data and reading stored data as read data; anda bit distribution check unit suitable for performing a first error detection operation on the read data, based on a bit distribution of the read data.2. The data storage device of claim 1 , further comprising:an error correcting code (ECC) unit suitable for performing a second error detection operation on the read data based on an ECC algorithm.3. The data storage device of claim 2 , wherein the bit distribution check unit and the ECC unit respectively and independently perform the first and the second error detection operations on the read data.4. The data storage device of claim 1 , wherein the bit distribution check unit calculates a deflection factor of the read data based on the bit distribution claim 1 , and determines that the read data contains an error when the deflection factor exceeds a threshold value.5. The data storage device of claim 1 , further comprising:a processor suitable for performing an error correction operation on the read data based on parity data corresponding to the read data, in response to a result of the first error detection operation of the bit distribution check unit.6. The data storage device of claim 5 , wherein the processor generates the parity data and stores the parity data in the memory device when the memory device stores the data claim 5 ,wherein the parity data is stored in a designated memory region of the memory device, which is selected on a basis of erase count information on the memory device.7. The data storage device of claim 2 , wherein the ECC unit performs a second error correction operation on the read data based on the ECC ...

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Номер записи: 87
01-09-2022 дата публикации

APPARATUS AND METHOD INCLUDING NEURAL NETWORK LEARNING TO DETECT AND CORRECT QUANTUM ERRORS

Номер: US20220278696A1
Автор: HOGABOAM JUSTIN, Srinivasa Narayan
Принадлежит:

Apparatus and method for neural network learning to detect and correct quantum errors. For example, one embodiment of an apparatus comprises. For example, one embodiment of an apparatus comprises: a quantum processor comprising one or more data quantum bits (qbits) and one or more ancilla qbits; an error decoder to decode a state of at least one of the ancilla qbits to generate an error syndrome related to one or more qbit errors; a neural network to evaluate the error syndrome and to either identify a known corrective response for correcting the error or to perform unsupervised learning to identify a corrective response to the error syndrome. 1. A machine-readable medium having program code stored thereon which , when executed by a machine , causes the machine to perform the operations of:identifying a first potential corrective response to the error syndrome based on an existing error correction model containing data related to known corrective responses for different error syndromes;causing the first potential corrective response to be implemented; andif the first potential corrective response corrects the error, then updating the error correction model to include data related to the new error.2. The method of further comprising program code to cause the machine to perform the operation of:selecting one or more additional potential corrective responses if the first potential corrective response does not correct the error until one is identified which corrects the error.3. The method of further comprising program code to cause the machine to perform the operation of:re-initializing the data qbits upon reaching a threshold number of attempts to identify a corrective response. This application is a divisional of co-pending U.S. patent application Ser. No. 15/972,114, filed on May 5, 2018.The embodiments of the invention relate generally to the field of quantum computing. More particularly, these embodiments relate to an apparatus and method including neural network ...

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Номер записи: 88
01-09-2022 дата публикации

METHOD AND APPARATUS FOR DECODING POLAR CODE IN COMMUNICATION AND BROADCASTING SYSTEM

Номер: US20220278772A1
Автор: JANG Min, LIM Hyuntack
Принадлежит:

The disclosure proposes a technique for achieving validity decision performance of a suitable level in communication and broadcasting systems using a polar code. The polar code is a channel code in which it is difficult to use a syndrome check due to a successive cancellation (SC)-based decoding operation and coding structure. Accordingly, in the communication of the related art and broadcasting systems using the polar code, a validity check of a decoding result has been performed by using a path-metric (PM) generated during decoding and a concatenated error detection code, such as a cyclic redundancy check (CRC) code. However, it is difficult to achieve target error detection performance only via such methods when the length of the CRC code is short or when input and output lengths of a code are short. In this regard, an embodiment of the disclosure proposes a method for obtaining a Euclidean distance-based metric between a received signal and a decoded signal by using an estimated codeword output bit sequence, and performing post error detection based on this. 1. A method performed by a receiving end in a wireless communication system , the method comprising:receiving a signal from a transmitting end;performing successive cancellation (SC) decoding, based on a log-likelihood ratio (LLR) sequence obtained from the received signal;obtaining an estimated codeword bit sequence by re-encoding an encoding input bit sequence obtained through the decoding;obtaining a decision metric, based on the estimated codeword bit sequence and the LLR sequence; anddeciding whether the decoding is successful, based on the obtained decision metric.2. The method of claim 1 , wherein the obtaining of the estimated codeword bit sequence by re-encoding the estimated encoding input bit sequence through the decoding comprises:obtaining a code parameter and a code configuration; andobtaining the estimated encoding input bit sequence, based on the obtained code parameter and code configuration ...

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Номер записи: 89
21-05-2015 дата публикации

Systems and Methods for Soft Decision Generation in a Solid State Memory System

Номер: US20150143202A1
Автор: Erich F. Haratsch, Yunxiang Wu, Zhengang Chen
Принадлежит: LSI Corp

Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory.

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Номер записи: 90
17-05-2018 дата публикации

MEMORY CONTROLLER

Номер: US20180138923A1
Автор: IWASAKI Kiyotaka, Koizumi Shinya
Принадлежит:

According to one embodiment, a memory controller includes an encoder, a randomizing circuit, and an interface. The encoder subjects first data received from an external device to error correction coding. The randomizing circuit randomizes second data output from the encoder. The interface transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory. The interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence. 1. A memory controller comprising:an encoder which subjects first data received from an external device to error correction coding;a randomizing circuit which randomizes second data output from the encoder; andan interface which transmits third data output from the randomizing circuit to a nonvolatile semiconductor memory and controls write/read of the nonvolatile semiconductor memory,wherein the interface transmits data of a size larger than or equal to a size of a write unit of the nonvolatile semiconductor memory to the nonvolatile semiconductor memory in a write sequence.2. The memory controller of claim 1 , whereinpadding data is added to follow the first data when the size of the data to be transmitted to the nonvolatile semiconductor memory in the write sequence is smaller than the write unit.3. The memory controller of claim 1 , whereinpadding data is added to follow the second data when the size of the data to be transmitted to the nonvolatile semiconductor memory in the write sequence is smaller than the write unit.4. The memory controller of claim 1 , whereinpadding data is added to follow the third data when the size of the data to be transmitted to the nonvolatile semiconductor memory in the write sequence is smaller than the write unit.5. The memory controller of claim 1 , whereinthe encoder receives the first data of a unit ...

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Номер записи: 91
18-05-2017 дата публикации

ERROR CORRECTION FOR NUCLEOTIDE DATA STORES

Номер: US20170141793A1
Автор: Ang Siena Dumas, Bornholt James, Ceze Luis H., Strauss Karin
Принадлежит:

This disclosure provides techniques for adding error correction to information in a data store that encodes information as a sequence of bases in polynucleotides. Errors may be introduced through creation of the database (e.g., oligonucleotide synthesis) and/or reading information from the database (e.g., polynucleotide sequencing). Additional polynucleotides added to the database can provide error correction through redundancy. The sequence of polynucleotides that provide error correction may be designed by performing an invertible summary operation on information to be stored in the database. One example of an invertible summary operation is the exclusive or operation (XOR). This disclosure also provides techniques for storing metadata related to organization of a database and structure of information on polynucleotides within the database. Metadata may be encoded in polynucleotides and added to the data store. The polynucleotides holding metadata may be designed with unique primer sites so that the metadata can be selectively amplified and sequenced. 1. A method of providing error correction for binary data encoded in synthetic polynucleotides , the method comprising:synthesizing a first polynucleotide encoding a first information payload;synthesizing a second polynucleotide encoding a second information payload; andsynthesizing a third polynucleotide encoding an error-correction payload that has less than full redundancy of the first information payload and less than full redundancy of the second information payload, wherein the error-correction payload is determined by an invertible summary operation on the first information payload and the second information payload.2. The method of claim 1 , wherein the first polynucleotide includes a first address encoded in a first identifier region of the first polynucleotide claim 1 , the second polynucleotide includes a second address encoded a second identifier region of the second polynucleotide claim 1 , and the third ...

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Номер записи: 92
26-05-2016 дата публикации

DETECTING STORAGE ERRORS IN A DISPERSED STORAGE NETWORK

Номер: US20160147593A1
Автор: Kazi Asimuddin, Resch Jason K.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A method includes dividing a data object into data partitions. The method further includes, for each data partition: dividing the data partition into data segments; dispersed storage error encoding the data segments to produce sets of encoded data slices; storing the sets of encoded data slices in a first set of storage units; and generating a segment allocation table regarding storage information of the sets of encoded data slices. The method further includes generating a directory of segment allocation tables. The method further includes receiving an access request regarding at least a portion of the data object. The method further includes accessing the directory to identify one or more segment allocation tables containing storage information for the at least a portion of the data object. The method further includes accessing encoded data slices of the at least the portion of the data object based on the storage information. 1. A method for execution by one or more computing devices , the method comprises:dividing a data object into a plurality of data partitions; dividing the data partition into a plurality of data segments;', 'dispersed storage error encoding the plurality of data segments to produce a plurality of sets of encoded data slices;', 'storing the plurality of sets of encoded data slices in a first set of storage units of a distributed storage network (DSN);', 'generating a segment allocation table regarding storage information of the plurality of sets of encoded data slices;, 'for each data partition of the plurality of data partitionsgenerating a directory of a plurality of segment allocation tables from the segment allocation tables for each of the data partitions;receiving an access request regarding at least a portion of the data object;accessing the directory to identify one or more segment allocation tables of the plurality of segment allocation tables containing storage information for the at least a portion of the data object; andaccessing ...

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Номер записи: 93
08-09-2022 дата публикации

POLAR CODE ENCODING METHOD AND APPARATUS

Номер: US20220286144A1
Автор: GU Jiaqi, Li Bin
Принадлежит: Huawei Technologies Co., Ltd.

This application discloses a polar code encoding method and apparatus, which can improve encoding performance through codeword construction. The method includes: obtaining K information bits to be encoded, where K is a positive integer; determining a first bit sequence based on the K information bits to be encoded, where a length of the first bit sequence is N, the first bit sequence includes fixed bits and the K information bits to be encoded, and the K information bits to be encoded may further include a check bit; determining a second bit sequence based on the first bit sequence and an upper triangular matrix, where the upper triangular matrix is a matrix having N rows and N columns, and the upper triangular matrix may be an upper triangular Toeplitz matrix; and performing polar code encoding on the second bit sequence to obtain and output an encoded sequence. 1. A polar code encoding method implemented by a polar code encoding apparatus , comprising:obtaining K information bits to be encoded, wherein K is a positive integer;determining a first bit sequence based on the K information bits to be encoded, wherein a length of the first bit sequence is N, N is a positive integer power of 2, and the first bit sequence comprises fixed bits and the K information bits to be encoded;determining a second bit sequence based on the first bit sequence and an upper triangular matrix, wherein the upper triangular matrix is a matrix having N rows and N columns; andperforming polar code encoding on the second bit sequence to obtain and output an encoded sequence.2. The method according to claim 1 , wherein the upper triangular matrix is an upper triangular Toeplitz matrix.3. The method according to claim 1 , wherein the determining the first bit sequence based on the K information bits to be encoded comprises:determining K information bit positions based on reliability sorting of N polarized channels for a polar code and a weight of each row in N rows of a generator matrix for ...

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Номер записи: 94
08-09-2022 дата публикации

One-shot state transition probability encoder and decoder

Номер: US20220286147A1
Автор: Jason Bellorado, Marcus Marrow, Zheng Wang
Принадлежит: SEAGATE TECHNOLOGY LLC

A one-shot state transition decoder receives a codeword having N-bits. The decoder reads a first D-bits of the codeword to determine a stitching location d within the codeword. The stitching location identifies a start bit of unencoded data in the codeword. The codeword is decoded into an output buffer for user data of L bits, where N>L. Parameters of the decoder are set before the decoding, including setting a length of the codeword to N−L+d and a number of expected decoded bits to d. The decoding including decoding the d bits based on a set of state transition probabilities and copying decoded bits into the output buffer, the unencoded data being copied to the end of the output buffer.

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Номер записи: 95
26-05-2016 дата публикации

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD

Номер: US20160149589A1
Автор: IKEGAYA Ryoji, Shinohara Yuji, Yamamoto Makiko
Принадлежит: SONY CORPORATION

The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 12/15, 6/15, or 8/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code. 1. A data processing device comprising:an encoding unit configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length N is 16200 bits and an encoding rate r is 12/15;a group-wise interleaving unit configured to perform group-wise interleave of interleaving the LDPC code in units of bit groups of 360 bits; anda mapping unit configured to map the LDPC code to any of 64 signal points decided in a modulation scheme in units of 6 bits, whereinin the group-wise interleave, when an (i+1)-th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 44 of the LDPC code of 16200 bits is interleaved into a sequence of bit groups17, 11, 14, 7, 31, 10, 2, 26, 0, 32, 29, 22, 33, 12, 20, 28, 27, 39, 37, 15, 4, 5, 8, 13, 38, 18, 23, 34, 24, 6, 1, 9, 16, 44, 21, 3, 36, 30, 40, 35, 43, 42, 25, 19, and 41,the LDPC code includes an information bit and a parity bit,the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit,the information matrix portion is represented by a parity check matrix initial value table, andthe parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes3 394 ...

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Номер записи: 96
09-05-2019 дата публикации

CONTROLLER AND OPERATING METHOD THEREOF

Номер: US20190140659A1
Автор: KIM Se-Hyun
Принадлежит:

A controller includes a processor suitable for determining whether to store further data corresponding to a command from a host into a first region in a main memory of the host when receiving the command from the host, requesting the host to store the further data corresponding to the command into the first region of the main memory when the first region is determined to store the further data corresponding to the command; and an error correction code unit suitable for encoding the further data stored in the first region in response to the storage request. The processor may control a memory device to store the encoded data. 1. A controller comprising:a processor suitable for:storing to a memory device a data corresponding to a command received from a host;generating a metadata regarding the data stored in the memory device;determining whether to store the metadata into a memory included in the host; andrequesting the host to store the metadata into the memory when the metadata is determined to be stored in the memory.2. The controller of claim 1 ,further comprising an internal memory,wherein the processor is suitable for storing the metadata into the internal memory when the metadata is determined not to be stored into the memory.3. The controller of claim 2 ,wherein the processor is suitable for storing the metadata into the internal memory or requesting the host to store the metadata into the memory, according to one or more among types, characteristics, usage frequencies and sizes of the metadata.4. The controller of claim 3 ,wherein the metadata include map data.5. The controller of claim 1 ,wherein the processor is further suitable for transmitting the metadata to the host when the metadata is determined to be stored in the memory.6. A memory system operatively coupled with a host claim 1 , comprising:a memory device suitable for storing a user data and a meta data relevant to the user data; anda controller suitable for storing the user data, corresponding to a ...

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Номер записи: 97
09-05-2019 дата публикации

INTEGRATED PHYSICAL CODING SUBLAYER AND FORWARD ERROR CORRECTION IN NETWORKING APPLICATIONS

Номер: US20190140771A1
Автор: Basso Claude, SONG Cheng Wei, Verplanken Fabrice Jean
Принадлежит:

Techniques for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer are provided. A PCS transmit structure is configured to receive data from a MAC sublayer, the PCS transmit structure comprising a first FEC hardware module that inserts one or more alignment markers in the data and performs FEC encoding, in a first clock domain, on the one or more alignment markers and the data to generate FEC encoded data. Further, a PCS receive structure configured to receive the FEC encoded data from the PCS transmit structure, the PCS receive structure comprising a second FEC hardware module is configured to perform FEC decoding, in the second clock domain, on the FEC encoded data to generate FEC decoded data, and remove the one or more alignment markers from the FEC decoded data. 1. A system comprising: insert one or more alignment markers in the data; and', 'perform FEC encoding, in a first clock domain, on the one or more alignment markers and the data to generate FEC encoded data;', 'wherein the PCS transmit structure is further configured to transmit the FEC encoded data from the first clock domain with a first clock cycle to a second clock domain with a second clock cycle; and, 'a physical coding sublayer (PCS) transmit structure configured to receive data from a media access control (MAC) sublayer, the PCS transmit structure comprising a first forward error-correction (FEC) hardware module configured to perform FEC decoding, in the second clock domain, on the FEC encoded data to generate FEC decoded data; and', 'remove the one or more alignment markers from the FEC decoded data., 'a PCS receive structure configured to receive the FEC encoded data from the PCS transmit structure, the PCS receive structure comprising a second FEC hardware module configured to2. The system of claim 1 , wherein the first FEC hardware module performs Reed-Solomon encoding on the one or more alignment markers and the data.3. The system ...

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Номер записи: 98
30-04-2020 дата публикации

TRANSMITTER AND PARITY PERMUTATION METHOD THEREOF

Номер: US20200136647A1
Автор: Jeong Hong-Sil, KIM Kyung-Joong, MYUNG Se-Ho
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to puncture some of the parity bits in the group-wise interleaved bit groups, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups. 2. The receiving apparatus of claim 1 , wherein each of the plurality of groups comprises 360 values.4. The receiving method of claim 3 , wherein each of the plurality of groups comprises 360 values. This application is a continuation of U.S. application Ser. No. 16/361,805 filed on Mar. 22, 2019 which is a continuation of U.S. application Ser. No. 15/058,242 filed Mar. 2, 2016, which is now U.S. Pat. No. 10,277,250 issued on Apr. 30, 2019, which claims priority from Korean Patent Application No. 10-2015-0137182 filed on Sep. 27, 2015 and U.S. Provisional Application No. 62/127,022 filed on Mar. 2, 2015, the disclosures of which are incorporated herein in their entirety by reference.Apparatuses and methods consistent with the exemplary embodiments of the inventive concept relate to a transmitter and a parity permutation method thereof, and more particularly, to a transmitter performing parity permutation on parity bits and a parity permutation method thereof.Broadcast communication services in information oriented society of the 21century are entering an era of digitalization, multi-channelization, bandwidth broadening, and high quality. In particular, as a high definition digital television (TV) and portable broadcasting signal reception devices are widespread, ...

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Номер записи: 99
10-06-2021 дата публикации

METHOD AND APPARATUS FOR PROVIDING A JOINT ERROR CORRECTION CODE FOR A COMBINED DATA FRAME COMPRISING FIRST DATA OF A FIRST DATA CHANNEL AND SECOND DATA OF A SECOND DATA CHANNEL AND SENSOR SYSTEM

Номер: US20210175906A1
Автор: HAMMERSCHMIDT Dirk, Rasbornig Friedrich, SCHEIBENZUBER Wolfgang, Scherr Wolfgang, Zettler Thomas
Принадлежит:

An apparatus () for providing an joint error correction code () for a combined data frame () comprising first data () of a first data channel and second data () of a second data channel comprises a first error code generator () configured to provide, based on a linear code, information on a first error correction code () using the first data (). The apparatus further comprises a second error code generator () configured to provide, based on the linear code, information on a second error correction code () using the second data (). The apparatus is configured to provide the joint error correction code () using the information on the first error correction code () and the information on the second error correction code (). 119-. (canceled)20. A method for providing a joint error correction code for a combined data frame comprising first data of a first data channel and second data of a second data channel , comprising:providing, based on a linear code, first error correction code information using a first cyclic code generator to process the first data;initializing a second cyclic code generator using the first error correction code information; andusing the initialized second cyclic code generator to provide, based on the linear code, the joint error correction code using the second data and the first error correction code information.21. The method of claim 20 , further comprising:initializing the first cyclic code generator with a seed value; anddetermining that the first data is available to be processed based on initializing the first cyclic code generator; and 'providing the first error correction code information based on determining that the first data is available to be processed.', 'wherein providing the first error correction code information comprises22. The method of claim 20 , further comprising:determining that the second data is available to be processed;processing the second data using the initialized second cyclic code generator; andproviding the ...

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Номер записи: 100