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Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
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Применить Всего найдено 2045. Отображено 100.
27-02-2005 дата публикации

ПРЕОБРАЗОВАТЕЛЬ ПОТОКОВ ДВОИЧНЫХ СЛОВ НЕКРАТНОЙ РАЗРЯДНОСТИ

Номер: RU0000044214U1
Автор:
Принадлежит: Федеральное государственное унитарное предприятие "Барнаульское специальное конструкторское бюро "ВОСТОК"

Преобразователь потоков двоичных слов некратной разрядности, состоящий из прямого преобразователя, содержащего n-разрядный регистр сдвига (q секций сдвига по n разрядов каждая), с входом данных D, подключенным к шине входных данных Dai, первый k-разрядный счетчик, первый дешифратор и m-разрядный буферный регистр, отличающийся тем, что он дополнительно содержит обратный преобразователь, блок сопряжения, входную шину, включающую шину данных Dai, шину входных стробов Eai и шину тактовой синхронизации Та, выходную шину, включающую шину выходных данных Dbo, шину выходного строба Ebo и шину тактовой синхронизации Tb, и шину ввода-вывода, причем блок сопряжения соединен с прямым преобразователем шиной ввода, включающий шину выходных данных Dao, шину выходных стробов Еао, шину тактовой синхронизации Та и шину начальной установки Ra, а с обратным преобразователем - шиной вывода, включающей шину входных данных Dbi, шину входных стробов Ebi, шину тактовой синхронизации Tb, шину начальной установки Rb и шину управления К, в прямой преобразователь добавлены m-разрядный мультиплексор (2 входов по m разрядов каждый), первый триггер, схема начального пуска, шина входных стробов Eai, шина начальной установки Ra, шина тактовой синхронизации Та, шина выходных данных Dao и шина выходных стробов Еао, в n - разрядный регистр сдвига и первый k-разрядный счетчик добавлены входы разрешения Е, причем вход управления DCE m-разрядного мультиплексора соединен с выходом первого k-разрядного счетчика и первым входом первого дешифратора, входы m-разрядного мультиплексора определенным образом соединены с выходом n-разрядного регистра сдвига, а выход m-разрядного мультиплексора соединен с входом данных D m-разрядного буферного регистра, вход разрешения Е этого регистра соединен с выходом первого дешифратора и входом данных D первого триггера, выход первого триггера соединен с шиной выходных стробов Еао, а выход m-разрядного буферного регистра - с шиной выходных данных Dao, входы схемы начального ...

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Номер записи: 1
10-01-2011 дата публикации

ПРЕОБРАЗОВАТЕЛЬ КОДА

Номер: RU0000101296U1
Автор: Бовсуновский Николай Иванович, Острижный Андрей Сергеевич, Панкова Галина Ивановна, Сахаутдинов Ильдар Вячеславович
Принадлежит: Открытое акционерное общество "Научно-исследовательский институт приборостроения имени В.В. Тихомирова"

Преобразователь кода, содержащий первый и второй счетчики, сдвиговый регистр, генератор опорной частоты, дешифратор, модуль упаковки информации, первое и второе ОЗУ, модуль управления, выход генератора опорной частоты соединен с входом первого счетчика, первый выход которого соединен шиной с дешифратором, первый выход которого соединен шиной с первым входом модуля упаковки информации, к второму входу которого подключена шина данных, являющаяся первым входом преобразователя кода, второй выход дешифратора соединен с первым входом сдвигового регистра, выход сдвигового регистра подключен к первому входу первого и второго ОЗУ, третий выход дешифратора подключен к входу второго счетчика, второй выход первого счетчика соединен с вторым входом сдвигового регистра, третий вход сдвигового регистра подключен к выходу модуля упаковки информации, выход первого ОЗУ шиной подключен к выходу второго ОЗУ и является выходом преобразователя кода, первый выход модуля управления соединен шиной с вторым входом первого ОЗУ, второй выход модуля управления подключен шиной к второму входу второго ОЗУ, первый вход модуля управления соединен с шиной адреса и является вторым входом преобразователя кода, к второму входу модуля управления шиной подключен выход второго счетчика, отличающийся тем, что дополнительно введены третье ОЗУ, второй сдвиговый регистр, второй модуль упаковки информации, второй дешифратор и третий счетчик, причем вход второго дешифратора подключен к шине адреса, а выход к второму входу третьего ОЗУ, к первому входу третьего ОЗУ подключен третий вход преобразователя, к третьему входу ОЗУ подключен первый выход третьего счетчика, к входу которого подключен генератор опорной частоты, выход третьего ОЗУ подключен шиной к первому входу второго сдвигового регистра, а к второму входу второго сдвигового регистра подключен второй выход третьего счетчика, выход второго сдвигового регистра соединен шиной с входом второго модуля упаковки информации, выход которого соединен шиной с ...

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Номер записи: 2
29-01-2019 дата публикации

УСТРОЙСТВО СБОРА ДАННЫХ

Номер: RU0000186683U1
Автор: Атопшев Юрий Сергеевич, Воронков Алексей Всеволодович, Корниенко Тимофей Андреевич
Принадлежит: Публичное акционерное общество "Научно-производственное объединение "Алмаз" имени академика А.А. Расплетина" (ПАО "НПО "Алмаз")

Устройство сбора данных, содержащее узлы ввода данных и буферизации и блок выходного интерфейса, причем группа входов данных, а также входы частоты синхронизации и частоты дискретизации узла ввода данных являются одноименными входами устройства, вход управления которого и группа выходов сформированных данных которого являются одноименными входом и группой выходов блока выходного интерфейса, отличающееся тем, что узел ввода данных содержит блоки параллельного и параллельно-последовательного ввода данных, устройство также содержит блоки выбора режима и первой генерации тактовой последовательности, а узел буферизации содержит блоки управления режимами, второй генерации тактовой последовательности, обработки параллельного интерфейса, обработки последовательного интерфейса, обработки параллельно-последовательного интерфейса, формирования интерфейса обмена с памятью и персональным компьютером (ПК) и памяти, при этом группа входов данных аналого-цифрового преобразования и входы частоты синхронизации и частоты дискретизации узла ввода данных соединены соответственно с одноименными входами блоков параллельного и параллельно-последовательного ввода данных, выход первой шины передачи данных и выход первой частоты дискретизации блока параллельного ввода данных соединены с одноименными входами блока обработки параллельного интерфейса, выход которого соединен с соответствующим входом блока формирования интерфейса обмена с ПК и памятью, выход которого соединен с блоком выходного интерфейса, выход второй шины передачи данных и выход второй частоты дискретизации блока параллельно-последовательного ввода данных соединены с одноименными входами блока обработки параллельно-последовательного интерфейса, выход которого соединен с соответствующим входом блока формирования интерфейса обмена с памятью и ПК, выходы данных первой, второй и третьей линий блока параллельно-последовательного ввода данных соединены с соответствующими одноименными входами блока обработки последовательного ...

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Номер записи: 3
12-01-2012 дата публикации

Hybrid data transmission circuit

Номер: US20120008713A1
Автор: Tsuyoshi Ebuchi, Yoshihide Komatsu
Принадлежит: Panasonic Corp

A data transmitter having a parallel-to-serial conversion function is supplied with a clock by a PLL circuit unit. In the PLL circuit unit, a first multiphase clock supplied to a first parallel-to-serial conversion circuit is generated and output by a multiphase VCO circuit, while a second multiphase clock supplied to a second parallel-to-serial conversion circuit is generated and output by a multiphase clock generator. The multiphase clock generator generates the second multiphase clock based on the clock output from the multiphase VCO circuit.

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Номер записи: 4
23-02-2012 дата публикации

Resonant clock amplifier with a digitally tunable delay

Номер: US20120044958A1
Автор: Afshin Momtaz, Bharath Raghavan, JUN Cao
Принадлежит: Broadcom Corp

A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.

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Номер записи: 5
26-04-2012 дата публикации

Shift register, electronic device, control method and software program product

Номер: US20120099696A1
Автор: Jurgen Geerlings
Принадлежит: NXP BV

Disclosed is a shift register ( 200, 400 ) comprising an input ( 205 ), an output ( 230 ) and a plurality of register cells ( 210 ) serially connected between the input and the output, each register cell being connected to a neighboring cell via a node, wherein at least some of said nodes comprise a multiplexer ( 220 ) having an output coupled to the downstream register cell and a plurality of inputs, each of said plurality of inputs being coupled to a different upstream register cell such that different length sections of the shift register can be selectively bypassed, the shift register further comprising a set of parallel IO channels ( 230, 410 ) facilitating conversion between interleaved and de-interleaved data, each of said channels being coupled to a different one of said nodes, the number of parallel IO channels being smaller than the total number of register cells in the shift register.

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Номер записи: 6
16-08-2012 дата публикации

Signaling to application lack of requested bandwidth

Номер: US20120207233A1
Автор: Amer A. Hassan, Christian Huitema, D. Gabriel Frost, Deyun Wu, Thomas W. Kuehnel
Принадлежит: Microsoft Corp

A system for signaling an application when a requested data rate and Quality of Service cannot be achieved using OFDM wireless data transmission, and the application proceeds by either renegotiating QoS and data rate, or waiting until they requested rate and QoS are met.

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Номер записи: 7
25-10-2012 дата публикации

High speed and high jitter tolerance dispatcher

Номер: US20120269206A1
Автор: Alberto Scandurra, Carmelo Pistritto, Mounir Zid, Rached Tourki
Принадлежит: STMICROELECTRONICS SA, STMICROELECTRONICS SRL, UNIVERSITE DE MONASTIR

A deserializer circuit includes demultiplexer circuitry configured to receive serial data from an input and output a plurality of divided data outputs, and multiplexer circuitry configured to receive a first logic level at a first input of said multiplexer circuitry, and receive a second logic level at a second input of said multiplexer circuitry and receive one of said divided data outputs at a control input of said multiplexer circuitry. The outputs of the multiplexer circuitry produce the received serial data in a parallel form.

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Номер записи: 8
18-04-2013 дата публикации

CONVERSION DEVICE

Номер: US20130093607A1
Автор: Okamura Jun-ichi, YASUDA Akira
Принадлежит: TRIGENCE SEMICONDUCTOR, INC.

The disclosed conversion device converts an analog input signal into a digital signal and outputs thereof, wherein the conversion device comprises a feedback signal generator for performing mismatch shaping on the digital signal that has been converted and output, and then performing digital-analog conversion to generate a feedback signal; a subtractor for subtracting the feedback signal from the analog input signal and outputting thereof; a serial-parallel converter for converting the signal output from the subtractor into a plurality of parallel signals and outputting thereof; a vector filter for performing signal processing on the plurality of parallel signals output by the serial-parallel converter and outputting a plurality of signals; a quantizer for quantizing the plurality of signals output by the vector filter and outputting digital signals; and a parallel-serial converter for converting the digital signals output by the quantizer into serial signals and outputting thereof. 1. A conversion device which converts an analog input signal to a digital signal and outputs the digital signal , the conversion device comprising:a feedback signal generator which performs digital-analog conversion after mismatch shaping the digital signal, which is converted and output by the conversion device, and generates a feedback signal;a subtractor which subtracts the feedback signal from the analog signal and outputs the analog signal, which is subtracted;a serial-parallel converter which converts a signal output from the subtractor to a plurality of parallel signals and outputs the plurality of parallel signals;a vector filter which performs signal processing on the plurality of parallel signals, which are output from the serial-parallel converter, and outputs a plurality of signals;a quantizer which quantizes the plurality of signals, which are output from the vector filter, and outputs a digital signal; anda parallel-serial converter which converts the digital signal, which ...

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Номер записи: 9
18-04-2013 дата публикации

SIGNAL PROCESSING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF

Номер: US20130093608A1
Автор: KIM Jin Mok, KIM Ki Woong, KWON Hyukchan, Lee Yong Ho
Принадлежит: Korea Research Institute of Standards and Science

Provided are a signal processing apparatus and a signal processing method. The signal processing method include receiving a serial signal including an information frame including channel information and data information of a corresponding channel, extracting a clock signal from the serial signal, generating a load signal when a clock count reaches a maximum clock count by calculating the clock signal; converting the serial signal to a parallel signal according to the load signal, and changing the maximum clock count by comparing parallel-converted parallel channel information with a load count indicating the number of local signals. 1. A signal processing method comprising:receiving a serial signal including an information frame including channel information and data information of a corresponding channel;extracting a clock signal from the serial signal;generating a load signal when a clock count reaches a maximum clock count by calculating the clock signal;converting the serial signal to a parallel signal according to the load signal; andchanging the maximum clock count by comparing parallel-converted parallel channel information with a load count indicating the number of local signals.2. The signal processing method as set forth in claim 1 , wherein changing the maximum clock count comprises:increasing a load count when the load signal is generated;changing the load count to the parallel channel information when the maximum clock count is different from a set reference value;changing the maximum clock count when the parallel channel information is different from the load count and setting the maximum clock count to the set reference value when the parallel channel information is identical to the load count; andresetting the load count when the load count is the set maximum load count.3. The signal processing method as set forth in claim 1 , wherein generating a load signal when a clock count reaches a maximum clock count by calculating the clock signal comprises: ...

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Номер записи: 10
16-05-2013 дата публикации

Signal transfer circuit and image pickup device

Номер: US20130121455A1
Автор: Yusaku Koyama
Принадлежит: Denso Corp, Olympus Corp

A signal transfer circuit may include first to n th switches that are respectively connected to bits of an n-bit digital signal output from a digital signal generating circuit and controlled by a transfer control circuit, a first memory circuit including first to n th memories that respectively hold bits of the n-bit digital signal input through the first to n th switches and are serially connected to each other, a second memory circuit including (n+1) th to m th memories that hold a digital signal and are serially connected to each other, an output signal of the n th memory of the first memory circuit being input to the (n+1) th memory of a first stage, and (n+1) th to m th switches that are connected to output signals of the (n+1) th to m th memories of the second memory circuit and controlled by a read control circuit.

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Номер записи: 11
23-05-2013 дата публикации

SERIAL TRANSMISSION SYSTEM INCLUDING TRANSMITTER APPARATUS AND RECEIVER APPARATUS, FOR USE IN TRANSMISSION OF AV DATA

Номер: US20130127645A1
Автор: SHIBATA Osamu
Принадлежит: Panasonic Corporation

A transmitter apparatus is provided for converting parallel data of natural number n×12 bits into n pieces of serial data, and transmitting n transmission signals each of natural number m bits. In the transmitter apparatus, a dividing buffer divides inputted parallel data into n pieces of 12-bit parallel data, and an encoder circuit 12B14B-converts the n pieces of 12-bit parallel data into n pieces of 14-bit parallel data, respectively, and outputs resulting data. A parallel-to-serial converter circuit parallel-to-serial converts the n pieces of 14-bit parallel data into n pieces of 1-bit serial data, respectively, and outputs resulting data, and an m-bit driver circuit amplifies and transmits the n pieces of 1-bit serial data, as n transmission signals each of m bits, respectively, to n transmission paths. 1. A transmitter apparatus for converting parallel data of natural number n multiplied by 12 bits into n pieces of serial data , and transmitting n transmission signals each of natural number m bits , the transmitter apparatus comprising:a dividing buffer configured to divide inputted parallel data into n pieces of 12-bit parallel data;an encoder circuit configured to 12B14B-convert the n pieces of 12-bit parallel data into n pieces of 14-bit parallel data, respectively, and output resulting data;a parallel-to-serial converter circuit configured to parallel-to-serial convert the n pieces of 14-bit parallel data into n pieces of 1-bit serial data, respectively, and output resulting data; andan m-bit driver circuit configured to amplify and transmit the n pieces of 1-bit serial data, as n transmission signals each of m bits, respectively, to n transmission paths.2. A transmitter apparatus for converting parallel data of natural number p units , whose one unit is parallel data of natural number n multiplied by 12 bits , into (n multiplied by p) pieces of serial data , and transmitting n transmission signals each of natural number m bits , the transmitter apparatus ...

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Номер записи: 12
08-08-2013 дата публикации

Serial-Parallel Conversion Circuit, Method for Driving the Same, Display Device, and Semiconductor Device

Номер: US20130201165A1
Автор: Fujita Masashi
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

A serial-parallel conversion circuit for converting a high-speed serial signal to a parallel signal is provided. Further, a display device with high image quality and fewer external connection terminals is provided. Furthermore, a method for driving a serial-parallel conversion circuit for converting a high-speed serial signal to a parallel signal is provided. A serial-parallel conversion circuit includes a plurality of units in each of which a sampling switch and an amplifier are connected to each other. In the serial-parallel conversion circuit, each sampling switch is configured to output part of a serial signal to its respective amplifier only through one transistor. 1. A semiconductor device comprising:a input portion;a first signal line;a second signal line;an output portion; and a first transistor;', 'a second transistor;', 'a third transistor;', 'a capacitor; and', 'an amplifier;', 'wherein a gate of the first transistor is electrically connected to the first signal line,', 'wherein a gate of the second transistor is electrically connected to the second signal line,', 'wherein one of a source of the first transistor and a drain of the first transistor is electrically connected to a first potential line,', 'wherein one of a source of the second transistor and a drain of the second transistor is electrically connected to the other of the source of the first transistor and the drain of the first transistor,', 'wherein the other of the source of the second transistor and the drain of the second transistor is electrically connected to a second potential line,', 'wherein a gate of the third transistor is electrically connected to the other of the source of the first transistor and the drain of the first transistor,', 'wherein one of a source of the third transistor and a drain of the third transistor is electrically connected to the input portion,', 'wherein a first electrode of the capacitor is electrically connected to the other of the source of the third ...

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Номер записи: 13
29-08-2013 дата публикации

TIMING DEVICE AND METHOD

Номер: US20130221215A1
Автор: Sherwood Ian
Принадлежит: KRATOS ANALYTICAL LIMITED

The present invention provides a timing device, especially a timing device for use in mass spectrometers, for example TOF mass spectrometers, for processing trigger signal data containing a trigger signal indicating the occurrence of a trigger event, the timing device having: a trigger signal deserialiser configured to receive trigger signal data containing a trigger signal indicating the occurrence of a trigger event as serial data and to output the trigger signal data as parallel data, and wherein suitably the timing device has a processing means configured to process trigger signal data outputted by the trigger signal deserialiser as parallel data. 129.-. (canceled)30. A timing device for processing trigger signal data containing a trigger signal indicating the occurrence of a trigger event , the timing device having:a trigger signal deserialiser configured to receive trigger signal data containing a trigger signal indicating the occurrence of a trigger event as serial data and to output the trigger signal data as parallel data.31. A timing device according to claim 30 , wherein the timing device has a processing means configured to process trigger signal data outputted by the trigger signal deserialiser as parallel data.32. A timing device according to selected from the group consisting of:a) a timing device wherein the processing means is configured to produce data based on trigger signal data outputted by the trigger signal deserialiser as parallel data;b) a timing device wherein the processing means is configured to detect a trigger signal contained in trigger signal data outputted by the trigger signal deserialiser as parallel data;c) a timing device wherein the processing means is configured to detect a trigger signal contained in trigger signal data outputted by the trigger signal deserialiser as parallel data, and to produce data based on the detected trigger signal such that the data produced by the processing means is synchronized to a trigger event ...

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Номер записи: 14
19-09-2013 дата публикации

PROVIDING A FEEDBACK LOOP IN A LOW LATENCY SERIAL INTERCONNECT ARCHITECTURE

Номер: US20130241751A1
Автор: BENHAMOU Assaf, LAZAR Dror, SHOOR Ehud
Принадлежит:

In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed. 1. (canceled)2. An apparatus comprising: a receiver front end to receive and condition an analog signal into serial data; and', 'a de-serializer to receive the serial data at a first rate and to output a parallel data frame corresponding to the serial data and having a bit width of N, wherein the de-serializer is to output the parallel data frame aligned to a frame alignment boundary in response to a phase control signal; and, 'an analog front end includinga receiver logic including digital logic coupled to the de-serializer to receive the parallel data frame from the de-serializer, wherein the receiver logic is to feedback the phase control signal to the de-serializer, the digital logic to not perform frame alignment on the parallel data frame.3. The apparatus of claim 2 , wherein the de-serializer is to cut the serial data into a plurality of parallel data frames each at a possible alignment of the frame alignment boundary.4. The apparatus of claim 1 , wherein the de-serializer includes a shift register to receive the serial data and an output circuit to output the parallel data frame responsive to the phase control signal.5. The apparatus of claim 4 , wherein the de-serializer is to clock the serial data into the shift register with a digital clock recovered from the serial data claim 4 , and wherein the output circuit includes N flops and the phase control signal is to clock the N flops.6. The apparatus of claim 5 , wherein the receiver logic includes a phase control circuit to generate the phase control signal.7. The apparatus of claim 6 , ...

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Номер записи: 15
26-09-2013 дата публикации

Delaying Data Signals

Номер: US20130249717A1
Автор: Paulius Mosinskis, Phillip Johnson, Richard Booth
Принадлежит: Lattice Semiconductor Corp

In one embodiment, multiple (serializer-deserializer) SERDES channels are aligned by selectively slipping one or more of the incoming serial data streams one bit at a time prior to deserialization. Within each SERDES channel, a slip circuit slips the corresponding serial data stream by one bit (i.e., one unit interval (UI)) by extending the high portion of the duty cycle of a corresponding clock signal. The high portion of the clock signal is extended using a 3-to-1 mux that selects a fixed high signal, such as the high power supply rail, as an intermediate mux output signal whenever transitioning between two different applied clock signals that are offset from one another by one UI. In this way, the slip circuit avoids glitches that might otherwise result from switching directly between the two clock signals.

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Номер записи: 16
10-10-2013 дата публикации

Digital phase locked loop circuitry and methods

Номер: US20130265179A1
Автор: Chong H. Lee, Ramanand Venkata
Принадлежит: Altera Corp

Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.

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Номер записи: 17
12-12-2013 дата публикации

Scalable Serializer

Номер: US20130328704A1
Автор: Chandrasekharan Karthik, Chen Hua-Feng, Djaja Gregory, Gorti Ramamurthy, SMITH Douglas
Принадлежит: BROADCOM CORPORATION

According to an exemplary embodiment, a serializer includes upper and lower shift registers configured to perform a load function where parallel input data is loaded from a parallel input bus and a shift function where the parallel input data is shifted to an output register. The upper shift register is configured to perform the load function while the lower shift register performs the shift function, and the lower shift register is configured to perform the load function while the upper shift register performs the shift function. An output register is configured to alternately receive the parallel input data from the upper shift register and the parallel input data from the lower shift register. The upper and lower shift registers and the output register can comprise scan flip-flops. 120-. (canceled)21. A serializer comprising:upper and lower shift registers configured to perform a load function wherein parallel input data is loaded from a parallel input bus and a shift function wherein said parallel input data is shifted to an output register;said output register configured to alternately receive all of said parallel input data from said upper shift register followed by all of said parallel input data from said lower shift register.22. The serializer of claim 21 , wherein said upper and lower shift registers are configured to perform said shift function at a frequency of a shift clock and wherein said load function of said upper and lower shift registers is performed at a frequency of a load clock.23. The serializer of claim 22 , wherein said parallel input bus has a number of channels claim 22 , said frequency of said load clock being equal to said frequency of said shift clock divided by said number of channels.24. The serializer of claim 21 , wherein said upper and lower shift registers are configured to perform said shift function at a frequency of a shift clock claim 21 , said output register configured to alternately receive said parallel input data from ...

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Номер записи: 18
02-01-2014 дата публикации

COMMUNICATION SYSTEM VIA CASCADE CONNECTION AND COMMUNICATION DEVICE

Номер: US20140006912A1
Автор: Morikawa Daisuke
Принадлежит:

A communication system having a main control portion (MCP) to transmit information destined to a device n cascade levels down, and create an error detection code (CRC code) for data that contains a count of remaining cascade levels until an n-th cascade level and the information. The code is transmitted to an upstream sub-control portion (USCP) with the data. The USCP creates a CRC code for the data, and compares the created and received codes. For a match, the USCP determines whether the information is destined to itself based on the remaining cascade level count. When the information is not so destined, the USCP creates new data with the remaining cascade level count reduced by 1, and a CRC code for the new data, and transmits the created code to a further device, with the new data. 1. A communication system , comprising:a plurality of communication devices including a first communication device and a second communication device, which are connected by cascade connection, the first communication device including: communication data destined to another communication device, which is one of the plurality of communication devices, that is n-th cascade level down from the first communication device,', 'a count of remaining cascade level till the n-th cascade level, and', 'an first error detection code;, 'first transmitting unit configured to transmit first information to the second communication device which is on a cascade level next to the first communication device, wherein the first information comprisingfirst creating unit configured to create the first error detection code for the communication data and the count; second creating unit configured to create second error detection code for the communication data and the count in the received first information;', 'a determining unit configured to determine, in the case where the second error detection code match with the first error detection code in the received first information, whether or not the communication ...

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Номер записи: 19
13-02-2014 дата публикации

PARALLEL-TO-SERIAL CONVERTER CIRCUIT

Номер: US20140043174A1
Автор: Suzuki Shigeto
Принадлежит: FUJITSU LIMITED

A first multiplexer, at each given cycle, outputs a second input data signal, after outputting a first input data signal. A second multiplexer, at each given cycle, outputs a fourth input data signal, after outputting a third input data signal. The second multiplexer outputs the third input data signal at a timing that coincides with the timing at which the second input data signal is output from the first multiplexer. At each given cycle, a third multiplexer, after outputting the first input data signal and the second input data signal output from the first multiplexer, outputs the third input data signal and the fourth input data signal output from the second multiplexer. 1. A parallel-to-serial converter circuit that converts parallel first to fourth input data signals into a serial signal , the parallel-to-serial converter circuit comprising:a first latch group that based on a first clock signal of a given cycle, outputs the first input data signal at a first timing of the given cycle;a second latch group that outputs the second input data signal at a second timing that is of the given cycle and delayed by half a cycle of the given cycle relative to the first timing;a third latch group that outputs the third input data signal at the second timing;a fourth latch group that outputs the fourth input data signal at a third timing that is of the given cycle and delayed by one given cycle relative to the first timing;a first multiplexer that at each given cycle and based on a second clock signal having a phase that differs by ¼ cycle from the phase of the first clock signal, outputs the second input data signal, after outputting the first input data signal;a second multiplexer that at each given cycle and based on the second clock signal, outputs the fourth input data signal, after outputting the third input data signal and that outputs the third input data signal at a timing that coincides with the timing at which the second input data signal is output from the first ...

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Номер записи: 20
13-02-2014 дата публикации

Method and apparatus for direct digital synthesis of signals using taylor series expansion

Номер: US20140043179A1
Автор: Dipayan Mazumdar, Govind Rangaswamy Kadambi
Принадлежит: MS Ramaiah School of Advanced Studies

A method and apparatus for direct digital synthesis (DDS) of signals using Taylor series expansion is provided. The DDS may include a modified phase-to-amplitude converter that includes read-only-memories (ROMs), registers and, a single size, such as a coarse, intermediate, and fine ROM corresponding to respective higher resolution phase angles. The outputs of the ROMs when combined can form a digital output signal in the form of a Taylor series of a sinusoid function.

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Номер записи: 21
03-01-2019 дата публикации

COMPARATOR

Номер: US20190007037A1
Автор: Barnhill Ryan, Berkram Daniel Alan, Poirier Christopher Allan, Wilson Christopher, ZHOU Dacheng
Принадлежит:

A comparator includes a resolver controlled by a resolver clock signal and a differential amplifier controlled by a sampling clock signal. The resolver clock signal and the sampling clock signal are such that amplification at the differential amplifier during the reset phase of the resolver clock signal and the reset phase of the sampling clock signal begins during the resolving phase of the resolver. 1. A comparator , comprising:a pulse generator to generate a resolver clock signal having a resolving phase and a resolver reset phase, and a sampling clock signal having a sampling phase occurring during the resolver reset phase, a hold phase occurring during the resolving phase, and a sample reset phase occurring during the resolving phase and the resolver reset phase;a resolver controlled by the resolver clock signal to output a decision during the resolving phase and to stop output during the resolver reset phase;a differential amplifier connected to the resolver and controlled by the sampling clock signal to amplify an input differential signal during the sampling phase, hold the amplified sampling clock signal during the hold phase, and be reset during the sample reset phase.2. The comparator of claim 1 , further comprising:a qualified tap circuit to influence the resolver with a bias voltage during the hold phase, the qualified tap circuit comprising a first qualified differential amplifier controlled by a first qualified clock signal and a second qualified differential amplifier controlled by a second qualified clock signal; whereinthe pulse generator generates a first qualified clock signal pulse coinciding with the sampling phase if a tap data signal corresponding to the qualified tap circuit has a first value, andthe pulse generator generates a second qualified clock signal pulse coinciding the sampling phase of the sampling clock signal if the tap data signal corresponding to the qualified tap circuit has a second value.3. The comparator of claim 2 , ...

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Номер записи: 22
03-01-2019 дата публикации

SERDES WITH ADAPTIVE CLOCK DATA RECOVERY

Номер: US20190007053A1
Автор: Boyette Jon, HAILU Eskinder, Pandita Bupesh
Принадлежит:

A gear-shifting serializer-deserializer (SerDes) is provided that uses a first divisor value to form a divided clock while de-serializing a serial data stream prior to a lock detection and that uses a second divisor value to form the divided clock value after the lock detection, wherein the second divisor value is greater than the first divisor value. 1. A receiver , comprising;a mixer configured to phase shift an input clock signal to form a sampling clock signal;a de-serializer configured to sample a serial data stream responsive to the sampling clock signal to form a parallel output data stream;a clock divider configured to divide the sampling clock signal by an adjustable divisor to form a divided clock signal; anda selector circuit configured to set the adjustable divisor to equal to a first divisor responsive to the divided clock signal not being locked with the serial data stream and to set the adjustable divisor to equal a second divisor responsive to the divided clock signal being locked to the serial data stream, wherein the second divisor is greater than the first divisor.2. The receiver of claim 1 , further comprising:a phase detector configured to compare the divided clock signal to the serial data stream to form a phase detector output signal; anda loop filter configured to filter the phase detector output signal to form a filtered phase difference, wherein the mixer is further configured to phase shift the input clock signal responsive to the filtered phase difference.3. The receiver of claim 2 , further comprising:a quadrature mixer configured to phase shift a quadrature (Q) version of the input clock signal to form a Q version of the sampling clock signal, wherein the mixer is an in-phase mixer configured to phase shift an in-phase version of the input clock signal to form the sampling clock signal.4. The receiver of claim 2 , wherein the clock divider is further configured to divide a quadrature version of the sampling clock signal to form a ...

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Номер записи: 23
11-01-2018 дата публикации

Method and apparatus for clock phase generation

Номер: US20180013435A1
Автор: Catherine Hearne, Jinyung Namkoong, Marc Erett, Mayank Raj, Parag Upadhyaya, VAMSHI Manthena
Принадлежит: Xilinx Inc

A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit includes an injection locked oscillator, a loop controller, and a phase interpolator. The injection locked oscillator includes an input for receiving an injected clock signal and an output for forwarding a set of fixed clock phases. The loop controller includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator to a frequency of the injected clock signal. The phase interpolator includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator, an input for receiving the supply voltage from the loop controller, and an output for forwarding an arbitrary clock phase.

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Номер записи: 24
10-01-2019 дата публикации

Serializer, data transmitting circuit, semiconductor apparatus and system including the same

Номер: US20190013928A1
Автор: Hyun bae Lee
Принадлежит: SK hynix Inc

A serializer may include a pre-buffer stage and a main buffer stage. The pre-buffer stage may be configured to generate a plurality of delayed signals by buffering a plurality of signals in synchronization with a plurality of pre-clock signals, respectively. The main buffer stage may be configured to generate an output signal by buffering the plurality of delayed signals in synchronization with a plurality of main clock signals, respectively. The plurality of pre-clock signals may have phase differences from the plurality of main clock signals, respectively.

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Номер записи: 25
15-01-2015 дата публикации

Serializer/deserializer apparatus with loopback configuration and methods thereof

Номер: US20150016493A1
Автор: Michael S. Harwood, Parmanand Mishra
Принадлежит: Inphi Corp

The present invention is directed to integrated circuits. In a specific embodiment, high frequency signals from an equalizer are directly connected to a first pair of inputs of a sense amplifier. The sense amplifier also has a second pair of inputs, which can be selectively coupled to output signals from a DAC or high frequency loopback signals. There are other embodiments as well.

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Номер записи: 26
14-01-2021 дата публикации

PARALLEL CHANNEL SKEW FOR ENHANCED ERROR CORRECTION

Номер: US20210013998A1
Автор: QIAN Haoli, SUN Junqing
Принадлежит: CREDO TECHNOLOGY GROUP LIMITED

Digital communication transmitters, systems, and methods can introduce skew into parallel transmission channels to enhance the performance of forward error correction (FEC) decoders. One illustrative serializer-deserializer (SerDes) transmitter embodiment includes: a block code encoder configured to convert a sequence of input data blocks into a sequence of encoded data blocks; a demultiplexer configured to distribute code symbols from the sequence of encoded data blocks to multiple lanes in a cyclical fashion, the multiple lanes corresponding to parallel transmission channels; a skewer configured to buffer the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; and multiple drivers, each driver configured to transmit code symbols from one of said multiple lanes on a respective one of said parallel transmission channels. 1. An active cable that comprises electrical conductors joining a first transceiver to a second transceiver to provide parallel transmission channels therebetween , each of the first and second transceivers including:a block code encoder configured to convert a sequence of input data blocks into a sequence of encoded data blocks;a demultiplexer configured to distribute code symbols from the sequence of encoded data blocks to multiple lanes in a cyclical fashion;a skewer configured to buffer the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; andmultiple drivers each configured to transmit code symbols from one of said multiple lanes on a respective one of said parallel transmission channels.2. The active cable of claim 1 , wherein each of the first and second transceivers further include:multiple receivers each configured to convert a receive signal from a respective one of said transmission channels into a sequence of channel symbols;an alignment module configured ...

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Номер записи: 27
24-04-2014 дата публикации

Deserializers

Номер: US20140111256A1
Автор: Keun Soo Song
Принадлежит: SK hynix Inc

Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.

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Номер записи: 28
24-04-2014 дата публикации

TRANSMISSION INTERFACE AND SYSTEM USING THE SAME

Номер: US20140111360A1
Автор: CHEN Yi-Hsi, GU Wei-Cheng, Li Chun-Nan, Tsai Chung-Hung
Принадлежит: MEDIATEK INC.

A transmission interface includes a first pin, a second pin, a conversion unit, and a decoding unit. The conversion unit receives a serial input data stream via the first pin and receives a serial clock via the second pin. The conversion unit converts the serial input data stream to parallel input data and converts the serial clock to a parallel clock. The serial input data stream has a full swing form. The decoding unit receives and decodes the parallel input data and generates an input data signal according to the decoded parallel input data. 1. A transmission interface , being applied in a display system , comprising:a first pin and a second pin;a conversion unit for receiving a first serial input data stream via the first pin, receiving a serial clock via the second pin, converting the first serial input data stream to parallel input data, and converting the serial clock to a parallel clock, wherein each of the first serial input data stream and the first serial clock has a full swing form, and analog circuits dealing with differential signals are omitted in the transmission interface; anda decoding unit for receiving and decoding the parallel input data and generating an input data signal according to the decoded parallel input data.2. The transmission interface as claimed in claim 1 , wherein the first serial input data stream is transmitted from a transmission device at double data rate.3. The transmission interface as claimed in claim 1 , wherein the conversion unit further receives a serial synchronization data stream claim 1 , which has the full swing form and is merged with the first serial input data stream claim 1 , via the first pin and converts the serial synchronization data stream to parallel synchronization data.4. The transmission interface as claimed in claim 3 , wherein the decoding unit further receives and decodes the parallel synchronization data and generates a first synchronization signal and a second synchronization signal according to the ...

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Номер записи: 29
25-01-2018 дата публикации

HIGH-SPEED SERIAL DATA RECEIVING APPARATUS

Номер: US20180026657A1
Автор: LEE Young su
Принадлежит: HANWHA TECHWIN CO., LTD.

Provided is a high-speed serial data receiving apparatus including: a clock converter configured to convert a serial clock into a parallel clock; a data converter configured to convert a serial data packet into N parallel data packets and outputting the N parallel data packets; a synchronization signal detector configured to receive the N parallel data packets and the parallel clock, and detecting a data start synchronization of the N parallel data packets output from the data converter by comparing the parallel data packets with a synchronization code of N bits set in advance; and an error compensation unit configured to detect and compensate for a skew between parallel clock and data. 1. A high-speed serial data receiving apparatus comprising:a clock converter configured to convert a serial clock into a parallel clock;a data converter configured to convert a serial data packet into N parallel data packets and output the N parallel data packets;a synchronization signal detector configured to receive the N parallel data packets and the parallel clock, and detect data start synchronization of the N parallel data packets output from the data converter by comparing the parallel data packets with a synchronization code of preset N bits; andan error compensation unit configured to detect a clock skew between parallel clocks and compensate for the clock skew.2. The high-speed serial data receiving apparatus of claim 1 , wherein the data converter converts the serial data packet into N parallel data packets by sampling the serial data packet into N flip-flops based on the serial clock.3. The high-speed serial data receiving apparatus of claim 2 , wherein the data converter outputs the N parallel data packets by synchronizing the N parallel data packets by using the parallel clock.4. The high-speed serial data receiving apparatus of claim 1 , wherein the clock converter comprises:a counter configured to receive a selection signal value that is selected between a single data ...

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Номер записи: 30
23-01-2020 дата публикации

SEEMINGLY MONOLITHIC INTERFACE BETWEEN SEPARATE INTEGRATED CIRCUIT DIE

Номер: US20200028521A1
Автор: Duwel Keith, Jones Jakob Raymond, Mendel David W., Ngo Huy, Schulz Jeffrey Erik
Принадлежит:

A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die. 1. A system comprising:a first interface disposed on a first integrated circuit die, wherein the first interface is configured to receive and store a plurality of signals in parallel from the first integrated circuit die;multiplexing circuitry disposed on the first integrated circuit die, wherein the multiplexing circuitry is configured to select a first subplurality of the plurality of signals for sampling from the first interface more often than a second subplurality of the plurality of signals; anda serial transmitter disposed on the first integrated circuit die, wherein the serial transmitter is configured to generate a serial signal based on an order of selection by the multiplexing circuitry.2. The system of claim 1 , wherein the serial transmitter is configured to generate the serial signal using a first plurality of time slots for the first subplurality of the plurality of signals and a second plurality of time slots for the second subplurality of the plurality of signals claim 1 , wherein a first number of time slots of the first plurality of time slots is higher than a second number of time slots of the second plurality of time slots.3. The system of claim 1 , comprising:a serial receiver disposed on a second integrated circuit die, ...

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Номер записи: 31
30-01-2020 дата публикации

CALIBRATION SCHEME FOR SERIALIZATION IN TRANSMITTER

Номер: US20200036402A1
Автор: CHATTOPADHYAY BIMAN, KANSAL Shourya, MEHTA RAVI
Принадлежит:

A system for clock calibration is described herein which comprises a serializer configured to convert an input data stream in parallel format to provide an out data stream in a serial format; a clock source configured to generate one or more clock signals; a first frequency divider configured to provide at least one divided clock signal of the one or more clock signals; a delay line configured to delay at least one divided clock signal; and a clock calibrator configured to control delay of the at least one divided clock signal at the delay line to adjust the one or more divided clock signals at a fixed relationship with respect to the one or more clock signals based on voltage and temperature variation. 1. A system , comprising:a serializer configured to convert an input data stream in parallel format to provide an out data stream in a serial format;a clock source configured to generate one or more clock signals;a first frequency divider configured to provide at least one divided clock signal of the one or more clock signals;a delay line configured to delay the at least one divided clock signal; anda clock calibrator configured to control delay of the at least one divided clock signal at the delay line to adjust the one or more divided clock signals at a fixed relationship with respect to the one or more clock signals.2. The system of claim 1 , wherein the delay line comprises a fixed delay line and a variable delay line.3. The system of claim 2 , wherein the variable delay line comprises a plurality of RC programmable delay units.4. The system of claim 2 , wherein the clock calibrator comprises:a calibration controller configured to generate control signals to control delay period introduced by the delay line; and send one or more commands to set fixed delay period introduced by the fixed delay line;', 'send one or more commands to set variable delay period introduced by the variable delay line;', 'analyze sampled data of the one or more clock signals using the at ...

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Номер записи: 32
04-02-2021 дата публикации

Bit string conversion

Номер: US20210036712A1
Автор: Vijay S. Ramesh
Принадлежит: Micron Technology Inc

Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can determine that the bit string having the first quantity of bits has a particular data pattern and alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision based, at least in part, on the determination that the bit string has the particular data pattern.

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Номер записи: 33
09-02-2017 дата публикации

LEVEL SHIFTER AND PARALLEL-TO-SERIAL CONVERTER INCLUDING THE SAME

Номер: US20170041003A1
Автор: Song Taek-Sang
Принадлежит:

A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level. 1. A level shifter , comprising:a level shifting unit configured to receive a clock and one or more input signals having a first variable amplitude, and generate one or more output signals having a second variable amplitude, through an output terminal and a complementary output terminal respectively;a first pre-charging unit configured to receive a clock and pre-charge the output terminal by a pre-charging voltage having a predetermined level when the clock is in a first level; anda second pre-charging unit configured to receive a clock and pre-charge the complementary output terminal by the pre-charging voltage when the clock is in the first level a first inverter configured to invert an output signal from the output terminal to generate an inverted output signal;', 'a first PMOS transistor configured to transfer an output of the first inverter to a first node when the clock is in the second level,', 'a first NMOS transistor configured to drive the first node by a ground voltage level when the clock is in the first level,', 'a second PMOS transistor configured to supply the pre-charging voltage when the clock is in the first level, and', 'a third PMOS transistor configured to transfer the pre-charging voltage supplied through the second PMOS transistor to the output terminal under a control of the first node., ' ...

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Номер записи: 34
08-02-2018 дата публикации

IMPEDANCE AND SWING CONTROL FOR VOLTAGE-MODE DRIVER

Номер: US20180041232A1
Автор: Chan Kok Lim, Chang Kun-Yung, Frans Yohan, Koay Chin Yang, Lim Siok Wei, Tan Kee Hian, Zhao Hongyuan
Принадлежит: XILINX, INC.

A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator. 1. A driver circuit , comprising: a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output;', 'first source terminals of the pair of inverters coupled to the first common node; and', 'second source terminals of the pair of inverters coupled to the second common node;, 'a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node, each of the plurality of output circuits comprisinga first voltage regulator having an output coupled to the first common node of the plurality of output circuits;a second voltage regulator having an output coupled to the second common node of the plurality of circuits; anda current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator.2. The driver circuit of claim 1 , wherein the current compensation circuit comprises:a plurality of circuits having an enable input, a first bias input, and a ...

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Номер записи: 35
06-02-2020 дата публикации

Scan-Chain Testing Via Deserializer Port

Номер: US20200041565A1
Автор: AGA Arshan, Xing Nianwei
Принадлежит: CREDO TECHNOLOGY GROUP LIMITED

Scan-chain testing of a semiconductor chip may be performed entirely via a deserializer port. In one illustrative device embodiment, a semiconductor chip includes at least one deserializer having: a serial-to-parallel converter coupled to a pair of differential signal input pins; a scan-chain receiver circuit coupled to at least one of the pair of differential signal input pins in parallel with the serial-to-parallel converter to receive a scan-chain test input data stream; a scan-chain test logic circuit that loads the scan-chain test input data stream into a scan chain and extracts a scan-chain test result data stream from the scan chain; and a scan-chain transmit circuit that drives the pair of differential signal input pins with the scan-chain test result data stream. If multiple SerDes blocks exist on the chip, the deserializer ports may be employed in parallel for input and output of test data streams. 1. A semiconductor chip that comprises at least one deserializer having:a serial-to-parallel converter coupled to a pair of signal input pins that form a differential pair;a scan-chain receiver circuit coupled to at least one of the pair of signal input pins in parallel with the serial-to-parallel converter to receive a scan-chain test input data stream; anda scan-chain transmit circuit that drives the pair of signal input pins with the scan-chain test result data stream.2. The semiconductor chip of claim 1 , wherein the scan-chain receiver circuit is coupled in parallel with the serial-to-parallel converter to each of the signal input pins in said pair.3. The semiconductor chip of claim 1 , wherein the scan-chain transmit circuit supplies the scan-chain test result data stream as a common mode output signal on the pair of signal input pins.4. The semiconductor chip of claim 3 , wherein the scan-chain receiver circuit receives the scan-chain test input data stream concurrently with transmission of the scan-chain test result data stream by the scan-chain transmit ...

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Номер записи: 36
19-02-2015 дата публикации

Data input/output device and system including the same

Номер: US20150048957A1
Автор: Seon Kwang Jeon
Принадлежит: SK hynix Inc

A data input/output (I/O) device includes a plurality of data units and an I/O assembly. The plurality of data units is coupled to a global I/O (GIO) line through corresponding local I/O (LIO) lines and configured to receive or transmit a plurality of data groups through the corresponding LIO lines. At least one of the plurality of data units have a different operation speed. The I/O assembly performs serial/parallel conversion operations on the plurality of data groups including a high-speed data group and outputs results of the serial/parallel conversion operations. The high-speed data group is output from the at least one of the plurality of data units having the different operation speed.

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Номер записи: 37
18-02-2016 дата публикации

High data rate serial link

Номер: US20160049992A1
Автор: Philippe Galy
Принадлежит: STMICROELECTRONICS SA

A data transmission circuit transmits a data signal over a transmission line. A digital to analog converter (DAC) operates to receive N-bit input digital values for conversion to corresponding ones of 2 N different DC voltage levels. The DAC selects, for each N-bit input digital value, one of the 2 N DC voltage levels. An analog to digital converter (ADC) operates to sense the DC voltage on the transmission line for conversion to a corresponding N-bit output digital value.

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Номер записи: 38
03-03-2022 дата публикации

Transmission circuit, interface circuit, and memory

Номер: US20220068854A1
Автор: FENG Lin
Принадлежит: Changxin Memory Technologies Inc

A transmission circuit includes: an upper-layer clock bonding pad configured to transmit a clock signal; M upper-layer data bonding pads configured to transmit data signals; a lower-layer clock bonding pad electrically connected with the upper-layer clock bonding pad, and an area of the lower-layer clock bonding pad is smaller than that of the upper-layer clock bonding pad; and M lower-layer data bonding pads electrically connected with the M upper-layer data bonding pads in a one-to-one correspondence, and an area of a lower-layer data bonding pad is smaller than that of an upper-layer data bonding pad. The upper-layer clock bonding pad and the upper-layer data bonding pads are located on a first layer, the lower-layer clock bonding pad and the lower-layer data bonding pads are located on a second layer.

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Номер записи: 39
13-02-2020 дата публикации

DATA COMPRESSION METHOD

Номер: US20200052714A1
Автор: Kamal Andrew
Принадлежит:

An example method of compressing a data set includes determining whether individual values from a data set correspond to a first category or a second category of values. Based on one of the values corresponding to the first category, the value is added to a compressed data set. Based on one of the values corresponding to the second category, the value is excluded from the compressed data set, and a statistical distribution of values of the second category is updated based on the value. During a first phase, the determining is performed for a plurality of values from a first portion of the data set based on comparison of the values to criteria. During a second phase, the determining is performed for a plurality of values from a second portion of the data set based on the statistical distribution. 1. A method of compressing a data set , comprising:obtaining a data set and criteria for determining whether individual values from the data set correspond to a first category or a second category of values;determining whether values of the data set correspond to the first category or the second category;based on one of the values corresponding to the first category, adding the value to a compressed data set; and excluding the value from the compressed data set; and', 'updating a statistical distribution of values of the second category in the data set based on the value;, 'based on one of the values corresponding to the second categorywherein during a first phase, the determining is performed for a plurality of values from a first portion of the data set based on comparison of the values to the criteria; andwherein during a second phase that is subsequent to the first phase, the determining is performed for a plurality of values from a second portion of the data set that is different from the first portion based on the statistical distribution.2. The method of claim 1 , wherein values corresponding to the first category of data are more complex than values corresponding to ...

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Номер записи: 40
05-03-2015 дата публикации

EFFICIENT HIGH SPEED ADC INTERFACE DESIGN

Номер: US20150061906A1
Автор: Luu Howard K.
Принадлежит: Raytheon Company

A system can include a first section with an ultra high speed digital sampler configured to sample at a first rate, a scrambler connected to the sampler, and a set of ultra high speed serial data outputs. The system can further include a second section with a set of ultra high speed serial data inputs, a set of serial to parallel converter circuits connected to the inputs and outputting data at a second rate, a descrambler having inputs connected to the reduced speed data outputs, and a set of parallel outputs configured to output the serial data. The set of ultra high speed serial data outputs of the first section are configured to be connected to the set of ultra high speed serial data inputs in the second section by a set of ultra high speed communication pathways clocked at a speed substantially equal to the first rate. 1. A system comprising: an ultra high speed digital sampler configured to output samples at a first rate on a plurality of output lines;', 'a set of parallel scramblers connected to the plurality of output lines of the sampler, each scrambler having an ultra high speed serial data output; and, 'a first section comprising a set of ultra high speed serial data inputs;', 'a set of serial to parallel converter circuits connected to the inputs and outputting data at a second rate;', 'a descrambler having inputs connected to the reduced speed data outputs; and', 'a set of parallel outputs configured to output the sample data,, 'a second section comprisingwherein the ultra high speed serial data outputs of the plurality of scramblers are configured to be connected to the set of ultra high speed serial data inputs in the second section by a set of ultra high speed communication pathways clocked at a speed substantially equal to the first rate.2. The system of further comprising:a deskew channel circuit in the first section connected to the ultra high speed data outputs of the first section, the deskew channel circuit having an ultra high speed serial ...

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Номер записи: 41
21-02-2019 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR PROFILING EVENTS IN SEMICONDUCTOR DEVICE

Номер: US20190057733A1
Автор: CHOI Youn-Sik, JEON Ho-yeon, KIM AH CHAN, LEE MIN JOUNG
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor device includes a first serializer configured to collect at least one event in a first domain to generate a first serial data stream and transmit the first serial data stream periodically at a first period, a first de-serializer configured to receive the first serial data stream to restore the first serial data stream into first parallel data streams, the first parallel data stream encoding first parallel data items, a timer configured to provide a clock signal having a second period, a direct memory access (DMA) configured to capture the first parallel data items periodically at a second period using the clock signal to generate capture data items, and a first memory configured to store the capture data items. The addresses of the first memory at which the respective capture data items are stored are arranged in an order that the respective capture data items are captured. 1. A semiconductor device comprising:a first serializer configured to collect events in a first domain to generate a first serial data stream and transmit the first serial data stream periodically at a first period;a first de-serializer configured to receive the first serial data stream to restore the first serial data stream into first parallel data streams, the first parallel data stream encoding first parallel data items;a timer configured to provide a clock signal having a second period;a direct memory access (DMA) configured to capture the first parallel data items periodically at the second period using the clock signal to generate capture data items; anda first memory configured to store the capture data items,wherein addresses of the first memory at which respective ones of the capture data items are stored are arranged in an order that the respective capture data items are captured.2. The semiconductor device of claim 1 , wherein the events includes at least one of a clock gating status claim 1 , a power gating status claim 1 , and a dynamic voltage and frequency scaling ...

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Номер записи: 42
02-03-2017 дата публикации

Serializer and deserializer for odd ratio parallel data bus

Номер: US20170060218A1
Автор: Chulkyu Lee, Le Zhang, Wenjun Su
Принадлежит: Qualcomm Inc

Serializers and deserializers for odd ratio parallel data buses are disclosed. In one embodiment, serializers and deserializers operating with an odd number of parallel data bits work with a half-rate clock to provide a serial data stream at a full clock rate. By providing a half-rate clock, power and area are conserved on the integrated circuit incorporating the serializer. Additionally, by providing a 7:1 serializer, the bus is now compatible with the MIPI C-PHY standard.

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Номер записи: 43
10-03-2016 дата публикации

Data processing apparatus and method of processing data

Номер: US20160072522A1
Автор: Hideaki Hasegawa, Hiroyoshi Ichikura, Kunihiro Harayama
Принадлежит: Lapis Semiconductor Co Ltd

A data processing apparatus includes an inputting portion; a first retrieving portion; a second retrieving portion; a clock determining portion; a first serial parallel converting portion; a second serial parallel converting portion; and a combining portion. The inputting portion receives a serial data including a clock bit. The first retrieving portion obtains a first retrieved data. The second retrieving portion obtains a second retrieved data. The clock determining portion determines whether the clock bit is included in the first retrieved data or the second retrieved data. The first serial parallel converting portion performs parallel conversion to obtain a first parallel data. The second serial parallel converting portion performs parallel conversion to obtain a second parallel data. The combining portion combines the first parallel data and the second parallel data to output a parallel data.

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Номер записи: 44
08-03-2018 дата публикации

Clock recovery and data recovery for programmable logic devices

Номер: US20180069735A1
Автор: Bradley Sharpe-Geisler
Принадлежит: Lattice Semiconductor Corp

Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.

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Номер записи: 45
08-03-2018 дата публикации

CLOCK RECOVERY AND DATA RECOVERY FOR PROGRAMMABLE LOGIC DEVICES

Номер: US20180069736A1
Автор: Sharpe-Geisler Bradley
Принадлежит:

Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream. 1. A system comprising:a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream;a Grey code converter configured to convert the Grey code count approximately at the signal transitions in the serial data stream to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream; andat least one storage register configured to store a corresponding at least one calibration binary count of the plurality of binary counts and provide the at least one calibration binary count for comparison to payload binary counts of the plurality of binary counts.2. The system of claim 1 , further comprising:at least one comparator configured to compare the payload binary counts to the at least one calibration binary count and/or a data pattern binary count and change an output state of the at least one comparator when a compared payload binary count exceeds the at least one calibration binary count and/or data pattern binary count.3. The system ...

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Номер записи: 46
05-06-2014 дата публикации

SYMBOL DECODER, THRESHOLD ESTIMATION AND CORRELATION SYSTEMS AND METHODS

Номер: US20140152485A1
Автор: Levy David
Принадлежит: INFINEON TECHNOLOGIES AG

A threshold estimate system includes a level quantizer, a correlation mechanism, and a threshold adaptation component. The level quantizer is configured to receive an input signal and to generate a quantization signal from the input signal according to one or more threshold levels. The correlation mechanism is configured to correlate the quantization signal with reference symbols to generate an output signal. The threshold adaptation component is configured to modify the one or more threshold levels according to the output signal and the input signal. 1. A threshold estimation system comprising:a level quantizer configured to receive an input signal and generate a quantization signal according to one or more threshold levels;a correlation mechanism configured to correlate the quantization signal with reference symbols to generate an output signal; anda threshold adaptation component configured to modify the one or more threshold levels according to the output signal and the input signal.2. The system of claim 1 , wherein the one or more threshold levels includes at least 2 threshold levels.3. The system of claim 1 , wherein the input signal is a differential signal using current modulation at a first modulated current level and a second modulated current level.4. The system of claim 3 , wherein the second modulated current level is twice the first modulated current level.5. The system of claim 1 , further comprising a quiescent current removal component configured to remove a quiescent current from the input signal prior to being received by the level quantizer.6. The system of claim 1 , wherein the input signal includes amounts of information as chips.7. The system of claim 6 , wherein the chips have a specified chip duration.8. The system of claim 6 , wherein a portion of the chips correspond to a symbol.9. The system of claim 1 , wherein the threshold adaptation component is configured to obtain an average measured current and determine an expected average ...

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Номер записи: 47
16-03-2017 дата публикации

REGULATOR, SERIALIZER, DESERIALIZER, SERIALIZER/DESERIALIZER CIRCUIT, AND METHOD OF CONTROLLING THE SAME

Номер: US20170077808A1
Автор: Iwai Takayuki, Shizuki Yasushi
Принадлежит:

According to an embodiment, a regulator includes: a voltage control circuit to supply a voltage; a clock signal output circuit to output a clock signal controlled by the voltage supplied from the voltage control circuit; and a current control circuit to supply the voltage supplied from the voltage control circuit to the clock signal output circuit, the current control circuit make to flow a dummy current which is determined based on the voltage, and stopping flowing the dummy current at a timing when the clock signal output circuit outputs the clock signal. 1. A regulator comprising:a voltage control circuit to supply a voltage;a clock signal output circuit to output a clock signal controlled by the voltage supplied from the voltage control circuit; anda current control circuit to supply the voltage supplied from the voltage control circuit to the clock signal output circuit, the current control circuit making to flow a dummy current which is determined based on the voltage, and stopping flowing the dummy current at a timing when the clock signal output circuit outputs the clock signal.2. The regulator according to claim 1 , wherein the current control circuit controls an amount of the dummy current based on an amount of a load current flowing when the clock signal output circuit output the clock signal without being controlled.3. The regulator according to claim 1 , wherein the current control circuit controls the amount of the dummy current based on a clock frequency of the clock signal inputted into the clock signal output circuit.4. The regulator according to claim 3 , wherein the current control circuit comprises one or a plurality of dummy current flowing circuits to allow the dummy current to flow from an output of the current control circuit.5. The regulator according to claim 4 , further comprising a dummy current flowing control circuit to select one or plurality of the dummy current flowing circuits based on the clock frequency of the clock signal so as ...

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Номер записи: 48
16-03-2017 дата публикации

Self resetting latch

Номер: US20170077917A1
Автор: Sasan Cyrusian
Принадлежит: Marvell International Ltd

An apparatus includes first and second input transistors receiving respective first and second input signals, and a feedback circuit coupled to the first and second input transistors. The first and second input transistors provide first and second nodes with first and second currents according to values of the first and second input signals, respectively, when the feedback circuit is turned on. The first and second input transistors produce a reset value on the nodes when the feedback circuit is turned off. A method includes resetting, using first and second input transistors, respectively, values of first and second nodes to a reset value, providing first and second currents to the nodes using the first and second input transistors according to values of first and second input signals, and determining the values of the nodes according to the values of the first and second input signals.

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Номер записи: 49
16-03-2017 дата публикации

Conversion of a Discrete-Time Quantized Signal into a Continuous-Time, Continuously Variable Signal

Номер: US20170077944A1
Автор: Pagnanelli Christopher
Принадлежит:

Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive nonlinear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g., programmable noise-transfer-function response) bandpass delta-sigma modulators; and/or (7) a digital pre-distortion linearizer (DPL) for canceling noise and distortion introduced by an analog signal bandpass (reconstruction) filter bank. 1. An apparatus for converting a discrete-time quantized signal into a continuous-time , continuously variable signal , comprising:an input line for accepting full-rate samples of an input signal that are discrete in time and in value, that are separated in time by a full-rate sampling period, and that represent a signal sampled at a full-rate sampling frequency corresponding to the full-rate sampling period;a parallel signal processor having an input coupled to said input line and having a plurality of sub-rate outputs, each sub-rate output providing a different subsampling phase of a complete signal that is output by said apparatus;a first multi-bit-to-variable-level signal converter which is coupled to a first sub-rate output of the parallel signal processor and which operates at a sampling rate that is less than or equal to the full-rate sampling frequency of said ...

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Номер записи: 50
24-03-2022 дата публикации

TRANSMISSION CIRCUIT AND TRANSMISSION SYSTEM ADOPTING REDUCED NUMBER OF INTERFACES

Номер: US20220094377A1
Автор: Chen Yan-Guei, Huang Liang-Wei
Принадлежит: Realtek Semiconductor Corp.

A transmission circuit includes a data input pin, a serial-to-parallel converter, an interface decoder, a parallel-to-serial converter, and a processor circuit. The serial-to-parallel converter is electrically coupled to the data input pin. The serial-to-parallel converter converts a plurality of data signals received by the first data input pin into a set of parallel data signals. The interface decoder is electrically coupled to the serial-to-parallel converter. The interface decoder decodes the set of parallel data signals to generate a set of decoded data signals for parallel transmission. The parallel-to-serial converter is electrically coupled to the interface decoder. The parallel-to-serial converter converts the set of decoded data signals into a plurality of input data signals for serial transmission. The processor circuit is electrically coupled to the parallel-to-serial converter. The processor circuit receives and processes the plurality of input data signals. 1. A transmission circuit comprising:a first data input interface;a first serial-to-parallel converter electrically coupled to the first data input interface, and configured to convert at least a plurality of first data signals from the first data input interface into a set of first parallel data signals, the set of first parallel data signals including a plurality of bit signals transmitted in parallel;an interface decoder electrically coupled to the first serial-to-parallel converter, and configured to decode the set of first parallel data signals to generate a set of decoded data signals for parallel transmission;a first parallel-to-serial converter electrically coupled to the interface decoder, and configured to convert the set of decoded data signals into a plurality of input data signals for serial transmission; anda processor circuit electrically coupled to the first parallel-to-serial converter, and configured to receive and process the plurality of input data signals.2. The transmission ...

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Номер записи: 51
05-03-2020 дата публикации

SERIALIZER-DESERIALIZER DIE FOR HIGH SPEED SIGNAL INTERCONNECT

Номер: US20200075521A1
Автор: Elsherbini Adel A., Liff Shawna M., Pasdast Gerald S., Swan Johanna M.
Принадлежит: Intel Corporation

In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed. 1. A semiconductor package comprising:a first die;a second die; anda first serializer/deserializer (SerDes) die physically coupled with the first die and communicatively coupled with the second die, wherein the first SerDes die is to serialize signals transmitted from the first die to the second die, and the first SerDes die is to deserialize signals received from the second die.2. The semiconductor package of claim 1 , wherein the die is a monolithic die or a composite die.3. The semiconductor package of claim 1 , further comprising a second SerDes die physically coupled with the second die and communicatively coupled with the first SerDes die claim 1 , wherein the second SerDes die is to serialize signals transmitted from the second die to the first die claim 1 , and the second SerDes die is to deserialize signals received from the first die.4. The semiconductor package of claim 1 , wherein the first SerDes die has first pads at a first pitch at a side of the SerDes die coupled with the first die claim 1 , and the first SerDes die has second pads at a second pitch at a side of the SerDes die communicatively coupled with the second die.5. The semiconductor package of claim 4 , wherein the first pitch is larger than the second pitch.6. The semiconductor package of claim 1 , wherein the second die is an interposer.7. The semiconductor package of claim 1 , wherein the second die is a dual-sided interconnect die that includes an active component.8. A method of forming a die with a serializer/deserializer (SerDes) die attached thereto claim 1 , the method comprising: ...

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Номер записи: 52
22-03-2018 дата публикации

Multi-rate transceiver circuitry

Номер: US20180083765A1
Автор: Boon Hong Oh, Chee Wai Yap
Принадлежит: Altera Corp

Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit.

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Номер записи: 53
12-03-2020 дата публикации

System for Serializing High Speed Data Signals

Номер: US20200084016A1
Автор: CHATTOPADHYAY BIMAN, MEHTA RAVI
Принадлежит:

A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal. 1. A system for serializing data signals comprising:a first-in-first-out (FIFO) memory configured to launch a plurality of input data signals, each input data signal launched based on a respective clock signal of a plurality of clock signals; and receive two input data signals of the plurality of input data signals;', 'receive two clock signals of the plurality of clock signals, the two clock signals having launched the two input data signals; and', 'serialize the two received input data signals to generate a serialized signal., 'a plurality of input serializer circuits, each input serializer circuit configured to2. The system of claim 1 , further comprising a clock generator configured to generate the plurality of clock signals claim 1 , each clock signal offset in phase from at least one other clock signal of the plurality of clock signals.3. The system of claim 1 , wherein each of the plurality of input serializer circuits has a critical path claim 1 , a length of the critical path equal to a full clock cycle of the plurality of clock signals.4. The system of claim ...

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Номер записи: 54
21-03-2019 дата публикации

System for Serializing High Speed Data Signals

Номер: US20190089522A1
Автор: CHATTOPADHYAY BIMAN, MEHTA RAVI
Принадлежит:

A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal. 1. A system for serializing data signals comprising:a clock generator configured to generate a plurality of clock signals, each clock signal offset in phase from at least one other clock signal of the plurality of clock signals;a first-in-first-out (FIFO) memory configured to launch a plurality of input data signals, each input data signal launched based on a respective clock signal of the plurality of clock signals; and receive two input data signals of the plurality of input data signals;', 'receive two clock signals of the plurality of clock signals, the two clock signals having launched the two input data signals; and', 'serialize the two received input data signals to generate a serialized signal., 'a plurality of input serializer circuits, each input serializer circuit configured to2. The system of claim 1 , wherein each of the plurality of input serializer circuits has a critical path claim 1 , a length of the critical path equal to a full clock cycle of the plurality of clock signals.3. The system of claim 1 , wherein the two input clock signals received by one ...

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Номер записи: 55
07-04-2016 дата публикации

Transmission circuit, integrated circuit, and parallel-to-serial conversion method

Номер: US20160099717A1
Автор: Masanori Yoshitani
Принадлежит: Socionext Inc

A transmission circuit includes: a shift register configured to shift, in synchronization with a first clock signal, input parallel data within a plurality of flip-flop circuits; a control circuit configured to output a second clock signal of a phase in accordance with a phase of the first clock signal; a selector configured to select any one of the input parallel data and pieces of output parallel data of the plurality of flip-flop circuits; and a conversion circuit configured to convert, in synchronization with the second clock signal, the parallel data selected by the selector into pieces of serial data, in which the control circuit outputs a selection signal to the selector, in accordance with a deviation amount of the detected phase of the first clock signal.

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Номер записи: 56
05-04-2018 дата публикации

Embedded Clock in Digital Communication System

Номер: US20180097611A1
Автор: Payne Robert Floyd
Принадлежит:

A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line. 1. A transmitter for transmitting a first data signal , a second data signal , and a clock signal on a four-wire system , the transmitter comprising:a first output for outputting the sum of the first data signal and the clock signal;a second output for outputting the clock signal minus the first data signal;a third output for outputting the second data signal minus the clock signal; anda fourth output for outputting the sum of the inverse of the second data signal and the inverse of the clock signal.2. The transmitter of claim 1 , further comprising:a first adder coupled to the first output, the first adder for adding the first data signal to the clock signal and subtracting a logic 1;a second adder coupled to the second output, the second adder for subtracting the first data signal from the clock signal;a third adder coupled to the third output, the third adder for subtracting the clock signal from the second data signal; anda fourth adder coupled to the fourth output, the fourth adder for subtracting the second data signal and the clock signal from a logic one.3. The transmitter of further comprising:a first differential pair having inputs of the clock signal and the inverse of the clock signal, the outputs of the first differential pair being coupled to the second output and the fourth output;a ...

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Номер записи: 57
12-04-2018 дата публикации

IMPEDANCE AND SWING CONTROL FOR VOLTAGE-MODE DRIVER

Номер: US20180102797A1
Автор: Chan Kok Lim, Chang Kun-Yung, Frans Yohan, Koay Chin Yang, Lim Siok Wei, Tan Kee Hian, Zhao Hongyuan
Принадлежит: XILINX, INC.

A driver circuit includes a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node. Each of the plurality of output circuits includes a series combination of a pair of inverters and a pair of resistors, coupled between the differential input and the differential output; first source terminals of the pair of inverters coupled to the first common node; and second source terminals of the pair of inverters coupled to the second common node. The driver circuit further includes a first voltage regulator having an output coupled to the first common node of the plurality of output circuits; a second voltage regulator having an output coupled to the second common node of the plurality of circuits; and a current compensation circuit coupled between the outputs of the first voltage regulator and the second voltage regulator. 1. A driver circuit , comprising: a series combination of a pair of enable circuits, a pair of inverters, and a pair of resistors, coupled between the differential input and the differential output;', 'a first transistor coupled between the first common node and first source terminals of the pair of inverters; and', 'a second transistor coupled between the second common node and second source terminals of the pair of inverters;, 'a plurality of output circuits coupled in parallel between a differential input and a differential output and having a first common node and a second common node, each of the plurality of output circuits comprisingfirst and second replica output circuits coupled in series between the first and second common nodes; anda control circuit coupled to each of: respective gates of the first and second transistors in each of the plurality of output circuits; and the first and second replica output circuits.2. The driver circuit of claim 1 , further comprising:a replica load resistor coupled in series between the first and second ...

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Номер записи: 58
04-04-2019 дата публикации

METHODS FOR ENABLING IN-FIELD SELECTION OF NEAR-SENSOR DIGITAL IMAGING FUNCTIONS

Номер: US20190104269A1
Автор: FRECHETTE Jonathan, GROSSMANN Peter J., STAMPLIS Matthew, THURMER Kate, TYRRELL BRIAN
Принадлежит: Massachusetts Institute of Technology

An imaging device is often paired with a readout integrated circuit (ROIC), which provides processing and data transfer functionality. The circuitry of a ROIC is typically specialized to meet the requirements of an application, which limits the ROIC to a few modes of operation and restricts compatibility to only certain types of imaging devices and applications. Furthermore, the circuitry supporting the processing functionality is limited due to size constraints on the ROIC. These shortcomings can be overcome with a field programmable imaging array (FPIA), which can be implemented as an integrated circuit combining customized ROIC sensor interface circuitry with field programmable gate array (FPGA) circuitry to enable post-fabrication definition of ROIC operational modes. An FPIA chip may form part of a three-chip stack that also includes an analog sensor interface chip for analog-to-digital conversion and an imaging device. 1. A field programmable imaging array (FPIA) chip , comprising:a substrate;a plurality of macropixel elements, disposed on the substrate, to process digital data, each one of the macropixel elements including non-reconfigurable circuitry; anda plurality of field programmable gate array (FPGA) elements, disposed on at least a portion of the substrate in electronic communication with the plurality of FPGA elements, to receive processed digital data from the plurality of macropixel elements.2. The FPIA chip of claim 1 , further comprising:a plurality of reconfigurable interconnects, disposed on the substrate, to reconfigurably connect the plurality of macropixel elements to the plurality of FPGA elements.3. The FPIA chip of claim 2 , wherein a first reconfigurable interconnect in the plurality of reconfigurable interconnects is configured to be dynamically reconfigured to electronically couple at least one FPGA element to each macropixel element.4. The FPIA chip of claim 2 , further comprising:a plurality of deserializer elements, disposed on the ...

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Номер записи: 59
10-07-2014 дата публикации

TIMING DEVICE AND METHOD

Номер: US20140191121A1
Автор: Sherwood Ian
Принадлежит: KRATOS ANALYTICAL LIMITED

The present invention provides a timing device, especially a timing device for use in mass spectrometers, for example TOF mass spectrometers, for processing trigger signal data containing a trigger signal indicating the occurrence of a trigger event, the timing device having: a trigger signal deserialiser configured to receive trigger signal data containing a trigger signal indicating the occurrence of a trigger event as serial data and to output the trigger signal data as parallel data, and wherein suitably the timing device has a processing means configured to process trigger signal data outputted by the trigger signal deserialiser as parallel data. 1. A timing device for processing trigger signal data containing a trigger signal indicating the occurrence of a trigger event , the timing device having:a trigger signal deserialiser configured to receive trigger signal data containing a trigger signal indicating the occurrence of a trigger event as serial data and to output the trigger signal data as parallel data.2. A timing device according to claim 1 , wherein the timing device has a processing means configured to process trigger signal data outputted by the trigger signal deserialiser as parallel data.3. A timing device according to selected from the group consisting of:a) a timing device wherein the processing means is configured to produce data based on trigger signal data outputted by the trigger signal deserialiser as parallel data;b) a timing device wherein the processing means is configured to detect a trigger signal contained in trigger signal data outputted by the trigger signal deserialiser as parallel data;c) a timing device wherein the processing means is configured to detect a trigger signal contained in trigger signal data outputted by the trigger signal deserialiser as parallel data, and to produce data based on the detected trigger signal such that the data produced by the processing means is synchronized to a trigger event indicated by the ...

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Номер записи: 60
19-04-2018 дата публикации

DECODER, RECEIVER, AND ELECTRONIC DEVICE

Номер: US20180109752A1
Автор: AOKI Takeshi, KOZUMA Munehiro, KUROKAWA Yoshiyuki
Принадлежит:

A decoder with reduced power consumption is provided. The decoder includes a first circuit and a second circuit for holding data. The second circuit includes a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor include an oxide semiconductor in a channel formation region. The third transistor includes silicon in a channel formation region. A gate of the second transistor is electrically connected to one of a source and a drain of the first transistor and a gate of the third transistor is electrically connected to one of a source and a drain of the second transistor. The decoder is configured to provide or stop power supply to the semiconductor device depending on a packet ID of a header portion of the data and to perform data storing or restoring of data between the first circuit and the second circuit. 1. A decoder configured to decode data , the decoder comprising: a first circuit; and', a first transistor;', 'a second transistor, a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor; and', 'a third transistor, a gate of the third transistor is electrically connected to one of a source and a drain of the second transistor,, 'a second circuit comprising], 'a semiconductor device comprisingwherein the first circuit is configured to hold data while power supply voltage is supplied,wherein the second circuit is configured to hold the data while power supply voltage is not supplied,wherein the first transistor and the second transistor comprise an oxide semiconductor in a channel formation region,wherein the third transistor comprises silicon in a channel formation region,wherein the decoder is configured to provide and stop power supply to the semiconductor device depending on an identifier of a header portion of the data, andwherein the decoder is configured to perform data storing and restoring of data between the first circuit and the second circuit ...

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Номер записи: 61
11-04-2019 дата публикации

TRANSMISSION DEVICE AND COMMUNICATION SYSTEM

Номер: US20190109734A1
Автор: SAEKI TAKANORI
Принадлежит:

A transmission device of the disclosure includes a first selector configured to select one of a first signal and a second signal, and output the selected signal; a second selector configured to select one of an inversion signal of the first signal, the second signal, and an inversion signal of the second signal, and output the selected signal; a first control signal generator configured to generate a first control signal, a second control signal, and a third control signal, based on the first signal, the second signal, and a third signal; a first driver configured to set a voltage of a first output terminal, based on an output signal of the first selector and the first control signal; and a second driver configured to set a voltage of a second output terminal, based on an output signal of the second selector and the second control signal. 1. A transmission device comprising:a transmitter includinga first selector configured toreceive a first serialized signal and a second serialized signal, andoutput a first signal based on the first serialized signal and the second serialized signal,a first driver configured to receive the first signal and a second signal, anda first output terminal that is electrically connected to the first driver,wherein the first driver is configured toin a first operation mode and based on the first signal and the second signal, selectively set a voltage of the first output terminal to one of a first voltage or a second voltage,in a second operation mode and based on the first signal and the second signal, exclusively set the voltage of the first output terminal to one of a third voltage, a fourth voltage, or a fifth voltage.2. The transmission device according to claim 1 ,wherein the transmitter further includesa second selector configured to output a third signal based on the second serialized signal and the inverted signal of the second serialized signal,', 'a third selector configured to', 'receive an inverted signal of the first ...

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Номер записи: 62
02-04-2020 дата публикации

NOISE CANCELLING CIRCUIT AND DATA TRANSMISSION CIRCUIT

Номер: US20200106439A1
Автор: FUNABASHI Masami, KATO Syuji, SHINMYO Akinori
Принадлежит:

A noise cancelling circuit includes: a first parallel-serial conversion circuit which converts inputted 2N-bit parallel data into serial data; an inverting circuit which inverts one of odd-numbered bits and even-numbered bits included in the inputted 2N-bit parallel data; a second parallel-serial conversion circuit which converts, into serial data, parallel data outputted by the inverting circuit and parallel data of the other one of the odd-numbered bits and the even-numbered bits included in the inputted 2N-bit parallel data which were not inverted; a first buffer which receives output data of the first parallel-serial conversion circuit; and a second buffer which receives output data of the second parallel-serial conversion circuit. 1. A noise cancelling circuit , comprising:a first parallel-serial conversion circuit which converts 2N-bit parallel data into serial data in synchronization with a clock signal, where N is a natural number of 1 or more;an inverting circuit which inverts one of odd-numbered bits and even-numbered bits included in the 2N-bit parallel data;a second parallel-serial conversion circuit which converts, into serial data in synchronization with the clock signal, parallel data outputted by the inverting circuit and parallel data of the other one of the odd-numbered bits and the even-numbered bits included in the 2N-bit parallel data which were not inverted;a first buffer which receives output data of the first parallel-serial conversion circuit; anda second buffer which receives output data of the second parallel-serial conversion circuit, whereinthe first parallel-serial conversion circuit and the second parallel-serial conversion circuit are formed using substantially a same kind of circuit,the first buffer and the second buffer are formed using substantially a same kind of circuit, andthe first buffer and the second buffer are connected to a common power source and connected to a common ground.2. The noise cancelling circuit according to ...

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Номер записи: 63
02-04-2020 дата публикации

ENCODING AND DECODING ARCHITECTURE FOR HIGH-SPEED DATA COMMUNICATION SYSTEM AND RELATED PHYSICAL LAYER CIRCUIT, TRANSMITTER AND RECEIVER AND COMMUNICATION SYSTEM THEREOF

Номер: US20200106457A1
Автор: CHANG CHING-HSIANG
Принадлежит:

A physical layer circuit at a transmitter includes an encoding chain and a plurality of flip-flops. The encoding chain, including encoding units coupled in series, is configured to encode a plurality of symbols to generate a plurality of first wire states. The encoding units are arranged to receive the symbols respectively, and convert respective symbol values of the symbols to the first wire states respectively. A first encoding unit is configured to convert a symbol value of a corresponding symbol according to a second wire state provided by a second encoding unit. The flip-flops are arranged to receive and output the first wire states according to a clock signal, respectively. One of the flip-flops is coupled between the first encoding unit and the second encoding unit. The second wire state provided by the second encoding unit is sent to the first encoding unit through the one of the flip-flops. 1. A physical layer circuit at a transmitter , comprising: 'a plurality of encoding units coupled in series, arranged to receive the symbols respectively, and convert respective symbol values of the symbols to the first wire states respectively, wherein a first encoding unit of the encoding units is configured to convert a symbol value of a corresponding symbol according to a second wire state provided by a second encoding unit of the encoding units; and', 'an encoding chain, configured to encode a plurality of symbols to generate a plurality of first wire states, the encoding chain comprisinga plurality of first flip-flops, coupled to the encoding units to receive the first wire states respectively, the first flip-flops being arranged to output the first wire states according to a first clock signal, respectively, wherein one of the first flip-flops is coupled between the first encoding unit and the second encoding unit, and the second wire state provided by the second encoding unit is sent to the first encoding unit through the one of the first flip-flops.2. The ...

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Номер записи: 64
07-05-2015 дата публикации

SERIALIZERS

Номер: US20150123826A1
Автор: LEE Hyeng Ouk, LEE Sang Kwon
Принадлежит: SK HYNIX INC.

Serializers are provided. The serializer includes a first drive control signal generator and a second drive control signal generator. The first drive control signal generator amplifies a first input data signal in response to a first clock signal and a second clock signal to generate a first pull-up drive control signal and a first pull-down drive control signal. The second drive control signal generator amplifies a second input data signal in response to the second clock signal and a third clock signal to generate a second pull-up drive control signal and a second pull-down drive control signal. 1. A serializer comprising:a first drive control signal generator suitable for amplifying a first input data signal in response to a first clock signal and a second clock signal to generate a first pull-up drive control signal and a first pull-down drive control signal; anda second drive control signal generator suitable for amplifying a second input data signal in response to the second clock signal and a third clock signal to generate a second pull-up drive control signal and a second pull-down drive control signal.2. The serializer of claim 1 , wherein the first clock signal precedes the second clock signal by a set phase.3. The serializer of claim 1 , wherein the first clock signal precedes the second clock signal by a phase of about 90 degrees.4. The serializer of claim 3 , wherein the first drive control signal generator amplifies the first input data while the first and second clock signals have a predetermined logic level combination.5. The serializer of claim 3 , wherein the second clock signal precedes the third clock signal by a phase of about 90 degrees.6. The serializer of claim 5 , wherein the second drive control signal generator amplifies the second input data while the second and third clock signals have a predetermined logic level combination.7. The serializer of claim 1 , further comprising an output drive signal generator suitable for buffering the first ...

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Номер записи: 65
27-04-2017 дата публикации

DATA LINE DRIVING CIRCUIT, DATA LINE DRIVER AND DISPLAY DEVICE INCLUDING THE SAME

Номер: US20170116906A1
Автор: CAI Zong-Hua, LIN Ching-Chih, Tai Ya-Hsiang
Принадлежит:

A data line driving circuit for a display device having a plurality of data lines is provided to include a plurality of data line drivers respectively coupled to the data lines. Each data line driver includes a register unit to store video data having a pixel value, a pulse width modulation unit generating a PWM signal having a pulse width positively correlated with the pixel value, and a charge-discharge unit performing charge-discharge operation to generate a data voltage on a respective one of the data lines according to the PWM signal. A magnitude of voltage variation on the respective data line is positively correlated with the pulse width of the PWM signal during the charge-discharge operation. 1. A data line driving circuit for a display device having a plurality of data lines , said data line driving circuit comprising: a register unit to store video data having a pixel value;', 'a pulse width modulation (PWM) unit coupled to said register unit for receiving the video data therefrom, and generating a PWM signal having a pulse width positively correlated with the pixel value of the video data; and', 'a charge-discharge unit coupled to said PWM unit for receiving the PWM signal therefrom, to be coupled to a respective one of the data lines, and generating a data voltage on the respective one of the data lines by performing charge-discharge operation on the respective one of the data lines according to the PWM signal, a magnitude of voltage variation on the respective one of the data lines being positively correlated with the pulse width of the PWM signal during the charge-discharge operation., 'a plurality of data line drivers to be respectively coupled to the data lines, each of said data line drivers including2. The data line driving circuit of claim 1 , wherein said PWM unit includes:a counter to generate a counter signal that indicates a counting number; anda comparator coupled to said register unit and said counter for respectively receiving the video ...

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Номер записи: 66
05-05-2016 дата публикации

DISPLAY SYSTEM AND CONVERSION APPARATUS

Номер: US20160125835A1
Автор: KIM In-beom, UM Soo-hyun, YONG Seok-woo
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A display system and a conversion apparatus are provided. The display system includes an image signal input apparatus configured to convert a first parallel image signal to a serial image signal, a conversion apparatus configured to convert the serial image signal to a second parallel image signal, and a display apparatus configured to process the second parallel image signal, and display the processed second parallel image signal. The conversion apparatus is attachable to and detachable from the display apparatus. 1. A display system comprising:an image signal input apparatus configured to convert a first parallel image signal to a serial image signal;a conversion apparatus configured to convert the serial image signal to a second parallel image signal; anda display apparatus configured to process the second parallel image signal, and display the processed second parallel image signal,wherein the conversion apparatus is attachable to and detachable from the display apparatus.2. The display system as claimed in claim 1 , wherein the conversion apparatus comprises:a first connector configured to be coupled to the display apparatus;a second connector configured to be coupled to the image signal input apparatus, and receive the serial image signal from the image signal input apparatus; anda serializer/deserializer (SerDes) configured to convert the serial image signal to the second parallel image signal,wherein the first connector is further configured to transmit the second parallel image signal to the display apparatus.3. The display system as claimed in claim 2 , wherein the conversion apparatus further comprises power supplies configured to supply powers to the first connector claim 2 , the second connector claim 2 , and the SerDes.4. The display system as claimed in claim 3 , wherein the power supplies are separated by a bead.5. The display system as claimed in claim 3 , wherein the powers have respective voltages differently set from each other claim 3 , andthe ...

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Номер записи: 67
05-05-2016 дата публикации

COMMUNICATION APPARATUS, IMAGE FORMING APPARATUS, COMMUNICATION METHOD, AND COMPUTER-READABLE STORAGE MEDIUM

Номер: US20160126977A1
Автор: Abe Yasuhiro, HIGASHIYAMA Makoto, MIYADERA Tatsuya, OHMIYA Satoshi, OHYAMA Tatsuo, Oikawa Masahiko, SHUKUYA Yuichiro
Принадлежит:

A communication apparatus includes a serializer configured to convert parallel data into serial data and output the serial data; and a deserializer configured to convert the serial data output from the serializer into parallel data and output the parallel data. The serializer is configured to add first data used for detecting unique data in the parallel data before the unique data, add second data used for detecting the unique data after the unique data, and add third data whose length is variable to each of the first data and the second data. 1. A communication apparatus comprising:a serializer configured to convert parallel data into serial data and output the serial data; anda deserializer configured to convert the serial data output from the serializer into parallel data and output the parallel data,wherein the serializer is configured to add first data used for detecting unique data in the parallel data before the unique data, add second data used for detecting the unique data after the unique data, and to interleave third data whose length is variable into each of the first data and the second data.2. The communication apparatus according to claim 1 , wherein the unique data is image data.3. The communication apparatus according to claim 1 , wherein the parallel data is 10-bit data generated by 8B/10B conversion.4. The communication apparatus according to claim 1 , wherein the serializer is configured to stationarily add fourth data to an outside of the parallel data.5. The communication apparatus according to claim 4 , wherein the first data claim 4 , the second data claim 4 , the third data claim 4 , and the fourth data are each any one of a plurality of types of symbol codes for the 8B/10B conversion.6. The communication apparatus according to claim 5 , wherein the third data is any one of K28.5 claim 5 , K28.1 claim 5 , K28.2 claim 5 , K28.3 claim 5 , and K28.6.7. The communication apparatus according to claim 5 , wherein the fourth data is any one of K28. ...

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Номер записи: 68
27-05-2021 дата публикации

DATA TRANSMISSION CIRCUIT, DISPLAY DEVICE AND DATA TRANSMISSION METHOD

Номер: US20210158774A1
Автор: He Zongze, LAN Ronghua, Zhang Junrui, Zhang Yehao, Zhu Xuehui
Принадлежит:

The embodiments of the present disclosure provide a data transmission circuit, a display device and a data transmission method. The data transmission circuit includes a serial-to-parallel conversion circuit configured to receive serial data and a mode setting signal, generate a mode selection signal according to the mode setting signal, and convert the serial data into parallel data with a corresponding bit width according to the mode selection signal; a control signal generating circuit configured to generate a control signal based on the mode setting signal; and a latch circuit connected to the serial-to-parallel conversion circuit and the control signal generating circuit, and being configured to receive the parallel data from the serial-to-parallel conversion circuit and the control signal from the control signal generating circuit, and latch and output the received parallel data under the control of the control signal. 1. A data transmission circuit , comprising:a serial-to-parallel conversion circuit configured to receive serial data and a mode setting signal, generate a mode selection signal according to the mode setting signal, and convert the serial data into parallel data with a corresponding bit width according to the mode selection signal;a control signal generating circuit configured to generate a control signal based on the mode setting signal; anda latch circuit connected to the serial-to-parallel conversion circuit and the control signal generating circuit, and being configured to receive the parallel data from the serial-to-parallel conversion circuit and the control signal from the control signal generating circuit, and latch and output the received parallel data under the control of the control signal.2. The data transmission circuit according to claim 1 , wherein the serial-to-parallel conversion circuit is further configured to generate a plurality of mode signals respectively for a plurality of modes claim 1 , wherein the mode signals are used ...

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Номер записи: 69
16-04-2020 дата публикации

DATA DISTRIBUTION METHOD, DATA AGGREGATION METHOD, AND RELATED APPARATUSES

Номер: US20200120017A1
Автор: Wang Xinyuan, Yang Wenbin
Принадлежит: Huawei Technologies CO.,Ltd.

A data distribution method, a data aggregation method, and related apparatuses are disclosed. The data distribution method may include: receiving a first packet stream; dividing the first packet stream to obtain a first data block stream; sending the first data block stream to a first circuit; processing, by the first circuit, the first data block stream to obtain a first data stream; distributing, by the first circuit, the first data stream to N1 second circuits of M second circuits in a PT-W, where M is greater than N1, N1 is a positive integer, and M is a positive integer; and processing, by the N1 second circuits, the received first data stream to obtain N1 first code streams. The technical solutions provided by the embodiments of the present application help to meet a requirement for complex bandwidth configuration and extend an application scenario. 1. A data distribution method , comprising:receiving, by a first circuit, a first data stream;distributing, by the first circuit, the first data stream to a first subset of second circuits, wherein the first subset comprises more than one of the second circuits; andprocessing, by the first subset of the second circuits, the distributed first data stream to generate unique first code streams, that correspond to each one of the first subset of the second circuits.2. The method of claim 1 , wherein the first circuit comprises a receiving circuit to receive a first data block stream as the first data stream claim 1 , wherein each second circuit comprises a physical layer encoding circuit claim 1 , a scrambling circuit claim 1 , and an alignment marker insertion circuit claim 1 , and wherein the generated first code streams are obtained via a physical layer encoding circuit claim 1 , a scrambling circuit and an alignment marker insertion circuit of the each one of the first subset of the second circuits.3. The method of claim 1 , wherein the first circuit comprises a physical layer encoding circuit claim 1 , wherein the ...

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Номер записи: 70
07-08-2014 дата публикации

Techniques For Alignment of Parallel Signals

Номер: US20140218221A1
Автор: Mendel David, Wortman Curt
Принадлежит: Altera Corporation

Receiver circuits in serial lanes each generate a synchronous clock signal that is aligned with a master clock signal to allow synchronous transfer of data onto the master clock domain without corruption. A serial-to-parallel converter circuit in each receiver circuit converts a serial data signal into parallel data signals in response to one of the synchronous clock signals. Phase detection circuitry generates an indication of a phase shift based on a phase offset between the synchronous and master clock signals. A clock signal generation circuit provides an adjustment to a phase of the synchronous clock signal based on the indication of the phase shift. The serial-to-parallel converter circuit adjusts positions of bits indicated by the parallel data signals based on the adjustment to the phase of the synchronous clock signal. 1. A circuit comprising:a serial-to-parallel converter circuit to convert a serial data signal into first parallel data signals;phase detection circuitry to generate an indication of a phase shift based on a phase offset between a first periodic signal and a second periodic signal; anda clock signal generation circuit to provide an adjustment to a phase of the first periodic signal based on the indication of the phase shift, the serial-to-parallel converter circuit to adjust a word boundary to a different one of the first parallel data signals based on the adjustment to the phase of the first periodic signal.2. The circuit of further comprising:a barrel shifter circuit to generate second parallel data signals based on the first parallel data signals, wherein the barrel shifter circuit adjusts positions of bits indicated by the second parallel data signals relative to positions of bits indicated by the first parallel data signals to shift a word boundary in the second parallel data signals.3. The circuit of claim 2 , wherein the barrel shifter circuit comprises storage circuits to store values of the first parallel data signals in response to ...

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Номер записи: 71
28-05-2015 дата публикации

DIGITAL SERIAL-TO-PARALLEL CONVERTER AND GaAs MMIC USING THE SAME

Номер: US20150145707A1
Автор: JEONG Jin-Cheol, JU In-Kwon, SHIN Dong-Hwan, YOM In-Bok
Принадлежит:

A digital serial-to-parallel converter capable of minimizing a malfunction of a circuit by more stably performing an operation of a D flip flop in implementing a GaAs MMIC digital serial-to-parallel converter and a GaAs MMIC using the same are disclosed. The digital serial-to-parallel converter includes: a converter configured to convert a received clock signal, serial data, and load signal of TTL into a DCFL signal; a plurality of D flip flops configured to transmit the serial data received through the converter to a D flip flop of a next stage by the clock signal received through the converter and output the serial data of the D flip flop of the next stage by the load signal received through the converter; and a plurality of buffers configured to receive the serial data from the plurality of D flip flops to generate and output complementary signals. 1. A digital serial-to-parallel converter , comprising:a converter configured to convert a received clock signal, serial data, and load signal of TTL into a DCFL signal;a plurality of D flip flops configured to transmit the serial data received through the converter to a D flip flop of a next stage by the clock signal received through the converter and output the serial data of the D flip flop of the next stage by the load signal received through the converter; anda plurality of buffers configured to receive the serial data from the plurality of D flip flops to generate and output complementary signals.2. The digital serial-to-parallel converter of claim 1 , wherein the plurality of D flip flops are each operated by one input signal and one output signal.3. The digital serial-to-parallel converter of claim 1 , wherein the plurality of D flip flops each include a plurality of 2-input NOR gates and one 3-input NOR gate.4. The digital serial-to-parallel converter of claim 1 , wherein the plurality of buffers each include two inverters which are connected in series.5. The digital serial-to-parallel converter of claim 4 , ...

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Номер записи: 72
21-08-2014 дата публикации

LOW POWER QUANTIZER FOR ANALOG TO DIGITAL CONVERTER

Номер: US20140232579A1
Автор: BRASWELL BRANDT, KABIR Mohammad Nizam, Shiwale Rakesh
Принадлежит:

A quantizer includes a voltage reference network and a set of comparators coupled with the voltage reference network. The voltage reference network generates a plurality of reference voltages. Each of the comparators receives an input signal and produces a sequence of digital samples. The set of comparators includes first, second, and third subsets of comparators. Each comparator of the first subset includes a switched capacitor stage, each comparator of the second subset includes a preamplifier stage, and each comparator of the third subset includes a switched capacitor stage. The first and third subsets of comparators compares the input signal with reference voltages corresponding to the upper and lower voltage ranges of the input signal, and the second subset of comparators compares the input signal with reference voltages corresponding to the middle voltage range of the input signal. 1. A quantizer comprising:a voltage reference network configured to generate a plurality of reference voltages; anda set of comparators coupled with said voltage reference network, each of said comparators being configured to receive an input signal and produce a sequence of digital samples, wherein said set of comparators comprises:a first subset of comparators, each comparator of said first subset including a first switched capacitor stage;a second subset of comparators, each comparator of said second subset including a preamplifier stage; anda third subset of comparators, each comparator of said third subset including a second switched capacitor stage.2. A quantizer as claimed in wherein:said first subset of comparators is configured to compare said input signal with a first set of reference voltages, said first set of reference voltages corresponding to an upper voltage range of said input signal;said second subset of comparators is configured to compare said input signal with a second set of reference voltages, said second set of reference voltages corresponding to a middle ...

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Номер записи: 73
25-05-2017 дата публикации

LEVEL SHIFTER AND PARALLEL-TO-SERIAL CONVERTER INCLUDING THE SAME

Номер: US20170149435A1
Автор: Song Taek-Sang
Принадлежит:

A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a negative input terminal, respectively and to output signals that may vary in a second range to a positive output terminal and a negative output terminal, respectively, where the second range is larger than the first range, a first pre-charging unit configured to pre-charge the positive output terminal to a predetermined level when a clock is in a first level, and a second pre-charging unit configured to pre-charge the negative output terminal to the predetermined level when the clock is in the first level. 17-. (canceled)8. A parallel-to-serial converter , comprising:a first level shifter suitable for shifting a level of a first input signal having a first variable amplitude to output first output signals having a second variable amplitude, to an output line; anda second level shifter suitable for shifting a level of a second input signal having the first variable amplitude to output second output signals having the second variable amplitude to the output line,wherein the first and level shifters are alternately enabled based on a clock.9. The parallel-to-serial converter according to claim 8 , wherein the first level shifter includes claim 8 ,a first level shifting unit suitable for receiving the first input signal to generate the first output signals through a first output terminal and a first complementary output terminal, when the clock is in a first level;a first pre-charging unit suitable for pre-charging the first output terminal by a pre-charging voltage having a predetermined level when the clock is in a second level,a second pre-charging unit suitable for pre-charging the first complementary output terminal by the pre-charging voltage when the clock is in the second level, anda first transferring unit suitable for transferring the first output signals from the first output terminal and the first ...

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Номер записи: 74
15-09-2022 дата публикации

MINIMUM INTRINSIC TIMING UTILIZATION AUTO ALIGNMENT ON MULTI-DIE SYSTEM

Номер: US20220294435A1
Автор: HSU Ying-Yu
Принадлежит: MEDIATEK INC.

The present invention provides a system including a transmitter and a receiver is disclosed. The transmitter includes a first main data path and a first main strobe path, wherein the first main data path is configured to generate a plurality of data signals, the first main strobe path is configured to generate a first strobe signal, and delay amount of the first main data path and delay amount of the first main strobe path are unbalanced. The receiver includes a second main data path and a second main strobe path, wherein the second main strobe path is configured to receive the first strobe signal to generate a plurality of second strobe signals, and the second main data path is configured to receive the plurality of data signals, and uses the plurality of second strobe signals to sample the plurality of data signals to generate a plurality of sampled signals, respectively. 1. A system , comprising:a transmitter, comprising a first main data path and a first main strobe path, wherein the first main data path is configured to generate a plurality of data signals, the first main strobe path is configured to generate a first strobe signal, the first main data path comprises a first delay circuit, the first main strobe path comprises a second delay circuit, and delay amount of the first main data path and delay amount of the first main strobe path are unbalanced so that the strobe signal and the plurality of data signals are not aligned; anda receiver, comprising a second main data path and a second main strobe path, wherein the second main strobe path is configured to receive the first strobe signal to generate a plurality of second strobe signals, and the second main data path is configured to receive the plurality of data signals, and uses the plurality of second strobe signals to sample the plurality of data signals to generate a plurality of sampled signals, respectively;a deskew circuit, configured to generate a first control signal and a second control signal to ...

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Номер записи: 75
16-05-2019 дата публикации

TRANSMISSION DEVICE, TRANSMISSION SYSTEM, AND ROBOT

Номер: US20190149161A1
Автор: Komine Naoki, MASUDA Hiromasa, YASUDA Hirokazu
Принадлежит: SONY CORPORATION

There is provided a transmission device configured to serialize data of a change amount that is based on a signal acquired from a sensor, and transmit the data by simplex communication. 1. A transmission device configured to serialize data of a change amount that is based on a signal acquired from a sensor , and transmit the data by simplex communication.2. The transmission device according to claim 1 , comprising:a serializer configured to serialize the data of the change amount, and transmit the serialized data by the simplex communication.3. The transmission device according to claim 1 , comprising:an analog-to-digital conversion circuit configured to convert a signal into a digital signal, the signal being acquired from the sensor that outputs an analog signal,wherein the data of the change amount that is to be serialized is data converted by the analog-to-digital conversion circuit.4. The transmission device according to claim 3 , wherein the analog-to-digital conversion circuit is a delta sigma type analog-to-digital converter.5. The transmission device according to claim 1 , wherein the data of the change amount that is to be serialized is a signal acquired from the sensor that outputs a digital signal.6. The transmission device according to claim 1 , wherein the sensor includes an incremental encoder.7. The transmission device according to claim 1 , wherein the simplex communication is wired communication.8. A transmission system comprising:a transmission device configured to serialize data of a change amount that is based on a signal acquired from a sensor, and transmit the data by simplex communication; anda receiving device configured to receive data transmitted by the simplex communication, and deserialize the data.9. The transmission system according to claim 8 , wherein the sensor and the transmission device are provided in a robot including a robot arm having one end connected to a main body and another end that is made movable claim 8 , on the other ...

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Номер записи: 76
23-05-2019 дата публикации

DATA OUTPUT CIRCUIT, MEMORY DEVICE INCLUDING THE DATA OUTPUT CIRCUIT, AND OPERATING METHOD OF THE MEMORY DEVICE

Номер: US20190156870A1
Автор: KIM Yongjun, Lee Chang-Yong, Park Hyunsoo
Принадлежит:

A memory device includes a memory cell array storing input data, a clock generator circuit generating first clocks and second clocks using a reference clock, a phase information generator circuit comparing a phase of the reference clock and a phase of at least one of the first clocks and the second clocks and generating phase information as a comparison result, an intermediate data generator circuit serializing a part of input data provided from the memory cell array based on the first clocks to generate first data, serializing a remaining part of the input data to generate second data, and selectively swapping the first data and the second data using the phase information to generate intermediate data, and an output data generator circuit serializing the intermediate data using the second clocks, to output output data through one output data line. 1. A memory device comprising:a memory cell array configured to store input data;a clock generator circuit configured to generate first clocks and second clocks, using a reference clock;a phase information generator circuit configured to compare a phase of the reference clock and a phase of at least one of the first clocks and the second clocks, and to generate phase information as the comparison result;an intermediate data generator circuit configured to serialize a part of the input data provided from the memory cell array using the first clocks to generate a plurality of first data, to serialize a remaining part of the input data to generate a plurality of second data, and to selectively swap the plurality of first data and the plurality of second data using the phase information to generate a plurality of intermediate data; andan output data generator circuit configured to serialize the plurality of intermediate data using the second clocks, to output output data through one output data line.2. The memory device of claim 1 , wherein a frequency of the first clocks is substantially the same as a frequency of the ...

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Номер записи: 77
22-09-2022 дата публикации

METHOD AND APPARATUS FOR SENDING AND RECEIVING CLOCK SYNCHRONIZATION PACKET

Номер: US20220303035A1
Автор: Chen Jingfeng, HE XIANG, Lin Tao, Qi Yunlei, Song Junmin, Wang Xinyuan
Принадлежит: Huawei Technologies Co., Ltd.

This disclosure provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet. 1. A method for sending a clock synchronization packet in flexible Ethernet (FlexE) , comprising:encoding a clock synchronization packet;generating a plurality of data blocks including a first data block for data sampling based on the encoded clock synchronization packet; andtransmitting the plurality of data blocks in a client payload of FlexE.2. The method according to claim 1 , including generating indication information to trigger sampling of the first data block.3. The method according to claim 2 , wherein the indication information comprises one of out-of-band information or in-band information.4. The method according to claim 2 , wherein the indication information indicates a data block associated with a start-of-frame delimiter claim 2 , SFD.5. The method according to claim 4 , wherein the indication information indicates a data block corresponding to the SFD claim 4 , or claim 4 , the indication information indicates a data block corresponding to a first symbol after the SFD.6. The method according to ...

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Номер записи: 78
23-05-2019 дата публикации

ENCODING AND DECODING ARCHITECTURE FOR HIGH-SPEED DATA COMMUNICATION SYSTEM AND RELATED PHYSICAL LAYER CIRCUIT, TRANSMITTER AND RECEIVER AND COMMUNICATION SYSTEM THEREOF

Номер: US20190158127A1
Автор: LU YUEH-CHUAN
Принадлежит:

The present invention proposes an inventive encoding and decoding architecture for use in a physical layer of a high-speed serial data communication system, such as, MIPI C-PHY. Embodiments of the present invention include encoding chains and decoding chains adaptable to physical layer circuits of transmitters and receivers, respectively. The physical layer circuit of a transmitter includes: an encoding chain and a parallel-to-serial (P2S) converter. The encoding chain having a plurality of encoding unit coupled in series, and is arranged to receive a plurality of first symbols and convert each of the symbols to a corresponding wire state, thereby to generate a plurality of wire states. The P2S converter is coupled to the encoding chain, arranged to receive the plurality of wire states and serialize the plurality of wire states to provide a sequence of wire states. 1. A physical layer circuit at a transmitter , comprising:an encoding chain, having a plurality of encoding units coupled in series, arranged to receive a plurality of first symbols and convert a symbol value of each of the plurality of first symbols to a corresponding wire state, thereby to generate a plurality of wire states; anda parallel-to-serial (P2S) converter, coupled to the encoding chain, arranged to receive the plurality of wire states and serialize the plurality of wire states to provide a sequence of wire states.2. The physical layer circuit of claim 1 , wherein at least one of the plurality of encoding units is arranged to convert the symbol value according to the symbol value and a previous wire state generated by a previous one of the encoding units in series claim 1 , thereby to derive a present wire state.3. The physical layer circuit of claim 1 , further comprising:a mapper coupled to the encoding chain, arranged to receive a word of data and map the word of data to generate at least the plurality of first symbols during a cycle of operation.4. The physical layer circuit of claim 3 , ...

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Номер записи: 79
18-06-2015 дата публикации

CONFIGURABLE MULTI-MODE MEDIA INDEPENDENT INTERFACE

Номер: US20150171892A1
Автор: Yu Hongchun
Принадлежит:

A configurable media independent interface in an integrated circuit device includes a first plurality of channels and a second plurality of channels, wherein each channel of the first and second pluralities includes a transmit path. The interface also includes a first serializer configurable to serialize transmit data for the first and second pluralities of channels in a first mode and to serialize transmit data for the first plurality of channels in a second mode, and a second serializer configurable to be disabled in the first mode and to serialize data for the second plurality of channels in the second mode. 1. A configurable media independent interface in an integrated circuit device , comprising:a first plurality of channels, wherein each channel of the first plurality comprises a transmit path;a second plurality of channels, wherein each channel of the second plurality comprises a transmit path;a first serializer configurable to serialize transmit data for the first and second pluralities of channels in a first mode and to serialize transmit data for the first plurality of channels in a second mode; anda second serializer configurable to be disabled in the first mode and to serialize transmit data for the second plurality of channels in the second mode.2. The media independent interface of claim 1 , wherein each channel of the first and second pluralities of channels further comprises a receive path claim 1 , and the media independent interface further comprises:a first deserializer configurable to de-serialize receive data for the first and second pluralities of channels in the first mode and to de-serialize receive data for the first plurality of channels in the second mode; anda second deserializer configurable to be disabled in the first mode and to de-serialize receive data for the second plurality of channels in the second mode.3. The media independent interface of claim 1 , further comprising a third plurality of channels configurable to transmit idle ...

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Номер записи: 80
24-06-2021 дата публикации

CENTRALIZED FIXED RATE SERIALIZER AND DESERIALIZER FOR BAD COLUMN MANAGEMENT IN NON-VOLATILE MEMORY

Номер: US20210193226A1
Автор: CHEN CHEN, Li YenLung, Peng Min, Watanabe Mitsuyuki
Принадлежит: SanDisk Technologies LLC

In a non-volatile memory circuit, performance is improved by converting data between a serial format, for transfer on and off of the memory circuit, and a parallel format, for transfer to and from the memory latches used for read and writing data into the memory array of the memory circuit. The memory array is split into M+N divisions, but transferred with a degree of parallelism of M, allowing M words of data to be transferred in parallel at a fixed transfer rate while allowing for up to N bad columns in a transfer. In the write path, a column skipping mechanism is used when converting words of write data into a parallel format. In the read path, a set of (M+N) to 1 multiplexers is used to align the word of read data so that read data can be transferred at a fixed rate and without any added latency. 1. An apparatus , comprising:an array of non-volatile memory cells formed along a plurality of word lines and a plurality of columns, the columns being divided into a plurality of M+N divisions, each of the divisions formed of a plurality of contiguous columns, wherein the word lines span columns of the array, M is an integer greater than 1, and N is an integer greater than or equal to 1;M+N sets of data latches, each set of data latches connectable to the columns of a corresponding one of the M+N divisions and each configured to hold data being transferred between the sot of data latches and the corresponding division;an input/output circuit configured to transfer data on and off of the apparatus serially;a serializer/deserializer circuit connected to the input/output circuit and selectively connectable to M of the M+N sets of data latches and configured to transfer data between a selected M sets of the data latches and the input/output circuit; andone or more control circuits connected to the M+N sets of data latches and the serializer/deserializer circuit, the one or more control circuits configured to transfer data between the input/output circuit and the sets of ...

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Номер записи: 81
15-06-2017 дата публикации

Path encoding and decoding

Номер: US20170170843A1
Автор: Frederic J. Bauchot, Marc Joel Herve Legroux
Принадлежит: International Business Machines Corp

This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure definition including a starting empty cell; one or more path definitions defining paths through the data structure; a character reading and writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by methodically checking cells along one of the paths in the data structure until an empty cell is located; a loop facilitator for looping back to the writing next character step and the determining next cell step until there are no more data characters or a next empty cell is not determined; and a serialization deserialization engine for methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.

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Номер записи: 82
23-06-2016 дата публикации

PATH ENCODING AND DECODING

Номер: US20160182085A1
Автор: Bauchot Frederic J., Legroux Marc Joel Herve
Принадлежит:

This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure definition including a starting empty cell; one or more path definitions defining paths through the data structure; a character reading and writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by methodically checking cells along one of the paths in the data structure until an empty cell is located; a loop facilitator for looping back to the writing next character step and the determining next cell step until there are no more data characters or a next empty cell is not determined; and a serialization deserialization engine for methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters. 1. A system for encoding an input string of binary characters , comprising:a register for cellular data structure definition including a starting empty cell;a register for one or more path definitions defining paths through the data structure;a character reading and writing engine for writing a binary character to an empty cell with a predefined initial position;a next cell determination engine for determining a next empty cell by methodically checking cells along one of the paths in the data structure until an empty cell is located;a loop facilitator for looping back to the writing next character step and the determining next cell step until there are no more data characters or a next empty cell is not determined; anda serialization deserialization engine for methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.2. A system according to claim 1 , wherein methodically checking cells along the path comprises traversing cells ...

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Номер записи: 83
18-09-2014 дата публикации

Interleaved multipath digital power amplification

Номер: US20140266820A1
Автор: Donald R. Laturell, James F. MacDonald, Peter Kiss, Ross S. Wilson, Said E. Abdelli
Принадлежит: LSI Corp

In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.

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Номер записи: 84
22-06-2017 дата публикации

SR LATCH CIRCUIT WITH SINGLE GATE DELAY

Номер: US20170179934A1
Автор: LOVITT Travis William
Принадлежит:

An SR latch circuit with single gate delay is provided. The circuit has an an enable input and an SR latch. There is first input stage having an input for receiving a set input and having an output for producing a first component of the SR latch circuit output, the first input stage having only one transistor that receives the enable input, the first input stage becoming transparent while enabled, the first input stage having a single gate delay between the input of the first input stage and the output of the first input stage. There is a second input stage having an input for receiving a reset input and having an output for producing a second component of the SR latch circuit output, the second input stage having only one transistor that receives the enable input, the second input stage becoming transparent while enabled, the second input stage having a single gate delay between the input of the second input stage and the output of the second input stage. 1. An SR latch circuit having an enable input and an SR latch circuit output , the SR latch circuit comprising:a first input stage having an input for receiving a set input and having an output for producing a first component of the SR latch circuit output, the first input stage configured to receive an enable input in advance of set an reset inputs becoming valid, the enable input causing the first input stage to become transparent while enabled, the first input stage having a single gate delay between the input of the first input stage and the output of the first input stage;a second input stage having an input for receiving a reset input and having an output for producing a second component of the SR latch circuit output, the second input stage configured to receive the enable input in advance of set and reset inputs becoming valid, the enable input causing the second input stage to become transparent while enabled, the second input stage having a single gate delay between the input of the second input stage ...

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Номер записи: 85
02-07-2015 дата публикации

LOW LATENCY DATA DESERIALIZER

Номер: US20150188567A1
Автор: Liu Yong
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A deserializer includes an input interface configured to receive an N-bit serialized stream at a source clock frequency; a modified-tree deserializing architecture that receives the first N−1 bits of the serialized stream from the input interface and generates N−1 parallel outputs corresponding to the first N−1 bits; and a last-bit flip-flop that directly samples the input interface to obtain an Nth bit, such that all N bits are available within one source clock cycle after the Nth bit arrives at the input interface. 1. A deserializer , comprising:an input interface configured to receive an N-bit serialized stream at a source clock frequency;a modified-tree deserializing architecture that receives the first N−1 bits of the serialized stream from the input interface and generates N−1 parallel outputs corresponding to the first N-1 bits; anda last-bit flip-flop that directly samples the input interface to obtain an Nth bit, such that all N bits are available within one source clock cycle after the Nth bit arrives at the input interface.2. The deserializer of claim 1 , wherein the input interface is a flip-flop triggered at the source clock frequency.3. The deserializer of claim 1 , wherein the input interface is a deserializer block triggered at half the source clock frequency.4. The deserializer of claim 1 , wherein the last-bit flip-flop is triggered at sub-rate frequency that is 1/N of the source clock frequency.5. The deserializer of claim 1 , wherein the modified-tree deserializing architecture comprises N−1 output flip-flop triggered at UN of the source clock frequency.6. The deserializer of claim 5 , wherein all flip-flops other than the N−1 output flip-flops and the last-bit flip-flop are triggered on inverted waveforms.7. The deserializer of claim 5 , wherein all flip-flops other than the N−1 output flip-flops and the last-bit flip-flop are triggered on an edge opposite to that of the N−1 output flip-flops.8. The deserializer of claim 1 , wherein each flip- ...

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Номер записи: 86
28-06-2018 дата публикации

SEEMINGLY MONOLITHIC INTERFACE BETWEEN SEPARATE INTEGRATED CIRCUIT DIE

Номер: US20180183463A1
Автор: Duwel Keith, Jones Jakob Raymond, Mendel David W., Ngo Huy, Schulz Jeffrey Erik
Принадлежит:

A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die. 1. A method comprising:sampling a plurality of signals stored in a first parallel interface on a first integrated circuit die, wherein a first one of the plurality of signals is sampled more often than a second one of the plurality of signals;generating a serial signal based on the plurality of signals; andtransmitting the serial signal.2. The method of claim 1 , comprising:receiving the serial signal at a second integrated circuit die;obtaining the plurality of signals based on the serial signal; andstoring the plurality of signals in a second parallel interface on the second integrated circuit die.3. The method of claim 2 , wherein the second parallel interface is substantially identical to the first parallel interface.4. The method of claim 2 , wherein the plurality of signals are stored in second buffers of the second parallel interface that correspond to equivalent buffers of the first parallel interface.5. The method of claim 2 , wherein each of the plurality of signals is sampled often enough to appear to be substantially asynchronous to the second integrated circuit.6. The method of claim 1 , wherein the first one of the plurality of signals has a higher latency sensitivity than the second one of the plurality of signals.7. The method ...

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Номер записи: 87
09-07-2015 дата публикации

Receiver with pipelined tap coefficients and shift control

Номер: US20150195108A1
Автор: Amaresh V. Malipatil, Tomasz Prokop, Viswanath Annampedu, Volodmyr Shvydun
Принадлежит: LSI Corp

A serializer-deserializer using series-coupled signal processing blocks to process digitized input symbols, each block having a coefficient input. Each of plurality of series-coupled coefficient delay elements has a control input and a coefficient output coupling to the coefficient inputs of a corresponding one of the signal processing modules, is controlled by a shift register having an input and a plurality of outputs, each one of the plurality of outputs coupled to the control input of a corresponding one of the coefficient delay elements. An adaptation unit has a flag output coupled to the input of the shift register, and a first coefficient output coupled to the input of a first one of the coefficient delay elements. The adaptation unit generates a flag when the adaptation unit generates a coefficient, and the coefficient is entered into the first one of the coefficient delay elements when the shift register receives the flag.

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Номер записи: 88
29-06-2017 дата публикации

Semiconductor apparatus

Номер: US20170187517A1
Автор: Jeong Kyoum KIM, Myeong Jae PARK
Принадлежит: SK hynix Inc

A semiconductor apparatus includes a pattern conversion circuit configured to generate conversion data in response to a monitoring enable signal, pattern select signals and parallel input data; a transmission circuit configured to output the conversion data as serial data in response to a plurality of clocks; a reception circuit configured to output the serial data as parallel output data in synchronization with the plurality of clocks; and a monitoring circuit configured to generate a result signal in response to the plurality of clocks, clock select signals and the serial data.

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Номер записи: 89
04-06-2020 дата публикации

APPARATUS AND METHODS FOR SERIALIZING DATA OUTPUT

Номер: US20200176059A1
Автор: CHOI Hoon, Ghalam Ali Feiz Zarrin, Maccarrone Agatino Massimo, Pilolli Luigi, TANG Qiang
Принадлежит: MICRON TECHNOLOGY, INC.

Methods for serializing data output including receiving a plurality of data values, sequentially providing data values representative of data values of a first subset of data values of the plurality of data values to a first signal line while sequentially providing data values representative of data values of a second subset of data values of the plurality of data values to a second signal line, and providing data values representative of the sequentially-provided data values from the first signal line and providing data values representative of the sequentially-provided data values from the second signal line in an alternating manner to a third signal line, as well as apparatus having a configuration to support such methods. 1. An apparatus , comprising:a first multiplexer comprising a plurality of input signal lines, a first output signal line and a second output signal line, wherein each input signal line of the plurality of input signal lines is configured to receive a data value to be output from the apparatus, and wherein the first multiplexer is configured to provide data values representative of the data values for a first subset of input signal lines of the plurality of input signal lines to the first output signal line and to provide data values representative of the data values for a second subset of input signal lines of the plurality of input signal lines to the second output signal line;a second multiplexer comprising a first input signal line, a second input signal line and an output signal line, wherein the first input signal line of the second multiplexer is configured to receive the data values from the first output signal line of the first multiplexer, wherein the second input signal line of the second multiplexer is configured to receive the data values from the second output signal line of the first multiplexer, and wherein the second multiplexer is configured to selectively provide data values representative of the data values from its first ...

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Номер записи: 90
16-07-2015 дата публикации

PARALLEL-SERIAL CONVERTER CIRCUIT

Номер: US20150200683A1
Автор: SHIRAISHI MIKIO
Принадлежит:

A parallel-serial converter circuit has a frequency divider configured to generate a frequency-divided signal by dividing a frequency of a reference clock signal by a dividing ratio depending on a logic of a speed control signal, a timing pulse generator configured to generate a timing pulse signal based on the frequency-divided signal, a load signal generator configured to generate a load signal based on the speed control signal and the timing pulse signal, a bit clock generator configured to generate a bit clock signal based on the speed control signal and the timing pulse signal, and a parallel-serial converter configured to newly load the parallel data in synchronization with the load signal and convert the loaded parallel data into serial data in synchronization with the bit clock signal. 1. A parallel-serial converter circuit comprising:a frequency divider configured to generate a frequency-divided signal by dividing a frequency of a reference clock signal by a dividing ratio depending on a logic of a speed control signal;a timing pulse generator configured to generate a timing pulse signal based on the frequency-divided signal;a load signal generator configured to generate a load signal based on the speed control signal and the timing pulse signal;a bit clock generator configured to generate a bit clock signal based on the speed control signal and the timing pulse signal; anda parallel-serial converter configured to newly load the parallel data in synchronization with the load signal and convert the loaded parallel data into serial data in synchronization with the bit clock signal.2. The parallel-serial converter circuit of claim 1 ,wherein the bit clock generator comprises:a first selector configured to select one from a plurality of first reference bit strings based on the logic of the speed control signal and set the selected first reference bit string as a first initial value; anda first shift register configured to generate the bit clock signal by ...

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Номер записи: 91
06-07-2017 дата публикации

EMBEDDED CLOCK IN COMMUNICATION SYSTEM

Номер: US20170195148A1
Автор: Payne Robert Floyd
Принадлежит:

A method for simultaneously transmitting data bits and a clock signal includes converting the combination of the data bits and the clock signal to analog voltages by a digital-to-analog converter. The clock signal are the most significant bit of the digital-to-analog conversion and the data bits are the least significant bit of the digital-to-analog conversion. 1. A receiver for decoding a data signal and a clock signal from an input signal having four voltage levels , the receiver comprising:a voltage input for receiving the input signal;a first comparator coupled to the voltage input for comparing the input signal to a zero voltage;a second comparator coupled to the voltage input for comparing the input signal to a first reference voltage;a third comparator coupled to the voltage input for comparing the input signal to a second reference voltage; anda decoder coupled to outputs of the comparators, the decoder for generating a first logic state of the data signal in response to the input signal being greater than the first reference voltage when the input signal is positive, and for generating a second logic state of the data signal in response to the input voltage being less than the second reference voltage when the input signal is negative.2. The receiver of claim 1 , wherein the input signal has a maximum positive value and wherein the first reference voltage is approximately two thirds of the maximum positive value.3. The receiver of claim 1 , wherein the input signal has a minimum negative value and wherein the second reference voltage is approximately two thirds of the minimum negative value.4. The receiver of claim 1 , wherein the decoder is further for:decoding a first logic state of the clock signal in response to the output of the first comparator being a first value; anddecoding a second logic state of the clock signal in response to the output of the first comparator being a second value.5. The receiver of claim 1 , wherein the decoder is further for: ...

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Номер записи: 92
25-09-2014 дата публикации

CURRENT COMPENSATION CIRCUIT

Номер: US20140285367A1
Автор: Matsumoto Junichi
Принадлежит: ADVANTEST CORPORATION

A first circuit operates in synchronization with a first clock having a first frequency, and generates N parallel data sets for every cycle period of the first clock. An interface circuit time-division multiplexes the N data sets received from the first circuit. A second circuit processes the N data set thus time-division multiplexed, in synchronization with a second clock having a second frequency which is N times the first frequency. A judgment unit judges whether or not the N data sets are effective data which instructs a flip-flop group, configured as a state holding element included in the second circuit, to generate an effective state transition. In a cycle period in which the N data sets are ineffective, a data replacement unit replaces at least a part of the N data sets with current compensation data D. 1. A current compensation circuit configured to receive N parallel data sets for every cycle period of a first clock from a first circuit configured to operate in synchronization with the first clock having a first frequency and to output the N data sets thus received to a second circuit configured as a downstream stage , the current compensation circuit comprising:a judgment unit configured to judge, for every cycle period, whether or not the N data sets are effective data which instructs at least one state holding element included in the second circuit to generate an effective state transition; anda data replacement unit configured such that, in a cycle period in which judgment has been made that the N data sets are ineffective, at least a part of the N data sets is replaced by current compensation data so as to instruct at least one state holding element included in the second circuit to generate an effective state transition.2. The current compensation circuit according to claim 1 , wherein a parallel/serial converter is arranged between the current compensation circuit and the second circuit claim 1 ,and wherein the second circuit is configured to ...

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Номер записи: 93
22-07-2021 дата публикации

Frequency-Multiplying Direct Digital Synthesizer

Номер: US20210226642A1
Автор: Booth Richard W.D.
Принадлежит: ERIDAN COMMUNICATIONS, INC.

A frequency-multiplying DDS includes a digital multiplier, a phase accumulator, a post-accumulator digital processing section, and a digital-to-analog converter (DAC). The digital multiplier multiplies a digital tuning word of value M by a digital multiplier of value B, to produce a digital product (M×B), and the n-bit accumulator accumulates by a step size of the digital product (M×B), at a rate of a low-speed reference clock of frequency f/B. The post-accumulator digital processing section synthesizes B digital waveforms from the sequence of n-bit accumulator output numbers produced by the n-bit accumulator, and rotates each digital waveform with respect to each adjacent digital waveform by (M/2)×2π radians. The DAC serializes the digital samples of the B digital waveforms at full speed, i.e., at a rate f, to produce a full-speed serialized digital output having 2/M samples per cycle, and converts the full-speed serialized digital output to a final output analog waveform of frequency f=(M/2)×f. 1. A direct digital synthesizer (DDS) , comprising:a digital multiplier configured to multiply a digital tuning word by a digital multiplier and produce a digital product;an accumulator configured to accumulate at a step size of the digital product and at a rate of a reference clock; anda post-accumulator digital processing section including two or more branches configured to synthesize two or more digital waveforms from a sequence of output numbers produced by the accumulator.2. The DDS of claim 1 , further comprising:a serializer configured to serialize digital samples of the two or more digital waveforms and produce an output digital waveform; anda digital-to-analog converter (DAC) configured to convert the output digital waveform to a final output analog waveform.3. The DDS of claim 2 , wherein the serializer and DAC together comprise a single interleaved radio frequency DAC (RF-DAC).4. The DDS of claim 1 , further comprising:two or more digital-to-analog converters ( ...

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Номер записи: 94
12-07-2018 дата публикации

Sample-and-hold circuit for an electrical signal

Номер: US20180197618A1
Автор: Arnaud Meyer, Bruno Louis, Herve Petit, Patricia DESGREYS, Remi Corbiere, Vincent Petit
Принадлежит: Thales SA

Sample-and-hold device for an electrical signal including an input module having two inputs, including a first switching block including two input switches, each input of the input module being connected at the input of one of the input switches, the input module being connected at the input of a first track-and-hold module with two inputs and two outputs, so as to alternately convey the signal from one of the two inputs to one of the two inputs of the first track-and-hold module; the device including a second track-and-hold module connected in parallel with the first track-and-hold module, these track-and-hold modules connected at the output of the first switching block, and an output module including a second switching block including two output switches, the outputs of the first and second track-and-hold modules being connected to the inputs of the output switches, to time interleave the output signals of the track-and-hold modules.

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Номер записи: 95
18-06-2020 дата публикации

PARALLEL-TO-SERIAL CONVERSION CIRCUIT

Номер: US20200195274A1
Автор: CHAE Joo-Hyung, Kim Suhwan
Принадлежит:

A parallel-to-serial conversion circuit may include first to fourth data lines; first to fourth parallel-to-serial converters configured to parallel-to-serial convert data of corresponding two data lines, among the first to fourth data lines, at a ratio of 2:1, respectively; and first to fourth drivers configured to transmit converted data of corresponding parallel-to-serial converter, among the first to fourth parallel-to-serial converters, respectively, to an output line, wherein two of the first to fourth drivers are simultaneously activated. 1. A parallel-to-serial conversion circuit comprising:first to fourth data lines;first to fourth parallel-to-serial converters configured to parallel-to-serial convert data of corresponding two data lines, among the first to fourth data lines, at a ratio of 2:1, respectively; andfirst to fourth drivers configured to transmit converted data of corresponding parallel-to-serial converter, among the first to fourth parallel-to-serial converters, respectively, to an output line,wherein two of the first to fourth drivers are simultaneously activated.2. The parallel-to-serial conversion circuit of claim 1 , wherein the first parallel-to-serial converter parallel-to-serial converts data of the fourth data line and data of the first data line at a ratio of 2:1 claim 1 ,the second parallel-to-serial converter parallel-to-serial converts the data of the first data line and data of the second data line at a ratio of 2:1,the third parallel-to-serial converter parallel-to-serial converts the data of the second data line and data of the third data line at a ratio of 2:1, andthe fourth parallel-to-serial converter parallel-to-serial converts the data of the third data line and data of the fourth data line at a ratio of 2:1.3. The parallel-to-serial conversion circuit of claim 2 , wherein the fourth driver and the first driver are activated during a first period claim 2 ,the first driver and the second driver are activated during a second ...

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Номер записи: 96
29-07-2021 дата публикации

MULTI-LANE SERIALIZER DEVICE

Номер: US20210234553A1
Автор: Fujita Yusuke, Miura Satoshi
Принадлежит: THINE ELECTRONICS, INC.

A multi-lane serializer device includes serializer circuits to and a controller . A phase difference detector of each serializer circuit detects a phase difference between a load signal and a first clock, and outputs an abnormal detection signal to the controller when the detected phase difference is abnormal. When the controller receives the abnormal detection signal from any of the serializer circuits, the controller transmits a batch reset instruction signal to all the serializer circuits. Then, in all the serializer circuits, when a reset signal generator receives the batch reset instruction signal output from the controller , the reset signal generator transmits a reset instruction signal to a load signal generator to reset the operation of a load signal generation in the load signal generator. 1. A multi-lane serializer device , comprising:serializer circuits each serializing parallel data input in synchronization with a first clock and outputting serial data in synchronization with a second clock; anda controller that controls operations of the serializer circuits,wherein each of the serializer circuits includes:a converter that latches the parallel data at a timing indicated by a load signal having the same period as the first clock and outputs the latched data as serial data in synchronization with the second clock;a load signal generator that generates the load signal based on the second clock, wherein the load signal generator resets an operation of a load signal generation when the load signal generator receives a reset instruction signal;a phase difference detector that detects a phase difference between the load signal and the first clock and outputs an abnormal detection signal to the controller when the detected phase difference is abnormal; anda reset signal generator that generates the reset instruction signal and provides the generated reset instruction signal to the load signal generator when the reset signal generator receives a batch reset ...

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Номер записи: 97
06-08-2015 дата публикации

COMMUNICATION APPARATUS, IMAGE FORMING APPARATUS, COMMUNICATION METHOD, AND COMPUTER-READABLE STORAGE MEDIUM

Номер: US20150222290A1
Автор: Abe Yasuhiro, HIGASHIYAMA Makoto, MIYADERA Tatsuya, OHMIYA Satoshi, OHYAMA Tatsuo, Oikawa Masahiko, SHUKUYA Yuichiro
Принадлежит:

A communication apparatus includes a serializer configured to convert parallel data into serial data and output the serial data; and a deserializer configured to convert the serial data output from the serializer into parallel data and output the parallel data. The serializer is configured to add first data used for detecting unique data in the parallel data before the unique data, add second data used for detecting the unique data after the unique data, and add third data whose length is variable to each of the first data and the second data. 1. A communication apparatus comprising:a serializer configured to convert parallel data into serial data and output the serial data; anda deserializer configured to convert the serial data output from the serializer into parallel data and output the parallel data,wherein the serializes is configured to add first data used for detecting unique data in the parallel data before the unique data, add second data used for detecting the unique data after the unique data, and add third data whose length is variable to each of the first data and the second data.2. The communication apparatus according to claim 1 , wherein the unique data is image data.3. The communication apparatus according to claim 1 , wherein the parallel data is 10-bit data generated by 8 B/10 B conversion.4. The communication apparatus according to claim 1 , wherein the serializer is configured to stationarily add fourth data to an outside of the parallel data.5. The communication apparatus according to claim 4 , wherein the first data claim 4 , the second data claim 4 , the third data claim 4 , and the fourth data are each any one of a plurality of types of symbol codes for the 8 B/10 B conversion.6. The communication apparatus according to claim 5 , wherein the third data is any one of K28.5 claim 5 , K28.1 claim 5 , K28.2 claim 5 , K28.3 claim 5 , and K28.6.7. The communication apparatus according to claim 5 , wherein the fourth data is any one of K28.5 claim ...

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Номер записи: 98
13-08-2015 дата публикации

MULTIPLEXER

Номер: US20150229327A1
Автор: Nedovic Nikola
Принадлежит: FUJITSU LIMITED

A multiplexer may include a first circuit, a second circuit, and a third circuit. The first circuit may be configured to receive a first input signal and a first trigger signal and to output a first output signal that may be based on the first input signal during a first level of the first trigger signal and may be at a known level during a second level of the first trigger signal. The second circuit may be configured to receive a second input signal and a second trigger signal and to output a second output signal that may be based on the second input signal during a first level of the second trigger signal and may be at the known level during a second level of the second trigger signal. The third circuit may be configured to output a third output signal based on the first and second output signals. 1. A multiplexer comprising:a first circuit configured to receive a first input signal and a first trigger signal and to output a first output signal on a first output node, the first output signal being based on the first input signal during a first level of the first trigger signal and being at a known level during a second level of the first trigger signal;a second circuit configured to receive a second input signal and a second trigger signal and to output a second output signal on a second output node, the second output signal being based on the second input signal during a first level of the second trigger signal and being at the known level during a second level of the second trigger signal, the second trigger signal being an inversion of the first trigger signal; anda third circuit coupled to the first output node and the second output node and configured to output a third output signal based on the first and second output signals.2. The multiplexer of claim 1 , wherein the third output signal is the first input signal when the second output signal is at the known level and the third output signal is the second input signal when the first output signal is at the ...

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Номер записи: 99
04-08-2016 дата публикации

TRANSMISSION DEVICE AND COMMUNICATION SYSTEM

Номер: US20160226679A1
Автор: SAEKI TAKANORI
Принадлежит:

A transmission device of the disclosure includes a first selector configured to select one of a first signal and a second signal, and output the selected signal; a second selector configured to select one of an inversion signal of the first signal, the second signal, and an inversion signal of the second signal, and output the selected signal; a first control signal generator configured to generate a first control signal, a second control signal, and a third control signal, based on the first signal, the second signal, and a third signal; a first driver configured to set a voltage of a first output terminal, based on an output signal of the first selector and the first control signal; and a second driver configured to set a voltage of a second output terminal, based on an output signal of the second selector and the second control signal. 1. A transmission device comprising:a first selector configured to select a first output signal from one of a first signal and a second signal;a second selector configured to select a second output signal from one of an inversion signal of the first signal, the second signal, and an inversion signal of the second signal;a first control signal generator configured to generate a first control signal, a second control signal, and a third control signal, based on the first signal, the second signal, and a third signal;a first driver configured to set a voltage of a first output terminal, based on the first output signal and the first control signal; anda second driver configured to set a voltage of a second output terminal, based on the second output signal and the second control signal.2. The transmission device according to claim 1 , whereina plurality of operation modes including a first operation mode are provided, andin the first operation mode,the first selector alternately selects the first signal and the second signal,the second selector selects the inversion signal of the first signal when the first selector selects the first ...

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Номер записи: 100