ТОРГОВАЯ СИСТЕМА

МАРШРУТИЗАТОР ПАКЕТОВ В СЕТЯХ С НЕОДНОРОДНОЙ ТОРОИДАЛЬНОЙ ТОПОЛОГИЕЙ

MEHRFACHPORT-VERTEILTE SPEICHERSCHNITTSTELLE UND ZUGEHÖRIGES VERFAHREN

SYSTEM UND VERFAHREN ZUM VERMITTELN VON DATEN UNTER VERWENDUNG EINES GEMEINSAMEN KOPPELFELDES

VERMITTLUNGSKNOTEN FUER DIE VERMITTLUNG VON IN DATENPAKETEN UEBERTRAGENEN DATENSIGNALEN.

A data distribution system has 'n' input lines (E1,-En) that handle data packets generated by terminals or other systems. The inputs are coupled to buffer memories (PS1-PSn) each of which has an associated control stage. A connection with a number of output lines (A1-An) is made via a coupling matrix (RK) that receives the input (mn). The setting of the coupling unit is provided by a control unit (ZST) that can be microprocessor based and which has a number of wait loop buffers (AP1-APn).

PAKETVERMITTLUNGSSYSTEM.

Kommunikationsgerät

SPEICHERSCHNITTSTELLENEINHEIT, VERMITTLUNGSSYSTEM MIT GEMEINSAMEM SPEICHER UND VERFAHREN DAZU

Kreuzschienenverteiler

Ein Kreuzschienenverteiler weist eine Anzahl von Kreuzungspunkten (3) auf, an denen steuerbare Schaltelemente (6) angeordnet sind, mittels derer ein einer Zeile (1) zugeführtes Eingangssignal (E) auf eine diese Zeile (1) an diesem Kreuzungspunkt (3) kreuzende Spalte (2) durchschaltbar ist, wenn dem jeweiligen Kreuzungspunkt (3) über einen Steuereingang (7) ein Durchschaltsignal (D) zugeführt wird. Die steuerbaren Schaltelemente (6) weisen Verstärkerelemente (10) auf, deren Verstärkereingänge (11) mit den Zeilen (1) und deren Verstärkerausgänge (12) mit den Spalten (2) verbunden sind. Die Verstärkerelemente (10) sind derart beschaltet, dass sie nur dann elektrische Energie verbrauchen, wenn dem jeweiligen Kreuzungspunkt (3) das Durchschaltsignal (D) zugeführt wird. An den Zeileneingängen (4) bzw. den Spaltenausgängen (8) gegenüberliegenden Enden der Zeilen (1) sind Zeilenwellenwiderstände (13) bzw. Spaltenwellenwiderstände (14) angeordnet, über die an die Zeilen (1) eine Zeilenspannung ( ...

VERFAHREN UND GERÄT UM DEN NETZWERKVERKEHR ZU ÜBERWACHEN

RRGS-Round-Robin-Greedy Ablaufsteuerung für Eingangs-/Ausgangsgepufferte Terabitswitches

PAKETVERARBEITUNGS-VERMITTLUNG UND BETRIEBSVERFAHREN DAFÜR

NxN Crossbar packet switch

A novel NxN Crossbar Packet Switch is disclosed, which crossbar switch is based on a distributed port architecture, asynchronous output port arbitration, support of non fixed-size packets (cells), support for virtual channels (VC) and/or priority, and which only requires 2 * N * N control lines for the arbitration.

NxN Crossbar packet switch

Apparatus and method for switching data packets

A method and apparatus (1) is disclosed for switching data packets. A data packet is received from an input interface device (7) at one of a plurality of initial input pods (6). The data packet is divided into plural smaller data fragments. Each data fragment is passed to a respective one of a plurality of slices of an input port (3) of a core switch (2). The data fragments are switched using the core switch (2) so as to pass each data fragment to a selected respective one of a plurality of slices of an output port (3') of the core switch (2). The data fragments are then passed to a selected one of a plurality of ultimate output ports (5'). The data fragments are assembled to reform the data packet, and the reformed data packet is transmitted to an output interface device (7') connected to said selected one of a plurality of ultimate output ports (5').

Switching device for routing data, computer interconnection network and routing method using such device

The invention is directed to a switching device (S ij ) adapted to connects parts of a computer interconnection network, having N input ports (Ia - Ih) and N output ports (Oa - Oh), the device adapted for routing data packets by means of direct crosspoints (CP xy ), the direct crosspoints configured for enabling direct connectivity between each of the N input ports to a subset m < N of the output ports only, in accordance with connectivity needs of the computer interconnection network. Preferably, it further comprises an additional circuitry (L) and additional crosspoints (ΠΡx,L, ΠΡL,y) configured such that at least some of the input ports of the switching device can be indirectly connected to at least some of the output ports of the switching device, through the additional circuitry. The invention further concerns an interconnection network and a method for routing data.

Customised ports in a crossbar and method for transmitting data between customised ports and system agents

A crossbar (50) and method (180) for providing connections between a plurality of ports and a plurality of system agents via a processing system, which includes a plurality of ports (52, 54, 56, 58), each port being capable of being an input port (60, 68, 76, 84) customized for receiving data from a source agent and an output port (62, 70, 78, 86) customized for transferring data to a destination agent, and crossbar control data (66, 74, 82, 90) for specifying crossbar control information for transferring data from an input port to an output port having different port configurations.

Network topology having nodes interconnected by extended diagonal links

AUTOMATIC TELECOMMUNICATIONS SWITCHING SYSTEM

A system and method for bridging computer resources

CROSSPOINT SWITCH ARCHITECTURE OF A COMMON MEMORY

MULTI-ACCESS LINE PROCEDURE AND - EQUIPMENT FOR VIRTUAL HAVEN

SWITCHING NODE FOR THE SWITCHING OF IN PACKETS UBERTRAGENEN DATA SIGNALS.

PROCEDURE AND SWITCH FOR MEDIATING INFORMATION.

LOCAL MESHED NETWORK WORK OF HIGH SPEED

MEDIATION PROCEDURE AND - DEVICE FOR A SATELLITE COMMUNICATION SYSTEM

CONNECTING PROTECTION IN A DIGITAL COMMUNICATIONS SYSTEM

CROSS BAR SWITCHING CENTER, ASSOCIATED OPERATING CONTROL PROCEDURE AND - PROGRAM

PROCEDURE FOR THE SETTING-UP OF CONNECTIONS VIRTUAL OVER OUPLE MULTIPLE OF A MULTI-LEVEL OUPLE ARRANGEMENT RUNNING.

PROCEDURE AND SYSTEM FOR SELECTING AN OPTIMAL REARRANGING SEQUENCE FOR A BYPASS SWITCH

PROCEDURE FOR THE PATH SELECTION IN A TELEPHONE EXCHANGE NETWORK

CROSS POINT SWITCH WITH SERIALIZER AND DESERIALIZER FUNCTIONS

Method for providing delays independent of switch size in a crossbar switch with speedup

Forwarding variable-length packets in a multiport switch

CROSSBAR SWITCH AND PARALLEL PROCESSING SYSTEM USING THE SAME

METHOD OF AND SWITCH FOR SWITCHING INFORMATION

IMPROVEMENTS IN OR RELATING TO ROUTING DEVICES

The invention relates to a router device (200) having a plurality of ingress line interface cards (LICs) (212, 214, 216, 218), a plurality of egress LICs (222, 224, 226, 228)), a backplane (230) and a controller (240). Transmission of signals from the ingress LICs (212, 214, 216, 218) to the controller (240) and likewise the transmission of signals from the controller (240) to each of the ingress LICs (212, 214, 216, 218) and each of the egress LICs (222, 224, 226, 228) takes place across the backplane (230). Each ingress LIC (212, 214, 216, 218) is provided with a dedicated timeslot in which it can send information to the controller (240) via connection (242). Information is sent in a slice within the dedicated timeslot and each egress LIC (222, 224, 226, 228) ignores data sent by a given ingress LIC within the timeslot assigned to said ingress LIC. A similar system is used for transmission of communications from the controller (240) to the LICs. It is thus possible to avoid provision ...

IMPROVEMENTS IN OR RELATING TO PACKET SWITCHES

The invention relates to cell level scheduling for handling multicast traffic in routing devices, for example cross-bar switches. The routing device has a plurality of ingress line interface cards (LICs), a plurality of egress LICs, a cross-bar and a controller. Multicast and unicast data traffic passes from the ingress LICs via the cross-bar to the egress LICs. A given multicast data packet is sent from a given ingress LIC to a predetermined set of egress LICs known as the fanout of the given packet. Each ingress LIC has an associated rate of send opportunities. The inventive method allows multicast send opportunities to be spread as evenly as possible over cell periods. The method also invokes a conventional unicast scheduling scheme when no multicast send opportunity is scheduled and a multicast scheduling scheme when one or more multicast send opportunities are present. The schedule is filled out with the fanouts of multicast packets in accordance with the send priority associated with ...

WIDEBAND DIGITAL SWITCHING NETWORK

A WIDEBAND DIGITAL SWITCHING NETWORK Disclosed is a wide bandwidth self-routing switch. One-to-one, one-to-many, and many-to-many modes of communications are achieved with time multiplexed signal packets of multi-service users with a system having a bank of demultiplexers which demultiplex incoming signals and supply them to a broadcast network. The broadcast network includes a concentrator a "sort on source" sorting network and a copy network. The concentrator permits a reduction in subsequent processing by segregating the incoming lines which carry active signals. The "sort on source" sorting network places all blank copy packets (which are destined to users that wish to tune to a broadcaster) adjacent to the broadcaster's signal packets. The copy network copies the information in the broadcaster's signal packets into the packets destined to the users. The blank copy packets are continually generated by the users wishing to receive broadcasts or, alternatively, by a blank packet generator ...

MATRIX SWITCH CIRCUIT

... ▓▓ In an embodiment of a matrix switch circuit, a group▓provided with twelve 64-to-1 selectors is arranged by 64 pieces,▓that is, (12 x 64) pieces of 64-to-1 selectors are provided.▓ Address information is input to the selector. STS-12 (one frame)▓in which twelve 8-bit STS-1 (unit data) are serially arrayed▓is input from 64 pieces of input terminals of the selector. The▓matrix switch circuit is further provided with a selecting▓circuit that selects specific unit data in the frame and 64 pieces▓of 12-to-1 selectors that forms unit data output from the▓selecting circuit in one frame and outputs it.▓ ...

SYSTEM AND METHOD FOR SIGNAL PROCESSING

... ²²A plurality of systems for routing signals are described. The system includes ²a cross ²point switch that can couple any one of a plurality of input terminals to a ²plurality of ²output processor terminals. Signals received at the input terminals are ²coupled to ²corresponding output terminals and are processed by output modules. The ²resulting ²processed signals are provided at output terminals. In some embodiments, one ²or more ²input modules are provided to process input signal prior to routing through ²the cross-point² switch.² ...

METHODS AND SYSTEMS FOR IMMEDIATELY CONNECTING AND RESWITCHING DIGITAL CROSS-CONNECT NETWORKS

... 91AD004 PATENT APPLICATION METHODS AND SYSTEM FOR IMMEDIATELY CONNECTING AND RESWITCHING DIGITAL CROSS-CONNECT NETWORKS A method and system to immediately connect and reswitch connection configurations through a rearrangeable communications matrix that immediately connects an input gate causing rearrangeably blocked condition through the communications matrix to an output gate through a dedicated or extra switching element of the center. With the rearrangeably blocked condition, the method and system select a set of switching elements pairs from the center stage switches to form a plurality of possible connections from the input gates to the output gates that excludes the dedicated switching element. The method and system then determines from the possible connections a minimum rearrangement connection configuration that excludes the dedicated switch and that requires the minimum number of rearrangements of existing communications matrix connections. Then, the invention reswitches the matrix ...

INTERCONNECT FABRIC PROVIDING CONNECTIVITY BETWEEN AN INPUT AND ARBITRARY OUTPUT (S) OF A GROUP OF OUTPUTS

CONFIGURABLE CONNECTION FABRIC FOR PROVIDING SERIAL BACKPLANES WITH ADAPTIVE PORT/MODULE BANDWIDTH

A configurable connection subsystem to connect first ports coupled to a switching fabric and second ports connected to a digital system, whereby the connection subsystem comprises: configurable switch means for connecting the first ports to the second ports in response to configuration control signals; and control means, coupled to the configurable switch means, for creating and sending configuration control signals to the switch means to configure the switch means to connect each of a selected number of the second ports to corresponding ones of the first ports, the control means including means for receiving load inputs indicating a need for the selected number of ports, and configuration means for determining a configuration of the switch means based upon the selected number of ports.

Equipment and method for estiblishing non-management ethernet exchange structure information

PACKET SWITCHING SYSTEM

Matrice de commutation multidebits a large bande, pour reseau de connexion

La matrice comporte n circuits de maille CM1 a CMn relies chacun a une maille entrante E1 a En, une matrice spatiale MS de type n x m reliee par des lignes entrantes I1 a In aux circuits de maille, et a m mailles sortantes Z1 a Zm, et un circuit logique de commande CLC relie a chaque circuit de maille, et a un registre d'adresses d'entree, un registre d'adresses de sortie et une entree de validation de la matrice spatiale. Chaque circuit de maille comprend une sous-maille spatiale 8 pour les trafics a hauts debits et une sous-maille temporelle mt pour les trafics de trames temporelles asynchrones, de canaux a tous debits.

STAMP SWITCHES HAS TWO POSITIONS EACH ONE

L'invention est relative à une matrice de commutateurs à deux positions chacun permettant de transférer m signaux d'entrées vers le même nombre de sorties. La commande de la matrice est telle que tous les arrangements de m signaux entrants soient possibles sur m sorties. Cette matrice est caractérisée en ce qu'elle comporte une matrice principale (20) et une matrice de dépannage (22, 221) qui comprend un même nombre d'entrées et de sorties qui est au moins égal au plus petit des nombres n et p, n étant le nombre d'entrées de la matrice principale, et p le nombre de sorties de cette matrice. Les commutateurs de cette matrice de dépannage sont agencés et commandés de façon telle qu'elle agit comme un simple commutateur dont les entrées sont constituées par n'importe quel couple d'entrées (e'i, e'j) de cette matrice de dépannage et dont les deux sorties (s'i, s'j) sont constituées par les deux sorties de cette matrice de dépannage qui ont le même rang que le couple d'entrées, les autres entrées ...

PROCESS AND DEVICE OF COMMUNICATION ENTER A PLURALITY OF TERMINALS, COMPATIBLE WITH STANDARD ARINC 629.

PROCESS AND SWITCHING SYSTEM OF CELLS BRACKETS TO THE ASYNCHRONOUS TIME-DIVISION SWITCHING

High digital transmission rate switching circuit, for optical communication, having interconnection matrix controlled signal and reference transmissions and two distinct lines having common voltage reference channel

L'invention concerne un dispositif de commutation comportant une pluralité d'entrées et de sorties reliées entre elles par une matrice de points d'interconnexion pour transmettre des signaux électriques émis sur lesdites entrées vers lesdites sorties via des lignes de transmission selon un plan de commutation prédéfini. Chaque ligne de transmission comporte une voie de signal pour transporter les signaux électriques et une voie de référence en tension. Les points d'interconnexion sont arrangés dans la matrice de sorte que deux lignes de transmission distinctes comportent une voie de référence en tension commune. Application : commutation de paquets dans les transmissions optiques.

SWITCHING SYSTEM OF PACKAGES FOR NODE OF COMMUNICATION NETWORK

Pour aiguiller sélectivement via une matrice de commutation (1) des paquets en attente dans des modules d'entrée (IMi) vers des modules de sortie (OMj) destinataires, des fonctions d'arbitrage reparties sont exécutables par cycles d'arbitrage successifs. Chaque cycle comporte : - une première phase exécutable par chaque contrôleur d'entrée (ICi) pour envoyer à chaque contrôleur de sortie (OCj) des requêtes représentatives de quantités de paquets en attente "requises", - une seconde phase exécutable par chaque contrôleur de sortie (OCj) pour déterminer en fonction des requêtes des quantités de paquets "admissibles", - une troisième phase exécutable par une unité d'arbitrage central (CSC) pour déterminer en fonction de toutes les quantités admissibles des quantités "agrégées admises", - une quatrième phase exécutable par chaque contrôleur d'entrée (ICi) pour déterminer en fonction des quantités admissibles et des quantités agrégées admises des quantités de paquets admises. Application aux ...

PACKET SWITCHING SYSTEM FOR TELECOMMUNICATIONS NETWORK NODE

METHOD FOR GENERATING AND MONITORING TRAFFIC TEST, INLET PORT OR OUTLET AND SWITCH THEREFOR

L'invention concerne un procédé de génération, au niveau de commutateurs émetteurs (1, 31) de test d'un réseau de nœuds de calcul, d'un trafic de test, et de contrôle, au niveau de commutateurs destinataires (1, 33) de test de ce réseau, de ce trafic de test, comprenant : la génération et l'émission, au moins au niveau d'un port d'entrée (5) ou de sortie (6) émetteur de test sélectionné d'un commutateur émetteur (1, 31) de test sélectionné, d'un trafic de test, à destination au moins d'un port d'entrée (5) ou de sortie (6) destinataire de test sélectionné d'un commutateur destinataire (1, 33) de test sélectionné, ledit trafic de test étant généré et émis par un composant générateur (23) de trafic configuré comme une entrée supplémentaire (14) dudit port d'entrée (5) ou de sortie (6) émetteur de test sélectionné, ledit trafic de test étant contrôlé par un composant contrôleur (24) de trafic configuré pour filtrer la sortie (15) dudit port d'entrée (5) ou de sortie (6) destinataire de test ...

PROCESS AND DEVICE OF SELECTION Of the ILO Of ADDRESS IN a SWITCHING NETWORK OF PACKAGES

Relay apparatus e.g. router used in computer network, stores header information in table which is referred during packet routing for communication quality, forwarding priority and suitability

Dispositif et procédé d'interconnexion de réseaux destinés à garantir une qualité de communication élevée, une fiabilité et une sécurité élevées. Un moteur de transfert (13) mémorise les paquets reçus à travers au moins une interface réseaux (30) dans un tampon de paquets (12), et les informations d'en-tête dans une mémoire RAM d'en-tête (11). Un moteur de recherche (14) recherche les informations de commande de transfert, telles que les informations de destination et les informations d'action basées sur les informations d'en-tête, et les écrit dans la mémoire RAM d'en-tête (11). Le moteur de transfert (13) prépare un paquet de sortie sur la base des informations mémorisées dans le tampon de paquets (12) et dans la mémoire RAM d'en-tête (11), et émet le paquet de sortie vers la destination. Un commutateur (20) commute le paquet de sortie vers le processeur de routage (10) de la destination. Chaque mémoire RAM d'en-tête (11) est accessible d'une manière asynchrone indépendamment du tampon ...

MULTIPLE INPUT/OUTPUT BUFFER-TYPE EXCHANGE

PURPOSE: A multiple input/output buffer-type exchange is provided to suggest a method of implementing a scheduler and a method of managing buffers for correcting sequence errors between packets in output buffers, based on a multiple crossbar exchange network, thereby obtaining the same performance as an output buffer-type exchange. CONSTITUTION: Based on a multiple crossbar exchange network(20), input buffers(10) and output buffers(30) are disposed every input and every output. An 'Nxk' intermediate connection network(11) moves only one packet to either one of input lines from each input buffer(10). An 'mxM' intermediate connection network(31) moves packets arriving at output ends to either one of the output buffers(30) from output lines. A scheduler having 'multiple token arbiters' operates in round-robin method for multipoint-to-multipoint scheduling. © KIPO 2004 ...

FABRIC-BASED HIGH SPEED SERIAL CROSSBAR SWITCH FOR ATE

A loopback module is disclosed in which N differential High Speed Serial (HSS) digital data input channels are received and sent to a serial to parallel converter, whose output is M-bit wide parallel data. By doing so, the effective data rate is divided down by M to 1/M ''fabric'' speeds. If the channels contain an embedded clock, the clock is extracted. The parallel data is then sent to a non-blocking crossbar switch, which is able to route any of the N M-bit parallel data inputs to any of Q parallel data outputs by effectively utilizing one multiplexer for each parallel output. Each parallel data output of the crossbar is sent to a parallel to serial converter, whose output is a high speed serial output. Each high speed serial output is fed into a jitter generator circuit, and then to an output driver. © KIPO & WIPO 2009 ...

CROSS POINT SWITCH WITH SERIALIZER AND DESERIALIZER FUNCTIONS

A programmable switch (10) of three or more ports, each port having data lines separate from lines sharing control and addressing. The programmable switch (10) includes internal logic control (20,22) and electronic modules (12,14) that accept and deserialize the control and address signals. The logic control (20,22) directs the data in signals to one or more of the output data lines. Since the data and control and addressing lines are separate, the control may act concurrently with the data to direct the data properly. The sending unit must synchronize such operations to ensure data coherency and proper timing. The data signal path from any input to any or all outputs is designed to have, typically, only a single logic gate or on transistor switch delay. © KIPO & WIPO 2007 ...

SWITCHING SYSTEM

METHOD AND DEVICE FOR SELECTING AN ADDRESS BIT IN A PACKET-SWITCHING NETWORK

Un réseau du commutation de paquets (100) comprend un ensemble de noeuds de commutation (110), appartenant chacun à un étage (101, 102, 103) du réseau . Chaque noeud d'un étage est connecté à un bus d'étage (220-1) qui indique ou noeud le rang de l'étage auquel il appartient, et comprend un circuit qui réagit à l'information acheminée par le bus d'étage associé en sélectionnant le bit dont le rang correspond au rang de l'étage, dans la zone de destination d'un paquet recu, en tant que bit à utiliser pour acheminer le paquet dans le noeud considéré.

METHODS FOR HARDWARE REDUCTION AND OVERALL PERFORMANCE IMPROVEMENT IN COMMUNICATION SYSTEM

The aim of the present invention is a method to achieve the customization of the communication network of a multicore communication system. This goal is achieved thanks to a method to design a multicore communication system, said communication system comprising a communication network having a plurality of switches and several elements communicating through the communication network, said method comprising the steps of: a) defining the communication network topology, comprising a number of switches, the architecture of said switches and the interconnection between said switches, b) defining routes to communicate among the elements through the switches according to the application running on the system, c) marking the input-to-output connections used within the switches traversed by these routes, d) removing all or part of the electronic components related to the non-marked connections.

NON-BLOCKING VIRTUAL SWITCH ARCHITECTURE

A non-blocking virtual switch architecture (Fig. 5) for a data communication network. The switch includes a plurality of input ports and output ports. Each input port may be connected directly to each output port by a directly connected network or by a mesh network. Thus, data packets may traverse the switch simultaneously with other packets. At each output port (618), buffer space is dedicated for queuing packets received from each of the input ports (Port A in-Port D in). An arbitration scheme is utilized to forward data from the buffers to the network. Accordingly, the use of a crossbar array, and associated bottle necks, are avoided. Rather, the system advantageously provides separate buffer space at each output port for every input port.

MATRIX SWITCH

L'invention porte sur un commutateur de matrices qui comprend un corps de commutateur (2), une section de prétraitement (1) ménagée sur le côté entrée du corps de commutateur de matrices (2), et une section de post-traitement (3) ménagée sur le côté sortie du corps de commutateur de matrices (2). La section de prétraitement (1), le corps de commutateur de matrices (2), et la section de post-traitement (3) comportent chacun un circuit qui convertit l'entrée de la ligne en données en parallèle ayant une largeur de bit préétablie, convertit les données en parallèle en données de série par une opération d'arrangement des bits à l'intérieur de la largeur de bit préétablie, et sort en ligne les données. Le corps de commutateur de matrices (2) est divisé par largeur de bit préétablie convertie en parallèle par la section de prétraitement (1), puis commuté.

Switch fabric with memory management unit for improved flow control

A method for controlling a flow of packet data in a memory management unit of a network switch fabric is disclosed. A first portion of a data packet is received at a port on an ingress bus ring of the network switch fabric. A class of service for the data packet is determined based on the first portion and the portion is stored in a packer RAM of the port based on the class of service. Subsequent portions of the data packet are stored in the packer RAM. Once the predetermined number of portions have been received, the predetermined number of portions is sent to a packet pool RAM. A reference pointer to a first predetermined number of portions is sent to a transaction queue once an end of packet is detected and an egress scheduler detects a presence of a ready packet in the transaction queue and notifies an unpacker of the ready packet. The unpacker puts the ready packet into a FIFO and the ready packet is sent to an ingress/egress module.

Configurable connection fabric for providing serial backplanes with adaptive port/module bandwidth

A configurable connection fabric between a switching fabric and a backplane allows any of the ports of the backplane to be connected to any of the ports of the switching fabric. The connection fabric receives bandwidth load requirements from modules connected to the backplane and uses these load requirements to determine the number of ports required to make a particular connection.

Distributed type switching system

A switching system for integratedly switching voice, data, image information and the like. The switching system comprises a plurality of front-end modules each adapted to perform a switching processing in association with a subscriber line or a trunk line, and a single or a plurality of central modules for interconnecting the plurality of front-end modules in star-type fashion and switching information prevailing between the front-end modules, in unit of block accommodating the information and a header added thereto to contain connection control information and in accordance with the contents of the header. The front-end modules are connected to the central module via inter-module highways each having frames occurring at a predetermined period and time slots contained in each frame to carry blocks.

Method and system for network switch element

Method and system for a network switch element is provided. The switch element includes a plurality of megaports, each megaport uniquely identified by a unique megaport address identifier for network addressing. Each megaport includes a plurality of operational ports, each operational port identified by a unique operational port address identifier. The switch element also includes a local crossbar for communication between the plurality of operational ports, and a shared logic module configured to provide common control of the plurality of operational ports within a megaport to allow operational ports to share resource of a single megaport to route network packets there between. The switch element also includes a global crossbar configured to allow communication between the megaports.

Sliced crossbar architecture with no inter-slice communication

A method and apparatus includes identifying a first portion of a first message in a first slice of a switch, the first message associated with a first priority, the first portion of the first message including a first routing portion specifying a network resource; identifying a second portion of the first message in a second slice of the switch, the second portion of the first message including the first routing portion; identifying a first portion of a second message in the first slice, the second message associated with a second priority, the first portion of the second message including a second routing portion specifying the network resource; identifying a second portion of the second message in the second slice, the second portion of the second message including the second routing portion; selecting, independently in each slice, the same one of the first and second messages based on the first and second priorities; sending the first portion of the selected message from the first slice ...

Making a flow ID for an exact-match flow table using a programmable reduce table circuit

An exact-match flow table structure stores flow entries. Each flow entry includes a Flow Id. A flow entry is generated from an incoming packet. The flow table structure determines whether there is a stored flow entry, the Flow Id of which is an exact-match for the generated Flow Id. In one novel aspect, a programmable reduce table circuit is used to generate a Flow Id. A selected subset of bits of an incoming packet is supplied as an address to an SRAM, so that the SRAM outputs a data value. The data value is supplied to a programmable lookup circuit such that the lookup circuit performs a selected type of lookup operation, and outputs a result value of a reduced number of bits. A multiplexer circuit is used to form a Flow Id such that the result value is a part of the Flow Id.

Integrated system and method for controlling telecommunication network data communicated over a local area network and storage data communicated over a storage area network

A method and apparatus for a communications network that executes a medium access control (MAC) protocol that permits multiple access to a shared medium or shared switching fabric. The MAC protocol uses a bandwidth allocator to regulate access to the network by sending a permission message to a node, allowing it to transmit to a specific set of nodes for a specific length of time. The medium and switching fabric can carry one or more protocols, each of varying framing format and native bitrate. The switching fabric provides a connection-oriented bufferless data transport service that preserves frame ordering. An illustrative embodiment uses a slotted master/slave time-division multiplexed access (TDMA) scheme to allow flexible provisioning of network bandwidth.

Indefinitely expandable high-capacity data switch

A data switch for a packet data switch includes switching nodes connected to each other in an interconnecting matrix, providing a multiplicity of data paths between an incoming data or telecom port and an outgoing data or telecom port of the data switch. The interconnecting switching nodes can achieve high capacity data switching by providing a partial switching solution at each node, distributing the switching load. A switching protocol for interconnecting switching nodes allows data packets to be selectively passed from any incoming port on an interconnecting switch node to any interconnecting switching node or outgoing port connected to it. In at least one example, the switching protocol has mechanisms in it to provide for the duplicating of the contents of the data packet and pass them to multiple interconnecting switching nodes or outgoing ports.

System, method and article of manufacture for transferring a packet from a port controller to a switch fabric in a switch fabric chipset system

A system, method and article of manufacture are provided for transferring a packet from a port controller to a switch fabric in a switch fabric system. Notification is received indicating that a packet has been processed in the port controller. The processed packet is assigned and linked to an output priority queue. Subsequently, the packet is retrieved via the link and transmitted from the port controller to the switch fabric.

MULTI-CHASSIS ROUTER WITH MULTIPLEXED OPTICAL INTERCONNECTS

A multi-chassis network device includes a plurality of nodes that operate as a single device within the network and a switch fabric that forwards data plane packets between the plurality of nodes. The switch fabric includes a set of multiplexed optical interconnects coupling the nodes. For example, a multi-chassis router includes a plurality of routing nodes that operate as a single router within a network and a switch fabric that forwards packets between the plurality of routing nodes. The switch fabric includes at least one multiplexed optical interconnect coupling the routing nodes. The nodes of the multi-chassis router may direct portions of the optical signal over the multiplexed optical interconnect to different each other using wave-division multiplexing.

Switсh-bаsеd nеtwоrk prосеssоr

А nеtwоrk prосеssоr соmprisеs аn input intеrfасе, аn оutput intеrfасе, а switсh соuplеd bеtwееn thе input аnd оutput intеrfасеs, аnd а plurаlitу оf prосеssing еlеmеnts соuplеd tо rеspесtivе bidirесtiоnаl pоrts оf thе switсh. Suсh prосеssing еlеmеnts inсludе, in аn illustrаtivе еmbоdimеnt, а sсhеdulеr, а sесuritу еnginе, а сlаssifiсаtiоn еnginе, а strеаm еditоr, еtс. Infоrmаtiоn аssосiаtеd with а givеn pасkеt rесеivеd viа thе input intеrfасе is sеquеntiаllу prосеssеd thrоugh multiplе оnеs оf thе prосеssing еlеmеnts in а sеriаl prосеssing оrdеr bаsеd оn switсhing оpеrаtiоns оf thе switсh. In thе illustrаtivе еmbоdimеnt, thе switсh саn pеrmit аnу dеsirеd intеrсоnnесtiоn оf thе vаriоus prосеssing еlеmеnts sо аs tо асhiеvе а pаrtiсulаr pасkеt prосеssing flоw аpprоpriаtе fоr а givеn аppliсаtiоn.

HIGHLY PARALLEL SWITCHING SYSTEMS UTILIZING ERROR CORRECTION II

Device for switching control in a communication network and corresponding network

MATRIX SWITCH

Modular Ethernet Switch architecture with G.Link and without Interface module addressing

Architecture and organization of a high performance metropolitan area telecommunications packet network

Switch method and protocol for making dynamic connections

Switching node for switching data signals carried in data packets

The switching node is provided with at least one switching element, which has a number n of input lines (E1...En) and a number n of output lines (A1...An) which can be connected as required via a space switch (RK) to the input lines, where a buffer memory (PS1...PSn) is allocated in each case to the input lines, in which memory k data packets occurring consecutively on the relevant input line can be stored before being forwarded to the output line designated in each case by address signals contained in the relevant data packet. The buffer memories (PS1...PSn) in each case have a plurality m k of outputs (1,...,m), via which m data packets which are stored in the relevant buffer memory and are to be forwarded to m different output lines can be fed simultaneously to a space switch (RK) which has mxn inputs and n outputs. ...

Fibre channel switching system and method

A modular Fibre Channel switch (100) includes a data switching path (109) and a message switching path (102) to provide logical point to point connections between switch ports. The data switching path (102) includes a bank of shared SRAM memory devices that are accessed in a time-sliced protocol by each switch port. A receiving switch port writes a data frame to the bank of shared SRAM and the transmitting switch port then reads the data frame from the shared SRAM thereby effecting the logical point to point connection. Because the switch port includes a frame logic circuit that allows for an arbitrary start of frame address, each frame can be written to the first available DRAM device thus eliminating the need to buffer the data frame while waiting for a predetermined DRAM device to cycle in the time sliced protocol. The message switching path includes a message crossbar switch that is barrel shifted in a time sliced fashion to effect message passing among the switch ports. The switch ...

MULTIPLE-PORT SHARED MEMORY INTERFACE AND ASSOCIATED METHOD

NETWORK SYSTEM, INFORMATION PROCESSING APPARATUS, AND METHOD OF CONTROLLING NETWORK SYSTEM

PROBLEM TO BE SOLVED: To improve both of latency and bandwidth, in a network system, an information processing apparatus, and a method of controlling the network system. SOLUTION: The network system includes a crossbar switch, a plurality of crossbar interfaces having ports connected to the crossbar switch, and a bypass route directly connecting crossbar interfaces forming a group for ports in which a frequency of use is greater than or equal to a predetermined value among the plurality of crossbar interfaces. COPYRIGHT: (C)2011,JPO&INPIT ...

ИНТЕРФЕЙС ШИРОКОПОЛОСНОЙ СИСТЕМЫ СВЯЗИ

Изобретение относится к системам передачи данных, которые предоставляют доступ к широкополосным системам из систем цифровой сети с комплексными услугами. Технический результат заключается в обеспечении сопряжения широкополосных систем с системами цифровой сети с комплексными услугами. Система содержит систему обработки данных сигнализации, выполненную с возможностью обработки данных сигнализации вызова из ISDN-системы и из асинхронной системы для выбора по меньшей мере одного из ISDN-соединения и асинхронного идентификатора для каждого вызова и выдачи управляющих сообщений, которые идентифицируют выбранные соединения и идентификаторы, и мультиплексор, выполненный с возможностью приема управляющих сообщений от системы обработки данных сигнализации и межсетевого сопряжения средств связи вызова между ISDN-системой и асинхронной системой с использованием выбранных соединений и идентификаторов на основе управляющих сообщений. 3 с. и 11 з.п.ф-лы, 24 ил.

УСТРОЙСТВО И СПОСОБ ДЛЯ КОММУТАЦИИ МНОЖЕСТВА СИГНАЛОВ С ПРИМЕНЕНИЕМ МНОГОСТУПЕНЧАТОЙ ОБРАБОТКИ ПРОТОКОЛА

... 1. Устройство для коммутации множества пакетно-ориентированных сигналов в сетях (18, 19), в особенности для коммутации и маршрутизации в сетях (18, 19), содержащее множество блоков (14) портов, имеющих один или более портов (15), причем порты имеют возможность соединения с сетями, коммутационный блок (16), который предпочтительно имеет функцию матричного переключателя, о меньшей мере, один первый блок (12) протоколов, который анализирует, по меньшей мере, часть сигналов и их назначение, отличающееся тем, что имеется множество других блоков (17) протоколов, которые непосредственно соотнесены с блоками (14) портов и классифицируют сигналы по их протоколу передачи, чтобы в зависимости от протокола передачи для одной части пакетов осуществить самостоятельную обработку протокола, а для другой части передать обработку протокола к первому блоку протоколов. 2. Устройство по п.1, отличающееся тем, что упомянутые другие блоки (17) протоколов обрабатывают только те протоколы, для которых не требуются ...

Verfahren und Vorrichtung zum Datenrahmenweiterleiten in einer Vermittlungsstelle

Packet exchange device with coupling field has each exchange control for each coupling matrix providing feedback of results to preceding exchange control

The packet exchange device has a coupling field provided by a number of coupling matrices and associated exchange controls (7), connected in a matrix or a cascade, each having an identification analyzer for identifying an input port in a packet route identfication and storing the couplings between input ports and output ports and a result analyzer for informing the identification analyzer of the acceptable couplings. Each exchange control provides feedback of the results to the preceding exchange control.

Serieller Multimedia Linienschalter für Parallelnetzwerke und ein heterogenes homologes Rechnersystem

Elektrische Räumschaltmatrix

Granting access to interconnect devices using sequence numbers

An Infiniband õ Architecture (IBA) switching fabric comprising a crossbar (22), including data buses (30), a request bus (32) and a grant bus (34), which interconnects many input/ouput end node devices (24) in a System Area Network (SAN) employs an arbitration scheme whereby any grant authorizing communication between a source device and a destination device is allocated a grant sequence number (78, fig. 5A), later to be compared with a reference sequence number (106, fig. 6). Each port (24) sends a routing request containing identifiers (eg. destination address) via an arbiter (36) which allocates a grant sequence, allowing a grant controller (64) of another port to associate a received grant with a specific packet. Queues of grants (102, fig. 6) in each port's data transmission module (62) subsequently have their grant sequence number compared to a reference transmit sequence number (108, fig. 6) to determine when they are executed, and to a pre-fetch reference number (117, fig. 6) in ...

Performance and power optimized computer system architectures and methods leveraging power optimized tree fabric interconnect

A performance and power optimized computer system architecture and method leveraging power optimized tree fabric interconnect are disclosed. One embodiment builds low power server clusters leveraging the fabric with tiled building blocks while another embodiment implements storage solutions or cooling solutions. Yet another embodiment uses the fabric to switch non-Ethernet packets, switch multiple protocols for network processors and other devices.

MEDIATION PROCEDURE AND - MINUTES FOR THE PRODUCTION OF DYNAMIC CONNECTIONS

CELLBASED UMWICKELTER WELLENFRONTARBITER WITH RANGE RESERVATION

PROCEDURE FOR THE OPERATION OF A FLOW CONTROL OF A CROSS SWITCHING SWITCH AND FLOW CONTROL

SEGMENTING AND RECCOMPOSITION OF DATA FRAMEWORKS

SYNCHRONIZATION OF CELL TRANSMISSION IN A PACKET SWITCHING PLACE

PACKET SWITCHING SYSTEM FOR TELECOMMUNICATIONS KNOTS

Crossbar switch and recursive scheduling

A crossbar switch has N input ports, M output ports, and a switching matrix with N×M crosspoints. In an embodiment, each crosspoint contains an internal queue, which can store one or more packets to be touted. Traffic rates to be realized between all Input/Output (IO) pairs of the switch are specified in an N×M traffic rate matrix, where each element equals a number of requested cell transmission opportunities between each IO pair within a scheduling frame of F time-slots. An efficient algorithm for scheduling N traffic flows with traffic rates based upon a recursive and fair decomposition of a traffic rate vector with N elements, is proposed. To reduce memory requirements shared row queue (SRQ) may be embedded in each row of the switching matrix, allowing the size of all the XQs to be reduced. To further reduce memory requirements, a shared column queue may be used in place of the XQs. The proposed buffered crossbar switches with shared row and column queues, in conjunction with the now scheduling algorithm and the DCS column scheduling algorithm, can achieve high throughout with reduced buffer and VLSI area requirements, while providing probabilistic guarantees on rate, delay and jitter for scheduled traffic flows.

Method and system for network switch element

Method and system for a network switch element is provided. The switch element includes a plurality of megaports, each megaport uniquely identified by a unique megaport address identifier for network addressing. Each megaport includes a plurality of operational ports, each operational port identified by a unique operational port address identifier. The switch element also includes a local crossbar for communication between the plurality of operational ports, and a shared logic module configured to provide common control of the plurality of operational ports within a megaport to allow operational ports to share resource of a single megaport to route network packets there between. The switch element also includes a global crossbar configured to allow communication between the megaports.

Tracking written addresses of a shared memory of a multi-core processor

Described embodiments provide a method of controlling processing flow in a network processor having one or more processing modules. A given one of the processing modules loads a script into a compute engine. The script includes instructions for the compute engine. The given one of the processing modules loads a register file into the compute engine. The register file includes operands for the instructions of the loaded script. A tracking vector of the compute engine is initialized to a default value, and the compute engine executes the instructions of the loaded script based on the operands of the loaded register file. The compute engine updates corresponding portions of the register file with updated data corresponding to the executed script. The tracking vector tracks the updated portions of the register file. The compute engine provides the tracking vector and the updated register file to the given one of the processing modules.

Application Non Disruptive Task Migration In A Network Edge Switch

An apparatus and a method are described for zero packet loss task migration in an network switch in a computer network. The invention relates to active or programmable networks, i.e. networks based on packet switching algorithms and switch configurations which are subject to change. A well-defined protocol enables an intelligent switch to migrate tasks from one forwarding engine to another without any packet loss. This enables the algorithms and configurations of the switch to be updated or modified arbitrarily.

Crosspoint switch with separate voltage sources for input and output ports

A crosspoint switch device has a plurality of input ports each connected to a respective voltage source and a plurality of output ports each connected to a respective voltage source. A switch array selectively provides signal paths between the input ports and the output ports. The voltage sources are separate from one another.

System and method for implementing a multistage network using a two-dimensional array of tiles

A network, including: a first tile having a processor, a first top brick connected to the processor, a first bottom brick, and a first intermediate brick; a second tile having a second intermediate brick and a second bottom brick; multiple connections connecting the first top brick with the second intermediate brick and the first intermediate brick with the second bottom brick using a passthrough on an intermediate tile between the first and second tiles, where the first, the intermediate, and the second tiles are positioned in a row; and a third tile having a plurality of caches connected to a third bottom brick, where the second and third tiles are positioned in a column, and the first bottom brick, the second bottom brick, and the third bottom brick belong to a bottom layer of the network, and where the first and second intermediate bricks belong to an intermediate layer of the network.

Method and system for reducing traffic disturbance in a communication network caused by intermittent failure

A method may include: (i) in response to clearing of a fault on a working path of a protection switching group to which a first network element is interfaced: (a) transitioning, by the first network element, its state to a first state in which a protection path of the protection switching group is active; and (b) initiating, by the first network element, a wait to restore timer, the wait to restore timer having a duration such that upon expiration of the timer, the first network element is configured to switch the working path to active; and (ii) in response to receiving a message from a second network element interfaced to the protection switching group indicating that a failure has occurred on the working path: (a) maintaining, by the first network element, its state in the first state; and (b) continuing, by the first network element, the wait to restore timer.

Compact load balanced switching structures for packet based communication networks

A switching node is disclosed for the routing of packetized data employing a multi-stage packet based routing fabric combined with a plurality of memory switches employing memory queues. The switching node allowing reduced throughput delays, dynamic provisioning of bandwidth and packet prioritization.

High speed fibre channel switch element

A high-speed Fibre Channel switch element in a Fibre Channel network is provided. The Fibre Channel switch element includes, a rate select module that allows a port in the Fibre Channel switch element to operate at a rate equal to and/or higher than 10 gigabits per second (“G”). The port may operate at 20 G, 40 G or at a rate greater than 40 G. Also, a cut status is provided for cut-through routing between ports operating at different speed. Plural transmit and receive lines are used for port operation at a rate equal to or higher than 10 G.

Method & device

A method for controlling data packet routing through a switching element having a first plurality of input ports and a second plurality of output ports, the method comprising the steps of: detecting issuance of a first congestion indicator from an output port of the switching element, the first congestion indicator relating to a first routing request from a first input port of the switching element; allowing reassertion of the first routing request after a first time period; detecting issuance of a second congestion indicator from the output port of the switching element, the second congestion indicator relating to a second routing request from a second input port of the switching element; allowing reassertion of the second routing request after a second time period, wherein the first and second time periods are such that reassertions of the first and second connection requests occur substantially simultaneously. Also provided is a device for controlling such data packet routing.

BUFFERLESS NONBLOCKING NETWORKS ON CHIP

Network on Chips (NoC)s with a bufferless and nonblocking architecture are described. Core processors are communicatively coupled together on a substrate with a set of routing nodes based on nonblocking process. A network component routes data packets through the routing nodes and the core processors via communication links. A bufferless cross bar switch facilitates the communication of the data packets and/or path setup packets through the communication links among source processors and destination processors. The communication links include one or more channels, in which a channel comprises a data sub-channel, an acknowledgement sub-channel and a release sub-channel. 1. A system , comprising:core processers that are communicatively coupled together at a substrate via routing nodes based on a set of nonblocking processes;a network component configured to route data packets through the routing nodes and the core processors via communication links; anda bufferless crossbar switch configured to facilitate communication of the data packets through the communication links;wherein a communication link of the communication links includes a set of channels that include a data sub-channel configured to communicate the data packets, an acknowledgement sub-channel configured to communicate an acknowledgement message, and a release sub-channel configured to communicate a release message.2. The system of claim 1 , wherein the acknowledgement sub-channel is further configured to communicate an ACK signal through the set of channels and in a first direction claim 1 , wherein the release sub-channel is further configured to set the set of channels to an idle state by communicating a RELEASE signal through the set of channels claim 1 , and wherein the data sub-channel and the release sub-channel are further configured to communicate in the second direction of communication that is opposite to the first direction.3. The system of claim 1 , wherein the bufferless crossbar switch ...

Switching device for routing data, comuter interconnection network and routing method using such device

The invention is directed to a switching device (S ij ) adapted to connects parts of a computer interconnection network, having N input ports (I a -I h ) and N output ports (O a -O h ), the device adapted for routing data packets by means of direct crosspoints (CP xy ), the direct crosspoints configured for enabling direct connectivity between each of the N input ports to a subset m<N of the output ports only, in accordance with connectivity needs of the computer interconnection network. Preferably, it furelm.) they comprises an additional circuitry (L) and additional crosspoints (AP x,L , AP L,y ) configured such that at least some of the input ports of the switching device can be indirectly connected to at least some of the output ports of the switching device, through the additional circuitry. The invention further concerns an interconnection network and a method for routing data.

Router and many-core system

According to one embodiment, a router includes a plurality of input ports and a plurality of output ports. The input ports receive a packet including control information indicating a type of access. Each of the input ports includes a first buffer and a second buffer which store the packet. The output ports output the packet. Each of the input ports selects at least one of the first buffer and the second buffer as a buffer in which the packet is stored on the basis of the control information and a state of the output port serving as a destination port of the packet.

CROSSBAR SWITCH AND RECURSIVE SCHEDULING

A crossbar switch has N input ports, M output ports, and a switching matrix with N×M crosspoints. In an embodiment, each crosspoint contains an internal queue (XQ), which can store one or more packets to be routed. Traffic rates to be realized between all Input/Output (IO) pairs of the switch are specified in an N×M traffic rate matrix, where each element equals a number of requested cell transmission opportunities between each IO pair within a scheduling frame of F time-slots. An efficient algorithm for scheduling N traffic flows with traffic rates based upon a recursive and fair decomposition of a traffic rate vector with N elements, is proposed. To reduce memory requirements a shared row queue (SRQ) may be embedded in each row of the switching matrix, allowing the size of all the XQs to be reduced. To further reduce memory requirements, a shared column queue may be used in place of the XQs. The proposed buffered crossbar switches with shared row and column queues, in conjunction with the row scheduling algorithm and the DCS column scheduling algorithm, can achieve high throughput with reduced buffer and VLSI area requirements, while providing probabilistic guarantees on rate, delay and jitter for scheduled traffic flows. 1. A crossbar switch for switching packets from inputs to outputs , said crossbar switch comprisingn input ports, each feeding an associated group of m virtual output queues;an n×m switching matrix, having n×m cross points arranged in n rows and m columns, and a buffer at each of said n×m cross points;n row queues, each one interposed between one of said groups of m virtual output queues, and cross-points in a respective one of said n rows,at least one de-multiplexer to feed a packet at each of said n input ports into one virtual output queue of its associated group of m virtual output queues, as dictated by routing information in said packet,at least one multiplexer to empty m virtual output queues in a group in accordance with a schedule, into ...

FABRIC CHIP HAVING A PORT RESOLUTION MODULE

A fabric chip includes a plurality of port interfaces, wherein each of the plurality of port interfaces includes a network chip interface (NCI) block having a port resolution module, and wherein the port resolution module is to determine which of the port interfaces is to receive a packet from the NCI block, and a crossbar block communicatively coupled with each of the NCI blocks in the plurality of port interfaces. 1. A fabric chip comprising:a plurality of port interfaces, wherein each of the plurality of port interfaces includes a network chip interface (NCI) block having a port resolution module, and wherein the port resolution module is to determine which of the port interfaces is to receive a packet from the NCI block; anda crossbar block communicatively coupled with each of the NCI blocks in the plurality of port interfaces.2. The fabric chip according to claim 1 , wherein the packet contains an identification of at least one destination node chip that is to receive the packet claim 1 , and wherein the port resolution module is to determine which of at least one of the port interfaces is to receive the packet based upon a comparison of the node chips contained in the identification and a preprogrammed correlation between the interface ports and the destination node chips.3. The fabric chip according to claim 2 , wherein the NCI block is composed of a network chip receiving (NCR) block and a network chip transmitting (NCX) block claim 2 , and wherein the NCR block contains the port resolution module.4. The fabric chip according to claim 2 , wherein the NCX block comprises a node pruning module to prune the identification by removing a destination node chip from the identification to which a multicast packet has been delivered prior to the multicast packet being delivered to another fabric chip.5. A switch fabric comprising:a first node chip;a destination node chip; anda first fabric chip comprising a plurality of port interfaces, wherein the first node chip is ...

Byte selection and steering logic for combined byte shift and byte permute vector unit

Exemplary embodiments of the present invention disclose a method and system for executing data permute and data shift instructions. In a step, an exemplary embodiment encodes a control index value using the recoding logic into a 1-hot-of-n control for at least one of a plurality of datum positions in the one or more target registers. In another step, an exemplary embodiment conditions the 1-hot-of-n control by a gate-free logic configured for at least one of the plurality of datum positions in the one or more target registers for each of the data permute instructions and the at least one data shift instruction. In another step, an exemplary embodiment selects the 1-hot-of-n control or the conditioned 1-hot-of-n control based on a current instruction mode. In another step, an exemplary embodiment transforms the selected 1-hot-of-n control into a format applicable for the crossbar switch.

SCALABLE MULTI-LAYER 2D-MESH ROUTERS

Architectures, apparatus and systems employing scalable multi-layer 2D-mesh routers. A 2D router mesh comprises bi-direction pairs of linked paths coupled between pairs of IO interfaces and configured in a plurality of rows and columns forming a 2D mesh. Router nodes are located at the intersections of the rows and columns, and are configured to forward data units between IO inputs and outputs coupled to the mesh at its edges through use of shortest path routes defined by agents at the IO interfaces. Multiple instances of the 2D meshes may be employed to support bandwidth scaling of the router architecture. One implementation of a multi-layer 2D mesh is built using a standard tile that is tessellated to form a 2D array of standard tiles, with each 2D mesh layer offset and overlaid relative to the other 2D mesh layers. IO interfaces are then coupled to the multi-layer 2D mesh via muxes/demuxes and/or crossbar interconnects. 1. A router chip comprising:a plurality of input-output (IO) interfaces, disposed proximate to a periphery of the router chip; each IO interface comprising an IO input and an IO output;a first plurality of interconnect paths, configured in a first two-dimensional (2D) mesh comprising a plurality of rows and columns, each interconnect path operatively coupled at opposing ends to an IO input and an IO output for a pair of IO interfaces disposed on opposite sides of the router chip, wherein a given row or column of the 2D mesh includes a pair of interconnect paths configured to transfer data in opposite directions;a first plurality of router nodes, each disposed at a respective row and column intersection, wherein each router node is configured to route data along a path either in the same direction via which the data arrived at the node or turn the data to be routed along a path in a direction perpendicular to the direction via which the data arrived at the node; anda plurality of additional interconnect paths operatively coupled between nodes along ...

FRAMEWORK FOR UNIVERSALLY SPECIFIED AFFINITY TOPOLOGIES WITH PARTIAL PATH INVALIDATION AND GENERALIZED NETWORK FLOWS

A method for setting up forwarding tables is described. A USAT part for a node is received. The USAT part includes glow definitions and a FGPL. Each glow describes network traffic flows and role instructions for the flows. Each FGP describes a role for the switching node; a validity rule; and relevant network topology. The method also includes determining a selected active FGP in the FGPL using the validity rule for the FGP, a network state and the ordering of the FGPs; initializing the glows, requesting a role identification to perform based on the selected FGP, determining the role instructions and instructing the TMS to update tables accordingly; and storing entries in software tables based on glows and the role instructions for the identified role, dynamically resolving conflicts among entries, and granting table updates to hardware tables. The tables include a software table for each hardware memory for forwarding packets. 120-. (canceled)21. A method comprising:receiving a universally specified affinity topology (USAT) part specific to a switching node, the USAT part including a definition for at least one glow and a fabric graph part list (FGPL), the FGPL being an ordered list of at least one fabric graph part (FGP),wherein each glow describes at least two flows of network traffic and role instructions for the switching node when handling each flow of the at least two flows, andwherein each FGP describes a role that the switching node is to perform in the FGP and a validity rule for the FGP;determining a selected active FGP in the FGPL based on the validity rule for the associated FGP;initializing the at least one glow;identifying which role that the switching node is to perform based on the selected active FGP in the FGPL;determining the role instructions for the identified role;storing at least one entry in a plurality of software tables based on the definition for the at least one glow and the role instructions for the identified role;dynamically resolving ...

LOW LATENCY COMPACT CLOS NETWORK CONTROLLER

Many network protocols, including certain Ethernet protocols, include specifications for multiplexing using of virtual lanes. Due to skews and/or other uncertainties associated with the process, packets from virtual lanes may arrive at the receiver out of order. The present disclosure discusses implementations of receivers that may use multiplexer based crossbars, such as Clos networks, to reorder the lanes. State-based controllers for the Clos networks and state-based methods to assign routes in are also discussed. 1. An electronic device comprising: an ingress stage comprising a plurality of ingress stage crossbars;', 'a middle stage comprising a plurality of middle stage crossbars; and', 'an egress stage comprising a plurality of egress stage crossbars; and, 'a Clos network comprising identify a respective ingress stage crossbar associated with a respective virtual lane and a respective egress stage crossbar associated with the respective virtual lane;', 'determine a set of available middle stage crossbars for the respective virtual lane based on the respective ingress stage crossbar to the respective stage crossbar;', 'if the set of available middle stage crossbars is empty, de-assign a previously assigned virtual lane when the set of available middle stage crossbars is empty., 'a Clos network controller configurable to, for each de-assigned virtual lane of a plurality of virtual lanes2. The electronic device of claim 1 , wherein the Clos network controller is configurable to claim 1 , if the set of available middle stage crossbars is not empty claim 1 , assign the respective virtual lane to one available middle stage of the set of available middle stage crossbars.3. The electronic device of claim 1 , wherein the Clos network controller comprises a stack that comprises a list of assigned virtual lanes.4. The electronic device of claim 3 , wherein assigning the respective virtual lane comprises pushing the respective virtual lane to the stack claim 3 , and ...

Fabric Chip Having Trunked Links

A fabric chip includes a plurality of port interfaces, in which each of the plurality of port interfaces includes a network chip interface (NCI) block having a port resolution module to determine which of the port interfaces is to receive a packet from the NCI block and a crossbar block communicatively coupled with each of the NCI blocks in the plurality of port interfaces. In addition, at least two of the plurality of port interfaces are to be connected to at least two port interfaces of another fabric chip as trunked links of a trunk. Moreover, the NCI blocks of the at least two of the plurality of port interfaces include a resource that keeps track of the port interfaces in the fabric chip that are connected to the trunk links of the trunk. 1. A fabric chip comprising: a network chip interface (NCI) block having a port resolution module to determine which of the port interfaces is to receive a packet from the NCI block; and', 'a crossbar block communicatively coupled with each of the NCI blocks in the plurality of port interfaces; and, 'a plurality of port interfaces, wherein each of the plurality of port interfaces includes,'}wherein at least two of the plurality of port interfaces are to be connected to at least two port interfaces of another fabric chip as trunked links of a trunk, and wherein the NCI blocks of the at least two of the plurality of port interfaces include a resource that keeps track of the port interfaces in the fabric chip that are connected to the trunked links of the trunk.2. The fabric chip according to claim 1 , wherein the resource comprises a bit-mask claim 1 , wherein each bit in the bit-mask corresponds to one of the port interfaces of the fabric chip.3. The fabric chip according to claim 1 , wherein the packet contains a destination-node-chip-mask that indicates which of the plurality of node chips the packet is to be transmitted claim 1 , and wherein the port resolution module is to implement a port resolution operation to determine ...

Pipelined configurable processor

A configurable processing circuit capable of handling multiple threads simultaneously, the circuit comprising a thread data store, a plurality of configurable execution units, a configurable routing network for connecting locations in the thread data store to the execution units, a configuration data store for storing configuration instances that each define a configuration of the routing network and a configuration of one or more of the plurality of execution units, and a pipeline formed from the execution units, the routing network and the thread data store that comprises a plurality of pipeline sections configured such that each thread propagates from one pipeline section to the next at each clock cycle, the circuit being configured to: (i) associate each thread with a configuration instance; and (ii) configure each of the plurality of pipeline sections for each clock cycle to be in accordance with the configuration instance associated with the respective thread that will propagate through that pipeline section during the clock cycle.

ARBITER CIRCUIT FOR CROSSBAR

An example arbiter circuit for a crossbar may include request circuits corresponding respectively to ingress ports of the crossbar; grant circuits corresponding respectively to egress ports of the crossbar; a request register; and a grant register. Each of the request circuits may be to request a connection between its corresponding ingress port and a target by writing an encoded identifier of the target to the request register. Each of the grant circuits may be to grant a connection between its corresponding egress port and one of the ingress ports by writing an encoded identifier of the ingress port to the grant register. 1. An arbiter circuit for a crossbar , comprising:request circuits corresponding respectively to ingress ports of the crossbar;grant circuits corresponding respectively to egress ports of the crossbar;a request register; anda grant register,wherein each of the request circuits is to request a connection between its corresponding ingress port and a target by writing a connection request comprising an encoded identifier of the target (target identifier) to the request register, andeach of the grant circuits is to grant a connection between its corresponding egress port and one of the ingress ports by writing an encoded identifier of the request circuit that corresponds to the ingress port (source identifier) to the grant register.2. The arbiter circuit of claim 1 ,wherein each of the grant circuits is to:determine whether any of the connection requests are relevant to the respective grant circuit based on the target identifiers stored in the request register, andfor each of the connection requests that is relevant to the respective grant circuit, determine whether to grant the respective connection request.3. The arbiter circuit of claim 2 ,wherein each of the grant circuits is to, for each connection request it grants, determine the source identifier to be written to the grant register based on the location within the request register at which the ...

ROUTER FABRIC FOR SWITCHING BROADCAST SIGNALS IN A MEDIA PROCESSING NETWORK

A router fabric for switching real time broadcast video signals in a media processing network includes a logic device configured to route multiple channels of packetized video signals to another network device, a crossbar switch configured to be coupled to a plurality of input/output components and to switch video data of the multiple channels between the logic device and the plurality of input/output components in response to a control instruction, and a controller configured to map routing addresses for each video signal relative to the system clock, and to send the control instruction with the mapping to the crossbar switch and the logic device. 1. A system for routing a digital video signal in a media distribution network comprising:a router fabric configured to receive a digital video signal from an input source, the digital video signal including a plurality of frames and respective frame markers for each frame in the digital video signal;wherein the router fabric is configured to determine whether at least one frame of the plurality of frames in the received digital video signal is aligned with a frame interval of a system clock; andwherein the router fabric is also configured to route the received digital video signal to an output component of a media distribution network when the at least one frame in the received digital video signal is aligned with the frame interval of the system clock.2. The system according to claim 1 , further comprising a logic device configured to buffer the digital video signal at a first data rate and upsample the digital video signal from the buffer to the output component at a second data rate that is different than the first data rate to allow tolerance for jitter on the input source.3. The system according to claim 2 , wherein the logic device is further configured to provide gaps between a payload of each frame and a front of the frame and an end of the frame.4. The system according to claim 2 , wherein claim 2 , by up- ...

High Performance, Scalable Multi Chip Interconnect

A flexible, scalable server is described. The server includes plural server nodes each server node including processor cores and switching circuitry configured to couple the processor to a network among the cores with the plurality of cores implementing networking functions within the compute nodes wherein the plurality of cores networking capabilities allow the cores to connect to each other, and to offer a single interface to a network coupled to the server.

Low Latency Compact Clos Network Controller

Many network protocols, including certain Ethernet protocols, include specifications for multiplexing using of virtual lanes. Due to skews and/or other uncertainties associated with the process, packets from virtual lanes may arrive at the receiver out of order. The present disclosure discusses implementations of receivers that may use multiplexer based crossbars, such as Clos networks, to reorder the lanes. State-based controllers for the Clos networks and state-based methods to assign routes in are also discussed. 1. An electronic device comprising:a Clos network in that comprises an ingress stage comprising a plurality of ingress stage crossbars, a middle stage comprising a plurality of middle stage crossbars, and an egress stage comprising a plurality of egress stage crossbars; and identify a respective ingress stage crossbar associated with a respective virtual lane and a respective egress stage crossbar associated with the respective virtual lane;', 'determine a set of available middle stage crossbars for the respective virtual lane based on the respective ingress stage crossbar to the respective stage crossbar;', 'if the set of available middle stage crossbars is not empty, assign the respective virtual lane to one available middle stage of the set of available middle stage; and', 'if the set of available middle stage crossbars is empty, de-assign a previously assigned virtual lane when the set of available middle stage crossbars is empty., 'a Clos network controller comprising a state machine configured to, for each de-assigned virtual lane of a plurality of virtual lanes2. The electronic device of claim 1 , wherein the Clos network controller comprises a stack that comprises a list of assigned virtual lanes.3. The electronic device of claim 2 , wherein the stack comprises a first-in-first-out (FIFO) stack or a first-in-last-out (FILO) stack.4. The electronic device of claim 3 , wherein assigning the respective virtual lane comprises pushing the respective ...

Methods to strengthen cyber-security and privacy in a deterministic internet of things

each DTF to achieve a desired level of security well beyond what is possible with existing schemes such as AES, by using very long keys. The encryption/decryption units also use a new serial permutation unit the very low hardware cost, which allows for exceptional security and very-high throughputs in FPGA hardware.

WIRELESS CROSS-CONNECT SWITCH

Methods and systems for wireless packet switching include determining a schedule for a plurality of transceivers in an enclosure. The schedule specifies which of the plurality of transceivers will act as a transmitter and which will act as a receiver. Data is transmitted from each transmitter to a corresponding receiver with a configured beamforming direction. Data is transmitted from a transmitter to a corresponding receiver by a wired connection if an angle of the beamforming direction is lower than a minimum angle. 1. A method for wireless packet switching , comprising:determining a schedule for a plurality of transceivers in an enclosure, wherein the schedule specifies which of the plurality of transceivers will act as a transmitter and which will act as a receiver;transmitting data from each transmitter to a corresponding receiver with a configured beamforming direction; andtransmitting data from a transmitter to a corresponding receiver by a wired connection if an angle of the beamforming direction is lower than a minimum angle.2. The method of claim 1 , further comprising repeating said steps of determining and transmitting data for subsequent transmission periods.3. The method of claim 2 , wherein each transmission period ends when a transmission queue accumulates a threshold number of packets that cannot reach a specified destination under the determined schedule.4. The method of claim 1 , wherein the plurality of transceivers are inwardly facing within the enclosure.5. The method of claim 1 , wherein the plurality of transceivers are arranged in a plurality of vertically arranged rings.6. The method of claim 5 , wherein the beamforming direction selects a radial direction and a vertical direction.7. The method of claim 1 , wherein determining the schedule comprises analyzing packets queued by the computing devices to determine destination devices.8. The method of claim 1 , wherein one or more transmitters are configured with a beamforming pattern that is ...

Distributed Switch Architecture Using Permutation Switching

A distributed switch architecture using permutation switching. In one embodiment, the distributed switch architecture facilitates connections between a plurality of ingress nodes and a plurality of egress nodes, wherein each of the plurality of ingress nodes and plurality of egress nodes are coupled to a plurality of ports (e.g., 40 gigabit Ethernet (GbE), 100 GbE, etc.). A plurality of crossbar switch modules are provided that are configured for coupling to a single output from each of the plurality of ingress nodes, and for coupling to a single input from each of the plurality of egress nodes. Permutations of connections for a crossbar switch module are defined by a permutation connection set that is stored in a permutation engine. Each permutation connection in the permutation connection can be designed to couple one of the outputs from the plurality of ingress nodes to one of the inputs from the plurality of ingress nodes, wherein the permutation connection set can ensures that each of the plurality of ingress nodes has an opportunity to connect with each of the plurality of egress nodes. 1. A switch , comprising:a plurality of ingress nodes, each of said plurality of ingress nodes having a plurality of outputs;a plurality of egress nodes, each of said plurality of egress nodes having a plurality of inputs;a plurality of crossbar switch modules, wherein a first of said plurality of crossbar switch modules is coupled to a single output from each of said plurality of ingress nodes, said first of said plurality of crossbar switch modules also being coupled to a single input from each of said plurality of egress nodes; anda permutation engine that is operative to store a permutation connection set, each permutation connection in said permutation connection set being designed to coupled to one of said outputs from said plurality of ingress nodes to one of said inputs from said plurality of ingress nodes, said permutation connection set ensuring that each of said ...

IMPLEMENTING HIERARCHICAL HIGH RADIX SWITCH WITH TIMESLICED CROSSBAR

A method and system are provided for implementing a hierarchical high radix switch with a time-sliced crossbar. The hierarchical high radix switch includes a plurality of inputs and a plurality of outputs. Each input belongs to one input group; each input group sends consolidated requests to each output, by ORing the requests from the local input ports in that input group. Each output port belongs to one output group; each output port grants one of the requesting input groups using a rotating priority defined by a next-to-serve pointer. Each output group consolidates the output port grants and allows one grant to pass back to an input group. Each input port in an input group evaluates all incoming grants in an oldest packet first manner to form an accept. Each input group consolidates the input port accepts and selects one accept to send to the output port. 1. A method for implementing hierarchical high radix switching with a time-sliced crossbar comprising:providing a switching device comprising a plurality of inputs and a plurality of outputs; each input port belongs to one input group; and each output port belongs to one output group;one said input port receiving a packet in its data queues for one said output port; and said input port requesting an output for one said output port;each said input group, sending consolidated requests to each output by ORing the requests from the local input ports in said respective input group;each said output port, granting one of the requesting input groups using a rotating priority defined by a next-to-serve pointer;each said output group consolidating the output port grants and allowing one grant to pass back to one said input group;each said input port in said input group evaluating all incoming grants in an oldest packet first manner to form an accept; and each said input group consolidating the input port accepts and selecting one accept to send to the corresponding output port.2. The method as recited in includes buffering ...

SYSTEMS AND METHODS FOR RADIO CHANNEL EMMULATION OF A MULTIPLE INPUT MULTIPLE OUTPUT (MIMO) WIRELESS LINK

Systems and methods for testing a wireless device under test (DUT) using over the air (OTA) channel emulation are disclosed herein. According to an aspect, a system is disclosed for testing a wireless DUT having a DUT antenna array. The system includes a probe antenna array, a shielded test chamber, a radio channel emulator, and a wireless communication emulator. The probe antenna array is electrically coupled with the radio channel emulator, and the shielded test chamber is configured to position the DUT antenna array in a radiative near field region of the plurality of probe antennas. The wireless communication emulator is operatively coupled with the radio channel emulator and is configured to emulate an electrical coupling between at least one antenna port of the DUT and at least one radio channel model of the radio channel emulator. 1. A system for testing a wireless device under test (DUT) having a DUT antenna array , the system comprising:a probe antenna array electrically coupled with a radio channel emulator;a shielded test chamber configured to position the probe antenna array in a radiative near field region of the DUT antenna array; anda wireless communication emulator operatively coupled with the radio channel emulator, wherein the radio channel emulator is configured to emulate an electrical coupling between at least one antenna port of the DUT and at least one radio channel model of the radio channel emulator.2. The system of claim 1 , wherein the DUT antenna is configured as a multiple-input and multiple-output (MIMO) antenna array.3. The system of claim 2 , wherein the system further comprises a crossbar switch electrically coupled between the probe antenna array and the radio channel emulator claim 2 , and a processor coupled with the crossbar switch claim 2 , the radio channel emulator claim 2 , and the wireless communication emulator.4. The system of claim 3 , wherein the wireless communication emulator comprises a plurality of MIMO antenna ports ...

DYNAMIC SLICE BANDWIDTH MULTIPLEXING BASED ON SLICE PRIORITY

In a slice-based network, slice multiplexers can be used to anchor inter-cloud tunnels across different clouds in a slice path. The slice multiplexers can dynamically change a total allocated bandwidth of an outer tunnel and reconfigure relative slice bandwidths of inner tunnels. This can result in an optimized bandwidth allocation that enforces slice priorities, maintains required SLA performance levels, and minimizes total allocated bandwidth on the network connection. The dynamic changes can be based on slice priority levels, total number of slices, and historical slice throughput. 1. A method for slice-based quality of service (“QoS”) , comprising:creating a network connection between first and second slice multiplexers at different clouds;determining that a first slice is utilizing less bandwidth across the network connection than allotted by a service level agreement (“SLA”);based on the determination, reconfiguring a first slice multiplexer to increase an allowed bandwidth of a second slice and decrease an allowed bandwidth of the first slice, wherein the increase and decrease is based on relative slice priority levels of the first and second slices;comparing a current bandwidth of the network connection to a total allowed bandwidth, wherein the current bandwidth accounts for the first and second slices; andbased on the comparison, changing the total allowed bandwidth of the network connection by setting limits at the first and second slice multiplexers, wherein the slice priority levels of the first and second slices is factored into determining the changed total allowed bandwidth.2. The method of claim 1 , further comprising setting a crossbar switch to route packets between multiple slice multiplexers including the first slice multiplexer claim 1 , wherein the routing depends on a slice path for the packets.3. The method of claim 1 , wherein the network connection is an intercloud tunnel having an outer tunnel and multiple inner tunnels claim 1 , the inner ...

DYNAMIC SLICE BANDWIDTH MULTIPLEXING BASED ON SLICE PRIORITY

In a slice-based network, slice multiplexers can be used to anchor inter-cloud tunnels across different clouds in a slice path. The slice multiplexers can dynamically change a total allocated bandwidth of an outer tunnel and reconfigure relative slice bandwidths of inner tunnels. This can result in an optimized bandwidth allocation that enforces slice priorities, maintains required SLA performance levels, and minimizes total allocated bandwidth on the network connection. The dynamic changes can be based on slice priority levels, total number of slices, and historical slice throughput. 1. A method for intercloud slice connectivity , comprising: multiple slice connections, each having a slice bandwidth allotment; and', 'a total bandwidth allotment; and, 'creating a slice multiplexer that connects traffic from a first cloud to a second cloud, the slice multiplexer comprisingsetting the total bandwidth allotment as a function of the slice bandwidth allotments multiplied by weighting factors, wherein the weighting factors correspond to slice priority levels.2. The method of claim 1 , wherein packets are routed to different channels within the slice multiplexer based on a slice identifier.3. The method of claim 1 , further comprising adjusting the total bandwidth and slice-specific bandwidth based on a first slice using less than its corresponding slice bandwidth allotment.4. The method of claim 3 , wherein the total bandwidth allotment decreases and the slice-specific bandwidth allotment for a second slice increases.5. The method of claim 1 , wherein multiple tenants share the multiple slice connections between the first and second clouds.6. The method of claim 1 , further comprising configuring connections between first and second service function chain steering nodes and the slice multiplexer.7. The method of claim 6 , wherein the configuration includes connecting the first and second steering nodes to a crossbar switch claim 6 , and wherein the crossbar switch routes ...

ASYNCHRONOUS SWITCHING SYSTEM AND METHOD

An asynchronous switching system and method for processing SDI data streams, the system and method utilizing one or more buffers for cleaning up an output of a dirty IP switch. 1. An asynchronous switch for cleaning video signal source transitions , the switch comprising:a buffer loader for receiving internet protocol video signals IPA, IPB from video sources A and B;buffers A, B for buffering signals IPA, IPB;a cleaner for receiving the buffered IP signals and constructing a cleanly transitioned IP signal available at a cleaner output; and,an IP to SDI converter for converting the cleaned output signal to an SDI format; i) in time period p1 buffer A receives and plays out X frames of signal IPA,', 'ii) in time period p2 buffer B receives Y frames of signal IPB,', 'iii) the playout of the X frames is followed by replay from the X frames during period p2, and', 'iv) play from buffer B begins after a start-of-frame is detected in buffer B., 'wherein'}2. The switch of wherein buffer A replay begins at substantially the same time that source B forwarding begins.3. The switch of wherein the buffer A replay includes replay from portions of two different frames.4. The switch of wherein the buffer A replay does not include replay from portions of two different frames.5. The switch of wherein the buffer A replay length is more than one frame but less than three frames requiring a buffer capacity in excess of two frames.6. The switch of wherein a buffer B detection length is more than one frame but less than two frames requiring a buffer capacity in excess of one frame.7. An asynchronous video signal switching method comprising the steps of:providing an SDI signal source A and an SDI signal source B;coupling the signal sources to an SDI to IP converter block;coupling the converter block to an IP switch;a cleanup switch causing the IP switch to forward a selected one of the converted signals to the cleanup switch;initially forwarding source A signals to the cleanup switch and ...

TECHNIQUES FOR COMPUTING DOT PRODUCTS WITH MEMORY DEVICES

Sparse representation of information performs powerful feature extraction on high-dimensional data and is of interest for applications in signal processing, machine vision, object recognition, and neurobiology. Sparse coding is a mechanism by which biological neural systems can efficiently process complex sensory data while consuming very little power. Sparse coding algorithms in a bio-inspired approach can be implemented in a crossbar array of memristors (resistive memory devices). This network enables efficient implementation of pattern matching and lateral neuron inhibition, allowing input data to be sparsely encoded using neuron activities and stored dictionary elements. The reconstructed input can be obtained by performing a backward pass through the same crossbar matrix using the neuron activity vector as input. Different dictionary sets can be trained and stored in the same system, depending on the nature of the input signals. Using the sparse coding algorithm, natural image processing is performed based on a learned dictionary. 120-. (canceled)21. A memory device comprising:an array of memory cells arranged in columns and rows; receive a set of first vectors and a second vector;', 'load the set of first vectors in the array of memory cells;', 'compute an third vector as a dot product of the second vector and the set of first vectors by feeding the second vector forward through the array of memory cells loaded with the first vector;', 'compute a fourth vector as a non-linear transform of the third vector,', 'compute a fifth vector as a dot product of the fourth vector and a transpose of the set of first vectors by feeding the fourth vector backward through the array of memory cells loaded with the set of first vectors;', 'compute a sixth vector as a difference between the fifth vector and the second vector; and', 'compute a new instance of the third vector as a dot product of the sixth vector and the first vector by feeding the sixth vector through the array ...

ROUTER FABRIC

A router fabric for switching real time broadcast video signals in a media processing network includes a logic device configured to route multiple channels of packetized video signals to another network device, a crossbar switch configured to be coupled to a plurality of input/output components and to switch video data of the multiple channels between the logic device and the plurality of input/output components in response to a control instruction, and a controller configured to map routing addresses for each video signal relative to the system clock, and to send the control instruction with the mapping to the crossbar switch and the logic device. 1. A router fabric for switching real time broadcast video signals in a media processing network , comprising:a logic device configured to route multiple channels of packetized video signals to another network device;a crossbar switch configured to be coupled to a plurality of input/output components and to switch the packetized video signals between the logic device and the plurality of input/output components in response to a control instruction; anda controller configured to dynamically map routing addresses for each video signal in an order relative to a system clock, and to send a system time and the control instruction with a mapped address to the crossbar switch and the logic device.2. The router fabric of claim 1 , wherein the crossbar switch is further configured to switch the packetized video signals of different video formats claim 1 , including at least two of baseband video claim 1 , packetized digital video claim 1 , or packetized compressed digital video.3. The router fabric of claim 2 , wherein the crossbar switch is further configured to switch within a video frame time interval without a glitch.4. The router fabric of claim 2 , wherein the crossbar switch is further configured to perform the switch of the packetized data signals from all video sources at a mutual time point.5. The router fabric of claim ...

PACKET HEADER FIELD EXTRACTION

Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline. 120-. (canceled)21. A network switch for use with at least one network , the network switch , when in operation , being to receive at least one ingress packet via the at least one network and also being to generate at least one egress packet for being output from the switch to the at least one network , the network switch comprising: at least one parser stage to parse and identify, at least in part, at least one subset of header fields of the at least one ingress packet; and', 'a plurality of match-action stages to perform operations related to matching and modifying, at least in part, the at least one subset of header fields;, 'at least one packet processing pipeline for processing the at least one ingress packet to generate the at least one egress packet, the at least one packet processing pipeline comprising a plurality of stages, the stages comprising the network switch comprises hardware circuitry;', 'when the network switch is in the operation, the network switch is to receive configuration data for use in programming, at least in part, the at least one pipeline, the configuration data defining, at least in part, the processing that is to be carried out by the at least one pipeline to generate the at least one egress packet;', 'the configuration data is to be generated based, at least in part, upon compilation of program language code that describes, ...

Communication network, associated measuring system, transportation means and method for building a communication network

and, for each switch, the first (30) and second (32) input terminals are each connected to different input blocks (E1, . . . , EN1) and the first (34) and second (36) output terminals are each connected to different output blocks (S1, . . . , SN2).

VIDEO ROUTER

The embodiments described herein provide a data transmission system comprising a plurality of video routers, a supervisory system for transmitting one or more router configuration signals to one or more video routers, and a control communication network for coupling the plurality of video routers and the supervisory system. Each router in the system comprises a backplane including a plurality of backplane connections, at least one line card and at least one fabric card. Each line card comprises a plurality of input ports and output ports where each input and output port is coupled to a respective external signal through the backplane. Each line card further comprises a line card cross-point switch having a plurality of input switch terminals and a plurality of output switch terminals. Each fabric card comprises a fabric card cross-point switch having a plurality of input switch terminal and a plurality of output switch terminals. Furthermore, each line card and each fabric card comprises a card controller where the card controller selectively couples one or more input switch terminals of a cross-point switch to the output switch terminals of that cross-point switch. The cross-point switches being manipulated by the card controller may belong to one or more different cards within the same video router. 1. A data transmission system , comprising:a plurality of video routers; anda controller communication network coupling the plurality of video routers; a backplane including a plurality of backplane connections;', a plurality of input and output ports, each input port and output port being coupled to a respective data signal through the backplane; and', 'a line card cross-point switch having a plurality of input switch terminals and a plurality of output switch terminals, wherein a first plurality of input and output switch terminals are coupled to a respective plurality of input and output ports and a second plurality of input and output switch terminals are coupled ...

COMMUNICATION NETWORK, ASSOCIATED MEASURING SYSTEM, MEANS OF TRANSPORT AND METHOD FOR CONSTRUCTING A COMMUNICATION NETWORK

This communication network () extends between a plurality of input blocks (E, . . . , E) including a predetermined number P1 of input ports, multiple of the number N1 of input blocks, and a plurality of output blocks (S, . . . , S), each output block including a number P2 of output ports (Z, . . . , Z) greater than or equal to the predetermined number of input ports. In this network, when the number P1 of input ports is even, the number N3 of switches is equal to: 2. The communication network according to claim 1 , wherein claim 1 , for each switch claim 1 , the first and second input terminals are connected to the input blocks via one of their input ports and the first and second output terminals are connected to the output blocks via one of their output ports claim 1 , and wherein each input port is respectively connected to a single one of the data links and each output port is respectively connected to a single one of the data links.324. The communication network according to claim 1 , wherein the data links () are point-to-point physical links.4. The communication network according to claim 1 , wherein by numbering the input blocks with a different index j going from 1 to N1 and the output blocks with a different index i going from 1 to N2 claim 1 , with N2 the number of output blocks claim 1 , the communication network respects the following rules for each input block numbered from 1 to N1 considered successively claim 1 , in order to connect the input blocks claim 1 , the output blocks and the switches to one another via the data links: a first group of P1 switches not connected to input and output blocks is selected,', 'the P1 input ports of the input block are respectively connected to one of the input terminals of one of the respective switches of the first group,', 'one of the output terminals of the switches of the first group is respectively connected to one of the output ports of the output block having an index i equal to the index j of the input ...

UNIVERSAL RADIO FREQUENCY ROUTER WITH AN AUTOMATIC GAIN CONTROL

Various embodiments are described herein for a radio frequency (RF) signal router. In one example embodiment, the RF router comprises a controller, an input stage, an intermediate stage and an output stage. The input stage includes RF input terminals, pre-processing circuit and input processors, where each RF input terminal receives an incoming RF signal, each pre-processing circuit processes the incoming RF signal based on its power level, and each input processor adjusts a power level of an input RF signal based on a first controller signal to generate a processed input RF signal. The intermediate stage comprises intermediate switch matrices coupled to a controller and input processors, and configured to route intermediate RF signals. The output stage comprises output processors coupled to the controller, where each output processor is configured to adjust a power level of an output RF signal based on a second controller signal and generate a processed output RF signal, and where the second controller signal corresponds to the first controller signal. 1. A radio frequency (RF) router comprising:a controller;a plurality of RF input terminals, wherein each RF input terminal is configured to receive an incoming RF signal;an input processor system coupled to the plurality of RF input terminals and the controller, the input processor system being configured to apply a power level adjustment to a pre-processed RF signal corresponding to the incoming RF signal based on an adjust control signal from the controller to generate a processed input RF signal;a routing system comprising a plurality of switch matrices coupled to the controller and each input processor system, the plurality of switch matrices being configured to route a plurality of intermediate RF signals; andan output processor system coupled to the controller and the routing system, the output processor system being configured to receive an output RF signal, and to adjust a power level of the output RF signal ...

NETWORK SWITCH ARCHITECTURE SUPPORTING MULTIPLE SIMULTANEOUS COLLECTIVE OPERATIONS

An apparatus includes a collective switch hardware architecture, including an input arrangement circuit including multiple input ports and multiple outputs. The input arrangement circuit routes its multiple input ports to selected ones of its outputs. The collective switch hardware architecture includes collective reduction logic coupled to the multiple outputs of the input arrangement circuit and having multiple outputs. The collective reduction logic includes ALU(s) and arbitration and control circuity. The ALU(s) and arbitration and control circuitry support multiple simultaneous collective operations from different collective classes, and support arbitrary input port and output port mapping to different collective classes. The collective switch hardware architecture further includes an output arrangement circuit including a multiple inputs coupled to the multiple outputs of the collective reduction logic and including multiple output ports. The output arrangement circuit is configured to route its multiple inputs to selected ones of its output ports. 1. An apparatus , comprising:collective switch hardware architecture, comprising:an input arrangement circuit comprising a plurality of input ports and plurality of outputs, the input arrangement circuit configured to route its plurality of input ports to a selected plurality of its outputs;collective reduction logic coupled to the plurality of outputs of the input arrangement circuit and comprising a plurality of outputs, the collective reduction logic comprising one or more arithmetic logic units (ALUs) and arbitration and control circuity, the one or more ALUs and arbitration and control circuitry configured to support multiple simultaneous collective operations from different collective classes, and the one or more ALUs and arbitration and control circuity configured to support arbitrary input port and output port mapping to different collective classes; andan output arrangement circuit comprising a plurality of ...

ULTRA-SCALABLE, DISAGGREGATED INTERNET PROTOCOL (IP) AND ETHERNET SWITCHING SYSTEM FOR A WIDE AREA NETWORK

Systems and Methods for IP and Ethernet switching in an ultra-scalable disaggregated wide area common carrier (WACC) disaggregated networking switching system. The WACC network switching system may include an Ethernet fabric having a set of M Ethernet switches each including a set of N switch ports, and a set of N input/output (IO) devices each including a set of W IO ports, a set of M Ethernet ports, an IO side packet processor (IOSP), and a fabric side packet processor (FSP). Each Ethernet switch may establish switch queues. Each IO device may establish a set of M hierarchical virtual output queues each including a set of N ingress-IOSP queues and ingress-virtual output queues, a set of W egress-IOSP queues, a set of M ingress-FSP queues, and a set of N hierarchical virtual input queues each including a set of N egress-FSP queues and egress-virtual input queues. 1. A wide area common carrier (WACC) disaggregated networking switching system comprising:an Ethernet fabric including a set of M Ethernet switches each comprising a set of N switch ports, each Ethernet switch to establish switch queues, wherein a variable i having a value ranging from 1 to M to denote the ith Ethernet switch of the set of M Ethernet switches, wherein a variable j having a value ranging from 1 to N to denote the jth switch port of the set of N switch ports; and a set of W IO ports, wherein a variable x having a value ranging from 1 to W to denote the xth IO port of the W IO ports;', 'a set of M Ethernet ports, wherein the ith Ethernet port of the jth IO device is connected to the jth switch port of the ith Ethernet switch;', establish a set of M hierarchical virtual output queues (H-VOQs) each comprising a set of N ingress-IOSP queues (I-IOSPQs) and I-VOQs, wherein the ith H-VOQ corresponds to the ith Ethernet port of the jth IO device, and wherein the jth I-IOSPQ of the ith H-VOQ corresponds to the jth IO device; and', 'establish a set of W egress-IOSP queues (E-IOSPQs), wherein the xth E ...

MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) WITH VERTICAL MEMORY COMPONENTS, RELATED SYSTEMS AND METHODS

Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components are disclosed. A 3D memory crossbar architecture with tight-pitched vertical monolithic intertier vias (MIVs) for inter-block routing and multiplexers at each tier for block access is used to shorten overall conductor length and reduce resistive-capacitive (RC) delay. Elimination of such long crossbars reduces the RC delay of the crossbar and generally improves performance and speed. Further, elimination of the long horizontal crossbars makes conductor routing easier. The MIVs, with their small run-length, can work without the need for repeaters (unlike the long crossbars), and control logic may be used to configure the memory banks based on use. 1. A three dimensional (3D) integrated circuit (IC) (3DIC) , comprising: a plurality of tiers, each tier having a memory cell;', 'a plurality of monolithic intertier vias (MIVs) spanning the plurality of tiers;', 'a first multiplexer disposed in a first tier among the plurality of tiers and coupled to at least a respective memory cell within the first tier of the plurality of tiers;', 'a second multiplexer disposed in a second tier among the plurality of tiers and coupled to at least a second respective memory cell within the second tier of the plurality of tiers; and', 'control logic configured to determine which, if any, memory cells are active and reconfigure usage of memory cells based on such determination., 'a memory structure comprising2. The 3DIC of claim 1 , wherein the control logic configured to reconfigure usage of memory cells deactivates unused memory cells so that power is conserved.3. The 3DIC of claim 1 , wherein the plurality of MIVs are configured to act as crossbars for the memory structure.4. The 3DIC of claim 1 , wherein the memory cell comprises random access memory (RAM).5. The 3DIC of claim 4 , wherein the RAM comprises static RAM (SRAM).6. The 3DIC of claim 1 , wherein the plurality of tiers ...

SWITCHING DEVICE

A switching device in a network system for transferring data includes one or more source line cards, one or more destination line cards and a switching fabric coupled to the source line cards and the destination line cards to enable data communication between any source line card and destination line card. Each source line card includes a request generator to generate a request signal to be transmitted in order to obtain an authorization to transmit data. Each destination line card includes a grant generator to generate and send back a grant signal to the source line card in response to the request signal received at the destination line card to authorize the source line card to transmit a data cell to the destination line card. 1. A switching device for transferring data packets , comprising:one or more source line cards each including a request generator to generate a request signal to be transmitted in order to obtain an authorization to transmit data;one or more destination line cards each including a grant generator to generate and send back a grant signal to a source line card in response to the request signal received at the destination line card to authorize the source line card to transmit a data cell to the destination line card; anda switching fabric coupled to the source line card and the destination line card, the switching fabric being configured to receive and transmit the request, grant and data cell to the appropriate line cards.2. The switching device of claim 1 , wherein the source line card further includes a data cell transmitter to transmit the data cell upon receiving the grant signal from the destination line card.3. The switching device of claim 2 , wherein the source line card further includes transmit logic to receive a request signal and a data cell which are unrelated to each other on each cell slot from the request generator and data cell transmitter claim 2 , respectively claim 2 , and transmit the request signal and the data cell ...

PACKET HEADER FIELD EXTRACTION

Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline. 120-. (canceled)21. At least one non-transitory machine readable medium storing program instructions for being executed by at least one machine , the program instructions being for use in association with generation of configuration data for use in programming , at least in part , at least one packet processing pipeline of a network switch , the at least one packet processing pipeline comprising at least one parser stage and a plurality of match-action stages , the network switch being for use with at least one network , the network switch , when in operation , being to receive at least one ingress packet via the at least one network , the at least one pipeline being to process the at least one ingress packet to generate at least one egress packet for being output from the switch to the at least one network , the program instructions , when executed by the at least one machine , resulting in the at least one machine being configured for performing operations comprising: user-desired functionality of the at least one pipeline;', 'at least one parse graph that indicates, at least in part, manner in which the at least one parser stage is to parse and identify, at least in part, the at least one subset of header fields of the at least one ingress packet, the parse graph including a plurality of nodes that correspond to headers in the at least one ingress packet ...

PACKET HEADER FIELD EXTRACTION

Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline. 120-. (canceled)21. Network switch circuitry for use with at least one network , the network switch circuitry , when in operation , being to receive at least one ingress packet via the at least one network and also being to generate at least one egress packet for being output from the network switch circuitry to the at least one network , the network switch circuitry comprising: at least one parser stage to parse and identify, at least in part, at least one subset of header fields of the at least one ingress packet;', 'a plurality of match-action stages to perform operations related to matching and modifying, at least in part, the at least one subset of header fields; and', 'at least one deparser stage for use in generating, at least in part, the at least one egress packet based upon the at least one subset of header fields modified, at least in part, by the plurality of header fields;, 'at least one packet processing pipeline for processing the at least one ingress packet to generate the at least one egress packet, the at least one packet processing pipeline comprising a plurality of stages, the stages comprising when the network switch circuitry is in the operation, the plurality of match-action stages are to perform the operations related to the matching and the modifying, at least in part, of the at least one subset of the header fields based upon ...

PACKET HEADER FIELD EXTRACTION

Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline. 120- (canceled)21. Network switch circuitry for use with at least one network , the network switch circuitry , when in operation , being to receive at least one ingress packet via the at least one network and also being to generate at least one egress packet for being output from the network switch circuitry , the network switch circuitry comprising:packet processing circuitry for processing the at least one ingress packet to generate the at least one egress packet, the packet processing circuitry being for being programmed for use in (1) identifying header field values of the at least one ingress packet that correspond to particular flow information of the at least one ingress packet, and (2) determining at least one particular action that the network switch circuitry is to take with respect to the processing of the at least one ingress packet, the packet processing circuitry being programmable, at least in part, based upon compilation of user-provided program instruction code, the user-provided program language code describing, at least in part, (1) manner that the packet processing circuitry is to parse the at least one ingress packet, and (2) match-action table entries that correlate possible packet flows with corresponding actions to be taken by the network switch circuitry, the compilation being for use in generating, at least in part, configuration ...

NETWORK-ON-CHIP USING TEMPERATURE-EFFECT-INVERSION AND OPERATION METHOD THEREOF

Provided is a network-on-chip (NoC). The NoC includes a plurality of routers configured to receive power through each corresponding power gating switch, and a controller configured to control a power gating switch of each of the plurality of routers based on temperature information provided from each of the plurality of routers and control a driving clock of the plurality of routers. The controller controls the power gating switch to turn off at least one first router by referring to the temperature information and over-scale a clock frequency of at least one turned-on second router. 1. A network-on-chip (NoC) comprising:a plurality of routers configured to receive power through each corresponding power gating switch; anda controller configured to control a power gating switch of each of the plurality of routers based on temperature information provided from each of the plurality of routers and control a driving clock of the plurality of routers,wherein the controller controls the power gating switch to turn off at least one first router by referring to the temperature information and over-scale a clock frequency of at least one turned-on second router.2. The NoC of claim 1 , wherein the over-scaled clock frequency is higher than a design maximum frequency of the at least one second router.3. The NoC of claim 2 , wherein the over-scaled clock frequency is determined with a value for providing a performance to execute a function of the at least one first router based on a temperature-effect-inversion phenomenon that a signal delay is reduced as a temperature increases.4. The NoC of claim 1 , wherein each of the plurality of routers comprises a temperature sensor for providing the temperature information.5. The NoC of claim 1 , wherein the plurality of routers comprise a Fin Field Effect Transistor (FinFET) or a transistor driven at a Ultra Low Voltage (ULV) of 1 V or less.6. The NoC of claim 1 , wherein the controller is connected to any one of the plurality of ...

Apparatus and method for low latency switching

A method of data switching. Data is received at least one input port of a crosspoint switch. The crosspoint switch configurably casts the data to at least one output port of the crosspoint switch. The or each output port of the crosspoint switch is connected to a respective input of a logic function device such as a FPGA. The logic function device applies a logic function to data received from the or each output port of the crosspoint switch, such as address filtering or multiplexing, and outputs processed data to one or more respective logic function device output interfaces. Also, a method of switching involving circuit switching received data to an output while also copying the data to a higher layer function.

METHOD AND APPARATUS FOR ANALYZING A COAXIAL NETWORK INFRASTRUCTURE

Method for generating a virtual representation of a coaxial network structure of a MoCA (Multimedia over Coaxial Alliance) network, which MoCA network comprises a plurality of node devices, including one network management device, wherein the node devices are interconnected through the coaxial network, the method includes determining a time lapse matrix having time lapse values Trepresenting propagation time through the coaxial network between node devices nand n, processing the time lapse matrix to establish a branch association for each node device with respect to the network management device, and storing virtual representation data of the coaxial network comprising the branch associations. 1. Method for generating a virtual representation of a coaxial network structure of a communications network , which communications network comprises a plurality of node devices , the plurality of node devices comprising a network management device and node devices nand n , wherein the plurality of node devices are interconnected through the coaxial network , the method comprising:{'sub': i,j', 'i', 'j, 'determining a time lapse matrix, the time lapse matrix comprising time lapse values Trepresenting propagation time through the coaxial network between node devices nand n;'}{'sub': i', 'j, 'processing the time lapse matrix to establish a branch association for each of node devices nand nwith respect to the network management device;'}storing virtual representation data of the coaxial network comprising the branch associations.2. The method of claim 1 , wherein storing virtual representation data includes storing a branch identifier for each node device.3. The method of claim 1 , comprising:{'sub': 0', '0, 'arranging the time lapse matrix with the network management device as a node device n, and columns and rows in magnitude order of time lapse values T with respect to n.'}4. The method of claim 3 , wherein processing the time lapse matrix comprises:comparing magnitude of time ...

Systems and methods for the design and implementation of input and output ports for circuit design

Systems and methods for providing input and output ports to connect to channels are provided. Input and output ports are the basic building blocks to create more complex data routing IP blocks. By aggregating these modular ports in different ways, different implementations of crossbar or Network on Chip (NoC) can be implemented, allowing flexible routing structure while maintaining all the benefits of channels such as robustness against delay variation, data compression and simplified timing assumptions.

SCALABLE TERAHERTZ PHASED ARRAY AND METHOD

A device and method for terahertz signal generation are disclosed. Oscillators are arranged in a two-dimensional array, each oscillator connected to a corresponding antenna. Each oscillator is unidirectional connected to its adjacent oscillators by a phase shifter. A method for generating a steerable terahertz signal utilizes an array of oscillators connected by corresponding phase shifters. A terahertz signal having a fundamental frequency is generated using the array. The phase shift of one or more of the phase shifters is varied in order to vary the fundamental frequency and/or steer the signal generated by the array. 1. A device for terahertz signal generation , comprising:a plurality of oscillators arranged in a two-dimensional array, each oscillator having an input, an antenna line, and an output, and wherein each oscillator has a fundamental frequency that is substantially the same as the other oscillators;a plurality of antennae, each antenna being connected to the antenna line of a corresponding oscillator of the plurality of oscillators; anda plurality of unidirectional phase shifters, each phase shifter connected between adjacent oscillators of the plurality of oscillators from the output of an oscillator to the input of an adjacent oscillator;wherein each oscillator is connected to each adjacent oscillator in the array by at least one phase shifter, the input of each oscillator being connected to an equivalent number of phase shifters as the corresponding output, and the input of each oscillator being connected to an equivalent number of phase shifters as each input of the other oscillators of the plurality of oscillators.2. The device of claim 1 , wherein each oscillator is a cross-coupled pair of transistors.3. The device of claim 2 , wherein the coupled pair includes a first transistor and a second transistor claim 2 , and wherein:a first transmission line connects a gate of the first transistor to a drain of the second transistor;a second ...

Multi-stage switch fabric fault detection and handling

In some examples, a switching system includes a plurality of fabric endpoints and a multi-stage switching fabric having a plurality of fabric planes each having a plurality of stages to switch data units between any of the plurality of fabric endpoints. A fabric endpoint of the fabric endpoints is configured to send, to a switch of a first one of the stages and within a first fabric plane of the plurality of fabric planes, a self-ping message destined for the fabric endpoint. The fabric endpoint is configured to send, in response to determining the fabric endpoint has not received the self-ping message after a predetermined time, an indication of a connectivity fault for the first fabric plane.

Two-Stage Crossbar Distributor and Method for Operation

An apparatus provides signal links of M with N signal connections. A first stage has first switching matrices, wherein the first switching matrices are designed to establish at least one switchable signal link between each associated first signal connection and an associated second signal connection. A second stage has a second switching matrix with a size of N×M. In a sub-area of the second switching matrix the intersection points X2that comprise switching elements are precise those that for N≧M satisfy the conditions: p−Σn≡q (mod n); 1≦p−Σ=1n≦nand 1≦q≦M. 3. The apparatus as claimed in claim 1 , wherein at least one of the first switching matrices comprises a matrix with switching elements only at those intersection points X1that lie on a main diagonal and on a half separate from the main diagonal.4. The apparatus as claimed in claim 1 , wherein at least one of the first switching matrices comprises a matrix with switching elements on all intersection points X1.5. The apparatus as claimed in claim 1 , wherein the sub-area comprises the entire second switching matrix.6. The apparatus as claimed in claim 1 , wherein k>=2.7. The apparatus as claimed in claim 1 , wherein N claim 1 , M>=3.8. The apparatus as claimed in claim 1 , wherein all nare the same.9. The apparatus as claimed in claim 1 , wherein the apparatus further comprises a third stage with kthird switching matrices claim 1 , wherein the third switching matrices mcomprise fifth signal connections and msixth signal connections claim 1 , which clamp third matrices claim 1 , wherein the third matrices comprise switching elements on all intersection points on a main diagonal and on a half of the third matrices separate from the main diagonal and wherein M is equal to a sum of all mfor u=1 to kand wherein in each case mfifth signal connections of each third switching matrix of the first stage has a signal link with in each case msignal connections of the M fourth signal connections of the second switching matrix. ...

Switch Fabric System And Data Switching Method

The present disclosure provides a switch fabric system, the system including M first crossbar units (CUs) and N second CUs, where each first CU includes L first input ports, a first arbiter, a first crossbar, and N first output ports. Each second CU includes M second input ports, a second arbiter, a second crossbar, and one second output port. M×N first output ports of the M first CUs are respectively coupled to N×M second input ports of the N second CUs, where N first output ports of each first CU are respectively coupled to and in a one-to-one correspondence with one second input port of each second CU in the N second CUs. In the example system, N equals M×L, and M, N, and L are all positive integers. 1. A switch fabric system , comprising:M first crossbar units (CUs) and N second CUs, wherein each first CU comprises: L first input ports, a first arbiter, a first crossbar, and N first output ports, and wherein each second CU comprises: M second input ports, a second arbiter, a second crossbar, and one second output port, and wherein M×N first output ports of the M first CUs are respectively coupled to N×M second input ports of the N second CUs, wherein N first output ports of each first CU are respectively coupled to and in a one-to-one correspondence with one second input port of each second CU in the N second CUs, wherein N=M×L, and M, N, and L are all positive integers; whereinany first input port in each first CU is configured to receive and cache data, and generate a first scheduling request according to the received data, wherein the data carries a destination port, the destination port is a second output port of any second CU in the N second CUs, and the first scheduling request is used to request to send the data to the destination port by using the N first output ports;the first arbiter is configured to perform scheduling and arbitration on the first scheduling request to determine a first target output port that matches the destination port and generate ...

Low level provisioning of network fabrics

A network fabric application coupled to a data link layer is provided with access to network elements in an optical fiber network. The network fabric application defines a network fabric configuration comprising at least a subset of the network elements, wherein the network fabric forms a multi-path communication network among the subset. The network fabric is configured to transmit data among networked devices in the network fabric along the multi-path communication network.

HIERARCHICAL SWITCHING DEVICE WITH DEADLOCKABLE STORAGE AND STORAGE PARTITIONS

An example hierarchical switching device may include sub-switches that form a fully interconnected all-to-all network, wherein the sub-switches comprise external output ports, internal input ports and internal output ports to exchange packets with other sub-switches within the fully interconnected all-to-all network. The switching device may further include a deadlockable storage, a storage partition and a switch controller. The deadlockable storage space is exclusively assigned to an internal input port of the internal input ports of the sub-switch including the deadlockable storage. The storage partition is exclusively assigned to an external output port of the external output ports and exclusively assigned to the internal input port. The switch controller is to route a packet destined for an external output port of a sub-switch through the internal input port of the sub-switch to the deadlockable storage or if the packet corresponds to the external output port, to the storage partition. 1. A hierarchical switching device comprising:a plurality of sub-switches forming a fully interconnected all-to-all network, the sub-switches comprising external output ports, internal input ports and internal output ports to exchange packets with other sub-switches within the fully interconnected all-to-all network;a deadlockable storage in a sub-switch of the plurality of sub-switches, the deadlockable storage being exclusively assigned to an internal input port of the internal input ports of the sub-switch;a storage partition exclusively assigned to an external output port of the external output ports and exclusively assigned to the internal input port; anda switch controller to route a packet destined for an external output port of a sub-switch through the internal input port of the sub-switch to the deadlockable storage or if the packet corresponds to the external output port, to the storage partition.2. The hierarchical switching device of claim 1 , wherein the deadlockable ...

Cabinet server system and server

The present disclosure relates to a cabinet server system, comprising a plurality of storage nodes and a plurality of calculation nodes. At least one serial storage signal switch node, respectively connected to the plurality of calculation nodes and the plurality of storage node, allocated to arrange the calculation node and the storage node. The present disclosure allocates a calculation node and a storage node through a serial storage signal switch node, and has a flexible configuration. Each calculation node can randomly allocate the number of hard disks according to service requirements, and the hard disks on each calculation node can be evenly allocated to multiple storage nodes to achieve load balancing while ensuring the security of the system data. Also, in the present disclosure, a single storage node can connect to the calculation nodes through two serial storage signal switch nodes, and when one path is not functioning, the hard disks on the storage node can still be accessed.

Networking device with orthogonal switch bars

A networking device with orthogonal switch bars may be provided. The networking device may comprise a first plurality of switch bars comprising leaf switches arranged parallel to one another. In addition, the networking device may comprise a second plurality of switch bars comprising top of pod switches arranged parallel to one another. Furthermore, the networking device may comprise a third plurality of switch bars comprising top of fabric switches arranged parallel to one another. The first plurality of switch bars, the second plurality of switch bars, and the third plurality of switch bars may be arranged mutually orthogonally. The first plurality of switch bars may be adjacent to and connected to the second plurality of switch bars and the second plurality of switch bars may be adjacent to and connected to the third plurality of switch bars.

SWITCHING MODULE

A fiber channel switching module can include an integrated trace buffer memory, a crossbar switch and a control processor disposed on a single line replaceable module (LRM). The trace buffer memory may be adapted to capture selected data traffic transiting the switch fabric based on pre-selected triggers. The selected data can be read out of the trace buffer memory and used for selected diagnostics. 120-. (canceled)21. A method for monitoring network data , the method comprising: 'a fabric crossbar including a network level monitoring section having simultaneous access to traffic flowing among all nodes connected to the fiber channel switch module;', 'providing a fiber channel switch module comprisingmonitoring, by the fiber channel switch module, network traffic;detecting a trigger event in network traffic between a first node and a second node; andcapturing, in response to detection of the trigger event data from network traffic between a third node and fourth node, the first, second, third, and fourth nodes all being different than each other.22. The method of claim 21 , wherein the monitoring includes monitoring network traffic based on monitoring parameters.23. The method of claim 22 , further comprising changing the monitoring parameters by reading and processing a fiber channel message sent to a well-known address of the fiber channel switch modules.24. The method of claim 23 , wherein the module is configured to be installed on an aircraft.25. The method of claim 24 , wherein the fiber channel message for changing monitoring parameters can be received and processed while the aircraft is in and the monitoring parameters can be dynamically updated while the aircraft is in flight.26. A method for continuous network-level monitoring of network data claim 24 , the method comprising: 'a first fabric crossbar including a first network-level monitoring section having simultaneous access to traffic flowing among all nodes connected to the first fiber channel switch ...

MULTI-CHASSIS SWITCH HAVING A MODULAR CENTER STAGE CHASSIS

A system may comprise a first group of switches, each switch including a first group of inputs and outputs, and a first group of controllers, each controller being independent from one another and corresponding to a switch of the first group of switches, to selectively control the switch to connect the switch's inputs with outputs. The first group of switches and controllers may be installed in a chassis. The system may comprise a second group of switches, each switch including a second group of inputs and outputs, and a second group of controllers, each controller corresponding to a switch of the second group of switches, to selectively control the switch to connect the switch's inputs with outputs. The second group of controllers may control and connect, via a group of control links, to the first group of controllers. 1. A system comprising: the first device being associated with an ingress stage and an egress stage of a switch fabric,', a first crossbar component associated with the ingress stage, and', 'a second crossbar component associated with the egress stage;, 'a first crossbar, associated with the switch fabric, comprising, 'the first device including], 'a first device,'} the second device being associated with a center stage of the switch fabric,', [ 'a third crossbar component associated with the center stage;', 'a second crossbar, associated with the switch fabric, comprising, a fourth crossbar component associated with the center stage,', 'the third crossbar component connecting, via one or more data links, to the first crossbar component and to the second crossbar component but not to the third crossbar, and', 'the fourth crossbar component connecting, via the one or more data links, to the first crossbar component and to the second crossbar component but not to the second crossbar;, 'a third crossbar, associated with the switch fabric, comprising], 'the second device including], 'a second device,'} 'the first controller connecting, via one or more ...

Sparse Coding With Memristor Networks

Sparse representation of information performs powerful feature extraction on high-dimensional data and is of interest for applications in signal processing, machine vision, object recognition, and neurobiology. Sparse coding is a mechanism by which biological neural systems can efficiently process complex sensory data while consuming very little power. Sparse coding algorithms in a bio-inspired approach can be implemented in a crossbar array of memristors (resistive memory devices). This network enables efficient implementation of pattern matching and lateral neuron inhibition, allowing input data to be sparsely encoded using neuron activities and stored dictionary elements. The reconstructed input can be obtained by performing a backward pass through the same crossbar matrix using the neuron activity vector as input. Different dictionary sets can be trained and stored in the same system, depending on the nature of the input signals. Using the sparse coding algorithm, natural image processing is performed based on a learned dictionary.

INDEFINITELY EXPANDABLE HIGH-CAPACITY DATA SWITCH

A data switch for a packet data switch includes switching nodes connected to each other in an interconnecting matrix, providing a multiplicity of data paths between an incoming data or telecom port and an outgoing data or telecom port of the data switch. The interconnecting switching nodes can achieve high capacity data switching by providing a partial switching solution at each node, distributing the switching load. A switching protocol for interconnecting switching nodes allows data packets to be selectively passed from any incoming port on an interconnecting switch node to any interconnecting switching node or outgoing port connected to it. In at least one example, the switching protocol has mechanisms in it to provide for the duplicating of the contents of the data packet and pass them to multiple interconnecting switching nodes or outgoing ports. 120-. (canceled)21. A data switching node of a plurality of data switching nodes , the data switching node comprising:a plurality of data ports; and receiving a data packet from a first data port of the plurality data ports;', 'determining a destination address of the data packet;', 'determining a routing path for the data packet through at least a portion of the plurality of data switching nodes based on the destination address of the data packet;', 'determining physical addresses of egress ports of the plurality of data switching nodes for the routing path;', 'modifying a packet header of the data packet to include physical addresses of egress ports; and', 'transmitting the data packet from a second data port of the plurality of data ports to another data switching node based on at least a portion of the physical addresses of the egress ports., 'a data switch configured for22. The data switching node of claim 21 , wherein the data packet is an Ethernet datagram.23. The data switching node of claim 21 , wherein the data packet is an asynchronous transfer mode (ATM) datagram.24. The data switching node of claim 21 , ...

WIRELESS CROSS-CONNECT SWITCH

Methods and systems for wireless packet switching include determining a schedule for transceivers in an enclosure. The schedule specifies which of the transceivers will act as a transmitter and which will act as a receiver. A beamforming direction for transmitting data from each transmitter to each corresponding receiver is determined. It is determined that an angle of the beamforming direction for at least one transmitter is lower than a minimum angle. Data is transmitted from a transmitter to the corresponding receiver by a wired connection, responsive to the determination that the angle of the beamforming direction is lower than a minimum angle. 1. A method for wireless packet switching , comprising:determining a schedule for a plurality of transceivers in an enclosure, wherein the schedule specifies which of the plurality of transceivers will act as a transmitter and which will act as a receiver;determining a beamforming direction for transmitting data from each transmitter to each corresponding receiver;determining that an angle of the beamforming direction for at least one transmitter is lower than a minimum angle; andtransmitting data from a transmitter to the corresponding receiver by a wired connection, responsive to the determination that the angle of the beamforming direction is lower than a minimum angle.2. The method of claim 1 , further comprising repeating said steps of determining and transmitting data for subsequent transmission periods.3. The method of claim 2 , wherein each transmission period ends when a transmission queue accumulates a threshold number of packets that cannot reach a specified destination under the determined schedule.4. The method of claim 1 , wherein the plurality of transceivers are inwardly facing within the enclosure.5. The method of claim 1 , wherein the plurality of transceivers are arranged in a plurality of vertically arranged rings.6. The method of claim 5 , wherein the beamforming direction selects a radial direction ...

Coherent memory interleaving with uniform latency

A data processing system includes a network of interconnected switch points having a plurality of edge switch points located at an edge of the network; a plurality of network interface controllers, wherein each edge switch point of the plurality of edge points is coupled to a corresponding network interface controller of the plurality of network interface controllers; a plurality of target controllers; and a crossbar switch coupled between the plurality of network interface controllers and the plurality of target controllers. The crossbar switch is configured to communicate read/write signals between any one of the plurality of network interface controllers and any one of the plurality of target controllers.

MODULAR, FLEXIBLY CONNECTED SWITCH-PORT INPUT-OUTPUT CARDS

Switches and groups of IO ports, conventionally integrated on a single shared PCB, may be divided into separate switch modules and IO modules that can be connected by high-speed low-loss management cables in a variety of configurations. Thereafter, the separate modules may be replaced independently of each other. Some of the management connections may be parallel, similar to production-data connections. Alternatively, a series of IO modules (e.g., a chain or a ring) may be managed by a single switch module using a management method. The management method may include collecting and updating configuration and status information specific to each of the IO modules and, by extension, each of their IO ports. This enables the switch module to recognize, and thereafter ignore, unconnected ports, removing the performance penalty that sometimes arises when fewer than all available ports are connected. It also allows the switch module to rapidly adjust to addition, subtraction, and replacement of connected IO modules. 1. A switching system , comprising:a switch module;a first input-output (“IO”) module comprising a first IO port and a second IO port;a first communication link carrying production data between the switch module and the first IO module;a second communication link carrying management messages between the switch module and the first IO module; anda power conduit supplying power from the switch module to the first IO module;wherein the switch module detects a “READY” status of the first IO module and a “connected or disconnected” state of the first IO port and the second IO port.2. The switching system of claim 1 , wherein the first communication link is physically separate from the second communication link.3. The switching system of claim 1 , wherein the power conduit is combined with the second communication link.4. The switching system of claim 1 , wherein the second communication link comprises a low-loss high-speed cable.5. The switching system of claim 1 , ...

Methods and Systems for Calibrating a Network Switch

A network switch includes first and second clock-and-data-recovery (CDR) circuits, a cross-bar switch electrically coupling the first and second CDR circuits, and a test pattern generation circuit electrically coupled to the first CDR circuit. The test pattern generation circuit is configured to generate a test pattern and transmit the test pattern from the first CDR circuit to the second CDR circuit via the cross-bar switch. The network switch also includes a test pattern checking circuit electrically coupled to the second CDR circuit and configured to verify the test pattern received at the second CDR circuit.

Scalable polylithic on-package integratable apparatus and method

Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

APPARATUS AND METHOD FOR FUSION OF COMPUTE AND SWITCHING FUNCTIONS OF EXASCALE SYSTEM INTO A SINGLE COMPONENT BY USING CONFIGURABLE NETWORK-ON-CHIP FABRIC WITH DISTRIBUTED DUAL MODE INPUT-OUTPUT PORTS AND PROGRAMMABLE NETWORK INTERFACES

Described is an apparatus which comprises: a Network-On-Chip fabric using crossbar switches, having distributed ingress and egress ports; and a dual-mode network interface coupled to at least one crossbar switch, the dual-mode network interface is to include: a dual-mode circuitry; a controller operable to: configure the dual-mode circuitry to transmit and receive differential signals via the egress and ingress ports, respectively, and configure the dual-mode circuitry to transmit and receive signal-ended signals via the egress and ingress ports, respectively. 1. An apparatus comprising:a Network-On-Chip fabric having crossbar switches and distributed ingress and egress ports; and a dual-mode circuitry; and', configure the dual-mode circuitry to transmit and receive differential signals via the egress and ingress ports, respectively, and', 'configure the dual-mode circuitry to transmit and receive signal-ended signals via the egress and ingress ports, respectively., 'a controller operable to], 'a dual-mode network interface coupled to at least one crossbar switch, the dual-mode network interface is to include2. The apparatus of claim 1 , wherein the controller is an input-output (IO) port controller and comprises:a network controller which is operable to configure the dual-mode circuitry to transmit and receive the differential signals via the egress and ingress ports, respectively.3. The apparatus of claim 2 , wherein the controller is an IO port controller and comprises:a memory controller which is operable to configure the dual-mode circuitry to transmit and receive the signal-ended signals via the egress and ingress ports, respectively.4. The apparatus of claim 3 , wherein the memory controller and network controller are selectable by a multiplexer.5. The apparatus of claim 1 , wherein the dual-mode network interface comprises:a programmable routing table which is to provide a destination port identifier according to an address field in an incoming packet header ...

SPRAYING FOR UNEQUAL LINK CONNECTIONS IN AN INTERNAL SWITCH FABRIC

In general, techniques are described for facilitating balanced cell handling by fabric cores of a fabric plane for an internal device switch fabric. In some examples, a routing system includes a plurality of fabric endpoints and a switching fabric comprising a fabric plane to switch cells among the fabric endpoints. The fabric plane includes two fabric cores and one or more inter-core links connecting the fabric cores. Each fabric core selects an output port of the fabric core to which to route a received cell of the cells based on (i) an input port of the fabric core on which the received cell was received and (ii) a destination fabric endpoint for the received cell, at least a portion of the selected output ports being connected to the inter-core links, and switches the received cell to the selected output port. 1. A routing system comprising:a plurality of fabric endpoints; anda switching fabric comprising a fabric plane to switch cells among the fabric endpoints,wherein the fabric plane includes two fabric cores and one or more inter-core links connecting the fabric cores,wherein each fabric core is configured to select an output port of the fabric core to which to route a received cell of the cells based on (i) an input port of the fabric core on which the received cell was received and (ii) a destination fabric endpoint for the received cell, at least a portion of the selected output ports being connected to the inter-core links, and switch the received cell to the selected output port.2. The routing system of claim 1 , wherein each fabric core includes a routing table that maps an input port to one more output ports to route the received cell based on (i) an input port of the fabric core on which the received cell was received and (ii) a destination fabric endpoint for the cell.3. The routing system of claim 2 , wherein at least a portion of the input ports are mapped to at least two output ports.4. The routing system of claim 3 , wherein for the portion of ...

ROUTER FABRIC

A router fabric for switching real time broadcast video signals in a media processing network includes a logic device configured to route multiple channels of packetized video signals to another network device, a crossbar switch configured to be coupled to a plurality of input/output components and to switch video data of the multiple channels between the logic device and the plurality of input/output components in response to a control instruction, and a controller configured to map routing addresses for each video signal relative to the system clock, and to send the control instruction with the mapping to the crossbar switch and the logic device. 1. A media signal routing system for routing and distributing media content , the media signal routing system comprising:a synchronized media router configured to route a plurality of packetized media signals to at least one output of the media signal routing system, the plurality of packetized media signals including at least one IP packetized video signal; anda media routing controller configured to control the synchronized media router to synchronously route data packets of the at least one IP packetized video signal in accordance with a system clock, such that the synchronized media router is configured to switch without at least one glitch between outputting the at least one IP packetized video signal and another media signal of the packetized media signals to the at least one output for media content distribution.2. The media signal routing system according to claim 1 , wherein the plurality of packetized media signals further include at least one of a baseband video stream and a compressed digital stream.3. The media signal routing system according to claim 1 , further comprising an IP gateway configured to receive and output the at least one IP packetized video signal to the synchronized media router when the data packets of the at least one IP packetized video signal are time aligned to clock frames of the system ...

MATRIX OF ON-CHIP ROUTERS INTERCONNECTING A PLURALITY OF PROCESSING ENGINES AND A METHOD OF ROUTING USING THEREOF

Embodiments of the present invention relate to a scalable interconnection scheme of multiple processing engines on a single chip using on-chip configurable routers. The interconnection scheme supports unicast and multicast routing of data packets communicated by the processing engines. Each on-chip configurable router includes routing tables that are programmable by software, and is configured to correctly deliver incoming data packets to its output ports in a fair and deadlock-free manner. In particular, each output port of the on-chip configurable routers includes an output port arbiter to avoid deadlocks when there are contentions at output ports of the on-chip configurable routers and to guarantee fairness in delivery among transferred data packets. 1. A chip comprising a network , wherein the network includes:a plurality of processing engines; anda matrix of on-chip routers, wherein each of the on-chip routers is communicatively coupled with a distinct group of the processing engines and with on-chip routers nearest to that on-chip router in the matrix of on-chip routers, and wherein each of the on-chip routers includes input ports, output ports, and an output port arbiter at each of the output ports, wherein the output port arbiter uses a global grant vector shared by all output port arbiters of that on-chip router and a local grant vector unique to that output port arbiter to grant a query request from one of the input ports.2. The chip of claim 1 , wherein the plurality of processing engines communicates together through the matrix of on-chip routers.3. The chip of claim 1 , wherein the network is scalable to support additional processing engines.4. The chip of claim 3 , wherein the additional processing engines are coupled with the plurality of on-chip routers.5. The chip of claim 3 , wherein additional on-chip routers are added to the matrix claim 3 , and the additional processing engines are coupled with the additional on-chip routers.6. The chip of claim ...

SYSTEM AND METHOD FOR DATA CENTER OPTICAL CONNECTION

A connectivity device permits simplified connections for realizing complex networking topologies using lower cost components. The device can be optically passive, or can have an active aspect to control switching to realize additional topology related features. The device permits cabling to be simplified while reducing cost to permit implementations of complex networking topologies to be realized faster and with greater reliability. The device aids in scaling out a network implementation and can provide connectivity for an arbitrary number of nodes with efficient capacity usage. 1. A fiber shuffle device for implementing network connectivity , comprising:a housing that includes a connector panel;at least four optical connectors mounted to the connector panel for receiving an optical cable connection; anda plurality of optical fibers in the housing, each one of the at least four optical connectors being coupled to each other via at least one optical fiber each in the plurality of optical fibers.2. The fiber shuffle device according to claim 1 , further comprising an optical fiber cable connected on one end to a first optical connector of the at least four optical connectors and connected on another end to a second optical connector of the at least four optical connectors to form a loop back connection.3. The fiber shuffle device according to claim 1 , further comprising an optical fiber cable connected on one end to a first optical connector of the at least four optical connectors and connected on another end to an optical connector for another fiber shuffle device to form cascaded fiber shuffle devices.4. The device according to claim 1 , further comprising a plurality of optical nodes claim 1 , each optical node being connected to an optical connector to form a physical network topology.5. The device according to claim 1 , further comprising:a plurality of optical transceivers located within the housing, each optical transceiver being coupled to at least one of the ...

SYSTEM AND METHOD FOR SUPPORTING CREDIT MANAGEMENT FOR OUTPUT PORTS IN A NETWORKING DEVICE

A system and method can support efficient packet switching in a network environment. A networking device, such as a network switch, which includes a crossbar fabric, can be associated with a plurality of input ports and a plurality of output ports. Furthermore, the networking device operates to detect a link state change at an output port on the networking device. The output port can provide one or more credits to an output scheduler, and the output scheduler allows one or more packets targeting the output port to be dequeued from one or more virtual output queues, based on the one or more credits. 1. A method for supporting packet switching in a network environment , comprising:detecting a link state change at an output port on a networking device, which includes a plurality of input ports and a plurality of output ports;providing, via the output port, one or more credits to an output scheduler; andallowing, via the output scheduler, one or more packets targeting the output port to be dequeued from one or more virtual output queues, based on the one or more credits.2. The method according to claim 1 , further comprising:allowing the networking device to be a network switch, which includes a crossbar fabric.3. The method according to claim 1 , further comprising:storing, via one or more input ports, said one or more packets into said one or more said virtual output queues.4. The method according to claim 1 , further comprising:allowing said one or more credits to be one or more initial credits that are received from a remote traffic destination, when the output port is up.5. The method according to claim 1 , further comprising:allowing said one or more credits to be one or more link down credits, which is configured by the output port, when the output port is down.6. The method according to claim 1 , further comprising:setting, via the output scheduler, the one or more credits to be maximum credits available.7. The method according to claim 6 , further comprising: ...

SYSTEM AND METHOD FOR SUPPORTING EFFICIENT VIRTUAL OUTPUT QUEUE (VOQ) PACKET FLUSHING SCHEME IN A NETWORKING DEVICE

A system and method can support packet switching in a network environment. The system can include an ingress buffer on a networking device, wherein the ingress buffer, which includes one or more virtual output queues, operate to store one or more incoming packets that are received at an input port on the networking device. Furthermore, the system can include a packet flush engine, which is associated with the ingress buffer, wherein said packet flush engine operates to flush a packet that is stored in a said virtual output queue in the ingress buffer, and notify one or more output schedulers that the packet is flushed, wherein each output scheduler is associated with an output port. 1. A system for supporting packet switching in a network environment , comprising:an ingress buffer on a networking device, wherein the ingress buffer, which includes one or more virtual output queues, operate to store one or more incoming packets that are received at an input port on the networking device; and flush a packet that is stored in a said virtual output queue in the ingress buffer, and', 'notify one or more output schedulers that the packet is flushed, wherein each output scheduler is associated with an output port., 'a packet flush engine associated with the ingress buffer, wherein said packet flush engine operates to'}2. The system according to claim 1 , wherein:the networking device is a network switch, which includes a crossbar fabric.3. The system according to claim 1 , wherein: enqueue an incoming packet into one or more buffers associated with the virtual output queue, and', 'inform said one or more output schedulers about an arrival of the incoming packet that is enqueued., 'said virtual output queue operates to'}4. The system according to claim 3 , wherein: schedule the input port to forward a packet to an output port that is associated with said output port arbiter, and', 'update a scoreboard associated with said output port arbiter., 'each said output scheduler is ...

SYSTEM AND METHOD FOR SUPPORTING EFFICIENT BUFFER REALLOCATION IN A NETWORKING DEVICE

A system and method can support efficient packet switching in a network environment. The system can comprise an ingress buffer on a networking device. The ingress buffer operate to store one or more incoming packets that are received at an input port on the networking device, wherein the input port is associated with a plurality of source virtual lanes (VLs). Furthermore, the ingress buffer operate to reallocate buffer resource in the ingress buffer from being associated with a first source VL in the plurality of source VLs to being associated with a second source VL in the plurality of source VLs, and send an initial credit update to the input port for the first source VL and the second source VL. 1. A method for supporting packet switching in a network environment , comprising:storing one or more packets that are received at an input port in an ingress buffer on a networking device, wherein the input port is associated with a plurality of source virtual lanes (VLs);reallocating buffer resource in the ingress buffer from being associated with a first source VL in the plurality of source VLs to being associated with a second source VL in the plurality of source VLs; andsending an initial credit update to the input port for the first source VL and the second source VL.2. The method according to claim 1 , further comprising:allowing the networking device to be a network switch, which includes a crossbar fabric.3. The method according to claim 1 , further comprising:allowing the ingress buffer to include a plurality of virtual output queues, wherein each said virtual output queue operates to store one or more packets targeting an output port.4. The method according to claim 3 , further comprising:selecting a virtual output queue that is associated with the first source VL and has a highest occupancy.5. The method according to claim 4 , further comprising:flushing one or more packets from said virtual output queue.6. The system according to claim 5 , further comprising: ...

ADAPTIVE COMMUNICATION NETWORK WITH CROSS-POINT SWITCHES

A cross-point switch system forming an adaptive communication network between a plurality of switches includes a plurality of ports connected to the plurality of switches, wherein the plurality of switches are connected to one another via a Port Aggregation Group (PAG) comprising multiple ports with a same set of endpoints between two switches; and a cross-point switch fabric configured to connect the plurality of ports between one another, wherein the cross-point switch fabric is configured to rearrange bandwidth in a PAG due to congestion thereon without packet loss. 1. A cross-point switch system forming an adaptive communication network between a plurality of switches , the cross-point switch comprising:a plurality of ports connected to the plurality of switches, wherein the plurality of switches are connected to one another via a Port Aggregation Group (PAG) comprising multiple ports with a same set of endpoints between two switches; anda cross-point switch fabric configured to connect the plurality of ports between one another,wherein the cross-point switch fabric is configured to rearrange bandwidth in a PAG due to congestion thereon without packet loss.2. The cross-point switch system of claim 1 , wherein the multiple ports in the PAG are filled in a sequential order by the switches to keep ports free to rearrange the bandwidth.3. The cross-point switch system of claim 1 , wherein the adaptive communication network is a packet network with the plurality of switches comprising packet switches at edges and the cross-point switch system in-between.4. The cross-point switch system of claim 3 , wherein each the plurality of switches are connected to a small subset of the plurality of switches in a mesh network configuration.5. The cross-point switch system of claim 1 , wherein the cross-point switch system is configured to detect which ports are carrying traffic and which are empty and used to rearrange the bandwidth.6. The cross-point switch system of claim 5 , ...

UNIVERSAL RADIO FREQUENCY ROUTER WITH AN AUTOMATIC GAIN CONTROL

Various embodiments are described herein for a radio frequency (RF) signal router. In one example embodiment, the RF router comprises a controller, an input stage, an intermediate stage and an output stage. The input stage includes RF input terminals, pre-processing circuit and input processors, where each RF input terminal receives an incoming RF signal, each pre-processing circuit processes the incoming RF signal based on its power level, and each input processor adjusts a power level of an input RF signal based on a first controller signal to generate a processed input RF signal. The intermediate stage comprises intermediate switch matrices coupled to a controller and input processors, and configured to route intermediate RF signals. The output stage comprises output processors coupled to the controller, where each output processor is configured to adjust a power level of an output RF signal based on a second controller signal and generate a processed output RF signal, and where the second controller signal corresponds to the first controller signal. 1. A radio frequency (RF) router comprising:a controller; a plurality of RF input terminals, wherein each RF input terminal is configured to receive an incoming RF signal;', 'a pre-processing circuit coupled to each RF input terminal and the controller, the pre-processing circuit configured to process the incoming RF signal to generate a pre-processed RF signal based on a first signal from the controller; and', 'an input processor coupled to each pre-processing circuit and the controller, the input processor being configured to process the pre-processed RF signal by adjusting a power level of the corresponding pre-processed RF signal based on a second signal from the controller to generate a processed input RF signal;, 'an input stage comprisingan intermediate stage comprising a plurality of intermediate switch matrices coupled to the controller, each intermediate switch matrix being coupled to each input processor, ...

High Performance, Scalable Multi Chip Interconnect

A flexible, scalable server is described. The server includes plural server nodes each server node including processor cores and switching circuitry configured to couple the processor to a network among the cores with the plurality of cores implementing networking functions within the compute nodes wherein the plurality of cores networking capabilities allow the cores to connect to each other, and to offer a single interface to a network coupled to the server. 116-. (canceled)17. A server node , comprising: 'an array of interconnected tiles with each of the tiles including a processor and a switch, with switches of the tiles configurable to couple the array of interconnected tiles to network among the processors;', 'a plurality of tiled compute nodes, with multiple ones of the plurality of tiled compute nodes each comprising gather packet data; and', 'transmit the packet data to a transmission physical interface for direct memory access (DMA) transmission from a first one of the plurality of compute nodes directly to another of the compute nodes in the array of interconnected tiles using physical addresses; and, 'a direct memory access engine configurable toswitching circuitry configured to couple the plurality of tiled compute nodes to an external network, with the switching circuitry configured to provide a network function within the server node.18. The server node of wherein the direct memory access engine is further configurable to move the packet data from an ingress port to the egress port.19. The server node of wherein the direct memory access engine moves data at an ingress port to the egress port under control of endpoint software.20. The server node of wherein the endpoint software executes one or more of:load balancing, and fast path routing.21. The server node of wherein the server node is configured with fast path software that processes network processing tasks according to whether the processing task is a common task or an uncommon task.22. The ...

USE OF STASHING BUFFERS TO IMPROVE THE EFFICIENCY OF CROSSBAR SWITCHES

A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery. 1. A crossbar switch comprising:a switching fabric; anda plurality of stash partitions coupled to the switching fabric, the stash partitions forming a stash storage pool from both of input buffers and output buffers of the crossbar switch.2. The switch of claim 1 , further comprising one or more storage virtual channels coupled to the stash partitions.3. The switch of claim 2 , the storage virtual channels coupling the input buffers to the stash partitions.4. The switch of claim 1 , further comprising logic to select packets from either the input buffers or from the stash partitions to rows of the switching fabric.5. The switch of claim 1 , further comprising one or more retrieval virtual channels.6. The switch of claim 5 , the retrieval virtual channel coupling the stash partitions to the output buffers.7. The switch of claim 1 , further comprising logic to implement one or more storage virtual channels and one or more retrieval virtual channels on each column of the switching fabric.8. The switch of claim 1 , further comprising logic to route packets to the stash partitions based on a join-shortest-queue algorithm.9. The switch of claim 1 , further comprising logic to route packets to the stash partitions based on a credit-based flow control algorithm.10. The switch of claim 1 , wherein the switch is a crossbar switch.11. The switch of claim 1 , wherein the switch is part of a dragonfly network.12. A crossbar switch comprising:a plurality of input ports and output ports; anda switching fabric coupling the input ports to the output ports; anda plurality of stash partitions in a packet recirculating data path interposed between the input ports and the output ports through the ...

LOW LEVEL PROVISIONING OF NETWORK FABRICS

A network fabric application coupled to a data link layer is provided with access to network elements in an optical fiber network. The network fabric application defines a network fabric configuration comprising at least a subset of the network elements, wherein the network fabric forms a multi-path communication network among the subset. The network fabric is configured to transmit data among networked devices in the network fabric along the multi-path communication network. 1. A method of provisioning a network fabric , comprising:providing, to a first application that couples with a data link layer, access to network elements that are connected via network connections;defining, by the first application, a network fabric configuration of at least a subset of the network elements;provisioning, by the first application, at the data link layer the subset of network elements according to the network fabric configuration to operate as a network fabric, where the network fabric forms a first multi-path communication network among networked devices; andconfiguring the network fabric to transmit data among the networked devices within the network fabric along the first multi-path communication network.2. The method recited in claim 1 , wherein each of the network connections comprises at least one physical fiber optic cable.3. The method recited in claim 2 , wherein each network connection comprises a matrix of physical channels within the at least one physical fiber optic cable.4. The method recited in claim 3 , wherein the matrix of physical channels comprises a wavelength dimension and a time dimension.5. The method recited in claim 4 , wherein the matrix of physical channels comprises at least 88 physical channels at each time slice claim 4 , wherein each of the 88 channels has a distinct optical wavelength.6. The method recited in claim 5 , wherein each of the at least 88 physical channel has a bandwidth of 100 Gb.7. The method recited in claim 3 , wherein the at ...

VIDEO ROUTER

The embodiments described herein provide a data transmission system comprising a plurality of video routers, a supervisory system for transmitting one or more router configuration signals to one or more video routers, and a control communication network for coupling the plurality of video routers and the supervisory system. Each router in the system comprises a backplane including a plurality of backplane connections, at least one line card and at least one fabric card. Each line card comprises a plurality of input ports and output ports where each input and output port is coupled to a respective external signal through the backplane. Each line card further comprises a line card cross-point switch having a plurality of input switch terminals and a plurality of output switch terminals. Each fabric card comprises a fabric card cross-point switch having a plurality of input switch terminal and a plurality of output switch terminals. Furthermore, each line card and each fabric card comprises a card controller where the card controller selectively couples one or more input switch terminals of a cross-point switch to the output switch terminals of that cross-point switch. The cross-point switches being manipulated by the card controller may belong to one or more different cards within the same video router. 1. A priority based transmission system comprising:a plurality of data signals;a plurality of video routers;a supervisory system configured to transmit one or more router configuration signals to one or more video routers, the one or more router configuration signals comprising a data signal path;a controller communication network for coupling the plurality of video routers and the supervisory system;wherein, each video router comprises:a backplane including a plurality of backplane connections, a plurality of input ports and output ports, each input port and output port being coupled to a respective data signal through the backplane, and', 'a line card cross-point ...

Network Interface Device

Roughly described: a network interface device has an interface. The interface is coupled to first network interface device circuitry, host interface circuitry and host offload circuitry. The host interface circuitry is configured to interface to a host device and has a scheduler configured to schedule providing and/or receiving of data to/from the host device. The interface is configured to allow at least one of: data to be provided to said host interface circuitry from at least one of said first network device interface circuitry and said host offload circuitry; and data to be provided from said host interface circuitry to at least one of said first network interface device circuitry and said host offload circuitry. 1. A network interface device comprising:an interface comprising a plurality of input ports and a plurality of output ports;first network interface device circuitry having at least one input port and at least one port configured to be coupled to respective ports of the interface;host interface circuitry configured to interface to a host device, said host interface circuitry having at least one input port and at least one output port configured to be coupled to respective ports of the interface, said host interface circuitry comprising a scheduler configured to schedule at least one of the providing of data to the host device and the receiving of data from the host; andhost offload circuitry configured to perform an offload operation for the host device, said host offload circuitry having at least one input port and at least one output port configured to be coupled to respective ports of the interface,wherein said interface is configured to allow at least one of:data to be provided to said host interface circuitry from at least one of said first network device interface circuitry and said host offload circuitry; anddata to be provided from said host interface circuitry to at least one of said first network interface device circuitry and said host offload ...

MULTICAST PACKET ROUTING VIA CROSSBAR BYPASS PATHS

An approach is described for routing data to a plurality of output terminals via a integrated switch router including a crossbar switch having both a crossbar and a plurality of crossbar bypass lines. Whereas the crossbar may connect each input of the crossbar switch to each output of the crossbar switch, each of the plurality of crossbar bypass lines may connect a single input of the crossbar switch to a corresponding single output of the crossbar switch. According to such approach, a replicated copy of a multicast packet may be forwarded to an output terminal via a crossbar bypass line in parallel with other data forwarded via the crossbar, thus increasing integrated switch router bandwidth. 1. An integrated switch router apparatus comprising:a broadcast network;a crossbar switch including a crossbar and a plurality of crossbar bypass lines;a plurality of multicast replication buffers communicatively connected to the broadcast network, wherein each of the plurality of multicast replication buffers respectively corresponds to one of the plurality of crossbar bypass lines;a broadcast arbiter configured to receive a multicast packet from an input terminal, to forward a payload of the multicast packet through the broadcast network, and to forward each header of the multicast packet through the broadcast network; anda crossbar arbiter configured to forward replicated copies of the multicast packet through the crossbar switch to a plurality of output terminals.2. The integrated switch router apparatus of claim 1 , wherein the broadcast arbiter is configured to forward the payload of the multicast packet through the broadcast network by facilitating a broadcast of the payload to a payload queue of each of the plurality of multicast replication buffers.3. The integrated switch router apparatus of claim 1 , wherein the broadcast arbiter is configured to forward each header of the multicast packet through the broadcast network by performing the following steps: upon ...

MULTICAST PACKET ROUTING VIA CROSSBAR BYPASS PATHS

An approach is described for routing data to a plurality of output terminals via a integrated switch router including a crossbar switch having both a crossbar and a plurality of crossbar bypass lines. Whereas the crossbar may connect each input of the crossbar switch to each output of the crossbar switch, each of the plurality of crossbar bypass lines may connect a single input of the crossbar switch to a corresponding single output of the crossbar switch. According to such approach, a replicated copy of a multicast packet may be forwarded to an output terminal via a crossbar bypass line in parallel with other data forwarded via the crossbar, thus increasing integrated switch router bandwidth. 1. A method of routing data to a plurality of output terminals via an integrated switch router , wherein the integrated switch router comprises a broadcast network , a crossbar switch having a crossbar and a plurality of crossbar bypass lines , and a plurality of multicast replication buffers communicatively connected to the broadcast network , wherein each of the plurality of multicast replication buffers respectively corresponds to one of the plurality of crossbar bypass lines , and wherein the method comprises:receiving a multicast packet from an input terminal;forwarding a payload of the multicast packet through the broadcast network;forwarding each header of the multicast packet through the broadcast network; andforwarding, by operation of one or more processors, replicated copies of the multicast packet through the crossbar switch to the plurality of output terminals.2. The method of claim 1 , wherein forwarding the payload of the multicast packet through the broadcast network comprises facilitating a broadcast of the payload to a payload queue of each of the plurality of multicast replication buffers.3. The method of claim 1 , wherein forwarding each header of the multicast packet through the broadcast network comprises: upon determining that a header queue of a ...

METHOD AND SYSTEM FOR SERIALIZATION AND DESERIALIZATION (SERDES) FOR INTER-SYSTEM COMMUNICATIONS

An integrated circuit may comprise a tuner operable to digitize a band of frequencies comprising a plurality of television channels, a crossbar operable to select one or more of the plurality of television channels output by the tuner, a plurality of demodulators operable to receive the selected one or more television channels from the crossbar and demodulate the selected one or more television channels to recover a plurality of transport streams, a transport module operable to multiplex the plurality of transport streams into a single packet stream, and a framer operable to: encapsulate packets of the plurality of transport streams into transport stream frames of a serial datastream, and insert filler frames into the serial datastream after every Nth transport stream frame of the serial datastream, where N is an integer. 120-. (canceled)21. A system comprising:a wideband tuner, a narrowband tuner, a crossbar, a plurality of demodulators, and a serializer, wherein: select a plurality of channels of one or more signals output by the wideband tuner and/or the narrowband tuner;', 'output the selected plurality of channels to the plurality of demodulators;, 'the crossbar is operable tothe plurality of demodulators are operable to demodulate the selected plurality of channels to generate a plurality of demodulated signals; generate, from the plurality of demodulated signals, a serial stream of frames for transmission onto a communication medium, wherein one or more of the frames are filler frames; and', 'determine when to insert the filler frames in the serial stream of frames based on a parameter value stored in memory., 'the serializer is operable to22. The system of claim 21 , wherein the serializer is operable to set the parameter value based on a timing mismatch between a first oscillator residing in the serializer and a second oscillator residing in a deserializer that receives the serial stream of frames via the communication medium.23. The system of claim 21 , ...

COMMUNICATING CONTROL PLANE DATA AND CONFIGURATION DATA FOR NETWORK DEVICES WITH MULTIPLE SWITCH CARDS

In some implementations, a switch card is provided. The switch card includes a set of switch chips configured to communicate data with a plurality of line cards. The plurality of line cards is coupled to a second switch card. The second switch card comprises a second set of switch chips. The switch card also includes a communication component coupled to the set of switch chips. The communication component is configured to determine whether the switch card should operate in a master mode or a slave mode. In response to determining that the switch card should operate in the master mode, the switch card is also configured to receive control plane data from a supervisor card. The switch card is further configured to communicate the control plane data to one or more switch chips of the set of switch chips and the second set of switch chips. 1. A switch card , comprising: the plurality of line cards is coupled to a second switch card; and', 'the second switch card comprises a second set of switch chips; and, 'a set of switch chips configured to communicate data with a plurality of line cards, wherein determine whether the switch card should operate in a master mode or a slave mode;', 'in response to determining that the switch card should operate in the master mode, receive control plane data from a supervisor card; and', 'communicate the control plane data to one or more switch chips of the set of switch chips and the second set of switch chips., 'a communication component coupled to the set of switch chips, the communication component configured to2. The switch card of claim 1 , wherein the communication component is further configured to:determine whether the control plane data is for a first switch chip of the set of switch chips or a second switch chip of the second set of switch chips.3. The switch card of claim 2 , wherein to communicate the control plane data the communication component is further configured to:forward the control plane data to the first switch ...

SYSTEM AND METHOD FOR AUTOMATIC TRANSPORT CONNECTION OF A NETWORK ELEMENT

Systems and methods are provided for configuring a Network Element (NE) to transport data within a network. A system configured accordingly may include a Transport Automation Tool (TAT) which can initiate, at a server on a network, a communication channel with a NE on the network. The TAT can determine or receive a network plan providing information about a circuit to be initiated or decommissioned on the network. The network plan may include a first port on the NE which is to be connected via a cross-connect (or disconnected) to a second port on the NE. The TAT can then establish or remove, using the communication channel, the cross-connect on the NE such that the NE is added to or removed from a circuit design utilizing the NE as a transport NE within the circuit. 1. A method comprising:retrieving a circuit design of a telecommunications network from an Inventory Service (IS) database;decomposing the circuit design to obtain an identification of a network element of the telecommunications network included in the circuit design;requesting operational information from the network element;storing the operational information in a localized database, wherein the operational information from the network element comprises an operational configuration and operational state of a plurality of communication ports of the network element; andestablishing a cross-connect on the network element between a first port and a second port of the plurality of communication ports based on the circuit design.2. The method of wherein the operational state of the plurality of communication ports indicates the interconnectivity of the plurality of communication ports.3. The method of further comprising transmitting a successful connection indicator to a network administrator if the plurality of communication ports are connected as described in the circuit design.4. The method of further comprising transmitting a failed connection indicator to a network administrator if the plurality of ...

METHOD AND SYSTEM FOR AN ANALOG CROSSBAR ARCHITECTURE

Methods and systems for an analog crossbar may comprise, in a wireless device comprising a receiver path with an analog crossbar: receiving a digital signal comprising a plurality of channels; amplifying the received signal; converting the amplified signal to an analog signal; separating the analog signal into a plurality of separate channels; routing the plurality of separate channels to desired signal paths utilizing the analog crossbar; and converting the routed plurality of separate channels to a plurality of digital signals. The analog crossbar may comprise an array of complementary metal-oxide semiconductor (CMOS) transistors. The analog crossbar may comprise a plurality of differential pair signal lines, and a plurality of single-ended signal lines. The received signal may be amplified utilizing a low-noise amplifier (LNA), where a gain level of the LNA may be configurable. The analog signal may be separated into separate channels using a channelizer. 1. A method for communication , the method comprising: receiving a digital signal comprising a plurality of channels;', 'amplifying the received signal;', 'converting the amplified signal to an analog signal utilizing an analog-to-digital converter (ADC);', 'separating the analog signal into a plurality of separate channels;', 'routing the plurality of separate channels to desired signal paths utilizing the analog crossbar; and', 'converting the routed plurality of separate channels to a plurality of digital signals utilizing analog-to-digital converters (DACs)., 'in a wireless device comprising a receiver path with an analog crossbar2. The method according to claim 1 , wherein the analog crossbar comprises an array of complementary metal-oxide semiconductor (CMOS) transistors.3. The method according to claim 1 , wherein the analog crossbar comprises a plurality of differential pair signal lines.4. The method according to claim 1 , wherein the analog crossbar comprises a plurality of single-ended signal lines.5. ...

Computing system with hardware reconfiguration mechanism and method of operation thereof

A method of operation of a computing system includes: providing a first cluster having a first kernel unit for managing a first reconfigurable hardware device; analyzing an application descriptor associated with an application; generating a first bitstream based on the application descriptor for loading the first reconfigurable hardware device, the first bitstream for implementing at least a first portion of the application; and implementing a first fragment with the first bitstream in the first cluster.

WIRELESS CROSS-CONNECT SWITCH

Wireless packet switches and enclosures include multiple port controllers, each in communication with a respective wireless transceiver located on an outer surface of a spherical shell. Each port controller is configured to analyze data streams to and from the respective wireless transceiver. Each wireless transceiver is configured to establish beamforming connections with a client device in a beamforming direction pointed away from the spherical shell. A cross-connect switch is in communication with all of the port controllers, configured to provide connections between respective port controllers. An arbiter is in communication with all of the port controllers and with the cross-connect switch and is configured to control the cross-connect switch, such that the cross-connect switch connects data streams of the port controllers in accordance with packet destination information and scheduling information from the port controllers. 1. A wireless packet switch , comprising:a plurality of port controllers, each in communication with a respective wireless transceiver located on an outer surface of a spherical shell, configured to analyze data streams to and from the respective wireless transceiver, wherein each wireless transceiver is configured to establish beamforming connections with a client device in a beamforming direction pointed away from the spherical shell;a cross-connect switch in communication with all of the port controllers, configured to provide connections between respective port controllers; andan arbiter, in communication with all of the port controllers and with the cross-connect switch, configured to control the cross-connect switch, such that the cross-connect switch connects data streams of the port controllers in accordance with packet destination information and scheduling information from the port controllers.2. The wireless packet switch of claim 1 , wherein the wireless transceivers comprise conformal antennas.3. An enclosure comprising:a ...

METHODS TO STRENGTHEN CYBER-SECURITY AND PRIVACY IN A DETERMINISTIC INTERNET OF THINGS

Methods to strengthen the cyber-security and privacy in a proposed deterministic Internet of Things (IoT) network are described. The proposed deterministic IoT consists of a network of simple deterministic packet switches under the control of a low-complexity ‘Software Defined Networking’ (SDN) control-plane. The network can transport ‘Deterministic Traffic Flows’ (DTFs), where each DTF has a source node, a destination node, a fixed path through the network, and a deterministic or guaranteed rate of transmission. The SDN control-plane can configure millions of distinct interference-free ‘Deterministic Virtual Networks’ (DVNs) into the IoT, where each DVN is a collection of interference-free DTFs. The SDN control-plane can configure each deterministic packet switch to store several deterministic periodic schedules, defined for a scheduling-frame which comprises F time-slots. The schedules of a network determine which DTFs are authorized to transmit data over each fiber-optic link of the network. These schedules also ensure that each DTF will receive a deterministic rate of transmission through every switch it traverses, with full immunity to congestion, interference and Denial-of-Service (DoS) attacks. Any unauthorized transmissions by a cyber-attacker can also be detected quickly, since the schedules also identify unauthorized transmissions. Each source node and destination node of a DTF, and optionally each switch in the network, can have a low-complexity private-key encryption/decryption unit. The SDN control-plane can configure the source and destination nodes of a DTF, and optionally the switches in the network, to encrypt and decrypt the packets of a DTF using these low-complexity encryption/decryption units. To strengthen security and privacy and to lower the energy use, the private keys can be very large, for example several thousands of bits. The SDN control-plane can configure each DTF to achieve a desired level of security well beyond what is possible with ...

SELECTIVE UNDERFLOW PROTECTION IN A NETWORK SWITCH

Techniques are disclosed to transmit packets by a network switch and according to a link protocol while reducing incidence of intra-packet transmission gaps unsupported by the link protocol. Whether a packet satisfies an underflow risk condition is determined by evaluating, for each of one or more cycles since receipt of one or more flits of the packet, a respective count of flits of the packet received by the network switch in the respective cycle. Only upon determining that the packet satisfies the underflow risk condition is selective underflow protection performed for the packet, including buffering an increased count of flits of the packet, prior to commencing transmission of the packet. 1. A computer-implemented method to transmit packets by a network switch and according to a link protocol while reducing incidence of intra-packet transmission gaps unsupported by the link protocol , the computer-implemented method comprising:determining whether an incoming packet satisfies the underflow risk condition, by evaluating, for each of one or more cycles since receipt of one or more flow control digits (flits) of the second packet, a respective count of flits of the incoming packet received by the network switch in the respective cycle; andupon determining that the incoming packet satisfies the underflow risk condition, providing selective underflow protection for the incoming packet by buffering at least an increased count of flits of the incoming packet, prior to commencing transmission of the incoming packet and by operation of one or more computer processors, in order to prevent a transmission gap from occurring due to a buffer underrun when subsequently transmitting the incoming packet.2. The computer-implemented method of claim 1 , further comprising:upon determining that the incoming packet does not satisfy the underflow risk condition, refraining from selective underflow protection for the incoming packet, by buffering no more than a reduced count, relative ...

INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND RECORDING MEDIA

An information processing device according to the present invention includes: a crossbar switch which arbitrates a plurality of input data, and outputs the arbitrated input data to either one of a plurality of output destinations; an output port control unit which receives output data from the crossbar switch as the output destination of the crossbar switch, and transmits the received output data to an external device; a first input port control unit which receives data with a lower bandwidth than a bandwidth of the crossbar switch, and outputs the received data with the same bandwidth as the bandwidth of the crossbar switch to the crossbar switch; and a second input port control unit which receives data with the same bandwidth as the bandwidth of the crossbar switch, and outputs the received data to the crossbar switch without changing the bandwidth of the received data. 1. An information processing device , comprising:a crossbar switch which arbitrates a plurality of input data, and outputs the arbitrated input data to either one of a plurality of output destinations;an output port control unit which receives output data from the crossbar switch as the output destination of the crossbar switch, and transmits the received output data to an external device;a first input port control unit which receives data with a lower bandwidth than a bandwidth of the crossbar switch, and outputs the received data with the same bandwidth as the bandwidth of the crossbar switch to the crossbar switch; anda second input port control unit which receives data with the same bandwidth as the bandwidth of the crossbar switch, and outputs the received data to the crossbar switch without changing the bandwidth of the received data.2. The information processing device according to claim 1 , whereinthe first input port control unit comprising:a first receiving buffer unit which receives and temporarily retains data;a first data output unit which receives and retains first half data which is ...

Full Channel-Swap Crossbar

A programmable channel-swap crossbar switch for swapping signal flow from one channel to another within an Ethernet physical layer device (PHY) is presented. The crossbar switch includes two or more programmed multiplexers, each multiplexer configured to receive two or more input signals and to select which one of the input signals to pass to a programmed corresponding channel, such that a first, input signal associated with a first channel can be swapped to a second channel as operating conditions necessitate. The crossbar switch can be used for Ethernet communications with various communication speeds, such as 10BaseT, 100BaseT, and Gigabit communications. A crossbar switch can be used in both a transmit path and a receive path. Two crossbar switches may be used in a receive path in order to undo channel swapping for control signal processing. A method of channel-swapping in an Ethernet PHY communications system is also presented. 1. A channel-swap crossbar switch , comprising:a control mechanism configured to effect a mapping of a virtual channel to an actual channel;a first multiplexer configured to select a signal received at a virtual channel port based on the mapping; anda second multiplexer configured to designate an actual channel on which to transmit the received signal based on the mapping.2. The channel-swap crossbar switch of claim 1 , wherein the control mechanism comprises chip inputs.3. The channel-swap crossbar switch of claim 1 , wherein the control mechanism comprises a register.4. The channel-swap crossbar switch of claim 3 , wherein the mapping comprises one or more bits stored in the register.5. The channel-swap crossbar switch of claim 1 , further comprising logic configured to detect when an overmapping has occurred.6. The channel-swap crossbar switch of claim 5 , wherein the logic is further configured to prioritize the channel mapping when the overmapping is detected.7. The channel-swap crossbar switch of claim 1 , wherein the signal ...

VIDEO ROUTER

The embodiments described herein provide a data transmission system comprising a plurality of video routers, a supervisory system for transmitting one or more router configuration signals to one or more video routers, and a control communication network for coupling the plurality of video routers and the supervisory system. Each router in the system comprises a backplane including a plurality of backplane connections, at least one line card and at least one fabric card. Each line card comprises a plurality of input ports and output ports where each input and output port is coupled to a respective external signal through the backplane. Each line card further comprises a line card cross-point switch having a plurality of input switch terminals and a plurality of output switch terminals. Each fabric card comprises a fabric card cross-point switch having a plurality of input switch terminal and a plurality of output switch terminals. Furthermore, each line card and each fabric card comprises a card controller where the card controller selectively couples one or more input switch terminals of a cross-point switch to the output switch terminals of that cross-point switch. The cross-point switches being manipulated by the card controller may belong to one or more different cards within the same video router. 120.-. (canceled)21. A video router comprising:a backplane including a plurality of backplane connections; a plurality of input ports and output ports, each input port and output port is coupled to a respective data signal through the backplane.', 'a line card cross-point switch having a plurality of input switch terminals and a plurality of output switch terminals, wherein a first plurality of input and output switch terminals are coupled to a respective plurality of input and output ports and a second plurality of input and output switch terminals are coupled to the plurality of backplane connections;', 'a line card controller coupled to the line card cross-point ...

SYSTEM FOR PROCESSING MESSAGES OF DATA STREAM

A system for processing messages of a high rate data stream and an apparatus including: a message processor including a plurality of processor sub-modules and configured to read an input data stream, process the input data stream, and to output an output data stream; at least one payload memory storing data related to the input data stream and accessible to the message processor; at least one instruction memory accessible to the message processor and storing computer program instructions configuring the message processor to process the input data stream; and an application processor configured to rewrite the at least one instruction memory. 1. An apparatus comprising:a message processor comprising a plurality of processor sub-modules in an array form, the message processor being configured to read an input data stream, process the input data stream, and to output an output data stream;at least one payload memory configured to store data related to the input data stream, the at least one payload memory being accessible to the message processor; andat least one instruction memory accessible to the message processor, wherein the at least one instruction memory stores computer program instructions executable by the message processor to process the input data stream,wherein a processing path through a subset of processor sub-modules of the plurality of processor sub-modules of the array is selectable by arrangement of the processor sub-modules of the subset in a serial form,wherein each processor sub-module of the subset of processor sub-modules includes a dedicated memory area in the at least one instruction memory and is configured to perform a dedicated task in the processing of the input data stream, andwherein a memory area of the at least one instruction memory that is dedicated to a first processor sub-module of the subset of processor sub-modules is rewriteable while a second processor sub-module of the subset of processor sub-modules is processing the input data ...

Messaging between remote controller and forwarding element

Some embodiments of the invention provide a forwarding element that can be configured through in-band data-plane messages from a remote controller that is a physically separate machine from the forwarding element. The forwarding element of some embodiments has data plane circuits that include several configurable message-processing stages, several storage queues, and a data-plane configurator. A set of one or more message-processing stages of the data plane are configured (1) to process configuration messages received by the data plane from the remote controller and (2) to store the configuration messages in a set of one or more storage queues. The data-plane configurator receives the configuration messages stored in the set of storage queues and configures one or more of the configurable message-processing stages based on configuration data in the configuration messages.

Data Processing Apparatus and Terminal

A data processing apparatus includes N apparatus input ends, an input switch, K cache areas, a first output switch, a second output switch, and M apparatus output ends. N input ends of the input switch are coupled to the N apparatus input ends, and K output ends of the input switch correspond to the K cache areas. Kinput ends of the first output switch correspond to Kcache areas in the K cache areas, and M output ends of the first output switch are coupled to the M apparatus output ends. Kinput ends of the second output switch correspond to Kcache areas in the K cache areas except the Kcache areas, and M output ends of the second output switch are coupled to the M apparatus output ends. 1. A data processing apparatus , comprising:N apparatus input ends;an input switch;K cache areas;a first output switch;a second output switch; andM apparatus output ends,wherein both N and M are integers greater than one,wherein N input ends of the input switch are coupled to the N apparatus input ends in a one to one manner;wherein K output ends of the input switch respectively correspond to the K cache areas,{'sub': 1', '1, 'wherein Kinput ends of the first output switch respectively correspond to Kcache areas in the K cache areas,'}wherein M output ends of the first output switch are coupled to the M apparatus output ends in the one to one manner,{'sub': '1', 'wherein Kis greater than or equal to one,'}{'sub': 2', '2', '1, 'wherein Kinput ends of the second output switch respectively correspond to Kcache areas in the K cache areas except the Kcache areas,'}wherein M output ends of the second output switch are coupled to the M apparatus output ends in the one to one manner,{'sub': '2', 'wherein Kis greater than or equal to one, and'}{'sub': 1', '2, 'wherein the Kcache areas are different from the Kcache areas.'}2. The data processing apparatus according to claim 1 , wherein the input switch is configured to obtain data from the N apparatus input ends claim 1 , wherein the data ...

Pipelined Configurable Processor

A configurable processing circuit capable of handling multiple threads simultaneously, the circuit comprising a thread data store, a plurality of configurable execution units, a configurable routing network for connecting locations in the thread data store to the execution units, a configuration data store for storing configuration instances that each define a configuration of the routing network and a configuration of one or more of the plurality of execution units, and a pipeline formed from the execution units, the routing network and the thread data store that comprises a plurality of pipeline sections configured such that each thread propagates from one pipeline section to the next at each clock cycle, the circuit being configured to: (i) associate each thread with a configuration instance; and (ii) configure each of the plurality of pipeline sections for each clock cycle to be in accordance with the configuration instance associated with the respective thread that will propagate through that pipeline section during the clock cycle.