КОММУТАЦИОННАЯ СИСТЕМА ДЛЯ ВЫПОЛНЕНИЯ АСИНХРОННОГО РЕЖИМА ПЕРЕДАЧИ И СПОСОБ КОММУТАЦИИ ЯЧЕЕК В НЕЙ

FIELD: computer engineering. SUBSTANCE: system has input buffer, input switching circuit that functions as retrieval and adding means, copy switching circuit that also functions as retrieval and adding means, feedback switching circuit that functions to receive cells sent back and to save them till next cell cycle, routing table used for data storage to convert them and replace data for cell routing, routing and feedback controller that functions to route and control input cells and those sent back according to routing table, routing switching circuits, cell separator that functions to separate cells into those routed and cells brought to routing circuits and to transmit them to routing switching circuits, and cell combiner used to combine cells and to bring separated ones from output ports of routing switching circuits. EFFECT: provision for complex data representation in asynchronous switching mode. 5 cl, 39 dwg, 1 tbl

Vermittlungsvorrichtung mit wenigstens einem Vermittlungskern-Zugriffselement zur Verbindung von verschiedenen Protokolladaptern

Vermittlungsvorrichtung mit wenigstens einem Vermittlungskern-Zugriffselement zur Verbindung von verschiedenen Protokolladaptern

Apparatus and method for switching data packets

A method and apparatus (1) is disclosed for switching data packets. A data packet is received from an input interface device (7) at one of a plurality of initial input pods (6). The data packet is divided into plural smaller data fragments. Each data fragment is passed to a respective one of a plurality of slices of an input port (3) of a core switch (2). The data fragments are switched using the core switch (2) so as to pass each data fragment to a selected respective one of a plurality of slices of an output port (3') of the core switch (2). The data fragments are then passed to a selected one of a plurality of ultimate output ports (5'). The data fragments are assembled to reform the data packet, and the reformed data packet is transmitted to an output interface device (7') connected to said selected one of a plurality of ultimate output ports (5').

SYSTEM AND METHOD FOR SWITCHING PACKETS IN A NETWORK

A switching node for transferring packets, each including a destination address, in a network includes a plurality of input port modules, a plurality of output port modules and a switching fabric, including a packet meta-data processor and a packet switch. Each input port module is connected to a communication link for receiving packets thereover, and each output port module is connected to a communication link for transmitting packets thereover. Each input port module, upon receiving a packet, buffers the packet and generates a meta-data packet therefore identifying the output port module that is to transmit the packet and packet identifier information, and provides it to the packet meta-data processor. The packet meta-data processor receives the meta-data packets generated by all of the input port modules and operational status information from all of the output port modules and for each output port module, processes the meta-data packets received from all of the input port modules in connection with the operational status information to determine whether the packet should be passed or dropped. If the packet meta-data processor determines that a packet associated with a meta-data packet is to be dropped, it will notify the input port module in which the packet is buffered, which, in turn, will discard the packet. On the other hand if the packet meta-data processor determines that the packet associated with the meta-data packet is not to be dropped, it will enqueue the meta-data packet for the associated output port module. Each output port module retrieves meta-data packets from its respective meta-data packet queue maintained therefor by the packet meta-data processor. For each meta-data packet retrieved by an ouput port module, the output port module will request that the input port module identified in the meta-data packet transfer the packet identified in the input port module thereto through the packet switch. When the output port module receives the packet, ...

ATM SWITCH AND CONTROL METHOD THEREOF

An ATN switch including ECC encoder circuits each for generating, for an ATM cell as an information symbol, an ECC check symbol and for adding the ECC check symbol thereto, cell partitioning circuits each for subdividing an information field of an ATM cell into N partial cells, for subdividing a check symbol field into M partial cells, and for assigning an identical routing tag to the obtained partial cells (N + M) partial cell switches for respectively routing the (N + M) partial cells in an independent fashion based on the routing tag, and ECC decoder circuits for receiving the (N + M) partial cells thus routed and for achieving an error correction on the received partial cells.

Method and structure for variable-length frame support in a shared memory switch

Pass/drop apparatus and method for network switching node

A switching node for transferring packets, each including a destination address, in a network includes a plurality of input port modules, a plurality of output port modules and a switching fabric, including a packet meta-data processor and a packet switch. Each input port module is connected to a communication link for receiving packets thereover, and each output port module is connected to a communication link for transmitting packets thereover. Each input port module, upon receiving a packet, buffers the packet and generates a meta-data packet therefor identifying the output port module that is to transmit the packet and packet identifier information, and provides it to the packet meta-data processor. The packet meta-data processor receives the meta-data packets generated by all of the input port modules and operational status information from all of the output port modules and for each output port module, processes the meta-data packets received from all of the input port modules in connection with the operational status information to determine whether the packet should be passed or dropped. If the packet meta-data processor determines that a packet associated with a meta-data packet is to be dropped, it will notify the input port module in which the packet is buffered, which, in turn, will discard the packet. On the other hand if the packet meta-data processor determines that the packet associated with the meta-data packet is not to be dropped, it will enqueue the meta-data packet for the associated output port module. Each output port module retrieves meta-data packets from its respective meta-data packet queue maintained therefor by the packet meta-data processor. For each meta-data packet retrieved by an output port module, the output port module will request that the input port module identified in the meta-data packet transfer the packet identified in the input port module thereto through the packet switch. When the output port module receives the packet, ...

Virtual junctors

The present invention guarantees that voice data (and other information types) will switch within a predetermined time period. Systems and methods consistent with the present invention accomplish this guarantee by, among other things, establishing permanent virtual paths or circuits between each network element, guaranteeing each voice line a slot in a packet in each frame, employing both octet switching and packet switching, synchronizing the operation of the network elements to a reference clock, and providing several levels of network redundancy.

DATA ELEMENT SWITCH

Asynchronous Transfer Mode Switch Architecture

DATA ELEMENT SWITCH

DATA ELEMENT SWITCH The invention concerns an Asynchronous Transfer Mode Switch having a plurality of input stages (ISl ... ISN) each for receiving a digital data transmission stream (DSl ...256) consisting of a series of cells and wherein each input stage of the switch includes a circuit (52) for determining the destination of the cells of that data stream, and a circuit (63) for disassembling each cell into cell elements and for allocating to each cell element routing data to enable it to be routed across the central stages.

PROCEDURE AND STRUCTURE FOR THE SUPPORT OF FRAMEWORKS OF VARIABLE LENGTH IN A SWITCHING PLANT WITH GEMEISAMEM MEMORY

SYNCHRONOUS DYNAMIC ACTUALIZATION OF A REGISTER OVER A DISTRIBUTED SYSTEM

ASYNCHRONOUS TRANSFER MODE SWITCH ARCHITECTURE

A high capacity packet switch is implemented using an expansion module that divides an incoming packet cell into a plurality of segments and supplies the segments, based on their sequential order, to respective ones of a plurality of concentrator units contained in the expansion module. Each concentrator unit includes a plurality of concentrator logic units and one of those logic units accepts a segment for storage based on routing information contained in the packet cell. The stored segments forming a packet cell are thereafter unloaded and recombined in proper sequence for routing to a packet switch module, which then forwards the packet cell toward its destination.

HIGH-PERFORMANCE NETWORK SWITCH

A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.

Backplane Interface Adapter

A backplane interface adapter for a network switch. The backplane interface adapter includes at least one receiver that receives input cells carrying packets of data; at least one cell generator that generates encoded cells which include the packets of data from the input cells; and at least one transmitter that transmits the generated cells to a switching fabric. The cell includes a destination slot identifier that identifies a slot of the switching fabric towards which the respective input cell is being sent. The generated cells include in-band control information.

УСТРОЙСТВО И СПОСОБ КОММУТАЦИИ ПАКЕТОВ ДАННЫХ В СЕТИ (ВАРИАНТЫ)

Data element switch

Ampic dram system in a telecommunication switch

AMPIC DRAM SYSTEM IN A TELECOMMUNICATION SWITCH

A technique and system for eliminating bus contention in multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, while eliminating the need for external control paths and random memory addressing, through the use of data header destination bits and a novel dedication of reduced size slot buffers to separate DRAM banks and similarly dedicated I/O data read resource ports, particularly useful for relatively short ATM message networking and the like, wherein all system I/O resources are enabled simultaneously to write complete ATM messages into a single slot buffer, and also for SONET Cross Connect and WDM messages.

SWITCHING SYSTEM WITH TIME-STAMPED PACKET DISTRIBUTION INPUT STAGE AND PACKET SEQUENCING OUTPUT STAGE

In a fast packet switching system, packet distributers are associated respectively with input ports for receiving successive packets therefrom and attaching a timeslot number to each of the received packets, and uniformly distributing the packets to output terminals of each distributer. Packet switches are provided corresponding in number to the output terminals of each packet distributer. Each packet switch has input terminals corresponding in number to the packet distributers and output terminals corresponding in number to the output ports. The input terminals of each packet switch are coupled to respective output terminals of the distributers for switching a packet from one of its input terminals to one of its output terminals in accordance with a destination address contained in the packet. Packet sequencers are associated respectively with the output ports. Each packet sequencer has input terminals coupled to respective output terminals of the packet switches for examining the timeslot ...

HIGH SPEED SWITCHING DEVICE

A router (20) for switching a data packet between a source (10) and destination (30) in a network including a plurality of input ports each including a data handler. The data handler divides a data packet into one or more fixed length cells. The router (20) includes a plurality of output port s at least one of which is for routing the data packet to the destination (30) and a memory divided into a plurality of memory banks. An input switch receives fixed length cells from the input ports and writes a single output switch routes cells received from the memory to an appropriate output port.< /SDOAB> ...

System and method for switching packets in a network

A switching node for transferring packets, each including a destination address, in a network includes a plurality of input port modules, a plurality of output port modules and a switching fabric, including a packet meta-data processor and a packet switch. Each input port module is connected to a communication link for receiving packets thereover, and each output port module is connected to a communication link for transmitting packets thereover. Each input port module, upon receiving a packet, buffers the packet and generates a meta-data packet therefor identifying the output port module that is to transmit the packet and packet identifier information, and provides it to the packet meta-data processor. The packet meta-data processor receives the meta-data packets generated by all of the input port modules and operational status information from all of the output port modules and for each output port module, processes the meta-data packets received from all of the input port modules in ...

Backplane interface adapter with error control and redundant fabric

A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.

SWITCHING DEVICE FOR ASYNCHRONOUS TRANSFER MODE EXCHANGE SYSTEM AND ITS METHOD

PROBLEM TO BE SOLVED: To efficiently use an input buffer by executing a take-out and addition function by an input switching network, transmitting input cells, storing them in the input buffer, referring to a routing table and controlling the routing of the cells by a routing network, a cell distributor and a cell merger. SOLUTION: An input network 12 uses a reverse banyan network and executes the take-out and addition function of the input cells and the function of storing the input cells in the input buffer 20. A routing and feedback control part 41 controls the routing of the inputted cells in a copy network 32 and a feedback network 52 by referring to the routing information of the routing table 42. The cell distributor 51 distributes the output cells of the copy network 32 and the feedback network 52 and the cell merger 64 stores and outputs the output cells of the routing networks 63a-63d to the respective output buffers of a port. Thus, by the more efficient operation of the buffer ...

DATA ELEMENT SWITCH

A routing arrangement

ATM SWITCH AND CONTROL METHOD THEREOF

An ATN switch including ECC encoder circuits each for generating, for an ATM cell as an information symbol, an ECC check symbol and for adding the ECC check symbol thereto, cell partitioning circuits each for subdividing an information field of an ATM cell into N partial cells, for subdividing a check symbol field into M partial cells, and for assigning an identical routing tag to the obtained partial cells (N + M) partial cell switches for respectively routing the (N + M) partial cells in an independent fashion based on the routing tag, and ECC decoder circuits for receiving the (N + M) partial cells thus routed and for achieving an error correction on the received partial cells.

ASYNCHRONOUS TRANSFER MODE (ATM) SWITCH FABRIC

In an asynchronous transfer mode (ATM) switching arrangement buffer memory capacity is effectively and efficiently increased by employing a pluralit y of circuit cards including a master circuit card and a plurality of so-called slave circuit cards including additional buffer memory and an internal cell format in which al l of the ATM cell routing information is supplied directly to the master circuit card . Then, the master circuit card utilizes the ATM cell routing information to contr ol writing and reading of data to and from its buffer memory locations and the buff er memory locations of each of the plurality of slave circuit cards. This control o f the plurality of slave circuit cards requires only unidirectional communications lin ks to pass the control information from the master circuit card to the slave circuit c ards.

SYSTEM AND METHOD FOR SWITCHING PACKETS IN A NETWORK

La présente invention concerne, dans un réseau, un noeud de commutation destiné à des transferts de paquets, chacun comprenant une adresse de destination. Ce noeud de commutation est constitué d'une pluralité de modules de voies d'entrée, de voies de sortie et un commutateur, qui comprennent un processeur de métadonnées de paquet et un commutateur de paquet. Chaque module de voie d'entrée est connecté à un lien de communication afin de recevoir des paquets en provenant, et chaque module de voie de sortie est connecté à un lien de communication afin d'y émettre des paquets. Chaque module de voie d'entrée, à la réception d'un paquet le met en file d'attente, et génère un paquet de métadonnées identifiant ainsi le module de voie de sortie qui doit émettre le paquet et une information identifiant le paquet, et les envoie au processeur de métadonnées de paquet. Le processeur de métadonnées de paquet reçoit les paquets de métadonnées générés par la totalité des modules de voie d'entrée ainsi ...

HIGH SPEED SWITCHING ARCHITECTURE

A high speed non-blocking buffered banyan packet switching architecture which utilizes parallel switching fabrics (16, 17, 18, 19) to switch slices of serial packets in parallel. A highly parallel interconnect network within each fabric allows for high speed effective data switching at relatively low clock speeds.

VIRTUAL JUNCTORS

The present invention guarantees that voice data (and other information types) will switch within a predetermined time period. Systems and methods consistent with the present invention accomplish this guarantee by, among other things, establishing permanent virtual paths or circuits between each network element, guaranteeing each voice line a slot in a packet in each frame, employing both octet switching and packet switching, synchronizing the operation of the network elements to a reference clock, and providing several levels of network redundancy.

A ROUTING ARRANGEMENT

A crossbar routing arrangement is disclosed for use in a digital system having three or more buses. An associated method is also disclosed. The routing arrangement is configured for transferring a set of data received from any particular one of the buses to any other selected one of the buses and includes a control arrangement associated with each bus for dividing the set of data into at least first and second subsets of data and for adding self- routing signals to each data subset which signals identify the selected bus. A switching arrangement is configured for directing the first and second data subsets in a predetermined way responsive to the self-routing signals. The control arrangement cooperates with the switching arrangement to transfer the data subsets over physically distinct data transfer paths defined between the switching arrangement and the control arrangements. In accordance with one feature, the configuration of the routing arrangement provides for linear expansion whereby ...

SWITCHING SYSTEM WITH TIME-STAMPED PACKET DISTRIBUTION INPUT STAGE AND PACKET SEQUENCING OUTPUT STAGE

Separation of data and control in a switching device

A method and apparatus for switching a data packet between a source and destination in a network. The data packet includes a header portion and a data portion. The header portion includes routing information for the data packet. The method includes defining a data path in the router comprising a path through the router along which the data portion of the data packet travels and defining a control path comprising a path through the router along which routing information from the header portion travels. The method includes separating the data path and control path in the router such that the routing information can be separated from the data portion allowing for the separate processing of each in the router. The data portion can be stored in a global memory while routing decisions are made on the routing information in the control path.

Switching system with time-stamped packet distribution input stage and packet sequencing output stage

In a fast packet switching system, packet distributors are associated respectively with input ports for receiving successive packets therefrom and attaching a timeslot number to each of the received packets, and uniformly distributing the packets to output terminals of each distributor. Packet switches are provided corresponding in number to the output terminals of each packet distributor. Each packet switch has input terminals corresponding in number to the packet distributors and output terminals corresponding in number to the output ports. The input terminals of each packet switch are coupled to respective output terminals of the distributors for switching a packet from one of its input terminals to one of its output terminals in accordance with a destination address contained in the packet. Packet sequencers are associated respectively with the output ports. Each packet sequencer has input terminals coupled to respective output terminals of the packet switches for examining the timeslot ...

Apparatus and method for switching data packets

Receiver decoding algorithm to allow hitless n+1 redundancy in a switch

HIGH SPEED SWITCHING ARCHITECTURE

A high speed non-blocking buffered banyan packet switching architecture which utilizes parallel switching fabrics (16, 17, 18, 19) to switch slices of serial packets in parallel. A highly parallel interconnect network within each fabric allows for high speed effective data switching at relatively low clock speeds.

HIGH SPEED VARIABLE LENGTH BEST MATCH LOOK-UP IN A SWITCHING DEVICE

A method and apparatus for looking up a key associated with a packet to determine a route through a routing device, the method including, upon receipt of a key, forward traversing one or more nodes which make up a trie stored in a memory by evaluating at each node traversed a bit in the key as indicated by a bit-to-test indicator associated with each node. A value of the bit in the key determining the path traversed along the trie. The method includes locating an end node having a route and comparing the route to the key (528). If they match, destination information associated with the end node is outputted to guide the transfer of the packet through the routing device (529). If they do not match, the trie is traversed backwards to locate a best match for the key.

Method and structure for variable-length frame support in a shared memory switch

The present invention relates to switching in electronic networks. Many data transmission protocols and technologies used in such networks, such as TCP/IP and Ethernet, use variable-length packets for transmission. Often however, the nodes that make up these networks typically contain high-speed cell switches that only support fixed-size data units. To support variable-length packets in such a fixed-size cell switch non-interleaving switching and transmission must be offered. The present invention provides such a solution in essence by segmenting a variable-length frame into a plurality of fixed-length cells including a start-of-frame cell, one or more continuation cell(s), and an end-of-frame cell and routes said fixed-length cells through said switch, thereby providing, at an output of said switch, subsequent and deadlock-free transmission of consecutive cells of a certain frame, and block any cell of a different frame from interleaving. This leads to better average delay characteristics ...

Backplane Interface Adapter

A backplane interface adapter for a network switch. The backplane interface adapter includes at least one receiver that receives input cells carrying packets of data; at least one cell generator that generates encoded cells which include the packets of data from the input cells; and at least one transmitter that transmits the generated cells to a switching fabric. The cell includes a destination slot identifier that identifies a slot of the switching fabric towards which the respective input cell is being sent. The generated cells include in-band control information.

Backplane Interface Adapter with Error Control and Redundant Fabric

A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.

HIGH SPEED VARIABLE LENGTH BEST MATCH LOOK-UP IN A SWITCHING DEVICE

A method and apparatus for looking up a key associated with a packet to determine a route through a routing device, the method including, upon receipt of a key, forward traversing one or more nodes which make up a trie stored in a memory by evaluating at each node traversed a bit in the key as indicated by a bit-to-test indicator associated with each node. A value of the bit in the key determining the path traversed along the trie. The method includes locating an end node having a route and comparing the route to the key (528). If they match, destination information associated with the end node is outputted to guide the transfer of the packet through the routing device (529). If they do not match, the trie is traversed backwards to locate a best match for the key.

High-performance network switch

MEMORY ORGANIZATION IN A SWITCHING DEVICE

A router (20) for switching data packets from a source (10) to a destination (30) in a network in which the router includes a distributed memory. The distributed memory includes two or more memory banks. Each memory bank is used for storing uniform portions of a data packet received from a source (10) and linking information for each data packets to allow for extraction of the uniform portions of a data packets from distributed locations in memory in proper order after a routing determination has been made by the router (20).

HIGH SPEED VARIABLE LENGTH BEST MATCH LOOK-UP IN A SWITCHINGDEVICE

A method and apparatus for looking up a key associated with a packet to determine a route through a routing device, the method including, upon recei pt of a key, forward traversing one or more nodes which make up a trie stored i n a memory by evaluating at each node traversed a bit in the key as indicated by a bit-to-test indicator associated with each node. A value of the bit in the key determining the path traversed along the trie. The method includes locating an end node having a route and comparing the route to the key (528) . If they match, destination information associated with the end node is outputted to guide the transfer of the packet through the routing device (529). If they do not match, the trie is traversed backwards to locate a bes t match for the key.

APPARATUS AND METHOD FOR SWITCHING DATA PACKETS

A method and apparatus (1) is disclosed for switching data packets. A data packet is received from an input interface device (7) at one of a plurality of initial input ports (6). The data packet is divided into plural smaller data fragments. Each data fragment is passed to a respective one of a plurality of slices of an input port (3) of a core switch (2). The data fragments are switched using the core switch (2) so as to pass each data fragment to a selected respective one of a plurality of slices of an output port (3') of the core switch (2). The data fragments are then passed to a selected one of a plurality of ultimate output ports (5'). The data fragments are assembled to reform the data packet, and the reformed data packet is transmitted to an output interface device (7') connected to said selected one of a plurality of ultimate output ports (5').

ATM-Vermittlungsschaltung

System and method for switching packets in a network

HIGH SPEED SWITCHING DEVICE

A router (20) for switching a data packet between a source (10) and destination (30) in a network including a plurality of input ports each including a data handler. The data handler divides a data packet into one or more fixed length cells. The router (20) includes a plurality of output ports at least one of which is for routing the data packet to the destination (30) and a memory divided into a plurality of memory banks. An input switch receives fixed length cells from the input ports and writes a single output switch routes cells received from the memory to an appropriate output port.

HIGH-PERFORMANCE NETWORK SWITCH

A backplane interface adapter (600) with error control and redundant fabric for a high-performance network switch (100). The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells (1300) carrying packets of data and output wide striped cells (1500) to a switching fabric.

ATM switch

MEMORY ORGANIZATION IN A SWITCHING DEVICE

A router (20) for switching data packets from a source (10) to a destination (30) in a network in which the router includes a distributed memory. The distributed memory includes two or more memory banks. Each memory bank is used for storing uniform portions of a data packet received from a source (10) and linking information for each data packets to allow for extraction of the uniform portions of a data packets from distributed locations in memory in proper order after a routing determination has been made by the router (20).

Asynchronous Transfer Mode (ATM) Switch Fabric

ATM SWITCH AND ITS CONTROL METHOD

PURPOSE: To configurate an ATM switch with a small hardware scale even when a switch capacity is large by dividing a cell into local cells so as to apply independent routing. CONSTITUTION: A 56-byte length ATM cell is inputted from 2.4Gb/s incoming highways 1-8 in a form of 40Mb/s×64-bit parallel × 7-lines. Cell division circuits 21-28 divide a cell of 40Mb/s×64-bit parallel × 7-lines for each 8-bit in parallel and give a same routing tag respectively to convert the cell into 8 local cells. Each local cell is fed to different local cell switch respectively. A local cell switch 30 receives a 0-th local cell from the cell division circuits 21-28 to execute the switching of the 0-th local cell. Since a same routing tag is provided to each local cell divided from one cell, each local cell switch makes similar switching operation. Thus, each local cell divided from one cell is simultaneously outputted to the 2.4Gb/s outgoing highway. COPYRIGHT: (C)1992,JPO&Japio ...

Backplane interface adapter

A backplane interface adapter for a network switch. The backplane interface adapter includes at least one receiver that receives input cells carrying packets of data; at least one cell generator that generates encoded cells which include the packets of data from the input cells; and at least one transmitter that transmits the generated cells to a switching fabric. The cell includes a destination slot identifier that identifies a slot of the switching fabric towards which the respective input cell is being sent. The generated cells include in-band control information.

Method and structure for variable-length frame support in a shared memory switch

The present invention relates to switching in electronic networks. Many data transmission protocols and technologies used in such networks, such as TCP/IP and Ethernet, use variable-length packets for transmission. Often however, the nodes that make up these networks typically contain high-speed cell switches that only support fixed-size data units. To support variable-length packets in such a fixed-size cell switch non-interleaving switching and transmission must be offered. The present invention provides such a solution in essence by segmenting a variable-length frame into a plurality of fixed-length cells including a start-of-frame cell, one or more continuation cell(s), and an end-of-frame cell and routes said fixed-length cells through said switch, thereby providing, at an output of said switch, subsequent and deadlock-free transmission of consecutive cells of a certain frame, and block any cell of a different frame from interleaving. This leads to better average delay characteristics ...

Data element switch

The invention concerns an Asynchronous Transfer Mode Switch having a plurality of input stages (IS1 ... ISN) each for receiving a digital data transmission stream (DS1 ...256) consisting of a series of cells and wherein each input stage of the switch includes a circuit (52) for determining the destination of the cells of that data stream, and a circuit (63) for disassembling each cell into cell elements and for allocating to each cell element routing data to enable it to be routed across the central stages.

Switching system with time-stamped packet distribution input stage and packet sequencing output stage

DATA ELEMENT SWITCH

DATA ELEMENT SWITCH

SYSTEM AND METHOD FOR SWITCHING PACKETS IN A NETWORK

A switching node for transferring packets, each including a destination address, in a network includes a plurality of input port modules, a plurality of output port modules and a switching fabric, including a packet meta-data processor and a packet switch. Each input port module is connected to a communication link for receiving packets thereover, and each output port module is connected to a communication link for transmitting packets thereover. Each input port module, upon receiving a packet, buffers the packet and generates a meta-data packet therefore identifying the output port module that is to transmit the packet and packet identifier information, and provides it to the packet meta-data processor. The packet meta-data processor receives the meta-data packets generated by all of the input port modules and operational status information from all of the output port modules and for each output port module, processes the meta-data packets received from all of the input port modules in connection with the operational status information to determine whether the packet should be passed or dropped. If the packet meta-data processor determines that a packet associated with a meta-data packet is to be dropped, it will notify the input port module in which the packet is buffered, which, in turn, will discard the packet. On the other hand if the packet meta-data processor determines that the packet associated with the meta-data packet is not to be dropped, it will enqueue the meta-data packet for the associated output port module. Each output port module retrieves meta-data packets from its respective meta-data packet queue maintained therefor by the packet meta-data processor. For each meta-data packet retrieved by an ouput port module, the output port module will request that the input port module identified in the meta-data packet transfer the packet identified in the input port module thereto through the packet switch. When the output port module receives the packet, ...

SYNCHRONOUS AND DYNAMIC REGISTER FOR UPDATING SCATTERED SYSTEM

(57)【要約】 （修正有） 【課題】パケットネットワーク用スイッチを提供する。 【解決手段】スイッチ１０は、パケットの一部が格納さ れるメモリメカニズム１４を具えており、スイッチ１０ は、メモリメカニズム１４が連続してパケットに作動し ている間、メモリメカニズム１４に変更を設定するメカ ニズムを具えている。パケットを切り換える方法は、ス イッチ１０のバッファ２０にて、メモリメカニズム１４ に対する変更を受信する工程を具え、次に、メモリメカ ニズム１４が連続してパケットに作動している間、メモ リメカニズム１４が実現信号を受信したとき、メモリメ カニズム１４に変更を指示する工程がある。

ATM switch and control method thereof

An ATM switch including ECC encoder circuits each for generating, for an ATM cell as an information symbol, an ECC check symbol and for adding the ECC check symbol thereto, cell partitioning circuits each for subdividing an information field of an ATM cell into N partial cells, for subdividing a check symbol field into M partial cells, and for assigning an identical routing tag to the obtained partial cells (N+M) partial cell switches for respectively routing the (N+M) partial cells in an independent fashion based on the routing tag, and ECC decoder circuits for receiving the (N+M) partial cells thus routed and for achieving an error correction on the received partial cells.

Memory organization in a switching device

A router for switching data packets from a source to a destination in a network in which the router includes a distributed memory. The distributed memory includes two or more memory banks. Each memory bank is used for storing uniform portions of a data packet received from a source and linking information for each data packet to allow for the extraction of the uniform portions of a data packet from distributed locations in memory in proper order after a routing determination has been made by the router ...

Backplane Interface Adapter with Error Control and Redundant Fabric

A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.

Verfahren und Struktur zur Unterstützung von Rahmen variabler Länge in einer Vermittlungsanlage mit gemeisamem Speicher

Ampic dram system in a telecommunication switch

TRAIN PACKET CONSTITUTING METHOD OF ATM SWITCH SYSTEM

PURPOSE: A train packet constituting method of an ATM switch system is provided to improve a processing rate by reading an effective cell from a unicast queue at a time point when a dummy cell is requested and generating a train packet only with the effective cell. CONSTITUTION: When a queue to be provided for service is selected through a primary scheduler, it is judged whether a grouped multicast queue has been selected as a service queue(S100,S102). If the grouped multicast queue has been selected as the service queue, a parameter 'i' indicating the number of level 0 train packets is set to '0' and new HOL(Head of Line) multicast cell is read from the selected grouped multicast queue(S104,S106). It is judged whether a B bit value of the grouped multicast cell has been set to '0'(S108). If the B bit value of the grouped multicast cell has not been set to '0', one of plural unicast queues corresponding to Fan-out Ports outputted by the grouped multicast cell is selected by a round robin ...

SWITCH DEVICE

PROBLEM TO BE SOLVED: To provide the connection switch device of a protocol adapter provided with different speed and format characteristics. SOLUTION: This device is provided with a centralized switch core 10 and a switch core access layer element SCAL. Then, the switch core and the SCAL perform communication through the (n) lines of parallel/serial links for transmitting a logic unit. The SCAL is provided with the (n) pieces of FIFOs, the (n) pieces of RAM storage existing together with respective RAMs related to one logic unit, a first multiplex means for performing a write processing under the control of the first set of the (n) pieces of tables and receiving the contents of a parallel bus and a second multiplex means for performing a read processing from the (n) pieces of the RAM storage under the control of the second set of the (n) pieces of the tables and the logic unit is generated. COPYRIGHT: (C)2000,JPO ...

Large scale interconnect switch timer identifier crossbar component

AMPIC DRAM system

A technique and system for eliminating bus contention in multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, while eliminating the need for external control paths and random memory addressing, through the use of data header destination bits and a novel dedication of reduced size slot buffers to separate DRAM banks and similarly dedicated I/O data read resource ports, particularly useful for relatively short ATM message networking and the like, wherein all system I/O resources are enabled simultaneously to write complete ATM messages into a single slot buffer, and also for SONET cross connect and WDM messages.

Separation of data and control in a switching device

A method and apparatus for switching a data packet between a source and destination in a network. The data packet includes a header portion and a data portion. The header portion includes routing information for the data packet. The method includes defining a data path in the router comprising a path through the router along which the data portion of the data packet travels and defining a control path comprising a path through the router along which routing information from the header portion travels. The method includes separating the data path and control path in the router such that the routing information can be separated from the data portion allowing for the separate processing of each in the router. The data portion can be stored in a global memory while routing decisions are made on the routing information in the control path.

Separation of data and control in a switching device

A method and apparatus for switching a data packet between a source and destination in a network. The data packet includes a header portion and a data portion. The header portion includes routing information for the data packet. The method includes defining a data path in the router comprising a path through the router along which the data portion of the data packet travels and defining a control path comprising a path through the router along which routing information from the header portion travels. The method includes separating the data path and control path in the router such that the routing information can be separated from the data portion allowing for the separate processing of each in the router. The data portion can be stored in a global memory while routing decisions are made on the routing information in the control path.

Separation of data and control in a switching device

A method and apparatus for switching a data packet between a source and destination in a network. The data packet includes a header portion and a data portion. The header portion includes routing information for the data packet. The method includes defining a data path in the router comprising a path through the router along which the data portion of the data packet travels and defining a control path comprising a path through the router along which routing information from the header portion travels. The method includes separating the data path and control path in the router such that the routing information can be separated from the data portion allowing for the separate processing of each in the router. The data portion can be stored in a global memory while routing decisions are made on the routing information in the control path.

High speed switching architecture

PCT No. PCT/AU92/00322 Sec. 371 Date Nov. 18, 1993 Sec. 102(e) Date Nov. 18, 1993 PCT Filed Jul. 1, 1992 PCT Pub. No. WO93/01669 PCT Pub. Date Jan. 21, 1993.The present invention provides a high speed non-blocking buffered banyan packet switching architecture which utilizes parallel switching fabrics to switch slices of serial packets (subpackets) in a parallel manner. Serial digital information is received, converted into parallel form, buffered, and introduced into a parallel interconnect network which provides separate parallel paths for each packet/subpacket of information. The parallel subpackets are multiplexed, switched, demultiplexed, and recombined by way of a parallel-to-serial converter and an output port controller so as to reconstitute the original serial data stream, thereby providing high speed effective data switching at relatively low clock speeds.

Synchronous dynamic register updating across a ditributed system

A switch for a network. The switch comprises a memory mechanism in which portions of packets are stored. The switch comprises a mechanism for instituting changes to the memory mechanism while the memory mechanism continuously operating on packets. A method for switching packets. The method comprises the steps of receiving changes for a memory mechanism of a switch at a buffer of the switch. Then there is the step of implementing the changes to the memory mechanism when the memory mechanism receives an implementation signal while the memory mechanism continuously operates on packets.

High speed switching device

A router (20) for switching a data packet between a source (10) and destination (30) in a network including a plurality of input ports each including a data handler. The data handler divides a data packet into one or more fixed length cells. The router (20) includes a plurality of output ports at least one of which is for routing the data packet to the destination (30) and a memory divided into a plurality of memory banks. An input switch receives fixed length cells from the input ports and writes a single output switch routes cells received from the memory to an appropriate output port.

Switching system and method for asynchronous transfer mode exchange for multimedia service

A switch network and method of an asynchronous transfer mode switch network, includes an input buffer; an input switch network performing fetch and add function; a copy switch network performing fetch and add function; a feedback switch network receiving cells fedback and maintaining them until the next cell cycle; a routing table for storing data for translation and replacement of data for the cells' routing; a routing/feedback controller routing-controlling the input cells and fedback cells with reference to the routing table; routing switch networks switching-outputting the cells input; a cell splitter splitting the cells routing-output into the number of the routing networks and transferring them to the routing switch networks, and a cell merger merging and outputting the cells split and output from the output ports of the routing switch networks ...

High-performance network switch

The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band control information in multiple stripes to the switching fabric. The switching fabric includes a plurality of cross points corresponding to the multiple stripes. In one embodiment five stripes and five cross points are used. Each blade has a backplane interface adapter (BIA). One or more integrated bus translators (IBTs) and/or source packet processors are coupled to a BIA. An encoding scheme for packets of data carried in wide striped cells is provided.

Method of and operating architectural enhancement for multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, eliminating external control paths and random memory addressing, while providing zero bus contention for DRAM access

A technique and system for eliminating bus contention in multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, while eliminating the need for external control paths and random memory addressing, through the use of data header destination bits and a novel dedication of reduced size slot buffers to separate DRAM banks and similarly dedicated I/O data read resource ports, particularly useful for relatively short ATM message networking and the like, wherein all system I/O resources are enabled simultaneously to write complete ATM messages into a single slot buffer, and also for SONET Cross Connect and WDM messages.

Switching system with time-stamped packet distribution input stage and packet sequencing output stage

In a fast packet switching system, packet distributers are associated respectively with input ports for receiving successive packets therefrom and attaching a timeslot number to each of the received packets, and uniformly distributing the packets to output terminals of each distributer. Packet switches are provided corresponding in number to the output terminals of each packet distributer. Each packet switch has input terminals corresponding in number to the packet distributers and output terminals corresponding in number to the output ports. The input terminals of each packet switch are coupled to respective output terminals of the distributers for switching a packet from one of its input terminals to one of its output terminals in accordance with a destination address contained in the packet. Packet sequencers are associated respectively with the output ports. Each packet sequencer has input terminals coupled to respective output terminals of the packet switches for examining the timeslot ...

SPEICHERORGANISATION IN EINER VERMITTLUNGSVORRICHTUNG

A ROUTING ARRANGEMENT

L'invention concerne un dispositif d'acheminement crossbar destiné à être utilisé dans un système numérique pourvu d'au moins trois bus. L'invention concerne également le procédé associé à ce dispositif d'acheminement. Ce dispositif d'acheminement, conçu pour transmettre un ensemble de données envoyé par l'un des bus à un autre de ces bus, comprend un dispositif de commande associé à chaque bus afin de diviser ledit ensemble de données en au moins un premier et un second sous-ensembles de données, et d'ajouter des signaux d'acheminement automatique à chaque sous-ensemble de données, ces signaux identifiant un bus particulier. Un dispositif de commutation est en outre conçu pour diriger le premier et le second sous-ensembles de données de manière prédéterminée, en réponse audits signaux d'acheminement automatique. L'ensemble de commande coopère avec cet ensemble de commutation afin de transmettre les sous-ensembles de données sur des voies de transmission de données physiquement distinctes ...

Method and structure for variable-length frame support in a shared memory switch

The present invention relates to switching in electronic networks. Many data transmission protocols and technologies used in such networks, such as TCP/IP and Ethernet, use variable-length packets for transmission. Often however, the nodes that make up these networks typically contain high-speed cell switches that only support fixed-size data units. To support variable-length packets in such a fixed-size cell switch non-interleaving switching and transmission must be offered. The present invention provides such a solution in essence by segmenting a variable-length frame into a plurality of fixed-length cells including a start-of-frame cell, one or more continuation cell(s), and an end-of-frame cell and routes said fixed-length cells through said switch, thereby providing, at an output of said switch, subsequent and deadlock-free transmission of consecutive cells of a certain frame, and block any cell of a different frame from interleaving. This leads to better average delay characteristics ...

Memory organization in a switching device

A router for switching data packets from a source to a destination in a network in which the router includes a distributed memory. The distributed memory includes two or more memory banks. Each memory bank is used for storing uniform portions of a data packet received from a source and linking information for each data packet to allow for the extraction of the uniform portions of a data packet from distributed locations in memory in proper order after a routing determination has been made by the router ...

Backplane interface adapter

A backplane interface adapter for a network switch. The backplane interface adapter includes at least one receiver that receives input cells carrying packets of data; at least one cell generator that generates encoded cells which include the packets of data from the input cells; and at least one transmitter that transmits the generated cells to a switching fabric. The cell includes a destination slot identifier that identifies a slot of the switching fabric towards which the respective input cell is being sent. The generated cells include in-band control information.

Verfahren und Struktur zur Unterstützung von Rahmen variabler Länge in einer Vermittlungsanlage mit gemeisamem Speicher

High speed switching device

A router for switching a data packet between a source and destination in a network including a plurality of input ports each including a data handler. The data handler divides a data packet into one or more fixed length cells. The router includes a plurality of output ports at least one of which is for routing the data packet to the destination and a memory divided into a plurality of memory banks. A input switch receives fixed length cells from the input ports and writes a single cell in a cell slot time span to each memory bank. An output switch routes cells received from the memory to an appropriate output port.

Backplane Interface Adapter with Error Control

A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The error control may be provided by an administrative module that includes a level monitor, a stripe synchronization error detector, a flow controller, and a control character presence tracker. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.

A ROUTING ARRANGEMENT

A crossbar routing arrangement is disclosed for use in a digital system having three or more buses. An associated method is also disclosed. The routing arrangement is configured for transferring a set of data received from any particular one of the buses to any other selected one of the buses and includes a control arrangement associated with each bus for dividing the set of data into at least first and second subsets of data and for adding self-routing signals to each data subset which signals identify the selected bus. A switching arrangement is configured for directing the first and second data subsets in a predetermined way responsive to the self-routing signals. The control arrangement cooperates with the switching arrangement to transfer the data subsets over physically distinct data transfer paths defined between the switching arrangement and the control arrangements. In accordance with one feature, the configuration of the routing arrangement provides for linear expansion whereby ...

MEMORY ORGANIZATION IN A SWITCHING DEVICE

A router (20) for switching data packets from a source (10) to a destination (30) in a network in which the router includes a distributed memory. The distributed memory includes two or more memory banks. Each memory bank is used for storing uniform portions of a data packet received from a source (10) and linking information for each data packets to allow for extraction of the uniform portions of a data packets from distributed locations in memory in proper order after a routing determination has been made by the router (20).

Method of and operating architectural enhancement for multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, eliminating external control paths and random memory addressing, while providing zero bus contention for DRAM access

A technique and system for eliminating bus contention in multi-port internally cached dynamic random access memory (AMPIC DRAM) systems, while eliminating the need for external control paths and random memory addressing, through the use of data header destination bits and a novel dedication of reduced size slot buffers to separate DRAM banks and similarly dedicated I/O data read resource ports, particularly useful for relatively short ATM message networking and the like, wherein all system I/O resources are enabled simultaneously to write complete ATM messages into a single slot buffer, and also for SONET Cross Connect and WDM messages.

ATM switch and control method thereof

An ATM switch including ECC encoder circuits each for generating, for an ATM cell as an information symbol, an ECC check symbol and for adding the ECC check symbol thereto, cell partitioning circuits each for subdividing an information field of an ATM cell into N partial cells, for subdividing a check symbol field into M partial cells, and for assigning an identical routing tag to the obtained partial cells (N+M) partial cell switches for respectively routing the (N+M) partial cells in an independent fashion based on the routing tag, and ECC decoder circuits for receiving the (N+M) partial cells thus routed and for achieving an error correction on the received partial cells.

High speed variable length best match look-up in a switching device

A method and apparatus for looking up a key associated with a packet to determine a route through a routing device, the method including, upon receipt of a key, forward traversing one or more nodes which make up a trie stored in a memory by evaluating at each node traversed a bit in the key as indicated by a bit-to-test indicator associated with each node. A value of the bit in the key determining the path traversed along the trie. The method includes locating an end node having a route and comparing the route to the key. If they match, destination information associated with the end node is outputted to guide the transfer of the packet through the routing device. If they do not match, the trie is traversed backwards to locate a best match for the key.

A Routing Arrangement

3개 또는 그 이상의 버스를 가진 디지털 시스템에서 사용되는 크로스바 라우팅 배열이 개시되어 있다. 또한 관련 방법이 개시되어 있다. 라우팅 배열은 버스들 중의 어느 특정 버스로부터 수신된 데이터 세트를 버스들 중의 다른 선택 버스로 전송하는 것으로 구성되어 있고, 데이터 세트를 적어도 일차 및 이차 데이터 서브세트로 분할하고 선택 버스를 결정하는 셀프-라우팅 신호를 각각의 데이터 서브세트에 부가하기 위한, 각 버스에 연계되어 있는 제어 배열을 포함한다. 스위칭 배열은 셀프-라우팅 신호에 호응하여 미리 정해진 방식으로 일차 및 이차 데이터 서브세트를 인도하도록 구성되어 있다. 제어 배열은 스위칭 배열과 제어 배열 사이에 정의된 물리적으로 구별되는 데이터 전송 경로상으로 데이터 서브세트를 전송하도록 제어 배열과 함께 작동한다. 하나의 특징에 따르면, 라우팅 배열의 구성은 선형 확장을 제공하므로, 어떠한 경우에도 높은 데이터 처리량을 유지하면서 비용면에서 효과적인 방법으로, 증가된 폭을 가진 버스에 작용하고 증가된 수의 버스에 작용하게 된다.

Backplane interface adapter

A backplane interface adapter for a high-performance network switch. The backplane interface adapter receives narrow input cells carrying packets of data and outputs wide striped cells to a switching fabric. One traffic processing path through the backplane interface adapter includes deserializer receivers, a traffic sorter, wide cell generators, stripe send queues, a backplane transmit arbitrator, and serializer transmitters. Another traffic processing path through the backplane interface adapter includes deserialize receivers, a stripe interface, stripe receive synchronization queues, a controller, wide/narrow cell translator, destination queues, and serializer transmitters. An encoding scheme for packets of data carried in wide striped cells is provided.

High-performance network switch

The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band control information in multiple stripes to the switching fabric. The switching fabric includes a plurality of cross points corresponding to the multiple stripes. In one embodiment five stripes and five cross points are used. Each blade has a backplane interface adapter (BIA). One or more integrated bus translators (IBTs) and/or source packet processors are coupled to a BIA. An encoding scheme for packets of data carried in wide striped cells is provided.

Memory organization in a switching device

A router for switching data packets from a source to a destination in a network in which the router includes a distributed memory. The distributed memory includes two or more memory banks. Each memory bank is used for storing uniform portions of a data packet received from a source and linking information for each data packet to allow for the extraction of the uniform portions of a data packet from distributed locations in memory in proper order after a routing determination has been made by the router.

High-performance network switch

The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band control information in multiple stripes to the switching fabric. The switching fabric includes a plurality of cross points corresponding to the multiple stripes. In one embodiment five stripes and five cross points are used. Each blade has a backplane interface adapter (BIA). One or more integrated bus translators (IBTs) and/or source packet processors are coupled to a BIA. An encoding scheme for packets of data carried in wide striped cells is provided.

AMPIC DRAM system in telecommunications exchange

(57)【要約】 マルチポート内部キャッシュダイナミックランダムアクセスメモリ（AMPIC DRAM）システムにおけるバス競合をなくし、同時に、外部制御パス及びランダムなメモリアドレッシングを不要にするための技法及びシステムを開示する。これは、データヘッダーの宛先ビットと、サイズを小さくした新規な専用のスロットバッファを使用して、DRAMバンクと、専用化されたI/Oデータ読み出し用リソースポートとを分離することにより実現される。本発明は、比較短いATMメッセージネットワーキングやこれと類似のもの、さらに、SONET Cross Connect及びWDMメッセージに対して特に有効である。ATMメッセージネットワーキングの場合には、全てのシステムI/Oリソースが、完全なATMメッセージを単一のスロットバッファに同時に書き込むことができるようになる。

Switch fabrics logical synchronization utilizing propagation lockdown

A switch includes a port card for receiving packets from and sending packets to a network. The switch includes a fabric connected to the port card for switching the packets. The fabric has memory controllers which perform logical functions and in which portions of the packets are stored. The fabric has stages for switching the portions of the packets. The fabric has a mechanism for propagated lockdown of each stage wherein each stage is idle a correct number of cycles and each memory controller performs the same logical functions the corresponding same logical cycles. A method for switching packets includes the steps of introducing idles a correct number of cycles in each stage of memory controllers in fabrics of a switch to maintain the fabrics in logical synchronization. Then there is the step performing with each memory controller in the fabrics same logical functions at corresponding same logical cycles.

ATM switching device having memory

Backplane interface adapter with error control and redundant fabric

A backplane interface adapter with error control and redundant fabric for a high-performance network switch. The redundant fabric transceiver of the backplane interface adapter improves the adapter's ability to properly and consistently receive narrow input cells carrying packets of data and output wide striped cells to a switching fabric.

Method and system for encoding wide striped cells

A system and method for encoding wide striped cells that carry packets of data across stripes. The method encodes an initial block of a first wide striped cell is encoded with initial cell encoding information, and distributes initial bytes of packet data into available space in the initial block of the first wide striped cell. The initial cell encoding information includes control information and state information. One initial block of the first wide striped cell comprises five subblocks corresponding to five stripes. Each subblock includes identical control information and identical state information. The method further includes adding reserve information to available bytes at the end of the initial block of the first wide striped cell. Remaining bytes of packet data are distributed across one or more blocks in the first wide striped cell until an end of packet condition is reached or a maximum cell size is reached. Other steps include encoding the first wide striped cell or another wide striped cell with end of packet information. The end of packet information varies depending upon a set of end of packet conditions, such as, whether the end of packet occurs at the end of an initial block, at the end of the initial block, within a subsequent block, at a block boundary, or at a cell boundary.

Memory organization in a switching device

A router (20) for switching data packets from a source (10) to a destination (30) in a network in which the router includes a distributed memory. The distributed memory includes two or more memory banks. Each memory bank is used for storing uniform portions of a data packet received from a source (10) and linking information for each data packets to allow for extraction of the uniform portions of a data packets from distributed locations in memory in proper order after a routing determination has been made by the router (20).

Memory organization in a switching device

A network device switches variable length data units from a source to a destination in a network. An input port receives the variable length data unit and a divider divides the variable length data unit into uniform length data units for temporary storage in the network device. A distributed memory includes a plurality of physically separated memory banks addressable using a single virtual address space and an input switch streams the uniform length data units across the memory banks based on the virtual address space. The network device further includes an output switch for extracting the uniform length data units from the distributed memory by using addresses of the uniform length data units within the virtual address space. The output switch reassembles the uniform length data units to reconstruct the variable length data unit. An output port receives the variable length data unit and transfers the variable length data unit to the destination.

Receiver decoding algorithm to allow hitless n+1 redundancy in a switch

A switch for switching packets. The switch includes a plurality of fabrics (14) which switch portions of packets. The switch includes a port card (12) connected to the fabrics (14) and the network for receiving packets from and sending packets to the network. The port card (12) has a mechanism (16) for tolerating whether any one of the plurality of fabrics (14) has a failure and still sending correct packets to the network. A method for switching packets. The method includes the steps of receiving packets at a port card (12) from a network of a switch. Then there is the step of sending to fabrics (14) of the switch portions of the packets as stripes (20) from the port card (12). Next there is the step of switching the portions of the packets with the fabrics (14). Then there is the step of sending back to the port card the portions of the packets as stripes (20) from the fabrics (14). Next there is the step of sending correct packets with the port card (12) to the network even though one of the fabrics (14) has a failure.

Exchange system and method for asynchronous transmission mode exchange

异步传输方式交换网络的交换网络和方法包括：输入缓冲器；执行取和加功能的输入开关网络；执行取和加功能的拷贝开关网络；接收反馈的信元并保持它们直至下一个信元周期；存储用于翻译和替换信元路由数据的数据的路由选择表；参考路由表对输入信元和反馈信元进行路由控制的路由/反馈控制器；转换-输出信元输入信号的路由开关网络；把信元路由输出信号分割成路由网络数并把它们传输到路由开关网络；合并和输出路由开关网络输出端口的信元的信元合并器。

Verfahren und struktur zur unterstützung von rahmen variabler länge in einer vermittlungsanlage mit gemeisamem speicher

Switching apparatus comprising at least one switch core access element for the attachment of various protocol adapters

Synchronous dynamic register updating across a ditributed system

A switch for a network. The switch comprises a memory mechanism in which portions of packets are stored. The switch comprises a mechanism for instituting changes to the memory mechanism while the memory mechanism continuously operating on packets. A method for switching packets. The method comprises the steps of receiving changes for a memory mechanism of a switch at a buffer of the switch. Then there is the step of implementing the changes to the memory mechanism when the memory mechanism receives an implementation signal while the memory mechanism continuously operates on packets.

Synchrone dynamische Aktualisierung eines Registers über ein verteiltes System

Synchrone dynamische aktualisierung eines registers über ein verteiltes system

在atm交换系统中生成并传输串列分组的方法

本发明的实施例涉及生成一组数据(比如，分组)。这组数据包含来自第一队列和第二队列的信元。第一队列中的所有信元均相互独立。第二队列中至少有两个信元相互关联。

Parallel byte processing engines shared among multiple data channels

A method and apparatus for processing bytes received from a data stream includes multiple parallel byte processing engines that simultaneously process a first set of bytes received from a data channel during a first cycle and simultaneously process a second set of bytes received from the data channel during a second cycle. The method and apparatus further includes a state memory for storing byte information pertaining to the first set of bytes. When processing HDLC protocol bytes, the multiple parallel byte processing engines process the first and second set of bytes to identify at least one delineating byte contained within the data channel in accordance with a HDLC protocol. When processing ATM cell bytes, the method and apparatus further includes multiple parallel quad-byte processing engines for calculating cell delineation values, and multiple comparators for comparing the calculated cell delineation values with respective bytes from the second set of bytes to identify ATM start bytes contained in the first set of bytes.

Packet processing apparatus using packet processing units located at parallel packet flow paths and with different programmability

在atm交换系统中生成并传输串列分组的方法

本发明的实施例涉及生成一组数据(比如，分组)。这组数据包含来自第一队列和第二队列的信元。第一队列中的所有信元均相互独立。第二队列中至少有两个信元相互关联。

封包處理裝置、入口封包處理電路和出口封包處理電路

一種封包處理裝置、入口封包處理電路和出口封包處理電路。封包處理裝置包含入口封包處理電路，出口封包處理電路；以及流量管理器，處理至少封包排隊和排程；其中入口封包處理電路和出口封包處理電路之至少一封包處理電路包含：位於第一封包流路徑之第一封包處理單元，以及位於第二封包流路徑之第二封包處理單元，其中第一封包流路徑平行於第二封包流路徑，以及第一封包處理單元之可程式性高於第二封包處理單元之可程式性。上述封包處理裝置、入口封包處理電路和出口封包處理電路可在彈性和封包處理性能之間取得平衡。

Packet processing apparatus using packet processing units located at parallel packet flow paths and with different programmability

A packet processing apparatus has an ingress packet processing circuit, an egress packet processing circuit, and a traffic manager. The ingress packet processing circuit processes ingress packets received from ingress ports. The egress packet processing circuit processes egress packets to be forwarded through egress ports. The traffic manager deals with at least packet queuing and scheduling. At least one of the ingress packet processing circuit and the egress packet processing circuit includes a first packet processing unit located at a first packet flow path, and a second packet processing unit located at a second packet flow path. The first packet flow path is parallel with the second packet flow path, and programmability of the first packet processing unit is higher than programmability of the second packet processing unit.