High speed switching architecture

PCT No. PCT/AU92/00322 Sec. 371 Date Nov. 18, 1993 Sec. 102(e) Date Nov. 18, 1993 PCT Filed Jul. 1, 1992 PCT Pub. No. WO93/01669 PCT Pub. Date Jan. 21, 1993.The present invention provides a high speed non-blocking buffered banyan packet switching architecture which utilizes parallel switching fabrics to switch slices of serial packets (subpackets) in a parallel manner. Serial digital information is received, converted into parallel form, buffered, and introduced into a parallel interconnect network which provides separate parallel paths for each packet/subpacket of information. The parallel subpackets are multiplexed, switched, demultiplexed, and recombined by way of a parallel-to-serial converter and an output port controller so as to reconstitute the original serial data stream, thereby providing high speed effective data switching at relatively low clock speeds.