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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 44180. Отображено 100.
05-01-2012 дата публикации

Semiconductor device

Номер: US20120001243A1
Автор: Kiyoshi Kato
Принадлежит: Semiconductor Energy Laboratory Co Ltd

An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

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Номер записи: 1
05-01-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120001258A1
Автор: Wan Soo Kim
Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a gate metal buried within a trench included in a semiconductor substrate including an active region defined by an isolation layer, a spacer pattern disposed on an upper portion of a sidewall of a gate metal, a first gate oxide layer disposed between the spacer pattern and the trench, a second gate oxide layer disposed below the first gate oxide layer and the gate metal, and a junction region disposed in the active region to overlap the first gate oxide layer.

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Номер записи: 2
05-01-2012 дата публикации

Semiconductor Constructions

Номер: US20120001299A1
Автор: Todd Jackson Plum
Принадлежит: Micron Technology Inc

Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage node, a second dielectric material, and a second plate material. The first and second sections may be formed over a memory array region, and the first and second plate materials may be electrically connected to first and second interconnects, respectively, that extend to over a region peripheral to the memory array region. The first and second interconnects may be electrically connected to one another to couple the first and second plate materials to one another. Some embodiments include capacitor structures, and some embodiments include methods of forming DRAM arrays.

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Номер записи: 3
12-01-2012 дата публикации

Semiconductor device with side-junction and method for fabricating the same

Номер: US20120007258A1
Автор: Bong-Seok Jeon, Jae-Geun Oh, Jin-Ku Lee, Mi-Ri Lee, Seung-Joon Jeon
Принадлежит: Hynix Semiconductor Inc

A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench.

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Номер записи: 4
19-01-2012 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20120012926A1
Автор: Chang Jun Yoo, Ga Young Ha
Принадлежит: Hynix Semiconductor Inc

A method for fabricating a semiconductor memory device includes defining an active region having a shape protruding upward by forming a trench in a semiconductor substrate; forming an open region obtained by selectively exposing a lower side portion of the active region while forming a sidewall layer along the shape of the active region; covering the open region with a silicon layer; forming an impurity region in the lower side portion of the active region; forming a barrier metal layer on the silicon layer and the active region; forming a bit line metal layer buried in the entire active region; and forming a buried bit line having the barrier metal layer, the bit line metal layer and a silicide metal layer formed between the silicon layer and the barrier metal layer by etching the bit line metal layer up to a portion at which the impurity region is formed.

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Номер записи: 5
19-01-2012 дата публикации

Method of manufacturing non-volatile memory device

Номер: US20120015512A1
Автор: Choong-ho Lee, Dong-Uk Choi, Hee-Soo Kang, Suk-kang Sung
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A non-volatile memory device includes field insulating layer patterns on a substrate to define an active region of the substrate, upper portions of the field insulating layer patterns protruding above an upper surface of the substrate, a tunnel insulating layer on the active region, a charge trapping layer on the tunnel insulating layer, a blocking layer on the charge trapping layer, first insulating layers on upper surfaces of the field insulating layer patterns, and a word line structure on the blocking layer and first insulating layers.

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Номер записи: 6
26-01-2012 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20120018799A1
Автор: Hyung Jin Park
Принадлежит: Hynix Semiconductor Inc

A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to a silicon layer formed over a gate, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; a plurality of gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; a silicon layer disposed on the upper portion and sidewalls of the gate; and a second plug coupled to the silicon layer disposed over the gate.

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Номер записи: 7
26-01-2012 дата публикации

Pillar type capacitor of semiconductor device and method for forming the same

Номер: US20120019980A1
Автор: Cheol Hwan Park, Dong Kyun Lee, Ho Jin Cho
Принадлежит: Hynix Semiconductor Inc

An embodiment of the invention includes a pillar type capacitor where a pillar is formed over an upper portion of a storage node contact. A bottom electrode is formed over sidewalls of the pillar, and a dielectric film is formed over pillar and the bottom electrode. A top electrode is then formed over the upper portion of the dielectric film.

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Номер записи: 8
02-02-2012 дата публикации

System with logic and embedded mim capacitor

Номер: US20120025285A1
Автор: Jeong Y. Choi
Принадлежит: Mosys Inc

An embedded memory system includes an array of random access memory (RAM) cells, on the same substrate as an array of logic transistors. Each RAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-insulator-metal capacitor in a dielectric layer. The embedded RAM system includes fewer metal layers in the logic region than in the memory region

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Номер записи: 9
02-02-2012 дата публикации

Method of manufacturing semiconductor device using acid diffusion

Номер: US20120028434A1
Автор: Hyoung-hee KIM, Hyung-Rae Lee, Kyung-Hwan Yoon, So-Ra Han, Tae-hoi Park, Yool Kang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing a semiconductor device includes forming a resist pattern on a first region on a substrate, bringing a descum solution including an acid source into contact with the resist pattern and with a second region of the substrate, decomposing resist residues remaining on the second region of the substrate by using acid obtained from the acid source in the descum solution and removing the decomposed resist residues and the descum solution from the substrate.

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Номер записи: 10
02-02-2012 дата публикации

Method of manufacturing a semiconductor device

Номер: US20120028471A1
Автор: Hidetami Yaegashi, Kazuo Yabe, Kenichi Oyama
Принадлежит: Tokyo Electron Ltd

A method of manufacturing a semiconductor device includes: forming a thin film on a substrate; forming a resist mask which forms a photoresist mask having an elliptical hole pattern on the thin film; shrinking a hole size of the second pattern by forming an insulating film on a side wall of the second pattern of the photoresist layer; and etching the thin film using the insulating film and the photoresist layer which form the second pattern having the shrinked hole size as a mask.

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Номер записи: 11
09-02-2012 дата публикации

Method for fabrication of a semiconductor device and structure

Номер: US20120032294A1
Автор: Brian Cronquist, Deepak C. Sekar, Israel Beinglass, Jan Lodewijk de Jong, Zvi Or-Bach
Принадлежит: Monolithic 3D Inc

A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

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Номер записи: 12
09-02-2012 дата публикации

Semiconductor device and method for driving semiconductor device

Номер: US20120033486A1
Автор: Hiroki Inoue, Kiyoshi Kato, Shuhei Nagatsuka, Takanori Matsuzaki
Принадлежит: Semiconductor Energy Laboratory Co Ltd

It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and does not have a limitation on the number of writing operations. A semiconductor device includes a plurality of memory cells each including a transistor including a first semiconductor material, a transistor including a second semiconductor material that is different from the first semiconductor material, and a capacitor, and a potential switching circuit having a function of supplying a power supply potential to a source line in a writing period. Thus, power consumption of the semiconductor device can be sufficiently suppressed.

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Номер записи: 13
09-02-2012 дата публикации

Methods of fabricating semiconductor devices having various isolation regions

Номер: US20120034757A1
Автор: Eunkee Hong, Gil-heyun Choi, Ha-Young YI, Hong-Gun Kim, Jun-Won Lee, Yong-Soon Choi
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of fabricating a semiconductor device includes forming a first trench and a second trench in a semiconductor substrate, forming a first insulator to completely fill the first trench, the first insulator covering a bottom surface and lower sidewalls of the second trench and exposing upper sidewalls of the second trench, and forming a second insulator on the first insulator in the second trench.

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Номер записи: 14
23-02-2012 дата публикации

Methods of forming memory cells, memory cells, and semiconductor devices

Номер: US20120043611A1
Автор: Chandra V. Mouli, Gurtej S. Sandhu
Принадлежит: Micron Technology Inc

A memory device and method of making the memory device. Memory device may include a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure.

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Номер записи: 15
23-02-2012 дата публикации

Semiconductor Memory Device

Номер: US20120045872A1
Автор: Sang Min Hwang
Принадлежит: Hynix Semiconductor Inc

Disclosed herein is a semiconductor memory device for reducing a junction resistance and increasing amount of current throughout the unit cell. A semiconductor memory device comprises plural unit cells, each coupled to contacts formed in different shape at both sides of a word line in a cell array.

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Номер записи: 16
01-03-2012 дата публикации

Vertical gated access transistor

Номер: US20120049246A1
Автор: Werner Juengling
Принадлежит: Micron Technology Inc

A method of forming an apparatus includes forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The shallow trenches and the deep trenches are parallel to each other. A layer of conductive material is deposited over the first region and a second region of the substrate. The layer of conductive material is etched to define lines separated by gaps over the first region of the substrate, and active device elements over the second region of the substrate. The second region of the substrate is masked and the lines are removed from the first region of the substrate. Elongate trenches are etched where the lines were removed while the second region of the substrate is masked.

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Номер записи: 17
01-03-2012 дата публикации

A dram cell structure with extended trench and a manufacturing method thereof

Номер: US20120049262A1
Автор: Jing Chen, Miao Zhang, Xi Wang, Xiaolu Huang
Принадлежит: Shanghai Institute of Microsystem and Information Technology of CAS

A DRAM cell structure with extended trench, the DRAM cell structure comprises: a NMOS transistor and a trench capacitor connected with the source electrode of the NMOS transistor; the trench capacitor comprises: a semiconductor substrate; a multilayer structure as the bottom plate of the trench capacitor, formed over the semiconductor substrate, which is composed of N-type SiGe layers and N-type Si layers arranged alternatively; a trench formed through the multilayer structure deeply into the semiconductor substrate, whose sidewall cross section is serrate-shaped; a dielectric layer formed on the inner face of the trench; a first polycrystalline silicon layer which is filled in the trench as the top plate of the trench capacitor; and a P-type Si layer formed over the multilayer structure. The present invention adopts doping epitaxial growth process to fabricate a multilayer structure composed of N-type SiGe layers and N-type Si layers arranged alternatively as the bottom plate of the trench capacitor. Compared with the traditional buried plate, the fabricating process is simplified. In addition, the present invention adopts selective etching process to form a sidewall having a serrate-shaped cross section. This improved structure increases capacitor plate area and thus even thick dielectric layer will achieve required capacitance.

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Номер записи: 18
01-03-2012 дата публикации

Method for fabricating semiconductor device

Номер: US20120052643A1
Автор: Baek-Mann Kim
Принадлежит: Individual

A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has openings to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming an SNC to fill the opening of the second insulation patterns.

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Номер записи: 19
08-03-2012 дата публикации

Semiconductor device and method for forming the same

Номер: US20120056256A1
Автор: Noriaki Mikasa
Принадлежит: Elpida Memory Inc

A semiconductor device includes a first semiconductor pillar, a second semiconductor pillar, and a first wiring. The first semiconductor pillar includes a first diffusion region. The second semiconductor pillar is adjacent to the first semiconductor pillar. The first wiring is positioned between the first and second semiconductor pillars. The first wiring has a first metal surface. The first metal surface has an ohmic contact with the first diffusion region.

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Номер записи: 20
08-03-2012 дата публикации

Semiconductor Device

Номер: US20120056298A1
Автор: Koji Kuroki
Принадлежит: Elpida Memory Inc

A semiconductor device includes a first power supply terminal, a second power supply terminal, and first and second capacitors. The first power supply terminal is configured to be supplied with a first electrical potential. The second power supply terminal is configured to be supplied with a second electrical potential. The second electrical potential is different from the first electrical potential. The first and second capacitors are coupled in series between the first and second power supply terminals.

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Номер записи: 21
15-03-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120063212A1
Автор: Koji Miyamoto, Masahiko Kanda
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor device includes a first transistor and a second transistor having a conductivity type which is different from a conductivity type of the first transistor, the first transistor and the second transistor being disposed on a semiconductor substrate such that a gate electrode of the first transistor and a gate electrode of the second transistor are connected to each other. The gate electrode of the first transistor includes first impurities and second impurities which suppress diffusion of the first impurities, and a concentration peak of the first impurities is formed at a shallower position than a concentration peak of the second impurities.

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Номер записи: 22
15-03-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120064690A1
Автор: Takakazu Kiyomura, Toshiyuki Hirota
Принадлежит: Elpida Memory Inc

A method for manufacturing a semiconductor device includes at least forming a lower electrode made of titanium nitride on a semiconductor substrate, forming a dielectric film comprising zirconium oxide, in which at least the uppermost layer of the dielectric film is formed by an atomic layer deposition (ALD) method on the lower electrode, forming a first protective film on the dielectric film without exceeding the film forming temperature of the ALD method over 70° C., and forming an upper electrode made of a titanium nitride on the first protective film.

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Номер записи: 23
29-03-2012 дата публикации

Semiconductor Device

Номер: US20120074473A1
Автор: Sang Don Lee
Принадлежит: Hynix Semiconductor Inc

A method for fabricating a semiconductor device comprises forming a partial-insulated substrate comprising an insulating region located below both a channel region of a cell transistor and one of a storage node contact region and a bit line contact region, and forming a cell transistor comprising a fin region on the partial-insulated substrate.

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Номер записи: 24
05-04-2012 дата публикации

Semiconductor integrated circuit

Номер: US20120080750A1
Автор: Gyung Tae Kim, Kang Youl Lee
Принадлежит: Hynix Semiconductor Inc

A semiconductor integrated circuit includes: a semiconductor substrate comprising a word line decoder region and a memory cell region; a basic word line formed in the memory cell region in a buried gate type; and an additional word line formed to extend from the word line decoder region across the memory cell region, wherein the additional word line is formed over the basic word line in parallel to the basic word line and is coupled to the basic word line through two or more vias.

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Номер записи: 25
12-04-2012 дата публикации

Semiconductor device and method of forming the same

Номер: US20120086060A1
Автор: Koji Taniguchi
Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate, a gate electrode, a dummy gate electrode, and a first impurity diffusion region. The semiconductor substrate has first and second grooves. The gate electrode is in the first groove. The dummy gate electrode is in the second groove. The dummy gate electrode has a first top surface. The first impurity diffusion region in the semiconductor substrate is positioned between the first and second grooves. The first top surface is positioned at a lower level than a bottom of the first impurity diffusion region.

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Номер записи: 26
12-04-2012 дата публикации

Semiconductor device

Номер: US20120086063A1
Автор: Koji Taniguchi
Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate having a memory cell region and a peripheral circuit region; a bit line extending over the memory cell region and the peripheral circuit region, the bit line including a first portion in the peripheral circuit region; and a sense amplifier in the peripheral circuit region. The sense amplifier includes a transistor having a gate electrode which includes the first portion of the bit line.

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Номер записи: 27
12-04-2012 дата публикации

Dual port static random access memory cell layout

Номер: US20120086082A1
Автор: Jack M. Higman, Pierre Malinge, Sanjay R. Parihar
Принадлежит: Individual

A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node; a first pass transistor coupled to the true data node, and a second pass transistor coupled to the complementary data node. A second active region has the same size and shape as the first active region and has a third pull-down transistor coupled in parallel to the first-pull down transistor, a fourth pull-down transistor coupled in parallel to the second pull-down transistor; a third pass transistor coupled to the true data node, and a fourth pass transistor coupled to the complementary data node. A first pull-up transistor and a second pull-up transistor are located between the first and second active regions.

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Номер записи: 28
12-04-2012 дата публикации

Method of manufacturing vertical semiconductor device

Номер: US20120088343A1
Автор: Jong-Hyuk Kang, Jong-wook Lee, Yong-Hoon Son
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.

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Номер записи: 29
12-04-2012 дата публикации

Semiconductor device and structure

Номер: US20120088367A1
Автор: Deepak C. Sekar, Zvi Or-Bach
Принадлежит: Monolithic 3D Inc

A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate; preparing a first monocrystalline layer comprising semiconductor regions; preparing a second monocrystalline layer comprising semiconductor regions overlying the first monocrystalline layer; and etching portions of said first monocrystalline layer and portions of said second monocrystalline layer as part of forming at least one transistor on said first monocrystalline layer.

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Номер записи: 30
19-04-2012 дата публикации

Semiconductor device, method for forming the same, and data processing system

Номер: US20120091518A1
Автор: Mitsunari Sukekawa
Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate having a first groove, a word line in the first groove, and a buried insulating film in the first groove. The buried insulating film covers the word line. The buried insulating film comprises a silicon nitride film.

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Номер записи: 31
19-04-2012 дата публикации

Semiconductor device, method for forming the same, and data processing system

Номер: US20120091520A1
Автор: Nobuyuki Nakamura
Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate, a first interlayer insulating film over the semiconductor substrate, a first interconnect over the first interlayer insulating film, and a via plug penetrating the semiconductor substrate and the first interlayer insulating film. The via plug is coupled to the first interconnect.

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Номер записи: 32
19-04-2012 дата публикации

Semiconductor device

Номер: US20120091537A1
Автор: Kanna Adachi, Satoshi Inaba, Shigeru Kawanaka
Принадлежит: Toshiba Corp

In accordance with an embodiment, a semiconductor device includes an SRAM cell on a substrate. The SRAM cell includes: first and second load transistors each having an n-type source region and a p-type drain region, first and second driver transistors each having a p-type source region and an n-type drain region, and first and second transfer transistors each having an n-type source region and a n-type drain region. The n-type source regions of the first and second load transistors, the n-type drain regions of the first and second driver transistors, and the n-type source regions and the n-type drain regions of the first and second transfer transistors are located in a region other than a region present between any two of the p-type drain regions of the first and second load transistors and the p-type source regions of the first and second driver transistors.

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Номер записи: 33
26-04-2012 дата публикации

Method of forming a semiconductor device

Номер: US20120100702A1
Автор: Toshiya NAKAMORI
Принадлежит: Elpida Memory Inc

A method for forming a semiconductor device includes the following processes. A first well including a memory cell region of a semiconductor substrate is formed. A second well including a first peripheral circuit region of the semiconductor substrate is formed after forming the first well.

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Номер записи: 34
26-04-2012 дата публикации

Method for forming memory cell transistor

Номер: US20120100705A1
Автор: HONG Xiao
Принадлежит: Hermes Microvision Inc

A method for forming a memory cell transistor is disclosed which includes providing a substrate, forming a trench structure in the substrate, depositing a conductive substance on the surface of the substrate to form a conductive member inside the trench structure, forming one or more dielectric layers on the surface of the substrate, forming one or more first conductive layers on top of the dielectric layers, and etching the first conductive layers and the dielectric layers to form a hole structure extending through the first conductive and the dielectric layers, reaching to the substrate surface. One or more second conductive layers may be formed on top of the first conductive layers, with the second conductive layer material filling the hole structure.

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Номер записи: 35
03-05-2012 дата публикации

Field effect transistors (fets) and methods of manufacture

Номер: US20120104475A1
Автор: Brent A. Anderson, Edward J. Nowak
Принадлежит: International Business Machines Corp

An improved field effect transistors (FETs) and methods of manufacturing the field effect transistors (FETs) are provided. The method of manufacturing a zero capacitance random access memory cell (ZRAM) includes comprises forming a finFET on a substrate and enhancing a storage capacitance of the finFET. The enhancement can be by either adding a storage capacity to the finFET or altering a portion of the finFET after formation of a fin body of the finFET.

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Номер записи: 36
03-05-2012 дата публикации

Semiconductor Device Having Island Type Support Patterns

Номер: US20120104559A1
Автор: Hyun-Chul Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a plurality of cylindrical structures arranged in a first direction and a second direction, and a plurality of unit regions formed in the first direction and the second direction, each of the plurality of unit regions including an island type support pattern supporting the plurality of cylindrical structures contacting side surfaces of the plurality of cylindrical structures and an open region exposing the side surfaces of the plurality of cylindrical structures.

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Номер записи: 37
03-05-2012 дата публикации

Substrate Structure Having Buried Wiring And Method For Manufacturing The Same, And Semiconductor Device And Method For Manufacturing The Same Using The Substrate Structure

Номер: US20120108034A1
Автор: Byung-lyul Park, Dae-Lok Bae, Gil-heyun Choi, Pil-Kyu Kang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided are a substrate structure which may solve problems generated in a manufacturing process while having a relatively low resistance buried wiring, a method for manufacturing the substrate structure, and a semiconductor device and a method for manufacturing the same using the substrate structure. The substrate structure may include a supporting substrate, an insulating layer disposed on the supporting substrate, a line-shaped conductive layer pattern disposed in the insulating layer to extend in a first direction, and a line-shaped semiconductor pattern disposed in the insulating layer and on the conductive layer pattern to extend in the first direction and having a top surface exposed to the outside of the insulating layer.

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Номер записи: 38
10-05-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120112269A1
Автор: Suk Min Kim
Принадлежит: Hynix Semiconductor Inc

A technology is a semiconductor device and a method of manufacturing the same, capable of reducing capacitance with a storage node contact plug while maintaining a height and resistance of a bit line, by thickly forming a spacer between a bit line and the storage node contact plug. A semiconductor device includes a device isolation layer defining a plurality of active regions formed in a semiconductor substrate, a storage node contact hole exposing two neighboring active regions, a storage node contact plug material provided in the storage node contact hole, a bit line region that divides the storage node contact plug material into two parts and that has a convex portion at a lower portion of a sidewall, a spacer formed over a sidewall of the bit line region including the convex portion and a bit line formed in the bit line region.

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Номер записи: 39
10-05-2012 дата публикации

Semiconductor Device Comprising Transistor Structures and Methods for Forming Same

Номер: US20120112272A1
Автор: Venkatesan Ananthan
Принадлежит: Micron Technology Inc

A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.

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Номер записи: 40
10-05-2012 дата публикации

Methods of manufacturing semiconductor devices

Номер: US20120115293A1
Автор: Hun-Hyeong Lim, Jin-Gyun Kim, Jin-Tae Noh, Ki-Hyun Hwang, Sang-Ryol Yang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.

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Номер записи: 41
17-05-2012 дата публикации

Memory device and method of fabricating the same

Номер: US20120119276A1
Автор: Hung Ming Tsai, Ming Cheng Chang, Ping Cheng Hsu, Sheng Wei Yang, Ying Cheng CHUANG
Принадлежит: Nanya Technology Corp

A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections.

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Номер записи: 42
17-05-2012 дата публикации

Semiconductor device and method of forming the same

Номер: US20120119278A1
Автор: Noriaki Mikasa
Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate and a first gate structure. The semiconductor substrate has a first groove and a first pillar defined by the first groove. The first groove and the first pillar are adjacent to each other. The first gate structure is disposed in the first groove. The first gate structure includes a first gate insulating film and a first gate electrode. The first gate structure is separated by a first gap from the first pillar.

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Номер записи: 43
17-05-2012 дата публикации

Semiconductor device with vertical channel transistor and method of operating the same

Номер: US20120119289A1
Автор: Daeik Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Provided is a semiconductor device including a substrate having active patterns extending between first trenches and between second trenches (the first and second trenches intersecting each other), and gate patterns disposed within the first trenches, wherein each of the active patterns includes lower and upper impurity regions, and a channel region between the lower and upper impurity regions, the lower and upper impurity regions being vertically spaced apart from each other and having a conductivity type different from the substrate, and the channel region having the same conductivity type as the substrate, and a bottom surface of the gate pattern is closer to a bottom surface of the first trench than the lower impurity region.

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Номер записи: 44
17-05-2012 дата публикации

Semiconductor memory device

Номер: US20120120706A1
Автор: Takeshi Ohgami
Принадлежит: Elpida Memory Inc

A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.

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Номер записи: 45
17-05-2012 дата публикации

Sram cell

Номер: US20120120717A1
Автор: Hanpei Koike, Toshihiro Sekigawa, Yohei Matsumoto
Принадлежит: National Institute of Advanced Industrial Science and Technology AIST

The present invention provides an SRAM cell which does not have the constraints on the size of transistors in order to realize stabilized write and read operations, which has a fewer number of control signal lines per port, and which can be easily multi-ported in the read operation as well as the write operation so that the write and read operations can be performed through a single bit line. The SRAM cell includes a feedback control transistor for controlling connection or disconnection of a positive feedback circuit between particularly two inverters, a write control transistor and a read control transistor connected to a single bit line, and a read buffer transistor connected to the read control transistor.

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Номер записи: 46
24-05-2012 дата публикации

Semiconductor device having data bus

Номер: US20120127773A1
Автор: Hisayuki Nagamine, Takamitsu Onda
Принадлежит: Elpida Memory Inc

A semiconductor device is disclosed which comprises a first wiring layer, a second wiring layer formed over the first wiring layer, data input/output terminals, and a data bus formed in the first and second wiring layers. The data bus includes N data lines transmitting data between a predetermined circuit and the input/output terminals. M first data lines among the N data lines have a length shorter than a predetermined length and residual N-M second data lines have a length longer than the predetermined length. Shield lines adjacent to the N data lines are formed in the first and second layers. The N data lines are arranged at positions at which the data lines do not overlap one another in a stacking direction of the first and second wiring layers.

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Номер записи: 47
24-05-2012 дата публикации

System comprising a semiconductor device and structure

Номер: US20120129301A1
Автор: Brian Cronquist, Deepak C. Sekar, Israel Beinglass, Paul Lim, Ze'ev Wurman, Zvi Or-Bach
Принадлежит: Monolithic 3D Inc

A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.

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Номер записи: 48
31-05-2012 дата публикации

Semiconductor device and method of forming the same

Номер: US20120132971A1
Автор: Noriaki Mikasa
Принадлежит: Elpida Memory Inc

A semiconductor device includes a semiconductor substrate having a first gate groove having first and second side walls facing to each other. A first gate insulating film covers the first and second side walls. A first gate electrode is disposed on the first gate insulating film and in a lower portion of the first gate groove. A first burying insulating film buries the first gate groove and covers the first gate electrode. A first diffusion region is adjacent to a first upper portion of the first gate insulating film. The first upper portion is positioned on an upper portion of the first side wall of the first gate groove. A second diffusion region is in contact with an upper portion of the second side wall of the first gate groove.

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Номер записи: 49
31-05-2012 дата публикации

Method for manufacturing semiconductor device

Номер: US20120135592A1
Автор: Jung Nam KIM
Принадлежит: Hynix Semiconductor Inc

A method for manufacturing a semiconductor device is disclosed, which reduces a step difference between a peripheral region and a cell region. In the semiconductor device, a metal contact of the peripheral region is configured in a multi-layered structure. Prior to forming a bit line and a storage node contact in the cell region, a contact and a line are formed in the peripheral region, such that a step difference between the cell region and the peripheral region is reduced, resulting in a reduction in parasitic capacitance between lines.

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Номер записи: 50
31-05-2012 дата публикации

Method of manufacturing semiconductor device

Номер: US20120135601A1
Автор: Bok-yeon Won, Jong-Chul Park, Sang-Sup Jeong
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing a semiconductor device including a plurality of hole patterns is disclosed. The method includes: forming a plurality of first line patterns and a plurality of first space patterns extending in a first direction; forming a plurality of second line patterns and a plurality of second space patterns extending in a second direction, on the plurality of first line patterns and the plurality of first space patterns; forming a plurality of first hole patterns where the plurality of first space patterns and the plurality of second space patterns cross each other; and forming a plurality of second hole patterns where the plurality of first line patterns and the plurality of second line patterns cross each other.

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Номер записи: 51
07-06-2012 дата публикации

1t mim memory for embedded ram application in soc

Номер: US20120139022A1
Автор: Chen-Jong Wang, Chien-Hua Huang, Chun-Yao Chen, Chung S. Wang, Kun-Lung Chen, PING Yang, Shou-Gwo Wuu, Yi-Ching Lin
Принадлежит: Individual

Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

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Номер записи: 52
14-06-2012 дата публикации

Vertical semiconductor device and method of manufacturing the same

Номер: US20120146131A1
Автор: Jeong Seob KYE
Принадлежит: Hynix Semiconductor Inc

A vertical semiconductor device includes a first active pillar vertically protruded from a semiconductor substrate; a first vertical gate connected to at least one side of the first active pillar and formed along a direction that crosses a buried bit line; and a first body line connected to at least one side of the first active pillar which is not connected to the first vertical gate.

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Номер записи: 53
14-06-2012 дата публикации

Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines

Номер: US20120146132A1
Автор: Leonard Forbes
Принадлежит: Micron Technology Inc

A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.

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Номер записи: 54
14-06-2012 дата публикации

Semiconductor Integrated Circuit and Manufacturing Method Thereof

Номер: US20120147662A1
Автор: Kenichi Osada, Masanao Yamaoka, Shigenobu Komatsu
Принадлежит: Renesas Electronics Corp

High manufacturing yield is realized and variation in threshold voltage of each MOS transistor in a CMOS·SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. Threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is programmed into control memories according to results of determination. Levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS·SRAM are controlled to a predetermined error span. Body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

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Номер записи: 55
14-06-2012 дата публикации

Semiconductor memory device

Номер: US20120147687A1
Автор: Toshiaki Douzaka
Принадлежит: Toshiba Corp

A row decoder is disposed on a side of a memory cell array in a column direction and supplies one of word lines with a first drive signal for selecting one of memory cells. A dummy word line is formed extending in the column direction. A dummy bit line is formed extending in a row direction. At least one of the dummy word line and the dummy bit line is disposed outside of the memory cell array. The row decoder outputs a second drive signal toward a sense amplifier circuit via the dummy bit line and the dummy word line.

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Номер записи: 56
14-06-2012 дата публикации

Semiconductor device manufacturing method that allows rework rate in manufacturing step to decrease

Номер: US20120149135A1
Автор: Shinji Yanagi, Takashi Sugimura
Принадлежит: Elpida Memory Inc

A semiconductor device manufacturing method includes: forming a first pattern in a first film to be processed on a semiconductor substrate; measuring a first distance, which is a dimension in a predetermined direction in the first pattern; forming a second film to be processed on the first pattern; forming a second pattern in a photoresist formed on the second film to be processed; and measuring a second distance, which is a dimension in a predetermined direction in the second pattern. Whether or not the second pattern is defective is determined based on either the first distance or a value calculated from the first and second distances.

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Номер записи: 57
21-06-2012 дата публикации

Semiconductor device and method for forming the same

Номер: US20120153381A1
Автор: Hae Il SONG
Принадлежит: Hynix Semiconductor Inc

A semiconductor device and a method for forming the same are disclosed. A method for forming a semiconductor device includes forming a trench by etching a semiconductor substrate, forming a barrier metal layer having a thickness of 100 Å or less over a surface of the trench, forming a nucleation layer over the barrier metal layer, configured to include a β-tungsten (β-W) structure, and forming a bulk layer over the nucleation layer so as to bury the bottom of the trench. As a result, resistivity can be reduced and a stable-phase barrier metal layer can be obtained. In addition, productivity is improved so that gate resistance is prevented from increasing.

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Номер записи: 58
21-06-2012 дата публикации

Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit

Номер: US20120153431A1
Автор: Andres Bryant, Brent A. Anderson, Edward J. Nowak, Herbert L. Ho
Принадлежит: International Business Machines Corp

Disclosed is an integrated circuit having at least one deep trench isolation structure and a deep trench capacitor. A method of forming the integrated circuit incorporates a single etch process to simultaneously form first trench(s) and a second trenches for the deep trench isolation structure(s) and a deep trench capacitor, respectively. Following formation of a buried capacitor plate adjacent to the lower portion of the second trench, the trenches are lined with a conformal insulator layer and filled with a conductive material. Thus, for the deep trench capacitor, the conformal insulator layer functions as the capacitor dielectric and the conductive material as a capacitor plate in addition to the buried capacitor plate. A shallow trench isolation (STI) structure formed in the substrate extending across the top of the first trench(es) encapsulates the conductive material therein, thereby creating the deep trench isolation structure(s).

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Номер записи: 59
21-06-2012 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20120153481A1
Автор: Sung Hwan Ahn
Принадлежит: Hynix Semiconductor Inc

A semiconductor device and a method for manufacturing the same are disclosed, which can prevent a short-circuit between a bit line contact plug and a storage node contact plug, resulting in improved semiconductor device characteristics. A method for manufacturing a semiconductor device includes: forming a bit line contact hole from which an active region is protruded, by etching a semiconductor substrate; forming a conductive material over the semiconductor substrate including the bit line contact hole; etching the conductive material to form a bit line contact plug and a bit line, each of which has a smaller width than the bit line contact hole; and forming a spacer insulation film over the entire surface of the semiconductor substrate including the bit line contact hole, the bit line contact plug, and the bit line.

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Номер записи: 60
21-06-2012 дата публикации

Sense amplifier structure for a semiconductor integrated circuit device

Номер: US20120154046A1
Автор: Duk Su Chun
Принадлежит: Hynix Semiconductor Inc

A semiconductor integrated circuit device includes a first signal line and a second signal line, and a sense amplifier that includes a plurality of PMOS transistors and a plurality of NMOS transistors. The sense amplifier is configured to sense amplify a potential difference between the first signal line and the second signal line. The junction regions of the NMOS and PMOS transistors having the same conductivity type, and to which the same signal is applied, are formed in one integrated active region.

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Номер записи: 61
21-06-2012 дата публикации

Method for fabricating semiconductor device with buried gate

Номер: US20120156869A1
Автор: Jong-Han Shin, Kyung-Bo Kim
Принадлежит: Hynix Semiconductor Inc

A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming an isolation layer for defining an active region by using the hard mask pattern, forming a buried gate in and across the active region and the isolation layer over the substrate, forming an inter-layer dielectric layer over the substrate, forming a storage node contact hole that exposes the hard mask pattern by selectively etching the inter-layer dielectric layer, extending the storage node contact hole to expose the active region by removing the hard mask pattern exposed under the storage node contact hole, and forming a storage node contact plug that fills the extended storage node contact hole.

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Номер записи: 62
28-06-2012 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20120161125A1
Автор: Shunpei Yamazaki
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A semiconductor device capable of high speed operation is provided. Further, a highly reliable semiconductor device is provided. An oxide semiconductor having crystallinity is used for a semiconductor layer of a transistor. A channel formation region, a source region, and a drain region are formed in the semiconductor layer. The source region and the drain region are formed in such a manner that one or more of elements selected from rare gases and hydrogen are added to the semiconductor layer by an ion doping method or an ion implantation method with the use of a channel protective layer as a mask.

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Номер записи: 63
28-06-2012 дата публикации

Rectangular capacitors for dynamic random access memory (dram) and dual-pass lithography methods to form the same

Номер: US20120161215A1
Автор: Nick Lindert
Принадлежит: Intel Corp

A rectangular capacitor for dynamic random access memory (DRAM) and a dual-pass lithography method to form the same are described. For example, a capacitor includes a trench disposed in a first dielectric layer disposed above a substrate. A cup-shaped metal plate is disposed along the bottom and sidewalls of the trench. A second dielectric layer is disposed on and conformal with the cup-shaped metal plate. A trench-fill metal plate is disposed on the second dielectric layer. The second dielectric layer isolates the trench-fill metal plate from the cup-shaped metal plate. The capacitor has a rectangular or near-rectangular shape from a top-down perspective.

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Номер записи: 64
28-06-2012 дата публикации

Semiconductor device

Номер: US20120161219A1
Автор: Kazuhiro Nojima, Kensuke Okonogi, Kiyonori Oyu
Принадлежит: Elpida Memory Inc

a semiconductor device is provided, which includes an N well having a peak concentration of 2E+17 atom/cm 3 or more in the range of 0.2 to 1 μm depth from the surface of a P-type semiconductor substrate, and a region provided below the N well, the region containing P-type impurities with higher concentration than concentration of electrons.

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Номер записи: 65
05-07-2012 дата публикации

Method for fabricating semiconductor device with buried bit lines

Номер: US20120171846A1
Автор: Eui-Seong Hwang
Принадлежит: Individual

A method for fabricating a semiconductor device includes etching a substrate to form trenches that separate active regions, forming an insulation layer having an opening to open a portion of a sidewall of each active region, forming a silicon layer pattern to gap-fill a portion of each trench and cover the opening in the insulation layer, forming a metal layer over the silicon layer pattern, and forming a metal silicide layer as buried bit lines, where the metal silicide layer is formed when the metal layer reacts with the silicon layer pattern.

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Номер записи: 66
12-07-2012 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20120175734A1
Автор: Sang Ho Sohn
Принадлежит: Hynix Semiconductor Inc

A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes adjacent storage node contact plugs having different heights, and lower-electrode bowing profiles having different heights, such that a spatial margin between the lower electrodes is assured and a bridge fail is prevented, resulting in improved device operation characteristics. The semiconductor device includes a first storage node contact plug and a second storage node contact plug formed over a semiconductor substrate, wherein the second storage node contact plug is arranged at a height different from that of the first storage node contact plug, and a lower electrode formed over the first storage node contact plug and the second storage node contact plug.

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Номер записи: 67
19-07-2012 дата публикации

Semiconductor device

Номер: US20120181660A1
Автор: Naonori Fujiwara
Принадлежит: Elpida Memory Inc

A semiconductor device comprises a capacitor, the capacitor including a lower electrode, a dielectric film containing crystalline zirconium oxide formed on the lower electrode, and an upper electrode containing a titanium nitride film contacting to the dielectric film, wherein the dielectric film comprises an amorphous film on an interface with the titanium nitride film, thereby preventing the reduction of the thickness of the titanium nitride film formed on the dielectric electrode with a low leakage current and a high dielectric constant.

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Номер записи: 68
26-07-2012 дата публикации

Semiconductor device and method for manufacturing the same

Номер: US20120187535A1
Автор: Un Hee LEE
Принадлежит: Hynix Semiconductor Inc

A semiconductor device and a method for manufacturing the same are disclosed. An additional spacer is formed at a lateral surface of an upper part of the bit line so that the distance of insulation films between a storage node and a neighboring storage node contact plug is increased. Accordingly, the distance between the storage node and the neighboring storage node contact is guaranteed and a bridge failure is prevented.

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Номер записи: 69
26-07-2012 дата публикации

Asymmetric silicon-on-insulator sram cell

Номер: US20120190159A1
Автор: Jeffrey W. Sleight, Leland Chang
Принадлежит: International Business Machines Corp

A memory cell having N transistors including at least one pair of access transistors, one pair of pull-down transistors, and one pair of pull-up transistors to form a memory cell, wherein N is an integer at least equal to six, wherein each of the access transistors and each of the pull-down transistors is a same one of an n-type or a p-type transistor, and each of the pull-up transistors is the other of an n-type or a p-type transistor, wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric.

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Номер записи: 70
09-08-2012 дата публикации

Semiconductor memory device and method for manufacturing the same

Номер: US20120199842A1
Автор: Yasuhiko Takemura
Принадлежит: Semiconductor Energy Laboratory Co Ltd

A highly integrated DRAM is provided. A bit line is formed over a first insulator, a second insulator is formed over the bit line, third insulators which are in a stripe shape and the like are formed over the second insulator, and a semiconductor region and a gate insulator are formed to cover one of the third insulators. The bit line is connected to the semiconductor region through first contact plugs. Then, a conductive film is formed and subjected to anisotropic etching to form word lines at side surfaces of the third insulators, and a second contact plug is formed to be connected to a capacitor at a top of the one of the third insulators. By synchronizing the word lines, electric charge is accumulated or released through the capacitor. With such a structure, the area of a memory cell can be 4F 2 .

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Номер записи: 71
09-08-2012 дата публикации

High Density Metal-Insulator-Metal Trench Capacitor

Номер: US20120199949A1
Автор: Clarence Chui, Evgeni P. Gousev, Je-Hsiung Lan, Jonghae Kim, Matthew Michael Nowak
Принадлежит: Qualcomm Inc

Higher capacitance density is achieved by increasing a surface area of a capacitor. A larger surface area may be obtained by forming isotropic ball shapes (a concave surface) in the trenches on the semiconductor die. The concave surfaces are fabricated by depositing bilayers of amorphous-silicon and silicon oxide. Openings are patterned in the silicon oxide hard mask for trenches. The openings are transferred to the amorphous-silicon layers through isotropic etching to form concave surfaces. Conducting, insulating, and conducting layers are deposited on the concave surfaces of the trenches by atomic layer deposition.

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Номер записи: 72
16-08-2012 дата публикации

Design Structure for High Density Stable Static Random Access Memory

Номер: US20120205721A1
Автор: Ching-Te K. Chuang, Fadi H. Gebara, Hung C. Ngo, Jente Benedict Kuang, Keunwoo Kim
Принадлежит: International Business Machines Corp

A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit includes a plurality of bit line structures, a plurality of word line structures intersecting said plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding bit line structure under control of a corresponding word line structure, each of said cells comprising a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor, wherein said at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of said bit line structures, and said at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.

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Номер записи: 73
16-08-2012 дата публикации

Semiconductor device including capacitor and double-layer metal contact and fabrication method thereof

Номер: US20120205733A1
Автор: Chun Soo Kang
Принадлежит: Hynix Semiconductor Inc

Disclosed are a semiconductor device comprising a capacitor and a double-layer metal contact and a method fabricating the same. The method comprising: forming a gate of a peripheral transistor for a peripheral circuit; forming a first contact and a first peripheral circuit wiring layer pattern on a first interlayer insulating layer; forming a second contact and a second peripheral circuit wiring layer pattern; selectively removing a portion of the second interlayer insulating layer in a cell region; forming a mold layer covering the second peripheral circuit wiring layer pattern; forming storage nodes passing through the mold layer; removing the mold layer; forming a dielectric layer and a plate node, which cover the storage nodes; forming a third interlayer insulating layer; and forming third contacts passing through the third interlayer insulating layer.

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Номер записи: 74
23-08-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120211830A1
Автор: Min Soo Yoo
Принадлежит: Hynix Semiconductor Inc

A semiconductor device and a method of fabricating the same are provided, in which a full overlap between a storage node contact and an active region to solve an overlay in an etching process and an etching width of a storage node is increased to improve a processing margin. The semiconductor device includes a main gate and a device isolation structure disposed in a semiconductor device, an isolation pattern disposed over the device isolation structure, and contact plugs disposed at each side of the isolation pattern.

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Номер записи: 75
23-08-2012 дата публикации

Method for obtaining extreme selectivity of metal nitrides and metal oxides

Номер: US20120214306A1
Автор: Kevin R. Shea
Принадлежит: Micron Technology Inc

Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H 2 F 2 . The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride. A method is provided for producing an isolated capacitor, which can be used in a dynamic random access memory cell array, on a substrate using sacrificial layers selectively removed to expose outer surfaces of the bottom electrode.

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Номер записи: 76
30-08-2012 дата публикации

Method for fabricating buried bit line in semiconductor device

Номер: US20120220120A1
Автор: Hee-Sung Kang
Принадлежит: Hynix Semiconductor Inc

A method for fabricating a buried bit line in a semiconductor device includes forming a liner oxide layer over the entire surface of a substrate having bodies isolated by a trench, selectively etching the liner oxide layer contacted with one side surface of the trench to a given depth, forming a sacrifice layer at a larger height than an etched surface of the liner oxide layer wherein the sacrifice layer partially fills the trench to the larger height, forming a liner nitride layer on sidewalls of the trench over the sacrifice layer, removing the sacrifice layer to expose a part of a body at the one side surface of the trench, forming a barrier layer along the entire surface of the resultant structure including the liner oxide layer, and forming a buried bit line over the barrier layer to be contacted with the exposed part of the body.

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Номер записи: 77
06-09-2012 дата публикации

Gated Bipolar Junction Transistors, Memory Arrays, and Methods of Forming Gated Bipolar Junction Transistors

Номер: US20120223369A1
Автор: Farid Nemati, Rajesh N. Gupta, Scott T. Robins
Принадлежит: Micron Technology Inc

Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

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Номер записи: 78
06-09-2012 дата публикации

Semiconductor device

Номер: US20120223374A1
Автор: Masaki Kondo, Tetsu Morooka
Принадлежит: Toshiba Corp

A semiconductor device according to an embodiment includes: a semiconductor region on a semiconductor substrate, an upper face and side faces of the semiconductor region forming a saddle-like shape, convex portions being formed at both ends of a region including a saddle point in the upper face; a gate insulating film on the upper face of the semiconductor region except upper faces of the convex portions, and on side faces of the convex portions on a side of the region including the saddle point in the upper face; a gate electrode on the gate insulating film and including: a main body part located immediately above the region including the saddle point in the upper face; and leg portions leading to the main body portion and covering the side faces of the semiconductor region, a length of the leg portions being greater than a length of the main body portion.

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Номер записи: 79
06-09-2012 дата публикации

Transistor with reduced charge carrier mobility and associated methods

Номер: US20120223396A1
Автор: Christian Pacha, Jörg Berthold, Klaus Von Arnim
Принадлежит: Individual

One or more embodiments relate to an apparatus comprising: a first transistor including a fin; and a second transistor including a fin, the fin of the first transistor having a lower charge carrier mobility than the fin of the second transistor.

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Номер записи: 80
06-09-2012 дата публикации

Transistor with reduced charge carrier mobility and associated methods

Номер: US20120224415A1
Автор: Christian Pacha, Jörg Berthold, Klaus Von Arnim
Принадлежит: Individual

One or more embodiments of the invention relate to a method comprising: treating a fin of a first n-channel access transistor in a static random access memory cell to have a lower charge carrier mobility than a fin of a first n-channel pull-down transistor in a first inverter in the memory cell, the first n-channel access transistor being coupled between a first bit line and a first node of the first inverter; and treating a fin of a second n-channel access transistor in the memory cell to have a lower charge carrier mobility than a fin of a second n-channel pull-down transistor in a second inverter in the memory cell, the second n-channel access transistor being coupled between a second bit line and a second node of the second inverter.

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Номер записи: 81
06-09-2012 дата публикации

Semiconductor storage device

Номер: US20120224419A1
Автор: Satoshi Inaba
Принадлежит: Toshiba Corp

A semiconductor storage device according to an embodiment includes wells in a semiconductor substrate, fins formed on the wells, gate electrodes provided on one side and another opposite side of each fin via a gate insulating film to form a channel region in the fin, impurity-diffused layers that each form a potential barrier that confines holes in a body region within the channel region, and source/drain layers each formed at the fin such that the channel region is sandwiched between the source layer and the drain layer. At the time of writing of data ‘1’, a gate voltage is set to a negative potential, a well bias voltage is set to a positive potential, and a drain voltage is set to a positive potential.

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Номер записи: 82
13-09-2012 дата публикации

Methods of fabricating a semiconductor device having metallic storage nodes

Номер: US20120231601A1
Автор: Byoung-Yong Gwak, Inseak Hwang, Mongsup Lee, Sang-Jun Lee, Sukhun Choi
Принадлежит: Individual

The present disclosure describes methods of fabricating a semiconductor device. An exemplary method includes forming a metal pattern on a substrate and etching the metal pattern using an etchant including at least an alkaline solution and an oxidant to form a metal electrode, where at least a portion of the surface of the metal electrode is uneven.

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Номер записи: 83
13-09-2012 дата публикации

Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance

Номер: US20120231626A1
Автор: Kai Wu, Sang Ho Yu, Sang-Hyeob Lee
Принадлежит: Applied Materials Inc

The invention provides a method of forming a film stack on a substrate, comprising performing a silicon containing gas soak process to form a silicon containing layer over the substrate, reacting with the silicon containing layer to form a tungsten silicide layer on the substrate, depositing a tungsten nitride layer on the substrate, subjecting the substrate to a nitridation treatment using active nitrogen species from a remote plasma, and depositing a conductive bulk layer directly on the tungsten nitride layer.

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Номер записи: 84
20-09-2012 дата публикации

High density six transistor finfet sram cell layout

Номер: US20120235240A1
Автор: Abhisek Dixit
Принадлежит: International Business Machines Corp

Dual orientation of finFET transistors in a static random access memory (SRAM) cell allows aggressive scaling to a minimum feature size of 15 nm and smaller using currently known masking techniques that provide good manufacturing yield. A preferred layout and embodiment features inverters formed from adjacent, parallel finFETs with a shared gate and different conductivity types developed through a double sidewall image transfer process while the preferred dimensions of the inverter finFETs and the pass transistors allow critical dimensions of all transistors to be sufficiently uniform despite the dual transistor orientation of the SRAM cell layout.

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Номер записи: 85
20-09-2012 дата публикации

Methods Of Forming Transistors, And Methods Of Forming Memory Arrays

Номер: US20120238061A1
Автор: Mark Fischer, Sanh D. Tang
Принадлежит: Micron Technology Inc

Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 Å/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.

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Номер записи: 86
27-09-2012 дата публикации

Semiconductor device having cell capacitors

Номер: US20120241830A1
Автор: Hiroyuki Uchiyama
Принадлежит: Elpida Memory Inc

A semiconductor device including: a bit line being arranged on top surfaces of first and second contact plugs via a first insulation layer and extending in a direction connecting a first impurity diffusion layer and a second impurity diffusion layer; a bit line contact plug being formed through the first insulation layer and electrically connecting the bit line to the first contact plug; a first cell capacitor having a first lower electrode beside one of side surfaces of the bit line; a first insulation film insulating the bit line and the first lower electrode from each other; and a first contact conductor electrically connecting a bottom end of the first lower electrode to a side surface of the second contact plug.

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Номер записи: 87
27-09-2012 дата публикации

DRAM Arrays

Номер: US20120241832A1
Автор: Mark Fischer
Принадлежит: Micron Technology Inc

The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions containing transistors with horizontally-opposing source/drain regions and channel regions between the source/drain regions. The transistors can include gates that encircle at least three-fourths of at least portions of the channel regions, and in some aspects can include gates that encircle substantially an entirety of at least portions of the channel regions.

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Номер записи: 88
04-10-2012 дата публикации

Memory device

Номер: US20120248434A1
Автор: Kiyoshi Kato, Toshihiko Saito
Принадлежит: Semiconductor Energy Laboratory Co Ltd

It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.

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Номер записи: 89
04-10-2012 дата публикации

Semiconductor memory device having plural cell capacitors stacked one another and manufacturing method thereof

Номер: US20120248520A1
Автор: Hiroyuki Uchiyama
Принадлежит: Elpida Memory Inc

Disclosed herein is a device that includes a semiconductor substrate having a first area, a plurality of cell transistors arranged on the first area of the semiconductor substrate, and a plurality of cell capacitors each coupled to an associated one of the cell transistors, the cell capacitors being provided so as to overlap with one another on the first area.

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Номер записи: 90
04-10-2012 дата публикации

Semiconductor device and method for forming the same

Номер: US20120252186A1
Автор: Young Man Cho
Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a semiconductor substrate including an active area defined by an device isolation region, a buried gate formed on both side walls of a trench formed in the semiconductor substrate, and a storage node contact which is buried between the buried gates, and is connected to the active region of a middle portion of the trench and the device isolation region.

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Номер записи: 91
11-10-2012 дата публикации

Semiconductor device for reducing interconnect pitch

Номер: US20120256243A1
Автор: Hirokazu ATOU, Hisayuki Nagamine
Принадлежит: Elpida Memory Inc

A semiconductor device includes a plurality of transistors formed on a semiconductor substrate, a first local wiring which is electrically connected to at least one of the plurality of transistors and extending in a first direction, a second local wiring which is formed above the first local wiring and which electrically connects to at least one of the plurality of transistors and extends in a second direction, a plurality of first wirings which are formed above the second local wiring and which extend in a third direction, at least each of the plurality of first wirings being electrically connected to the first local wiring and the second local wiring, respectively, and a second wiring which is formed above the first wiring and which electrically connects to at least one of the plurality of first wirings and extends in a fourth direction.

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Номер записи: 92
11-10-2012 дата публикации

Recessed gate transistor with cylindrical fins

Номер: US20120256256A1
Автор: Hsien-Wen Liu, Tieh-Chiang Wu, Yi-Nan Chen
Принадлежит: Nanya Technology Corp

A recessed gate transistor with cylindrical fins is disclosed. The recessed gate transistor is disposed in an active region of a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate to define an active region therebetween. The recessed gate transistor includes a gate structure, a source doping region and a drain doping region. The gate structure has at least three fins forms a concave and convex bottom of the gate structure. The front fin is disposed in one of the two isolation regions, the middle fin is disposed in the active region and a last fin disposed in the other one of the two isolation regions. The front fin and the last fin are both cylindrical. A lower part of the gate structure is M-shaped when view from the source doping region to the drain doping region direction.

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Номер записи: 93
11-10-2012 дата публикации

Semiconductor device and method for making same

Номер: US20120256261A1
Автор: Bruce B. Doris, Kangguo Cheng, Tenko Yamashita, Ying Zhang
Принадлежит: International Business Machines Corp

A semiconductor device including a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.

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Номер записи: 94
11-10-2012 дата публикации

Memory device comprising an array portion and a logic portion

Номер: US20120256272A1
Автор: Werner Juengling
Принадлежит: Micron Technology Inc

In an embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures.

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Номер записи: 95
25-10-2012 дата публикации

Semiconductor device with buried bit lines and method for fabricating the same

Номер: US20120267723A1
Автор: Su-Young Kim
Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes: a semiconductor substrate configured to include a plurality of trenches therein; a plurality of buried bit lines each configured to fill a portion of each trench; a plurality of active pillars each formed in an upper portion of each buried bit line; a plurality of vertical gates each configured to surround each active pillar; and a plurality of word lines configured to couple neighboring vertical gates with each other.

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Номер записи: 96
25-10-2012 дата публикации

Independently voltage controlled volume of silicon on a silicon on insulator chip

Номер: US20120267752A1
Автор: David P. Paulsen, Gregory J. Uhlmann, II John E. Sheets, Karl R. Erickson, Kelly L. Williams, Phil C. Paone
Принадлежит: International Business Machines Corp

A semiconductor chip has an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. A bottom, or floor, of the independently voltage controlled silicon region is a deep implant of opposite doping to a doping of a substrate of the independently voltage controlled silicon region. A top, or ceiling, of the independently voltage controlled silicon region is a buried oxide implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation. Voltage of the independently voltage controlled silicon region is applied through a contact structure formed through the buried oxide.

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Номер записи: 97
25-10-2012 дата публикации

Method of Fabricating Isolated Capacitors and Structure Thereof

Номер: US20120267754A1
Автор: Dominic J. Schepis, Junedong Lee, Oh-Jung Kwon, Paul C. Parries
Принадлежит: International Business Machines Corp

A structure and method is provided for fabricating isolated capacitors. The method includes simultaneously forming a plurality of deep trenches and one or more isolation trenches surrounding a group or array of the plurality of deep trenches through a SOI and doped poly layer, to an underlying insulator layer. The method further includes lining the plurality of deep trenches and one or more isolation trenches with an insulator material. The method further includes filling the plurality of deep trenches and one or more isolation trenches with a conductive material on the insulator material. The deep trenches form deep trench capacitors and the one or more isolation trenches form one or more isolation plates that isolate at least one group or array of the deep trench capacitors from another group or array of the deep trench capacitors.

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Номер записи: 98
25-10-2012 дата публикации

Capacitor structure with metal bilayer and method for using the same

Номер: US20120267757A1
Автор: Chris Carlson, Vassil Antonov, Vishwanath Bhat
Принадлежит: Nanya Technology Corp

A method for using a metal bilayer is disclosed. First, a bottom electrode is provided. Second, a dielectric layer which is disposed on and is in direct contact with the lower electrode is provided. Then, a metal bilayer which serves as a top electrode in a capacitor is provided. The metal bilayer is disposed on and is in direct contact with the dielectric layer. The metal bilayer consists of a noble metal in direct contact with the dielectric layer and a metal nitride in direct contact with the noble metal.

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Номер записи: 99
01-11-2012 дата публикации

Semiconductor device manufacturing method and semiconductor device

Номер: US20120273887A1
Автор: Hideaki Kuroda
Принадлежит: Sony Corp

A semiconductor device including a transistor formed on a first surface of a silicon layer; a first insulating film formed on the first surface of said silicon layer and covering said transistor; a wiring section formed in the first insulating film and electrically connected to the transistor; a supporting substrate formed on a surface of the first insulating film with a second insulating film interposed between the supporting substrate and the first insulating film; and an adjusting insulating film for adjusting a threshold voltage of said transistor, the adjusting insulating film being formed on a second surface of said silicon layer opposing the first surface of said silicon layer. Some embodiments may include a probing electrode electrically connected to the transistor and an opening in the silicon layer for exposing the probing electrode.

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Номер записи: 100