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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 19948. Отображено 100.
05-01-2012 дата публикации

Carbon-based memory element

Номер: US20120001142A1
Автор: Abu Sebastian, Charalampos Pozidis, Christophe P. Rossel, Daniele Caimi, Evangelos S. Eleftheriou
Принадлежит: International Business Machines Corp

One embodiment of the disclosure can provide a storage layer of a resistive memory element comprising a resistance changeable material. The resistance changeable material can include carbon. Contact layers can be provided for contacting the storage layer. The storage layer can be disposed between a bottom contact layer and a top contact layer. The resistance changeable material can be annealed at a predetermined temperature over a predetermined annealing time for rearranging an atomic order of the resistance changeable material.

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Номер записи: 1
05-01-2012 дата публикации

High-precision resistor and trimming method thereof

Номер: US20120001679A1
Автор: Antonello Santangelo, Stefania Maria Serena PRIVITERA
Принадлежит: STMICROELECTRONICS SRL

An embodiment of an electrically trimmable electronic device, wherein a resistor of electrically modifiable material is formed by a first generally strip-shaped portion and by a second generally strip-shaped portion, which extend transversely with respect to one another and are in direct electrical contact in a crossing area. The first and second portions have respective ends connected to own contact regions, coupled to a current pulse source and are made of the same material or of the same composition of materials starting from a same resistive layer of the material having electrically modifiable resistivity, for example, a phase-change material, such as a Ge—Sb—Te alloy, or polycrystalline silicon, or a metal material used for thin-film resistors. The trimming is performed by supplying a trimming current to the second portion so as to heat the crossing area and modify the resistivity thereof, without flowing longitudinally in the first portion.

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Номер записи: 2
05-01-2012 дата публикации

Methods, structures, and devices for reducing operational energy in phase change memory

Номер: US20120002465A1
Автор: Roy E. Meade
Принадлежит: Micron Technology Inc

Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material.

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Номер записи: 3
05-01-2012 дата публикации

Traffic load control in a mesh network

Номер: US20120002547A1
Автор: Gilles Picard
Принадлежит: Itron Inc

The present technology relates to protocols relative to utility meters associated with an open operational framework. More particularly, the present subject matter relates to protocol subject matter for advanced metering infrastructure, adaptable to various international standards, while economically supporting a 2-way mesh network solution in a wireless environment, such as for operating in a residential electricity meter field. The present subject matter supports meters within an ANSI standard C12.22/C12.19 system while economically supporting a 2-way mesh network solution in a wireless environment, such as for operating in a residential electricity meter field, all to permit cell-based adaptive insertion of C12.22 meters within an open framework. Cell isolation is provided through quasi-orthogonal sequences in a frequency hopping network. Additional features relate to apparatus and methodology subject matters concerning Traffic Load Control in a Mesh Network.

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Номер записи: 4
12-01-2012 дата публикации

RESTIVE MEMORY USING SiGe MATERIAL

Номер: US20120008366A1
Автор: Wei Lu
Принадлежит: Crossbar Inc

A resistive memory device includes a first electrode; a second electrode having a polycrystalline semiconductor layer that includes silicon; a non-crystalline silicon structure provided between the first electrode and the second electrode. The first electrode, second electrode and non-crystalline silicon structure define a two-terminal resistive memory cell.

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Номер записи: 5
19-01-2012 дата публикации

Vertically Fabricated BEOL Non-Volatile Two-Terminal Cross-Trench Memory Array with Two-Terminal Memory Elements and Method of Fabricating the Same

Номер: US20120012897A1
Автор: Paul Besser, Robin Cheung, Wen Zhong Kong
Принадлежит: Unity Semiconductor Corp

A non-Flash non-volatile cross-trench memory array formed using an array of trenches formed back-end-of-the-line (BEOL) over a front-end-of-the-line (FEOL) substrate includes two-terminal memory elements operative to store at least one bit of data that are formed at a cross-point of a first trench and a second trench. The first and second trenches are arranged orthogonally to each other. At least one layer of memory comprises a plurality of the first and second trenches to form a plurality of memory elements. The non-volatile memory can be used to replace or emulate other memory types including but not limited to embedded memory, DRAM, SRAM, ROM, and FLASH. The memory is randomly addressable down to the bit level and erase or block erase operation prior to a write operation are not required.

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Номер записи: 6
19-01-2012 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20120012944A1
Автор: Jae-Yun YI
Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a memory block including a transistor region and a memory region. A variable resistance layer of the memory region acts as a gate insulating layer in the transistor region.

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Номер записи: 7
26-01-2012 дата публикации

Non-Volatile Memory Element And Memory Device Including The Same

Номер: US20120018695A1
Автор: Chang-Bum Lee, Chang-Jung Kim, Dong-Soo Lee, Ji-hyun Hur, Man Chang, Myoung-Jae Lee, Seung-Ryul Lee, Young-Bae Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Example embodiments, relate to a non-volatile memory element and a memory device including the same. The non-volatile memory element may include a memory layer having a multi-layered structure between two electrodes. The memory layer may include first and second material layers and may show a resistance change characteristic due to movement of ionic species therebetween. The first material layer may be an oxygen-supplying layer. The second material layer may be an oxide layer having a multi-trap level.

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Номер записи: 8
02-02-2012 дата публикации

Memory resistor having plural different active materials

Номер: US20120026776A1
Автор: Jianhua Yang, Minxian Max Zhang, R. Stanley Williams
Принадлежит: Hewlett Packard Development Co LP

Methods and means related to memory resistors are provided. A memristor includes at least two different active materials disposed between a pair of electrodes. The active materials are selected to exhibit respective and opposite changes in electrical resistance in response to changes in oxygen ion content. The active materials are subject to oxygen ion reconfiguration under the influence of an applied electric field. An electrical resistance of the memristor is thus adjustable by way of applied programming voltages and is non-volatile between programming events.

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Номер записи: 9
02-02-2012 дата публикации

Methods of forming germanium-antimony-tellurium materials and a method of forming a semiconductor device structure including the same

Номер: US20120028410A1
Автор: Eugene P. Marsh
Принадлежит: Micron Technology Inc

A method of forming a material. The method comprises conducting an ALD layer cycle of a first metal, the ALD layer cycle comprising a reactive first metal precursor and a co-reactive first metal precursor. An ALD layer cycle of a second metal is conducted, the ALD layer cycle comprising a reactive second metal precursor and a co-reactive second metal precursor. An ALD layer cycle of a third metal is conducted, the ALD layer cycle comprising a reactive third metal precursor and a co-reactive third metal precursor. The ALD layer cycles of the first metal, the second metal, and the third metal are repeated to form a material, such as a GeSbTe material, having a desired stoichiometry. Additional methods of forming a material, such as a GeSbTe material, are disclosed, as is a method of forming a semiconductor device structure including a GeSbTe material.

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Номер записи: 10
09-02-2012 дата публикации

Programmable resistive memory cell with oxide layer

Номер: US20120032131A1
Автор: Insik Jin, Michael Xuefei Tang, Ming Sun, Nurul Amin, Philip George Pitcher, Venkatram Venkatasamy
Принадлежит: SEAGATE TECHNOLOGY LLC

Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. An electrically insulating oxide layer separates the ion conductor solid electrolyte material from the electrochemically active electrode.

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Номер записи: 11
16-02-2012 дата публикации

Method of Forming Semiconductor Device Having Self-Aligned Plug

Номер: US20120040508A1
Автор: Byoung-Jae Bae, Chul-Ho Shin, Dong-Hyun Im, Doo-Hwan Park, Gyu-Hwan OH, Ik-Soo Kim, Kyoung-Ha EOM, Sang-Sup Jeong, Sung-Lae Cho, Sung-Un Kwon
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

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Номер записи: 12
23-02-2012 дата публикации

Memory devices using a plurality of diodes as program selectors for memory cells

Номер: US20120044736A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

At least one junction diode fabricated in standard CMOS logic processes can be used as program selectors for the memory cells that can be programmed based on the directions of current flow. These memory cells are MRAM, RRAM, CBRAM, or other memory cells that have a resistive element coupled to the P terminal of the first diode and to the N terminal of a second diode. The diodes can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diodes. By applying a high voltage to a resistive element and switching the N terminal of the first diode to a low voltage while disabling the second diode, a current flows through the memory cell can change the resistance into one state. Similarly, by applying a low voltage to a resistive element and switching the P terminal of the second diode to a high voltage while disabling the first diode, a current flows through the memory cell can change the resistance into another state. The P+ active region of the diode can be isolated from the N+ active region in an N well by using dummy MOS gate, SBL, or STI isolations.

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Номер записи: 13
23-02-2012 дата публикации

One-time programmable memories using polysilicon diodes as program selectors

Номер: US20120044738A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Polysilicon diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, using electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse etc. as OTP element The diode can be constructed by P+/N+ implants on a polysilicon as a program selector. The OTP device has an OTP element coupled to a polysilicon diode. The OTP devices can be used to construct a two-dimensional OTP memory with the N-terminals of the diodes in a row connected as a wordline and the OTP elements in a column connected as a bitline. By applying a high voltage between a selected bitline and a selected wordline to turn on a diode in a selected cell for suitable duration of time, a current flows through an OTP element may change the resistance state. The cell data in the OTP memory can also be read by turning on a selected wordline and to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistivity global wordlines through conductive contact(s) or via(s).

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Номер записи: 14
23-02-2012 дата публикации

Reversible resistive memory using diodes formed in cmos processes as program selectors

Номер: US20120044747A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive memory cells that can be programmed based on magnitude, duration, voltage-limit, or current-limit of a supply voltage or current. These cells are PCM, RRAM, CBRAM, or other memory cells that have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. The memory cells can be used to construct a two-dimensional memory array with the N terminals of the diodes in a row connected as a wordline and the reversible resistive elements in a column connected as a bitline. By applying a voltage or a current to a selected bitline and to a selected wordline to turn on the diode, a selected cell can be programmed into different states reversibly based on magnitude, duration, voltage-limit, or current-limit. The data in the reversible resistive memory can also be read by turning on a selected wordline to couple a selected bitline to a sense amplifier. The wordlines may have high-resistivity local wordlines coupled to low-resistive global wordlines through conductive contact(s) or via(s).

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Номер записи: 15
23-02-2012 дата публикации

Variable resistance nonvolatile storage device and method of forming memory cell

Номер: US20120044749A1
Автор: Kazuhiko Shimakawa, Shunsaku Muraoka, Takeshi Takagi, Yoshihiko Kanzawa
Принадлежит: Panasonic Corp

A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate ( 301 ), (ii) a variable resistance element ( 309 ) having: lower and upper electrodes ( 309 a, 309 c ); and a variable resistance layer ( 309 b ) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes ( 309 a, 309 c ), and (iii) a MOS transistor ( 317 ) formed on the substrate ( 301 ), wherein the variable resistance layer ( 309 b ) includes: oxygen-deficient transition metal oxide layers ( 309 b - 1, 309 b - 2 ) having compositions MO x and MO y (where x<y) and in contact with the electrodes ( 309 a, 309 c ) respectively, and a diffusion layer region ( 302 b ) is connected with the lower electrode ( 309 a ) to form a memory cell ( 300 ), the region ( 302 b ) serving as a drain of the transistor ( 317 ) upon application of a voltage signal which causes a resistance change to high resistance state in the variable resistance layer ( 309 b ).

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Номер записи: 16
23-02-2012 дата публикации

Programmably reversible resistive device cells using cmos logic processes

Номер: US20120044753A1
Автор: Shine C. Chung
Принадлежит: Chung Shine C

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for reversible resistive devices, such as PCM, RRAM, CBRAM, or other memory cells. The reversible resistive devices have a reversible resistive element coupled to a diode. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a voltage or a current between a reversible resistive element and the N terminal of a diode, the reversible resistive device can be programmed into different states based on magnitude, duration, voltage-limit, or current-limit in a reversible manner. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations.

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Номер записи: 17
08-03-2012 дата публикации

Methods for adjusting the conductivity range of a nanotube fabric layer

Номер: US20120056149A1
Автор: C. Rinn Cleavelin, Darlene Hamilton, Feng Gu, H. Montgomery Manning, Thomas Rueckes
Принадлежит: Nantero Inc

Methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer are disclosed. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via wet chemistry techniques. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via plasma treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via CVD treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via an inert ion gas implant.

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Номер записи: 18
15-03-2012 дата публикации

Multi-level resistance change memory

Номер: US20120063193A1
Автор: Reika Ichihara
Принадлежит: Individual

According to one embodiment, a multi-level resistance change memory includes a memory cell includes first and second resistance change films connected in series, and a capacitor connected in parallel to the first resistance change film, a voltage pulse generating circuit generating a first voltage pulse with a first pulse width to divide a voltage of the first voltage pulse into the first and second resistance change films based on a resistance ratio thereof, and generating a second voltage pulse with a second pulse width shorter than the first pulse width to apply a voltage of the second voltage pulse to the second resistance change film by a transient response of the capacitor, and a control circuit which is stored multi-level data to the memory cell by using the first and second voltage pulses in a writing.

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Номер записи: 19
15-03-2012 дата публикации

Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same

Номер: US20120063194A1
Автор: Chul-woo Park, Hak-soo Yu, Hong-Sun Hwang, In-Gyu Baek
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

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Номер записи: 20
22-03-2012 дата публикации

Reactive metal implated oxide based memory

Номер: US20120069624A1
Автор: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu
Принадлежит: Micron Technology Inc

Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide.

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Номер записи: 21
29-03-2012 дата публикации

Electronic Devices, Memory Devices and Memory Arrays

Номер: US20120074373A1
Автор: D.V. Nirmal Ramaswamy, Kirk D. Prall
Принадлежит: Individual

Some embodiments include electronic devices having two capacitors connected in series. The two capacitors share a common electrode. One of the capacitors includes a region of a semiconductor substrate and a dielectric between such region and the common electrode. The other of the capacitors includes a second electrode and ion conductive material between the second electrode and the common electrode. At least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Some embodiments include memory cells having two capacitors connected in series, and some embodiments include memory arrays containing such memory cells.

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Номер записи: 22
29-03-2012 дата публикации

Conductive path in switching material in a resistive random access memory device and control

Номер: US20120074374A1
Автор: Sung Hyun Jo
Принадлежит: Crossbar Inc

A non-volatile memory device structure. The device structure includes a first electrode, a second electrode, a resistive switching material comprising an amorphous silicon material overlying the first electrode, and a thickness of dielectric material having a thickness ranging from 5 nm to 10 nm disposed between the second electrode and the resistive switching layer. The thickness of dielectric material is configured to electrically breakdown in a region upon application of an electroforming voltage to the second electrode. The electrical breakdown allows for a metal region having a dimension of less than about 10 nm by 10 nm to form in a portion of the resistive switching material.

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Номер записи: 23
29-03-2012 дата публикации

Vertical transistor with hardening implatation

Номер: US20120074488A1
Автор: Chulmin Jung, Dadi Setiadi, Hyung-Kyu Lee, Maroun Georges Khoury, Peter Nicholas Manos, Young Pil Kim
Принадлежит: SEAGATE TECHNOLOGY LLC

A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.

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Номер записи: 24
29-03-2012 дата публикации

Resistor structure for a non-volatile memory device and method

Номер: US20120075907A1
Автор: Sung Hyun Jo
Принадлежит: Crossbar Inc

A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and a resistance substantially the same as an on state resistance of the switching device. The resistive material allows for a change in a resistance of the switching material upon application of voltage pulse without time delay and free of a reverse bias after the voltage pulse. The first voltage pulse causes a programming current to flow from the second electrode to the first electrode. The resistive material further causes the programming current to be no greater than a predetermined value.

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Номер записи: 25
05-04-2012 дата публикации

Phase change memory apparatus having row control cell

Номер: US20120081954A1
Автор: Kyoung Wook Park
Принадлежит: Hynix Semiconductor Inc

A semiconductor integrated circuit includes a phase change memory apparatus includes a plurality of row control cells and a plurality of phase change memory cells formed on the row control cells while being electrically connected to the row control cells. The plurality of row control cells and the plurality of phase change memory cells are vertically stacked in a cell array area.

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Номер записи: 26
12-04-2012 дата публикации

ATOMIC LAYER DEPOSITION OF CRYSTALLINE PrCaMnO (PCMO) AND RELATED STRUCTURES AND METHODS

Номер: US20120086104A1
Автор: Eugene P. Marsh
Принадлежит: Micron Technology Inc

Methods of forming a PrCaMnO (PCMO) material by atomic layer deposition. The methods include separately exposing a surface of a substrate to a manganese-containing precursor, an oxygen-containing precursor, a praseodymium-containing precursor and a calcium-containing precursor. The resulting PCMO material is crystalline. A semiconductor device structure including the PCMO material, and related methods, are also disclosed.

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Номер записи: 27
12-04-2012 дата публикации

Semiconductor device and structure

Номер: US20120088367A1
Автор: Deepak C. Sekar, Zvi Or-Bach
Принадлежит: Monolithic 3D Inc

A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate; preparing a first monocrystalline layer comprising semiconductor regions; preparing a second monocrystalline layer comprising semiconductor regions overlying the first monocrystalline layer; and etching portions of said first monocrystalline layer and portions of said second monocrystalline layer as part of forming at least one transistor on said first monocrystalline layer.

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Номер записи: 28
19-04-2012 дата публикации

Phase Change Material for a Phase Change Memory Device and Method for Adjusting the Resistivity of the Material

Номер: US20120091416A1
Автор: Hendrikus Jan Wondergem, Michael Antoine Armand In &#39;T Zandt, Robertus Adrainus Maria Wolters
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A phase change material for use in a phase change memory device comprises germanium-antimony-tellurium-indium, wherein the phase change material comprises in total more than 30 at % antimony, preferably 5-16 at % germanium, 30-60 at % antimony, 25-51 at % tellurium, and 2-33% at % indium.

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Номер записи: 29
19-04-2012 дата публикации

Non-volatile memory device and methods for manufacturing the same

Номер: US20120091424A1
Автор: Chrong-Jung Lin, Ya-Chin King
Принадлежит: Individual

A variable and reversible resistive element includes a transition metal oxide layer, a bottom electrode and at least one conductive plug module. The bottom electrode is disposed under the transition metal oxide layer. The conductive plug module is disposed on the transition metal oxide layer. The conductive plug module includes a metal plug and a barrier layer. The conductive plug is electrically connected with the transition metal oxide layer. The barrier layer surrounds the metal plug, wherein the transition metal oxide layer is made by reacting a portion of a dielectric layer being directly below the metal plug and a portion of the barrier layer contacting the portion of the dielectric layer, wherein the dielectric layer is formed on the bottom electrode. Moreover, a non-volatile memory device and methods for operating and manufacturing the same is disclosed in specification.

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Номер записи: 30
19-04-2012 дата публикации

Resistive Memory Element and Use Thereof

Номер: US20120092920A1
Автор: Sakyo Hirose
Принадлежит: Murata Manufacturing Co Ltd

A resistive memory element that includes an element body and at least a pair of electrodes opposed to each other with at least a portion of the element body interposed therebetween. The element body is made of an oxide semiconductor which has a composition represented by the general formula: (Ba 1-x Sr x )Ti 1-y M y O 3 (wherein M is at least one from among Mn, Fe, and Co; 0≦x≦1.0; and 0.005≦y≦0.05). The first electrode of the pair of electrodes is made of a material which can form a Schottky barrier which can develop a rectifying property and resistance change characteristics in an interface region between the first electrode and the element body. The second electrode is made of a material which provides a more ohmic junction to the element body as compared with the first electrode.

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Номер записи: 31
26-04-2012 дата публикации

Integrated Circuitry Comprising Nonvolatile memory Cells And Methods Of Forming A Nonvolatile Memory Cell

Номер: US20120097913A1
Автор: John K. Zahurak, Jun Liu
Принадлежит: Individual

An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed.

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Номер записи: 32
26-04-2012 дата публикации

Nonvolatile memory device and manufacturing method thereof

Номер: US20120097915A1
Автор: Atsushi Himeno, Takumi Mikawa, Yoshio Kawashima
Принадлежит: Panasonic Corp

There are provided a resistance variable nonvolatile memory device which changes its resistance stably at low voltages and is suitable for a miniaturized configuration, and a manufacturing method thereof. The nonvolatile memory device comprises: a substrate ( 100 ); a first electrode ( 101 ); an interlayer insulating layer ( 102 ); a memory cell hole ( 103 ) formed in the interlayer insulating layer; a first resistance variable layer ( 104 a ) formed in at least a bottom portion of the memory cell hole and connected to the first electrode; a second resistance variable layer ( 104 b ) formed inside the memory cell hole ( 103 ) and located on the first resistance variable layer ( 104 a ); and a second electrode ( 105 ); the first resistance variable layer ( 104 a ) and the second resistance variable layer ( 104 b ) respectively comprising metal oxides of the same kind; and the first resistance variable layer ( 104 a ) having a higher oxygen content than the second resistance variable layer ( 104 b ).

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Номер записи: 33
26-04-2012 дата публикации

Cross point variable resistance nonvolatile memory device

Номер: US20120099367A1
Автор: Kazuhiko Shimakawa, Ryotaro Azuma
Принадлежит: Panasonic Corp

A cross point variable resistance nonvolatile memory device includes memory cells having the same orientation for stable characteristics of all layers. Each memory cell ( 51 ) is placed at a different one of cross points of bit lines ( 53 ) in an X direction and word lines ( 52 ) in a Y direction formed in layers. In a multilayer cross point structure where vertical array planes sharing the word lines are aligned in the Y direction each for a group of bit lines aligned in a Z direction, even and odd layer bit line selection switch elements ( 57, 58 ) switch electrical connection and disconnection between a global bit line ( 56 ) and commonly-connected even layer bit lines and commonly-connected odd layer bit lines, respectively. A bidirectional current limiting circuit ( 92 ) having parallel-connected P-type current limiting element ( 91 ) and N-type current limiting element ( 90 ) is provided between the global bit line and the switch elements.

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Номер записи: 34
03-05-2012 дата публикации

Memristive Device

Номер: US20120104342A1
Автор: Alexandre M. Bratkovski, Jianhua Yang, Qiangfei Xia
Принадлежит: Hewlett Packard Development Co LP

A memristive device includes a first electrode, a second electrode crossing the first electrode at a non-zero angle, and an active region disposed between the first and second electrodes. The active region has a controlled defect profile throughout its thickness.

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Номер записи: 35
03-05-2012 дата публикации

Method for obtaining smooth, continuous silver film

Номер: US20120108030A1
Автор: Scott Brad Herner
Принадлежит: Crossbar Inc

A method for forming a semiconductor device including a resistive memory cell includes providing a substrate having an upper surface. A first conductive layer is formed over the upper surface of the substrate. An amorphous silicon layer is formed over the first conductive layer. A surface of the amorphous silicon layer is cleaned to remove native oxide formed on the surface of the amorphous silicon layer. A silver layer is deposited over the amorphous silicon layer after removing the native oxide by performing the cleaning step. The resistive memory cell includes the first conductive layer, the amorphous silicon layer, and the second conductive layer. The surface of the amorphous silicon layer is cleaned to prevent silver agglomeration on the native oxide.

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Номер записи: 36
10-05-2012 дата публикации

Method to reduce a via area in a phase change memory cell

Номер: US20120115302A1
Автор: Alejandro G. Schrott, Chung H. Lam, Eric A. Joseph, Matthew J. Breitwisch, Yu Zhu
Принадлежит: International Business Machines Corp

A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer.

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Номер записи: 37
17-05-2012 дата публикации

Forming Heaters for Phase Change Memories

Номер: US20120121864A1
Автор: Carla Maria Lazzari, Silvia Borsari
Принадлежит: Individual

A heater for a phase change memory may be formed by depositing a first material into a trench such that the material is thicker on the side wall than on the bottom of the trench. In one embodiment, because the trench side walls are of a different material than the bottom, differential deposition occurs. Then a heater material is deposited thereover. The heater material may react with the first material at the bottom of the trench to make Ohmic contact with an underlying metal layer. As a result, a vertical heater may be formed which is capable of making a small area contact with an overlying chalcogenide material.

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Номер записи: 38
24-05-2012 дата публикации

Upwardly Tapering Heaters for Phase Change Memories

Номер: US20120126196A1
Автор: Federico Pio
Принадлежит: Individual

A substantially planar heater for a phase change memory may taper as it extends upwardly to contact a chalcogenide layer. As a result, the contact area between heater and chalcogenide is reduced. This reduced contact area can reduce power consumption in some embodiments.

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Номер записи: 39
24-05-2012 дата публикации

Thermally insulated phase material cells

Номер: US20120129313A1
Автор: Alejandro G. Schrott, Bipin Rajendran, Chung H. Lam, Eric A. Joseph, Matthew J. Breitwisch, Roger W. Cheek, Yu Zhu
Принадлежит: International Business Machines Corp

A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.

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Номер записи: 40
07-06-2012 дата публикации

Programmable metallization memory cell with planarized silver electrode

Номер: US20120142169A1
Автор: DeXin Wang, Dimitar V. Dimitrov, Ivan Petrov Ivanov, Ming Sun, Muralikrishnan Balakrishnan, Venugopalan Vaithyanathan, WEI Tian, Yang Dong
Принадлежит: SEAGATE TECHNOLOGY LLC

Programmable metallization memory cells having a planarized silver electrode and methods of forming the same are disclosed. The programmable metallization memory cells include a first metal contact and a second metal contact, an ion conductor solid electrolyte material is between the first metal contact and the second metal contact, and either a silver alloy doping electrode separates the ion conductor solid electrolyte material from the first metal contact or the second metal contact, or a silver doping electrode separates the ion conductor solid electrolyte material from the first metal contact. The silver electrode includes a silver layer and a metal seed layer separating the silver layer from the first metal contact.

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Номер записи: 41
14-06-2012 дата публикации

Continuous mesh three dimensional non-volatile storage with vertical select devices

Номер: US20120147644A1
Автор: Roy E. Scheuerlein
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

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Номер записи: 42
14-06-2012 дата публикации

Three dimensional non-volatile storage with multi block row selection

Номер: US20120147689A1
Автор: Roy E. Scheuerlein, Tianhong Yan
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

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Номер записи: 43
14-06-2012 дата публикации

Confined resistance variable memory cell structures and methods

Номер: US20120149146A1
Автор: Brenda D. Kraus, Eugene P. Marsh, Timothy A. Quick
Принадлежит: Micron Technology Inc

Confined resistance variable memory cell structures and methods are described herein. One or more methods of forming a confined resistance variable memory cell structure includes forming a via in a memory cell structure and forming a resistance variable material in the via by performing a process that includes providing a germanium amidinate precursor and a first reactant to a process chamber having the memory cell structure therein and providing an antimony ethoxide precursor and a second reactant to the process chamber subsequent to removing excess germanium.

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Номер записи: 44
14-06-2012 дата публикации

Schottky diode switch and memory units containing the same

Номер: US20120149183A1
Автор: Dadi Setiadi, Insik Jin, Nurul Amin, Venugopalan Vaithyanathan, WEI Tian, Young Pil Kim
Принадлежит: SEAGATE TECHNOLOGY LLC

A switching element that includes a first semiconductor layer, the first semiconductor layer having a first portion and a second portion; a second semiconductor layer, the second semiconductor layer having a first portion and a second portion; an insulating layer disposed between the first semiconductor layer and the second semiconductor layer; a first metal contact in contact with the first portion of the first semiconductor layer forming a first junction and in contact with the first portion of the second semiconductor layer forming a second junction; a second metal contact in contact with the second portion of the first semiconductor layer forming a third junction and in contact with the second portion of the second semiconductor layer forming a fourth junction, wherein the first junction and the fourth junction are Schottky contacts, and the second junction and the third junction are ohmic contacts.

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Номер записи: 45
14-06-2012 дата публикации

Method for manufacturing integrated circuit device

Номер: US20120149195A1
Автор: Takuji Kuniya
Принадлежит: Toshiba Corp

According to one embodiment, a method for manufacturing an integrated circuit device, includes etching a metal member using a gas including a halogen, forming a silicon oxide film so as to cover an etching face of the etched metal member without exposing the metal member to atmospheric air, and removing the silicon oxide film.

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Номер записи: 46
21-06-2012 дата публикации

Semiconductor device having resistive device

Номер: US20120153247A1
Автор: Ja Chun Ku, Jin Hyock KIM, Seung Beom Baek, Young Ho Lee
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device includes a plurality of word lines vertically formed on a surface of a semiconductor substrate, where each pair of the plurality of word lines form a set of word lines, a bit line formed parallel to the surface of the semiconductor substrate and disposed in plurality stacked between the word lines of each pair constituting the one set of word lines, and unit memory cells disposed between respective ones of the bit lines and an adjacent one of the pair of word lines of said one of the word line sets.

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Номер записи: 47
21-06-2012 дата публикации

Highly integrated phase change memory device having micro-sized diodes and method for manufacturing the same

Номер: US20120156853A1
Автор: Jun Hyung PARK, Ki Sung Kwon
Принадлежит: Hynix Semiconductor Inc

A highly integrated phase change memory device and a method for manufacturing the same is disclosed. The highly integrated phase change memory device includes a semiconductor substrate having a cell area and a peripheral area with impurity regions formed in the cell area and extending in parallel to each other in a first direction to form a striped pattern. A gate electrode is formed in the peripheral area and dummy gate electrodes are formed in the cell area and extending in a second direction perpendicular to the first direction of the impurity regions. An interlayer dielectric layer pattern exposes portions of the cell area and the peripheral area and a PN diode is formed in a space defined by a pair of dummy gate electrodes and a pair of interlayer dielectric layer patterns.

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Номер записи: 48
28-06-2012 дата публикации

Phase change memory and method for fabricating the same

Номер: US20120161092A1
Автор: Fumitake Mieno, Youfeng He
Принадлежит: Semiconductor Manufacturing International Beijing Corp

The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC. A top of P-type conductive region is flush with a top of the peripheral substrate. The N-type conductive region containing SiC reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory.

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Номер записи: 49
28-06-2012 дата публикации

3d semiconductor memory device and manufacturing method thereof

Номер: US20120161094A1
Автор: Ming Liu, Zongliang Huo
Принадлежит: Chinese Academy of Science Institute of Microelectronics

The present application discloses a 3D semiconductor memory device having 1T1R memory configuration based on a vertical-type gate-around transistor, and a manufacturing method thereof. A on/off current ratio can be well controlled by changing a width and a length of a channel of the gate-around transistor, so as to facilitate multi-state operation of the 1T1R memory cell. Moreover, the vertical transistor has a smaller layout size than a horizontal transistor, so as to reduce the layout size effectively. Thus, the 3D semiconductor memory device can be integrated into an array with a high density.

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Номер записи: 50
09-08-2012 дата публикации

Polysilicon emitter bjt access device for pcram

Номер: US20120199806A1
Автор: Bipin Rajendran, Chung H. Lam, Tak H. Ning
Принадлежит: International Business Machines Corp

A resistive non-volatile memory cell with a bipolar junction transistor (BJT) access device formed in conjunction with the entire memory cell. The memory cell includes a substrate acting as a collector, a semiconductor base layer acting as a base, and a semiconductor emitter layer acting as an emitter. Additionally, metal plugs and the phase change memory element are formed above the BJT access device while the emitter, metal plugs, and phase change memory element are contained within an insulating region. In one embodiment of the invention, a spacer layer is formed and the emitter layer is contained within the protective spacer layer. The spacer layer is contained within the insulating region.

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Номер записи: 51
09-08-2012 дата публикации

Method of fabrication of the memristive device

Номер: US20120202334A1
Автор: Vladimir Kochergin
Принадлежит: Individual

Three-dimensionally spatially localized artificial filament in the active layer of the memristive device formed by means of ion implantation through the top electrode structure provide the means to achieve high repeatability and high reliability of the memristive devices, leading to significantly improved manufacturing yield. The memristive devices fabricated according to the disclosed method of fabrication can be used in data storage, signal processing and sensing applications.

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Номер записи: 52
23-08-2012 дата публикации

Memory apparatus

Номер: US20120212994A1
Автор: Chieko Nakashima, Hiroshi Yoshihara, Kentaro Ogata, Makoto Kitagawa, Tomohito Tsushima, Tsunenori Shiimoto
Принадлежит: Sony Corp

A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.

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Номер записи: 53
30-08-2012 дата публикации

Forming a Phase Change Memory With an Ovonic Threshold Switch

Номер: US20120220099A1
Автор: Charles H. Dennison
Принадлежит: Dennison Charles H

A phase change memory may include an ovonic threshold switch formed over an cyanic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.

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Номер записи: 54
06-09-2012 дата публикации

Electroforming-free nanoscale switching device

Номер: US20120223286A1
Автор: Alexandre Bratkovski, Gilberto Ribeiro, Jianhua Yang, R. Stanley Williams, Shih-Yuan Wang
Принадлежит: Hewlett Packard Development Co LP

A nanoscale switching device is constructed such that an electroforming process is not needed to condition the device for normal switching operations. The switching device has an active region disposed between two electrodes. The active region has at least one switching layer formed of a switching material capable of transporting dopants under an electric field, and at least one conductive layer formed of a dopant source material containing dopants that can drift into the switching layer under an electric field. The switching layer has a thickness about 6 nm or less.

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Номер записи: 55
06-09-2012 дата публикации

Methods for increasing bottom electrode performance in carbon-based memory devices

Номер: US20120223414A1
Автор: April D. Schricker, Er-Xuan Ping
Принадлежит: SanDisk 3D LLC

In some aspects, a method of forming a reversible resistance-switching metal-insulator-metal (“MIM”) stack is provided, the method including: forming a first conducting layer comprising a titanium nitride material having between about 50% Ti and about 95% Ti, forming a carbon nano-tube (CNT) material above the first conducting layer, forming a second conducting layer above the CNT material, and etching the first conducting layer, CNT material and second conducting layer to form the MIM stack. Numerous other aspects are provided.

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Номер записи: 56
06-09-2012 дата публикации

High density low power nanowire phase change material memory device

Номер: US20120225527A1
Автор: Bruce G. Elmegreen, Dennis M. Newns, Lia Krusin-Elbaum, Robert L. Sandstrom
Принадлежит: International Business Machines Corp

A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction.

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Номер записи: 57
13-09-2012 дата публикации

Memory Cell Constructions, and Methods for Fabricating Memory Cell Constructions

Номер: US20120228573A1
Автор: JIAN Li, Jun Liu
Принадлежит: Micron Technology Inc

Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals.

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Номер записи: 58
13-09-2012 дата публикации

Programmable phase-change memory and method therefor

Номер: US20120230100A1
Автор: Hans Boeve, Karen Attenborough, Niek Lambert, Victor Van Acht
Принадлежит: Individual

A non-volatile memory is disclosed. A contiguous layer of phase change material is provided. Proximate the contiguous layer of phase change material is provided a first pair of contacts for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing heating thereof within a first region. Also adjacent the contiguous layer is provided a second pair of contacts disposed for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing heating thereof within a second region thereof, the second region different from the first region.

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Номер записи: 59
20-09-2012 дата публикации

Phase-change material and phase-change type memory device

Номер: US20120235110A1
Автор: Junichi Koike, Toshiya Kamada, Yuji Sutou, Yuta Saito
Принадлежит: Tohoku University NUC

A phase-change material, which has a high crystallization temperature and is superior in thermal stability of the amorphous phase, which has a composition of the general chemical formula Ge x M y Te 100-x-y wherein M indicates one type of element which is selected from the group which comprises Al, Si, Cu, In, and Sn, x is 5.0 to 50.0 (at %) and y is 4.0 to 45.0 (at %) in range, and x and y are selected so that 40 (at %)≦x+y≦60 (at %). This phase-change material further contains, as an additional element L, at least one type of element L which is selected from the group which comprises N, O, Al, Si, P, Cu, In, and Sn in the form of Ge x M y L z Te 100-x-y-z wherein z is selected so that 40 (at %)≦x+y+z≦60 (at %).

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Номер записи: 60
20-09-2012 дата публикации

Methods Of Forming Transistors, And Methods Of Forming Memory Arrays

Номер: US20120238061A1
Автор: Mark Fischer, Sanh D. Tang
Принадлежит: Micron Technology Inc

Some embodiments include methods of forming vertical transistors. A construction may have a plurality of spaced apart fins extending upwardly from a semiconductor substrate. Each of the fins may have vertical transistor pillars, and each of the vertical transistor pillars may have a bottom source/drain region location, a channel region location over the bottom source/drain region location, and a top source/drain region location over the channel region location. Electrically conductive gate material may be formed along the fins while using oxide within spaces along the bottoms of the fins to offset the electrically conductive gate material to be above the bottom source/drain region locations of the vertical transistor pillars. The oxide may be an oxide which etches at a rate of at least about 100 Å/minute with dilute HF at room temperature. In some embodiments the oxide may be removed after the electrically conductive gate material is formed.

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Номер записи: 61
27-09-2012 дата публикации

Nonvolatile memory device

Номер: US20120241707A1
Автор: Kensuke Takahashi
Принадлежит: Toshiba Corp

According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, and a pillar. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction. The pillar is disposed between each of the word lines and each of the bit lines. The pillar includes a current selection film and a plurality of variable resistance films stacked on the current selection film. One variable resistance film includes a metal and either oxygen or nitrogen. Remainder of the variable resistance films include the metal, either oxygen or nitrogen, and a highly electronegative substance having electronegativity higher than electronegativity of the metal. A concentration of highly electronegative substance in the remainder of the variable resistance films is different among the variable resistance films.

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Номер записи: 62
27-09-2012 дата публикации

Fabrication of RRAM Cell Using CMOS Compatible Processes

Номер: US20120241710A1
Автор: Chee Mang NG, Kin-Leong Pey, Nagarajan Raghavan, Wenhu Liu
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD, NANYANG TECHNOLOGICAL UNIVERSITY

Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode. A method of making a resistance random access memory device is disclosed that includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device.

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Номер записи: 63
27-09-2012 дата публикации

Memory device

Номер: US20120243292A1
Автор: Akira Takashima, Daisuke Matsushita, Hidenori Miyagawa, Takashi Yamauchi, Yuuichi Kamimuta
Принадлежит: Individual

According to one embodiment, a memory device includes a first electrode including a crystallized Si x Ge 1-x layer (0≦x<1), a second electrode including a metal element, a variable resistance part between the first and second electrode, the part including an amorphous Si layer, and a control circuit controlling a filament in the amorphous Si layer, the filament including the metal element.

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Номер записи: 64
04-10-2012 дата публикации

Resistive switching in memory cells

Номер: US20120248396A1
Автор: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu
Принадлежит: Micron Technology Inc

Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a resistive switching region of a memory cell can include forming a metal oxide material on an electrode and forming a metal material on the metal oxide material, wherein the metal material formation causes a reaction that results in a graded metal oxide portion of the memory cell.

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Номер записи: 65
04-10-2012 дата публикации

Variable resistance element and manufacturing method thereof

Номер: US20120252184A1
Автор: Takeki Ninomiya, Takumi Mikawa, Yoshio Kawashima, Yukio Hayakawa
Принадлежит: Panasonic Corp

A variable resistance element comprises, when M is a transition metal element, O is oxygen, and x and y are positive numbers satisfying y>x; a lower electrode; a first oxide layer formed on the lower electrode and comprising MO x when a content ratio of O with respect to M is x; a second oxide layer formed on the first oxide layer and comprising MO y when a content ratio of O with respect to M is y; an upper electrode formed on the second oxide layer; a protective layer formed on the upper electrode and comprising an electrically conductive material having a composition different from a composition of the upper electrode; an interlayer insulating layer formed to cover the protective layer; and an upper contact plug formed inside an upper contact hole penetrating the interlayer insulating layer.

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Номер записи: 66
04-10-2012 дата публикации

Semiconductor Device and Method of Manufacturing the Same

Номер: US20120252187A1
Автор: Dong-Hyun Im, Dong-Hyun Kim, Gyu-Hwan OH, Kyung-min Chung
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other , forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.

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Номер записи: 67
11-10-2012 дата публикации

Closed loop sputtering controlled to enhance electrical characteristics in deposited layer

Номер: US20120256155A1
Автор: Pragati Kumar, Prashant Phatak, Tony Chiang, Wayne French
Принадлежит: Intermolecular Inc

This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of an electrical property as a function of cathode voltage used during a sputtering process. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials, be fabricated to have minimal leakage or “off” current characteristics (I leak or I off , respectively) or a maximum ratio of “on” current to “off” current (I on /I off ).

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Номер записи: 68
18-10-2012 дата публикации

Arrays Of Nonvolatile Memory Cells And Methods Of Forming Arrays Of Nonvolatile Memory Cells

Номер: US20120262973A1
Автор: Jun Liu
Принадлежит: Individual

An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed.

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Номер записи: 69
25-10-2012 дата публикации

Semiconductor device and its manufacturing method

Номер: US20120268981A1
Автор: Fumihiko Nitta, Nozomu Matsuzaki, Satoru Hanzawa, Toshihiro Tanaka
Принадлежит: Renesas Electronics Corp

In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

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Номер записи: 70
01-11-2012 дата публикации

Semiconductor storage device

Номер: US20120273742A1
Автор: Hiroyuki Minemura, Yumiko Anzai
Принадлежит: HITACHI LTD

An intermediate layer including at least one of elements constituting a phase change material and silicon is arranged between a recording layer composed of the phase change material and an n + polysilicon film to reduce contact resistance between the recording layer and the n + polysilicon film, thereby simplifying the structure of a phase change memory and reducing the cost thereof. If the phase change material contains Ge, Sb, and Te, for example, the intermediate layer includes at least one of Si—Sb, Si—Te, and Si—Ge.

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Номер записи: 71
01-11-2012 дата публикации

Nonvolatile semiconductor memory device

Номер: US20120273743A1
Автор: Hiroyuki Fukumizu, Kenichi Ootsuka, Masayuki Takata, Shuichi Kuboi, Tsukasa Nakai, Yasuhiro Nojiri
Принадлежит: Toshiba Corp

A nonvolatile semiconductor memory device includes: a first interconnect; a second interconnect at a position opposing the first interconnect; and a variable resistance layer between the first interconnect and the second interconnect, the variable resistance layer being capable of reversibly changing between a first state and a second state by a voltage applied via the first interconnect and the second interconnect or a current supplied via the first interconnect and the second interconnect, the first state having a first resistivity, the second state having a second resistivity higher than the first resistivity. Wherein the variable resistance layer has a compound of carbon and silicon as a main component and including hydrogen.

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Номер записи: 72
01-11-2012 дата публикации

Semiconductor cell and method for forming the same

Номер: US20120273919A1
Автор: Song Hyeuk Im
Принадлежит: Hynix Semiconductor Inc

A semiconductor cell includes storage node contact plugs disposed on a semiconductor substrate, a bit line formation area which is disposed between the storage node contact plugs and exposes the semiconductor substrate, and an air gap which is in contact with a lower portion of a sidewall of the bit line formation area and extends in a direction perpendicular to a direction in which the bit line formation area extends. Therefore, the coupling effect between adjacent bit lines as well as the coupling effect caused between adjacent storage node contact plugs and the coupling effect caused between the storage node contact plug and the bit line are controlled to improve characteristics of semiconductor devices.

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Номер записи: 73
08-11-2012 дата публикации

Variable resistance nonvolatile storage device

Номер: US20120281453A1
Автор: Kazuhiko Shimakawa, Satoru Mitani, Shunsaku Muraoka, Yoshihiko Kanzawa
Принадлежит: Kazuhiko Shimakawa, Satoru Mitani, Shunsaku Muraoka, Yoshihiko Kanzawa

The variable resistance nonvolatile storage device includes a memory cell ( 300 ) that is formed by connecting in series a variable resistance element ( 309 ) including a variable resistance layer ( 309 b ) which reversibly changes based on electrical signals each having a different polarity and a transistor ( 317 ) including a semiconductor substrate ( 301 ) and two N-type diffusion layer regions ( 302 a, 302 b ), wherein the variable resistance layer ( 309 b ) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes ( 309 a, 309 c ) are made of materials of different elements, a standard electrode potential V 1 of the lower electrode ( 309 a ), a standard electrode potential V 2 of the upper electrode ( 309 c ), and a standard electrode potential V t of the transition metal satisfy V t <V 2 and V 1 <V 2 , and the lower electrode ( 309 a ) is connected with the N-type diffusion layer region ( 302 b ), the electrical signals being applied between the lower and upper electrodes ( 309 a, 309 c ).

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Номер записи: 74
15-11-2012 дата публикации

Confinement techniques for non-volatile resistive-switching memories

Номер: US20120286230A1
Автор: Prashant Phatak
Принадлежит: Intermolecular Inc

Confinement techniques for non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. A resistive switching memory element described herein includes a first electrode adjacent to an interlayer dielectric, a spacer over at least a portion of the interlayer dielectric and over a portion of the first electrode and a metal oxide layer over the spacer and the first electrode such that an interface between the metal oxide layer and the electrode is smaller than a top surface of the electrode.

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Номер записи: 75
22-11-2012 дата публикации

Memory element and memory device

Номер: US20120294063A1
Автор: Akira Kouchiyama, Hiroaki Sei, Kazuhiro Ohba, Masayuki Shimuta, Shuichiro Yasuda, Tetsuya Mizuguchi
Принадлежит: Sony Corp

There are provided a memory element and a memory device excellently operating at a low current, and having the satisfactory retention characteristics. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer disposed on the first electrode side, and being in a single- or multi-layer structure including a layer containing a highest percentage of tellurium (Te) as an anionic component, and an ion source layer disposed on the second electrode side, and containing a metallic element and one or more chalcogen elements including tellurium (Te), sulfur (S), and selenium (Se) with aluminum (Al) of 27.7 atomic % or more but 47.4 atomic % or less.

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Номер записи: 76
22-11-2012 дата публикации

Method of manufacturing non-volatile semiconductor memory element and method of manufacturing non-volatile semiconductor memory device

Номер: US20120295413A1
Автор: Satoru Fujii, Takumi Mikawa
Принадлежит: Panasonic Corp

A method of manufacturing a non-volatile semiconductor memory element including a variable resistance element and a non-ohmic element. The variable resistance element includes a first electrode, a variable resistance layer, and a shared electrode. The non-ohmic element includes the shared electrode, a semiconductor or insulator layer, and a second electrode. The method includes: forming the first electrode on a substrate; forming the variable resistance layer on the first electrode; forming the shared electrode by nitriding a front surface of the variable resistance layer; forming the semiconductor or insulator layer on the shared electrode; and forming the second electrode. In the forming of the shared electrode, a front surface of a transition metal oxide is nitrided by a plasma nitriding process to form the shared electrode comprising a transition metal nitride.

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Номер записи: 77
29-11-2012 дата публикации

Semiconductor memory device, method of manufacturing the same and method of forming contact structure

Номер: US20120299189A1
Автор: Shingo Nakajima
Принадлежит: Toshiba Corp

When a first wiring and/or a second wiring is formed, a connection portion is formed in the first wiring and/or the second wiring which covers a part of a lower electrode layer outside the memory cell array. An etching suppressing portion is formed above the connection portion. A contact hole is formed in which a portion under the etching suppressing portion reaches up to a connection potion, and the other portion reaches up to the lower electrode layer by performing etching to a laminated body in a range including the etching suppressing portion. The laminated body includes the insulating layer, the first wiring, a memory cell layer, the second wiring, and the etching suppressing portion. The contact layer is formed by burying a conductive material in the contact hole.

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Номер записи: 78
06-12-2012 дата публикации

Memory devices and method of manufacturing the same

Номер: US20120305522A1
Автор: Dong-Whee Kwon, Doo-Hwan Park, Gyu-Hwan OH, Kyung-min Chung
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Memory devices and methods of forming memory devices including forming a plurality of preliminary electrodes, each of the plurality of preliminary electrodes including a protruding region, protruding from a first mold insulating layer, forming a second mold insulating layer on the first mold insulating layer, removing at least a portion of the plurality of preliminary electrodes to form a plurality of openings in the second mold insulating layer and a plurality of lower electrodes, and forming a plurality of memory elements in the plurality of openings. Memory devices and methods of forming memory devices including forming one or more insulating layers on sidewalls of all or part of a plurality of lower electrodes and/or a plurality of memory elements.

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Номер записи: 79
06-12-2012 дата публикации

Switching device having a non-linear element

Номер: US20120305879A1
Автор: Sung Hyun Jo, Wei Lu
Принадлежит: Crossbar Inc

A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

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Номер записи: 80
06-12-2012 дата публикации

Nitrogen Doped Aluminum Oxide Resistive Random Access Memory

Номер: US20120305881A1
Автор: Siu-Weng S. Wong, Sung Il Park, Wanki Kim, Zhiping Zhang
Принадлежит: Leland Stanford Junior University

A resistive random access memory (RRAM) device is provided that includes a first electrode, a second electrode, and a resistance-change film disposed between the first electrode and the second electrode, where the resistance-change film includes an atomic ratio of aluminum, oxygen and nitrogen.

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Номер записи: 81
06-12-2012 дата публикации

Semiconductor device and semiconductor device manufacturing method

Номер: US20120306081A1
Автор: Atsuko Sakata, Junichi Wada, Masahiko Hasunuma, Takeshi Ishizaki
Принадлежит: Individual

According to one embodiment, a semiconductor device includes an interconnect provided on a first interlayer insulating film covering a semiconductor substrate in which an element is formed, a cap layer provided on the upper surface of the interconnect, and a barrier film provided between the interconnect and a second interlayer insulating film covering the interconnect. The interconnect includes a high-melting-point conductive layer, and the width of the interconnect is smaller than the width of the cap layer. The barrier film includes a compound of a contained element in the high-melting-point conductive layer.

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Номер записи: 82
13-12-2012 дата публикации

Non-volatile memory device having phase-change material and method for fabricating the same

Номер: US20120314492A1
Автор: Ji-Won Jung, Yong-Shik Shin
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A non-volatile memory device includes a plurality of memory blocks. Each of memory blocks includes a main area including a plurality of first memory cells having a phase-change material and a spare area including at least one second memory cell for storing initial information about the plurality of first memory cells. In the non-volatile memory device, a circuit of the at least one second memory cell is cut off according to the initial information, and the initial information is defective block information that is information about a defect of the plurality of memory blocks.

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Номер записи: 83
13-12-2012 дата публикации

Surface treatment to improve resistive-switching characteristics

Номер: US20120315725A1
Автор: April Schricker, Michael Miller, Prashant Phatak, Tanmay Kumar, Tony Chiang, Xiyang Chen
Принадлежит: Intermolecular Inc

This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

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Номер записи: 84
20-12-2012 дата публикации

Variable resistance memory device having reduced bottom contact area and method of forming the same

Номер: US20120319073A1
Автор: Hasan Nejad
Принадлежит: Individual

A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom contact area. A variable resistance material is formed over the bottom electrodes such that the variable resistance material has a surface that is in electrical communication with the bottom electrode and a top electrode is formed over the variable resistance material. The small bottom electrode contact area reduces the reset current requirement which in turn reduces the write transistor size for each bit.

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Номер записи: 85
20-12-2012 дата публикации

Resistance-change memory device and method of operating the same

Номер: US20120320659A1
Автор: Makoto Kitagawa
Принадлежит: Sony Corp

Disclosed herein is a resistance-change memory device including a bit line; a voltage supplying layer; a memory element connected between the bit line and the voltage supplying layer, a resistance value of the memory element being changed in accordance with an applied voltage; and a drive controlling circuit causing a first current to flow through the bit line and causing a second current smaller than the first current to flow through the bit line, thereby controlling a resistance decreasing operation in which the memory element is made to transit from a high resistance state to a low resistance state by using the second current.

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Номер записи: 86
27-12-2012 дата публикации

Memory Device

Номер: US20120329237A1
Автор: Regino Sandoval, Wolodymyr Czubatyj
Принадлежит: Ovonyx Inc

A phase-change memory device includes a first insulator having a hole therethrough, a first electrode that conforms at least partially to the hole, a phase-change material in electrical communication with the first electrode, and a second electrode in electrical communication with the phase-change material. When current is passed from the first electrode to the second electrode through the phase-change material, at least one of the first and second electrodes remains unreactive with the phase change material.

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Номер записи: 87
03-01-2013 дата публикации

Compressive Structure for Enhancing Contact of Phase Change Material Memory Cells

Номер: US20130001499A1
Автор: Alejandro G. Schrott, Chung H. Lam, Matthew J. Breitwisch
Принадлежит: International Business Machines Corp

A process for manufacturing a PCM device comprises forming a dielectric, producing a via in the dielectric starting at an area on the surface of the dielectric by forming a via opening in the area and extending the opening into the dielectric toward and then terminating at an electrode comprising a first electrode in the dielectric. We form a spacer layer contiguous with the side walls of the via and fill the via with a PCM. We then remove the surface of the dielectric to leave a PCM cusp at the opening of the via, cap the PCM cusp with a low density capping film; densify the PCM and capping film to obtain a high density capping film that exerts compressive pressure on the high density PCM in a direction toward the first electrode to enhance electrical contact between the PCM and the first electrode.

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Номер записи: 88
03-01-2013 дата публикации

Low temperature deposition of phase change memory materials

Номер: US20130005078A1
Автор: Bryan C. Hendrix, Chongying Xu, Gregory T. Stauf, Jeffrey F. Roeder, Matthias Stender, Thomas H. Baum, Tianniu Chen, William Hunks
Принадлежит: Advanced Technology Materials Inc

A system and method for forming a phase change memory material on a substrate, in which the substrate is contacted with precursors for a phase change memory chalcogenide alloy under conditions producing deposition of the chalcogenide alloy on the substrate, at temperature below 350° C., with the contacting being carried out via chemical vapor deposition or atomic layer deposition. Various tellurium, germanium and germanium-tellurium precursors are described, which are useful for forming GST phase change memory films on substrates.

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Номер записи: 89
17-01-2013 дата публикации

Chip Comprising an Integrated Circuit, Fabrication Method and Method for Locally Rendering a Carbonic Layer Conductive

Номер: US20130015583A1
Автор: Uwe Hoeckele
Принадлежит: INFINEON TECHNOLOGIES AG

A chip includes an integrated circuit and a carbonic layer. The carbonic layer includes a graphite-like carbon, wherein a lateral conducting path through the graphite-like carbon electrically connects two circuit elements of the integrated circuit.

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Номер записи: 90
24-01-2013 дата публикации

Memory device and method of manufacturing the same

Номер: US20130021834A1
Автор: Kazuhide Koyama
Принадлежит: Sony Corp

A memory device includes a plurality of memory elements, each having a first electrode, a second electrode, and a memory layer between the first electrode and the second electrode. The plurality of memory layers are in a dotlike pattern. Two adjacent first electrodes share a same memory layer.

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Номер записи: 91
24-01-2013 дата публикации

Resistive ram, method for fabricating the same, and method for driving the same

Номер: US20130021835A1
Автор: Hyun-Sang Hwang, Myoung-Woo Son, Xinjun Liu
Принадлежит: Individual

A resistive random access memory (ReRAM) includes a first electrode, a threshold switching layer formed over the first electrode and configured to perform a switching operation according to an applied voltage, a resistance change layer formed over the threshold switching layer, and configured to perform a resistance change operation, and a second electrode formed over the resistance change layer, wherein the threshold switching layer comprises a stoichiometric transition oxide while the resistance change layer comprises a non-stoichiometric transition metal oxide.

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Номер записи: 92
31-01-2013 дата публикации

Phase change memory electrode with sheath for reduced programming current

Номер: US20130026436A1
Автор: Bipin Rajendran, Matthew J. Breitwisch
Принадлежит: International Business Machines Corp

An example embodiment is a phase change memory cell that includes a bottom contact and an electrically insulating layer disposed over the bottom contact. The electrically insulating layer defines an elongated via. Furthermore, a bottom electrode is disposed at least partially in the via. The bottom electrode includes a sleeve of a first electrically conductive material surrounding a rod of a second electrically conductive material. The first electrically conductive material and the second electrically conductive material have different specific electrical resistances. The memory cell also includes a phase change layer electrically coupled to the first electrode.

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Номер записи: 93
31-01-2013 дата публикации

Nonvolatile semiconductor memory apparatus and manufacturing method thereof

Номер: US20130029469A1
Автор: Takeshi Takagi, Takumi Mikawa
Принадлежит: Takeshi Takagi, Takumi Mikawa

A nonvolatile semiconductor memory apparatus including a substrate, lower-layer electrode wires provided on the substrate, an interlayer insulating layer provided with contact holes at locations respectively opposite to the lower-layer electrode wires, resistance variable layers which are respectively connected to the lower-layer electrode wires; and non-ohmic devices which are respectively provided on the resistance variable layers. The non-ohmic devices each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer. One layer of the laminated-layer structure is embedded to fill each of the contact holes and the semiconductor layer or the insulator layer which is the other layer of the laminated-layer structure has a larger area than an opening of each of the contact holes and is provided on the interlayer insulating layer.

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Номер записи: 94
14-02-2013 дата публикации

Nonvolatile memory element, manufacturing method thereof, and nonvolatile semiconductor device incorporating nonvolatile memory element

Номер: US20130037775A1
Автор: Koji Katayama, Satoru Mitani, Takeshi Takagi, Yoshihiko Kanzawa
Принадлежит: Koji Katayama, Satoru Mitani, Takeshi Takagi, Yoshihiko Kanzawa

A nonvolatile memory element of the present invention comprises a first electrode ( 103 ), a second electrode ( 108 ); a resistance variable layer ( 107 ) which is interposed between the first electrode ( 103 ) and the second electrode ( 107 ) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes ( 103 ) and ( 108 ), and the resistance variable layer ( 107 ) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfO x (0.9≦x≦1.6), and a second hafnium-containing layer having a composition expressed as HfO y (1.8≦y≦2.0) are stacked together.

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Номер записи: 95
14-02-2013 дата публикации

Variable resistance memory

Номер: US20130037776A1
Автор: Daisuke Matsushita, Hidenori Miyagawa, Jun Fujiki, Takeshi Imamura, Yoshifumi Nishi
Принадлежит: Toshiba Corp

A variable resistance memory according to an embodiment includes: a first wiring; a second wiring intersecting with the first wiring; a first electrode provided in an intersection region between the first wiring and the second wiring, the first electrode being connected to the first wiring; a second electrode connected to the second wiring, the second electrode facing to the first electrode; a variable resistance layer provided between the first electrode and the second electrode; and one of a first insulating layer and a first semiconductor layer formed at side portions of the second electrode. The one of the first insulating layer and the first semiconductor layer, and the second electrode form voids at the side portions of the second electrode.

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Номер записи: 96
14-02-2013 дата публикации

Connection and addressing of multi-plane crosspoint devices

Номер: US20130039111A1
Автор: Frederick Perner
Принадлежит: Hewlett Packard Development Co LP

A multi-plane circuit structure has at least a first circuit plane and a second circuit plane, and each circuit plane has a plurality of row wire segments, a plurality of column wire segments, and a plurality of crosspoint devices formed at intersections of the row wire segments and the column wire segments. The row and column wire segments have a segment length for forming a preselected number of crosspoint devices thereon. Each row wire segment in the second circuit plane is connected to a row wire segment in the first circuit plane with no offset in a row direction and in a column direction, and each column wire segment in the second circuit plane is connected to a column wire segment in the first circuit plane with an offset length in both the row direction and the column direction. The offset length corresponds to half of the preselected number of crosspoint devices.

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Номер записи: 97
14-02-2013 дата публикации

Method of fabricating resistance variable memory device and devices and systems formed thereby

Номер: US20130040408A1
Автор: Ki Joon Kim, KyungTae Nam, Youngnam HWANG
Принадлежит: SAMSUNG ELECTRONICS CO LTD

An exemplary method of forming a variable resistance memory may include forming first source/drain regions in a substrate, forming gate line structures and conductive isolation patterns buried in the substrate with the first source/drain regions interposed therebetween, and forming lower contact plugs on the first source/drain regions. The forming of lower contact plugs may include forming a first interlayer insulating layer, including a first recess region exposing the first source/drain regions adjacent to each other in a first direction, forming a conductive layer in the first recess region, patterning the conductive layer to form preliminary conductive patterns spaced apart from each other in the first direction, and patterning the preliminary conductive patterns to form conductive patterns spaced apart from each other in a second direction substantially orthogonal to the first direction.

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Номер записи: 98
28-02-2013 дата публикации

Method for forming resistive switching memory elements

Номер: US20130048937A1
Автор: Imran Hashim, Jinhong Tong, Randall Higuchi, Vidyut Gopal
Принадлежит: Intermolecular Inc

Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways.

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Номер записи: 99
28-02-2013 дата публикации

Methods, apparatuses, and circuits for programming a memory device

Номер: US20130051136A1
Автор: Agostino Pirovano, Andrea Redaelli, Umberto M. Meotto
Принадлежит: Micron Technology Inc

Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.

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Номер записи: 100