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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 6222. Отображено 100.
16-02-2012 дата публикации

Method of Forming Semiconductor Device Having Self-Aligned Plug

Номер: US20120040508A1
Автор: Byoung-Jae Bae, Chul-Ho Shin, Dong-Hyun Im, Doo-Hwan Park, Gyu-Hwan OH, Ik-Soo Kim, Kyoung-Ha EOM, Sang-Sup Jeong, Sung-Lae Cho, Sung-Un Kwon
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

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Номер записи: 1
15-03-2012 дата публикации

Multi-level resistance change memory

Номер: US20120063193A1
Автор: Reika Ichihara
Принадлежит: Individual

According to one embodiment, a multi-level resistance change memory includes a memory cell includes first and second resistance change films connected in series, and a capacitor connected in parallel to the first resistance change film, a voltage pulse generating circuit generating a first voltage pulse with a first pulse width to divide a voltage of the first voltage pulse into the first and second resistance change films based on a resistance ratio thereof, and generating a second voltage pulse with a second pulse width shorter than the first pulse width to apply a voltage of the second voltage pulse to the second resistance change film by a transient response of the capacitor, and a control circuit which is stored multi-level data to the memory cell by using the first and second voltage pulses in a writing.

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Номер записи: 2
29-03-2012 дата публикации

Resistor structure for a non-volatile memory device and method

Номер: US20120075907A1
Автор: Sung Hyun Jo
Принадлежит: Crossbar Inc

A non-volatile resistive switching memory device. The device includes a first electrode, a second electrode, a switching material in direct contact with a metal region of the second electrode, and a resistive material disposed between the second electrode and the switching material. The resistive material has an ohmic characteristic and a resistance substantially the same as an on state resistance of the switching device. The resistive material allows for a change in a resistance of the switching material upon application of voltage pulse without time delay and free of a reverse bias after the voltage pulse. The first voltage pulse causes a programming current to flow from the second electrode to the first electrode. The resistive material further causes the programming current to be no greater than a predetermined value.

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Номер записи: 3
26-04-2012 дата публикации

Integrated Circuitry Comprising Nonvolatile memory Cells And Methods Of Forming A Nonvolatile Memory Cell

Номер: US20120097913A1
Автор: John K. Zahurak, Jun Liu
Принадлежит: Individual

An integrated circuit has a nonvolatile memory cell that includes a first electrode, a second electrode, and an ion conductive material there-between. At least one of the first and second electrodes has an electrochemically active surface received directly against the ion conductive material. The second electrode is elevationally outward of the first electrode. The first electrode extends laterally in a first direction and the ion conductive material extends in a second direction different from and intersecting the first direction. The first electrode is received directly against the ion conductive material only where the first and second directions intersect. Other embodiments, including method embodiments, are disclosed.

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Номер записи: 4
26-04-2012 дата публикации

Nonvolatile memory device and manufacturing method thereof

Номер: US20120097915A1
Автор: Atsushi Himeno, Takumi Mikawa, Yoshio Kawashima
Принадлежит: Panasonic Corp

There are provided a resistance variable nonvolatile memory device which changes its resistance stably at low voltages and is suitable for a miniaturized configuration, and a manufacturing method thereof. The nonvolatile memory device comprises: a substrate ( 100 ); a first electrode ( 101 ); an interlayer insulating layer ( 102 ); a memory cell hole ( 103 ) formed in the interlayer insulating layer; a first resistance variable layer ( 104 a ) formed in at least a bottom portion of the memory cell hole and connected to the first electrode; a second resistance variable layer ( 104 b ) formed inside the memory cell hole ( 103 ) and located on the first resistance variable layer ( 104 a ); and a second electrode ( 105 ); the first resistance variable layer ( 104 a ) and the second resistance variable layer ( 104 b ) respectively comprising metal oxides of the same kind; and the first resistance variable layer ( 104 a ) having a higher oxygen content than the second resistance variable layer ( 104 b ).

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Номер записи: 5
03-05-2012 дата публикации

Method for obtaining smooth, continuous silver film

Номер: US20120108030A1
Автор: Scott Brad Herner
Принадлежит: Crossbar Inc

A method for forming a semiconductor device including a resistive memory cell includes providing a substrate having an upper surface. A first conductive layer is formed over the upper surface of the substrate. An amorphous silicon layer is formed over the first conductive layer. A surface of the amorphous silicon layer is cleaned to remove native oxide formed on the surface of the amorphous silicon layer. A silver layer is deposited over the amorphous silicon layer after removing the native oxide by performing the cleaning step. The resistive memory cell includes the first conductive layer, the amorphous silicon layer, and the second conductive layer. The surface of the amorphous silicon layer is cleaned to prevent silver agglomeration on the native oxide.

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Номер записи: 6
10-05-2012 дата публикации

Method to reduce a via area in a phase change memory cell

Номер: US20120115302A1
Автор: Alejandro G. Schrott, Chung H. Lam, Eric A. Joseph, Matthew J. Breitwisch, Yu Zhu
Принадлежит: International Business Machines Corp

A memory cell structure and method to form such structure. The method partially comprised of forming a via within an oxidizing layer, over the center of a bottom electrode. The method includes depositing a via spacer along the sidewalls of the via and oxidizing the via spacer. The via spacer being comprised of a material having a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The via area is reduced by expansion of the via spacer during the oxidation. Alternatively, the method is partially comprised of forming a via within a first layer, over the center of the bottom electrode. The first layer has a Pilling-Bedworth ratio of at least one and one-half and is an insulator when oxidized. The method also includes oxidizing at least a portion of the sidewalls of the via in the first layer.

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Номер записи: 7
24-05-2012 дата публикации

Upwardly Tapering Heaters for Phase Change Memories

Номер: US20120126196A1
Автор: Federico Pio
Принадлежит: Individual

A substantially planar heater for a phase change memory may taper as it extends upwardly to contact a chalcogenide layer. As a result, the contact area between heater and chalcogenide is reduced. This reduced contact area can reduce power consumption in some embodiments.

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Номер записи: 8
24-05-2012 дата публикации

Thermally insulated phase material cells

Номер: US20120129313A1
Автор: Alejandro G. Schrott, Bipin Rajendran, Chung H. Lam, Eric A. Joseph, Matthew J. Breitwisch, Roger W. Cheek, Yu Zhu
Принадлежит: International Business Machines Corp

A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material.

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Номер записи: 9
14-06-2012 дата публикации

Continuous mesh three dimensional non-volatile storage with vertical select devices

Номер: US20120147644A1
Автор: Roy E. Scheuerlein
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

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Номер записи: 10
14-06-2012 дата публикации

Three dimensional non-volatile storage with multi block row selection

Номер: US20120147689A1
Автор: Roy E. Scheuerlein, Tianhong Yan
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

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Номер записи: 11
21-06-2012 дата публикации

Highly integrated phase change memory device having micro-sized diodes and method for manufacturing the same

Номер: US20120156853A1
Автор: Jun Hyung PARK, Ki Sung Kwon
Принадлежит: Hynix Semiconductor Inc

A highly integrated phase change memory device and a method for manufacturing the same is disclosed. The highly integrated phase change memory device includes a semiconductor substrate having a cell area and a peripheral area with impurity regions formed in the cell area and extending in parallel to each other in a first direction to form a striped pattern. A gate electrode is formed in the peripheral area and dummy gate electrodes are formed in the cell area and extending in a second direction perpendicular to the first direction of the impurity regions. An interlayer dielectric layer pattern exposes portions of the cell area and the peripheral area and a PN diode is formed in a space defined by a pair of dummy gate electrodes and a pair of interlayer dielectric layer patterns.

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Номер записи: 12
30-08-2012 дата публикации

Forming a Phase Change Memory With an Ovonic Threshold Switch

Номер: US20120220099A1
Автор: Charles H. Dennison
Принадлежит: Dennison Charles H

A phase change memory may include an ovonic threshold switch formed over an cyanic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.

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Номер записи: 13
06-09-2012 дата публикации

Methods for increasing bottom electrode performance in carbon-based memory devices

Номер: US20120223414A1
Автор: April D. Schricker, Er-Xuan Ping
Принадлежит: SanDisk 3D LLC

In some aspects, a method of forming a reversible resistance-switching metal-insulator-metal (“MIM”) stack is provided, the method including: forming a first conducting layer comprising a titanium nitride material having between about 50% Ti and about 95% Ti, forming a carbon nano-tube (CNT) material above the first conducting layer, forming a second conducting layer above the CNT material, and etching the first conducting layer, CNT material and second conducting layer to form the MIM stack. Numerous other aspects are provided.

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Номер записи: 14
06-09-2012 дата публикации

High density low power nanowire phase change material memory device

Номер: US20120225527A1
Автор: Bruce G. Elmegreen, Dennis M. Newns, Lia Krusin-Elbaum, Robert L. Sandstrom
Принадлежит: International Business Machines Corp

A memory cell device includes a semiconductor nanowire extending, at a first end thereof, from a substrate; the nanowire having a doping profile so as to define a field effect transistor (FET) adjacent the first end, the FET further including a gate electrode at least partially surrounding the nanowire, the doping profile further defining a p-n junction in series with the FET, the p-n junction adjacent a second end of the nanowire; and a phase change material at least partially surrounding the nanowire, at a location corresponding to the p-n junction.

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Номер записи: 15
13-09-2012 дата публикации

Memory Cell Constructions, and Methods for Fabricating Memory Cell Constructions

Номер: US20120228573A1
Автор: JIAN Li, Jun Liu
Принадлежит: Micron Technology Inc

Some embodiments include methods for fabricating memory cell constructions. A memory cell may be formed to have a programmable material directly against a material having a different coefficient of expansion than the programmable material. A retaining shell may be formed adjacent the programmable material. The memory cell may be thermally processed to increase a temperature of the memory cell to at least about 300° C., causing thermally-induced stress within the memory cell. The retaining shell may provide a stress which substantially balances the thermally-induced stress. Some embodiments include memory cell constructions. The constructions may include programmable material directly against silicon nitride that has an internal stress of less than or equal to about 200 megapascals. The constructions may also include a retaining shell silicon nitride that has an internal stress of at least about 500 megapascals.

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Номер записи: 16
20-09-2012 дата публикации

Phase-change material and phase-change type memory device

Номер: US20120235110A1
Автор: Junichi Koike, Toshiya Kamada, Yuji Sutou, Yuta Saito
Принадлежит: Tohoku University NUC

A phase-change material, which has a high crystallization temperature and is superior in thermal stability of the amorphous phase, which has a composition of the general chemical formula Ge x M y Te 100-x-y wherein M indicates one type of element which is selected from the group which comprises Al, Si, Cu, In, and Sn, x is 5.0 to 50.0 (at %) and y is 4.0 to 45.0 (at %) in range, and x and y are selected so that 40 (at %)≦x+y≦60 (at %). This phase-change material further contains, as an additional element L, at least one type of element L which is selected from the group which comprises N, O, Al, Si, P, Cu, In, and Sn in the form of Ge x M y L z Te 100-x-y-z wherein z is selected so that 40 (at %)≦x+y+z≦60 (at %).

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Номер записи: 17
27-09-2012 дата публикации

Nonvolatile memory device

Номер: US20120241707A1
Автор: Kensuke Takahashi
Принадлежит: Toshiba Corp

According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, and a pillar. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction. The pillar is disposed between each of the word lines and each of the bit lines. The pillar includes a current selection film and a plurality of variable resistance films stacked on the current selection film. One variable resistance film includes a metal and either oxygen or nitrogen. Remainder of the variable resistance films include the metal, either oxygen or nitrogen, and a highly electronegative substance having electronegativity higher than electronegativity of the metal. A concentration of highly electronegative substance in the remainder of the variable resistance films is different among the variable resistance films.

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Номер записи: 18
04-10-2012 дата публикации

Variable resistance element and manufacturing method thereof

Номер: US20120252184A1
Автор: Takeki Ninomiya, Takumi Mikawa, Yoshio Kawashima, Yukio Hayakawa
Принадлежит: Panasonic Corp

A variable resistance element comprises, when M is a transition metal element, O is oxygen, and x and y are positive numbers satisfying y>x; a lower electrode; a first oxide layer formed on the lower electrode and comprising MO x when a content ratio of O with respect to M is x; a second oxide layer formed on the first oxide layer and comprising MO y when a content ratio of O with respect to M is y; an upper electrode formed on the second oxide layer; a protective layer formed on the upper electrode and comprising an electrically conductive material having a composition different from a composition of the upper electrode; an interlayer insulating layer formed to cover the protective layer; and an upper contact plug formed inside an upper contact hole penetrating the interlayer insulating layer.

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Номер записи: 19
04-10-2012 дата публикации

Semiconductor Device and Method of Manufacturing the Same

Номер: US20120252187A1
Автор: Dong-Hyun Im, Dong-Hyun Kim, Gyu-Hwan OH, Kyung-min Chung
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of manufacturing the semiconductor device includes sequentially forming first to third mold layer patterns on a substrate and spaced apart from each other , forming a first semiconductor pattern between the first mold layer pattern and the second mold layer pattern, and a second semiconductor pattern between the second mold layer pattern and the third mold layer pattern, forming a first trench between the first mold layer pattern and the third mold layer pattern by removing a portion of the second mold layer pattern and portions of the first and second semiconductor patterns, depositing a material for a lower electrode conformally along side and bottom surfaces of the first trench, and forming first and second lower electrodes separated from each other on the first and second semiconductor patterns, respectively, by removing a portion of the material for a lower electrode positioned on the second mold layer pattern.

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Номер записи: 20
29-11-2012 дата публикации

Semiconductor memory device, method of manufacturing the same and method of forming contact structure

Номер: US20120299189A1
Автор: Shingo Nakajima
Принадлежит: Toshiba Corp

When a first wiring and/or a second wiring is formed, a connection portion is formed in the first wiring and/or the second wiring which covers a part of a lower electrode layer outside the memory cell array. An etching suppressing portion is formed above the connection portion. A contact hole is formed in which a portion under the etching suppressing portion reaches up to a connection potion, and the other portion reaches up to the lower electrode layer by performing etching to a laminated body in a range including the etching suppressing portion. The laminated body includes the insulating layer, the first wiring, a memory cell layer, the second wiring, and the etching suppressing portion. The contact layer is formed by burying a conductive material in the contact hole.

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Номер записи: 21
06-12-2012 дата публикации

Memory devices and method of manufacturing the same

Номер: US20120305522A1
Автор: Dong-Whee Kwon, Doo-Hwan Park, Gyu-Hwan OH, Kyung-min Chung
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Memory devices and methods of forming memory devices including forming a plurality of preliminary electrodes, each of the plurality of preliminary electrodes including a protruding region, protruding from a first mold insulating layer, forming a second mold insulating layer on the first mold insulating layer, removing at least a portion of the plurality of preliminary electrodes to form a plurality of openings in the second mold insulating layer and a plurality of lower electrodes, and forming a plurality of memory elements in the plurality of openings. Memory devices and methods of forming memory devices including forming one or more insulating layers on sidewalls of all or part of a plurality of lower electrodes and/or a plurality of memory elements.

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Номер записи: 22
03-01-2013 дата публикации

Compressive Structure for Enhancing Contact of Phase Change Material Memory Cells

Номер: US20130001499A1
Автор: Alejandro G. Schrott, Chung H. Lam, Matthew J. Breitwisch
Принадлежит: International Business Machines Corp

A process for manufacturing a PCM device comprises forming a dielectric, producing a via in the dielectric starting at an area on the surface of the dielectric by forming a via opening in the area and extending the opening into the dielectric toward and then terminating at an electrode comprising a first electrode in the dielectric. We form a spacer layer contiguous with the side walls of the via and fill the via with a PCM. We then remove the surface of the dielectric to leave a PCM cusp at the opening of the via, cap the PCM cusp with a low density capping film; densify the PCM and capping film to obtain a high density capping film that exerts compressive pressure on the high density PCM in a direction toward the first electrode to enhance electrical contact between the PCM and the first electrode.

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Номер записи: 23
24-01-2013 дата публикации

Memory device and method of manufacturing the same

Номер: US20130021834A1
Автор: Kazuhide Koyama
Принадлежит: Sony Corp

A memory device includes a plurality of memory elements, each having a first electrode, a second electrode, and a memory layer between the first electrode and the second electrode. The plurality of memory layers are in a dotlike pattern. Two adjacent first electrodes share a same memory layer.

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Номер записи: 24
31-01-2013 дата публикации

Nonvolatile semiconductor memory apparatus and manufacturing method thereof

Номер: US20130029469A1
Автор: Takeshi Takagi, Takumi Mikawa
Принадлежит: Takeshi Takagi, Takumi Mikawa

A nonvolatile semiconductor memory apparatus including a substrate, lower-layer electrode wires provided on the substrate, an interlayer insulating layer provided with contact holes at locations respectively opposite to the lower-layer electrode wires, resistance variable layers which are respectively connected to the lower-layer electrode wires; and non-ohmic devices which are respectively provided on the resistance variable layers. The non-ohmic devices each has a laminated-layer structure including plural semiconductor layers, a laminated-layer structure including a metal electrode layer and an insulator layer, or a laminated-layer structure including a metal electrode layer and a semiconductor layer. One layer of the laminated-layer structure is embedded to fill each of the contact holes and the semiconductor layer or the insulator layer which is the other layer of the laminated-layer structure has a larger area than an opening of each of the contact holes and is provided on the interlayer insulating layer.

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Номер записи: 25
25-04-2013 дата публикации

Methods of manufacturing phase-change memory device and semiconductor device

Номер: US20130102120A1
Автор: Hye Jin Seo, Keum Bum Lee
Принадлежит: Hynix Semiconductor Inc

Methods of manufacturing a phase-change memory device and a semiconductor device are provided. The method of manufacturing the phase-change memory device includes forming a switching device layer, an ohmic contact layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer to form a hard mask pattern, etching the ohmic layer and the switching layer using the hard mask pattern to form a pattern structure including an ohmic contact pattern, a switching device pattern, and the hard mask pattern, selectively oxidizing a surface of the pattern structure, forming an insulating layer to bury the pattern structure, and selectively removing the hard mask pattern other than the oxidized surface thereof to form a contact hole.

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Номер записи: 26
02-05-2013 дата публикации

Phase-change memory device

Номер: US20130105756A1
Автор: Tae-hoon Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A phase-change memory device comprises a first insulating layer on a substrate and a through hole formed in the first insulating layer. A first phase-change material layer is positioned along lower sidewalls and a lower face of the through hole. A second insulating layer is laterally surrounded by the first phase-change material layer. A second phase-change material layer is positioned along upper sidewalls of the through hole and in contact with upper surfaces of the first phase-change material layer and the second insulating layer.

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Номер записи: 27
09-05-2013 дата публикации

Slurry Composition For Polishing And Method Of Manufacturing Phase Change Memory Device Using The Same

Номер: US20130112914A1
Автор: Choong-Ho Han, Jae-dong Lee, Jin-Woo Bae, Joon-Sang Park, Kyoung-Moon Kang, Sang-kyun Kim, Won-Jun Lee, Ye-Hwan Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A slurry composition includes an abrasive agent, an oxidizing agent, and a first adsorption inhibitor including a polyethylene oxide copolymer. A method of manufacturing a phase change memory device may include providing a substrate including an interlayer insulating film having a trench and a phase change material layer on the interlayer insulating film filling the trench, and performing chemical mechanical polishing on the phase change material layer using the slurry composition to form a phase change material pattern layer.

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Номер записи: 28
16-05-2013 дата публикации

Memory cell with post deposition method for regrowth of crystalline phase change material

Номер: US20130119339A1
Автор: Alejandro G. Schrott, Chung H. Lam, Stephen M. Rossnagel
Принадлежит: International Business Machines Corp

A phase change memory cell with substantially void free crystalline phase change material. An example memory cell includes a substrate and a bottom electrode carried by the substrate. The bottom electrode is a thermal conductor. A phase change layer includes phase change material. The phase change layer is void free within a switching region when the phase change material is in a crystalline phase. A top electrode is positioned over the phase change layer.

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Номер записи: 29
06-06-2013 дата публикации

Variable resistive memory device and method of fabricating the same

Номер: US20130141967A1
Автор: Hye Jin Choi, Ju Heyuck Baeck, Mann Ho CHO, Tae Hyeon Kim
Принадлежит: Hynix Semiconductor Inc, Industry Academic Cooperation Foundation of Yonsei University

A variable resistive memory device includes an array of a plurality of memory cells. Each of the plurality of memory cells includes first and second electrodes, and an Sb m Se n material layer (where m and n are positive numbers, respectively) interposed between the first electrode and the second electrode. The Sb m Se n material layer includes a separation structure in which a plurality of Sb atoms are in contact with a plurality of Se atoms.

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Номер записи: 30
13-06-2013 дата публикации

Antifuse-based memory cells having multiple memory states and methods of forming the same

Номер: US20130148404A1
Автор: Abhijit Bandyopadhyay, Peter Rabkin, Roy E. Scheuerlein
Принадлежит: SanDisk 3D LLC

In some aspects, a memory cell is provided that includes a steering element and a metal-insulator-metal (“MIM”) stack coupled in series with the steering element. The MIM stack includes a first dielectric material layer and a second dielectric material layer disposed on the first dielectric material layer, without a metal or other conductive layer disposed between the first dielectric material layer and the second dielectric material layer. Numerous other aspects are provided.

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Номер записи: 31
11-07-2013 дата публикации

Integrated Circuitry, Methods of Forming Memory Cells, and Methods of Patterning Platinum-Containing Material

Номер: US20130175495A1
Автор: Andrey V. Zagrebelny, Chet E. Carter
Принадлежит: Micron Technology Inc

Some embodiments include methods of patterning platinum-containing material. An opening may be formed to extend into an oxide. Platinum-containing material may be formed over and directly against an upper surface of the oxide, and within the opening. The platinum-containing material within the opening may be a plug having a lateral periphery. The lateral periphery of the plug may be directly against the oxide. The platinum-containing material may be subjected to polishing to remove the platinum-containing material from over the upper surface of the oxide. The polishing may delaminate the platinum-containing material from the oxide, and may remove the platinum-containing material from over the oxide with an effective selectivity for the platinum-containing material relative to the oxide of at least about 5:1. Some embodiments include methods of forming memory cells. Some embodiments include integrated circuitry having platinum-containing material within an opening in an oxide and directly against the oxide.

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Номер записи: 32
01-08-2013 дата публикации

Memory arrays and methods of forming same

Номер: US20130193398A1
Автор: Antonino Rigano, Fabio Pellizzer
Принадлежит: Micron Technology Inc

Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a first conductive material having a looped feature using a self-aligning multiple patterning technique, and forming a first sealing material over the looped feature. A first chop mask material is formed over the first sealing material. The looped feature and the first sealing material are removed outside the first chop mask material.

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Номер записи: 33
12-09-2013 дата публикации

Nonvolatile semiconductor storage device

Номер: US20130234095A1
Автор: Masanobu Baba
Принадлежит: Individual

A nonvolatile semiconductor storage device includes a word line, a first electrode, a high resistance ion diffusion layer, a second electrode, and a bit line. The word line is made of a conductive material extending in a first direction. The first electrode is provided on the word line. The high resistance ion diffusion layer is provided on the first electrode. The second electrode is provided on the ion diffusion layer and configured to supply a metal into the ion diffusion layer upon application of a positive voltage relative to the first electrode. The bit line is provided on the second electrode and made of a conductive material extending in a second direction orthogonal to the first direction. The ion diffusion layer contains oxygen at a higher concentration on the word line side than on the bit line side.

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Номер записи: 34
12-09-2013 дата публикации

Memory cell that includes a sidewall collar for pillar isolation and methods of forming the same

Номер: US20130234104A1
Автор: Scott Brad Herner
Принадлежит: SanDisk 3D LLC

A method of forming a memory cell is provided. The method includes forming a steering element pillar having a first stiffness and a sidewall, forming a sidewall collar along at least a portion of the sidewall of the steering element pillar, the sidewall collar having a second stiffness, wherein the second stiffness is greater than the first stiffness, and forming a memory element coupled to the steering element pillar. Numerous other aspects are provided.

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Номер записи: 35
26-09-2013 дата публикации

Nonvolatile memory device and method for manufacturing same

Номер: US20130248796A1
Автор: Hideki Inokuma
Принадлежит: Individual

According to one embodiment, a nonvolatile memory device includes a first wiring layer. The device includes a second wiring layer intersecting with the first wiring layer. And the device includes a first memory layer provided at a position where the first wiring layer and the second wiring layer intersect. And the first memory layer contacts with the first wiring layer, and the first wiring layer is a layer which is capable of supplying a metal ion to the first memory layer.

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Номер записи: 36
26-09-2013 дата публикации

Semiconductor memory device and method of manufacturing the same

Номер: US20130249114A1
Автор: Naohito Morozumi, Tomoya Osaki
Принадлежит: Toshiba Corp

A semiconductor memory device includes a memory cell array layer which includes a first wiring line, a memory cell stacked on the first wiring line, and a second wiring line formed on the memory cell so as to intersect the first wiring line, wherein a step is formed in the first wiring line so that the height of an upper surface of the first wiring line in the memory cell array region where the memory cell array is formed is higher than the height in a peripheral region around the memory cell array region.

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Номер записи: 37
24-10-2013 дата публикации

Method of fabricating semiconductor device

Номер: US20130280882A1
Автор: Young-Nam Hwang
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A method of fabricating a semiconductor device is provided. The method includes forming semiconductor patterns on a semiconductor substrate, such that sides are surrounded by a lower interlayer insulating layer. A lower insulating layer is formed that covers the semiconductor patterns and the lower interlayer insulating layer. A contact structure is formed that penetrates the lower insulating layer and the lower interlayer insulating layer and is spaced apart from the semiconductor patterns. The contact structure has an upper surface higher than the semiconductor patterns. An upper insulating layer is formed covering the contact structure and the lower insulating layer. The upper and lower insulating layers form insulating patterns exposing the semiconductor patterns and covering the contact structure, and each of the insulating patterns includes a lower insulating pattern and an upper insulating pattern sequentially stacked. After the insulating patterns are formed, metal-semiconductor compounds are formed on the exposed semiconductor patterns.

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Номер записи: 38
14-11-2013 дата публикации

Method of Forming Semiconductor Device Having Self-Aligned Plug

Номер: US20130302966A1
Автор: Byoung-Jae Bae, Chul-Ho Shin, Dong-Hyun Im, Doo-Hwan Park, Gyu-Hwan OH, Ik-Soo Kim, Kyoung-Ha EOM, Sang-Sup Jeong, Sung-Lae Cho, Sung-Un Kwon
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A conductive pattern on a substrate is formed. An insulating layer having an opening exposing the conductive pattern is formed. A bottom electrode is formed on the conductive pattern and a first sidewall of the opening. A spacer is formed on the bottom electrode and a second sidewall of the opening. The spacer and the bottom electrode are formed to be lower than a top surface of the insulating layer. A data storage plug is formed on the bottom electrode and the spacer. The data storage plug has a first sidewall aligned with a sidewall of the bottom electrode and a second sidewall aligned with a sidewall of the spacer. A bit line is formed on the data storage plug.

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Номер записи: 39
05-12-2013 дата публикации

Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same

Номер: US20130320287A1
Автор: April D. Schricker, Mark H. Clark, S. Brad Herner
Принадлежит: SanDisk 3D LLC

A method of forming a memory cell is provided that includes forming a steering element above a substrate, forming a material layer on the substrate, patterning and etching the material layer, and oxidizing the patterned and etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided.

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Номер записи: 40
19-12-2013 дата публикации

Vertical memory device and method of fabricating the same

Номер: US20130334488A1
Автор: Nam Kyun PARK
Принадлежит: SK hynix Inc

A vertical memory device capable of minimizing a cell size and improving current drivability and a method of fabricating the same are provided. The vertical memory device includes a common source region and source regions formed on the common source region and extending in a first direction. Channel regions are formed on each of the source regions, the channel regions extending in the first direction. Trenches are formed between the channel regions. A drain region is formed on each of the channel regions. A conductive layer is formed its on a side of each of the channel regions, the conductive layer extending to the first direction. A data storage material is formed on each of the drain regions.

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Номер записи: 41
23-01-2014 дата публикации

Nonvolatile memory device and method for manufacturing same

Номер: US20140021430A1
Автор: Junichi Wada, Katsuyuki Sekine, Kensuke Takano, Yoshio Ozawa
Принадлежит: Toshiba Corp

A nonvolatile memory device includes: a first conductive layer; a second conductive layer; a first resistance change layer provided between the first conductive layer and the second conductive layer and having an electrical resistance changing with at least one of an applied electric field and a passed current; and a first lateral layer provided on a lateral surface of the first resistance change layer and having an oxygen concentration higher than an oxygen concentration in the first resistance change layer

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Номер записи: 42
23-01-2014 дата публикации

Semiconductor Constructions, Memory Cells, Memory Arrays and Methods of Forming Memory Cells

Номер: US20140021431A1
Автор: Cinzia Perrone, Fabio Pellizzer
Принадлежит: Micron Technology Inc

Some embodiments include a construction having oxygen-sensitive structures directly over spaced-apart nodes. Each oxygen-sensitive structure includes an angled plate having a horizontal portion along a top surface of a node and a non-horizontal portion extending upwardly from the horizontal portion. Each angled plate has an interior sidewall where an inside corner is formed between the non-horizontal portion and the horizontal portion, an exterior sidewall in opposing relation to the interior sidewall, and lateral edges. Bitlines are over the oxygen-sensitive structures, and have sidewalls extending upwardly from the lateral edges of the oxygen-sensitive structures. A non-oxygen-containing structure is along the interior sidewalls, along the exterior sidewalls, along the lateral edges, over the bitlines, and along the sidewalls of the bitlines. Some embodiments include memory arrays, and methods of forming memory cells.

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Номер записи: 43
23-01-2014 дата публикации

Process-compatible decoupling capacitor and method for making the same

Номер: US20140021584A1
Автор: Kuo-Chi Tu, Wen-Ting Chu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Provided is decoupling capacitor device. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.

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Номер записи: 44
30-01-2014 дата публикации

Memristor cell structures for high density arrays

Номер: US20140027705A1
Автор: Gilberto Medeiros Ribeiro, Jianhua Yang, Minxian Max Zhang, R. Stanley Williams
Принадлежит: Hewlett Packard Development Co LP

A memristor array includes a lower layer of crossbars, upper layer of crossbars intersecting the lower layer of crossbars, memristor cells interposed between intersecting crossbars, and pores separating adjacent memristor cells. A method forming a memristor array is also provided.

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Номер записи: 45
06-02-2014 дата публикации

Semiconductor memory structure and its manufacturing method thereof

Номер: US20140034891A1
Автор: Pengfei Wang, Qingqing Sun, Wei Zhang, Xi Lin
Принадлежит: FUDAN UNIVERSITY

The present invention belongs to the technical field of microelectronic devices, specifically relates to a semiconductor memory structure and its manufacturing method thereof. The semiconductor memory structure which carries out erasing, writing and reading operation on the phase change memory or the resistance change memory through a tunneling field-effect transistor is formed, for one hand, the high current passed through the tunneling field-effect transistor when the p-n junction the biased positively, meeting the high current requirements for erasing of and writing of the phase change memory and the resistance change memory, and on the other hand, Vertical structure of the field-effect transistor can greatly improve the density of memory devices arrays. The present invention also discloses a method, which is very suitable for the memory chips, for the manufacturing of the semiconductor memory structure using self-aligned process.

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Номер записи: 46
06-02-2014 дата публикации

Switch device and crossbar memory array using same

Номер: US20140034893A1
Автор: Hajime Nakabayashi, Yoshihiro Hirota
Принадлежит: Tokyo Electron Ltd

A switch device used in a crossbar memory array having a non-volatile memory includes: a laminated body formed of a semiconductor film and an insulating film laminated on the semiconductor film; and a pair of electrode layers having the laminated body therebetween. The semiconductor film is made of a semiconductor material having an I-V characteristic with a negative resistance region.

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Номер записи: 47
06-03-2014 дата публикации

Nonvolatile memory

Номер: US20140061565A1
Автор: Kiyohito Nishihara
Принадлежит: Individual

A nonvolatile memory according to an embodiment includes a first wiring line; a second wiring line arranged above the first wiring line and extending in a direction crossing the first wiring line; and a resistance change layer arranged in an intersection region of the first wiring line the second wiring line, the second wiring line including a first member extending in the direction in which the second wiring line extends, and an electrode layer containing a metal element arranged on a side surface of the first member along the direction in which the second wiring line extends, a lower surface of the electrode layer being in contact with an upper surface of the resistance change layer.

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Номер записи: 48
06-03-2014 дата публикации

Non-volatile memory device and method for manufacturing the same

Номер: US20140063913A1
Автор: Yoshio Kawashima, Yukio Hayakawa
Принадлежит: Panasonic Corp

A non-volatile memory device includes: a memory cell array including a plurality of memory cells each including a variable resistance element and a first current steering element; and a current steering element parameter generation circuit. The current steering element parameter generation circuit includes: a third line placed between a substrate and a second interlayer dielectric; a fourth line placed above the second interlayer dielectric; and a second current steering element which is connected between the third line and the fourth line without the variable resistance element being interposed therebetween when the variable resistance element is removed between the third line and the fourth line and has the same non-linear current steering characteristics as the first current steering element.

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Номер записи: 49
20-03-2014 дата публикации

Continuous mesh three dimensional non-volatile storage with vertical select devices

Номер: US20140080272A1
Автор: Roy E. Scheuerlein
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

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Номер записи: 50
10-04-2014 дата публикации

Non-volatile memory device and manufacturing method thereof

Номер: US20140097396A1
Автор: Atsushi Himeno, Hideaki Murase, Yoshio Kawashima
Принадлежит: Panasonic Corp

A non-volatile memory device of the present invention comprises a first electrode; a variable resistance layer formed on and above the first electrode; a second electrode formed on and above the variable resistance layer; a side wall protective layer having an insulativity and covering a side wall of the first electrode, a side wall of the variable resistance layer and a side wall of the second electrode; and an electrically-conductive layer connected to the second electrode; the non-volatile memory device including a connection layer which is provided between the second electrode and the electrically-conductive layer to connect the second electrode and the electrically-conductive layer to each other, and comprises an electrically-conductive material different from a material constituting the electrically-conductive layer; wherein the side wall protective layer extends across the second electrode to a position which is above an upper end of the second electrode and below an upper end of the connection layer such that an upper end of the side wall protective layer is located above the upper end of the second electrode and below the upper end of the connection layer, when viewed from a side.

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Номер записи: 51
13-01-2022 дата публикации

Resistive memory device

Номер: US20220013171A1
Автор: Masayuki Terai
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A resistive memory device includes a first word line extending in a first horizontal direction, a second word line extending on the first word line in the first horizontal direction, a third word line extending on the second word line in the first horizontal direction, a first bit line extending between the first and second word lines in a second horizontal direction, a second bit line extending between the second and third word lines in the second horizontal direction, and memory cells respectively arranged between the first word line and the first bit line, between the first bit line and the second word line, between the second word line and the second bit line, and between the second bit line and the third word line. A thickness of the second word line is greater than a thickness of each of the first word line and the third word line.

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Номер записи: 52
07-01-2016 дата публикации

Methods of Forming Structures

Номер: US20160005966A1
Автор: Hyun Sik Kim, Irina V. Vasilyeva, Kyle B. Campbell, Kyuchul Chong
Принадлежит: Micron Technology Inc

Some embodiments include methods of forming structures. Spaced-apart features are formed which contain temperature-sensitive material. Liners are formed along sidewalls of the features under conditions which do not expose the temperature-sensitive material to a temperature exceeding 300° C. The liners extend along the temperature-sensitive material and narrow gaps between the spaced-apart features. The narrowed gaps are filled with flowable material which is cured under conditions that do not expose the temperature-sensitive material to a temperature exceeding 300° C. In some embodiments, the features contain memory cell regions over select device regions. The memory cell regions include first chalcogenide and the select device regions include second chalcogenide. The liners extend along and directly against the first and second chalcogenides.

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Номер записи: 53
07-01-2016 дата публикации

Memory Structures and Arrays, and Methods of Forming Memory Structures and Arrays

Номер: US20160005968A1
Автор: Durai Vishak Nirmal Ramaswamy, Mark S. Korber
Принадлежит: Micron Technology Inc

Some embodiments include memory structures having a diode over a memory cell. The memory cell can include programmable material between a pair of electrodes, with the programmable material containing a multivalent metal oxide directly against a high-k dielectric. The diode can include a first diode electrode directly over one of the memory cell electrodes and electrically coupled with the memory cell electrode, and can include a second diode electrode laterally outward of the first diode electrode and not directly over the memory cell. Some embodiments include memory arrays comprising the memory structures, and some embodiments include methods of making the memory structures.

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Номер записи: 54
02-01-2020 дата публикации

Phase change memory device with reduced read disturb and method of making the same

Номер: US20200005863A1
Автор: Michael Grobis, Ward Parkinson, Zhaoqiang BAI
Принадлежит: SanDisk Technologies LLC

A method of operating a phase change memory device includes flowing a write current of a first polarity through a phase change memory element of a selected phase change memory cell, and flowing a read current of a second polarity opposite to the first polarity through the phase change memory element of the selected phase change memory cell. A first junction between the phase change memory element and a first electrode and a second junction between the phase change memory element and a second electrode exhibit asymmetric thermoelectric heat generation during the step of flowing the write current.

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Номер записи: 55
04-01-2018 дата публикации

Methods of manufacturing semiconductor devices

Номер: US20180006219A1
Автор: Bok-yeon Won, Gwang-Hyun Baek, Hye-Jin Choi, Jae-Hun Seo, Jong-Chul Park, Jung-Ik Oh, Woo-Ram KIM, Yoo-Chul Kong
Принадлежит: SAMSUNG ELECTRONICS CO LTD

In method of manufacturing a semiconductor memory device, a selection layer and a variable resistance layer may be sequentially formed on a substrate. A preliminary first mask extending in a first direction may be formed on the variable resistance layer. An upper mask extending in a second direction crossing the first direction may be formed on the variable resistance layer and the preliminary first mask. The preliminary first mask may be etched using the upper mask as an etching mask to form a first mask having a pillar shape. The variable resistance layer and the selection layer may be anisotropically etched using the first mask as an etching mask to form a pattern structure including a variable resistance pattern and selection pattern sequentially stacked. The pattern structure may have a pillar shape. Damages to the pattern structure may decrease.

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Номер записи: 56
02-01-2020 дата публикации

Three-dimensional memory device containing cobalt capped copper lines and method of making the same

Номер: US20200006431A1
Автор: Satoru Mayuzumi, Wei Kuo Shih, Yuji Takahashi
Принадлежит: SanDisk Technologies LLC

A memory device includes first conductive rails laterally extending along a first horizontal direction over a substrate, where the first conductive rails include a fill portion, and a first cobalt-containing cap liner contacting a top surface of the fill portion, a rectangular array of first memory pillar structures overlying top surfaces of the first conductive rails, where each first memory pillar structure includes a respective first resistive memory element, and second conductive rails laterally extending along a second horizontal direction and overlying top surfaces of the rectangular array of first memory pillar structures.

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Номер записи: 57
27-01-2022 дата публикации

Phase-change memory device having reversed phase-change characteristics and phase-change memory having highly integrated three-dimensional architecture using same

Номер: US20220029094A1
Автор: Yun Heub Song
Принадлежит: SAMSUNG ELECTRONICS CO LTD

According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrode; and a selector which selectively switches the heat supplied by the upper electrode and the lower electrode to the phase-change layer, wherein the selector is formed of a compound which includes a transition metal in the phase-change material so as to have a high resistance when the crystalline state of the selector is crystalline and so as to have a low resistance when the crystalline state of the selector is non-crystalline.

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Номер записи: 58
14-01-2016 дата публикации

Multiple bit per cell dual-alloy gst memory elements

Номер: US20160012889A1
Автор: Daniel R. Shepard, Mac D. Apodaca
Принадлежит: HGST Inc, HGST NETHERLANDS BV

In various embodiments, a memory cell for storing two or more bits of information includes two series-connected memory storage elements composed of programmable materials having different melting points, enabling independent programming of the storage elements via different current pulses.

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Номер записи: 59
10-01-2019 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20190013357A1
Автор: Jeong Hee Park, Jong Uk Kim, Jung Moo Lee, Seong Geon PARK, Soon Oh PARK
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a first memory cell, a second memory cell, a first capping film, and a second capping film. The first memory cell includes a first ovonic threshold switch (OTS) on a first phase change memory. The second memory cell includes a second OTS on a second phase change memory. The first capping film is on side surfaces of the first and second memory cells. The second capping film is on the first capping film and fills a space between the first and second memory cells.

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Номер записи: 60
10-01-2019 дата публикации

Replacement materials processes for forming cross point memory

Номер: US20190013358A1
Автор: DerChang Kau, Gianpaolo Spadini, Jong-Won Lee, Stephen W. Russell
Принадлежит: Micron Technology Inc

Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.

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Номер записи: 61
09-01-2020 дата публикации

Programming enhancement in self-selecting memory

Номер: US20200013463A1
Автор: Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Innocenzo Tortorelli
Принадлежит: Micron Technology Inc

Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.

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Номер записи: 62
14-01-2021 дата публикации

Resistive random access memory structure and method for manufacturing the same

Номер: US20210013403A1
Автор: Chuan-Fu Wang, Chun-hung Cheng, Wen-Jen Wang
Принадлежит: United Microelectronics Corp

A resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.

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Номер записи: 63
09-01-2020 дата публикации

Semiconductor device and method for fabricating the same

Номер: US20200013949A1
Автор: Chiu-Jung Chiu, Hung-Chan Lin, Ya-Sheng Feng, Yu-Chun Chen, Yu-Ping Wang
Принадлежит: United Microelectronics Corp

A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a magnetic tunneling junction (MTJ) on the first IMD layer; forming a liner on the MTJ and the first IMD layer; removing part of the liner to form a spacer adjacent to the MTJ; and forming a second IMD layer on the first IMD layer.

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Номер записи: 64
21-01-2021 дата публикации

Phase change memory cell with second conductive layer

Номер: US20210020833A1
Автор: Junli Wang, Juntao Li, Kangguo Cheng, Ruilong Xie
Принадлежит: International Business Machines Corp

A method may include forming a via opening in a dielectric layer, depositing a first conductive layer along a bottom and a sidewall of the via opening, depositing a second conductive layer on top of the first conductive layer. The method may further include recessing the first conductive layer to form a trench and exposing a sidewall of the second conductive layer, depositing a non-conductive material in the trench, and depositing a phase change material layer on top of the dielectric layer. The top surface of the second conductive layer may be in direct contact with a bottom surface of the phase change material layer.

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Номер записи: 65
28-01-2016 дата публикации

Semiconductor device and method for fabricating the same, and microprocessor, processor, system, data storage system and memory system including the semiconductor device

Номер: US20160028011A1
Автор: Hye-Jung Choi, Su-Ock Chung
Принадлежит: SK hynix Inc

A semiconductor device includes first lines extending in a first direction; second lines extending in a second direction crossing with the first direction; and first resistance variable elements defined between the first lines and the second lines and each including a first substance layer and a second substance layer, wherein the first substance layer extends in the first direction and the second substance layer extends in the second direction.

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Номер записи: 66
24-04-2014 дата публикации

Phase Change Memory with Various Grain Sizes

Номер: US20140110656A1
Автор: Chun-Sheng Liang, Fu-Liang Yang, Tzyh-Cheang Lee
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size.

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Номер записи: 67
24-01-2019 дата публикации

Resistance change memory device and fabrication method thereof

Номер: US20190027683A1
Автор: Frederick Chen
Принадлежит: Winbond Electronics Corp

The resistance change memory device including a first resistance change memory element, a second resistance change memory element, and a memory controller is provided. The first resistance change memory element is disposed on a chip. The second resistance change memory element is disposed on the same chip. The memory controller is disposed on the same chip. The memory controller is configured to control data access of the first resistance change memory element and the second resistance change memory element. An accessing frequency of the first resistance change memory element is different from an accessing frequency of the second resistance change memory element.

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Номер записи: 68
24-04-2014 дата публикации

Phase-change random access memory device and method of manufacturing the same

Номер: US20140113427A1
Автор: Nam Kyun PARK
Принадлежит: SK hynix Inc

A phase-change random access memory (PCRAM) device includes a semiconductor substrate; switching elements formed on the semiconductor substrate; a plurality of phase-change structures formed on the switching elements; and heat absorption layers buried between the plurality of phase-change structures, wherein the plurality of phase-change structures are insulated from the heat absorption layers.

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Номер записи: 69
23-01-2020 дата публикации

Method for forming a phase change memory (pcm) cell with a low deviation contact area between a heater and a phase change element

Номер: US20200028075A1
Автор: Shih-Chang Liu, Yi Jen Tsai
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A phase change memory (PCM) cell with a low deviation contact area between a heater and a phase change element is provided. The PCM cell comprises a bottom electrode, a dielectric layer, a heater, a phase change element, and a top electrode. The dielectric layer overlies the bottom electrode. The heater extends upward from the bottom electrode, through the dielectric layer. Further, the heater has a top surface that is substantially planar and that is spaced below a top surface of the dielectric layer. The phase change element overlies the dielectric layer and protrudes into the dielectric layer to contact with the top surface of the heater. Also provided is a method for manufacturing the PCM cell.

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Номер записи: 70
23-01-2020 дата публикации

Resistive memory crossbar array with top electrode inner spacers

Номер: US20200028076A1
Автор: Hiroyuki Miyazoe, Iqbal R. Saraf, Shyng-Tsong Chen, Takashi Ando
Принадлежит: International Business Machines Corp

A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming conductive lines within an interlayer dielectric (ILD), forming a metal nitride layer over at least one conductive line, forming a bottom electrode, forming a RRAM stack over the metal nitride layer, the RRAM stack including a first top electrode and a second top electrode, undercutting the second top electrode to define recesses, and filling the recesses with inner spacers.

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Номер записи: 71
23-01-2020 дата публикации

Resistive memory crossbar array compatible with cu metallization

Номер: US20200028080A1
Автор: Lawrence A. Clevenger, Michael RIZZOLO, Shyng-Tsong Chen, Takashi Ando
Принадлежит: International Business Machines Corp

A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including a bottom electrode, a top electrode, and a bi-layer hardmask, forming a low-k dielectric layer over the RRAM stack, removing a first layer of the bi-layer hardmask during a via opening, and removing a second layer of the bilayer hardmask concurrently with a plurality of sacrificial layers formed over the low-k dielectric layer.

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Номер записи: 72
02-02-2017 дата публикации

Metal line connection for improved rram reliability, semiconductor arrangement comprising the same, and manufacture thereof

Номер: US20170033161A1
Автор: Chun-Yang Tsai, Kuo-Ching Huang, Yu-Wei Ting
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.

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Номер записи: 73
17-02-2022 дата публикации

Rram device structure and manufacturing method

Номер: US20220052258A1
Автор: Chung-Liang Cheng
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A resistive random access memory cell includes a gate all around transistor and a resistor device. The resistor device includes a first electrode including a plurality of conductive nanosheets. The resistor device includes a high-K resistive element surrounds the conductive nanosheets. The resistor device includes a second electrode separated from the conductive nanosheets by the resistive element.

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Номер записи: 74
30-01-2020 дата публикации

Multi-layer structure to increase crystalline temperature of a selector device

Номер: US20200035916A1
Автор: Hai-Dang Trinh
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

In some embodiments, a semiconductor device is provided. The semiconductor device includes a first amorphous switching structure disposed over a first electrode. A buffer structure is disposed over the first amorphous switching structure. A second amorphous switching structure is disposed over the buffer structure. A second electrode is disposed over the second amorphous switching structure, where the first and second amorphous switching structures are configured to switch between low resistance states and high resistance states depending on whether a voltage from the first electrode to the second electrode exceeds a threshold voltage.

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Номер записи: 75
18-02-2021 дата публикации

Crosspoint Phase Change Memory with Crystallized Silicon Diode Access Device

Номер: US20210050384A1
Автор: Asit Ray, Bahman Hekmatshoartabari, Fabio Carta, Matthew J. BrightSky, Wanki Kim
Принадлежит: International Business Machines Corp

A method of fabricating an access device in a crosspoint memory array structure during BEOL processing includes: forming at least a first doped semiconductor layer on an upper surface of a first conductive layer, the first doped semiconductor layer being in electrical connection with the first conductive layer; exposing at least a portion of the first doped semiconductor layer to a directed energy source to cause localized annealing in the first doped semiconductor layer to activate a dopant of a first conductivity type in the first doped semiconductor layer, thereby converting at least a portion of the first doped semiconductor layer into a polycrystalline layer; forming a second conductive layer over a least a portion of the first doped semiconductor layer; and etching the first doped semiconductor layer and the first and second conductive layers to form an access device that is self-aligned with the first and second conductive layers.

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Номер записи: 76
18-02-2021 дата публикации

Techniques for forming self-aligned memory structures

Номер: US20210050521A1
Автор: Agostino Pirovano, Andrea Redaelli, Fabio Pellizzer, Innocenzo Tortorelli, Lorenzo Fratin, Stephen W. Russell
Принадлежит: Micron Technology Inc

Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

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Номер записи: 77
08-05-2014 дата публикации

Pillar structure for memory device and method

Номер: US20140127876A1
Автор: Scott Brad Herner
Принадлежит: Crossbar Inc

A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.

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Номер записи: 78
03-03-2022 дата публикации

Small line or pillar structure and process

Номер: US20220069211A1
Автор: Chiao-Wen Yeh, Hsiang-Lan Lung
Принадлежит: Macronix International Co Ltd

A pillar-shaped structure and a line-shaped structure are described that include a supporting top conductive layer, an active material layer, such as a memory material or switching material, and a bottom conductive layer. The active material layer is more narrow than the supporting top conductive layer. A supporting side insulating layer is formed connecting the top and bottom conductive layers to provide structure stability. A void, or air gap, is formed between the active material layer and the supporting side insulating layer, which can provide improved thermal isolation between adjacent pillar-shaped or line-shaped structures.

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Номер записи: 79
25-02-2016 дата публикации

Cross-point memory and methods for fabrication of same

Номер: US20160056208A1
Автор: Andrea Ghetti, Fabio Pellizzer, Innocenzo Tortorelli
Принадлежит: Micron Technology Inc

The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.

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Номер записи: 80
25-02-2016 дата публикации

Integrated phase change switch

Номер: US20160056373A1
Автор: Michael A. Stuber, Sinan Goktepeli
Принадлежит: Qualcomm Switch Corp

Various methods and devices that involve phase change material (PCM) switches are disclosed. An exemplary integrated circuit comprises an active layer with a plurality of field effect transistor (FET) channels for a plurality of FETs. The integrated circuit also comprises an interconnect layer comprising a plurality of conductive interconnects. The plurality of conductive interconnects couple the plurality of field effect transistors. The integrated circuit also comprises an insulator layer covering at least a portion of the interconnect layer. The integrated circuit also comprises a channel of a radio-frequency (RF) PCM switch. The channel of the RF PCM switch is formed on the insulator layer.

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Номер записи: 81
15-05-2014 дата публикации

Logic compatible rram structure and process

Номер: US20140131651A1
Автор: Chih-Yang Chang, Chin-Chieh YANG, Hsia-Wei CHEN, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen LIAO
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A memory cell and method including a first electrode conformally formed through a first opening in a first dielectric layer, a resistive layer conformally formed on the first electrode, a second electrode conformally formed on the resistive layer, and a second dielectric layer conformally formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer is formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond a region defined by the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the region defined by the first opening. The second electrode is coupled to a second metal layer using a via that extends through the second opening.

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Номер записи: 82
25-02-2021 дата публикации

ReRAM STRUCTURE AND METHOD OF FABRICATING THE SAME

Номер: US20210057643A1
Автор: Chin-Fu Lin, Hsin-Fu Huang, Hui-Ting Lin, Kuo-Chih Lai, Nien-Ting Ho, Shih-Min Chou, Szu-Yao Yu, Wei-Ming Hsiao
Принадлежит: United Microelectronics Corp

An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

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Номер записи: 83
23-02-2017 дата публикации

Resistive memory devices with a multi-component electrode

Номер: US20170053968A1
Автор: Hans S. Cho, Jianhua Yang, Richard H. Henze, Xia Sheng, Yoocharn Jeon
Принадлежит: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

A resistive memory device includes a conductor and a resistive memory stack in contact with the conductor. The resistive memory stack includes a multi-component electrode and a switching region. The multi-component electrode includes a base electrode having a surface, and an inert material electrode on the base electrode surface in a form of i) a thin layer, or ii) discontinuous nano-islands. A switching region is in contact with the conductor and with the inert material electrode when the inert material electrode is in the form of the thin layer; or the switching region is in contact with the conductor, with the inert material electrode, and with an oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands.

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Номер записи: 84
13-02-2020 дата публикации

Variable resistance memory devices

Номер: US20200052038A1
Автор: Byongju Kim, Jeong-hee Park, Jong-Uk Kim, Kwangmin Park, Young-Min Ko
Принадлежит: SAMSUNG ELECTRONICS CO LTD

There is provided a variable resistance memory device including a first electrode line layer including first electrode lines extending in a first direction and spaced apart from each other on a substrate, a second electrode line layer that is above the first electrode line layer and including second electrode lines extending in a second direction orthogonal to the first direction and spaced apart from each other, and a memory cell layer including memory cells between the first electrode line layer and the second electrode line layer. Each of the memory cells includes a selection device layer, an intermediate electrode layer, and a variable resistance layer. A first insulating layer is between the first electrode lines, a second insulating layer is between the memory cells, and a third insulating layer is between the second electrode lines. The second insulating layer includes air gaps on side surfaces of the memory cells.

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Номер записи: 85
10-03-2022 дата публикации

Memory device and method of manufacturing the same

Номер: US20220077235A1
Автор: Jinhong Kim, Seyun KIM, Soichiro Mizusaki, Youngjin Cho, Yumin KIM
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A memory device may include an insulating structure including a first surface and a protrusion portion protruding from the first surface in a first direction, a recording material layer on the insulating structure and extending along a protruding surface of the protrusion portion to cover the protrusion portion and extending onto the first surface of the insulating structure, a channel layer on the recording material layer and extending along a surface of the recording material layer, a gate insulating layer on the channel layer; and a gate electrode formed on the gate insulating layer at a location facing a second surface of the insulating structure. The second surface of the insulating structure may be a protruding upper surface of the protrusion portion.

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Номер записи: 86
10-03-2022 дата публикации

Vertical 3d memory device and method for manufacturing the same

Номер: US20220077236A1
Автор: Corrado Villa, Paolo Fantini, Paolo Tessariol
Принадлежит: Micron Technology Inc

A vertical 3D memory device may comprise: a substrate including a plurality of conductive contacts each coupled with a respective one of a plurality of digit lines; a plurality of word line plates separated from one another with respective dielectric layers on the substrate, the plurality of word line plates including at least a first set of word lines separated from at least a second set of word lines with a dielectric material extending in a serpentine shape and at least a third set of word lines separated from at least a fourth set of word lines with a dielectric material extending in a serpentine shape; at least one separation layer separating the first set of word lines and the second set of word lines from the third set of word lines and the fourth set of word lines, wherein the at least one separation layer is parallel to both a digit line and a word line; and a plurality of storage elements each formed in a respective one of a plurality of recesses such that a respective storage element is surrounded by a respective word line, a respective digit line, respective dielectric layers, and a conformal material formed on a sidewall of a word line facing a digit line.

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Номер записи: 87
22-05-2014 дата публикации

Methods for forming narrow vertical pillars and integrated circuit devices having the same

Номер: US20140138604A1
Автор: Jun Liu, Kunal Parekh
Принадлежит: Micron Technology Inc

In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material.

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Номер записи: 88
22-05-2014 дата публикации

Resistance variable memory device

Номер: US20140138606A1
Автор: Jun-kyo Suh
Принадлежит: SK hynix Inc

Embodiments relate to a resistance variable memory device and a method for forming the same. The resistance variable memory device may include a first electrode, a second electrode spaced apart from the first electrode, a first resistance variable pattern provided over the first electrode and surrounding a lower portion of the second electrode, and a spacer surrounding a sidewall of the first resistance variable pattern. According to embodiments, the resistance variable pattern can be prevented from being damaged in an etching process and an air gap surrounding a portion of the electrode may contribute to improve reliability and an operational speed of the resistance variable memory device.

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Номер записи: 89
22-05-2014 дата публикации

Non-volatile memory device and manufacturing method thereof

Номер: US20140138607A1
Автор: Satoru Ito, Takumi Mikawa
Принадлежит: Panasonic Corp

A non-volatile memory device comprises first wires on and above a first plane; second wires extending in a direction crossing the first wires, on and above a second plane, third wires extending in parallel with the second wires on and above a fourth plane, and memory cells provided to correspond to three-dimensional cross-points of the first wires and the third wires, respectively, each of the memory cells including a transistor and a variable resistance element, the transistor including a first main electrode, a second main electrode, and a control electrode, the variable resistance element being placed on and above a third plane and including a lower electrode, an upper electrode and a variable resistance layer, wherein the upper electrode is connected to corresponding one of the third wires; and further comprises a first contact plug extending from the first main electrode to the second plane and connected to corresponding one of the second wires; a second contact plug extending from the second main electrode to the second plane; and a third contact plug extending from the second contact plug and connected to the lower electrode; wherein the second main electrode and the lower electrode are connected to each other via the second contact plug and the third contact plug.

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Номер записи: 90
03-03-2016 дата публикации

3d variable resistance memory device having junction fet and driving method thereof

Номер: US20160064454A1
Автор: Nam Kyun PARK
Принадлежит: SK hynix Inc

A 3D variable resistance memory device having a junction FET and a driving method thereof are provided. The variable resistance memory device includes a semiconductor substrate and a string selection switch formed on the semiconductor substrate. A channel layer is formed on the column string selection switch. A plurality of gates stacked along a length of the channel layer and each of the gates contacts an outer side of the channel layer. A variable resistance layer is formed on an inner side of the channel layer, and contacts the channel layer.

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Номер записи: 91
20-02-2020 дата публикации

Phase-Change Material (PCM) Radio Frequency (RF) Switch with Reduced Parasitic Capacitance

Номер: US20200058862A1
Автор: David J. Howard, Gregory P. Slovin, Jefferson E. Rose, Nabil El-Hinnawy
Принадлежит: Newport Fab LLC

A significantly reduced parasitic capacitance phase-change maternal (PCM) radio frequency (RF) switch includes an RF clearance zone including a step-wise structure of intermediate interconnect segments and vias to connect PCM contacts to setback top routing interconnects. The said RF clearance zone does not include cross-over interconnect segments. A low-k dielectric is situated in the RF clearance zone. A closed-air gap is situated in the RF clearance zone within the low-k dielectric. The setback top routing interconnects are situated higher over a substrate than the PCM contacts and the intermediate interconnect segments. The PCM RF switch may further include an open-air gap situated between the setback top routing interconnects.

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Номер записи: 92
22-05-2014 дата публикации

Gcib-treated resistive device

Номер: US20140141590A1
Автор: Gurtej S. Sandhu, John A. Smythe, III
Принадлежит: Micron Technology Inc

The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods for forming the GCIB-treated resistive devices. One method of forming a GCIB-treated resistive device includes forming a lower electrode, and forming an oxide material on the lower electrode. The oxide material is exposed to a gas cluster ion beam (GCIB) until a change in resistance of a first portion of the oxide material relative to the resistance of a second portion of the oxide material. An upper electrode is formed on the first portion.

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Номер записи: 93
12-03-2015 дата публикации

Memory cell formed by improved cmp process

Номер: US20150069630A1
Автор: Samuele Sciarrillo
Принадлежит: Micron Technology Inc

Memory cell array architectures and methods of forming the same are provided. An example method for forming an array of memory cells can include forming a plurality of vertical structures each having a switch element in series with a memory element in series with a top electrode, and forming an interconnection conductive material between the respective top electrodes of the plurality of vertical structures. The interconnection conductive material is etched-back and chemical-mechanical polished (CMPed). A conductive line is formed over the interconnection conductive material after CMPing the interconnection conductive material.

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Номер записи: 94
17-03-2022 дата публикации

Rram bottom electrode

Номер: US20220085288A1
Автор: Fu-Chen Chang, Kuo-Chi Tu, Wen-Ting Chu
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.

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Номер записи: 95
17-03-2022 дата публикации

Semiconductor storage device

Номер: US20220085291A1
Автор: Hiroyuki Ode
Принадлежит: Kioxia Corp

A semiconductor storage device includes a first region, a second region, and a third region. The first region includes first wirings extending in a first direction, second wirings extending in a second direction, and a memory cells provided at intersections of the first and second wirings. The second region includes a contact extending in a third direction. The third region includes first dummy wirings extending in the first direction, and a second dummy wirings extending in the second direction. A width in the first direction of a first one of the second dummy wirings, closest to the first region or the second region in the first direction, is equal to or less than a width in the first direction of a second one of the second dummy wirings next closest to the first region or the second region in the first direction.

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Номер записи: 96
10-03-2016 дата публикации

Memory Circuits and a Method for Forming a Memory Circuit

Номер: US20160071565A1
Автор: Marko Lemke
Принадлежит: INFINEON TECHNOLOGIES AG

A memory circuit includes a memory element which includes a first electrode layer including lithium. The memory element further includes a second electrode layer and a solid-state electrolyte layer arranged between the first electrode layer and the second electrode layer. The memory circuit also includes a memory access circuit configured to determine a memory state of the memory element.

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Номер записи: 97
09-03-2017 дата публикации

Semiconductor memory device

Номер: US20170069840A1
Автор: Kikuko Sugimae, Kiyoshi Okuyama, Masayuki Ichige, Masumi SAITOH
Принадлежит: Toshiba Corp

According to one embodiment, a semiconductor memory device includes first-third conductive layers, a semiconductor layer, a resistance change layer and a metal-containing layer. The second conductive layer is separated from the first conductive layer in a first direction. The semiconductor layer is provided between the first and the second conductive layers. The third conductive layer is arranged with the first semiconductor layer in a direction crossing the first direction. The first resistance change layer is provided between the first semiconductor layer and the first conductive layer. The first metal-containing layer is provided between the first resistance change layer and the first conductive layer. The first conductive layer extends in a second direction crossing the first direction. The second conductive layer extends in a third direction crossing the first direction and crossing the second direction. The third conductive layer extends in a direction crossing the first direction.

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Номер записи: 98
27-02-2020 дата публикации

Phase change memory with a dielectric bi-layer

Номер: US20200066977A1
Автор: Injo OK, Iqbal Rashid Saraf, Kevin W. Brew, Nicole Saulnier, Robert Bruce
Принадлежит: International Business Machines Corp

Techniques regarding protecting a dielectric material during additive patterning of one or more phase change memories are provided. For example, one or more embodiments described herein can comprise a method, which can comprise forming a bi-layer adjacent a phase change memory element. The bi-layer can comprise a dielectric material and a capping material that can protect a thickness of the dielectric material during a patterning process.

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Номер записи: 99
27-02-2020 дата публикации

Variable resistance memory device

Номер: US20200066978A1
Автор: Gwang-Hyun Baek, Jaeho Jung, Pyojin JEON
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A variable resistance memory device includes an interlayer insulating structure on a substrate, the interlayer insulating structure having a hole, a bottom electrode in a lower portion of the hole, and a pattern in an upper portion of the hole, the pattern including at least one of a phase change pattern or an intermediate electrode, a sidewall of the pattern defining an angle with a top surface of the substrate, and the angle decreasing as a vertical distance from the substrate increases.

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Номер записи: 100