Tunnel junction via

Novel vertical diode structures with low series resistance

Mit einem Verstärker eine Baueinheit bildender Hallgenerator

Tunnel-Diode und Verfahren zu ihrer Herstellung

Verfahren zum Herstellen einer Halbleiteranordnung

Verfahren zur Herstellung von Halbleitervorrichtungen, insbesondere von Tunneldioden

Procédé de fabrication de diodes

Halbleitervorrichtung mit einem aus mehreren Bereichen unterschiedlicher Leitfähigkeit zusammengesetzten Halbleiterkörper

Verfahren zur Herstellung von Halbleitervorrichtungen

Verfahren zur Herstellung einer Halbleiteranordnung mit einem Grundkörper aus Galliumarsenid

Diode.

Working method for manufacturing electrische semiconductor institutions.

Flash memory cell and method for fabricating the same

A flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, and a source/drain region. The floating gate, disposed over the substrate and insulated from the substrate, has a plurality of hut structures. The control gate is disposed over the floating gate and insulated from the floating gate. The source/drain region is formed in the substrate. This invention further includes a method of fabricating a flash memory cell. First, a polysilicon layer and a germanium layer are successively formed over a substrate and insulated from the substrate. Subsequently, the substrate is annealed to form a germanium layer having a plurality of hut structures on the polysilicon layer to serve as a floating gate with the polysilicon layer. Next, a control gate is formed over the floating gate and insulated from the floating gate. Finally, a source/drain region is formed in the substrate.

Method of fabricating InAs/GaSb/AlSb material system SRAM

An SRAM including first and second RITDs each formed with a heterostructure including a GaSb active layer sandwiched between AlSb barrier layers, which are sandwiched between InAs layers with each RITD having a contact connected to a first of the InAs layers. A TD including an AlSb layer sandwiched between InAS layers. A second InAs layer for each of the RITDs being integrally formed with a first InAs layer of the TD and a read/write terminal connected to a second InAs layer of the TD.

DIODE

In a pn junction diode having a conductivity modulating element provided on a first principal surface of a semiconductor substrate, when an impurity concentration of a p type impurity region is lowered to shorten a reverse recovery time, hole injection is suppressed, thereby causing a problem that a forward voltage value is increased at a certain current point. Moreover, introduction of a life time killer to shorten the reverse recovery time leads to a problem of increased leak current. On an n- type semiconductor layer that is a single crystal silicon layer, a p type polycrystalline silicon layer (p type polysilicon layer) is provided. Since the polysilicon layer has more grain boundaries than the single crystal silicon layer, an amount of holes injected into the n- type semiconductor layer from the p type polysilicon layer in forward voltage application can be suppressed. Moreover, a natural oxide film formed between the n- type semiconductor layer and the p type polysilicon layer in ...

Silicon on insulator transistor structure for imbedded DRAM

To address the above-discussed deficiencies of the prior art, the present invention provides an integrated circuit formed on a semiconductor wafer, comprising a doped base substrate; an insulator layer formed over the doped base substrate; and a doped ultra thin active layer formed on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate. The present invention therefore provides a semiconductor wafer that provides a doped ultra thin active layer. The lower Ioff in the DRAM transistor allows for lower heat dissipation, and the overall power requirement is decreased. Thus, the present invention provides a lower Ioff with reasonably good ion characteristics.

Nonlinear tunnel resistor and method of manufacturing the same

An alloy for use in the manufacture of tunnel diodes (see Division H1) consists of 99 parts by weight indium, 0.5 parts gallium and 0.5 parts zinc. The tunnel diode produced by fusing this alloy to an N type germanium body is freed of surface imperfections by treatment in a slow iodide etch and then electroplated with a thin layer of nickel from an aqueous solution containing 32 ozs. nickel sulphate, 6 ozs. of nickel chloride and 4 ozs. of boric acid per gallon of water. The bath has a pH of 4.5-6.

Improvements in gallium arsenide semiconductor devices

... 967,292. Gallium arsenide tunnel diodes. GENERAL ELECTRIC CO. Sept. 22, 1961 [Sept. 26, 1960], No. 34014/61. Heading H1K. A tunnel diode comprises a gallium arsenide body containing a narrow PN junction between degenerate P and N type regions having uncompensated acceptor and donor concentrations respectively greater than 1018 atoms/c.c. but a total concentration of the rapidly diffusing impurities copper, silver and gold less than 1015 atoms/c.c. A typical device is prepared from a wafer of gallium arsenide doped to P- type degeneracy with cadmium by heating it in potassium cyanide at 650‹ C. for 30 hours. After removal from the cyanide and cooling the wafer is placed on an assembly consisting of a gold wire 9 (Fig. 2), a layer of indium-cadmium solder, a plate 2 consisting of an alloy of 54% by weight iron, 29% nickel, 17% cobalt, and a layer of indium-cadmium containing 4% by weight cadmium, and heated in hydrogen at 450‹ C. for 20 seconds. The PN junction is then formed ...

Improved method of forming tunnelling junctions in intermetallic semiconductor material

... 1,060,025. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 1, 1965 [Oct. 7, 1964], No. 41711/65. Heading H1K. A tunnel junction is produced by alloying an impurity into the surface of a body of a degenerately doped intermetallic compound for at least forty minutes. A plurality of tunnel diodes are produced from a wafer (10) of P-type GaAs doped to degeneracy with Zn by covering the surface with a layer (11) of SiO 2 , which may be covered with a thin film of glass, etching a pattern of small and large apertures (12) and (13) using a photo-masking technique and depositing a film (14), (15) of Ag or Au on the walls of each aperture (12), (13) by evaporation in vacuum using a molybdenum mask with apertures aligned with those in layer (11), Figs. 1 to 3 (not shown). The wafer may then be dippad in a flux and pre-heated on a hotplate before immersing it in a bath of molten material comprising an impurity such as Sn, Se, Te, or S, saturated with a carrier metal such ...

Improvements in and relating to semiconductive devices

... 1,139,746. Diodes. PHILCO-FORD CORP. 22 June, 1966 [22 June, 1965], No. 27886/66. Heading H1K. The PN junction of a tunnel diode lies between a mesa of one conductivity type and a smaller mesa of the opposite type. A typical device is made in multiple by coating one face of an N-type germanium wafer with aluminium, reducing this to a series of dots by etching, cutting into individual units and then flash alloying the aluminium to the germanium. After thermocompression bonding a gold wire to the aluminium residue the device is electrolytically etched in potassium hydroxide to undercut the bond and form a mesa. Subsequently the device is re-etched in oxalic acid, preferably mixed with hydrogen peroxide and a wetting agent, to preferentially remove the aluminium-alloyed region to form the second mesa of smaller cross section. The completed device is then mounted in a ceramic tube between metal end plugs.

SEMICONDUCTOR DEVICE HAVING A RECTIFYING JUNCTION AND METHOD OF MANUFACTURING SAME

The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller doping concentration than the first region (1) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions (1, 2) are each provided with a connection conductor (3, 4). Such a device can very suitably be used as a switching element, in particular as a switching element for a high voltage and/or high power. In the known device, the silicon-germanium mixed crystal is relaxed, leading to the formation of misfit dislocations. These serve to reduce the service life of the minority charge carriers, thus enabling the device to be switched very rapidly. In a device in accordance with the invention, the entire first region (1) comprises a mixed crystal of silicon and germanium, and the germanium content and the thickness ...

Optical controlled resonant tunneling oscillator

An optical controlled resonant tunneling oscillator utilizing an oscillation variation characteristic of a resonant tunneling oscillator in accordance with a negative differential resistance, a series resistance and a static capacitance varied with an intensity of light when the light is incident on a resonant tunneling device having a double barrier quantum well structure and a method for fabricating the same are disclosed. The oscillator can modulate the frequency 2 or 3 levels in response to an intensity of an incident light as compared with the method of a conventioal photoelectric system that modulates the frequency in response to ON/OFF of an electric signal, thereby simplifying the system. The oscillator controls the resonant tunneling at the high speed by light, thereby enabling processing a signal of tens to hundreds GHz.

Method of fabricating InAs/GaSb/AlSb material system SRAM

An SRAM including first and second RITDs each formed with a heterostructure including a GaSb active layer sandwiched between AlSb barrier layers, which are sandwiched between InAs layers with each RITD having a contact connected to a first of the InAs layers. A TD including an AlSb layer sandwiched between InAS layers. A second InAs layer for each of the RITDs being integrally formed with a first InAs layer of the TD and a read/write terminal connected to a second InAs layer of the TD.

Magnetic tunneling junction element having thin composite oxide film

A tunneling junction element comprises: a substrate; a lower conductive layer formed on the substrate; a first oxide layer formed on the lower conductive layer and having a non-stoichiometric composition;a second oxide layer formed on the first oxide layer and having a stoichiometric composition; and an upper conductive layer formed on the second oxide layer, wherein the first oxide layer is oxidized during a process of forming the second oxide layer and has an oxygen concentration which is lower than an oxygen concentration of the second oxide layer and lowers with a depth in the first oxide layer, and the first and second oxide layers form a tunneling barrier.

Method for growing high-quality crystalline Si quantum wells for RTD structures

A method of forming a crystalline silicon well over a perovskite barrier layer, preferably for use in formation of a resonant tunneling diode. A silicon substrate (1) is provided of predetermined crystallographic orientation. A layer of crystallographic perovskite material (5) is formed over the silicon substrate and substantially matched to the lattice constant of the silicon substrate. A layer of crystallographic silicon (7) is formed over the perovskite layer substantially matched to the lattice constant of the perovskite layer. The perovskite layer is formed by the steps of placing the silicon substrate in a chamber and then evaporating a layer of barium strontium oxide (3) thereon with a thickness of from about three to about six Angstroms and then evaporating a layer of calcium strontium titanate (5) thereon having a thickness of from about six to about 25 Angstroms thereon in the case of a tunneling diode. A second layer of silicon oxide (9) is provided on the layer of silicon remote ...

Method of fabricating organic light emitting diode device

A method of fabricating an organic electroluminescent device. A substrate comprising an organic electroluminescent unit thereon is provided. A passivation layer is formed on the substrate to cover the organic electroluminescent layer. An ion beam is provided to perform a surface treatment on the passivation layer. A plastic layer is formed on the passivation layer. The steps of forming the passivation layer, providing the ion beam and forming the plastic layer are repeated at least once to enhance device reliability. In addition, a solid passivation layer is formed by the steps of forming the passivation layer, providing the ion beam and forming the plastic layer.

SILIZIUM-GERMANIUM-HALBLEITERANORDNUNG UND VERFAHREN ZUR HERSTELLUNG

Esaki-Diode und Verfahren zu ihrer Herstellung

Improvements in semiconductor devices

... 940,520. Semi-conductor devices. GENERAL ELECTRIC CO. Jan. 19, 1962 [Jan. 23, 1961], No. 2019/62. Heading H1K. A tunnel diode comprises a heavily impregnated body 1, Fig. 3, having at one of its surfaces a small regrown area 2, has a layer of dielectric material 6 surrounding the regrown area, and a continuous metallic layer 7 deposited on the dielectric material and having electrical contact with the regrown area. As shown, the body 1 of N-type material such as germanium heavily doped with phosphorus is alloyed with a pellet 4 consisting of indium containing 2% gallium to form a P-N junction 5. A metallic base layer 8 is then deposited on the surface, using a mask to prevent this layer from contacting the regrown region. The dielectric layer is then deposited over the whole of the area surrounding the pellet 4 and the metallic layer 7 is then deposited over the whole area to contact the pellet 4. External contacts are established via the layer 7 and either the layer 8 or the body 1. In ...

Multiple junction semiconductor devices

... 916,889. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 22, 1960 [Dec. 30, 1959], No. 44023/60. Class 37. A semi-conductor structure comprises zones of alternate conductivity types meeting at PN junctions which are alternately of tunnel and normal type. The arrangement provides a device having a current-voltage characteristic as shown in Fig. 5. The tunnel junctions have successively increasing impurity concentrations to provide characteristics with successively increasing values. The arrangement may also be used to provide a photo-electric voltage provided by the normal junctions which are effectively connected in series by the tunnel junctions. Fig. 4 shows the device with tunnel junctions 12a-12d and normal PN junctions 13a-13c. The device may be manufactured by epitaxial deposition as described in Specification 916,887 such as by providing sources of germanium, iodine and gallium tri-iodide which deposit on a substrate of germanium. The resistivity of the ...

Semiconductor device and method of making it

The following alloys (composition by weight) are used in the fabrication of semi-conductor devices (see Division H1): 98% indium, 2% gallium; and 96% silver, 2% gallium, 2% indium.

Improvements in methods of producing semi-conductor arrangements

... 923,801. Coating with metals; coating by vapour dep sition. SIEMENS & HALSKE A.G. June 13, 1961 [June 13, 1960], No. 21279/61. Class 82. [Also in Group XXXVI] A PN junction is made by deposition of semi-conductor material on a substrate in two stages from a gaseous mixture containing a decomposable compound of the semi-conductor and, in the first stage a donor (acceptor) impurity to form an N(P) layer, and in the second stage an acceptor (donor) impurity to form a P(N) layer. The layers are each less than 500Š thick and the impurities and the temperature of the substrate and rate of deposition in the second stage are so selected that the density of the minority impurity at the side of each region remove from the PN junction resulting from interfacial diffusion is not more than half the density of the same impurity in the other region. A tunnel diode is made in the apparatus shown in Fig. 1 using a monocrystalline silicon substrate 1 on a monocrystalline semi-conductor support 4. The wafer ...

Improvements in forming semiconductor devices

A tunnel diode is formed by epitaxially depositing, in a closed container, a layer of semi-conductor of one conductivity type on a substrate of the opposite conductivity type by vapour deposition from a gaseous compound of the semi-conductor element and a transport element as in the parent Specification, the resulting junction being heat treated, either before, or during, the alloying of ohmic contacts thereto, to increase the ratio of peak to valley currents of the current voltage characteristic of the diode. In examples, germanium is deposited on germanium or gallium arsenide bodies which are then heat treated for 20 seconds-10 minutes at 665 DEG C.

Tunnel junction via

A Process for the Production of Semiconductor Diodes

1,196,515. Semi-conductor devices. C.I.T. COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS. 15 March, 1968 [18 April, 1967], No. 12746/68. Heading H1K. A plurality of diodes is formed in a common substrate of material of one conductivity type by depositing an insulating layer over the substrate, forming apertures of the same or different sizes in the layer to expose areas of the substrate, depositing a dopant of opposite type in each aperture and then applying electric pulses between the dopant in individual apertures and the substrate to form diode junctions of similar or differing characteristics which may subsequently be divided from the substrate. In the embodiment tunnel diodes are formed on a substrate of heavily doped N-type germanium, silicon or gallium arsenide using silicon dioxide as the insulator and vapour deposited aluminium as dopant. After pulsing, elements containing one or a group of junctions are separated from the substrate by scribing.

Insulating films with tunnel effect with stable characteristics in time and their process of preparation

PROCESS OF FORMING P-N LAYER

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification.

Process for fabricating integrated devices including nonvolatile memories and transistors with tunnel oxide protection

A process for simultaneously fabricating memory cells, transistors, and diodes for protecting the tunnel oxide layer of the cells, using the DPCC process wherein the first polysilicon layer is not removed from the transistor area, and the gate regions of the transistors are formed by shorted first and second polysilicon layers. To form the diodes, the polyl layer is removed from the active areas in which the diodes are to be formed, using the same mask employed for shaping polyi; the interpoly dielectric layer and the gate oxide layer are removed from the active areas of the diodes, using the same mask employed for removing the dielectric layer from the transistor area; a second polysilicon layer is deposited directly on to the active areas of the diodes; and the poly2 doping ions penetrate the active areas to form N+ regions which, together with the substrate, constitute the protection diodes. The diodes are thus formed prior to shaping poly2, and are connected to the control gates of ...

Resonant tunneling structure and fabrication methods

A resonant tunneling diode (400) with lateral carrier transport through tunneling barriers (404, 408) grown as a refilling of trenches etched into a transverse quantum well (410) and defining a quantum wire or quantum dot (406). The fabrication method uses angled deposition to create overhangs at the top of openings which define sublithographic separations for tunneling barrier locations. ...

Improvements in and relating to the manufacture of tunnel diodes

An alloy used in the manufacture of tunnel diodes (see Division H1) consists of 5-15% by weight copper, 1% of each of sulphur, selenium and tellurium, and the residue indium. A typical alloy contains 90 parts of indium, 10 of cooper and 1 each of sulphur, selenium and tellurium.

Semiconductor device

... 908,690. Semi-conductor devices. WESTING- HOUSE ELECTRIC CORPORATION. April 13, 1961 [May 16, 1960], No. 13325/61. Class 37. In a diode with a PNP or NPN zone configuration and ohmic contacts to the outer zones one of the PN junctions has an Esaki diode negative resistance characteristic and the other a backward diode characteristic. The resultant characteristic of the device, Fig. 3, has the forward Esaki diode characteristic for one direction of bias and the forward characteristic of the backward diode in the opposite direction. Such a diode is made by diffusing donor impurities into a nearly degenerate N-type semi-conductor wafer to form a degenerate surface region, etching away this region from one face of the wafer, and then alloying acceptor material into both faces to form degenerate P-type zones making narrow PN junctions with the wafer. The wafer may be of silicon, germanium, gallium arsenide, gallium phosphide or indium antimonide.

Semiconductor circuit elements

... 989,118. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. April 18, 1962 [April 20, 1961], No. 15036/62. Heading H1K. [Also in Division H3] A circuit element has a body with two or more adjoining semi-conductive portions, the two adjoining portions, or an adjoining two of the portions, being of different basic semiconductor material; the body also has a region of semi-conductive material which adjoins each of the portions of the body and forms a rectifying junction with at least one of them. The embodiment shown in Fig. 2 has an intrinsic portion 3 of GaAs (pn 5 x 106 ohm.cms.) on which an N+ Ge portion 2 is epitaxially deposited. A large area ohmic contact 5 is provided on the lower face of the composite body. To the upper surface of the body is alloyed a pellet 4 of a Ga/Sn alloy. The Ga converts the recrystallized Ge region 6 to P+ conductivity, thus producing a Ge tunnel diode supported by intrinsic GaAs (except for a small region 7 converted to N+ conductivity ...

Method of Manufacture of Tunnel Diodes of Gallium Arsenide

... 1,179,420. Tunnel diodes. N. PUYCHEVRIER, and M. MENORET. 3 Oct., 1967 [3 Oct., 1966], No. 44899/67. Heading H1K. A tunnel diode comprising a heavily-doped N-type GaAs plate I having fused thereto a Zncovered Cu wire 2 is manufactured by placing the Zn-covered wire 2 in contact with the doped GaAs plate and then applying a reverse-biasing voltage pulse between the plate 1 and wire 2 of such amplitude and duration that the pulse ceases when the current flowing reaches a predetermined value whereby the wire 2 is fused to the plate 1 and a P-type impurity in the form of zinc is diffused into the plate I to form a junction therein. The plate 1 containing 1019 atoms. cm.-3 of selenium is initially soldered by a Sn-Pb solder to copper wire 11 while galvanized copper wire 12 is soldered to the wire 12. Wires 11 and 12 are supported within a glass bead 10. After formation the tunnel diode is varnished and encased.

Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization ...

SILIZIUM-GERMANIUM-HALBLEITERANORDNUNG UND VERFAHREN ZUR HERSTELLUNG

Halbleiterbauelement mit mindestens einem PN-UEbergang

Semiconductor device and method of producing it

... 997,228. Semi-conductor rectifiers. STANDARD TELEPHONES & CABLES Ltd. Dec. 21, 1961 [Dec. 22, 1960], No. 45852/61. Heading H1K. By forming a high doped semi-conductor body 1 and an electrode 4 with a coating 6 containing an impurity of opposite conductivity type to the body so that they have an area of contact small relative to the maximum cross-section of the body 1, and heating the assembly to melt the coating 6, a small PN junction is formed at the same time as the body 1 is attached to the electrode 4. By this means the capacitance of the junction and the series resistance provided by the body 1 are kept small and conditions necessary for a tunnel diode are fulfilled. At the same time as electrode 4 is attached a second electrode 5 may be attached, a coating 7 of the same conductivity type as the body 1 being used to effect an ohmic contact with the body. The electrodes 4 and 5 are of silver or copper, the coating 6 is an alloy of 95% tin and 5% arsenic, the coating 7 is of tin, and ...

Improvements in and relating to semiconductor devices

... 921,264. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 2, 1960 [Aug. 5, 1959], No. 15286/60. Class 37. A semi-conductor device comprises a continuous PN junction of which part has an Esaki diode characteristic and another part a normal junction diode characteristic. The essential constructional features of an Esaki diode are that the valence band in the P-type region overlaps the conduction band in the N-type region, and that the distance between the regions is small enough to allow electrons to tunnel between the bands, e.g. 150 Š or less. In one example a transistor, Fig. 5, comprises degenerate P and N regions 15, 16, non-degenerate N and P regions 13, 12 and ohmic contacts 17, 18, 19. The emitter current-voltage characteristic 28a, 28b, between emitter contact 18 and base contact 17 is the sum of the characteristic 26a 26b, of an Esaki diode and that 27a, 27b, of a conventional diode, as shown in Figs. 6A and 6B. Fig. 6A represents the situation where the ...

Method of fabricating and contacting ultra-small three terminal semiconductor devices

Ultra-small three terminal semiconductor devices and a method of fabrication including patterning the planar surface of a substrate and a control layer to form a first and second pattern edge and consecutively forming a plurality of layers of semiconductor material in overlying relationship to the pattern edges so that a discontinuity is produced in the layers and a first layer on one side of the pattern edge is aligned with and in electrical contact with a different layer on the other side of the pattern edge.

High performance PD SOI tunneling-biased MOSFET

A new type of partially-depleted SOI MOSFET is described in which a tunneling connection between the gate and the base is introduced. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made somewhat longer than normal and a region near one end is implanted to be P+ (or N+ in a PMOS device). This allows holes (electrons for PMOS) to tunnel from gate to base. Since the hole current is self limiting, applied voltages greater than 0.7 volts may be used without incurring excessive leakage (as is the case with prior art DTMOS devices). A process for manufacturing the device is also described.

TUNNEL JUNCTION VIA

A memory device comprising a plurality of tunnel junctions (TJs) includes a bottom wiring layer; a top wiring layer; a plurality of TJs contacting the bottom wiring layer and the top wiring layer; and a plurality of tunnel junction vias (TJVs) contacting the bottom wiring layer and the top wiring layer, wherein the plurality of TJVs each have a lower resistance the each of the plurality of TJs, wherein the plurality of TJVs comprise at least one concave surface, and wherein the at least one concave surface of the plurality of TJVs is configured to trap etched material during formation of the TJVs so as to reduce the resistance of the plurality of TJVs.

Halbleitervorrichtung

Improvements in or relating to semiconductive devices

... 964,325. Semi-conductor devices. WESTERN ELECTRIC CO. Inc. Sept. 22, 1960 [Sept. 29, 1959], No. 32604/60. Heading H1K. A device exhibiting a negative resistance region in its forward characteristic comprises a semi-conductor body of one conductivity type with two spaced regions of the opposite conductivity type forming PN junctions therewith, one of which has the characteristics of a tunnel diode and the other of which rectifies in the opposite sense to a conventional PN junction. A typical device is made from a 0.001 ohm cm. N-type silicon wafer. After etching in a mix of concentrated nitric and hydrofluoric acids and rinsing successively in de-ionized water and methyl alcohol the wafer is placed on a tantalum strip heater with the ends of wires 14, 15 pressed lightly against it, heated for 4 seconds in helium at above the eutectic temperatures of the wires and silicon, and then cooled rapidly in a blast of compressed air. Wire 14 of aluminium is 5 mils in diameter and is spaced 20 mils ...

Manufactoring process of the diodes by electric impulses

INTEGRATED CIRCUIT RESISTOR FABRICATION METHOD

A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least ...

Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization ...

Polycrystalline silicon diode string for ESD protection of different power supply connections

An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit has a string of serially connected lateral polycrystalline silicon diodes characterized by consistent turn-on threshold voltage level such that as the number of stage of the ESD protection circuit increase, the turn-on voltage threshold of the ESD protection circuit increase linearly.

Formierung von Halbleitern

Verfahren zur Verbesserung der elektrischen Eigenschaften des duennen, isolierenden durch-tunnelbaren Filmes eines elektronischen Fest-koerperbauelementes

Semiconductor devices and methods of manufacturing them

... 1,058,036. Semi-conductor devices. RADIO CORPORATION OF AMERICA. Oct. 29, 1964 [Nov. 26, 1963], No. 44247/64. Heading H1K. A semi-conductor PN junction device is made by masking a limited area of a wafer of one conductivity type, the area having a peripheral notch, depositing material of the opposite conductivity type over the unmasked area including the notch to form the junction, depositing metal over the masked area and over the deposited material in the notch, removing part of the material within the notch and finally providing contacts to opposite sides of the junction. Typically tunnel diodes are made by masking notched areas 14 (Fig. 2) on a degenerately doped N-type germanium wafer 10 with evaporated silicon monoxide, magnesium fluoride or oxide, or with a colloidal suspension of magnesium hydroxide. Degenerate N-type germanium is epitaxially deposited over the unmasked area and then one or more metals such as chromium, aluminium or gold are evaporated through a mask to cover the ...

Semiconductor devices

... 972,820. Semi-conductor devices. RADIO CORPORATION OF AMERICA. Feb. 22, 1962 [March 17, 1961], No. 7010/62. Heading H1K. A semi-conductor body 10 with a PN junction formed by an impurity layer 13 and having an electrode pellet 16 ohmically connected to the impurity layer is shaped by removing material from the body except for material underneath the electrode pellet. The body may be of Ge, Si, InP, or GaAs, but is preferably Ge with sufficient Ga to give 8 x 1019 to 5 x 1020 charge carriers/cm.3 The impurity layer may be diffused into the surface of a larger body from which body 10 is cut or may be produced by flooding the surface with a melt of 50 gm. of lead-tin alloy containing 2 gm. germanium arsenide. The electrode pellet 16 may be of gold, lead or tin or lead-tin alloy and is preferably lead with the donor antimony. The body is mounted in an insulating ring 18 between nickel-iron-cobalt gold plated plates 15 and 19. Plate 19 has a prong 17 cut out of its ...

Improvements in or relating to the manufacture of semiconductor devices

... 916,887. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 6, 1960 [May 28, 1959], No. 16151/60. Drawings to Specification. Class 37. [Also in Group II] A semi-conductor device is made in a closed container by forming a gaseous compound of a semi-conductor material and a transport element and epitaxially depositing a layer of the semi-conductor material from the compound on to a substrate of semi-conductor material. In the examples, (A) N-type germanium substrates are coated with P-type germanium using germanium tetraiodide or iodine as transport element, and (B) N-type and P-type silicon substrates are coated with pure silicon using iodine as transport element. Before coating, the substrate is preferably " etched " by raising its temperature to above that of the rest of the container so that it reacts with vaporized transport element. Reference is also made to (i) the production of NPIN structures by successive deposition of P-, I- and N-type materials on to an N-type ...

Manufactoring processes of devices semiconductors and circuits using these devices

METHODS OF MAKING SEMICONDUCTOR STRUCTURES INCLUDING VERTICAL DIODE STRUCTURES

Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Method of fabricating DRAM cell with self-aligned contact

A structure and method are provided for reducing DRAM cell area by eliminating the contact-to-gate spacing requirement while increasing the capacitor area by designing the capacitor to extend inside the contact, without sacrificing the sidewall capacitance. The new structure uses a self-aligned contact where the contact can overlap the gate region in the layout.

Method of forming an SRAM

A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least a portion of the spacer outer surface; g) providing a conformal layer of a semiconductive material over the exposed outer spacer surface and over the inner spacer surface, the conformal layer making electrical connection with the node; and h) patterning the conformal layer into a desired resistor shape. SRAM and other integrated circuitry incorporating this and other resistors is disclosed.

Flash memory cell and method for fabricating the same

A flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, and a source/drain region. The floating gate, disposed over the substrate and insulated from the substrate, has a plurality of hut structures. The control gate is disposed over the floating gate and insulated from the floating gate. The source/drain region is formed in the substrate. This invention further includes a method of fabricating a flash memory cell. First, a polysilicon layer and a germanium layer are successively formed over a substrate and insulated from the substrate. Subsequently, the substrate is annealed to form a germanium layer having a plurality of hut structures on the polysilicon layer to serve as a floating gate with the polysilicon layer. Next, a control gate is formed over the floating gate and insulated from the floating gate. Finally, a source/drain region is formed in the substrate.

Improvements in or relating to tunnel diodes

... 1,060,755. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 27; 1964 [June 28, 1963], No. 21924/64. Heading H1K. A process for increasing the peak current of a tunnel diode comprises passing a current in the forward direction through the diode while monitoring its current-voltage characteristic and increasing the forward current until an initial increase in the peak current is observed. As shown, Fig. 4, a tunnel diode 4 is produced by alloying a dot 3 comprising an alloy of indium, copper, selenium, tellurium and sulphur to the surface of a wafer 2 of gallium arsenide doped with zinc. The device, is chemically etched to reduce the junction to the desired diameter and is then connected in the circuit shown. A forward current supplied by source 13 is switched through diode 4 by an electronic switch 9 operating at 100 kc/s. with a 10: 1 duty cycle. During the part of the cycle in which source 13 is disconnected a curve tracer 10a is connected to diode 4 and the currentvoltage ...

Formation of a semiconductor device

Preparation of time stable tunneling diode films

PROCESS OF FORMING P-N LAYER

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification.

Method of forming a resistor

A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least ...

Integrated circuits and SRAM memory cells

The invention encompasses integrated circuits and SRAM cells. In one aspect, the invention includes an integrated circuit comprising: a) an electrically insulative pillar extending substantially vertically outward of an underlying layer, the pillar having opposing substantially vertical side surfaces and a top, the pillar being taller than it is wide; b) a resistor comprising a layer of material which extends along both pillar vertical surfaces and over the top of the pillar; c) a first node in electrical connection with the resistor on one side of the insulative pillar; and d) a second node in electrical connection with the resistor on the other side of the insulative pillar.

SEMICONDUCTOR DIODE AND METHOD OF PRODUCING SAME

Improvements in or relating to semi-conductor structures

... 989,205. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 15, 1962 [Nov. 15, 1961], No. 43170/62. Heading H1K. A semi-conductor device consists of a semiconductor body comprising a thin region of one conductivity type extending the full width of the body between two regions of high resistivity, and a region of opposite conductivity type in contact with the other three regions on one face of the body and forming a PN junction extending only part way across the body. In the embodiment (Fig. 1) a region 3 of degenerate N-type material formed by diffusion of arsenic into the germanium waver, is sandwiched between two regions 2 and 4 of high resistivity or substantially intrinsic germanium. A dot of acceptor material 5, e.g. gallium is then alloyed on to the crystal surface to form a region 6 (Fig. 1b of degenerate P-type defining with one surface of the sandwich layer 3 a P+N+ junction. The tunnel junction so formed has only a small proportion of its perimeter exposed ...

Method for increasing efficiency of thermotunnel devices

Semiconductive tunnel-effect devices

... 997,965. Semi-conductor devices. WESTERN ELECTRIC CO. Inc. Sept. 5, 1961 [Sept. 6, 1960], No. 31852/61. Heading H1K. In a tunnel effect device with an improved peak-valley current ratio degenerate P and N- type zones are separated by a thin layer of a material with an energy gap at least 3 electron volts less than that of either the P or the N-type zone. The effective electron mass in the layer material which may be intrinsic or N or P-type should be as small as possible. In addition, to avoid high concentrations of recombination centres at the interfaces between the layer and the zones, the lattice constants and orientation of adjoining layers should match sufficiently to produce not more than one dislocation per 20 atoms at either interface, e.g. lattice constants should match to within 5% and the crystallographic orientations to within 3 degrees. Suitable materials for the thin layer, which is preferably 10-300 Š thick, are indium antimonide in association with P and N zones of cadmium ...

Manufactoring process of diodes tunnel out of gallium arsenide

Vertical diode structures

A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Static memory cell and method of manufacturing a static memory cell

A static memory cell having no more than three transistors. A static memory cell is formed by providing a semiconductor substrate; forming a buried n-type layer in the substrate, the n-type layer having a first average n-type dopant concentration of at least 1.times.10.sup.16 ions/cm.sup.3 ; forming an n-channel transistor relative to the substrate over the buried n-type layer, the n-channel transistor having a source, a gate, and a drain, the source having a second average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3 and the drain having a third average n-type dopant concentration of at least 1.times.10.sup.19 ions/cm.sup.3, and the source having a depth deeper than the drain so as to be closer to the buried n-type layer than the drain; and forming a p-type region in junction with the source to define a tunnel diode between the p-type region and the source.

Improvements in or relating to tunnel diodes

... 985,382. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. Aug. 29, 1962 [Sept. 18, 1961], No. 33204/62. Heading H1K. A tunnel diode is produced by alloying a pellet formed of 0.1 to 5% As, 0.1 to 10% Sb, 15 to 18% Sn and balance Pb to the surface of a P-type germanium body which may contain gallium in a concentration of between 1019 and 1020 atoms per cm.

Tunnel junction via

A method for forming a tunnel junction, or TJ, circuit, the method includes forming a bottom wiring layer (308); forming a plurality of TJs (301) contacting the bottom wiring layer; forming a plurality of tunnel junction vias, or TJVs (305), simultaneously with the formation of the plurality of TJs, the TJVs contacting the bottom wiring layer; and forming a top wiring layer (310) contacting the plurality of TJs and the plurality of TJVs. A circuit comprising a plurality of tunnel junctions includes a bottom wiring layer contacting the plurality of TJs, the bottom wiring layer further contacting a plurality of tunnel junction vias, wherein the plurality of TJs and the plurality of TJVs comprise the same material; and a top wiring layer contacting the plurality of TJs and the plurality of TJVs.

Improvements in and relating to the epitaxial deposition of semi-conductor material

... 916,888. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. Sept. 20, 1960 [Dec. 31, 1959], No. 32266/60. Class 37. [Also in Group II] In a method of making a semi-conductor with a narrow PN junction (e.g. a tunnel diode) by the deposition of for instance N-type germanium on a substrate of, for instance, P-type germanium, a halide decomposition process is used (see Group II). The process is carried out in a closed container which has three zones which can be temperature-controlled by coils 2a, 2b and 2c. In a first period of time the substrate is etched by the carrier (e.g. iodine) which also attacks the source 3. In a second period of time germanium is deposited on the substrate from vapour 6. Specification 916,887 is referred to.

Improvements in semiconductor devices and method of fabricating the same

An alloy used in making tunnel diodes (see Group XXXVI) consists of indium containing 2% atomic of gallium.

A tunnel diode and a process for its production

An alloy used in making semi-conductor devices (see Division H1) consists of tin containing 0.1-2% by weight zinc. Other alloys suggested are alloys of tin with up to 10% by weight cadmium, of indium with a total of up to 10% by weight of zinc and/or cadmium, and of tin with up to 10% by weight of germanium, silicon, sulphur, selenium, or tellurium. Specification 757,672 is referred to.

Manufactoring process of the diodes tunnel and product obtained by this process

Solid-state imaging device and manufacturing method for solid-state imaging device

A solid-state imaging device, comprises: a semi-conductor substrate demarcating a two-dimensional surface; a multiplicity of photoelectric conversion units formed being arranged in a plurality of rows and columns on the semiconductor substrate; a planarizing insulating film formed above the semiconductor substrate; and a plurality of gap-less microlenses having spectral characters, each gap-less microlens being formed above each of the photoelectric conversion units with the planarizing insulating film placed in-between.

DIODE

PROBLEM TO BE SOLVED: To provide a method for reducing a reverse recovery time (trr) for discharging the accumulated charge amount, with respect to a pn junction diode that achieves high-speed switching time. SOLUTION: A p-type polysilicon layer 7 is disposed on a n-type semiconductor layer 2 which is a single crystal silicon layer. The amount of a hole that is implanted in the n-type semiconductor layer 2 from the p-type polysilicon layer is controlled at forward voltage application since there exists much grain boundary in the polysilicon layer. Also, the amount of the hole implanted in the n-type semiconductor layer 2 is reduced depending on a natural oxide film formed between the n-type semiconductor layer 2 and p-type polysilicon layer 7. This results in reducing the time required for extracting the hole, i.e., the reverse recovery time (trr) at backward voltage application without using a lifetime killer. COPYRIGHT: (C)2009,JPO&INPIT ...

Halbleiterdoppeldiode mit zwei einander beruehrenden gleich dotierten Zonen mit unterschiedlichem Wert der Leitfaehigkeit

Improvements in or relating to semiconductive circuit elements

... 987,708. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. June 12, 1962 [June 12, 1961], No. 22500/62. Heading H1K. A unitary semi-conductor device contains in parallel a tunnel junction and a different type of junction such as a normal rectifying junction or a backward junction. As shown in Fig. 1 a semi-conductor body, apparently of germanium, originally all of N+ conductivity has produced therein, for example by vapour diffusion of arsenic, a degenerate region 3. A material containing an acceptor impurity such as gallium is alloyed to the body and forms a tunnel junction 6 with the degenerate region and depending on the degree of doping of the original body forms either a normal rectifying junction or a backward diode junction with region 2. Leads are attached to a large area ohmic contact 8 bridging the two N-type regions and to the alloyed material 4. The forward characteristic of the device over its operating region is dominated by the behaviour of the tunnel junction ...

Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures

Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures

Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures

Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures

Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures

Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures

Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Method for fabricating transistorless, multistable current-mode memory cells and memory arrays

A transistorless memory cell for storing information as one of two possible bistable current states comprises (i) at least one first transistorless device exhibiting N-type negative differential resistance, including a high-impedance region, a low-impedance region and a negative-resistance region and having a polarity and (ii) at least one second transistorless device exhibiting an exponential or linear current-voltage characteristic and coupled to the first transistorless device. The read/write operation of the transistorless memory cell is performed in a current mode. A method for fabricating a self-aligned, three-dimensional structure of memory cells comprises the steps of (i) forming a first conducting layer, (ii) forming a first semiconductor layer above the first conducting layer, (iii) forming a second semiconductor layer above the first semiconductor layer, (iv) patterning the second semiconductor layer, (v) etching the second semiconductor layer, the first semiconductor layer and the first conducting layer, (vi) forming a second conducting layer above the second semiconductor layer, (vii) patterning and etching the second conducting layer, and (viii) etching the second semiconductor layer using the second conducting layer as a mask to form multiple semiconducting devices of a second kind, and etching the first semiconductor layer using the second conducting layer as a mask to form multiple semiconducting devices of a first kind.

Light-emitting diode device and method for fabricating the same

一种发光二极管装置及其制造方法，该发光二极管装置包括：一半导体基板，该半导体基板上设置有一发光二极管芯片；至少两个分隔的外部导线层，设置于该半导体基板的一底面上且电性连结于该发光二极管芯片；以及一透镜模块，黏着于该半导体基板的一顶面上，以覆盖该发光二极管芯片。在一实施例中，该透镜模块包括：一玻璃基板，该玻璃基板的一第一表面上形成有一第一凹穴；一荧光层，形成于该第一凹穴内的该第一表面的一部分上并相对于该发光二极管芯片；以及一模塑透镜，形成于该玻璃基板的与该第一表面相对的一第二表面上。本发明的发光二极管装置可改善荧光层的均匀性，并能够降低制造成本，以及提高产品的产出率。

Formation of a semiconductor device

Computer logic device consisting of an array of tunneling diodes,isolators and short circuits

Integrated circuit resistor manufacturing method

반도성 물질로부터 저항기를 형성하는 반도체 처리 방법이, a) 저항기와의 전기적 접속이 이루어질 노드를 제공하는 단계; b) 상기 노드의 바깥쪽으로 제1 전기 절연성 물질을 제공하는 단계; c) 상기 노드의 바깥쪽으로 상기 제1 전기 절연성 물질 내에 노출된 수직 측벽을 제공하는 단계; d) 상기 제1 물질의 바깥쪽으로 그리고 상기 제1 물질 수직 측벽 위에 제2 전기 절연성 물질을 제공하는 단계로서, 상기 제1 및 제2 물질들은 서로에 대하여 선택적으로 에칭 가능하며; e) 상기 제1 물질에 대하여 선택적으로 상기 제2 물질을 이방성 에칭하여 상기 제1 물질 수직 측벽 위에 실질적으로 수직으로 연장하는 측벽 스페이서를 형성하고 상기 측벽 스페이서에 인접한 상기 제1 물질을 바깥쪽으로 노출시키는 단계로서, 상기 스페이서는 안쪽 표면 및 바깥쪽 표면을 가지며; f) 상기 제2 물질에 대하여 선택적으로 상기 제1 물질을 에칭하여 상기 스페이서 바깥쪽 표면의 적어도 일부를 바깥쪽으로 노출시키는 단계; g) 상기 노출된 바깥쪽 스페이서 표면 위에 그리고 상기 안쪽 스페이서 표면 위에 반도성 물질의 컨포멀한 층(conformal layer)을 제공하는 단계로서, 상기 컨포멀한 층은 상기 노드와 전기적으로 접속하며; h) 상기 컨포멀한 층을 소정의 저항기 형태로 패터닝하는 단계를 포함한다. 이런 저항기 및 다른 저항기들을 통합한 SRAM 및 기타 집적 회로가 개시되어 있다. A semiconductor processing method of forming a resistor from a semiconducting material, the method comprising: a) providing a node to be electrically connected with the resistor; b) providing a first electrically insulating material out of the node; c) providing a vertical sidewall exposed in said first electrically insulating material outwardly of said node; d) providing a second electrically insulating material outwardly of the first material and above the first material vertical sidewalls, the first and second materials being selectively etchable with respect to each other; e) anisotropically etching the second material with respect to the first material to form a sidewall spacer that extends substantially perpendicularly over the first material vertical sidewall and to expose the first material outwardly adjacent the sidewall spacer. As a step, the spacer has an inner surface and an outer surface; f) selectively etching the first material relative to the second material to expose at least a portion of the outer surface of the spacer outward; g) providing a conformal layer of semiconductive material over the exposed outer spacer surface and over the inner spacer surface, wherein the conformal layer is in electrical connection with the node; h) patterning the ...

Quantum tunneling devices and circuits with lattice- mismatched semiconductor structures

Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials, using heter- epitaxy, in particular epitaxial necking.

Process for fabricating integrated devices including nonvolatile memories and transistors with tunnel oxide protection

A process for simultaneously fabricating memory cells, transistors, and diodes for protecting the tunnel oxide layer of the cells, using the DPCC process wherein the first polysilicon layer is not removed from the transistor area, and the gate regions of the transistors are formed by shorted first and second polysilicon layers. To form the diodes, the polyl layer is removed from the active areas in which the diodes are to be formed, using the same mask employed for shaping polyi; the interpoly dielectric layer and the gate oxide layer are removed from the active areas of the diodes, using the same mask employed for removing the dielectric layer from the transistor area; a second polysilicon layer is deposited directly on to the active areas of the diodes; and the poly2 doping ions penetrate the active areas to form N+ regions which, together with the substrate, constitute the protection diodes. The diodes are thus formed prior to shaping poly2, and are connected to the control gates of the cells by the second polycrystalline silicon layer strips forming the word lines.

Semiconductor diode and method of producing same

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Super bright light emitting diode of nanorod array structure having InGaN quantum well and method for manufacturing the same

An GaN light emitting diode (LED) having a nanorod (or, nanowire) structure is disclosed. The GaN LED employs GaN nanorods in which a n-type GaN nanorod, an InGaN quantum well and a p-type GaN nanorod are subsequently formed in a longitudinal direction by inserting the InGaN quantum well into a p-n junction interface of the p-n junction GaN nanorod. In addition, a plurality of such GaN nanorods are arranged in an array so as to provide an LED having much greater brightness and higher light emission efficiency than a conventional laminated-film GaN LED.

Semiconductor device with controlled zone thickness

Rectifying devices

Silicon germanium semiconductor device and method of manufacturing the same

(57)【要約】 トンネルダイオード(23)を有する半導体デバイスは、特に様々なアプリケーションに適している。このようなデバイスは、２個の隣接する両伝導型の半導体領域(2、3)を有していて、これらの半導体領域は、それらの間のブレークダウンがトンネリングによって伝導状態をもたらすことを可能にする高いドーピング濃度を有している。既知のデバイスの欠点は、電流-電圧特性がいくつかのアプリケーションに対してはまだ十分に急峻でないことである。本発明のデバイスでは、接合(23)に隣接している半導体領域(2、3)の部分(2A、3A)はシリコンとゲルマニウムの混晶を有する。驚くべきことに、ドーパントの量が領域(2、3)以外の部分を形成する間に供給されるドーパントと同量であると、リンとホウ素の両方のドーピング濃度が実質的に増加することが判明した。トンネル効率は、この結果、そして当該部分(2A、3A)の減少したバンドギャップとのために、実質的に改良されている。本発明のデバイスは、順方向と逆方向の両方ではるかに急峻な電流-電圧特性を有する。これは、トンネルpn接合(23)が２個の従来のダイオード、例えば、pnまたはpinダイオード、の間の遷移として使用され、積み重ねられた一体として使用されかつ本発明により一回のエピタキシャル成長で形成することができる、魅力的なアプリケーションの可能性をもたらす。トンネル接合(22)に隣接している部分(2A、3A)は、厚さ5〜30mmで、10〜50at%のゲルマニウムを含有することが望ましい。ドーピング濃度は、6 x 10 19 または10 20 at/cm 3 以上にすることができる。本発明は、本発明のデバイスを製造する簡単な方法にも関する。これは、550℃と800℃の間の温度で行われることが望ましい。

Methods of fabricating and contacting ultra-small semiconductor devices

A method of fabricating ultra-small semiconductor devices including providing a mesa on a substrate. A plurality of overlying layers of semiconductor material are grown in overlying relationship to the mesa so that a perpendicular discontinuity is produced in the layers at the mesa sidewall and the first layer overlying the mesa is in contact with the last layer overlying the substrate adjacent the mesa. A spacer of nonconductive material is formed on the discontinuity and the plurality of overlying layers are etched, using the spacer as a mask, so as to form a contact area overlying the mesa and a contact area overlying the substrate adjacent the mesa, and a semiconductor device positioned adjacent the sidewall beneath the spacer and between the contact areas.

Polycrystalline silicon diode string for ESD protection of different power supply connections

An ESD protection circuit protects integrated circuits having multiple power supply voltage sources from damage when an ESD event causes excessive differential voltages between the multiple separate power supply voltage sources. The ESD protection circuit has a string of serially connected lateral polycrystalline silicon diodes characterized by consistent turn-on threshold voltage level such that as the number of stage of the ESD protection circuit increase, the turn-on voltage threshold of the ESD protection circuit increase linearly.

Silicon oxide germanium resonant tunneling

A resonant tunneling diode (400) made of a germanium quantum well (406) with silicon oxide tunneling barriers (404, 408). The silicon oxide tunneling barriers (404, 408) plus germanium quantum well (406) may be fabricated by oxygen segregation from germanium oxides to silicon oxides.

Flash memory and its manufacturing method

Fabrication method of single electron tunelling device

SET 소자의 제작방법에 관해 개시된다. 개시된 SET 소자의 제작방법은, 절연기판 상에 소정 간격으로 이격된 소오스 전극과 드레인 전극을 형성하는 단계; 상기 소오스 전극과 드레인 전극 사이에 수 nm 두께의 금속층을 형성하는 단계; 상기 소오스 전극과 드레인 전극에 소정 전압을 인가하여 상기 금속층의 금속원자/이온의 이동에 의해 상기 소오스 전극과 드레인 전극 사이에 퀀텀도트를 형성하는 단계;를 포함한다. 이러한 방법에 따르면, 상기와 같은 본 발명에 따르면, SET 소자를 제작함에 있어서, SAM 법이나 리소그래피법에 의존하지 않고 간단한 방법에 의해 퀀텀도트를 형성할 수 있다. 따라서, 본 발명에 따르면, SET 소자는 물질에 대한 의존성이 없이 없으면서도 LSI 에 적용가능하게 된다. 뿐만 아니라, 퀀텀도트가 증착과 EM 과정에 의해 얻어지므로, 상기와 같은 잇점을 가지는 SET 소자를 대량 생산할 수 있게 된다. A manufacturing method of a SET element is disclosed. The disclosed manufacturing method of the SET device comprises the steps of forming a source electrode and a drain electrode spaced at a predetermined interval on the insulating substrate; Forming a metal layer having a thickness of several nm between the source electrode and the drain electrode; And applying a predetermined voltage to the source electrode and the drain electrode to form a quantum dot between the source electrode and the drain electrode by the movement of metal atoms / ions in the metal layer. According to this method, according to the present invention as described above, in manufacturing the SET element, the quantum dots can be formed by a simple method without depending on the SAM method or the lithography method. Thus, according to the present invention, the SET element can be applied to the LSI without being dependent on the material. In addition, since the quantum dots are obtained by deposition and EM processes, it is possible to mass-produce SET devices having the above advantages.

Integrated field effect transistor and resonant tunneling diode

This is an integrated device which comprises an integrated transistor and resonant tunneling diode where the transistor comprises a substrate 10, a buffer layer 12 over the substrate 10, and a channel layer 14 over the buffer layer 12; and the resonant tunneling diode (RTD) comprises a first contact layer 18, a first tunnel barrier layer 20 over the first contact layer 18, a quantum well 22 over the first tunnel barrier layer 20, a second tunnel barrier layer 24 over the quantum well 22, and a second contact layer 26 over the second tunnel barrier layer 24. Other devices and methods are also disclosed.

Quantum mechanical tunneling semiconductor device

976,294. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 2, 1961 [Nov. 3, 1960], No. 39212/61. Drawings to Specification. Heading H1K. A tunnel diode consists of a body of N-type conductivity indium antimonide having an alloyed junction of pure indium. The indiumantimonide is heavily doped with selenium to make it degenerate N-type and then brought into contact with the pure indium and heated to 400‹ C. for five minutes. In the alloying process the indium imparts P-type conductivity to the recrystallized junction, the narrow separation layer between the P- and N-types being the high resistance layer of intrinsic type through which tunnelling takes place. The indium serves as an ohmic contact to the recrystallized region.

Epitaxial semiconductor deposition and apparatus

Fabrication method of single electron tunelling device

SET 소자의 제작방법에 관해 개시된다. 개시된 SET 소자의 제작방법은, 절연기판 상에 소정 간격으로 이격된 소오스 전극과 드레인 전극을 형성하는 단계; 상기 소오스 전극과 드레인 전극 사이에 수 nm 두께의 금속층을 형성하는 단계; 상기 소오스 전극과 드레인 전극에 소정 전압을 인가하여 상기 금속층의 금속원자/이온의 이동에 의해 상기 소오스 전극과 드레인 전극 사이에 퀀텀도트를 형성하는 단계;를 포함한다. 이러한 방법에 따르면, 상기와 같은 본 발명에 따르면, SET 소자를 제작함에 있어서, SAM 법이나 리소그래피법에 의존하지 않고 간단한 방법에 의해 퀀텀도트를 형성할 수 있다. 따라서, 본 발명에 따르면, SET 소자는 물질에 대한 의존성이 없이 없으면서도 LSI 에 적용가능하게 된다. 뿐만 아니라, 퀀텀도트가 증착과 EM 과정에 의해 얻어지므로, 상기와 같은 잇점을 가지는 SET 소자를 대량 생산할 수 있게 된다.

Process of making tunnel diodes that results in a peak current that is maintained over a long period of time

High performance PD SOI tunneling-biased mosfet

A new type of partially-depleted SOI MOSFET is described in which a tunneling connection between the gate and the base is introduced. This is achieved by using a gate dielectric whose thickness is below its tunneling threshold. The gate pedestal is made somewhat longer than normal and a region near one end is implanted to be P+ (or N+ in a PMOS device). This allows holes (electrons for PMOS) to tunnel from gate to base. Since the hole current is self limiting, applied voltages greater than 0.7 volts may be used without incurring excessive leakage (as is the case with prior art DTMOS devices). A process for manufacturing the device is also described.

Method of manufacturing semiconductor device with a tunnel diode

A semiconductor device with a tunnel diode comprises two mutually adjoining semiconductor regions ( 2, 3 ) of opposed conductivity types having high enough doping concentrations to provide a tunneling junction. Portions ( 2 A, 3 A) of the semiconductor regions adjoining the junction comprise a mixed crystal of silicon and germanium. The doping concentration of both phosphorus and boron are substantially increased, given the same amount of dopants being offered as during the formation of the remainder of the regions. The tunneling efficiency is substantially improved, and also because of the reduced bandgap of said portions ( 2 A, 3 A). A much steeper current-voltage characteristic both in the forward and in the reverse direction is achieved. Thus, the tunneling pn junction can be used as a transition between two conventional diodes which are stacked one on the other and formed in a single epitaxial growing process. The doping concentration may be 6×10 19 or even more than 10 20 at/cm 3 . A simple method of manufacturing such a device is preferably done at a temperature between 550° C. and 800° C.

Silicon based lateral tunneling memory cell

An SRAM memory cell device is provide having a single transistor and a single RTD latch structure. The single transistor and RTD latch structure are formed on a very thin silicon layer, typically in the range of 250 to 300 Å thick, allowing for increased memory cell density over a given area. The RTD latch structure is a lateral RTD device, such that the outer contacting regions, the tunneling barriers and the central quantum well are formed side-by-side as opposed to being stacked on top of one another. This allows for formation of the memory cell device on very thin silicon layers. The layers can then be stacked to form memory devices for use with computers and the like. The memory device can be formed employing silicon-on-insulator (SOI) technology to take advantage of SOI device characteristics.

Semiconductor diode with a pn junction exhibiting a tunnel effect

Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

Gallium arsenide semiconductor devices

Tunnel diode

Integrated device manufacturing method

Process for the production of a semiconductor component with a quantum mechanical tunnel effect from n-conducting indium antimonide

Method of fabricating semiconductor devices having alloyed junctions

A METHOD OF FABRICATING ALLOYED JUNCTION SEMICONDUCTOR DEVICES IS DISCLOSED IN WHICH THE JUNCTION IS PREPARED IN THE FORM OF A MESA HAVING A PREDETERMINED POSITION AND CONFIGURATION. THE ALLOY JUNCTION IS FORMED WITHIN THAT PROTRUSION, THEREBY TO CONTROL THE SPREAD OF THE ALLOYING MATERIAL.

Silicon oxide tunnel diode structure and method of making same

Halbleiterbauelement mit einer Folge von Zonen abwechselnd entgegengesetzten Leitfaehigkeits-typs im Halbleiterkoerper und Verfahren zum Herstellen eines solchen Halbleiterbauelements

垂直共振器型面発光半導体レーザ装置

【課題】 面発光型半導体レーザと保護素子を集積化することで静電破壊電圧を向上させ、信頼性の高い半導体レーザ装置を提供する。 【解決手段】 半導体レーザ装置１は、ｎ型のＧａＡｓ基板２００上にｐ型のＧａＡｓ層２１０を含むツェナーダイオード２０と、ツェナーダイオード２０上に積層されるＶＣＳＥＬ１０とを有する。ＧａＡｓ基板２００の裏面には、ｎ側電極層２２０が形成され、ｎ側電極層２２０がＶＣＳＥＬ１０のｐ側電極層１１５に電気的に接続される。また、ｐ型のＧａＡｓ層２１０とＶＣＳＥＬのｎ型の下部ＤＢＲミラー層１０３とが電極層２３０によって電気的に接続される。 【選択図】 図２

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Verfahren zum Herstellen eines Halbleiterbauelementes

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1,053,105. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORPORATION. Aug. 18, 1964 [Aug. 19, 1963], No. 33635/64. Heading H1K. A plurality of PN junction devices are simultaneously manufactured by coating selected areas of a semi -conductor wafer of one conductivity type with metal, immersing the coated wafer in a melt saturated with said metal and containing also dopant characteristic of the opposite conductivity type, withdrawing the wafer with dopant combining material adhering to the coated areas, cooling, and then heating to form alloy junctions beneath the films. In a typical case pairs of holes 12, 13 (Fig. 3) are formed by photo-engraving in a film consisting of silicon oxide overlaid with glass (the method of making which is described) on a degenerate P-type germanium or gallium arsenide wafer. Gold, silver or, with germanium, copper is vapour deposited into the holes through an apertured molybdenum mask. After dipping in solder flux the wafer is slowly heated to 200‹ C. and then plunged into the melt. This contains a solid lump of the vapour deposited metal and consists of arsenic and tin, or arsenic, lead and tin if the wafer is germanium or of tin, tin-gold alloy, or indium or gold doped with tin, sulphur, selenium or tellurium if the wafer is gallium arsenide. After withdrawal from the melt and cooling, the wafer is reheated to 500-600‹ C. to form PN junctions beneath the holes. The metal residues are then etched away and replaced by evaporated gold contacts. which for use with germanium are doped with antimony. After annealing at 400‹ C. to reduce the peak currents of the resulting tunnel diodes the wafer is split into devices each containing one small and one large junction. The devices which may then be further annealed are used with the small junction forward biased.

Method of making interband tunneling diodes

Interband tunnel diodes which are compatible with Si-based processes such as, but not limited to, CMOS and SiGe HBT fabrication. Interband tunnel diodes are disclosed (i) with spacer layers surrounding a tunnel barrier; (ii) with a quantum well adjacent to, but not necessarily in contact with, one of the injectors, and (iii) with a first quantum well adjacent to, but not necessarily in contact with, the bottom injector and a second quantum well adjacent to, but not necessarily in contact with, the top injector. Process parameters include temperature process for growth, deposition or conversion of the tunnel diode and subsequent thermal cycling which to improve device benchmarks such as peak current density and the peak-to-valley current ratio.

Method of making vertical diode structures

A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Diode

In a pn junction diode having a conductivity modulating element provided on a first principal surface of a semiconductor substrate, when an impurity concentration of a p type impurity region is lowered to shorten a reverse recovery time, hole injection is suppressed, thereby causing a problem that a forward voltage value is increased at a certain current point. Moreover, introduction of a life time killer to shorten the reverse recovery time leads to a problem of increased leak current. On an n− type semiconductor layer that is a single crystal silicon layer, a p type polycrystalline silicon layer (p type polysilicon layer) is provided. Since the polysilicon layer has more grain boundaries than the single crystal silicon layer, an amount of holes injected into the n− type semiconductor layer from the p type polysilicon layer in forward voltage application can be suppressed. Moreover, a natural oxide film formed between the n− type semiconductor layer and the p type polysilicon layer in formation of the p type polysilicon layer can also reduce the amount of holes injected into the n− type semiconductor layer. Thus, a time to extract the holes in reverse voltage application, that is, a reverse recovery time can be shortened without using a life time killer.

Sandwich-structure-type alloyed semiconductor element

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Method of making vertical diode structures

A method of making a vertical diode is provided, the vertical dioxide having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

Method of forming gallium arsenide semiconductor devices

Tunneldiode mit einem Halbleiterkoerper aus Galliumarsenid und Verfahren zum Herstellen

Process of forming p-n layer

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification.

Process of forming p-n layer

High performance varactor diodes

A varactor diode having a first electrode comprising a well region of a first conductivity type in a substrate, a second electrode comprising a first plurality of diffusion regions of a second conductivity type abutting isolation regions disposed in said well region, and a second plurality of diffusion regions of said first conductivity type extending laterally from portions of said first plurality of diffusion regions not adjacent said isolation regions and having a dopant concentration greater than that of said first plurality of diffusion regions. The varactor has a tunability of at least approximately 3.5 in a range of applied voltage between approximately 0V to 3V, an approximately linear change in capacitive value in a range of applied voltage between approximately 0V to 2V, and a Q of at least approximately 100 at a circuit operating frequency of approximately 2 GHz.

Single-Electron Tunnel Junction for a Complementary Metal-Oxide Device and Method of Manufacturing the Same

A method of providing a p-type substrate, disposing a pad oxide layer on the p-type substrate, disposing a nitride layer on the pad oxide layer, forming a nitride window in the nitride layer, disposing a field oxide in the nitride window, disposing a polysilicon gate over the field oxide, and diffusing a n-doped region in the p-type substrate, thereby forming at least one single-electron tunnel junction between the polysilicon gate and the n-doped region.

Silicon on insulator transistor structure for imbedded DRAM

To address the above-discussed deficiencies of the prior art, the present invention provides an integrated circuit formed on a semiconductor wafer, comprising a doped base substrate; an insulator layer formed over the doped base substrate; and a doped ultra thin active layer formed on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate. The present invention therefore provides a semiconductor wafer that provides a doped ultra thin active layer. The lower Ioff in the DRAM transistor allows for lower heat dissipation, and the overall power requirement is decreased. Thus, the present invention provides a lower Ioff with reasonably good ion characteristics.

Semiconductor diode having a rectifying junction and method of manufacturing same

The invention relates to a semiconductor device having a rectifying junction ( 5 ) which is situated between two (semiconductor) regions ( 1, 2 ) of an opposite conductivity type. The second region ( 2 ), which includes silicon, is thicker and has a smaller doping concentration than the first region ( 1 ) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions ( 1, 2 ) are each provided with a connection conductor ( 3, 4 ). Such a device can very suitably be used as a switching element, in particular as a switching element for a high voltage and/or high power. In the known device, the silicon-germanium mixed crystal is relaxed, leading to the formation of misfit dislocations. These serve to reduce the service life of the minority charge carriers, thus enabling the device to be switched very rapidly. In a device in accordance with the invention, the entire first region ( 1 ) comprises a mixed crystal of silicon and germanium, and the germanium content and the thickness of the first region ( 1 ) are selected so that the voltage built up in the semiconductor device remains below the level at which misfit dislocations develop. Surprisingly, it has been found that such a device can also be switched very rapidly, even more rapidly than the known device. The absence of misfit dislocations has an additional advantage, namely that the device is very reliable. Misfit dislocations do not develop if the product of said relative deviation in the lattice constant and the thickness of the first region is smaller than or equal to 40 nm %. A safe upper limit for said product is 30 nm %.

电子热泵装置、应用该装置的电子机器及热泵模块

电子热泵装置(100)具备，发射极(101)和集电极(102)、支持这些电极的管座(103、104)、使这些管座间的间隔保持固定的间隔保持部(106)、而且维持管座间真空的密封部件(107)。发射极(101)具有第1半导体衬底(110)和发射极电极(111)。集电极(102)具有第2半导体衬底(120)和集电极电极(121)。发射极电极(111)和集电极电极(121)要配置为使其空出间隙并对置，在第1和第2的半导体衬底的至少一方，整体形成使发射极电极与集电极电极之间的间隙保持一定同时电和热绝缘性的隔层(105)。

Semiconductor device having a rectifying junction and method of manufacturing same

The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller doping concentration than the first region (1) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions (1, 2) are each provided with a connection conductor (3, 4). Such a device can very suitably be used as a switching element, in particular as a switching element for a high voltage and/or high power. In the known device, the silicon-germanium mixed crystal is relaxed, leading to the formation of misfit dislocations. These serve to reduce the service life of the minority charge carriers, thus enabling the device to be switched very rapidly. In a device in accordance with the invention, the entire first region (1) comprises a mixed crystal of silicon and germanium, and the germanium content and the thickness of the first region (1) are selected so that the voltage built up in the semiconductor device remains below the level at which misfit dislocations develop. Surprisingly, it has been found that such a device can also be switched very rapidly, even more rapidly than the known device. The absence of misfit dislocations has an additional advantage, namely that the device is very reliable. Misfit dislocations do not develop if the product of said relative deviation in the lattice constant and the thickness of the first region is smaller than or equal to 40 nm %. A safe upper limit for said product is 30 nm %.

Semiconductor device having a rectifying junction and method of manufacturing same

The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller doping concentration than the first region (1) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions (1, 2) are each provided with a connection conductor (3, 4). Such a device can very suitably be used as a switching element, in particular as a switching element for a high voltage and/or high power. In the known device, the silicon-germanium mixed crystal is relaxed, leading to the formation of misfit dislocations. These serve to reduce the service life of the minority charge carriers, thus enabling the device to be switched very rapidly. In a device in accordance with the invention, the entire first region (1) comprises a mixed crystal of silicon and germanium, and the germanium content and the thickness of the first region (1) are selected so that the voltage built up in the semiconductor device remains below the level at which misfit dislocations develop. Surprisingly, it has been found that such a device can also be switched very rapidly, even more rapidly than the known device. The absence of misfit dislocations has an additional advantage, namely that the device is very reliable. Misfit dislocations do not develop if the product of said relative deviation in the lattice constant and the thickness of the first region is smaller than or equal to 40 nm %. A safe upper limit for said product is 30 nm %.