26-09-2019 дата публикации
Номер: WO2019178988A1
Автор:
XU, Daiguo,
HU, Gangyi,
LI, Ruzhang,
WANG, Jian'an,
CHEN, Guangbing,
FU, Dongbing,
XU, Shiliu,
LIU, Tao,
PU, Jie,
FENG, Zhihua
Принадлежит:
Provided is a high speed, low noise dynamic comparator, comprising: an input unit, comprising input NMOS transistors (M1, M2) and input PMOS transistors (M6, M9); and a latch unit, comprising latch NMOS transistors (M4, M5) and latch PMOS transistors (M7, M8), wherein the latch NMOS transistors (M4, M5) and the latch PMOS transistors (M7, M8) are connected to form a latch structure; a pull-up unit, comprising pull-up PMOS transistors (M10, M11, M12) connected to the input NMOS transistors (M1, M2); and a substrate bootstrap voltage generating circuit for generating a substrate bootstrap voltage. By using a substrate bootstrap technology of the MOS transistor, the on-resistance of the MOS transistor is reduced, the comparator speed of the comparator is increased, and the comparator speed of the comparator is further improved. At the same time, the threshold voltage of the input transistor of the comparator is reduced, so that a transconductance of the input transistor is increased, thereby ...
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