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Применить Всего найдено 4. Отображено 4.
08-05-2015 дата публикации

MASK PATTERN FOR HOLE PATTERNING AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE USING SAME

Номер: KR1020150049506A
Автор: KANG, CHUN SOO
Принадлежит:

The present invention relates to a manufacturing method of a semiconductor device capable of preventing a patterning defect of a cell matrix edge area. The technology comprises; a step of forming a layer to be etched on a substrate including first and second areas; a step of forming a first hard mask layer on the layer to be etched; a step of forming a first mask structure, including a blocking pattern capable of blocking the second area and a second hard mask pattern of a spacer shape located in the first area on the first hard mask layer; a step of forming a plurality of open units by etching the first hard mask layer through the first mask structure; a step of forming a second hard mask structure which crosses the second hard mask pattern by blocking the first open units and the second area; a step of forming a plurality of second open units by etching the second hard mask pattern and the first hard mask layer through the second mask structure; and a step of forming a plurality of hole ...

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30-03-2018 дата публикации

복층 금속 콘택을 포함하는 반도체 소자

Номер: KR0101844058B1
Автор: 강춘수, 오상진
Принадлежит: 에스케이하이닉스 주식회사

... 본 발명의 메모리 소자의 소자분리 형성 방법은, 셀 영역 및 주변영역을 포함하는 반도체 기판; 주변영역의 반도체 기판 상에 주변회로를 구성하게 형성된 주변트랜지스터의 게이트; 게이트를 덮게 형성된 제1 층간절연층; 주변영역의 제1 층간절연층 상에 형성된 제1 주변회로배선층 패턴; 주변영역의 제1 층간절연층 내에 게이트와 제1 주변회로배선층 패턴을 연결하게 형성된 제1 연결콘택; 제1주변회로배선층 패턴을 덮게 주변영역 상에 형성된 제2 층간절연층; 제2 층간절연층 상에 형성된 제2 주변회로배선층 패턴; 주변회로를 구성하도록 제1 주변회로배선층 패턴과 제2 주변회로배선층 패턴을 연결하게 제2 층간절연층 내에 형성된 제2 연결콘택 및 제2 층간절연층 및 제1 층간절연층을 관통하여 주변트랜지스터의 게이트와 제2 주변회로배선층 패턴을 연결하는 제3 연결콘택을 포함한다.

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15-07-2016 дата публикации

PATTERN FORMING METHOD

Номер: KR1020160085043A
Принадлежит:

The present technique is to provide a method for manufacturing a semiconductor device, which overcomes limitations of resolving power of an exposure device, and can form a fine pattern. The method for manufacturing a semiconductor device according to the present technique comprises: a step of forming a plurality of line patterns positioned at the upper portion of a first area of an etching target layer and a preliminary pad pattern covering a second area and a third area of the etching target layer; a step of forming a plurality of pillars positioned at the upper portion of the line patterns and a sacrificial pad pattern positioned at the upper portion of the preliminary pad pattern of the second area; a step of forming a plurality of first spacers on the sidewalls of the pillars, the first spacers coming in contact and forming a plurality of preliminary first openings among the first spacers; a step of removing the pillars to form a plurality of preliminary second openings; a step of cutting ...

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02-02-2017 дата публикации

METHOD FOR FORMING PATTERNS OF SEMICONDUCTOR DEVICE

Номер: KR1020170011849A
Автор: KANG, CHUN SOO
Принадлежит:

The present invention provides a method for forming patterns of a semiconductor device, simultaneously forming patterns that have different densities or widths and vary in size and pitch. According to the present invention, the method of forming patterns of a semiconductor device comprises: a step of preparing an etching target layer where a first area and a second area are defined; a step of forming a first regular feature positioned on an upper part of the etching target layer of the first area and a random feature positioned on an upper part of the etching target layer of the second area; a step of forming a second regular feature on an upper part of the first regular feature; a step of forming a first cutting barrier and a second cutting barrier on an upper part of the random feature to allow a part of the random feature to be exposed; a step of cutting the first regular feature by using the second regular feature to form a regular array feature; a step of cutting the random feature ...

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