Настройки

Укажите год
-

Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

Подробнее
-

Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

Подробнее

Форма поиска

Поддерживает ввод нескольких поисковых фраз (по одной на строку). При поиске обеспечивает поддержку морфологии русского и английского языка
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Ведите корректный номера.
Укажите год
Укажите год
Применить Всего найдено 12. Отображено 12.
15-07-2015 дата публикации

Pillow for Protecting Cervical Vertebral

Номер: KR0101536821B1
Автор: 신우열
Принадлежит: 신우열

... 본 발명은 사용자에 신체 조건에 따라 높낮이 조절이 가능한 경추 베개에 관한 것으로서, 좀더 상세하게는 반원형 단면 구조의 코어(11)와 상기 코어가 상단에 상부로 돌출되게 결합 형성된 매트(15)로 구성하여 상기 코어를 매트에 감아 벨트(20)로 묶어 고정하되, 상기 코어(11)를 매트(15)에 감아주는 횟수에 따라 메트의 두께에 의해 베개 높낮이를 조절하므로 구조가 간단하여 제조 단가가 저렴함은 물론 사용자의 신체 조건에 따라 높낮이 조절이 간단하여 사용 편리성을 우수하게 제공하는데 그 특징이 있다.

Подробнее
Номер записи: 1
20-05-2015 дата публикации

HEIGHT-ADJUSTABLE PILLOW FOR CERVICAL VERTEBRAE

Номер: KR1020150054115A
Автор: SHIN, WOO YEOL
Принадлежит:

The present invention relates to a pillow for cervical vertebrae, capable of the height being adjusted depending on a user body type and, more specifically to a pillow comprising: a core (11) having a semicircular section structure, and a mat (15) bonded with the core protruding upward from the top end, wherein the core is coiled around the mat and fixed by binding with a belt (20), and the height of the pillow is adjusted by the thickness of the mat according to the number of times of coiling by the core. Therefore, manufacturing cost is inexpensive by the simple structure, and convenience of use is excellent by a simple adjustment of height depending on the users body type. COPYRIGHT KIPO 2015 ...

Подробнее
Номер записи: 2
23-04-2018 дата публикации

CERVICAL SPINE CORRECTION APPARATUS

Номер: KR1020180041061A
Автор: SHIN, WOO YEOL
Принадлежит:

A cervical spine correction apparatus capable of more effectively performing correction by transferring optimized stimulation to each part of cervical spine is provided. The cervical spine correction apparatus comprises: a support block disposed to be put at a rear neck between a head and a back, and having an arch portion corresponding to the rear neck; and a plurality of pressure plates having a pair of supporting blocks connected to both sides of the arch portion, forming an inclination from the support block toward the rear neck, and having at least one edge arranged at an end portion so as to form a pressing point at different points of the rear neck according to the height of the arch portion. COPYRIGHT KIPO 2018 ...

Подробнее
Номер записи: 3
25-08-2017 дата публикации

CLOCK GENERATING CIRCUIT, AND INTERFACE CIRCUIT AND SEMICONDUCTOR SYSTEM USING SAME

Номер: KR1020170096798A
Автор: KIM, KYUNG HOON, PARK, MYEONG JAE, SHIN, WOO YEOL, LEE, SUNG EUN, CHI, HAN KYU, HAN, JAE WON
Принадлежит:

A clock generating circuit includes a master delay locked loop circuit, a code divider, and a slave delay locked loop circuit. The master delay locked loop circuit generates a phase pulse signal including a pulse width corresponding to one period of the clock signal and generates a delay control code corresponding to the phase pulse signal. The code divider divides the delay control code to generate a division delay control code. The slave delay locked loop circuit delays a strobe signal by a predetermined time corresponding to the division delay control code. The clock generating circuit can complete the delay locked operation of the delay locked loop circuit without feedback and comparison operations. Accordingly, the present invention can improve the data communication accuracy of an interface circuit. COPYRIGHT KIPO 2017 (110) Master delay locked loop circuit (120) Code divider (130) Slave delay locked loop circuit ...

Подробнее
Номер записи: 4
26-09-2017 дата публикации

DELAY CIRCUIT

Номер: KR1020170107772A
Автор: LEE, SUNG EUN, KIM, KYUNG HOON, PARK, MYEONG JAE, SHIN, WOO YEOL, CHI, HAN KYU, KIM, YONG JU
Принадлежит:

The present invention provides a technique for increasing resolution of a delay circuit while reducing the area thereof. The delay circuit comprises: multiple delay units connected in series in a loop shape, and sequentially delaying an input signal of the delay circuit; an input control part selecting the delay unit to receive the input signal of the delay circuit among the multiple delay units; and an output control part controlling to output an output signal of a predetermined delay unit to an output signal of the delay circuit, when the output signal of the predetermined delay unit among the multiple delay units is activated an N number of times (N is an integer greater than or equal to zero). COPYRIGHT KIPO 2017 (121) Pulse generator (122) Decoder (131) Counter (132) Code comparator (133) Delay line ...

Подробнее
Номер записи: 5
09-08-2018 дата публикации

CERVICAL SPINE BRACE

Номер: WO2018070704A3
Автор: SHIN, Woo-yeol
Принадлежит:

Provided is a cervical spine brace which transfers optimal stimulation to each portion of the cervical spine so as to enable more efficient correction. The cervical spine brace comprises: a support block disposed to be placed on the back of the neck between the head and the back and having an arch part corresponding to the arch of the back of the neck; and a plurality of pressing plates which are connected in pairs at opposite sides of the arch part of the support block, make an inclination toward the back of the neck from the support block, and have one or more edges at end portions thereof, the edges being arranged to form pressure points on different spots of the back of the neck depending on height of the arch part.

Подробнее
Номер записи: 6
13-06-2017 дата публикации

SEMICONDUCTOR SYSTEM

Номер: KR1020170065352A
Автор: SONG, KEUN SOO, SHIN, WOO YEOL
Принадлежит:

The present invention relates to a semiconductor system to implement a high-speed operation. The semiconductor system comprises: a controller for providing an external command, an external address, and a first external clock, and transmitting and receiving a second external clock and a third external clock for transmitting and receiving external data; and a semiconductor memory device for receiving the external command and the external address in synchronization with the first external clock, receiving the external data in synchronization with the second external clock, and providing the external data and the third external clock to the controller. COPYRIGHT KIPO 2017 (110) Clock generating unit (121) Command and address transmitting unit (122) First external clock transmitting unit (131) Second external clock transmitting unit (212) Logic circuit unit (222) Distribution unit ...

Подробнее
Номер записи: 7
02-03-2017 дата публикации

PERIOD SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR SYSTEM INCLUDING SAME

Номер: KR1020170022457A
Автор: PARK, MYEONG JAE, KIM, KYUNG HOON, SHIN, WOO YEOL, CHI, HAN KYU
Принадлежит:

The present invention relates to a period signal generation circuit and a semiconductor system including the same, comprising: a first semiconductor device for outputting a command and receiving data; and a second semiconductor device for generating a periodically toggled period signal in response to the command, outputting the data in response to the period signal, and emitting a charge of an internal node when the period signal is not toggled during a predetermined section. COPYRIGHT KIPO 2017 (220) Oscillator (230) Detection signal generation unit (240) Reset signal generation unit ...

Подробнее
Номер записи: 8
10-03-2016 дата публикации

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING SAME

Номер: KR1020160027349A
Автор: KIM, MIN CHANG, SHIN, WOO YEOL, KWAK, NO HYEOP
Принадлежит:

The objective of the present invention is to provide a semiconductor system capable of examining the interface properties of a semiconductor device equipped with a micro-bump pad. The semiconductor system comprises: a first semiconductor device including a first pad group; and a second semiconductor device including a second pad group electrically connected to the first pad group, a third pad group for inputting and outputting signals in and from a third semiconductor device, and a selective transmitting unit for connecting the third pad group to the first pad group or connecting an interface unit connected to the first pad group in response to a test mode enable signal. COPYRIGHT KIPO 2016 (127) Selective transmitting unit (128) Interface unit ...

Подробнее
Номер записи: 9
19-04-2018 дата публикации

CERVICAL SPINE BRACE

Номер: WO2018070704A2
Автор: SHIN, Woo-yeol
Принадлежит:

Provided is a cervical spine brace which transfers optimal stimulation to each portion of the cervical spine so as to enable more efficient correction. The cervical spine brace comprises: a support block disposed to be placed on the back of the neck between the head and the back and having an arch part corresponding to the arch of the back of the neck; and a plurality of pressing plates which are connected in pairs at opposite sides of the arch part of the support block, make an inclination toward the back of the neck from the support block, and have one or more edges at end portions thereof, the edges being arranged to form pressure points on different spots of the back of the neck depending on height of the arch part.

Подробнее
Номер записи: 10
26-10-2016 дата публикации

INTERPOSER FOR INSPECTION

Номер: KR1020160123890A
Автор: SEO, JAE HWAN, SHIN, WOO YEOL
Принадлежит:

Disclosed is an interposer for inspection of reliability of a semiconductor chip. The interposer for inspection can comprise: active pads which include: pads which are placed in an active area in a first surface and where data and control signals are inputted and outputted for testing the chip to be inspected in an active mode; and pads which receive power for operation of the chip to be inspected and the interposer; passive pads which include pads which are placed in a passive area in the first surface and receive data for testing the chip to be inspected in a passive mode and power for operation of the chip to be inspected and the interposer; and bump pads which are placed in a second surface, which faces the first surface, and are connected to the chip to be inspected. COPYRIGHT KIPO 2016 ...

Подробнее
Номер записи: 11
23-08-2017 дата публикации

CLOCK DATA RECOVERY CIRCUIT, CLOCK DATA RECOVERY METHOD AND INTEGRATED CIRCUIT INCLUDING SAME

Номер: KR1020170096073A
Автор: SHIN, WOO YEOL, PARK, MYEONG JAE, KIM, KYU YOUNG, CHI, HAN KYU, LEE, SUNG EUN, KIM, KYUNG HOON
Принадлежит:

The present invention relates to a clock data recovery circuit, a clock data recovery method, and an integrated circuit including the same. According to an embodiment of the present invention, the clock data recovery circuit comprises: a phase comparison part comparing input data with multiple phase clock phases, and generating up/down signals corresponding to phase transition information; a filtering part including a counting part counting the up/down signals based on an upper threshold value and a lower threshold value, setting the lower threshold value as an initial value of the counting part when overflow occurs, and setting the upper threshold value as the initial value of the counting part when underflow occurs; and a phase rotation part responding to a control code output from the filtering part, and adjusting the multiple phase clock phases. COPYRIGHT KIPO 2017 (120) Counting part (140) Underflow/overflow prediction part (160) Control code generation part ...

Подробнее
Номер записи: 12