SEMICONDUCTOR SYSTEM AND METHOD FOR MANUFACTURING SAME

A semiconductor system having a trench MOS barrier Schottky diode is described, including an n-type epitaxial layer, in which at least two etched trenches are located in a two-dimensional manner of presentation on an n-type substrate which acts as the cathode zone. An electrically floating, p-type layer, which acts as the anode zone of the p-n type diode, is located in the n-type epitaxial layer, at least in a location below the trench bottom. An oxide layer is located between a metal layer and the surface of the trenches. The n-type epitaxial layer may include two n-type layers of different doping concentrations. 117-. (canceled)18. A semiconductor system , comprising:{'sup': '+', 'a trench MOS barrier Schottky diode (TMBS) made of an n-type epitaxial layer in which at least two etched trenches are located on an n-type substrate which acts as a cathode zone, in a two-dimensional representation, electrically floating p-type layers, which act as an anode zone, being situated in the n-type epitaxial layer, at least in a location below a bottom of the trenches, and an oxide layer being situated between a metal layer and a surface of the trenches.'}19. The semiconductor system as recited in claim 18 , wherein the n-type epitaxial layer is composed of two n-type layers doped to different degrees claim 18 , an upper epitaxial layer of the two n-type layers being a highly doped n-type layer claim 18 , and a lower epitaxial partial layer of the two n-type layers adjoining the upper epitaxial layer and having a higher doping concentration than the upper epitaxial layer.20. The semiconductor system as recited in claim 18 , wherein a breakdown voltage of a p-n type diode formed from the floating p-type and the n-type epitaxial layer is lower than a breakdown voltage of the Schottky diode formed from the metal layer as an anode and the n-type epitaxial layer as the cathode claim 18 , and a breakdown voltage of a MOS structure formed from the metal layer claim 18 , the oxide ...

Field-Effect Transistor with Integrated TJBS Diode

A semiconductor component includes at least one MOS field-effect transistor and a trench junction barrier Schottky diode (TJBS) configured as a monolithically integrated structure. The breakdown voltages of the MOS field-effect transistor and of the trench junction barrier Schottky diode (TJBS) are selected such that the MOS field-effect transistor can be operated in breakdown mode. 122-. (canceled)23. A semiconductor component , comprising:at least one MOS field-effect transistor; anda trench junction barrier Schottky diode.24. The semiconductor component as recited in claim 23 , wherein the MOS field-effect transistor and the trench junction barrier Schottky diode are configured as a monolithically integrated structure.25. The semiconductor component as recited in claim 24 , wherein the breakdown voltages of the MOS field-effect transistor and of the trench junction barrier Schottky diode are selected such that the MOS field-effect transistor is able to operate in breakdown mode.26. The semiconductor component as recited in claim 25 , wherein the breakdown voltage of the trench junction barrier Schottky diode is selected as the smallest breakdown voltage such that the breakdown voltage of the trench junction barrier Schottky diode is smaller than (i) the breakdown voltage of a Schottky transition in the semiconductor component claim 25 , (ii) the breakdown voltage of a pn inverse diode in the semiconductor component claim 25 , and (iii) the breakdown voltage of a parasitic NPN transistor of the semiconductor component.27. The semiconductor component as recited in claim 25 , wherein:{'sup': '+', 'an n-doped silicon layer is applied onto a highly n-doped silicon substrate;'}multiple trenches are provided in the n-doped silicon layer; andfor at least some of the trenches, (i) a thin dielectric layer is provided on at least one of side walls and floor, (ii) the interior of the trenches are filled with a layer of conductive material, and (iii) the layer of conductive ...

SCHOTTKY DIODE HAVING A SUBSTRATE P-N DIODE

A semiconductor device has a trench junction barrier Schottky diode that includes an integrated substrate p-n diode (TJBS-Sub-PN) as a clamping element, the trench junction barrier Schottky diode being suited, e.g., as a Zener diode having a breakdown voltage of approximately 20 V, for use in motor-vehicle generator systems. In this context, the TJBS-Sub-PN is made up of a combination of a Schottky diode, an epitaxial p-n diode and a substrate p-n diode, and the breakdown voltage of the substrate p-n diode (BV_pn) is less than the breakdown voltage of the Schottky diode (BV_schottky) and the breakdown voltage of the epitaxial p-n diode (BV_epi). 110-. (canceled)11. A semiconductor device , comprising: the trench junction barrier Schottky diode is in the form of a Zener diode having a breakdown voltage in the range of 20 V,', 'the trench junction barrier Schottky diode which includes the integrated substrate p-n diode is made up of at least a combination of a Schottky diode, an epitaxial p-n diode and the substrate p-n diode, and', 'the breakdown voltage of the substrate p-n diode is less than the breakdown voltage of the Schottky diode and the breakdown voltage of the epitaxial p-n diode., 'a trench junction barrier Schottky diode which includes an integrated substrate p-n diode as a clamping element, wherein12. The semiconductor device as recited in claim 11 , wherein the semiconductor device is incorporated as a part of a motor-vehicle generator system.13. The semiconductor device as recited in claim 11 , wherein the semiconductor device is operable at high currents during breakdown.14. The semiconductor device as recited in claim 11 , wherein:{'sup': '+', 'an n-epitaxial layer is situated on an n-substrate and is used as a cathode region;'}{'sup': '+', 'at least two trenches etched through the n-epitaxial layer up to the n-substrate are present;'}the at least two trenches are filled with one of p-doped Si or poly-Si and are used as an anode region of the ...

Semiconductor system including a schottky diode

A semiconductor system is described, which includes a trench junction barrier Schottky diode having an integrated p-n type diode as a clamping element, which is suitable for use in motor vehicle generator system, in particular as a Zener diode having a breakdown voltage of approximately 20V. In this case, the TJBS is a combination of a Schottky diode and a p-n type diode. Where the breakdown voltages are concerned, the breakdown voltage of the p-n type diode is lower than the breakdown voltage of Schottky diode. The semiconductor system may therefore be operated using high currents at breakdown.

Schottky diode

A semiconductor system of a Schottky diode is described having an integrated PN diode as a clamping element, which is suitable in particular as a Zener diode having a breakdown voltage of approximately 20 V for use in motor vehicle generator systems. The semiconductor system of the Schottky diode includes a combination of a Schottky diode and a PN diode. The breakdown voltage of the PN diode is much lower than the breakdown voltage of the Schottky diode, the semiconductor system being able to be operated using high currents during breakdown operation.

PROTECTIVE ELEMENT FOR ELECTRONIC CIRCUITS

A protective element for electronics has at least one Schottky diode and at least one Zener diode which are located between a power supply and the electronics, the anode of the Schottky diode being connected to the power supply and the cathode of the Schottky diode being connected to the electronics, and the cathode and the anode of the Zener diode are connected to ground. The Schottky diode is a trench MOS barrier junction diode or trench MOS barrier Schottky (TMBS) diode or a trench junction barrier Schottky (TJBS) diode and includes an integrated semiconductor arrangement, which has at least one trench MOS barrier Schottky diode and a p-doped substrate, which is used as the anode of the Zener diode. 110-. (canceled)11. A protective element for an electronic unit , comprising:at least one Schottky diode and at least one Zener diode located between a power supply and the electronics unit; the anode of the Schottky diode is connected to the power supply;', 'the cathode of the Schottky diode is connected to the electronics unit;', 'the cathode and the anode of the Zener diode are connected to ground; and', 'the Schottky diode is one of a trench MOS barrier junction diode, trench MOS barrier Schottky diode, or a trench junction barrier Schottky diode., 'wherein12. The protective element as recited in claim 11 , wherein the protective element has an integrated semiconductor system including at least one trench MOS barrier Schottky diode and a p-doped substrate claim 11 , and wherein the p-doped substrate is the anode of the Zener diode.13. The protective element as recited in claim 12 , further comprising:a buried layer.14. The protective element as recited in claim 11 , wherein the protective element has a trench junction barrier Schottky diode and a p-doped substrate claim 11 , and wherein the p-doped substrate is the anode of the Zener diode.15. The protective element as recited in claim 12 , wherein trenches are provided in the protective element.16. The protective ...

SUPER TRENCH SCHOTTKY BARRIER SCHOTTKY DIODE

A Schottky diode includes an n-substrate, an n-epilayer, trenches introduced into the n-epilayer, floating Schottky contacts being located on their side walls and on the entire trench bottom, mesa regions between the adjacent trenches, a metal layer on its back face, this metal layer being used as a cathode electrode, and an anode electrode on the front face of the Schottky diode having two metal layers, the first metal layer of which forms a Schottky contact and the second metal layer of which is situated below the first metal layer and also forms a Schottky contact. Preferably, these two Schottky contacts have different barrier heights. 1. A Schottky diode , comprising:{'sup': '+', 'an n-substrate;'}an n-epilayer;trenches introduced into the n-epilayer;mesa regions between adjacent trenches;a metal layer on a back face of the diode, the metal layer being used as a cathode electrode;an anode electrode provided on a front face of the diode, the anode electrode having two metal layers, a first metal layer forming a Schottky contact, and a second metal layer being situated below the first metal layer and also forming a Schottky contact; andadditional, floating Schottky contacts situated on walls of the trenches between the second metal layer and bottoms of the trenches.2. The Schottky diode according to claim 1 , wherein the first metal layer and the second metal layer claim 1 , each of which forms a Schottky contact claim 1 , have different barrier heights.3. The Schottky diode according to claim 2 , wherein the second metal layer has a greater barrier height than the first metal layer.4. The Schottky diode according to claim 1 , wherein a distance (D gap) is provided between the second metal layer and the additional Schottky contact adjacent to the second metal layer claim 1 , and between the additional Schottky contacts.5. The Schottky diode according to claim 1 , wherein each of the additional Schottky contacts has a same barrier height as the second metal layer ...

SUPER-JUNCTION SCHOTTKY OXIDE PIN DIODE HAVING THIN P-TYPE LAYERS UNDER THE SCHOTTKY CONTACT

A semiconductor chip, which includes an n-type substrate, over which an n-type epitaxial layer having trenches introduced into the epitaxial layer and filled with p-type semiconductor is situated, the trenches each having a heavily doped p-type region on their upper side, the n-type substrate being situated in such a manner, that an alternating sequence of n-type regions having a first width and p-type regions having a second width is present; a first metallic layer, which is provided on the front side of the semiconductor chip, forms an ohmic contact with the heavily doped p-type regions and is used as an anode electrode; a second metallic layer, which is provided on the back side of the semiconductor chip, constitutes an ohmic contact and is used as a cathode electrode; a dielectric layer provided, in each instance, between an n-type region and an adjacent p-type region, as well as p-type layers provided between the n-type regions and the first metallic layer. 1. A semiconductor chip , comprising:{'sup': +', '+, 'an n-type substrate, over which an n-type epitaxial layer having trenches that are introduced into the epitaxial layer and filled with p-type semiconductor material, is situated, the trenches each having a highly doped p-type region on an upper side, and the n-type substrate being situated in such a manner that an alternating sequence of n-type regions having a first width and p-type regions having a second width is present;'}a first metallic layer provided on a front side of the semiconductor chip, which forms an ohmic contact with heavily doped p-type regions and is used as an anode electrode; anda second metallic layer provided on a back side of the semiconductor chip, the second metallic layer constituting an ohmic contact and is used as a cathode electrode, and in each instance, a dielectric layer is provided between an n-type region and an adjacent p-type region;wherein in each instance, a p-type layer is provided between each n-type region and the ...

RECTIFIER ARRANGEMENT HAVING SCHOTTKY DIODES

A rectifier system having press-in diodes that contain a Schottky diode as semiconductor element. The Schottky diodes are operated in an operating range in which the diode losses increase as the temperature increases. 110-. (canceled)11. A generator having a rectifier system having press-in diodes that each contain as a semiconductor element a Schottky diode , the generator having a hot point at which , as a function of a rotational speed of the generator , a temperature of the diodes is at its highest , wherein a thermal resistance between a barrier layer of a semiconductor of the semiconductor element and an ambient air during operation in the hot point of the generator does not exceed a specified value , the diodes being configured so that a maximum permissible barrier layer temperature of the diodes is at least for operation in the hot point , and the Schottky diodes are operated in an operational range in which the diode losses increase with increasing temperature.13. The generator as recited in claim 11 , wherein the thermal resistance between the barrier layer of the semiconductor and ambient air at the operation in the hot point of the generator is less than 7 K/W.14. The generator as recited in claim 11 , wherein the thermal resistance between the barrier layer of the semiconductor and the ambient air at the operation in the hot point of the generator is less than 5 K/W.15. The generator as recited in claim 11 , wherein the thermal resistance between the barrier layer of the semiconductor and ambient air at the operation in the hot point of the generator is less than 3 K/W.16. The generator as recited in claim 11 , wherein the Schottky diode is a trench MOS barrier Schottky diode.17. The generator as recited in claim 16 , wherein the Schottky diode is a trench MOS barrier Schottky diode claim 16 , in which a trench depth is 1-3 μm and a distance from trench to trench is 0.5-1 μm.18. The generator as recited in claim 11 , wherein the Schottky diode is a ...

GENERATOR DEVICE FOR THE VOLTAGE SUPPLY OF A MOTOR VEHICLE

A generator device for the voltage supply of a motor vehicle is equipped with at least one rectifying element for rectifying an alternating voltage provided by a generator. The rectifying element has an n-channel MOS field-effect transistor in which the gate, the body area, and the source area are electrically fixedly connected to one another and in which the drain area is used as a cathode. 114-. (canceled)15. A generator device for voltage supply of a motor vehicle , comprising:at least one rectifying element for rectifying an alternating voltage provided by a generator;{'sup': '2', 'wherein the rectifying element has an n-channel MOS field-effect transistor in which a gate, a body area, and a source area are electrically fixedly connected to one another and in which the drain area is used as a cathode; the rectifying element has a conducting-state voltage which is lower than a forward voltage of a p-n diode; the rectifying element has the conducting-state voltage (UON) which is lower than 0.7 V when a current flows through the rectifying element at 500 A/cm; and the rectifying element has a gate oxide thickness which is smaller than 20 nm.'}16. The generator device as recited in claim 15 , wherein a doping of the body area is reduced to reduce a threshold voltage on a surface.17. The generator device as recited in claim 15 , wherein a connection of source and gate contacts is monolithically integrated.18. The generator device as recited in claim 15 , wherein the rectifying element has solderable front and back sides.19. The generator device as recited in claim 15 , wherein the rectifying element has an integrated voltage limitation (load dump protection).20. The generator device as recited in claim 19 , wherein the integrated voltage limitation takes place due to an avalanche breakdown of a body diode.21. The generator device as recited in claim 15 , wherein the MOSFET is produced as a power MOSFET in planar technology or as a power MOSFET in trench technology.22 ...

Method for manufacturing a diode, and a diode

In a method for manufacturing a diode, a semiconductor crystal wafer is used to produce a p-n or n-p junction, which extends in planar fashion across the top side of a semiconductor crystal wafer. Separation edges form perpendicularly to the top side of the semiconductor crystal wafer, which edges extend across the p-n or n-p junction. The separation of the semiconductor crystal wafer is achieved in that, starting from a disturbance, a fissure is propagated by local heating and local cooling of the semiconductor crystal wafer. The separation fissure thus formed extends along crystal planes of the semiconductor crystal, which avoids the formation of defects in the area of the p-n or n-p junction.

Semiconductor Arrangement Having a Schottky Diode

A semiconductor assemblage of a super-trench Schottky barrier diode (STSBD) made up of an n substrate, an n-epilayer, trenches etched into the n-epilayer that have a width and a distance from the n substrate, mesa regions between the adjacent trenches having a width, a metal layer on the front side of the chip that is a Schottky contact and serves as an anode electrode, and a metal layer on the back side of the chip that is an ohmic contact and serves as a cathode electrode, wherein multiple Schottky contacts having a width or distance and a distance between the Schottky contacts, and between the Schottky contact as anode electrode and the first Schottky contact, are located on the trench wall. 119-. (canceled)20. A semiconductor assemblage , comprising:{'sup': +', '+, 'a super-trench Schottky barrier diode (STSBD) having an n substrate, an n-epilayer, trenches etched into the n-epilayer that have a width and a distance from the n substrate, mesa regions between the adjacent trenches having a width, a metal layer on a front side of the chip that is a Schottky contact and serves as an anode electrode, a metal layer on a back side of the chip that is an ohmic contact and serves as a cathode electrode, multiple Schottky contacts having a width or distance and a distance between the Schottky contacts, and between the Schottky contact as anode electrode and the first Schottky contact, being located on the trench wall.'}21. The semiconductor assemblage of claim 20 , wherein the Schottky contacts are floated on the trench wall.22. The semiconductor assemblage of claim 20 , wherein the metal layer on the front side of the chip claim 20 , which is a Schottky contact and serves as an anode electrode claim 20 , covers the trench wall up to a depth.23. The semiconductor assemblage of claim 20 , wherein the metal layer on the front side of the chip fills up the trenches up to a depth.24. The semiconductor assemblage of claim 20 , wherein the last floated Schottky contact covers ...

Rectifierarrangement having schottky diodes

A rectifier system having press-in diodes that contain a Schottky diode as semiconductor element. The Schottky diodes are operated in an operating range in which the diode losses increase as the temperature increases.

SEMICONDUCTOR CONFIGURATION HAVING REDUCED ON-STATE RESISTANCE

A semiconductor configuration, which includes an epitaxial layer of the first conductivity type disposed on a highly doped substrate of first conductivity type; a layer of a second conductivity type introduced into the epitaxial layer; and a highly doped layer of the second conductivity type provided at the surface of the layer of the second conductivity type. Between the layer of the second conductivity type and the highly doped substrate of the first conductivity type, a plurality of Schottky contacts, which are in the floating state, are provided mutually in parallel in the area of the epitaxial layer. 113-. (canceled)14. A semiconductor configuration , comprising:an epitaxial layer of a first conductivity type disposed on a highly doped substrate of the first conductivity type;a layer of a second conductivity type introduced into the epitaxial layer;a highly doped layer of the second conductivity type provided at a surface of the layer of the second conductivity type; anda plurality of floating Schottky contacts provided in trenches and disposed mutually in parallel in a direction of the highly doped substrate, and configured between the layer of the second conductivity type and the highly doped substrate of the first conductivity type.15. The semiconductor configuration as recited in claim 14 , wherein claim 14 , at the surface of the layer of the second conductivity type claim 14 , a highly doped layer of the first conductivity type and a highly doped layer of the second conductivity type are provided claim 14 , at least two trenches filled with doped polysilicon and covered with dielectric layers are introduced into the epitaxial layer claim 14 , the dielectric layers at bottoms of the trench are dimensioned to be thicker than the dielectric layers at side walls of the trenches claim 14 , and an alternating sequence of a metal claim 14 , respectively silicide layer with a further dielectric layer claim 14 , is disposed in each case between the layer of the ...

TRENCH SCHOTTKY DIODE

A trench Schottky diode is described, which has a highly doped substrate of a first conductivity type and an epitaxial layer of the same conductivity type that is applied to the substrate. At least two trenches are introduced into the epitaxial layer. The epitaxial layer is a stepped epitaxial layer that has two partial layers of different doping concentrations. 1. A trench Schottky diode comprising a highly doped substrate of a first conductivity type (n) and an epitaxial layer of the same conductivity type (n) applied to the substrate , at least two trenches being introduced into the epitaxial layer ,{'b': 2', '2, 'i': a,', 'b, 'wherein the epitaxial layer is a stepped epitaxial layer that has two partial layers () of different doping concentrations.'}22121ba. The trench Schottky diode as recited in claim 1 , wherein the first partial layer () is contacted by the substrate () and has a higher doping concentration than the second partial layer () claim 1 , which is not contacted by the substrate ().3. The trench Schottky diode as recited in claim 1 , whereinit is a trench MOS barrier Schottky diode;{'b': '5', 'at the rear side thereof, a first metal layer () used as a cathode electrode is provided;'}{'b': 4', '2', '4, 'i': 'a', 'at the front side thereof, a second metal layer () is provided that is used as an anode electrode and forms a Schottky contact with the second partial layer (); and, between the second metal layer (); and'}{'b': '7', 'the side walls of the trenches, a layer () of dielectric material is provided.'}4. The trench Schottky diode as recited in claim 3 , whereinit is realized as a chip that has a chip surface region and a lower MOS region;{'b': 2', '7', '4, 'i': 'b', 'the first partial layer (), together with the layer () of dielectric material, and the second metal layer () form the lower MOS region;'}{'b': 2', '4, 'i': 'a', 'the second partial layer () and the second metal layer () form the chip surface region; and'}the breakdown voltage of the ...

VERTICAL POWER TRANSISTOR HAVING HETEROJUNCTIONS

A vertical power transistor, including a semiconductor substrate, on which at least one first layer and one second layer are situated, the second layer being situated on the first layer, and the first layer including a first semiconductor material; and a plurality of trenches, which extend from an upper side of the second layer into the first layer. The first layer has a first doping, and each trench has a first region, which extends from the respective trench bottom to a first level. Each first region is filled with a second semiconductor material, which has a second doping. The first semiconductor material and the second semiconductor material are different. Each first region is connected electrically to the second layer. The second doping is higher than the first doping. Heterojunctions, which behave as unipolar, rectifying junctions, form between the first layer and each first region. 18-. (canceled)9. A vertical power transistor , comprising:a semiconductor substrate, on which at least one first layer and one second layer are situated, the second layer being situated on the first layer, and the first layer including a first semiconductor material; anda plurality of trenches which extend from an upper side of the second layer into the first layer, so that a respective trench bottom of each of the trenches is surrounded by the first layer; the first layer has a first doping, and each of the trenches has a first region which extends from the respective trench bottom to a first level, each of the first regions being filled with a second semiconductor material, which has a second doping;', 'the first semiconductor material and the second semiconductor material are different from one another;', 'each of the first regions is connected electrically to the second layer; and', 'the second doping being higher than the first doping, so that heterojunctions, which behave as unipolar, rectifying junctions, form between the first layer and each of the first regions., ' ...

HIGH-VOLTAGE TRENCH JUNCTION BARRIER SCHOTTKY DIODE

In a Schottky diode having an n-type substrate, an n-type epitaxial layer, at least two p-doped trenches introduced into the n-type epitaxial layer, mesa regions between adjacent trenches, a metal layer functioning as a cathode electrode, and another metal layer functioning as an anode electrode, the thickness of the epitaxial layer is more than four times the depth of the trenches. 18-. (canceled)9. A Schottky diode , comprising:{'sup': '+', 'an n substrate;'}an n-epitaxial layer having a thickness D_epi;at least two trenches introduced into the n-epitaxial layer, each trench having a width Wt and a depth Dt;mesa regions each having a width Wm, wherein each mesa region is provided between two adjacent trenches;{'sup': '+', 'a metal layer functioning as a cathode electrode on the rear side of the n substrate of the Schottky diode; and'}a metal layer functioning as an anode electrode on the front side of the Schottky diode, the metal layer forming an ohmic contact with the trenches and a Schottky contact with the n-epitaxial layer; the following equation holds for the depth Dt of the trenches and the thickness D_epi of the n-epitaxial layer: K·Dt4;', 'the following equation holds for the ratio of the depth Dt of the trenches to the width Wm of the mesa regions: Dt/Wm≧2; and', 'the following relationship holds: NA·Wt>>ND·Wm, where NA is the doping concentration of the trenches, Wt is the width of each of the trenches, ND is the doping concentration of the n-epitaxial layer, and Wm is the width of the mesa region between two trenches., 'wherein10. The Schottky diode as recited in claim 9 , wherein the trenches are filled with highly p-doped material to form p regions claim 9 , and wherein the breakdown voltage of PN junctions between the p regions and the n-epitaxial layer is lower than the breakdown voltage of the Schottky contact between the metal layer and the n-epitaxial layer.11. The Schottky diode as recited in claim 10 , wherein the Schottky ...

Schottky diode

A semiconductor system of a Schottky diode is described having an integrated PN diode as a clamping element, which is suitable in particular as a Zener diode having a breakdown voltage of approximately 20 V for use in motor vehicle generator systems. The semiconductor system of the Schottky diode includes a combination of a Schottky diode and a PN diode. The breakdown voltage of the PN diode is much lower than the breakdown voltage of the Schottky diode, the semiconductor system being able to be operated using high currents during breakdown operation.

RECTIFIER DIODE

A pseudo-Schottky diode has an n-channel trench MOSFET which includes: a cathode, an anode, and located between the cathode and the anode, the following elements: a highly n-doped silicon substrate; an n-doped epilayer having a trench extending into the n-doped epilayer from above; p-doped body regions provided above the n-doped epilayer and between the trenches. Highly n-doped regions and highly p-doped regions are provided on the upper surface of the p-doped body regions. Dielectric layers are provided on the side walls of the trench. The trench is filled with a first p-doped polysilicon layer, and the bottom of the trench is formed by a second p-doped layer which is in contact with the first p-doped polysilicon layer, and the second p-doped layer determines the breakdown voltage of the pseudo-Schottky diode. 113-. (canceled)14. A pseudo-Schottky diode , comprising: a cathode;', 'an anode; and', [{'sup': '+', 'a highly n-doped silicon substrate;'}, 'an n-doped epilayer having at least one trench extending into the n-doped epilayer from above;', {'sup': +', '+, 'p-doped body regions provided above the n-doped epilayer and between the trenches, wherein highly n-doped regions and highly p-doped regions are provided on the upper surface of the p-doped body regions;'}], 'located between the cathode and the anode, the following elements, 'wherein the gate region, the body regions and the source region of the MOSFET are monolithically and electrically connected to one another, and wherein the drain region of the MOSFET acts as the cathode, and wherein dielectric layers are provided on the side walls of the at least one trench, and wherein the at least one trench is filled with a first p-doped polysilicon layer, and the bottom of the at least one trench is formed by a second p-doped layer which is in contact with the first p-doped polysilicon layer, and wherein the second p-doped layer which forms the bottom of the at least one trench determines the breakdown voltage of ...

Electronic Component

An electronic component includes: a plate-shaped semiconductor element connected to a metallic contacting by a sinter layer; a dielectric layer having a surface metal layer disposed thereon, the dielectric layer being provided in an edge region of the semiconductor element, the edge region being provided with raised areas and depressions by patterning of the dielectric layer and/or the surface metal layer; and the sinter layer covers the edge region with the raised areas and depressions and thereby connects the edge region to the metallic contacting. 1. An electronic component , comprising:a plate-shaped semiconductor element connected to a metallic contacting by a sinter layer; anda dielectric layer with a surface metal layer situated on the dielectric layer, wherein the dielectric layer and a portion of the surface metal layer are provided in an edge region of the semiconductor element, the edge region being provided with raised areas and depressions by patterning of at least one of the dielectric layer and the surface metal layer, and wherein the sinter layer covers the edge region having the raised areas and depressions to connect the edge region to the metallic contacting.2. The component as recited in claim 1 , wherein the patterning is in the form of jags.3. The component as recited in claim 2 , wherein the jags are in one of rectangular claim 2 , triangular claim 2 , or a postage stamp edge form.4. The component as recited in claim 1 , wherein the patterning is configured as insular regions or as perforated structures.5. The component as recited in claim 2 , wherein the dielectric layer includes one of silicon oxide claim 2 , silicon nitride claim 2 , silicon oxynitride claim 2 , or a plastic.6. The component as recited in claim 2 , wherein the surface metal layer covers an area of the surface of the semiconductor element which is provided with the dielectric layer claim 2 , and establishes an electrical contact with the semiconductor element.7. The ...

SEMICONDUCTOR ARRAY HAVING TEMPERATURE-COMPENSATED BREAKDOWN VOLTAGE

A semiconductor array is described whose breakdown voltage has only a very low temperature coefficient or none at all and therefore there is little or no temperature-dependent voltage rise. The voltage limitation is achieved by a punch-through effect. 1. A semiconductor array , comprising:a first metal layer arranged as a cathode;a highly n-doped silicon layer contacted with the first metal layer;an additional n-doped silicon layer contacted with the highly n-doped silicon layer; and trenches are introduced into the additional n-doped silicon layer, the trenches having edge regions filled with a p-doped silicon layer, the trenches having an interior region filled with highly p-doped silicon,', 'the edge regions of the trenches are contacted with the additional metal layer via a highly p-doped layer that forms an ohmic contact with the additional metal layer,', 'the additional metal layer forms Schottky diodes with the additional n-doped layer,', 'the highly p-doped internal regions of the trenches form npn transistors together with the edge regions of the trenches and the additional n-doped layer,', 'the additional n-doped layer is arranged as a collector region,', 'the highly p-doped internal regions of the trenches are arranged as emitter regions,', 'the edge regions of the trenches function as base regions, and', 'a limitation of reverse voltages for diode-forming collector-base junctions is determined by a punch-through effect., 'an additional metal layer connected to the additional n-doped silicon layer and arranged as an anode, wherein2. The semiconductor array as recited in claim 1 , wherein the additional n-doped silicon layer is divided into two differently doped regions claim 1 , one region being contacted with the additional metal layer and the other region being contacted with the highly n-doped silicon layer.3. The semiconductor array as recited in claim 2 , wherein a doping concentration of the region contacted with the additional metal layer is lower ...

Semiconductor device and method of manufacturing a semiconductor device

Various embodiments provide a semiconductor device, wherein the semiconductor device comprises a semiconductor device chip formed at a substrate, wherein the semiconductor device chip comprises an active region formed in a center of the substrate and a boundary region free of active components of the semiconductor device chip; and a detection wiring arranged in the boundary region of the substrate and at least partially surrounding the active region, wherein the detection wiring and the semiconductor device chip are electrically isolated from each other; and wherein the detection wiring and the substrate are electrically connected with each other via a connection having a high electrical resistance. 1. A semiconductor device , the semiconductor device comprising:a semiconductor device chip formed at a substrate, wherein the semiconductor device chip comprises an active region formed at a center of the substrate and a boundary region free of active components of the semiconductor device chip; anda detection wiring arranged in the boundary region of the substrate and at least partially surrounding the active region;wherein the detection wiring and the semiconductor device chip are electrically isolated from each other; andwherein the detection wiring and the substrate are electrically connected with each other via a connection path having a high electrical resistance.2. The semiconductor device according to claim 1 , wherein the detection wiring surrounds the active region formed in the center region of the substrate.3. The semiconductor device according to claim 1 , wherein the detection wiring comprises a material selected out of the group consisting of:metal; andsemiconductor material.4. The semiconductor device according to claim 1 , wherein the detection wiring is formed so that a leakage current flowing through the detection wiring is small compared to a diode leakage current at operation temperature of the semiconductor device.5. The semiconductor device ...

Super-junction schottky pin diode

A semiconductor chip has an n + -doped substrate, above which an n-doped epilayer having trenches is introduced, the trenches being filled with p-doped semiconductor material and in each case having a highly p-doped region at their top side, such that an alternating arrangement of n-doped regions having a first width and p-doped regions having a second width is present. A first metal layer functioning as an anode is provided on the front side of the chip and forms a Schottky contact with the n-doped epilayer and forms an ohmic contact with the highly p-doped regions. A second metal layer which represents an ohmic contact and functioning as a cathode is formed on the rear side of the semiconductor chip. A dielectric layer is provided between each n-doped region and an adjacent p-doped region.

SEMICONDUCTOR SYSTEM INCLUDING A PIN DIODE

A semiconductor system includes a PIN diode including a heavily n-doped layer, a lightly n-doped layer situated on the heavily n-doped layer, and a p-doped layer situated on the lightly n-doped layer, the p-doped layer forming an ohmic contact with a first metallization and the heavily n-doped layer forming an ohmic contact with a second metallization. During operation in the forward direction, a high injection takes place in which the lightly n-doped layer is flooded with charge carriers. At least two trench structures are introduced into the lightly n-doped layer, the trench structures on a surface in contact with the n-doped surface including a dielectric layer. The surface of the lightly n-doped layer in contact with the dielectric layer includes an increased surface recombination velocity for charge carriers. 19-. (canceled)10. A semiconductor system , comprising:a PIN diode including a heavily n-doped layer, a lightly n-doped layer situated on the heavily n-doped layer, and a p-doped layer situated on the lightly n-doped layer, wherein the p-doped layer forms an ohmic contact with a first metallization and the heavily n-doped layer forms an ohmic contact with a second metallization, and wherein during operation in the forward direction, a high injection takes place in which the lightly n-doped layer is flooded with charge carriers;wherein at least two trench structures are introduced into the lightly n-doped layer, the trench structures including a dielectric layer on a surface in contact with the n-doped surface, and the surface of the lightly n-doped layer in contact with the dielectric layer having an increased surface recombination velocity.11. The semiconductor system of claim 10 , wherein the surface of the lightly n-doped layer in contact with the dielectric layer has an increased surface recombination velocity only in a portion of the trench structure.12. The semiconductor system of claim 10 , wherein the ratio of width of the trench structures to the ...

Diode having a plate-shaped semiconductor element

A diode is provided having a plate-shaped semiconductor element that includes a first side and a second side, the first side being connected by a first connecting layer to a first metallic contact and the second side being connected by a second connecting layer to a second metallic contact, the first side having a diode element in a middle area and having a further diode element in an edge area of the first side, which has crystal defects as a result of a separating process of the plate-shaped semiconductor element, the first connecting layer only establishing an electrical contact to the diode element and not to the further diode element and, on the first side, the further diode element having an exposed contact, which may be electrically contacted by the first connecting layer.

Semiconductor device having a trench MOS barrier schottky diode

A semiconductor device having a trench MOS barrier Schottky diode includes a semiconductor volume of a first conductivity type, the semiconductor volume (i) having a first side which is covered with a metal layer, and (ii) including at least one trench which extends in the first side and is at least partially filled with metal and/or with a semiconductor material of a second conductivity type. The trench has at least one wall section which includes an oxide layer, at least in areas. At least one area, situated next to the trench, of the first side covered with the metal layer has a layer, situated between the metal layer and the semiconductor volume, made of a first semiconductor material of the second conductivity type. 1. A semiconductor device having a trench MOS barrier Schottky diode , comprising:a semiconductor volume of a first conductivity type, the semiconductor volume (i) having a first side which is covered with a metal layer, and (ii) including at least one trench which extends in the first side and is at least partially filled with at least one of metal and a semiconductor material of a second conductivity type, the trench having at least one wall section which includes an oxide layer, at least in areas;wherein at least one area, situated next to the trench, of the first side covered with the metal layer has a layer, situated between the metal layer and the semiconductor volume, made of a first semiconductor material of the second conductivity type.2. The semiconductor device as recited in claim 1 , wherein the semiconductor volume includes at least two trenches.3. The semiconductor device as recited in claim 1 , wherein at least one area of a base of the at least one trench is filled with a second semiconductor material which is a semiconductor material of the second conductivity type.4. The semiconductor device as recited in claim 1 , wherein at least one area of a base of the at least one trench is converted into a second semiconductor material of ...

Semiconductor apparatus having a trench schottky barrier schottky diode

A semiconductor apparatus having a trench Schottky barrier Schottky diode, which includes: a semiconductor volume of a first conductivity type, which semiconductor volume has a first side covered with a metal layer, and at least one trench extending in the first side and at least partly filled with metal. At least one wall segment of the trench, and/or at least one region, located next to the trench, of the first side covered with the metal layer, is separated by a layer, located between the metal layer and the semiconductor volume, made of a first semiconductor material of a second conductivity type.

Trench-based diode and method for manufacturing such a diode

A semiconductor system including a planar anode contact, a planar cathode contact, and a volume of n-conductive semiconductor material, which has an anode-side end and a cathode-side end and extends between the anode contact and the cathode contact. A p-conductive area extends from the anode-side end of the volume toward the cathode-side end of the volume without reaching the cathode-side end. The p-conductive area has two sub-areas which are separated from one another in a cross section lying transversely with respect to the anode contact and the cathode contact, which delimit a sub-volume of the volume filled with n-conductive semiconductor material. The sub-volume is open toward the cathode contact, and is delimited by cathode-side ends of the sub-areas. A distance of the two sub-areas defining the opening is smaller than a distance between the two sub-areas prevailing outside of the opening and lying between anode side ends of the sub-areas.

POWER MOSFET AND METHOD FOR PRODUCING A POWER MOSFET

A power MOSFET having a substrate that has a substrate surface into which a trench structure is introduced, wherein first trenches and second trenches form the trench structure. The first trenches and second trenches are arranged in alternation. The first trenches are filled at least partially with a first material and the second trenches are filled with a second material. The first material has a first conductivity type and the second material has a second conductivity type, the first conductivity type and the second conductivity type being different from each other. 112-. (canceled).13. A power MOSFET , comprising:a substrate that has a substrate surface into which a trench structure is provided, wherein first trenches and second trenches form the trench structure, the first trenches and the second trenches being arranged in alternation, the first trenches being filled at least partially with a first material and the second trenches being filled with a second material, the first material having a first conductivity type and the second material having a second conductivity type, the first conductivity type and the second conductivity type differing from each other.14. The power MOSFET as recited in claim 13 , wherein the substrate includes at least one source layer claim 13 , a body layer claim 13 , an epilayer claim 13 , and a silicon layer claim 13 , the source layer being situated directly on the body layer claim 13 , the body layer being situated directly on the epilayer claim 13 , and the epilayer being situated on the silicon layer claim 13 , the source layer including a third material claim 13 , the epilayer including a fifth material claim 13 , and the silicon layer including a sixth material claim 13 , the third material claim 13 , the fifth material and the sixth material having the first conductivity type claim 13 , the body layer including a fourth material claim 13 , the fourth material having the second conductivity type claim 13 , the first trenches ...

Diode having a plate-shaped semiconductor element

A diode is provided having a plate-shaped semiconductor element that includes a first side and a second side, the first side being connected by a first connecting layer to a first metallic contact and the second side being connected by a second connecting layer to a second metallic contact, the first side having a diode element in a middle area and having a further diode element in an edge area of the first side, which has crystal defects as a result of a separating process of the plate-shaped semiconductor element, the first connecting layer only establishing an electrical contact to the diode element and not to the further diode element and, on the first side, the further diode element having an exposed contact, which may be electrically contacted by the first connecting layer.

RECTIFIER CIRCUIT INCLUDING A SELF-CLAMPING TRANSISTOR

A rectifier circuit is described, which includes a cathode terminal, an anode terminal and, between the cathode terminal and the anode terminal, an electronic circuit which includes at least one MOSFET transistor including an integrated inverse diode, the drain-source breakdown voltage of the MOSFET transistor operated in the avalanche mode corresponding to the clamping voltage between the cathode terminal and the anode terminal of the rectifier circuit. In addition, a method is provided for operating a rectifier circuit which contains a cathode terminal, an anode terminal and, between the cathode terminal and the anode terminal, at least one MOSFET transistor including an integrated inverse diode, the drain-source breakdown voltage of the MOSFET transistor being selected in accordance with the clamping voltage between the cathode terminal and the anode terminal, and the MOSFET transistor being operated in the avalanche mode. 18-. (canceled)9. A rectifier circuit , comprising:a cathode terminal;an anode terminal;an electronic circuit between the cathode terminal and the anode terminal, the electronic circuit including at least one MOSFET transistor having an integrated inverse diode;wherein a drain-source breakdown voltage of the MOSFET transistor operated in the avalanche mode corresponds to a clamping voltage between the cathode terminal and the anode terminal of the rectifier circuit.10. The rectifier circuit as recited in claim 9 , wherein the MOSFET transistor is a planar claim 9 , vertical DMOSFET transistor.11. The rectifier circuit as recited in claim 9 , wherein the MOSFET transistor is a trench MOS transistor.12. The rectifier circuit as recited in claim 9 , wherein the MOSFET transistor is designed in such a way that a power loss incurred in the avalanche breakdown is distributed at least approximately uniformly over the active chip area.13. The rectifier circuit as recited in claim 9 , wherein the MOSFET transistor is designed in such a way that an ...

High-voltage trench junction barrier schottky diode

一種肖特基二極體，具有－一個n+基材（10）；－一個n-磊晶層（20），其厚度（D-epi）；－至少二個做入該n-磊晶層（20）中的渠溝（70），它們更具有寬度（Wt）和深度（Dt）；－台面區域（80），位在相鄰的渠溝（70）間，其中該台面區域（80）更有一寬度（Wm）；－在該肖特基二極體的前側（V）上有一金屬層（50），當作陽極電極，磊晶層的厚度大於渠溝的深度的四倍。（圖2）

Rectifier arrangement with different rectifier elements

Gleichrichteranordnung, insbesondere Gleichrichterbrücke für einen Drehstromgenerator, die mehrere Gleichrichterelemente umfasst, wobei vorgebbare Gleichrichterelemente sich in wenigstens einer Eigenschaft von den übrigen Gleichrichterelementen unterscheiden. Die Gleichrichterelemente sind beispielsweise Dioden, die sich in den Eigenschaften Schaltzeit bzw. die Reserve Recovery-Schaltzeit (trr) und/oder Stromdichte und/oder Chipfläche und/oder Chipdicke und/oder die Durchbruchspannung (UZ) und/oder Innenwiderstand (RI) und/oder Bahnwiderstand und/oder durch eine weitere Eigenschaft, die zur Reduzierung der Welligkeit geeignet ist, voneinander unterscheiden. Rectifier arrangement, in particular rectifier bridge for a three-phase generator comprising a plurality of rectifier elements, wherein predetermined rectifier elements differ in at least one property from the other rectifier elements. The rectifier elements are, for example, diodes, which are in the properties switching time or the reserve recovery switching time (trr) and / or current density and / or chip area and / or chip thickness and / or the breakdown voltage (UZ) and / or internal resistance (RI) and / or web resistance and / or by another property that is suitable for reducing the waviness, different from each other.

DIODE WITH METAL SEMICONDUCTOR CONTACT AND METHOD FOR THEIR MANUFACTURE

MOUNTING IN BRIDGE RECTIFIER

Montage en pont redresseur comportant plusieurs éléments redresseurs. Les éléments redresseurs sont des diodes TMBS (diodes MOS à barrière de Schottky en tranchée) à tension de blocage à faible dérive. Rectifier bridge assembly comprising a plurality of rectifier elements. The rectifier elements are TMBS diodes (Schottky barrier MOS diodes in trench) with low drift clamping voltage.

Semiconductor device and method for producing the same

Semiconductor device and method for its production

Halbleiteranordnung mit einer Trench-MOS-Barrier-Schottky-Diode mit integrierter Substrat-PN-Diode als Klammerelement (TMBS-Sub-PN), die sich insbesondere als Z-Diode mit einer Durchbruchspannung von ca. 20 V zum Einsatz in Kfz-Generatorsystem eignet, wobei die (TMBS-Sub-PN) aus einer Kombination von Schottky-Diode, MOS-Struktur und Substrat-PN-Diode besteht und die Durchbruchspannung der Substrat-PN-Diode BV_pn niedriger als die Durchbruchspannung der Schottky-Diode BV_schottky und die Durchbruchspannung der MOS-Struktur BV_mos ist. Semiconductor arrangement with a trench MOS-barrier Schottky diode with integrated substrate PN diode as a clamping element (TMBS-Sub-PN), which in particular as Z-diode with a breakdown voltage of about 20 V for use in automotive generator system , wherein the (TMBS-Sub-PN) consists of a combination of Schottky diode, MOS structure and substrate PN diode and the breakdown voltage of the substrate PN diode BV_pn lower than the breakdown voltage of the Schottky diode BV_schottky and the Breakdown voltage of the MOS structure BV_mos is.

MONOLITHICALLY INTEGRATED SEMICONDUCTOR ARRANGEMENT

Rectifier circuit including a self-clamping transistor

A rectifier circuit is described, which includes a cathode terminal, an anode terminal and, between the cathode terminal and the anode terminal, an electronic circuit which includes at least one MOSFET transistor including an integrated inverse diode, the drain-source breakdown voltage of the MOSFET transistor operated in the avalanche mode corresponding to the clamping voltage between the cathode terminal and the anode terminal of the rectifier circuit. In addition, a method is provided for operating a rectifier circuit which contains a cathode terminal, an anode terminal and, between the cathode terminal and the anode terminal, at least one MOSFET transistor including an integrated inverse diode, the drain-source breakdown voltage of the MOSFET transistor being selected in accordance with the clamping voltage between the cathode terminal and the anode terminal, and the MOSFET transistor being operated in the avalanche mode.

Solderable semiconductor chip and method of manufacturing a semiconductor chip

Halbleiterchip (100) umfassend ein Halbleiterbauelement (101), das eine erste Haupterstreckungsrichtung (x) und eine zweite Haupterstreckungsrichtung (y) aufweist, wobei die erste Haupterstreckungsrichtung (x) und die zweite Haupterstreckungsrichtung (y) eine Haupterstreckungsebene bilden, wobei die Haupterstreckungsebene senkrecht zu einer Stapelrichtung (z) des Halbleiterchips (100) angeordnet ist, wobei unmittelbar auf dem Halbleiterbauelement (101) • ein erster metallischer Bereich (102), der lötfähig ist, • mindestens ein zweiter metallischer Bereich (103), der lötfähig ist und • ein dielektrischer Bereich (104) angeordnet sind, wobei der erste metallische Bereich (102) und der mindestens eine zweite metallische Bereich (103) durch den dielektrischen Bereich (104) galvanisch getrennt sind, wobei der mindestens eine zweite metallische Bereich (103) einen ersten Abstand (105) entlang der ersten Haupterstreckungsrichtung (x) zum ersten metallischen Bereich (102) aufweist, dadurch gekennzeichnet, dass auf dem ersten metallischen Bereich (102) ein erstes Lötmittel (107) angeordnet ist, das in einem ungelöteten Zustand eine vierte Schichtdicke aufweist, die mindestens ein Dreifaches des ersten Abstands (105) umfasst und ein dritter metallischer Bereich (108) auf dem ersten Lötmittel (107) angeordnet ist und der dritte metallische Bereich (108) einen dritten Abstand (109) entlang der ersten Haupterstreckungsrichtung (x) zum Rand des Halbleiterbauelements (101) aufweist, der mindestens dem Fünffachen der vierten Schichtdicke des ersten Lötmittels (107) im ungelöteten Zustand entspricht, wobei der erste metallische Bereich (102), der zweite metallische Bereich (103), der dritte metallische Bereich (108) und das erste Lötmittel (107) eine stoffschlüssige Verbindung aufweisen. A semiconductor chip (100) comprising a semiconductor device (101) having a first main extension direction (x) and a second main extension direction (y), the first main extension direction (x) and ...

Semiconductor arrangement and method for producing it

MOUNTING IN BRIDGE RECTIFIER

Montage en pont redresseur comportant plusieurs éléments redresseurs. Les éléments redresseurs sont des diodes TMBS (diodes MOS à barrière de Schottky en tranchée) à tension de blocage à faible dérive. Rectifier bridge assembly comprising a plurality of rectifier elements. The rectifier elements are TMBS diodes (Schottky barrier MOS diodes in trench) with low drift clamping voltage.

Semiconductor device and method of manufacturing same

Diode with stress reducing means

The component has lead-free high-temperature resistant extensive connections (4, 5) that are formed between a semiconductor chip (3) and parts (1, 6) of the component. The semiconductor chip is a silicon semiconductor chip and parts are copper parts. The connections are formed as low-temperature connection layers that are formed using low-temperature connection technique. Silicon carbide and gallium nitrides are utilizable as semiconductor chip. The layers are formed within silicon surfaces of the chip.

Semiconductor device having a trench MOS barrier Schottky diode

A semiconductor device having a trench MOS barrier Schottky diode includes a semiconductor volume of a first conductivity type, the semiconductor volume (i) having a first side which is covered with a metal layer, and (ii) including at least one trench which extends in the first side and is at least partially filled with metal and/or with a semiconductor material of a second conductivity type. The trench has at least one wall section which includes an oxide layer, at least in areas. At least one area, situated next to the trench, of the first side covered with the metal layer has a layer, situated between the metal layer and the semiconductor volume, made of a first semiconductor material of the second conductivity type.

Semiconductor device and methods for the production thereof

Semiconductor device and method for its manufacture

A semiconductor system having a trench MOS barrier Schottky diode, having an integrated substrate PN diode as a clamping element (TMBS-ub-PN), suitable in particular as a Zener diode having a breakdown voltage of approximately 20V for use in a vehicle generator system, the TMBS-sub-PN being made up of a combination of Schottky diode, MOS structure, and substrate PN diode, and the breakdown voltage of substrate PN diode BV_pn being lower than the breakdown voltage of Schottky diode BV_schottky and the breakdown voltage of MOS structure BV_mos.

MONOLITHICALLY INTEGRATED SEMICONDUCTOR DISPOSITION.

SE PROPONE UN DISPOSITIVO DE SEMICONDUCTORES MONOLITICAMENTE INTEGRADO, EN EL QUE EN LA SUPERFICIE PRINCIPAL DE UN TRANSISTOR NPN O PNP, MONOLITICAMENTE INTEGRADO, SE HA DISPUESTO UN ELECTRODO (D1) PARA LA LIMITACION DE LA TENSION INTERNA, EL CUAL CUBRE UNA UNICA ZONA DE TRANSICION ENTRE UNA ZONA ALTAMENTE DOTADA (5), Y EL SUBSTRATO ESCASAMENTE DOTADO (1). UNA ZONA CONTIGUA ALTAMENTE DOTADA (4) NO ES CUBIERTA POR EL ELECTRODO (D1). POR MEDIO DE LA CONEXION DEL ELECTRODO METALICO (D1) A LA TOMA (12) DE UN DIVISOR DE TENSION (R1,R2), SE PUEDE CONSEGUIR UNA TENSION DE PASO, QUE ES MAYOR QUE LA SUMA DE LA TENSION DE PASO EMPOBRECIDA Y DE LA TENSION DE PASO ENRIQUECIDA. A MONOLITHICALLY INTEGRATED SEMICONDUCTOR DEVICE IS PROPOSED, IN WHICH ON THE MAIN SURFACE OF A NPN OR PNP TRANSISTOR, MONOLITHICALLY INTEGRATED, AN ELECTRODE (D1) HAS BEEN PROVIDED FOR THE LIMITATION OF AN INTERNAL VOLTAGE, WHICH COVERS A ZONE BETWEEN A HIGHLY GIFTED AREA (5), AND THE SCARELY GIFTED SUBSTRATE (1). A HIGHLY FURNISHED CONTAINING AREA (4) IS NOT COVERED BY THE ELECTRODE (D1). THROUGH THE CONNECTION OF THE METALLIC ELECTRODE (D1) TO THE INLET (12) OF A VOLTAGE DIVIDER (R1, R2), A PASSING VOLTAGE, WHICH IS GREATER THAN THE SUM OF THE EMPOWDERED PASSING VOLTAGE AND OF THE ENRICHED STEP TENSION.

Diode system having zener diodes and a generator

A diode system and a generator, uses Zener diodes. The diode system has AC voltage terminals and DC voltage terminals, in which the Zener diodes are operable in the forward direction to rectify an AC voltage present at the AC voltage terminals, in which a lower limit is provided for the Zener voltage of the Zener diodes, and in which the lower limit of the Zener voltage is provided so that it is lower than a preset lower DC voltage.

Diode comprising a metal semiconductor contact and a method for the production thereof

The invention relates to a diode, comprising a semiconductor substrate which is located between two metallic electrodes (5, 6). Said substrate has a highly doped first zone (3) which forms an ohmic junction with the first electrode (6), a second zone (1), weakly doped with the same conductivity type, which forms a rectifying junction to a second electrode (5) and a third zone (2) which is doped with a weaker concentration of the same conductivity type than the second zone (1). The third zone (2) separates the first and second zones (1, 3) from each other and the second zone (1) is enclosed between the second electrode (5) and the third zone (2).

Semiconductor arrangement with a PN transition and method for the production of a semiconductor arrangement

Semiconductor arrangement comprising a Schottky diode

Diode

Monolithically integrated planar semiconductor device

The invention concerns a semi-conductor component in which a zone (3) is produced in a semi-conductor substrate (1, 2) and forms therewith a PN junction. A cover electrode (6) and a highly doped zone (4) are provided in the region of the developing space charge zone. The cover electrode (6) is connected to a voltage divider (Z1, R1, Z2, R2, TR) whereby the potential of the cover electrode (6) is adjusted so as to be temperature-compensated.

Generator device with improved bump strength

Die Erfindung betrifft eine Generatorvorrichtung zur Spannungsversorgung eines Kraftfahrzeugs, welche einen Generator und einen mit dem Generator verbundenen Gleichrichter aufweist. Der Gleichrichter weist zur Verbesserung der Verpolfestigkeit mindestens eine Schottkydiode auf. The invention relates to a generator device for supplying voltage to a motor vehicle, which has a generator and a rectifier connected to the generator. The rectifier has at least one Schottky diode to improve reverse polarity resistance.

Semiconductor arrangement having reduced on-state resistance

Trench based diode and method of making such a diode

Vorgestellt wird eine Halbleiteranordnung (10) mit einem flächigen Anodenkontakt (12), einem flächigen Kathodenkontakt (14), und einem ersten Volumen (16) aus n-leitfähigem Halbleitermaterial, das ein anodenseitiges Ende (16.1) und ein kathodenseitiges Ende (16.2) aufweist und sich zwischen dem Anodenkontakt und dem Kathodenkontakt erstreckt. Wenigstens ein p-leitfähiger Bereich (20) erstreckt sich vom anodenseitigen Ende (16.1) des ersten Volumens ausgehend zu dem kathodenseitigen Ende des ersten Volumens, ohne das kathodenseitige Ende zu erreichen. Die Halbleiteranordnung zeichnet sich dadurch aus, dass der p-leitfähige Bereich in einem quer zu dem Anodenkontakt und dem Kathodenkontakt liegenden Querschnitt zwei voneinander getrennte Teilbereiche (20.1, 20.2; 28.1, 28.2) aufweist, die ein mit n-leitfähigem Halbleitermaterial ausgefülltes erstes Teilvolumen (16.3) des ersten Volumens begrenzen, wobei das erste Teilvolumen zum Kathodenkontakt hin offen ist, die Öffnung (16.4) von kathodenseitigen Enden (20.3, 20.4) der Teilbereiche (20.1, 20.2; 28.1, 28.2) begrenzt wird und ein die Öffnung (16.4) definierender Abstand der beiden Teilbereiche (20.1, 20.2; 28.1, 28.2) kleiner ist als ein außerhalb der Öffnung herrschender und zwischen anodenseitigen Enden (20.5, 20.6) der Teilbereiche (20.1, 20.2; 28.1, 28.2) liegender Abstand (24) zwischen den beiden Teilbereichen. Disclosed is a semiconductor device (10) having a two-dimensional anode contact (12), a flat cathode contact (14), and a first volume (16) of n-conductive semiconductor material having an anode-side end (16.1) and a cathode-side end (16.2) and extending between the anode contact and the cathode contact. At least one p-type region (20) extends from the anode-side end (16.1) of the first volume to the cathode-side end of the first volume without reaching the cathode-side end. The semiconductor device is characterized in that the p-conductive region has, in a cross-section lying transversely to the anode ...

A semiconductor device

Es wird eine Halbleiteranordnung mit einer Trench-erter PN-Diode als Klammerelement, die sich insbesondere als Z-Diode mit einer Druchbruchspannung von ca. 20V zum Einsatz in Kfz-Generatorsystem eignet, beschrieben. Dabei besteht die TJBS aus einer Kombination von Schottky-Diode und PN-Diode. Für die Durchbruchspannungen gilt, dass die Durchbruchspannung der PN-Diode BV_pn niedriger ist als die Durchbruchspannung der Schottky-Diode BV_schottky. Daher kann die Halbleiteranordnung mit hohen Strömen im Durchbruch betrieben werden. A semiconductor arrangement with a trenched PN diode as a clamp element is described, which is particularly suitable as a Z diode with a breakdown voltage of approximately 20V for use in a motor vehicle generator system. The TJBS consists of a combination of Schottky diode and PN diode. For the breakdown voltages, the breakdown voltage of the PN diode BV_pn is lower than the breakdown voltage of the Schottky diode BV_schottky. Therefore, the semiconductor device can be operated with high currents in the breakdown.

Rectifier circuit, electronic component, generator and method for operating a rectifier circuit

Es wird eine Gleichrichterschaltung, welche einen Kathodenanschluss (K1), einen Anodenanschluss (A1) und zwischen dem Kathodenanschluss (K1) und dem Anodenanschluss (A1) eine elektronische Schaltung (2) aufweist, die mindestens einen MOSFET-Transistor (T1) mit integrierter lnversdiode (D6) enthält, beschrieben, wobei die Drain-Source-Durchbruchsspannung des im Avalanchebetrieb betriebenen MOSFET-Transistors (T1) der Klammerspannung zwischen dem Kathodenanschluss (K2) und dem Anodenanschluss (A2) der Gleichrichterschaltung (1) entspricht. Ferner wird ein Verfahren zum Betreiben einer Gleichrichterschaltung, welche einen Kathodenanschluss (K1), einen Anodenanschluss (A1) und zwischen dem Kathodenanschluss (K1) und dem Anodenanschluss (A1) mindestens einen MOSFET-Transistor (T1) mit integrierter lnversdiode (D6) enthält, vorgeschlagen, wobei die Drain-Source-Durchbruchspannung des MOSFET-Transistors (T1) entsprechend der Klammerspannung zwischen dem Kathodenanschluss (K2) und dem Anodenanschluss (A2) gewählt wird und der MOSFET-Transistor (T1) im Avalanchebetrieb betrieben wird. It is a rectifier circuit having a cathode terminal (K1), an anode terminal (A1) and between the cathode terminal (K1) and the anode terminal (A1) an electronic circuit (2), the at least one MOSFET transistor (T1) with integrated inverse diode (D6), wherein the drain-source breakdown voltage of the operated in Avalanchebetrieb MOSFET transistor (T1) of the clamping voltage between the cathode terminal (K2) and the anode terminal (A2) of the rectifier circuit (1) corresponds. Further, a method of driving a rectifier circuit including a cathode terminal (K1), an anode terminal (A1), and between the cathode terminal (K1) and the anode terminal (A1) includes at least one inverse-diode integrated-diode (D6) MOSFET transistor (T1), proposed, wherein the drain-source breakdown voltage of the MOSFET transistor (T1) is selected according to the clamping voltage between the cathode terminal (K2) and the ...

Semiconductor arrangement comprising a Schottky diode

Method For Manufacturing Semiconductor Chips From A Wafer

A method is for manufacturing semiconductor chips from a wafer which includes a plurality of semiconductor chips. Defects in the crystal structure of the chips may be substantially reduced by producing rupture joints in the surface of the wafer after the wafer has been produced, and by breaking the wafer along the rupture joints to separate the semiconductor chips.

Halbleiterbauelement

Semiconductor arrangement with a PN transition and method for the production of a semiconductor arrangement

Lateral semiconductor structure for forming a temperature-compensated voltage limitation

A lateral semiconductor structure having a punch-through diode for forming a temperature-compensated voltage limitation in which the space charge resistance is reduced through a lateral arrangement of preferably annular regions around a base trough. This is achieved in that the preferably annular regions are arranged with a specific doping as well as a specific separation from the base trough. By using the punch-through and avalanche effects, a higher breakdown voltage is achieved since the space charge resistance is reduced by the chosen arrangement.

集積化された垂直形半導体素子

(57)【要約】 【課題】 省スペースであるにもかかわらず絶縁耐力を 備えた高抵抗な配置構成で裏側領域電位に相関付けされ た電気量を供給することのできる垂直形半導体素子を提 供すること。 【解決手段】 スイッチング手段を垂直に配設する。

Halbeleiterdiode und verfahren zu ihrer herstellung

Bei einer aus mehreren Teilschichten (1, 2, 3, 4) bestehenden Halbleiteranordnung (20) grenzt eine Teilschicht (4) über den grössten Teil einer Querschnittsfläche BC im Inneren der Halbleiteranordnung (20) unmittelbar an eine erste Teilschicht (2) und nur in einem vergleichsweise schmalen Randbereich der Querschnittsfläche BC an eine zweite Teilschicht (l). Die Halbleiteranordnung zeichnet sich durch einen geringen Bahnwiderstand und eine hohe Durchbruchsspannung im Randbereich aus. Weiter wird ein Verfahren zur Herstellung dieser Halbleiteranordnung angegeben.

Electronic switch with a definite breakdown voltage

An electronic switch, in particularly a transistor, has at least one barrier layer extending between regions of different doping concentrations within a semiconductor and is characterized in that the barrier layer has at least one voltage limiting zone (Z) having a radius of curvature (R) less than or at most equal to the diffusion depth (x JB ) of the diffused junction.

Electric semiconductor element with a contact hole

An electric semiconductor component includes a monocrystalline semiconductor substrate made of silicon, for example, an insulation layer arranged on the surface of the semiconductor substrate and penetrated by a contact hole in at least one location and a contact element that contacts the semiconductor substrate through the contact hole and is made of a material in which the semiconductor material of the substrate is soluble in an anisotropic dissolving process. The edges of the contact hole are configured as diffusion stop structures.

Schottkydiode

Es wird eine Halbleiteranordnung einer Schottkydiode mit integrierter PN-Diode als Klammerelement beschrieben, die sich insbesondere als Z-Diode mit einer Durchbruchspannung von ca. 20V zum Einsatz in Kfz-Generatorsystem eignet. Dabei besteht die Halbleiteranordnung der Schottkydiode aus einer Kombination von Schottkydiode und PN-Diode. Die Durchbruchspannung der PN-Diode BV_pn ist sehr viel niedriger als die Durchbruchspannung der Schottkydiode BV _ schottkyt , wobei die Halbleiteranordnung mit hohen Strömen im Durchbruch betrieben werden kann.

Gleichrichteranordnung, welche schottkydioden aufweist

Die Erfindung betrifft eine Gleichrichteranordnung, welche Einpressdioden aufweist, die als Halbleiterelement eine Schottkydiode enthalten. Die Schottkydioden werden in einem Arbeitsbereich betrieben, bei dem die Diodenverluste mit zunehmender Temperatur ansteigen.

Rectifier arrangement having schottky diodes

Verfahren zum betreiben eines generators mit einer gleichrichteranordnung, welche schottkydioden aufweist

Vertikaler Leistungstransistor mit verbesserter Leitfähigkeit und hohem Sperrverhalten

Vertikaler Leistungstransistor (200, 300) mit mindestens einer Epitaxieschicht (203, 303), die ein erstes Halbleitermaterial umfasst, das mit ersten Ladungsträgern dotiert ist, und einer Mehrzahl von ersten Gräben (207, 307) und zweiten Gräben (220, 320), wobei die ersten Gräben (207, 307) und die zweiten Gräben (220, 320) alternierend angeordnet sind und sich ausgehend von einer Oberfläche der Epitaxieschicht (103, 203) ins Innere der Epitaxieschicht (203, 303) erstrecken, dadurch gekennzeichnet, dass die zweiten Gräben (220, 320) mit einem zweiten Halbleitermaterial (218, 318) verfüllt sind, das mit zweiten Ladungsträgern dotiert ist, wobei die ersten Ladungsträger und die zweiten Ladungsträger verschieden sind und zwischen einer Grabenoberfläche der zweiten Gräben (220, 320) und der Epitaxieschicht (203, 303) eine erste Wannenschicht (219, 319) angeordnet ist, die ein drittes Halbleitermaterial umfasst, das mit den zweiten Ladungsträgern dotiert ist, und die Grabenoberfläche der zweiten Gräben den Grabenboden des jeweiligen Grabens (207, 307) und Seitenwände des jeweiligen Grabens (207, 307) umfasst.

Generator mit gleichrichteranordnung

Es wird ein Generator, beispielsweise ein Drehstromgenerator mit einer zugeordneten Gleichrichteranordnung beschrieben, der beispielsweise zur elektrischen Spannungsversorgung eines Kraftfahrzeugs dient. Die vom Generator erzeugte Wechselspannung wird mit Hilfe der Gleichrichteranordnung mit mehreren gleichrichtenden Elementen 2 bzw. 7 gleichgerichtet. Wesentlich ist, dass die gleichrichtenden Elemente 2 des Gleichrichters mehrere Reihenschaltungen eines selbstleitenden n-Kanal JFETs und eines selbstleitenden p-Kanal JFETs aufweisen, wobei die Gateanschlüsse mit den äußeren Source- bzw. Drainkontakten des jeweils anderen Transistors verbunden sind. Alternativ können die selbstleitenden JFETs aus des gleichrichtenden Elements 2 in Figur 1 durch selbstleitende MOS-Feldeffekttransistoren (Depletion MOSFET) ersetzt werden. Der p-Kanal JFET des Ausführungsbeispiels nach Figur 1 ist dabei durch einen selbstleitenden p-Kanal MOSFET und der n-Kanal JFET durch einen selbstleitenden n-Kanal MOSFET ersetzt. Wieder erfolgt die Verschaltung der Gateanschlüsse zu den gegenüberliegenden äußeren Anschlüssen.

Verfahren zum herstellen von halbleiterchips aus einem wafer

Die Erfindung betrifft ein Verfahren zum Herstellen von Halbleiterchips (2) aus einem Wafer (1), der eine Vielzahl von Halbleiterchips (2) umfasst. Störungen in der Kristallstruktur der Chips (2) können wesentlich verringert werden, wenn in der Waferoberfläche nach der Fertigstellung des Wafers (1) Sollbruchstellen (14) erzeugt werden, und der Wafer (1) entlang der Sollbruchstellen (14) gebrochen wird, um die Halbleiterchips (2) zu vereinzeln.

Verfahren zum herstellen von halbleiterchips aus einem wafer

Die Erfindung betrifft ein Verfahren zum Herstellen von Halbleiterchips (2) aus einem Wafer (1), der eine Vielzahl von Halbleiterchips (2) umfasst. Störungen in der Kristallstruktur der Chips (2) können wesentlich verringert werden, wenn in der Waferoberfläche nach der Fertigstellung des Wafers (1) Sollbruchstellen (14) erzeugt werden, und der Wafer (1) entlang der Sollbruchstellen (14) gebrochen wird, um die Halbleiterchips (2) zu vereinzeln.

Super-junction-schottky-pin-diode

Die Erfindung betrifft einen Halbleiterchip, der ein n + -dotiertes Substrat, über dem sich eine n-dotierte Epischicht mit in die Epischicht eingebrachten, mit p-dotiertem Halbleitermaterial gefüllten Gräben, die an ihrer Oberseite jeweils einen hoch p-dotierten Bereich aufweisen, derart befindet, dass eine alternierende Anordnung von n-dotierten Bereichen mit einer ersten Breite und p-dotierten Bereichen mit einer zweiten Breite vorliegt. Des Weiteren enthält der Chip eine an seiner Vorderseite vorgesehene erste Metallschicht, die einen Schottky-Kontakt mit der n-dotierten Epischicht und einen ohmschen Kontakt mit den hoch p-dotierten Bereichen bildet und als Anodenelektrode dient. An der Rückseite des Halbleiterchips ist eine zweite Metallschicht vorgesehen, die einen ohmschen Kontakt darstellt und als Kathodenelektrode dient. Zwischen einem n-dotierten Bereich und einem benachbarten p-dotierten Bereich ist jeweils eine dielektrische Schicht vorgesehen.

Arrangement with p-doped and n-doped semiconductor layers and method for producing the same

An arrangement having p-doped semiconductor layers and n-doped semiconductor layers which exhibits transitions between the p-doped semiconductor layers and n-doped semiconductor layers, the transitions displaying a Zener breakdown upon application of a voltage characteristic of a transition, a plurality of transitions between p-doped semiconductor layers and n-doped semiconductor layers being present, and the characteristic voltages additively make up the breakdown voltage of the entire arrangement. Also described is a method for manufacturing the arrangement.

Verfahren zur herstellung hochdotierter halbleiterbauelemente

Es wird ein Verfahren zur Herstellung von Halbleiterbauelementen vorgeschlagen, bei dem in einem Wafer mindestens ein dotiertes Gebiet eingebracht wird, wobei zumindest auf einer der beiden Seiten eines Halbleiterwafers (1) eine mit Dotierstoff versehene feste Glasschicht (2; 4; 2, 3; 4, 5) aufgebracht wird, in einem weiteren Schritt der Wafer auf hohe Temperaturen erhitzt wird, so dass der Dotierstoff aus der Glasschicht tief in den Wafer eindringt zur Erzeugung des mindestens einen dotierten Gebiets (10; 11), und in einem weiteren Schritt die Glasschicht entfernt wird. Das Verfahren dient zur Herstellung homogener hoch dotierter Gebiete, wobei diese Gebiete auch beidseitig im Wafer eingebracht werden können und von unterschiedlichem Dotiertyp sein können.

Gleichrichteranordnung

Gleichrichteranordnung insbesondere für einen Generator, mit einer Brückenanordnung mit einer vorgebbaren Anzahl von Gleichrichterelementen, wobei mindestens ein Gleichrichterelement (D1+ - D6-) ein Gleichrichterelement mit zumindest in einem vorgebbaren Bereich sperrspannungsunabhängiger Kennlinie ist und beispielsweise eine der Minusdioden (D1+ - D6-) einen höheren Sperrsättigungsstrom als die dazugehörige Plusdiode aufweist und wobei mindestens eine der Minusdioden an einer Stelle im Gleichrichter platziert wird, bei der die Temperatur erhöht ist.

Diode inseree tres resistante a des alternances de temperature

Diode insérée ayant une puce semi-conductrice fixée par une couche de liaison entre un socle et un fil de tête, la couche de liaison étant en retrait en périphérie sur le côté avant de la puce par rapport au bord extérieur de la puce et la région de la puce semi-conductrice sans couche de liaison comporte une première couche de matière plastique périphérique , isolante. Une seconde couche de matière plastique (11) isolante, complètement périphérique chevauche la région d'extrémité radialement intérieure de la première couche de matière plastique (10).

耐大幅溫度變化的壓入式二極體

一種壓入式二極體，具有一個半導體晶片，利用一連接層固定在一插座和一頭金屬絲之間，其中該連接層至少在該晶片前側相對於該晶片的外緣環燒拉回，且其中在該半導體晶片之沒有連接層的區域上方有一環繞之絕緣的第一塑膠層，其中，設有一完全環繞的絕緣之第二塑膠層(11)，它和該第一塑膠層(10)的徑向內側的端區域重疊。(圖5)

Diode inseree tres resistante a des alternances de temperature

Vertikaler leistungstransistor und verfahren zur herstellung des vertikalen leistungstransistors

Vertikaler Leistungstransistor (1) mit einem Halbleitersubstrat (2), das ein erstes Halbleitermaterial umfasst und mindestens eine Epitaxieschicht (3) aufweist, wobei sich eine Grabenstruktur von einer Oberfläche des Halbleitersubstrats (2) ins Innere der mindestens einen Epitaxieschicht (3) erstreckt, dadurch gekennzeichnet, dass die Grabenstruktur erste Bereiche (13) aufweist, die sich jeweils von einem Grabenboden bis zu einer bestimmten Höhe des jeweiligen Grabens erstrecken, wobei die ersten Bereiche (13) erste Teilbereiche umfassen, die jeweils eine erste Tiefe (t1) und eine erste Weite (wl) aufweisen, wobei sich die ersten Teilbereiche im Wesentlichen senkrecht zur Oberfläche des Halbleitersubstrats (2) erstrecken, wobei die ersten Bereiche (13) zweite Teilbereiche umfassen, die jeweils eine zweite Tiefe und eine zweite Weite (w2) aufweisen, wobei die zweiten Teilbereiche einen ersten Neigungswinkel zur Oberfläche des Halbleitersubstrats (2) aufweisen, wobei die ersten Bereiche (13) dritte Teilbereiche umfassen, die jeweils eine dritte Tiefe und eine dritte Weite aufweisen, wobei die dritten Teilbereiche einen zweiten Neigungswinkel zur Oberfläche des Halbleitersubstrats (2) aufweisen, wobei die ersten Bereiche (13) mit einem Sourceanschluss elektrisch leitend verbunden sind.

Halbleiterbauelement und verfahren zur herstellung eines halbleiterbauelements

Halbleiterbauelement (200, 300, 400) mit einem Halbleitersubstrat (201, 301, 401), das eine erste Seite aufweist auf der eine Epitaxieschicht (202, 302, 402) angeordnet ist, wobei auf der Epitaxieschicht (202, 302, 402) bereichsweise Bodygebiete (203, 303, 403) angeordnet sind und auf den Bodygebieten (203, 303, 403) Sourcegebiete (204, 304, 404) angeordnet sind, wobei sich eine Vielzahl erster Gräben (205, 305, 405) und eine Vielzahl zweiter Gräben (206, 306, 406) ausgehend von den Sourcegebieten (204, 304, 404) bis in die Epitaxieschicht (202, 302, 402) erstrecken, wobei die ersten Gräben (205, 305, 405) eine größere Tiefe aufweisen als die zweiten Gräben (206, 306, 406), wobei sich jeweils ein zweiter Graben (206, 306, 406) bereichsweise in einen ersten Graben (205, 305, 405) erstreckt, dadurch gekennzeichnet, dassauf einer Grabenoberfläche der ersten Gräben (205, 305, 405) jeweils eine Schicht mit einer ersten Dotierung angeordnet ist, wobei die ersten Gräben (205, 305, 405) mit einem ersten Material (207, 307, 407) verfüllt sind, das eine zweite Dotierungskonzentration aufweist, wobei die erste Dotierungskonzentration einen höheren Wert aufweist als die zweite Dotierungskonzentration.

Vertikaler feldeffekttransistor und verfahren zum herstellen desselben

Es wird ein vertikaler Feldeffekttransistor (200) bereitgestellt, aufweisend: einen Driftbereich (2) mit einem ersten Leitfähigkeitstyp; eine erste Grabenstruktur (3a) auf oder über dem Driftbereich (2), wobei eine Gate-Elektrode (5) in der ersten Grabenstruktur (3a) angeordnet ist und wobei die erste Grabenstruktur (3a) mindestens eine Seitenwand aufweist und die erste Grabenstruktur (3a) an der mindestens einen Seitenwand eine Gate-Dielektrikum- Schicht (4) aufweist; eine zweite Grabenstruktur (3b), die lateral neben der mindestens einen Seitenwand der ersten Grabenstruktur (3a) angeordnet ist und sich vertikal bis in den Driftbereich (2) oder vertikal weiter in Richtung des Driftbereichs (2) erstreckt als die erste Grabenstruktur (3a), wobei die zweite Grabenstruktur (3b) einen zweiten Leitfähigkeitstyp aufweist, der sich von dem ersten Leitfähigkeitstyp unterscheidet; und eine Source-Elektrode (9) auf oder über dem Driftbereich (2), die mit der zweiten Grabenstruktur (3b) elektrisch leitfähig verbunden ist.

Vertikaler leistungstransistor und verfahren zur herstellung des vertikalen leistungstransistors

Vertikaler Leistungstransistor (1) mit einem Halbleitersubstrat (2), das ein erstes Halbleitermaterial umfasst und mindestens eine Epitaxieschicht (3) aufweist, wobei sich eine Grabenstruktur von einer Oberfläche des Halbleitersubstrats (2) ins Innere der mindestens einen Epitaxieschicht (3) erstreckt, dadurch gekennzeichnet, dass die Grabenstruktur erste Bereiche (13) aufweist, die sich jeweils von einem Grabenboden bis zu einer bestimmten Höhe des jeweiligen Grabens erstrecken, wobei die ersten Bereiche (13) erste Teilbereiche umfassen, die jeweils eine erste Tiefe (t1) und eine erste Weite (wl) aufweisen, wobei sich die ersten Teilbereiche im Wesentlichen senkrecht zur Oberfläche des Halbleitersubstrats (2) erstrecken, wobei die ersten Bereiche (13) zweite Teilbereiche umfassen, die jeweils eine zweite Tiefe und eine zweite Weite (w2) aufweisen, wobei die zweiten Teilbereiche einen ersten Neigungswinkel zur Oberfläche des Halbleitersubstrats (2) aufweisen, wobei die ersten Bereiche (13) dritte Teilbereiche umfassen, die jeweils eine dritte Tiefe und eine dritte Weite aufweisen, wobei die dritten Teilbereiche einen zweiten Neigungswinkel zur Oberfläche des Halbleitersubstrats (2) aufweisen, wobei die ersten Bereiche (13) mit einem Sourceanschluss elektrisch leitend verbunden sind.

Vertikaler leistungstransistor mit verbesserter leitfähigkeit und hohem sperrverhalten

Vertikaler Leistungstransistor (100, 200) mit mindestens einer Epitaxieschicht (103, 203), die ein erstes Halbleitermaterial umfasst, das mit ersten Ladungsträgern dotiert ist, und einer Mehrzahl von Gräben (107, 207), wobei sich die Gräben (107, 207) ausgehend von einer Oberfläche der Epitaxieschicht (103, 203) ins Innere der Epitaxieschicht (103, 203) erstrecken, dadurch gekennzeichnet, dass jeder Graben (107, 207) einen Bereich (108, 208) aufweist, der sich vom Grabenboden bis zu einer bestimmten Höhe erstreckt, wobei der Bereich (108, 208) mindestens teilweise mit einem zweiten Halbleitermaterial (109, 209) verfüllt ist, das mit zweiten Ladungsträgern dotiert ist und der Bereich (108, 208) elektrisch mit einem Sourcegebiet (105, 205) verbunden ist, wobei die ersten Ladungsträger und die zweiten Ladungsträger verschieden sind.

Elektrisches halbleiterbauelement mit einem kontaktloch

Ein elektrisches Halbleiterbauelement umfasst ein einkristallines Halbleitersubstrat, zum Beispiel aus Silicium, eine an wenigstens einer Stelle von einem Kontaktloch (30) durchbrochene, an der Oberfläche des Halbleitersubstrats (1) angeordnete Isolationsschicht (6) und ein das Halbleitersubstrat (1) durch das Kontaktloch (30) berührendes Kontaktelement aus einem Material wie zum Beispiel Aluminium, in dem das Halbleitermaterial des Substrats in einem anisotropen Lösevorgang löslich ist. Die Ränder des Kontaktlochs (30) sind als Diffusionsstoppstrukturen ausgebildet.

Elektrisches halbleiterbauelement mit einem kontaktloch

Ein elektrisches Halbleiterbauelement umfasst ein einkristallines Halbleitersubstrat, zum Beispiel aus Silicium, eine an wenigstens einer Stelle von einem Kontaktloch (30) durchbrochene, an der Oberfläche des Halbleitersubstrats (1) angeordnete Isolationsschicht (6) und ein das Halbleitersubstrat (1) durch das Kontaktloch (30) berührendes Kontaktelement aus einem Material wie zum Beispiel Aluminium, in dem das Halbleitermaterial des Substrats in einem anisotropen Lösevorgang löslich ist. Die Ränder des Kontaktlochs (30) sind als Diffusionsstoppstrukturen ausgebildet.

Semiconductor device and its manufacturing method

僞肖特基二極體

一種偽肖特基二極體，其具有一種n通道渠溝MOS場效電晶體，該n通道渠溝MOS場效電晶體具有：一陰極、一陽極，一高n+摻雜的矽基材，位在該陰極與該陽極間，一n摻雜的磊晶層，一些渠溝，其延伸到該n摻雜的磊晶層中，一些p摻雜的體領域，其設在該渠溝之間，一些高n+摻雜的區域，設在該體領域的表面，及一些高p+摻雜的區域，其中該電晶體的閘極、體領域和源極的領域係是單晶方式及導電方式互相連接，且其中該電晶體的排極的領域當作陰極，其中在該渠溝的側邊緣設有介電層，該些渠溝用一p摻雜的多晶矽層充填，渠溝的底由另外之p摻雜的層形成，該另外之p摻雜的層與該p摻雜的多晶矽層接觸，其中該渠溝的底由另一p摻雜的層形成，該層與該p摻雜的多晶矽層接觸，且其中該另外之p摻雜層決定該偽肖特徵二極體的貫穿電壓。

Vertikaler leistungstransistor mit verbesserter leitfähigkeit und hohem sperrverhalten

Vertikaler Leistungstransistor (200, 300) mit mindestens einer Epitaxieschicht (203, 303), die ein erstes Halbleitermaterial umfasst, das mit ersten Ladungsträgern dotiert ist, und einer Mehrzahl von ersten Gräben (207, 307) und zweiten Gräben (220, 320), wobei die ersten Gräben (207, 307) und die zweiten Gräben (220, 320) alternierend angeordnet sind und sich ausgehend von einer Oberfläche der Epitaxieschicht (103, 203) ins Innere der Epitaxieschicht (203, 303) erstrecken, dadurch gekennzeichnet, dass die zweiten Gräben (220, 320) mit einem zweiten Halbleitermaterial (218, 318) verfüllt sind, das mit zweiten Ladungsträgern dotiert ist, wobei die ersten Ladungsträger und die zweiten Ladungsträger verschieden sind und zwischen einer Grabenoberfläche der zweiten Gräben (220, 320) und der Epitaxieschicht (203, 303) eine erste Wannenschicht (219, 319) angeordnet ist, die ein drittes Halbleitermaterial umfasst, das mit den zweiten Ladungsträgern dotiert ist, und die Grabenoberfläche der zweiten Gräben den Grabenboden des jeweiligen Grabens (207, 307) und Seitenwände des jeweiligen Grabens (207, 307) umfasst.