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Применить Всего найдено 3. Отображено 3.
09-01-2014 дата публикации

METHOD AND SYSTEM FOR TIME INTERLEAVED ANALOG-TO-DIGITAL CONVERTER TIMING MISMATCH ESTIMATION AND COMPENSATION

Номер: US20140009318A1
Автор: Anandakumer Anand, Chen Xuefeng, Gallagher Timothy Leo, Taluja Pawandeep, Ye Sheng, Zhu Mingrui
Принадлежит:

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients. 1. A method for wireless communication , the method comprising:receiving an analog signal on a chip;converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC); andreducing a blocker signal that is aliased onto a desired digital signal by a timing offset in said time interleaved ADC, by estimating complex coupling coefficients between said desired digital signal and said blocker signal utilizing a decorrelation algorithm in timing offset estimation and compensation circuitry.2. The method according to claim 1 , wherein the decorrelation algorithm comprises a symmetric adaptive decorrelation algorithm..3. The method according to claim 1 , comprising approximating an amplitude of said blocker signal as linear within said desired frequency bandwidth.4. The method according to claim 1 , comprising performing a foreground estimation and timing offset compensation by generating the received ...

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Номер записи: 1
11-02-2016 дата публикации

Method and system for Time Interleaved Analog-To-Digital Converter Timing Mismatch Estimation And Compensation

Номер: US20160043731A1
Автор: Anandakumer Anand, Chen Xuefeng, Gallagher Timothy Leo, Taluja Pawandeep, Ye Sheng, Zhu Mingrui
Принадлежит:

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients. 120-. (canceled)21. A method for wireless communication , the method comprising:receiving an analog signal on a chip;converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC); andreducing a blocker signal that is aliased onto a desired digital signal by a timing offset in said time interleaved ADC, by estimating complex coupling coefficients between said desired digital signal and said blocker signal.22. The method according to claim 21 , comprising estimating said complex coupling coefficients utilizing a decorrelation algorithm running in timing offset estimation and compensation circuitry.23. The method according to claim 21 , comprising approximating an amplitude of a blocker signal as linear within a desired frequency bandwidth.24. The method according to claim 21 , comprising performing a foreground estimation and timing offset compensation by generating the received analog signal utilizing a calibration tone generator on said chip.25. The method ...

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Номер записи: 2
07-05-2015 дата публикации

METHOD AND SYSTEM FOR TIME INTERLEAVED ANALOG-TO-DIGITAL CONVERTER TIMING MISMATCH ESTIMATION AND COMPENSATION

Номер: US20150124915A1
Автор: Anandakumer Anand, Chen Xuefeng, Gallagher Timothy Leo, Taluja Pawandeep, Ye Sheng, Zhu Mingrui
Принадлежит:

Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may comprise receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients. 120-. (canceled)21. A method for wireless communication , the method comprising:receiving an analog signal on a chip;converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC); andreducing a blocker signal that is aliased onto a desired digital signal by a timing offset in said time interleaved ADC, by estimating complex coupling coefficients between said desired digital signal and said blocker signal utilizing timing offset estimation and compensation circuitry.22. The method according to claim 21 , comprising utilizing claim 21 , by the timing offset estimation and compensation circuitry claim 21 , a decorrelation algorithm.23. The method according to claim 21 , comprising approximating an amplitude of said blocker signal as linear within said desired frequency bandwidth.24. The method according to claim 21 , comprising performing a foreground estimation and timing offset compensation by generating the received analog signal utilizing a calibration tone generator on said ...

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Номер записи: 3