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Применить Всего найдено 5. Отображено 5.
23-05-2019 дата публикации

PACKAGE WITH ISOLATION STRUCTURE

Номер: US20190157222A1
Автор: Nishant LAKHERA, Andrew Jefferson MAWER, Akhilesh Kumar SINGH, Navas Khan ORATTI KALANDAR, LAKHERA NISHANT, MAWER ANDREW JEFFERSON, SINGH AKHILESH KUMAR, ORATTI KALANDAR NAVAS KHAN, LAKHERA, Nishant, MAWER, Andrew Jefferson, SINGH, Akhilesh Kumar, ORATTI KALANDAR, Navas Khan
Принадлежит:

Embodiments are provided herein for a packaged semiconductor device that includes a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and an isolation structure on the outer surface of the RDL structure around one or more contact pads of the plurality of contact pads, wherein a height of the isolation structure is at least two thirds of a height of the external connections. 1. A packaged semiconductor device comprising:a package comprising: a semiconductor die, and a redistribution layer (RDL) structure on an active side of the semiconductor die;a plurality of contact pads on an outer surface of the RDL structure;a plurality of external connections attached to the plurality of contact pads; andan isolation structure on the outer surface of the RDL structure around a set of at least two contact pads of the plurality of contact pads, wherein a height of the isolation structure is at least two thirds of a height of the external connections.2. The packaged semiconductor device of claim 1 , wherein the set of at least two contact pads are connected to radio frequency (RF) signal lines of the semiconductor die.3. The packaged semiconductor device of claim 1 , whereinthe plurality of external connections is configured to be attached to a plurality of landing pads of a printed circuit board (PCB), andan edge of the isolation structure is configured to be separated from the PCB by a stand off height.4. The packaged semiconductor device of claim 3 , whereinthe isolation structure is configured to be a barrier between a set of at least two external connections attached to the set of at least two contact pads and an adhesive material between the RDL structure and the PCB.5. The packaged semiconductor device of claim 1 , whereinthe isolation structure ...

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Номер записи: 1
24-03-2022 дата публикации

PACKAGED SEMICONDUCTOR DEVICE ASSEMBLY

Номер: US20220093499A1
Автор: Foong Chee Seng, Lakhera Nishant, Mahatme Nihaar N., Mawer Andrew Jefferson, Singh Akhilesh Kumar
Принадлежит:

A semiconductor device comprises a substrate including a set of interconnect pads, a die mounted on the substrate, wherein the die includes circuitry that cannot withstand typical lead-free (Pb-free) solder reflow temperature during reflow process, and a reinforcing interposer including a first set of interconnect pads and a second set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads on the substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer. A printed circuit board includes a set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads of the printed circuit board to a corresponding one of the second set of interconnect pads of the reinforcing interposer. The low temperature solder material has a reflow temperature below typical Pb-free solder material. 1. A semiconductor device comprising:a substrate including a set of interconnect pads;a die mounted on the substrate, wherein the die includes circuitry that cannot withstand temperatures above a lead-free (Pb-free) solder reflow temperature during a solder reflow process; a first set of interconnect pads, and', 'a second set of interconnect pads;, 'a reinforcing interposer includinglow temperature solder material connecting one of the set of interconnect pads on the substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer;a printed circuit board;a set of interconnect pads on the printed circuit board;low temperature solder material connecting one of the set of interconnect pads of the printed circuit board to a corresponding one of the second set of interconnect pads of the reinforcing interposer,wherein the low temperature solder material has a reflow temperature below the Pb-free solder reflow temperature.2. The semiconductor device of wherein:the die is mounted on the first major surface of the substrate using Pb-free solder ...

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Номер записи: 2
20-02-2024 дата публикации

Packaged semiconductor device assembly

Номер: US11908784B2
Автор: Akhilesh Kumar Singh, Andrew Jefferson MAWER, Chee Seng Foong, Nihaar N. Mahatme, Nishant Lakhera
Принадлежит: NXP USA Inc

A semiconductor device comprises a substrate including a set of interconnect pads, a die mounted on the substrate, wherein the die includes circuitry that cannot withstand typical lead-free (Pb-free) solder reflow temperature during reflow process, and a reinforcing interposer including a first set of interconnect pads and a second set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads on the substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer. A printed circuit board includes a set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads of the printed circuit board to a corresponding one of the second set of interconnect pads of the reinforcing interposer. The low temperature solder material has a reflow temperature below typical Pb-free solder material.

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Номер записи: 3
03-05-2023 дата публикации

Stacking a semiconductor die and chip-scale-package unit

Номер: EP4174918A2
Автор: Akhilesh Kumar Singh, Andrew Jefferson MAWER, Chee Seng Foong, Franciscus Henrikus Martinus Swartjes
Принадлежит: NXP BV

There is disclosed a semiconductor package assembly comprising: a substrate (110) having a top substrate surface (112) and a substrate bottom surface (114); a first semiconductor die (120), partially over the substrate and having a die bottom surface having first and second pluralities of I/O pads thereon; a first plurality of localised electrical connection components (LECCs) (150), affixed between the die bottom surface and the substrate top surface and providing electrical connections between the substrate and the first plurality of I/O pads; a second plurality of LECCs (118), affixed to the substrate bottom surface, and for providing electrical connection between the substrate and a circuit board (170); wherein the second plurality of I/O pads are arranged for providing electrical connections to a chip-scale-package unit (130) to be affixed to the first semiconductor die by a third plurality of LECCs (160), and to be positioned in a same horizonal plane as the substrate. Corresponding methods are also disclosed.

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Номер записи: 4
27-12-2023 дата публикации

Stacking a semiconductor die and chip-scale-package unit

Номер: EP4174918A3
Автор: Akhilesh Kumar Singh, Andrew Jefferson MAWER, Chee Seng Foong, Franciscus Henrikus Martinus Swartjes
Принадлежит: NXP BV

There is disclosed a semiconductor package assembly comprising: a substrate (110) having a top substrate surface (112) and a substrate bottom surface (114); a first semiconductor die (120), partially over the substrate and having a die bottom surface having first and second pluralities of I/O pads thereon; a first plurality of localised electrical connection components (LECCs) (150), affixed between the die bottom surface and the substrate top surface and providing electrical connections between the substrate and the first plurality of I/O pads; a second plurality of LECCs (118), affixed to the substrate bottom surface, and for providing electrical connection between the substrate and a circuit board (170); wherein the second plurality of I/O pads are arranged for providing electrical connections to a chip-scale-package unit (130) to be affixed to the first semiconductor die by a third plurality of LECCs (160), and to be positioned in a same horizonal plane as the substrate. Corresponding methods are also disclosed.

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Номер записи: 5