BRUSH HOLDER ELECTRIC MOTOR AND GEARING DRIVE UNIT EQUIPPED THEREWITH

Support de balai (100) comportant un corps de base (20) muni d'un passage (25) pour l'arbre d'induit et comportant une première zone de réception pour fixer une plaque de circuit garnie de composants électroniques ou électriques sur le corps de base (20). La première zone s'étend entre la limite extérieure du corps (20) et l'orifice de passage (25). La première zone de réception (37) reçoit la plaque de circuit pour l'essentiel perpendiculairement à son plan et sur celui-ci et comportant des composants (26, 33) reliés à la plaque de circuit. Le corps (20) comporte une seconde zone de réception pour la plaque (35), sur le côté du passage (25) opposé à la première zone et des emplacements (29, 30) pour des composants (26, 33).

MOP HOLDER FOR ELECTRIC MOTOR AND TRANSMISSION DRIVE UNIT EQUIPPED THEREWITH

INSTALLATION MACHINE BRUSH ELECTRIC OXIDE SORBENTS

Installation de balai (100) de machine électrique (10) comportant un balai (20) installé de manière à coulisser longitudinalement dans un élément de guidage de balai (21) en direction de l'élément de contact (16). Le balai (20) a un axe longitudinal (25) qui fait un premier angle (a) par rapport à l'axe de rotation (11) de l'élément de contact (16). La face arrière (23) du balai à l'opposé de la surface de contact (30) est sollicité par la force (F) d'un ressort (32) qui exerce une première composante de force (F1) sur le balai (20) dans la direction de l'élément de contact (16), et une seconde composante de force (F2), poussant le balai (20) contre la paroi (34) de l'élément de guidage de balai (21), La face frontale (22) est appliquée contre l'élément de contact (16) uniquement par une région partielle formant la surface de contact (30).

A METHOD OF AND A DEVICE FOR MAKING A WATER-IN-OIL EMULSION FROM AN OIL-IN-WATER EMULSION

Schlafeinrichtung fuer Schutzraeume,insbesondere Luftschutzbunker

A METHOD OF AND AN EQUIPMENT FOR OBTAINING BUTTER-LIKE PRODUCTS WITH A LAW CONTENT OF GREASES

REPLACEMENT GATES TO ENHANCE TRANSISTOR STRAIN

Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain. 1. A method comprising:forming an NMOS transistor including a channel, a stressor, and a gate structure over the channel and between sidewall spacers, wherein the stressor causes a tensile strain on the channel; andremoving at least a portion of the gate structure to allow the stressor to enhance the tensile strain on the channel, wherein removing the portion of the gate structure forms a trench.2. The method of claim 1 , wherein the stressor comprises a tensile layer over the gate structure.3. The method of claim 1 , wherein removing the portion of the gate structure includes removing a gate electrode claim 1 , and wherein a gate dielectric remains.4. The method of claim 3 , wherein the gate dielectric comprises a high-k gate dielectric.5. The method of claim 4 , further comprising:forming a metal gate electrode over the high-k gate dielectric.6. A method comprising:forming a PMOS transistor including a channel, a stressor, and a gate structure over the channel and between sidewall spacers, wherein the stressor causes a compressive strain on the channel; andremoving at least a portion of the gate structure to allow the stressor to enhance the compressive strain on the channel, wherein removing the portion of the gate structure forms a trench.7. The method of claim 6 , wherein the stressor comprises an epitaxial source and drain film.8. The method of claim 6 , wherein removing the portion of the gate structure includes removing a gate electrode and a gate dielectric.9. The method of claim 8 , further comprising:forming a high-k gate dielectric in the trench; andforming a metal gate electrode over the high-k gate dielectric, wherein the metal gate electrode provides an additional compressive strain in the channel. The present application is a divisional of U.S. patent application Ser. No. 11/305,465, entitled “REPLACEMENT GATES TO ENHANCE TRANSISTOR ...

METHOD TO USE COMPOSITIONS HAVING ANTIDEPRESSANT ANXIOLYTIC AND OTHER NEUROLOGICAL ACTIVITY AND COMPOSITIONS OF MATTER

The sponges were collected from a variety of locations in the Florida Keys and separated based on morphology and color. The samples were identified as three species, two of which are well known: (Esper, 1794) (order Verongida, family Aplysinidae) and (Hyatt, 1875) (order Dictyoceratida, family Thorectidae), and a third (Duchassaing & Michelotti, 1864), is less common and separated based on subtle differences of morphology and coloration, from the other two species. Several compounds were isolated and were evaluated in established animal models predictive of neurological related drug function, namely, the rodent FST and the chick anxiety-depression model. 1. A method of treating a neurological condition in an animal host in need thereof comprising:administering to said host an effective amount of an isolated and purified marine natural product,wherein said neurological condition is selected from the group consisting of depression and anxiety.4. The method of comprising: administering an effective amount of 5-6-bromo-N—N-dimethytryptamine claim 1 , wherein said neurological condition is selected from the group consisting of depression and anxiety.5. A method to sedate of an animal host comprising: administering an effective amount of 5-dibromo-N claim 1 ,N-dimethyltryptamine to said animal host according to the method of .7. The method of comprising: administering an effective amount of 3-bromotyramine to said animal host.10. A pharmaceutical formulation comprising the compound of and a pharmaceutically acceptable earlier or a pharmaceutically acceptable excipient.11. A method of treating a neurological condition in an animal host in need thereof comprising:{'claim-ref': {'@idref': 'CLM-00009', 'claim 9'}, 'administering an effective amount of the composition of to an animal host.'}12. A method of treating a neurological condition in an animal host in need thereof comprising:{'claim-ref': {'@idref': 'CLM-00010', 'claim 10'}, 'administering an effective amount of the ...

Method of assigning a relative seminality score to individual patents within a patent landscape

A method for assigning a relative score to patents within a patent landscape is described, with the objective of being able to compare any two or more patents. A patent is considered seminal if the novelty of the invention is not a product of variations of prior art and spawns a new direction in intellectual property as described by new patents that come later. The method described in this document is one that combines a number of direct and indirect network factors and tempers the method by considering proximity to other patents within the landscape, incestuous citations, and other metric quantities inherent in the patent documents and from publicly available information. The method described is a relativistic model that is generic in that it does not depend on specific success of any individual patent to produce revenue or to fend off exposure to other specified intellectual property.

Orthogonal integrated cleaving device

An orthogonal integrated cleaving apparatus and methods of controlling such an apparatus are taught. The cleaving apparatus includes two cleaving devices mounted at right angles with respect to a mount facing a substrate to be processed. The non-metallic and/or brittle substrate is separated along two orthogonal axes without rotating or moving the substrate to a second machine by moving the mount or the substrate along the axes. Each cleaving device laser sequentially heats a surface of the substrate along a respective cutting axis, cools the cut area and then laser re-heats the cut area to form a clean break.

Self-aligned contacts

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

PENETRATING IMPLANT FOR FORMING A SEMICONDUCTOR DEVICE

A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack. 1. A method of forming a system-on-a-chip , comprising:providing a substrate having a first portion and a second portion, wherein the first portion is well-free and the second portion includes a well region of a first conductivity type;forming a first gate stack above the first portion of the substrate and a second gate stack above the well region of the second portion of the substrate;forming a mask layer above the second portion of the substrate but not above the first portion of the substrate;implanting dopant impurity atoms of a second conductivity type, opposite the first conductivity type, into the first portion of the substrate to form tip regions on either side of the first gate stack, wherein the first gate stack blocks the implanting of dopant impurity atoms of the second conductivity type in the first portion of the substrate directly below the first gate stack during the formation of the tip regions, and wherein the mask layer blocks the implanting of dopant impurity atoms of the second conductivity type in the second portion of the substrate during the formation of the tip regions in the first portion of the substrate; andimplanting dopant impurity atoms of the first conductivity type into the first portion of the substrate to form halo regions adjacent the tip regions and to form a threshold voltage ...

SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS

A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder. 1. A semiconductor device , comprising:a gate stack disposed on a substrate, wherein said gate stack is comprised of a metal gate electrode above a channel region in said substrate, and a high-k gate dielectric layer between said metal gate electrode and said channel region and along the sidewalls of said metal gate electrode;an inter-layer dielectric film directly adjacent to the portions of said high-k gate dielectric layer along the sidewalls of said metal gate electrode;a pair of source/drain regions in said substrate on either side of said channel region, wherein said pair of source/drain regions is in direct contact with said high-k gate dielectric layer, and wherein the lattice constant of said pair of source/drain regions is different than the lattice constant of said channel region, said pair of source/drain regions having an undercut profile of approximately 55 degrees with respect to a horizontal axes; andregions of boron out-diffusion in said substrate and adjacent to the periphery of said pair of source/drain regions.2. The semiconductor device of claim 1 , wherein said channel region is comprised substantially of silicon atoms claim 1 , and wherein said pair of source/drain regions is comprised substantially ...

3D INTERCONNECT STRUCTURE COMPRISING FINE PITCH SINGLE DAMASCENE BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH THROUGH-SILICON VIAS

A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow. 1. A 3D interconnect structure comprising:a semiconductor substrate having a front surface and a back surface;a via extending through the semiconductor substrate between the front and back surfaces; anda single damascene redistribution layer (RDL) formed over the back surface.2. The 3D interconnect structure of claim 1 , further comprising a passivation layer disposed between the back surface and the RDL.3. The 3D interconnect structure of claim 2 , wherein the passivation layer comprises silicon carbide or silicon nitride.4. The 3D interconnect structure of claim 3 , wherein the via further comprises:an insulating liner layer formed on side surfaces of a via opening in the semiconductor substrate;a continuous barrier layer formed on a bottom surface of the via opening, and on the insulating liner layer formed on the side surfaces of the via opening; anda conductive metal filling a bulk volume of the via opening.5. The 3D interconnect structure of claim 4 , wherein the single damascene RDL further comprises:a barrier layer formed on side surfaces of a trench opening in a dielectric layer, wherein the trench opening exposes the passivation layer and the via; anda conductive metal filling a bulk volume of the trench opening.6. The 3D interconnect structure of claim 3 , further comprising:an array of landing pads arranged over the back surface in a series of rows and columns;an array of through-silicon vias (TSVs) arranged under the back surface such that the array of TSVs is not directly underneath the array of landing pads; anda plurality of RDLs running between ...

REPLACEMENT GATES TO ENHANCE TRANSISTOR STRAIN

Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain. 1. A method comprising:forming an NMOS transistor on a substrate, wherein the substrate further comprises a PMOS transistor disposed thereon, wherein the NMOS transistor comprises first channel, a first gate structure disposed on the first channel, and first sidewall spacers adjacent the first gate structure;forming a first trench in the first gate structure;forming a first high-k gate dielectric in the first trench;forming an n-type work function material on the first high-k gate dielectric disposed in the first trench; andforming a first metal gate electrode over the n-type work function material.2. The method of claim 1 , further comprising wherein a stressor is formed over the first gate structure claim 1 , wherein the stressor comprises a tensile layer over the first gate structure.3. The method of claim 1 , wherein forming the first trench comprises removing portion of the first gate structure by removing a first gate electrode and a first gate dielectric claim 1 , and wherein removing a portion of the first gate structure increases a tensile strain on the first channel.4. The method of claim 1 , further comprising: wherein the first metal gate electrode provides an additional tensile strain in the first channel.5. The method of claim 4 , wherein the first channel is stressed via the first high-k gate dielectric.6. The method of claim 4 , wherein the first channel is stressed via the first sidewall spacers.7. The method of claim 4 , wherein the first metal gate electrode includes at least one of tungsten or titanium carbide.8. The method of claim 4 , further comprising:wherein the PMOS transistor comprises a second gate structure disposed on a second channel, a second stressor disposed on the second gate structure, and second sidewall spacers adjacent the second gate structure;forming a second trench in the second gate structure;forming a ...

3D INTERCONNECT STRUCTURE COMPRISING THROUGH-SILICON VIAS COMBINED WITH FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES FABRICATED USING A DUAL DAMASCENE TYPE APPROACH

A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow. 1. A 3D interconnect structure comprising:a semiconductor substrate having a front surface and a back surface; anda dual damascene via and redistribution layer (RDL);wherein the via extends through the semiconductor substrate between the front and back surfaces, and the RDL is formed over the back surface.2. The 3D interconnect structure of claim 1 , further comprising a passivation layer disposed between the back surface and the RDL.3. The 3D interconnect structure of claim 2 , wherein the passivation layer comprises silicon carbide or silicon nitride.4. The 3D interconnect structure of claim 3 , wherein the dual damascene via and RDL further comprises an insulating liner layer formed on side surfaces of a dual damascene via and trench openings claim 3 , and not formed on bottom surfaces of the dual damascene via and trench opening.5. The 3D interconnect structure of claim 4 , wherein the dual damascene via and RDL further comprise a continuous barrier layer formed on the bottom surfaces of the dual damascene via and trench openings claim 4 , and on the insulating liner layer formed on the side surfaces of the dual damascene via and trench openings.6. The 3D interconnect structure of claim 3 , further comprising:an array of landing pads arranged over the back surface in a series of rows and columns;an array of through-silicon vias (TSVs) arranged under the back surface such that the array of TSVs is not directly underneath the array of landing pads; anda plurality of RDLs running between two of the rows of the landing pads connecting one of the two rows to a corresponding ...

THROUGH GATE FIN ISOLATION

Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes. 1. A microelectronic device , comprising:a first gate electrode disposed over a first semiconductor fin;a second gate electrode disposed over a second semiconductor fin,a first isolation region disposed between the first and second gate electrodes and separating adjacent ends of the first and second semiconductor fins,wherein the first electrode, second gate electrode, and first isolation region are substantially parallel with longitudinal centerlines at a substantially equal pitch.2. The microelectronic device of claim 1 , further comprising a second isolation region disposed on an end of the first semiconductor fin opposite the first isolation region claim 1 , wherein centerlines of the first and second isolation regions define an isolation region pitch that is an integer multiple of a minimum pitch for the gate electrodes.3. The microelectronic device of claim 2 , wherein centerlines the first and second gate electrodes define a gate electrode pitch that is an integer multiple of the minimum gate electrode pitch.4. The microelectronic device of claim 3 , wherein the gate electrode pitch is substantially equal to the isolation region pitch with the gate electrodes and isolation regions forming stripes at a minimum stripe pitch.5. The microelectronic device ...

Heat transfer apparatus and method

A method is provided for heat transfer from a surface to a fluid. The method includes directing a first fluid flow towards the surface in a first direction and directing a second fluid flow towards the surface in a second direction. The first and second fluid flows cooperate to cool the surface.

Two stage melting and casting system and method

A system for two stage casting of a metal alloy is disclosed that dispenses multiple feedstock metals into an arc melting crucible via a pressurized inert gas or metal vapor chamber to lower the volatilization rate of metals in an arc melting crucible at a rate proportional to the composition of the final desired alloy. The melt from the melting crucible enters a second stage cold wall crucible through a passage, where the melt cools and solidifies. A casting piston is used to slowly and progressively withdraw the solidified alloy from the cold wall crucible as it cools.

SELF-ALIGNED CONTACTS

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. 1. A semiconductor structure , comprising:a gate electrode over a portion of a silicon substrate, the gate electrode having an upper surface, a first side and a second side, the second side opposite the first side;a first dielectric spacer laterally adjacent to the first side of the gate electrode, the first dielectric spacer having an upper surface;a second dielectric spacer laterally adjacent to the second side of the gate electrode, the second dielectric spacer having an upper surface;a first inter-layer dielectric layer laterally adjacent to the first dielectric spacer and the second dielectric spacer, the first inter-layer dielectric layer having an upper surface, wherein the upper surface of the first inter-layer dielectric layer, the upper surface of the first dielectric spacer, the upper surface of the second dielectric spacer, and the upper surface of the gate electrode are substantially co-planar with one another;an insulating cap layer on the upper surface of the gate electrode and on a portion of the upper surface of the first inter-layer dielectric layer, the insulating cap layer having an upper surface, a first side and a second side, the second side opposite the first side; anda second inter-layer dielectric layer laterally ...

REPLACEMENT METAL GATES TO ENHANCE TRANISTOR STRAIN

Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain. 114.-. (canceled)15. A method comprising:forming a PMOS transistor on a substrate, wherein the substrate further comprises an NMOS transistor disposed thereon, wherein the PMOS transistor comprises a first channel, a first gate structure disposed on the first channel, and first sidewall spacers adjacent the first gate structure;forming a compressive stressor adjacent to the first sidewall spacers;forming a tensile stressor over the compressive stressor, the first gate structure and the first sidewall spacers;removing a portion of the tensile stressor from over the first gate structure and leaving a portion of the tensile stressor on the first sidewall spacers and on the compressive stressor;forming a first trench in the first gate structure after removing the portion of the tensile stressor from the over the first gate structure;forming a first high-k gate dielectric in the first trench;forming a p-type work function material on the first high-k gate dielectric disposed in the first trench; andforming a first metal gate electrode over the p-type work function material.16. The method of claim 15 , wherein forming the first trench comprises removing a portion of the first gate structure by removing a first gate electrode and a first gate dielectric.17. The method of claim 15 , wherein the first metal gate electrode provides an additional compressive strain in the first channel.18. The method of claim 17 , wherein the first channel is further stressed via the first high-k gate dielectric.19. The method of claim 17 , wherein the first channel is further stressed via the first sidewall spacers.20. The method of claim 17 , wherein the first metal gate electrode includes a metal selected from the group consisting of ruthenium claim 17 , palladium claim 17 , platinum claim 17 , cobalt and nickel.21. The method of claim 17 , wherein the NMOS transistor ...

SELF-ALIGNED CONTACTS

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. 1. An integrated circuit structure , comprising:a substrate comprising silicon;a gate structure above the substrate, the gate structure comprising a gate dielectric and a gate electrode;a first dielectric gate spacer adjacent a first side of the gate structure;a second dielectric gate spacer adjacent a second side of the gate structure;a first source or drain region at the first side of the gate structure;a second source or drain region at the second side of the gate structure;a conductive contact structure on the first source or drain region;a first dielectric layer over a portion of the gate structure, the first dielectric layer having an opening over a portion of the conductive contact structure;a first dielectric contact spacer along a first sidewall of the opening of the first dielectric layer;a second dielectric contact spacer along a second sidewall of the opening of the first dielectric layer;a metal structure between the first dielectric contact spacer and the second dielectric contact spacer, the metal structure in contact with the portion of the conductive contact structure; anda second dielectric layer over on the first dielectric layer.2. The integrated circuit structure of claim 1 , wherein the metal structure is through and ...

UNIFORM LAYOUTS FOR SRAM AND REGISTER FILE BIT CELLS

Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction. 1. An integrated circuit structure , comprising:a substrate; first and second active regions parallel along a first direction of the substrate; and', 'first, second, third and fourth gate lines over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction., 'a six transistor (6T) static random access memory (SRAM) bit cell on the substrate, the 6T SRAM bit cell comprising2. The integrated circuit structure of claim 1 , wherein the first active region is an N-type doped active region claim 1 , and the second active region is a P-type doped active region.3. The integrated circuit structure of claim 1 , wherein the first and second active regions are in first and second silicon fins claim 1 , respectively.4. The integrated circuit structure of claim 1 , wherein all individual ones of the first claim 1 , second claim 1 , third and fourth gate lines are continuous between the first and second active regions.5. The integrated circuit structure of claim 1 , wherein the 6T SRAM bit cell has a length along the first direction and a length along the second direction claim 1 , and the first length is greater than the second length.6. The integrated circuit structure of claim 1 , wherein individual ones of the first claim 1 , second claim 1 , third and fourth gate lines are spaced apart ...

SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS

A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder. 1. A semiconductor structure , comprising:a fin comprising semiconductor material;a gate structure on top and side surfaces of part of the fin, the gate structure comprising a gate electrode and a gate dielectric, the gate electrode comprising metal, the gate dielectric comprising a first portion and a second portion, the first portion at least between the gate electrode and the part of the fin and comprising high-k dielectric material, the second portion at least between the first portion and the part of the fin and comprising oxygen, and the second portion compositionally different from the first portion;a source region laterally adjacent to and in contact with the part of the fin, the source region extending under the gate structure and also in contact with the second portion of the gate dielectric, wherein an upper surface of the source region is above a part of the gate dielectric that is between the gate electrode and the part of the fin;a drain region laterally adjacent to and in contact with the part of the fin, such that the part of the fin is at least partly laterally between the source region and the drain region, the drain region extending under the gate structure and also in contact with the second portion of ...

MULTIPLE RETICLE FIELD SEMICONDUCTOR DEVICES

Techniques are described for fabricating integrated circuit devices that span multiple reticle fields. Integrated circuits formed within separate reticle fields are placed into electrical contact with each other by overlapping reticle fields to form an overlapping conductive interconnect. This overlapping conductive interconnect electrically connects an interconnect layer of a first reticle field with an interconnect layer of a second, laterally adjacent reticle field. The overlapping conductive interconnection extends into a common scribe zone between adjacent reticle fields. 1. An integrated circuit comprising:a first device layer;a first plurality of interconnect layers over the first device layer, the interconnect layers comprising a first plurality of conductive interconnects and interlayer dielectric material;a second device layer laterally adjacent to the first device layer and separated from the first device layer by a common scribe zone;a second plurality of interconnect layers over the second device layer, the interconnect layers comprising a second plurality of conductive interconnects and interlayer dielectric material; andan overlapping conductive interconnect comprising a first portion within or on an interconnect layer of the first plurality of interconnect layers, a second portion within or on an interconnect layer of the second plurality of interconnect layers, and a third portion between the first portion and the second portion, the third portion traversing the common scribe zone.2. The integrated circuit of claim 1 , wherein the first portion claim 1 , the second portion claim 1 , and the third portion are a continuous conductive interconnect.3. The integrated circuit device of claim 1 , wherein:the first device layer and the first plurality of interconnect layers are associated with a first reticle field; andthe second device layer and the second plurality of interconnect layers are associated with a second reticle field adjacent to the first ...

HYPERCHIP

Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective. 1. An integrated circuit assembly , comprising:a first integrated circuit chip comprising a device side opposite a backside, the device side comprising a plurality of transistor devices and a plurality of device side contact points, and the backside comprising a plurality of backside contacts; anda second integrated circuit chip comprising a device side comprising a plurality of device contact points thereon, the second integrated circuit chip on the first integrated circuit chip in a device side to device side configuration, wherein ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip, and wherein the second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.2. The integrated circuit assembly of claim 1 , further comprising:one or more additional integrated circuit chips, each of the one or more additional integrated circuit chips comprising a device side comprising a plurality of device contact points ...

SELF-ALIGNED CONTACTS

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. 1. A transistor comprising:a substrate;a pair of spacers on the substrate;a conformal high-k gate dielectric layer on a surface of the substrate and along sidewalls of the pair of spacers;a conformal gate electrode layer that is: (a) on the portion of the conformal high-k gate dielectric layer that is on the surface of the substrate and (b) along portions of the conformal high-k gate dielectric layer that are along sidewalls of the pair of spacers;a fill metal layer on the conformal gate electrode layer;a cap layer between the pair of spacers and in physical contact with all three of the conformal high-k gate dielectric layer, the conformal gate electrode layer, and the fill metal layer; anda pair of diffusion regions adjacent to the pair of spacers.2. The transistor of claim 1 , wherein the conformal gate electrode layer comprises a metal selected from the group consisting of hafnium claim 1 , tantalum claim 1 , titanium claim 1 , and nickel.3. The transistor of claim 1 , further comprising:a conductive contact disposed on one of the pair of diffusion regions and on a portion of the cap layer.4. The transistor of claim 1 , further comprising:a conductive contact disposed on one of the pair of diffusion regions and directly adjacent to one of ...

Distributed semiconductor die and package architecture

The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

SELF-ALIGNED CONTACTS

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. 1. A nonplanar transistor comprising:a body;a pair of spacers on the body;a gate dielectric layer on a surface of the body between the pair of spacers and along sidewalls of the pair of spacers;a gate electrode on the gate dielectric layer and between the pair of spacers, wherein the gate electrode is separated from the pair of spacers by portions of the gate dielectric layer along the sidewalls of the pair of spacers;an insulating cap layer on the gate electrode between the pair of spacers and directly on the portions of the gate dielectric layer along the sidewalls of the pair of spacers; anda pair of diffusion regions adjacent to the pair of spacers.2. The nonplanar transistor of claim 1 , wherein the gate electrode includes:a gate electrode layer that is (a) on a portion of the gate dielectric layer that is on the surface of the body between the pair of spacers and (b) along portions of the gate dielectric layer that are along sidewalls of the pair of spacers; anda fill metal layer on the gate electrode layer.3. The nonplanar transistor of claim 2 , wherein the gate electrode layer is a conformal layer claim 2 , or the gate dielectric layer is a conformal layer claim 2 , or both the gate electrode layer and the gate dielectric layer are ...

REPLACEMENT METAL GATES TO ENHANCE TRANSISTOR STRAIN

Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain. 1. A method comprising:forming an NMOS transistor on a substrate, wherein the substrate further comprises a PMOS transistor disposed thereon, wherein the NMOS transistor comprises first channel, a first gate structure disposed on the first channel, and first sidewall spacers adjacent the first gate structure;forming a first trench in the first gate structure;forming a first high-k gate dielectric in the first trench;forming an n-type work function material on the first high-k gate dielectric disposed in the first trench; andforming a first metal gate electrode over the n-type work function material.2. The method of claim 1 , further comprising wherein a stressor is formed over the first gate structure claim 1 , wherein the stressor comprises a tensile layer over the first gate structure.3. The method of claim 1 , wherein forming the first trench comprises removing portion of the first gate structure by removing a first gate electrode and a first gate dielectric claim 1 , and wherein removing a portion of the first gate structure increases a tensile strain on the first channel.4. The method of claim 1 , further comprising: wherein the first metal gate electrode provides an additional tensile strain in the first channel.5. The method of claim 4 , wherein the first channel is stressed via the first high-k gate dielectric.6. The method of claim 4 , wherein the first channel is stressed via the first sidewall spacers.7. The method of claim 4 , wherein the first metal gate electrode includes at least one of tungsten or titanium carbide.8. The method of claim 4 , further comprising:wherein the PMOS transistor comprises a second gate structure disposed on a second channel, a second stressor disposed on the second gate structure, and second sidewall spacers adjacent the second gate structure;forming a second trench in the second gate structure;forming a ...

MULTI VERSION LIBRARY CELL HANDLING AND INTEGRATED CIRCUIT STRUCTURES FABRICATED THEREFROM

Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch. 1. A method of fabricating a layout for an integrated circuit structure , the method comprising:designating alternating ones of a plurality of gate lines parallel along a first direction as even (E) or odd (O) along a second direction;selecting a location for a cell type over the plurality of gate lines;selecting between a first version of the cell type and a second version of the cell type depending on the location, the second version structurally different than the first version, wherein the selected version of the cell type has an even (E) or odd (O) designation for interconnects at edges of the cell type along the second direction, and wherein the designation of the edges of the cell type match with the designation of individual ones of the plurality of gate lines below the interconnects.2. The method of claim 1 , wherein the interconnects have a pitch along the second direction less than a pitch of the gate lines along the second direction.3. The method of claim 1 , wherein individual ones of the interconnects of the first version of the cell type align with individual ones of the plurality of gate lines along the first direction at both edges of the first version of the cell type along the second direction.4. The method of claim 3 , wherein individual ones of the interconnects of the second version of the cell type do not align with individual ones of the plurality of gate lines along the ...

3D INTEGRATED CIRCUIT PACKAGE WITH WINDOW INTERPOSER

3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die. 1. A semiconductor package , comprising:a substrate;a top semiconductor die disposed above the substrate;an interposer having a window, the interposer disposed between and interconnected to the substrate and the top semiconductor die; anda bottom semiconductor die disposed in the window of the interposer, and interconnected to the top semiconductor die.2. The semiconductor package of claim 1 , wherein the bottom semiconductor die comprises no through silicon vias (TSVs) and is not interconnected directly to the substrate.3. The semiconductor package of claim 1 , wherein an active side of the bottom semiconductor die faces an active side of the top semiconductor die claim 1 , and away from the substrate.4. The semiconductor package of claim 1 , wherein the bottom semiconductor die comprises through silicon vias (TSVs) and is interconnected directly to the substrate.5. The semiconductor package of claim 1 , wherein an active side of the bottom semiconductor die faces away from an active side of the top semiconductor die claim 1 , and toward the substrate.6. The semiconductor package of claim 1 , wherein the bottom semiconductor die is disposed in a closed window of ...

High speed, high efficiency, high power rf pulse modulating integrated switch

Embodiments of a drain modulator that uses high power switch sensing to control active pulldown are generally described herein. In some embodiments, a logic and sense module is arranged to receive a control signal for controlling an on and an off state of an input of a switch to turn a high power voltage at an output of the switch on and off. A pullup module and a pulldown module are coupled to the input of the switch. An active pulldown module coupled to the output of the switch. The logic and sense module monitors the input to the switch and activates the active pulldown module to drain the output of the switch to a zero voltage when the input of the switch transitions to the off state.

VIA BLOCKING LAYER

An embodiment includes an apparatus comprising: a metal layer comprising a plurality of interconnect lines on a plurality of vias; an additional metal layer comprising first, second, and third interconnect lines on first, second, and third vias; the first and third vias coupling the first and third interconnect lines to two of the plurality of interconnect lines; a lateral interconnect, included entirely within the additional metal layer, directly connected to each of the first, second, and third interconnect lines; and an insulator layer included entirely between two sidewalls of the second via. Other embodiments are described herein. 1. An apparatus comprising:a metal layer comprising a plurality of interconnect lines that are on a plurality of vias;an additional metal layer comprising first, second, and third interconnect lines that are on first, second, and third vias; the first and third vias coupling the first and third interconnect lines to two of the plurality of interconnect lines;a lateral interconnect, included within the additional metal layer, directly connected to each of the first, second, and third interconnect lines; andan insulator layer included between two sidewalls of the second via.2. The apparatus of wherein the insulator layer includes a metal and at least one of an oxide and a nitride.4. The apparatus of wherein the lateral interconnect includes metal fill and the first claim 3 , second claim 3 , and third interconnect lines respectively include first claim 3 , second claim 3 , and third metal fill that are all monolithic with the metal fill.5. An apparatus comprising:a metal layer comprising a plurality of metal interconnect lines respectively on a plurality of vias;an additional metal layer comprising first, second, and third metal interconnect lines respectively on first, second, and third vias; the first and third vias respectively coupling the first and third metal interconnect lines to two of the plurality of metal interconnect lines;a ...

SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS

A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder. 1. A semiconductor device , comprising:a gate stack disposed on a substrate, wherein the gate stack is comprised of a metal gate electrode above a channel region in the substrate, and a high-k gate dielectric layer between the metal gate electrode and the channel region and along sidewalls of the metal gate electrode;a pair of source drain regions in the substrate on either side of the channel region, wherein a lattice constant of the pair of source drain regions is different than a lattice constant of the channel region, and wherein the pair of source drain regions is under the high-k gate dielectric layer and under a portion of the metal gate electrode;a shallow trench isolation structure laterally adjacent to one of the pair of source/drain regions; andan inter-layer dielectric layer directly laterally adjacent to and in contact with a portion of the high-k gate dielectric layer along the sidewalls of the metal gate electrode, the inter-layer dielectric layer over the one of the pair of source/drain regions and over the shallow trench isolation structure.2. The semiconductor device of claim 1 , wherein the pair of source/drain regions have an undercut profile of approximately 55 degrees with respect to a horizontal axis. ...

Self-aligned contacts

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Active silicon bridge

A package substrate and a package assembly including a package substrate including a substrate body including a plurality of first contact points on a surface thereof configured for electrical connection to a first die and a plurality of second contact points on the surface configured for electrical connection to a second die; and a bridge coupled to the substrate body, the bridge including active device circuitry that is coupled to ones of the plurality of first contact points and ones of the plurality of second contact points. A method of forming a package assembly including coupling a first die to a package substrate, the package substrate including a bridge substrate including active device circuitry; and coupling a second die to the package substrate, wherein coupling the first die and the second die to the package substrate includes coupling the first die and the second die to the active circuitry.

TECHNIQUES FOR DIE STACKING AND ASSOCIATED CONFIGURATIONS

Embodiments of the present disclosure describe techniques for fabricating a stacked integrated circuit (IC) device. A first wafer that includes a plurality of first IC dies may be sorted to identify first known good dies of the plurality of first IC dies. The first wafer may be diced to singulate the first IC dies. A second wafer that includes a plurality of second IC dies may be sorted to identify second know good dies of the plurality of second IC dies. The first known good dies may be bonded to respective second known good dies of the second wafer. In some embodiments, the first known good dies may be thinned after bonding the first know good dies to the second wafer. Other embodiments may be described and/or claimed. 1. A method for fabricating a stacked integrated circuit (IC) device , the method comprising:sorting a first wafer that includes a plurality of first IC dies to identify first known good dies of the plurality of first IC dies;dicing the first wafer to singulate the first IC dies;sorting a second wafer that includes a plurality of second IC dies to identify second known good dies of the plurality of second IC dies; andbonding the first known good dies to respective second known good dies of the second wafer.2. The method of claim 1 , further comprising:arranging the first known good dies on a carrier wafer in locations that correspond to locations of the second known good dies on the second wafer;wherein the bonding includes bonding the first known good dies arranged on the carrier wafer to the respective second known good dies and removing the carrier wafer.3. The method of claim 1 , further comprising claim 1 , after the bonding claim 1 , thinning the first known good dies while the first known good dies are bonded to the second wafer.4. The method of claim 3 , further comprising claim 3 , prior to the thinning claim 3 , forming a dielectric on the second wafer between the first known good dies.5. The method of claim 3 , wherein the thinning ...

VIA BLOCKING LAYER

Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided. 1. An integrated circuit comprising:a first layer including one or more dielectric materials, the first layer including a first trench and a second trench, wherein metal material is below the first trench and metal material is below the second trench;a first structure in the first trench, the first structure including one or more metal materials;a second structure in the second trench, the second structure including one or more metal materials; anda second layer between the first structure and the metal material below the first trench, wherein the second layer includes one or more dielectric materials.2. The integrated circuit of claim 1 , wherein the second layer is absent between the second structure and the metal material below the second trench.3. The integrated circuit of claim 1 , wherein the second layer is absent between the first structure and the first layer.4. The integrated circuit of claim 1 , wherein the first trench has a lower portion and an ...

DIE PACKAGE ARCHITECTURE WITH EMBEDDED DIE AND SIMPLIFIED REDISTRIBUTION LAYER

A die package architecture with an embedded die and simplified redistribution layer is described. In one example a method includes attaching a front side of a die to a temporary carrier panel applying a molding compound around the die and over the temporary carrier panel. Removing the temporary carrier, applying a metal routing layer over the front side of the die and the molding compound, and applying a connection array to the metal routing layer. 1. A method comprising:attaching a front side of a die to a temporary carrier panel;applying a molding compound around the die and over the temporary carrier panel;removing the temporary carrier;applying a metal routing layer over the front side of the die and the molding compound; andapplying a connection array to the metal routing layer.2. The method of claim 1 , wherein applying the molding compound comprises applying the molding compound over the die.3. The method of claim 1 , wherein applying a metal routing layer comprises applying the metal routing layer over a bump-less connection array of the die.4. The method of claim 1 , wherein the hump-less connection array comprises a plurality of lands over an M9 metal layer of the die.5. The method of claim 1 , wherein applying a connection array comprises applying a solder ball grid array.6. The method of claim 1 , wherein applying a solder ball grid array comprises depositing a patterned solder resist directly over the metal layer to expose a portion of the metal layer and depositing solder over exposed portion of the metal layer.7. The method of claim 1 , further comprising attaching a second die to a back side of the die after attaching the die to the temporary carrier and before applying a molding compound.8. The method of claim 1 , further comprising applying a dielectric layer over at least a portion of the top side of the die before attaching the front side to the temporary carrier.9. The method of claim 8 , wherein the dielectric layer is a passivation layer.10. ...

STRAND TRIMMER

A strand trimmer and method of use thereof. The strand trimmer includes a pair of pivotable arms each having a motor, a follower wheel, and a cutter-spindle assembly disposed thereon. The arms are biased toward one another and are guided by the follower wheels to pivot around obstacles passing between the arms. The motor rotates the cutter-spindle assembly to move cutting strands extending therefrom through a cutting path with sufficient rotational velocity to cut vegetation. The cutter-spindle assembly includes a reloadable spool and a strand-feed mechanism. The strand-feed mechanism includes a solenoid actuated plunger within a shaft of the cutter-spindle assembly which operates to non-contactingly actuate the plunger to feed out a length of strand. The solenoid is non-rotatably carried on the trimmer arm while the shaft of the cutter-spindle assembly is encircled by and rotated within the solenoid. 1. A strand trimmer comprising:a spindle collar mountable to a trimmer arm; a shaft aligned coaxially with the axis, the shaft including a bore aligned coaxially with the axis and extending along at least a portion of the length of the shaft,', 'a plunger disposed within the bore in the shaft and being moveable axially within the bore,', 'a strand canister coupled to the shaft, an interior of the strand canister being in communication with the bore in the shaft, and', 'a spool disposed in the strand canister and including a length of a strand wound thereon; and, 'a cutter-spindle assembly rotatably mounted to the spindle collar to be rotatable about an axis, the cutter-spindle assembly including'}a solenoid disposed on the spindle collar in proximity to the plunger and operable to non-contactingly move the plunger axially within the bore to feed out the strand from the spool, the shaft being rotated within the solenoid while the solenoid and the spindle collar remain non-rotatably fixed.2. The strand trimmer of claim 1 , wherein the solenoid is operable to move the ...

Replacement of Virtual Functions

Techniques are described for replacement of virtual functions. In one or more implementations, a call to a virtual function is intercepted and redirected to a shim module associated with a replacement function. The shim module is configured to adjust a pointer (e.g., a “this” pointer) for the virtual function. In at least some embodiments, the pointer can be adjusted based on information retrieved from symbol data for the virtual function. The replacement function can utilize the adjusted pointer to access an object instance associated with the virtual function. For example, the replacement function can use the adjusted pointer to access data and/or functionalities of the object instance.

HYPERCHIP

Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective. 1. An integrated circuit assembly , comprising:a first integrated circuit chip comprising a device side opposite a backside, the device side comprising a plurality of transistor devices, a plurality of metal layers over the plurality of transistor devices, and a plurality of device contact points above the plurality of metal layers, the plurality of metal layers comprising a topmost metal layer and a bottommost metal layer, and the backside comprising a plurality of backside contacts, the first integrated circuit chip comprising one or more through silicon vias (TSVs), the TSVs extending from the backside contacts to a location between the bottommost metal layer and the topmost metal layer, and the first integrated circuit chip having a footprint; anda second integrated circuit chip comprising a device side comprising a plurality of device contact points thereon, the second integrated circuit chip on the first integrated circuit chip in a device side to device side configuration, wherein ones of the plurality of device contact points of the second integrated circuit chip are coupled to ...

THROUGH GATE FIN ISOLATION

Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes. 1. An integrated circuit structure , comprising:a fin comprising silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a first direction;an isolation structure separating a first portion of the fin from a second portion of the fin along the first direction, the isolation structure having a width along the first direction;a first gate structure comprising a first gate electrode over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin, and the first gate structure further comprising a first high-k dielectric layer between the first gate electrode and the first portion of the fin and along sidewalls of the first gate electrode, wherein the first gate structure has the width along the first direction, and wherein a center of the first gate structure is spaced apart from a center of the isolation structure by a pitch along the first direction;a second gate structure comprising a second gate electrode over the top of and laterally adjacent to the sidewalls of a first region of the second portion of the fin, and the second gate structure further comprising a second high-k dielectric layer between the second gate electrode and the second portion of the fin and along sidewalls of the second ...

FUNCTIONALLY REDUNDANT SEMICONDUCTOR DIES AND PACKAGE

Systems and methods of providing redundant functionality in a semiconductor die and package are provided. A three-dimensional electrical mesh network conductively couples smaller semiconductor dies, each including circuitry to provide a first functionality, to a larger base die that includes circuitry to provide a redundant first functionality to the semiconductor die circuitry. The semiconductor die circuitry and the base die circuitry selectively conductively couple to a common conductive structure such that either the semiconductor die circuitry or the base die circuitry is able to provide the first functionality at the conductive structure. Driver circuitry may autonomously or manually, reversibly or irreversibly, cause the semiconductor die circuitry and the base die circuitry couple to the conductive structure. The redundant first functionality circuitry improves the operational flexibility and reliability of the semiconductor die and package. 1. A semiconductor package , comprising: a first plurality of conductors;', 'a second plurality of conductors, each of the second plurality of conductors intersecting at least one of the first plurality of conductors to form a plurality of nodes, each of the plurality of nodes at a respective intersection of one of the first plurality of conductors with one of the second plurality of conductors;, 'an electrical mesh network that includesa base die having an upper surface and a lower surface, the base die including circuitry providing a first functionality conductively coupled to at least one of the plurality of nodes;a plurality of semiconductor dies, at least one of the plurality of semiconductor dies including circuitry providing the first functionality; each of the plurality of semiconductor dies conductively coupled to a respective one of the plurality of nodes; anddriver circuitry to selectively conductively couple the electrical mesh network to at least one of the first semiconductor die circuitry providing the ...

USE OF MANZAMINES AS ANTIPROLIFERATIVE AGENT

Described herein are methods and systems for using an alkaloid, such as manzamine A, for anti-proliferative effects at relatively low and non-cytotoxic concentrations (up to 4 μM) wherein manzamine A blocks cell cycle progression in cervical cancer cell lines and regulates cell cycle-related genes, including restoration of p21 and p53 expression inducing apoptosis. 1. A method for suppressing proliferation of cancer cells comprising:administering a therapeutically effective amount of at least one alkaloid;wherein the alkaloid binds with at least one kinase involved with oncogenesis; andwherein the bound alkaloid and kinase regulate at least one oncoprotein associated with a cancer.2. The method of claim 1 , wherein the alkaloid is a manzamine analog.3. The method of claim 2 , wherein the manzamine analog is manzamine A.4. The method of claim 1 , wherein the kinase is Casein Kinase 2.5. The method of claim 1 , wherein the oncoprotein has a protein sequence of SEQ. 1.6. The method of claim 1 , wherein the alkaloid is noncytotoxic in concentrations up to 4 μM.7. The method of claim 1 , wherein the cancer includes cervical claim 1 , colon claim 1 , pancreatic claim 1 , prostrate claim 1 , and breast cancer.8. The method of claim 1 , wherein the alkaloid is naturally occurring.9. The method of claim 1 , wherein administering the alkaloid restores expression of proteins inducing cell apoptosis.10. The method of claim 1 , wherein the at least one alkaloid is administered in a dose concentration ranging from 1 μM to 4 μM.11. A system for suppressing proliferation of cancer cells comprising:administering a pharmaceutically acceptable carrier containing an affective amount of at least one an alkaloid;wherein the alkaloid binds with at least one kinase involved with oncogenesis; andwherein the bound alkaloid and kinase regulate at least one oncoprotein associated with a cancer.12. The system of claim 11 , wherein the alkaloid is a manzamine analog.13. The system of claim 12 , ...

Metal on both sides with power distributed through the silicon

An apparatus including a circuit structure including a device stratum; and a contact coupled to a supply line and routed through the device stratum and coupled to at least one device on a first side. A method including providing a supply from a package substrate to at least one transistor in a device stratum of a circuit structure; and distributing the supply to the at least one transistor using a supply line on an underside of the device stratum and contacting the at least one transistor on a device side by routing a contact from the supply line through the device stratum. A system including a package substrate, and a die including at least one supply line disposed on an underside of a device stratum and routed through the device stratum and coupled to at least one of a plurality of transistor devices on the device side.

DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTURE

The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network. 1. A semiconductor package , comprising: a first plurality of conductors;', 'a second plurality of conductors, each of the second plurality of conductors intersecting at least one of the first plurality of conductors, forming a plurality of network nodes, each of the network nodes at an intersection of one of the first plurality of conductors with one of the second plurality of conductors;, 'an electrical mesh network that includesa base die including I/O circuitry conductively coupled to at least one of the plurality of nodes; anda plurality of cores that each have an upper surface and a transversely opposed lower surface and include processor core circuitry, wherein each core is conductively coupled to a respective one of the plurality of nodes, and wherein each of at least one of the cores includes at least one transistor disposed proximate the lower surface of the respective core.2. The semiconductor package of :wherein the base die includes an upper surface and a transversely opposed lower surface;wherein the first plurality of conductors ...

Heat pipes having wick structures with variable permeability

A heat pipe is provided having a hollow body defining an interior vapor space, evaporator and condenser regions, a wick structure lining an inner wall of the hollow body, and a working fluid disposed in the hollow body, wherein a path for the working fluid in liquid state extends from the condenser region toward the evaporator region or wherein the wick structure extends along a direction from a first end of the hollow body toward the second end, and wherein the wick structure includes first and second regions that extend along the path or direction and that each have wick particles defining respective pore sizes that are different from one another.

REPLACEMENT METAL GATES TO ENHANCE TRANSISTOR STRAIN

Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain. 1. A semiconductor structure , comprising:an NMOS transistor and a PMOS transistor above a silicon substrate;a first gate stack for the PMOS transistor, the first gate stack comprising a workfunction metal layer;a second gate stack for the NMOS transistor, the second gate stack comprising a layer comprising titanium and aluminum, wherein the workfunction metal layer of the first gate stack is not included in the second gate stack, and wherein the layer comprising titanium and aluminum is over the workfunction metal layer in the first gate stack;a source region and a drain region for the NMOS transistor;a raised source region and a raised drain region for the PMOS transistor, the raised source and drain regions comprising a silicon germanium layer creating a stressed channel for the PMOS device, and the raised source and drain regions extending above a surface of the silicon substrate over which the first gate stack is formed; anda nitride layer over the silicon germanium layer and co-planar with an uppermost surface of the first gate stack.2. The semiconductor structure of claim 1 , wherein the first and second gate stacks comprise a same fill metal.3. The semiconductor structure of claim 1 , wherein the first and second gate stacks comprise a first and second gate dielectric layer claim 1 , respectively.4. The semiconductor structure of claim 3 , wherein the first and second gate dielectric layers comprise U-shaped gate dielectric layers.5. The semiconductor structure of claim 3 , wherein the first and second gate dielectric layers comprise hafnium oxide.6. The semiconductor structure of claim 1 , further comprising a silicide layer on the silicon germanium layer.7. A method of fabricating a semiconductor structure claim 1 , the method comprising:forming a first sacrificial gate stack for a PMOS transistor above a silicon substrate;forming a second ...

SELF-ALIGNED CONTACTS

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. 1. A transistor comprising:a substrate;a pair of spacers on the substrate;a gate dielectric layer on a surface of the substrate between the pair of spacers;a gate electrode on the gate dielectric layer and between the pair of spacers;an insulating cap layer between the pair of spacers and on the gate electrode;a pair of diffusion regions adjacent to the pair of spacers;an interlayer dielectric layer on said pair of diffusion regions;a contact opening in said interlayer dielectric layer, said contact opening exposing one of said pair of diffusion regions, one of said pair of spacers and a portion of said insulating cap layer;contact sidewall spacers formed along sidewalls of said contact opening and on said portion of said insulating cap layer; anda conductive material formed in the contact opening, adjacent to said contact sidewall spacers.2. The transistor of claim 1 , wherein the gate dielectric layer is a U-shaped high-k gate dielectric layer.3. The transistor of claim 1 , wherein the gate electrode is a metal gate electrode.4. The transistor of claim 3 , wherein the metal gate electrode comprises a work function metal layer and a fill metal layer.5. The transistor of claim 4 , wherein a top surface of the fill metal layer is above a top ...

SELF-ALIGNED CONTACTS

A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations. 1. (canceled)2. A transistor comprising:a substrate;a pair of spacers on the substrate;a gate dielectric layer on a surface of the substrate between the pair of spacers;a gate electrode on the gate dielectric layer and between the pair of spacers;a pair of diffusion regions adjacent to the pair of spacers;a silicide layer on the pair of diffusion regions, the silicide layer having a top surface;a first interlayer dielectric layer on the pair of diffusion regions;a second interlayer dielectric layer on the first interlayer dielectric layer, the second interlayer dielectric layer having a top surface;a contact opening in the first interlayer dielectric layer and the second interlayer dielectric layer, the contact opening exposing the top surface of the silicide layer;contact sidewall spacers formed along sidewalls of the first interlayer dielectric layer and the second interlayer dielectric layer exposed by the contact opening, the contact sidewall spacers on the top surface of the silicide layer, and the contact sidewall spacers having a top surface co-planar with a top surface of the second interlayer dielectric layer; anda conductive material formed in the contact opening, adjacent to the contact sidewall spacers and on the top surface of ...

System and methods for data evaluation through network sensitivity analysis

A method for evaluating a relative contribution of a first group of J data sets in a collection of N data sets, wherein N>J, includes first applying the collection of N data sets and second applying the first group of J data sets to a model and generating one or more observations O on the collection of N data sets and the first group of J data sets, including generating a N NSA curve comprising computing, using the model, an observation O N on the collection of N data sets; and generating a N−J NSA curve for the first group of J data sets by removing the first group of J data sets from the collection of N data sets, and generating, using the model, an observation O N−J with the first group of J data sets removed. The method then includes generating a measure M J of contributions of the group of J data sets based on the N NSA curve and the N−J NSA curves.

INTEGRATED CIRCUIT DEVICE WITH BACK-SIDE INERCONNECTION TO DEEP SOURCE/DRAIN SEMICONDUCTOR

Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor. 120-. (canceled)21. A transistor structure , comprising:a semiconductor body extending through an isolation dielectric;a gate electrode over a channel region of the semiconductor body and extending over a front side of the isolation dielectric;source and drain regions comprising semiconductor material electrically coupled to the channel region, wherein the source and drain regions include at least one deep source or deep drain region extending to a depth below that of the channel region;one or more front-side interconnect metallization levels over the front side of the isolation dielectric, and coupled to at least one of the source and drain regions, or to the gate electrode; andone or more back-side interconnect metallization levels over a back side of the isolation dielectric and electrically coupled to the deep source or deep drain region.22. The transistor structure of claim 21 , wherein:the source and drain regions include a shallow source or shallow drain region extending to a depth less than that of the deep source or deep drain region; andthe front-side interconnect metallization levels are coupled to the shallow source or shallow drain region, and to the gate electrode.23. The transistor structure of claim 22 , wherein the shallow source or shallow drain region ...

Cable Retainers for Packaging

Cable retainers for cables are disclosed. The cable retainers may include a panel having a pair of loop locks. The loop locks may engage each other to form a loop. The cable retainer may include a first and a second retention loop. Each retention loop may have a finger with a slot formed at a fold line of the finger. Each retention loop may also have a flap with a tab formed at a fold line of the flap. The finger and the flap of the first retention loop may be located directly across the panel from one another. The finger of the second retention loop may be located at a first end of the panel while the flap of the second retention loop may be located at a second end of the panel. The tabs and slots of each retention loop may interlock to form a rectangular cable passage. The cable may also include a reinforcement structure disposed in a retention loop. The reinforcement structure may be stepped reinforcement structure. The cable retainer may be formed entirely of paper and may be formed without and adhesive.

METAL ON BOTH SIDES WITH POWER DISTRIBUTED THROUGH THE SILICON

An apparatus including a circuit structure including a device stratum; and a contact coupled to a supply line and routed through the device stratum and coupled to at least one device on a first side. A method including providing a supply from a package substrate to at least one transistor in a device stratum of a circuit structure; and distributing the supply to the at least one transistor using a supply line on an underside of the device stratum and contacting the at least one transistor on a device side by routing a contact from the supply line through the device stratum. A system including a package substrate, and a die including at least one supply line disposed on an underside of a device stratum and routed through the device stratum and coupled to at least one of a plurality of transistor devices on the device side. 1a circuit structure comprising a device stratum comprising a plurality of transistor devices each comprising a first side and an opposite second side;a supply line disposed on the second side of the device stratum; anda contact coupled to the supply line and routed through the device stratum and coupled to at least one of the plurality of transistor devices on the first side.. An apparatus comprising: This patent application is a continuation of U.S. patent application Ser. No. 15/747,988, filed Jan. 26, 2018, which is a U.S. National Phase Application under 35 U.S.C. § 371 of International Application No. PCT/US2015/052445, filed Sep. 25, 2015, entitled “METAL ON BOTH SIDES WITH POWER DISTRIBUTED THROUGH THE SILICON,” which designates the United States of America, the entire disclosure of which are hereby incorporated by reference in their entirety and for all purposes.Semiconductor devices including devices including electrical connections from a backside of the device.For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller ...

POWER SHARED CELL ARCHITECTURE

An integrated circuit structure includes a metal level comprising a plurality of interconnect lines along a first direction. A cell is on the metal level, wherein one or more of the plurality of interconnect lines that extend through the cell comprise a power shared track that is segmented inside the cell into one or more power segments and one or more signal segments so that both power and signals share a same track.

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SOURCE OR DRAIN STRUCTURES WITH EPITAXIAL NUBS

Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs, are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures includes vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures includes vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires. A conductive contact structure is laterally between and in contact with the one of the first pair of epitaxial source or drain structures and the one of the second pair of epitaxial source or drain structures. 1. An integrated circuit structure , comprising:a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires;a first gate stack around the first vertical arrangement of horizontal nanowires, and a second gate stack around the second vertical arrangement of horizontal nanowires;a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires, the first pair of epitaxial source or drain structures comprising vertically discrete portions aligned with the first vertical arrangement of horizontal nanowires;a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires, the second pair of epitaxial source or drain structures comprising vertically discrete portions aligned with the second vertical arrangement of horizontal nanowires, wherein one of the first pair of epitaxial source or drain structures is laterally adjacent to but not merged with one of the ...

3D INTEGRATED CIRCUIT PACKAGE WITH WINDOW INTERPOSER

3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die.

INTEGRATED CIRCUIT DEVICE WITH CRENELLATED METAL TRACE LAYOUT

Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces. 123-. (canceled)24. The IC An integrated circuit (IC) structure , comprising:a trace layout include a plurality of traces extending in a direction, wherein individual ones of the plurality of traces intersect only one boundary of the structure; andadjacent ones of the plurality of traces are staggered to intersect boundaries on opposite sides of the structure.25. The IC structure of claim 24 , wherein individual ones of the plurality traces are within a first interconnect level claim 24 , and have an end that is laterally offset from that of an adjacent trace by at least a width of an orthogonal trace within a second interconnect level.26. The IC structure of claim 25 , wherein the end of individual ones of the plurality of traces is laterally offset from that of an adjacent trace by approximately the width of an orthogonal trace in the second interconnect level summed with half the distance separating the orthogonal trace from an adjacent trace in the second interconnect level.27. The IC structure of claim 25 , further comprising a conductive via coupling the orthogonal trace to at least one of the plurality of traces.28. The IC ...

DISTRIBUTED SEMICONDUCTOR DIE AND PACKAGE ARCHITECTURE

The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network. 1. A method , comprising:forming a first plurality of conductors on an upper surface of a base die; each of the first plurality of conductors disposed on a first surface and spaced apart from the remaining first plurality of conductors;', 'each of the second plurality of conductors spaced apart from the remaining second plurality of conductors; and', 'each of the first plurality of conductors intersects and conductively couples to at least one of the second plurality of conductors to form an electrical mesh network, the electrical mesh network conductively coupled to circuitry included in the base die;, 'forming a second plurality of conductors on the upper surface of the base die, whereinconductively coupling each of a plurality of cores to a node formed by an intersection of one of the first plurality of conductors with one of the second plurality of conductors.2. The method of wherein forming a second plurality of conductors on the upper surface of the base die further comprises:forming the second plurality of conductors on the upper surface ...

VIA BLOCKING LAYER

Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided. 1. An integrated circuit device , comprising:an interlayer dielectric (ILD) layer having a plurality of trenches formed therein, each trench having sidewalls and a bottom defined by a lower metal;an insulator layer on the bottom of a middle trench included in the plurality, the insulator layer covering the lower metal defining the bottom of the middle trench; anda fill metal in each of the trenches, the fill metal in electrical contact with the lower metal defining the bottom of each trench, except that the lower metal defining the bottom of the middle trench is isolated from the fill metal by the insulator layer.2. The device of wherein the plurality of trenches includes three trenches claim 1 , including a left trench claim 1 , the middle trench claim 1 , and a right trench claim 1 , the device further comprising a lateral interconnect that electrically connects the fill metal of the left claim 1 , middle claim 1 , and right trenches.3. The device of wherein ...

SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS

A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder. 1. A semiconductor structure , comprising:a gate electrode over a crystalline silicon substrate, the gate electrode comprising a metal;a channel region in the crystalline silicon substrate, the channel region beneath the gate electrode;a gate dielectric comprising an upper hafnium oxide portion between the gate electrode and the channel region and along sidewalls of the gate electrode, and comprising a lower silicon dioxide portion between the upper hafnium oxide portion and the channel region;an epitaxial silicon germanium source region in a first recess of the crystalline silicon substrate at a first side of the gate electrode, the epitaxial silicon germanium source region having an undercut profile of approximately 55 degrees with respect to an uppermost surface of the crystalline silicon substrate, a portion of the epitaxial silicon germanium source region in contact with a first portion of a bottommost surface of the lower silicon dioxide portion of the gate dielectric;an epitaxial silicon germanium drain region in a second recess of the crystalline silicon substrate at a second side of the gate electrode opposite the first side of the gate electrode, the epitaxial silicon germanium drain region having an undercut ...

SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS

A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder. 2. The semiconductor structure of claim 1 , wherein the trench isolation structure is a first trench isolation structure to the side of the source region claim 1 , and wherein the semiconductor structure comprises:a second trench isolation structure to one side of the drain region, wherein a sidewall of the second trench isolation structure is at an acute angle with respect to, and in contact with, the drain region.3. The semiconductor structure of claim 1 , wherein at least one of the source region or the drain region has an undercut profile of approximately 55 degrees with respect to a horizontal axes.4. The semiconductor structure of claim 1 , further comprising:a substrate, wherein the body is part of the substrate, and wherein at least one of the source region or the drain region has an undercut profile of approximately 55 degrees with respect to an uppermost surface of the substrate.5. The semiconductor structure of claim 1 , wherein the first dielectric material comprises a high-k dielectric material.6. The semiconductor structure of claim 1 , wherein the first dielectric material comprises one or more of hafnium claim 1 , oxygen claim 1 , nitrogen claim 1 , silicon claim 1 , lanthanum claim 1 , zirconium claim 1 , ...

3D INTERCONNECT STRUCTURE COMPRISING THROUGH-SILICON VIAS COMBINED WITH FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES FABRICATED USING A DUAL DAMASCENE TYPE APPROACH

A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow. 1. A 3D interconnect structure comprising:a semiconductor substrate having a front surface and a back surface;a dual damascene via extending through the semiconductor substrate between the front and back surfaces;a redistribution layer (RDL) formed over the back surface of the substrate and electrically coupled to the via, wherein a portion of the RDL is over the via and a portion of the RDL is not over the via; anda passivation layer formed over the RDL, wherein the passivation layer has an opening exposing a portion of the portion of the RDL not over the via, but not exposing the portion of the RDL over the via.2. The 3D interconnect structure of claim 1 , wherein the passivation layer comprises silicon nitride.3. The 3D interconnect structure of claim 1 , wherein the dual damascene via and RDL further comprises an insulating liner layer formed on side surfaces of a dual damascene via and trench opening claim 1 , and not formed on bottom surfaces of the dual damascene via and trench opening.4. The 3D interconnect structure of claim 3 , wherein the dual damascene via and RDL further comprise a continuous barrier layer formed on the bottom surfaces of the dual damascene via and trench opening claim 3 , and on the insulating liner layer formed on the side surfaces of the dual damascene via and trench opening.5. The 3D interconnect structure of claim 1 , further comprising:an landing pad formed in the opening of the passivation layer; anda conductive bump formed on the landing pad.6. The 3D interconnect structure of claim 1 , wherein the RDL is formed in a trench opening ...

MULTI VERSION LIBRARY CELL HANDLING AND INTEGRATED CIRCUIT STRUCTURES FABRICATED THEREFROM

Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch. 1. An integrated circuit structure , comprising:a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction;a first version of a cell type over a first portion of the plurality of gate lines, the first version of the cell type comprising a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch; anda second version of the cell type over a second portion of the plurality of gate lines laterally adjacent to the first version of the cell type along the second direction, the second version of the cell type comprising a second plurality of interconnect lines having the second pitch along the second direction, and the second version of the cell type structurally different than the first version of the cell type.2. The integrated circuit structure of claim 1 , wherein individual ones of the first plurality of interconnect lines of the first version of the cell type align with individual ones of the plurality of gate lines along the first direction at both edges of the first version of the cell type along the second direction.3. The integrated circuit structure of claim 2 , wherein the first version of the cell type is a first version of an inverter cell.4. The integrated circuit structure of claim 1 , wherein individual ones of the second ...

Drug delivery device with piezoelectric actuator

The invention refers to an electrically actuated, needle-free injection device. The main field of application is drug delivery. The device is based on a piezoelectric actuator (11). The device enables controlled, continuous, tuneable drug delivery. The device enables painless injection, personalized and programmable dosage profiles. The device is designed, both to pierce the epidermis for trans-epidermal drug delivery and to deliver controlled amounts of fluid (transdermal, electronic pill and implantable drug delivery). This type of device enables personalized drug delivery and is an enabling component for closed-loop drug delivery systems.

Polysilicon polish for patterning improvement

Polysilicon polish for patterning improvement

A polishing process for polysilicon gate patterning improvement using standard patterning techniques in the manufacture of high performance metal oxide semiconductor (MOS) devices. The addition of a short silicon polish step, after deposition and before patterning of a polysilicon layer reduces the non-planarity normally associated with polysilicon. Polysilicon polishing removes the surface roughness in the polysilicon layer caused by the grain structure of polysilicon and the surface roughness due to the replication of the underlying topography of the isolation and substrate regions. The described method for removal of both types of surface roughness leaves the polysilicon layer planarized without increasing the defect level already associated with the manufacture of high performance MOS devices.

Polysilicon polish for patterning improvement

A polishing process for polysilicon gate patterning improvement using standard patterning techniques in the manufacture of high performance metal oxide semiconductor (MOS) devices. The addition of a short silicon polish step, after deposition and before patterning of a polysilicon layer on a wafer (200) reduces the non-planarity normally associated with polysilicon. Polysilicon polishing removes the surface roughness in the polysilicon layer caused by the grain structure of polysilicon and the surface roughness due to the replication of the underlying topography of the isolation and substrate regions. The described method of removal of both types of surface roughness leaves the polysilicon layer planarized without increasing the defect level already associated with the manufacture of high performance MOS devices.

SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS

A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder. 1. A method for forming a semiconductor structure , the method comprising:forming a body comprising semiconductor material;forming a gate stack above the body, the gate stack comprising a gate electrode structure and a gate dielectric structure, the gate electrode structure including a conductive material, the gate dielectric structure including a first dielectric material and a second dielectric material, the first and second dielectric materials being compositionally different from each other, the first dielectric material at least between the gate electrode structure and the body, and the second dielectric material at least between the first dielectric material and the body;forming a source region laterally adjacent to and in contact with the body, the source region extending under the gate stack and also in contact with the second dielectric material, wherein an upper surface of the source region is above portions of the first and second dielectric materials that are between the gate electrode structure and the body;forming a drain region laterally adjacent to and in contact with the body, the drain region extending under the gate stack and also in contact with the second dielectric material, wherein an upper surface of ...

Drug delivery device with piezoelectric actuator

The invention refers to an electrically actuated, needle-free injection device. The main field of application is drug delivery. The device is based on a piezoelectric actuator (11). The device enables controlled, continuous, tuneable drug delivery. The device enables painless injection, personalized and programmable dosage profiles. The device is designed, both to pierce the epidermis for trans-epidermal drug delivery and to deliver controlled amounts of fluid (transdermal, electronic pill and implantable drug delivery). This type of device enables personalized drug delivery and is an enabling component for closed-loop drug delivery systems.

SELECTION BASED ON REACTIONS FOR THE EXPRESSION OF, AND THE CONCENTRATION OF, CATALITICAL REMAINS.

SE PRESENTAN Y REIVINDICAN LOS METODO PARA SELECCIONAR UN VIRUS RECOMBINANTE, FAGO O CELULA QUE EXPRESAN UN ANTICUERPO CATALITICO O UNA PORCION CATALITICA DEL MISMO O PARA SELECCIONAR LA ACTIVIDAD CATALITICA MEDIANTE UNA UNIDAD. EN EL METODO SE LLEVA A CABO UNA SELECCION DE LA ACTIVIDAD CATALITICA BASADA EN UNA REACCION. EL METODO SE PUEDE UTILIZAR TAMBIEN PARA CONCENTRAR (AUMENTAR LA PROPORCION DE UNIDADES CATALITICAS RESPECTO A LAS NO CATALITICAS) UNA MUESTRA QUE CONTENGA UNA UNIDAD CATALITICA O VIRUS, FAGOS O CELULAS QUE EXPRESAN UNA UNIDAD CATALITICA. LA SELECCION O CONCENTRACION SE PUEDEN LLEVAR A CABO UTILIZANDO UN INHIBIDOR BASADO EN UN MECANISMO, UN MOVIMIENTO ACELERADO POR UNA CATALISIS, UN ENLACE SUPERFICIAL, CAMBIOS EN EL COMPONENTE ENTALPICO DE ENLACE COMO UNA FUNCION DE LA TEMPERATURA, O CAMBIOS EN EL ENLACE MEDIANTE UNA COMPETICION, O COMBINACIONES DE LOS MISMOS. LA INVENCION TAMBIEN SE REFIERE A UN METODO PARA LA PRODUCCION DE UN VIRUS RECOMBINANTE O LINEA CELULAR QUE EXPRESEUNA UNIDAD CATALITICA TAL COMO UN ANTICUERPO CATALITICO O UNA PORCION CATALITICA DEL MISMO; Y ESTE METODO PUEDE CONSISTIR EN INFECTAR UN HUESPED ADECUADO CON VIRUS QUE SE SELECCIONAN PARA LA EXPRESION. ADEMAS SE PRESENTAN Y REIVINDICAN TAMBIEN LOS VIRUS RECOMBINANTES Y LAS LINEAS CELULARES QUE EXPRESAN DE ESTE MODO UNA UNIDAD CATALITICA TAL COMO UN ANTICUERPO CATALITICO O UNA PORCION CATALITICA DEL MISMO. THE METHODS FOR SELECTING A RECOMBINING VIRUS, PHAGO OR CELL THAT EXPRESS A CATALYTIC ANTIBODY OR A CATALYTIC PORTION OF THE SAME OR TO SELECT THE CATALYTIC ACTIVITY THROUGH A UNIT ARE PRESENTED AND REIVINDICATED. IN THE METHOD A SELECTION OF THE CATALYTIC ACTIVITY BASED ON A REACTION IS CARRIED OUT. THE METHOD CAN ALSO BE USED TO CONCENTRATE (INCREASE THE PROVISION OF CATALYTIC UNITS REGARDING NON-CATALYTICAL) A SAMPLE CONTAINING A CATALYTIC UNIT OR VIRUSES, PHONES OR CELLS THAT EXPRESS A CATALYTIC UNIT. THE SELECTION OR CONCENTRATION CAN BE CARRIED OUT BY USING AN INHIBITOR ...

Method and apparatus for managing files in a storage medium

A method for managing a storage medium includes searching the storage medium for a first file having a reference to a second file that has moved to a new location on the storage medium. The reference is updated such that it indicates that the second file has moved to the new location.

HEAT TUBES COMPREHENSIVE WICK STRUCTURES WITH VARIABLE PERMEABILITY

Ein Wärmerohr ist mit einem Hohlkörper, der einen inneren Dampfraum, einen Verdampferbereich und einen Kondensatorbereich festlegt, einer Dochtstruktur, die an einer Innenwand des Hohlkörpers liegt, und einem Arbeitsfluid, das in dem Hohlkörper angeordnet ist, vorgesehen, wobei sich ein Weg für das Arbeitsfluid in einem flüssigen Zustand von dem Kondensatorbereich in Richtung des Verdampferbereichs erstreckt, oder wobei sich die Dochtstruktur entlang einer Richtung von einem ersten Ende des Hohlkörpers in Richtung des zweiten Endes erstreckt, und wobei die Dochtstruktur einen ersten und einen zweiten Bereich aufweist, die sich entlang des Weges oder der Richtung erstrecken und die jeweils Dochtpartikel aufweisen, die entsprechende Porengrößen festlegen, die sich voneinander unterscheiden. A heat pipe is provided with a hollow body which defines an inner vapor space, an evaporator area and a condenser area, a wick structure which lies on an inner wall of the hollow body, and a working fluid which is arranged in the hollow body, with a path for the working fluid extends in a liquid state from the condenser region in the direction of the evaporator region, or wherein the wick structure extends along a direction from a first end of the hollow body towards the second end, and wherein the wick structure has a first and a second region extending along the Extending path or direction and each having wick particles that define corresponding pore sizes that differ from one another.

Electrophoretic display with rapid drawing mode waveform

Vehicle center pillar structure

A vehicle body includes a center pillar structure including an outer reinforcement having an outer wall and two side walls defining a channel. Two reinforcements are located within the channel, each rigidly interconnecting the outer wall with a respective one of the sidewalls. A tension panel preferably interconnects the two sidewalls. The center pillar structure is characterized by continuity of strength along its height and increased resistance to vertical compressive loads.

Wear parts for earth working equipment

Atomization systems for high viscosity products

The present invention pertains to improved atomization systems for comparatively higher viscosity liquid products. More particularly, the present invention provides an improved product delivery system which combines a pre-compression type pump mechanism with a nozzle having two or more orifices configured to discharge corresponding jets or streams of the product which impinge upon one another to provide a finely dispersed spray. The pre-compression pump mechanism ensures that the product will only be delivered when sufficient pressure is available for atomization. Regardless of the speed or authority with which the pump mechanism is actuated, pressure within the pump will accumulate without product discharge until a lower pressure threshold is reached, at which time a valve opens to permit product discharge with sufficient pressure for atomization. When the fluid streams impinge upon one another, the fluid is broken up into a finely dispersed mist which may then be directed toward the surface to be coated. In a configuration particularly well-suited for comparatively higher viscosity fluids, the nozzle assembly of the product delivery system imparts additional relative velocity to the jets by introducing a swirl component of velocity prior to impingement, thus enhancing the atomization of the product.

Method and apparatus for generating a volatilized liquid

A programmable aerosol generator forms a volatilized liquid by supplying a material in liquid form to a flow passage and heating the flow passage, such that the material volatilizes and expands out of an outlet of the channel. The volatilized material, if desired, mixes with ambient air such that volatilized material condenses to form the aerosol. An apparatus and method for generating such a volatilized liquid, as well as the control and methods of heating, are disclosed as an analytical tool useful for experimental use, a tool useful for production of commercial products or an inhaler device.

Anti-clogging atomizer nozzle

The present invention provides an improved atomization system for dispensing and atomizing a fluid product having film-forming characteristics. The atomization system includes a nozzle for atomizing the fluid product which has been formed of a reduced wettability composition including a base material and a wettability-reducing component for reducing the wettability of the base material with the fluid product. The reduced-wettability attribute ensures that the product will tend to "bead up" on the surfaces of the nozzle assembly rather than wetting or coating the surfaces. The surfaces will thus tend to repel the product, once the supply pressure driving the fluid toward the nozzle is relieved, leaving the critical nozzle surfaces substantially free of a film of product which would tend to dry and form a residue on the critical nozzle surfaces when exposed to atmospheric air. The reduced wettability of the nozzle assembly is preferably achieved through the addition of a melt additive to impart the desired characteristics to the nozzle base material. Improved atomizer nozzles according to the present invention also preferably incorporate a change in cross-sectional area of the nozzle passages to further enhance the migration of the fluid away from the nozzle orifice once the supply pressure is relieved utilizing capillary pressure phenomena.

The isolation and production of catalytic antibodies using phage technology

An electrophoretic display with reduced cross talk

Packaging

Nanoalum particles containing a sizing agent

Provided herein are nanoalum particles comprising an aluminum salt and a sizing agent, wherein the size of the particle ranges from about 1nm to 450nm. Such nanoalum particles are stable and are amenable to a terminal sterilization step prior to vialing. Compositions comprising the nanoalum particles, and the making and using of the nanoalum particles are also provided.

Reciprocating piston pump with air valve, detent and poppets

Method and system for allocating specific appointment time windows in a service industry

The present invention provides a method for allocating appointment time windows. The steps of this method include creating a statistical estimate of a daily schedule comprising a series of estimated service orders. An actual service order is then received. This actual service order is inserted into the daily schedule by using a set of scheduling instructions for determining the least cost to employ the available service resources. At this point, this actual service order does not have a system imposed time window. The set of scheduling instructions is used to determine a time window surrounding this insertion point. If the customer accepts this time window, then the closest estimated service order is replaced by this actual service order, and the daily schedule is recomputed based upon the revised set of service orders to yield a revised daily schedule. This process may be repeated for any number of days or time periods from which the customer may choose the time window best meeting the customer's availability.

Gimbal stiffness control for head suspension assemblies

The present invention includes a polymeric/copper ring gimbal adhesively attached to a load beam. Such a gimbal further includes at least one deformation inhibiter for inhibiting and/or preventing the deformation of the gimbal, such deformation inhibiters comprising a forwardly or distally extending non-water absorbent appendage. Such a deformation inhibiting appendage may be an extension of the conductive traces forming the electrical pathway on the gimbal.

EMG electrode apparatus and positioning system

A system for detecting and analyzing electrical activity in the anatomy of an organism underlying an electrode array provides signals corresponding to electrical activity adjacent each electrode. Such signals are correlated to the underlying anatomy of the organism and representative outputs presented through various types of output devices. Such outputs may include variations in coloration or other qualities in correspondence with representations of underlying anatomical structures. The system includes novel electrode structures ( 200, 224 , and 284 ) and methods for producing and attaching electrode arrays ( 240 and 280 ) to the organism. The exemplary form of the invention is used in connection with the diagnosis of muscle activity in the lower lumbar regions of humans. Levels of muscle activity detected are analyzed by correlation with the muscular structures underlying the electrode array. Forms of the invention may be used in other applications.

Patent DE602006014634D1

NiTi alloyed guidewires

The present invention is directed to an intracorporeal device, preferably a guidewire, and method for making the same. The device, has proximal and distal ends and includes an elongated high strength proximal portion having proximal and distal ends. The device further includes a distal portion having proximal and distal ends. The distal end of the proximal portion and the proximal end of the distal portion are connected by a connector. The distal portion is formed of a superelastic alloy composition. Preferably, the connector is also formed of the superelastic alloy composition. The superelastic alloy composition includes, in atomic percent, from about 28 to about 52% nickel, from about 48 to about 52% titanium, and up to about 20% of at least one alloying element selected from the group consisting of palladium, chromium, and hafnium.

Flexure guide bearing for short stroke stage

A laser processing system in which a laser beam propagates along a beam axis and through a lens for incidence on a work surface of a target specimen mounted on a support. The lens forms a focal region of the laser beam. The support is operatively connected to a multiple-axis positioning system that moves the laser beam and the target specimen relative to each other to position the laser beam at selected locations on the work surface. An assembly includes at least one flexure that supports the lens and guides movement of the lens along the beam axis in response to a motive force to adjust the focal region of the laser beam relative to the work surface.

Multi-burner head

A multi-burner system includes a horizontally elongated body structure having burner heads extending along an axis. Each burner head has a length along the axis greater than a width or height thereof and includes an inner chamber, a housing surrounding the inner chamber and holes formed on the housing to disperse gas externally from the inner chamber. The multi-burner system further includes a plurality of conduits connected to the body structure to convey the gas to the inner chamber of each burner head.

Heat transfer apparatus and method

A method is provided for heat transfer from a surface to a fluid. The method includes directing a first fluid flow towards the surface in a first direction and directing a second fluid flow towards the surface in a second direction. The first and second fluid flows cooperate to cool the surface.

A novel passivation structure and its method of fabrication

Via blocking layer

Computerized emg diagnostic system

Reciprocating pump with electronically monitored air valve and piston

Hermetic passivation structure with low capacitance

A wafer passivation structure and its method of fabrication is described. According to one embodiment of the present invention a metal layer having a bond pad spaced by a gap from a metal member is formed on a substrate. A first dielectric layer is then formed over the bond pad and the metal member and completely fills the gap. Next a second dielectric layer, having a dielectric constant greater than the first dielectric layer and being hermetic is formed over the first dielectric layer. In another embodiment of the present invention a first dielectric layer is formed on the top surface of a bond pad of a substrate. A second dielectric layer is then formed on the first dielectric. An opening is then formed through the first and second dielectric layers so as to expose the top surface of the bond pad. A barrier layer is then deposited on the sides of the opening and on the top surface of the bond pad. A contact is then formed on the barrier layer in the opening.

Insertion tool and insertion guide system

【課題】本発明は、骨締結具及び埋込みデバイスを手術部位に挿入するために用いる挿入工具及びガイドシステムを提供するものである。 【解決手段】挿入工具は、骨体に埋込みデバイスを固定するために、使用者が骨締結具と関連する工具とを手術部位に安全に挿入することを可能にする湾曲した締結具ガイドを備えている。挿入工具は、長尺のカニューレと、締結具ガイドの遠位端に結合された取付け用シャフトとを備えている。取付け用シャフトは、埋込みデバイスに連結され、挿入工具は、埋込みデバイスを手術部位に配置するために用いることができる。締結具ガイドは、骨締結具を正確に配置するために、埋込みデバイスに設けられた締結孔と整合させることができる。 【選択図】 図１

A method and apparatus for priority based flow control in an ethernet architecture

A method and apparatus for priority-based flow control in an Ethernet architecture is generally described. In accordance with one aspect of the invention, a method is presented comprising identifying a receive capability associated with one or more priority levels of Ethernet traffic for a network device, and generating a control message including a flow control priority level, the flow control priority level denoting the identified priority level above or below which the network device has the ability to receive Ethernet traffic.

Locally reversible barbed sutures.

Un dispositivo de cierre de incluye un filamento flexible que tiene un primer extremo, un segundo extremo, y un eje longitudinal que se extiende entre el primer y el segundo extremos; una pluralidad de dientes sobresalen hacia afuera desde el filamento flexible; cada diente tiene una base conectada con el filamento flexible, una punta roma separada de la base, un borde anterior que se extiende entre la base y la punta roma y que se orienta hacia el primer extremo del filamento flexible, y un borde posterior que se extiende entre la base y la punta y que se orienta hacia el segundo extremo del filamento flexible; el borde posterior del diente y el eje longitudinal del filamento flexible definen un ángulo de al menos 68° que se abre hacia el segundo extremo del filamento flexible.

Head suspension load beam and flexure construction for reducing structural height

A head suspension includes a two piece construction including a load beam and a separately formed flexure wherein the assembly and construction facilitates the need for less space between disks within a disk drive. More specifically, the thickness of the flexure member need not be factored into the height of the load point dimple. The load point dimple height need only facilitate pitch and roll slider movements; thus, reducing the side profile of the head suspension. Moreover, the present invention allows for the use of load point dimples which are formed within the thickness of the load beam material, which can further reduce the side profile. In one aspect, a mounting surface of the mounting portion is provided on an opposite side of the load beam than the side of the load beam from which the load point dimple extend. The load portion can be also provided with a reduced thickness area with the load point dimple within the reduced thickness area. Alternatively, with the provision of a reduced thickness area the mounting surface of the mounting portion can be provided on the dimple side of the load beam with each of its spring arms including an offset bend for providing a first surface portion of each spring arm that is spaced closer to a level of a surface of the reduced thickness area.

FIRE SENSOR SENSITIVE TO A DOUBLE FREQUENCY SPECTRUM

Thiazoles and oxazoles useful as modulators of atp-binding cassette transporters

Compound monitoring by electrochemiluminescence technique

【課題】本発明は、電気化学発光性化合物に共有結合でつないだ化学的に変換しうる第一の化合物からなる検知可能な化合物を提供する。これら化合物は、第一の化合物の状態をモニターし、そしてこのモニターリングから情報を引き出す方法およびキットに有用である。図は、非接合還元剤としてＴＰＡの使用と関連する反応段階を描いたＥＣＬの提案機構を示す。 【解決手段】試料中の対象分析物を測定するための化合物であって、金属の配位錯体を含む電気化学発光標識を含んでなり、該標識はβ−ラクタム及びβ−ニコチンアミドアデニンコファクターから選ばれた触媒基質に結合しているが、該触媒基質と対応する触媒産物とは、電気化学発光標識と反応して電気化学発光標識に電気化学発光を起こさせる能力において異なっている、上記化合物。 【選択図】図１