Forming a retrograde well in a transistor to enhance performance of the transistor

A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

Forming a retrograde well in a transistor to enhance performance of the transistor

A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

FIN FIELD EFFECT TRANSISTOR FORMING METHOD AND INTEGRATED CIRCUIT ELEMENT

The present invention relates to methods to form an FinFET. According to an embodiment of the present invention, the FinFET forming method includes a step of forming a fin-shaped channel area including indium on a substrate; a step of forming a deep source/drain area on the substrate to be adjacent to the channel area; and a step of forming a source/drain expansion area between the channel area and the deep source/drain area. Facing side walls of the source/drain expansion area make contact with the channel area and the deep source/drain area. The source/drain expansion area includes InyGa1-yAs including y in a range of 0.3 to 0.5. COPYRIGHT KIPO 2016 ...

SEMICONDUCTOR DEVICE INCLUDING STRAINED CHANNEL REGION

Provided is a semiconductor including a strained channel region. The semiconductor device includes a quantum well channel region. The quantum well channel region has a well thickness (TW) sufficient to yield a strain-induced splitting of a plurality of equivalent-type electron conduction states including respective unequal energy levels having a lowermost energy level associated with a lowermost surface roughness scattering formed adjacent to the surface of the channel region, when the surface of the channel region is biased into a state of inversion. COPYRIGHT KIPO 2016 ...

Forming a retrograde well in a transistor to enhance performance of the transistor

A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

GATED RESONANT TUNNELING DIODE

A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is formed on the body with the insulating layer extending over the quantum well region and at least a portion of the barrier region, and a control electrode region is formed on the insulating layer.

MULTI-LAYER FIN FIELD EFFECT TRANSISTOR DEVICE AND METHOD FOR FORMING SAME

Provided are multi-layer fin field effect transistor devices, and methods for forming the same. The devices can include a fin-shaped channel structure on a substrate. The channel structure includes stressor layers stacked on the substrate, and a channel layer among the stressor layers. The stressor layers can include a wide band gap sufficient to confine carriers as the channel layer, and a semiconductor material for inducing stress in the channel layer by having a lattice constant different from that of the channel layer. The devices can also include source/drain regions arranged on first sides facing the channel structure, respectively, and gates on second sides facing the channel structure between the source/drain regions. COPYRIGHT KIPO 2016 ...

METHODS OF FORMING SEMICONDUCTOR PATTERNS INCLUDING REDUCED DISLOCATION DEFECTS AND DEVICES FORMED USING SUCH METHODS

Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods are provided. The methods may include forming an oxide layer on a substrate and forming a recess in the oxide layer and the substrate. The methods may further include forming an epitaxially grown semiconductor pattern in the recess that contacts a sidewall of the substrate at an interface between the oxide layer and the substrate and defines an upper surface of a void in the recess in the substrate. 1. A method of forming a semiconductor pattern , the method comprising:forming an oxide layer on a substrate;forming a recess in the oxide layer and the substrate; andforming an epitaxially grown semiconductor pattern in the recess, which contacts a sidewall of the substrate at an interface between the oxide layer and the substrate and defines an upper surface of a void in the recess in the substrate.2. The method of claim 1 , wherein forming the epitaxially grown semiconductor pattern comprises:epitaxially growing a lower semiconductor pattern defining the upper surface of the void in the recess in the substrate using the sidewall of the substrate at the interface between the oxide layer and the substrate as a first seed layer; andepitaxially growing an upper semiconductor pattern in the recess using the lower semiconductor pattern as a second seed layer.3. The method of claim 2 , wherein the void exposes the sidewall of the substrate.4. The method of claim 2 , wherein the lower semiconductor pattern comprises a material different from the upper semiconductor pattern.5. The method of claim 4 , wherein the lower semiconductor pattern comprises silicon germanium (SiGe) claim 4 , and the upper semiconductor pattern comprises germanium (Ge).6. The method of claim 1 , wherein:the substrate comprises a first semiconductor layer and a second semiconductor layer extending between the oxide layer and the first semiconductor layer;the second semiconductor layer ...

Methods of fabricating quantum well field effect transistors having multiple delta doped layers

Methods of fabricating quantum well field effect transistors are provided. The methods may include forming a first barrier layer including a first delta doped layer on a quantum well layer and forming a second barrier layer including a second delta doped layer selectively on a portion of the first barrier layer in a first region of the substrate. The methods may also include patterning the first and second barrier layers and the quantum well layer to form a first quantum well channel structure in the first region and patterning the first barrier layer and the quantum well layer to form a second quantum well channel structure in a second region. The methods may further include forming a gate insulating layer on the first and second quantum well channel structures of the substrate and forming a gate electrode layer on the gate insulating layer.

STACK STRUCTURE OF SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF

The present invention relates to a stack structure of a semiconductor device and a forming method thereof. The stack structure of a semiconductor device comprises: a plurality of sacrificial layers each having a first lattice parameter; at least one channel layer which has a second lattice parameter different from the first lattice parameter, is formed between two of the sacrificial layers, and comes in contact with the two of the sacrificial layers; and a lower layer on which the sacrificial layers and the channel layer are formed. The sacrificial layers come in contact with the lower layer. The lower layer has a third lattice parameter. The third lattice parameter is practically equal to the lattice parameters of the sacrificial layers and the channel layer if the sacrificial layers and the channel layer are allowed to be coherently relaxed. COPYRIGHT KIPO 2017 ...

INTEGRATED CIRCUIT DEVICES INCLUDING STRAINED CHANNEL REGIONS AND METHODS OF FORMING THE SAME

Integrated circuit devices including strained channel regions and methods of forming the same are provided. The integrated circuit devices may include enhancement-mode field effect transistors. The enhancement-mode field effect transistors may include a quantum well channel region having a well thickness T W sufficient to yield a strain-induced splitting of a plurality of equivalent-type electron conduction states therein to respective unequal energy levels including a lowermost energy level associated with a lowermost surface roughness scattering adjacent a surface of the channel region when, the surface is biased into a state of inversion.

NANOSHEET FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF

Provided is a nanosheet field effect transistor (FET) to restrain a parasitic bipolar effect. The nanosheet FET comprises: a well having an impurity doped on a surface of a substrate; a channel including a semiconductor material stacked on the well and having a conductive impurity identical to the impurity of the well, and a plurality of nanosheet stacks separated from each other in a vertical direction on the surface of the substrate; a gate including work function metal arranged between the plurality of neighboring nanosheets, and between the plurality of nanosheets and the well on the nanosheets; a conductive material arranged to be adjacent to the plurality of nanosheets to electrically connect the plurality of nanosheets with the well; and an isolation layer arranged on the well to electrically isolate the well from the work function metal. COPYRIGHT KIPO 2016 ...

Integrated circuit devices including FinFETS and methods of forming the same

Integrated circuit devices including fin field-effect transistors (finFETs) and methods of forming the same are provided. The methods may include forming a fin-shaped channel region including germanium on a substrate and forming a source/drain region adjacent the channel region on the substrate. The methods may further include forming a barrier layer contacting sidewalls of the channel region and the source/drain region, and the barrier layer may include SixGe1-x, and x may be in a range of about 0.05 to about 0.2.

SEMICONDUCTOR DEVICES WITH STRUCTURES FOR SUPPRESSION OF PARASITIC BIPOLAR EFFECT IN STACKED NANOSHEET FETS AND METHODS OF FABRICATING THE SAME

A device may include a nanosheet field effect transistor (FET) that may include a substrate, a well that is doped with impurities at a surface of the substrate, a channel including a plurality of stacked nanosheets, a gate, a conductive material, and an isolation layer. Ones of the plurality of stacked nanosheets may include a semiconductor material that may be doped with impurities of the same conductivity type as the impurities of the well. The conductive material may be adjacent the plurality of nanosheets and may electrically connect ones of the plurality of nanosheets to the well. The isolation layer may electrically insulate the well from the workfunction metal. 1. A device comprising a nanosheet field effect transistor (FET) , the nanosheet FET comprising:a well that is doped with impurities at a surface of a substrate;a channel comprising a plurality of stacked nanosheets on the well, ones of the plurality of stacked nanosheets comprising a semiconductor material that is doped with impurities of a same conductivity type as the impurities of the well and ones of the plurality of stacked nanosheets spaced apart from each other in a direction that is perpendicular to the surface of the substrate;a gate comprising a workfunction metal on the plurality of nanosheets, between adjacent ones of the plurality of nanosheets, and between the plurality of nanosheets and the well;a conductive material adjacent the plurality of nanosheets and that electrically connects ones of the plurality of nanosheets to the well;an isolation layer on the well that electrically insulates the well from the workfunction metal.2. The device of claim 1 , wherein the conductive material comprises a semiconductor material that is doped with impurities of the same conductivity type as the impurities of the well.3. The device of claim 2 , wherein the conductive material comprises the same semiconductor material as the plurality of nanosheets.4. The device of claim 2 ,wherein an impurity ...

INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF

Provided is an integrated circuit including a nano-sheet FET. The integrated circuit includes: multiple first nano-sheet field-effect transistors (FET); and multiple second nano-sheet FETs. A nano-sheet of any one of the first nano-sheet FETs includes not more than 30% of Si, the first nano-sheet FETs define a critical speed path, a nano-sheet of any one of the second nano-sheet FETs includes not more than 30% of Si, the second nano-sheet FETs define a non-critical speed path, and one of the first nano-sheet FETs is faster than one of the second nano-sheet FETs. COPYRIGHT KIPO 2016 ...

LOW RESISTIVITY DAMASCENE INTERCONNECT

A damascene interconnect structure with low resistivity is provided. The damascene interconnect structure with low resistivity comprises: a dielectric material having a trench; a first liner material arranged along a sidewall of the trench and not arranged in a lower portion of the trench; a second liner material different from the first liner material, arranged along the lower portion of the trench, and not arranged on the sidewall of the trench; and a conductive material coming in contact with the first and second liner materials, deposited on the first and second liner materials, and filing the trench. The first liner material has relatively low wettability about the conductive material and the second liner material has relatively high wettability about the conductive material. COPYRIGHT KIPO 2016 ...

SEMI-METAL TRANSISTOR AND FABRICATING METHOD THEREOF

Provided are a semi-metal transistor and a fabricating method thereof. The semi-metal transistor comprises: a contact region which includes a semi-metal and is adjacent to a metal contact; at least one semiconductor terminal; and a semi-metal transition region connected between the contact region and the semiconductor terminal that transitions from a zero gap semi-metal beginning at an interface of the contact region into a semiconductor with an energy band gap towards the semiconductor terminal. COPYRIGHT KIPO 2016 ...

STACKED NANOSHEET FETS HAVING STRAIN AND/OR QUANTUM WELL- STACKED NANOSHEET

Provided is a method for manufacturing a nanosheet stack structure having one or more sub-stacks. The method grows an epitaxial crystalline added stack for the one or more sub-stacks. Each of the sub-stacks contains a sacrificial layer, a first and a second non-sacrificial layers having different material properties. The non-sacrificial layers have a thickness below thermodynamic or kinetic critical thickness related to a semi-stability during the entire manufacturing process. The sacrificial layer is placed only above or below the sub-stacks. Each of sub-stacks use the sacrificial layer to be connected to above or below adjacent sub-stacks. Then, the method proceeds with a manufacturing process of nanosheet devices in order to form pillar structures on both ends of the epitaxial crystalline stack so as to support nanosheets which remain after a selective removal of the sacrificial layer. The sacrificial layer is selectively removed with respect to the non-sacrificial layers, such that ...

FIELD EFFECT TRANSISTOR INCLUDING RECTANGULAR NANOSHEET AND METHOD FOR FABRICATING SAME

Provided are a method for fabricating a nanosheet structure and a field-effect transistor (FET) including the same. The method for fabricating a nanosheet structure, comprises: selecting an active material that will serve as a channel material in the nanosheet structure, a substrate suitable for epitaxial growth of the active material, and a sacrificial material to be used during fabrication of the nanosheet structure; growing a stack of alternating layers of active and sacrificial materials over the substrate; and selectively etching the sacrificial material, wherein due to the properties of the sacrificial material, the selective etch results in remaining layers of active material having an aspect ratio greater than 1 and the same thickness and atomic smoothness along the entire cross-sectional width of each active material layer perpendicular to current flow. COPYRIGHT KIPO 2016 (100) Selecting an active material functioning as a channel material in a nano sheet structure, a substrate ...

Forming a retrograde well in a transistor to enhance performance of the transistor

A method of forming a retrograde well in a transistor is provided. A transistor structure having a substrate, a gate, and a gate oxide layer between the substrate and the gate is formed. The substrate includes a channel region located generally below the gate. A first dopant is implanted into the channel region. A second dopant is implanted into the substrate to form a doped source region and a doped drain region. A third dopant is implanted into the gate oxide layer. A source/drain anneal is performed to form a source and a drain in the doped source region and the doped drain region, respectively. The source/drain anneal causes a portion of the first dopant in the channel region to be attracted by the third dopant into the gate oxide layer.

Enhanced PMOS via transverse stress

In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regions has a <100> direction through the channel region. Dielectric regions create a compressive stress on the channel region perpendicular to the current flow.

Enhanced PMOS via transverse stress

In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regions has a <100> direction through the channel region. Dielectric regions create a compressive stress on the channel region perpendicular to the current flow.

STRAINED STACKED NANOSHEET FIELD-EFFECT TRANSISTOR AND/OR QUANTUM WELL STACKED NANOSHEET

Provided is a method for manufacturing a biaxially strained nanosheet. The manufacturing method according to embodiments of the present invention comprises: growing an epitaxial crystalline initial superlattice having one or more periods, each of the periods including at least three layers of an active material layer, a first sacrificial material layer, and a second sacrificial material layer, the first and second sacrificial material layers having different material properties; in each of the one or more periods, placing each of the active material layers between the first and second sacrificial material layers, wherein lattice constants of the first and second sacrificial material layers are different from a lattice constant of the active material layer and applying biaxial stress to the active material layer; selectively etching the first sacrificial material layers for an additional process so as to expose a first surface of the active material layers and maintaining the biaxial stress ...

Quantum electro-optical device using CMOS transistor with reverse polarity drain implant

A CMOS IC containing a quantum well electro-optical device (QWEOD) is disclosed. The QWEOD is formed in an NMOS transistor structure with a p-type drain region. The NLDD region abutting the p-type drain region forms a quantum well. The QWEOD may be fabricated with 65 nm technology node processes to have lateral dimensions less than 15 nm, enabling possible energy level separations above 50 meV. The quantum well electro-optical device may be operated in a negative conductance mode, in a photon emission mode or in a photo detection mode.

Enhanced PMOS via transverse stress

In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regions has a <100> direction through the channel region. Dielectric regions create a compressive stress on the channel region perpendicular to the current flow.

MULTI-LAYER FIN FIELD EFFECT TRANSISTOR DEVICES AND METHODS OF FORMING THE SAME

Multi-layer fin field effect transistor devices and methods of forming the same are provided. The devices may include a fin shaped channel structure on a substrate. The channel structure may include stressor layers stacked on the substrate and a channel layer between the stressor layers, and the stressor layers may include a semiconductor material having a wide bandgap that is sufficient to confine carriers to the channel layer and having a lattice constant different from a lattice constant of the channel layer to induce stress in the channel layer. The devices may also include source/drain regions on respective first opposing sides of the channel structure and a gate on second opposing sides of the channel structure and between the source/drain regions.

GATED RESONANT TUNNELING DIODE

A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is ...

Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods

Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods are provided. The methods may include forming an oxide layer on a substrate and forming a recess in the oxide layer and the substrate. The methods may further include forming an epitaxially grown semiconductor pattern in the recess that contacts a sidewall of the substrate at an interface between the oxide layer and the substrate and defines an upper surface of a void in the recess in the substrate.

Method of forming enhanced device via transverse stress

In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regions has a <100> direction through the channel region. Dielectric regions create a compressive stress on the channel region perpendicular to the current flow.

FINFET SEMICONDUCTOR DEVICES INCLUDING RECESSED SOURCE-DRAIN REGIONS ON A BOTTOM SEMICONDUCTOR LAYER AND METHODS OF FABRICATING THE SAME

FinFET semiconductor devices and methods of forming the same are provided. The finFET semiconductor devices may include an insulator layer, a bottom semiconductor layer on the insulator layer, a channel fin on the bottom semiconductor layer, a source region on the bottom semiconductor layer and adjacent a first side of the channel fin, and a drain region on the bottom semiconductor layer and adjacent a second side of the channel fin opposite the first side. 1. A finFET semiconductor device , comprising:an insulator layer;a bottom semiconductor layer on the insulator layer, the bottom semiconductor layer comprising a first percentage of a first semiconductor material and a second semiconductor material;a channel fin on the bottom semiconductor layer, the channel fin comprising a second percentage of the first semiconductor material and the second semiconductor material, wherein the second percentage of the first semiconductor material in the channel fin is less than the first percentage of the first semiconductor material in the bottom semiconductor layer;a source region on the bottom semiconductor layer and adjacent a first side of the channel fin, the source region comprising a third percentage of the first semiconductor material and the second semiconductor material, wherein the third percentage of the first semiconductor material in the source region is greater than the second percentage of the first semiconductor material in the channel fin; anda drain region on the bottom semiconductor layer and adjacent a second side of the channel fin that is opposite the first side, the drain region comprising a fourth percentage of the first semiconductor material and the second semiconductor material, wherein the fourth percentage of the first semiconductor material in the drain region is greater than the second percentage of the first semiconductor material in the channel fin.2. The finFET semiconductor device of claim 1 , wherein the first semiconductor material is ...

QUANTUM ELECTRO-OPTICAL DEVICE USING CMOS TRANSISTOR WITH REVERSE POLARITY DRAIN IMPLANT

A CMOS IC containing a quantum well electro-optical device (QWEOD) is disclosed. The QWEOD is formed in an NMOS transistor structure with a p-type drain region. The NLDD region abutting the p-type drain region forms a quantum well. The QWEOD may be fabricated with 65 nm technology node processes to have lateral dimensions less than 15 nm, enabling possible energy level separations above 50 meV. The quantum well electro-optical device may be operated in a negative conductance mode, in a photon emission mode or in a photo detection mode. 1. An integrated circuit (IC) comprising:a p-type substrate;a gate dielectric layer formed on a top surface of the substrate;a gate formed on a top surface of the gate dielectric layer;an n-type source region formed in the substrate adjacent to and on one side of the gate;an n-type quantum well region formed in the substrate adjacent to the gate on an opposite side of the gate from the source region; anda p-type drain region formed in the substrate abutting the quantum well region on an opposite side of the quantum well region from the gate.2. The IC of claim 1 , wherein the IC further comprises a p-type halo region with a doping density between 1·10and 1·10cmformed in the substrate under the gate and abutting the quantum well region.3. The IC of claim 2 , in which a width of the quantum well region is less than 15 nanometers.4. The IC of claim 3 , in which a doping density of the quantum well region is above 1·10cm.5. The IC of claim 4 , in which a first electron energy state in the quantum well region is separated from a second electron energy state in the quantum well region by more than 50 meV.6. The IC of claim 5 , wherein the IC further comprises a gate sidewall spacer on a lateral surface of the gate overlapping the drain region claim 5 , whereby a lateral boundary of the drain region is defined on one side by a boundary of the gate sidewall spacer.7. The IC of claim 6 , in which a length of the quantum well region is less than ...

METHODS OF FABRICATING QUANTUM WELL FIELD EFFECT TRANSISTORS HAVING MULTIPLE DELTA DOPED LAYERS

Methods of fabricating quantum well field effect transistors are provided. The methods may include forming a first barrier layer including a first delta doped layer on a quantum well layer and forming a second barrier layer including a second delta doped layer selectively on a portion of the first barrier layer in a first region of the substrate. The methods may also include patterning the first and second barrier layers and the quantum well layer to form a first quantum well channel structure in the first region and patterning the first barrier layer and the quantum well layer to form a second quantum well channel structure in a second region. The methods may further include forming a gate insulating layer on the first and second quantum well channel structures of the substrate and forming a gate electrode layer on the gate insulating layer. 1. A method of forming an integrated circuit device comprising:forming a first barrier layer comprising a first delta doped layer on a quantum well layer;forming a second barrier layer comprising a second delta doped layer selectively on a portion of the first barrier layer in a first region of the substrate;patterning the first and second barrier layers and the quantum well layer to form a first quantum well channel structure in the first region and patterning the first barrier layer and the quantum well layer to form a second quantum well channel structure in a second region;forming a gate insulating layer on the first and second quantum well channel structures of the substrate; andforming a gate electrode layer on the gate insulating layer.2. The method of claim 1 , wherein forming the gate insulating layer comprises forming the gate insulating layer covering portions of sides of the first and second quantum well channel structures.3. The method of claim 1 , wherein forming the second barrier layer comprises:forming a preliminary second barrier layer comprising a preliminary second delta doped layer on the first barrier ...

QUANTUM INTERFERENCE BASED LOGIC DEVICES INCLUDING ELECTRON MONOCHROMATOR

A logic device is provided which includes an electron monochromator. The electron monochromator includes a quantum dot disposed between first and second tunneling barriers, an emitter coupled to the first tunneling barrier, and a collector coupled to the second tunneling barrier. The logic device also includes a quantum interference device. The quantum interference device includes a source which is coupled to the collector of the electron monochromator.

INTEGRATED CIRCUIT DEVICES INCLUDING FINFETS AND METHODS OF FORMING THE SAME

Integrated circuit devices including fin field-effect transistors (finFETs) and methods of forming the same are provided. The methods may include forming a fin-shaped channel region including germanium on a substrate and forming a source/drain region adjacent the channel region on the substrate. The methods may further include forming a barrier layer contacting sidewalls of the channel region and the source/drain region, and the barrier layer may include SiGe, and x may be in a range of about 0.05 to about 0.2. 1. A method of forming a finFET , the method comprising:forming a fin-shaped channel region comprising germanium on a substrate;forming a source/drain region adjacent the channel region on the substrate;{'sub': x', '1-x, 'forming a barrier layer contacting sidewalls of the channel region and the source/drain region, wherein the barrier layer comprises SiGe, and x is in a range of about 0.05 to about 0.2.'}2. The method of claim 1 , wherein a germanium concentration in the channel region is greater than a germanium concentration in the barrier layer.3. The method of claim 1 , wherein:{'sub': 1-y', 'y, 'forming the channel region comprises forming the channel region comprising SiGe, and y is in a range of about 0.8 to about 1; and'}forming the source/drain region comprises forming a portion of the source/drain region comprising substantially pure germanium.4. The method of claim 3 , wherein:a germanium concentration in the channel region is greater than a germanium concentration in the barrier layer; anda germanium concentration in the source/drain region is substantially equal to or greater than the germanium concentration in the barrier layer.5. (canceled)6. The method of claim 1 , wherein:{'sub': 1-y', 'y, 'forming the channel region comprises forming the channel region comprising SiGe, and y is in a range of about 0.85 to about 1; and'}forming the source/drain region comprises forming a portion of the source/drain region comprising substantially pure ...

Gated resonant tunneling diode

A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is ...

Quantum interference based logic devices including electron monochromator

A logic device is provided which includes an electron monochromator. The electron monochromator includes a quantum dot disposed between first and second tunneling barriers, an emitter coupled to the first tunneling barrier, and a collector coupled to the second tunneling barrier. The logic device also includes a quantum interference device. The quantum interference device includes a source which is coupled to the collector of the electron monochromator.

FINFET DEVICES INCLUDING HIGH MOBILITY CHANNEL MATERIALS WITH MATERIALS OF GRADED COMPOSITION IN RECESSED SOURCE/DRAIN REGIONS AND METHODS OF FORMING THE SAME

A finFET device can include a high mobility semiconductor material in a fin structure that can provide a channel region for the finFET device. A source/drain recess can be adjacent to the fin structure and a graded composition epi-grown semiconductor alloy material, that includes a component of the high mobility semiconductor material, can be located in the source/drain recess.

Gated resonant tunneling diode

A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is ...

FINFET DEVICES INCLUDING RECESSED SOURCE/DRAIN REGIONS HAVING OPTIMIZED DEPTHS AND METHODS OF FORMING THE SAME

A finFET device can include a source/drain contact recess having an optimal depth beyond which an incremental decrease in a spreading resistance value for a horizontal portion of a source/drain contact in the recess provided by increased depth may be less than an incremental increase in total resistance due to the increase in the vertical portion of the source/drain contact at the increased depth.

Gated resonant tunneling diode

A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region. An insulating layer is ...

THERMIONICALLY-OVERDRIVEN TUNNEL FETS AND METHODS OF FABRICATING THE SAME

A field effect transistor (FET) includes a nanosheet stack having first and second stacked semiconductor channel layers. The first channel layer defines a channel region of a tunnel FET, and the second channel layer defines a channel region of a thermionic FET. Source and drain regions are provided on opposite sides of the nanosheet stack such that the first and second channel layers extend therebetween. A first portion of the source region adjacent the first channel layer and a second portion of the source region adjacent the second channel layer have opposite semiconductor conductivity types. Related fabrication and operating methods are also discussed.

Finfet devices including high mobility channel materials with materials of graded composition in recessed source/drain regions and methods of forming the same

A finFET device can include a high mobility semiconductor material in a fin structure that can provide a channel region for the finFET device. A source/drain recess can be adjacent to the fin structure and a graded composition epi-grown semiconductor alloy material, that includes a component of the high mobility semiconductor material, can be located in the source/drain recess.

FINFET DEVICES INCLUDING RECESSED SOURCE/DRAIN REGIONS HAVING OPTIMIZED DEPTHS AND METHODS OF FORMING THE SAME

A finFET device can include a source/drain contact recess having an optimal depth beyond which an incremental decrease in a spreading resistance value for a horizontal portion of a source/drain contact in the recess provided by increased depth may be less than an incremental increase in total resistance due to the increase in the vertical portion of the source/drain contact at the increased depth. 1. A finFET device comprising:a semiconductor fin between doped semiconductor source and drain regions;a metal contact on the doped semiconductor source or drain region, providing a vertical and a horizontal interface of the metal contact and the doped semiconductor;a vertical contact resistance value defined by an area of the vertical interface and a resistivity of the vertical interface;a spreading resistance value associated with the horizontal interface; anda recess for the metal contact, the recess having a depth that is limited to a point where beyond which an incremental decrease in the spreading resistance value associated with the horizontal interface is less than an incremental increase in a total resistance of the finFET.2. The finFET device of wherein the depth of recess is inversely proportional to the resistivity of the vertical interface.4. The finFET device of wherein the depth of the recess varies based on different dopant types included in the doped semiconductor source or drain region.5. The finFET device of wherein the depth of the recess varies by about 10 nm based on the different dopant types.6. The finFET device of wherein the doped semiconductor comprises an epi-grown in-situ doped semiconductor.7. The finFET device of further comprising:a spreading resistance value associated with the vertical interface; anda spreading resistance value associated with the horizontal interface.8. The finFET device of wherein the resistivity of the vertical interface and the depth of the recess are substantially related as shown by a line segment in claim 1 , which ...

LOW RESISTIVITY DAMASCENE INTERCONNECT

A damascene interconnect structure may be formed by forming a trench in an ILD. A diffusion barrier may be deposited on trench surfaces, followed by a first liner material. The first liner material may be removed from a bottom surface of the trench. A second liner material may be directionally deposited on the bottom. A conductive seed layer may be deposited on the first and second liner materials, and a conductive material may fill in the trench. A CMP process can remove excess material from the top of the structure. A damascene interconnect may include a dielectric having a trench, a first liner layer arranged on trench sidewalls, and a second liner layer arranged on a trench bottom. A conductive material may fill the trench. The first liner material may have low wettability and the second liner material may have high wettability with respect to the conductive material. 1. A low resistivity damascene interconnect , comprising:a dielectric material having a trench formed therein;a first liner material arranged along sidewalls of the trench but not a bottom surface of the trench;a second liner material, different from the first liner material, arranged along a bottom surface of the trench but not along sidewalls of the trench; anda conductive material deposited on and contacting the first and second liner materials and filling the trench,wherein the first liner material has a relatively low wettability with respect to the conductive material, and wherein the second liner material has a relatively high wettability with respect to the conductive material.2. An interconnect according to claim 1 , wherein the conductive material is copper (Cu) claim 1 , aluminum (Al) claim 1 , gold (Au) claim 1 , or silver (Ag).3. An interconnect according to claim 1 , wherein the first liner material is tantalum (Ta) claim 1 , and wherein the second liner material is Ruthenium (Ru).4. An interconnect according to claim 1 , wherein the first liner material and the second liner material ...

Structure and method to achieve large strain in ns without addition of stack-generated defects

A stack for a semiconductor device and a method for making the stack are disclosed. The stack comprises a plurality of sacrificial layers in which each sacrificial layer comprises a first lattice parameter; and at least one channel layer comprising a second lattice parameter that is different from the first lattice parameter and in which each channel layer is disposed between and in contact with two sacrificial layers. The stack is formed on an underlayer in which a sacrificial layer is in contact with the underlayer. The underlayer comprises a third lattice parameter that substantially matches the lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were was allow to relax coherently.

RECTANGULAR NANOSHEET FABRICATION

Exemplary embodiments provide methods for fabricating a nanosheet structure suitable for field-effect transistor (FET) fabrication. Aspects of exemplary embodiment include selecting an active material that will serve as a channel material in the nanosheet structure, a substrate suitable for epitaxial growth of the active material, and a sacrificial material to be used during fabrication of the nanosheet structure; growing a stack of alternating layers of active and sacrificial materials over the substrate; and selectively etching the sacrificial material, wherein due to the properties of the sacrificial material, the selective etch results in remaining layers of active material having an aspect ratio greater than 1 and substantially a same thickness and atomic smoothness along the entire cross-sectional width of each active material layer perpendicular to current flow. 1. A method for fabricating a rectangular nanosheet structure , comprising:selecting an active material that will serve as a channel material in the nanosheet structure, a substrate suitable for epitaxial growth of the active material, and a sacrificial material to be used during fabrication of the nanosheet structure;growing a stack of alternating layers of active and sacrificial materials over the substrate; andselectively etching the sacrificial material, wherein due to properties of the sacrificial material, the selective etch results in remaining layers of active material having an aspect ratio greater than 1 and substantially a same thickness and atomic smoothness along the entire cross-sectional width of each active material layer perpendicular to current flow.2. The method of claim 1 , wherein the sacrificial material has properties including: a close lattice match to the active material; admits high quality growth on the active material and vice versa; and a chemical dissimilarity from the active material sufficient to enable highly selective etches.3. The method of claim 2 , wherein ...

Confined semi-metal field effect transistor

Exemplary embodiments are disclosed for a semi-metal transistor, comprising: a semi-metal contact region adjacent to a metal contact; at least one semiconductor terminal; and a semi-metal transition region connected between the contact region and the semiconductor terminal that transitions from a substantially zero gap semi-metal beginning at an interface of the contact region into a semiconductor with an energy band gap towards the semiconductor terminal.

STRAINED STACKED NANOSHEET FETS AND/OR QUANTUM WELL STACKED NANOSHEET

Exemplary embodiments provide for fabricating a nanosheet stack structure having one or more sub-stacks. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial stack of one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing, and wherein the sacrificial layer An is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top or the bottom using one of the sacrificial layers A; proceeding with fabrication flow of nanosheet devices, such that pillar structures are formed at each end of the epitaxial crystalline stack that to hold the nanosheets in place after selective etch of the sacrificial layers; and selectively removing sacrificial layers A to all non-sacrificial layers B and C, while the remaining layers in the stack are held in place by the pillar structures so that after removal of the sacrificial layers An, each of the sub-stacks contains the non-sacrificial layers B and C. 1. A method for fabricating a nanosheet stack structure having one or more sub-stacks , the method comprising:growing an epitaxial crystalline initial stack of one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing, and wherein the sacrificial layer A is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top ...

STRAINED STACKED NANOSHEET FETS AND/OR QUANTUM WELL STACKED NANOSHEET

Exemplary embodiments provide for fabricating a biaxially strained nanosheet. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial superlattice having one or more periods, each of the periods comprising at least three layers, an active material layer, a first sacrificial material layer and a second sacrificial material layer, the first and second sacrificial material layers having different material properties; in each of the one or more periods, placing each of the active material layers between the first and second sacrificial material layers, wherein lattice constants of the first and second sacrificial material layers are different than the active material layer and impose biaxial stress in the active material layer; selectively etching away all of the first sacrificial material layers thereby exposing one surface of the active material for additional processing, while the biaxial strain in the active material layers is maintained by the second sacrificial material layers; and selectively etching away all of the second sacrificial material layers thereby exposing a second surface of the active material layers for additional processing. 1. A method for fabricating a biaxially strained nanosheet , the method comprising:growing an epitaxial crystalline initial superlattice having one or more periods, each of the periods comprising at least three layers, an active material layer, a first sacrificial material layer and a second sacrificial material layer, the first and second sacrificial material layers having different material properties;in each of the one or more periods, placing each of the active material layers between the first and second sacrificial material layers, wherein lattice constants of the first and second sacrificial material layers are different than the active material layer and impose biaxial stress in the active material layer;selectively etching away all of the first sacrificial material layers thereby exposing ...

METHOD OF MAKING HIGH-EFFICIENCY SOLAR ENERGY DEVICE

A method of manufacturing a high-efficiency solar cell including an Indium, Gallium, Aluminum and Nitrogen (in a combination comprising InGaN, or InAlN, or InGaAlN) alloy which may be blended with a polyhedral oligomeric silsesquioxane (POSS) material, and which may include an absorption-enhancing layer including one of more of carbon nanotubes, quantum dots, and undulating or uneven surface topography. 1. A method of manufacturing a semiconductor structure useful in forming a solar cell comprising:forming a substrate;forming a first active layer material by mixing a nitride semiconductor material and a polyhedral oligomeric silsesquioxane (POSS) material to form a homogenous chemical compound; andforming a first active layer by applying the first active layer material on the substrate.2. The method of claim 1 , wherein the nitride semiconductor material comprises at least one of Indium and Nitride Indium Gallium Nitride (InGaN) claim 1 , Indium Aluminum Nitride (InAlN) claim 1 , and Indium Gallium Aluminum Nitride (InGaAlN).3. The method of claim 1 , wherein the step of mixing the nitride semiconductor material and the POSS material comprises atomizing the POSS material into the nitride semiconductor material.4. The method of claim 3 , wherein the step of forming the first active layer material further comprises vaporizing the POSS material for aligning grain boundaries of the nitride semiconductor material.5. The method of claim 4 , wherein the first active layer material is applied to the substrate via energetic neutral atom beam epitaxy.6. The method of claim 3 , wherein the nitride semiconductor material comprises a nitride semiconductor powder.7. The method of claim 1 , further comprising the step of doping first active layer material to enable photon absorption across a bandgap from approximately 0.7 electron Volt (eV) to 3.4 eV.8. The method of claim 1 , further comprising the step of forming an absorption-enhancing layer including at least one of carbon ...

INTEGRATED CIRCUIT DEVICES INCLUDING FINFETS AND METHODS OF FORMING THE SAME

Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep source/drain region adjacent to the channel region on the substrate and forming a source/drain extension region between the channel region and the deep source/drain region. Opposing sidewalls of the source/drain extension region may contact the channel region and the deep source/drain region, respectively, and the source/drain extension region may include InGaAs, and y is in a range of about 0.3 to about 0.5. 1. A method of forming a finFET , the method comprising:forming a fin-shaped channel region comprising indium (In) on a substrate;forming a deep source/drain region adjacent to the channel region on the substrate; andforming a source/drain extension region between the channel region and the deep source/drain region, wherein:opposing sidewalls of the source/drain extension region contact the channel region and the deep source/drain region, respectively; and{'sub': y', '1−y, 'the source/drain extension region comprises InGaAs, and y is in a range of about 0.3 to about 0.5.'}2. The method of claim 1 , wherein an indium concentration in the channel region is greater than an indium concentration in the source/drain extension region.3. The method of claim 2 , wherein forming the channel region comprises forming the channel region comprising InGaAs claim 2 , and x is in a range of about 0.5 to about 0.6.4. The method of claim 3 , wherein x is about 0.53.5. The method of claim 4 , wherein y is about 0.4.6. The method of claim 3 , wherein an indium concentration in the deep source/drain region is greater than the indium concentration in the channel region.7. The method of claim 6 , wherein forming the deep source/drain region comprises forming the deep source/drain region comprising InGaAs claim 6 , z is in a range of about 0.6 to about 1.8. The method of claim 6 , further comprising forming a contact region ...

CRYSTALLINE MULTIPLE-NANOSHEET STRAINED CHANNEL FETS AND METHODS OF FABRICATING THE SAME

A field effect transistor includes a body layer having a strained crystalline semiconductor channel region, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and a crystalline gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed. 1. A field effect transistor , comprising:a nanosheet stack comprising a plurality of individually gated conduction channels, the individually gated conduction channels respectively comprising a crystalline semiconductor channel layer, a crystalline dielectric layer on the channel layer, and a crystalline semiconductor gate layer on the gate dielectric layer opposite the channel layer, wherein the nanosheet stack is strained from lattice mismatch between ones of the layers thereof.2. The field effect transistor of claim 1 , wherein the crystalline channel layer claim 1 , the crystalline dielectric layer claim 1 , and the crystalline gate layer comprise heteroepitaxial layers.3. The field effect transistor of claim 1 , wherein the field effect transistor is an n-type device claim 1 , and wherein the crystalline channel layer comprises silicon (Si).4. The field effect transistor of claim 1 , wherein the field effect transistor is a p-type device claim 1 , and wherein the crystalline channel layer comprises silicon germanium (SiGe).5. The field effect transistor of claim 1 , wherein the crystalline dielectric layer comprises calcium fluoride (CaF) claim 1 , zinc sulfide (ZnS) claim 1 , praseodymium oxide (PrO) claim 1 , and/or gadolinium oxide (GdO).6. The field effect transistor of claim 1 , wherein the field effect transistor is an n-type device claim 1 , and wherein the crystalline gate layer comprises doped silicon germanium (SiGe).7. The field effect transistor of claim 1 , wherein the field effect transistor is a p-type device claim 1 , and wherein the ...

Integrated Circuits with Si and Non-Si Nanosheet FET Co-Integration with Low Band-to-Band Tunneling and Methods of Fabricating the Same

An integrated circuit may include multiple first, non-Si, nanosheet field-effect transistors (FETs) and multiple second, Si, nanosheet FETs. Nanosheets of ones of the first, non-Si, nanosheet FETs may include less than about 30% Si. The first, non-Si, nanosheet FETs may define a critical speed path of the circuit of the integrated circuit. Nanosheets of ones of the second, Si, nanosheet FETs may include more than about 30% Si. The second, Si, nanosheet FETs may define a non-critical speed path of the integrated circuit. Ones of the first, non-Si, nanosheet FETs may be configured to have a higher speed than a speed of ones of the second, Si, nanosheet FETs. 1. An integrated circuit comprising:a plurality of first nanosheet field-effect transistors (FETs), nanosheets of ones of the first nanosheet FETs comprising less than about 30% Si, the plurality of first nanosheet FETs defining a critical speed path; anda plurality of second nanosheet FETs, nanosheets of ones of the second nanosheet FETs comprising more than about 30% Si, the plurality of second nanosheet FETs defining a non-critical speed path, ones of the first nanosheet FETs configured to have a higher speed than a speed of ones of the second nanosheet FETs.2. The integrated circuit of claim 1 , wherein ones of the first nanosheet FETs comprise a barrier height from source to channel below a threshold value that is sufficient to limit the band-to-band tunneling induced current such that a total leakage current of the ones of the first nanosheet FETs has no significant contribution from the band-to-band tunneling induced current.3. The integrated circuit of claim 2 , wherein a thickness of nanosheets of ones of the first nanosheet FETs is greater than a critical thickness of the nanosheets of the ones of the first nanosheet FETs.4. The integrated circuit of claim 1 ,further comprising a plurality of third nanosheet FETs in the non-critical speed path,wherein nanosheets of ones of the third nanosheet FETs ...

High-efficiency solar energy device

A high-efficiency solar cell including an Indium, Gallium, Aluminum and Nitrogen (in a combination comprising InGaN, or InAlN, or InGaAlN) alloy which may be blended with a polyhedral oligomeric silsesquioxane (POSS) material, and which may include an absorption-enhancing layer including one of more of carbon nanotubes, quantum dots, and undulating or uneven surface topography.

Strained stacked nanosheet FETS and/or quantum well stacked nanosheet

Exemplary embodiments provide for fabricating a biaxially strained nanosheet. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial superlattice having one or more periods, each of the periods comprising at least three layers, an active material layer, a first sacrificial material layer and a second sacrificial material layer, the first and second sacrificial material layers having different material properties; in each of the one or more periods, placing each of the active material layers between the first and second sacrificial material layers, wherein lattice constants of the first and second sacrificial material layers are different than the active material layer and impose biaxial stress in the active material layer; selectively etching away all of the first sacrificial material layers thereby exposing one surface of the active material for additional processing, while the biaxial strain in the active material layers is maintained by the second sacrificial material layers; and selectively etching away all of the second sacrificial material layers thereby exposing a second surface of the active material layers for additional processing.

Cement slurry reclamation system and method

CEMENT SLURRY RECLAMATION SYSTEM AND METHOD Abstract of the Disclosure A slurry reclamation system for use with a concrete ready-mix plant which enables 100% reclamation of the constituents of concrete mix returned to the plant site by vehicles. Returned concrete mix is dumped into an inlet hopper having a screw classifier for removing aggregate and coarse sand, and a weired channel enabling gravity flow of the water, cement fines and sand fines constituents into a slurry vessel. The slurry in the vessel naturally separates into clarified water and concentrated slurry, and agitators are provided for periodically stirring up the slurry to maintain the cement fines active. The slurry vessel is sized in such a manner as to guarantee complete consumption of slurry returned during a day's production by the end of the following production day, the volumetric capacity of the vessel being related to the total average volume of water used to produce fresh concrete during a repre-sentativ e production day. An autochangeover unit automatically switches the water supply to truck washout stations and the screw classifier between normal plant supply water and the clarified water in the vessel, depending upon the level of the latter. The system enables substitution of slurry for cement fines alone, and alone, water alone, or any combination of these concrete constituents in accordance with the percent activity of the cement fines in the slurry and production demand.

鰭式場效電晶體半導體元件及形成其的方法

提供finFET半導體元件以及形成所述finFET半導體元件的方法。所述finFET半導體元件可包含：絕緣體層；底半導體層，位於所述絕緣體層上；通道鰭，位於所述底半導體層上；源極區，位於所述底半導體層上且鄰近於所述通道鰭的第一側；以及汲極區，位於所述底半導體層上且鄰近於與所述第一側相對的所述通道鰭的第二側。

Non-logic printed wiring board test system

FinFet-Bauelement

Die Erfindung bezieht sich auf ein FinFet-Bauelement, das eine Source-/Drain-Kontaktvertiefung beinhaltet. Ein FinFet-Bauelement gemäß der Erfindung beinhaltet eine Source-/Drain-Kontaktvertiefung mit einer Tiefe, die auf einen Punkt beschränkt ist, über den hinaus eine inkrementale Abnahme eines Werts eines Ausbreitungswiderstands, der mit einer horizontalen Grenzfläche am Boden der Vertiefung verknüpft ist, geringer als eine inkrementale Zunahme eines Gesamtwiderstands des FinFets ist. Verwendung in der Halbleiterbauelement-Technologie.

形成半導體圖案以及半導體層的方法

本發明提供形成包含減少錯位缺陷的半導體圖案的方法以及使用此等方法形成的裝置。所述方法可包含在基板上形成氧化物層，以及在氧化物層以及基板中形成凹槽。所述方法可更包含在凹槽中形成磊晶生長半導體圖案，所述磊晶生長半導體圖案接觸基板的在氧化物層與基板之間的界面處的側壁，且界定在所述基板中的所述凹槽中的空隙的上表面。

Verfahren zum Bilden einer Halbleiterschicht oder -struktur

Verfahren zum Bilden einer Halbleiterstruktur, wobei das Verfahren aufweist:- Bilden einer Oxidschicht (102) auf einem Substrat (100, 201);- Bilden einer Vertiefung (104, 204) in der Oxidschicht und dem Substrat; und- Bilden einer epitaxial aufgewachsenen unteren Halbleiterstruktur (106, 206) in der Vertiefung selektiv auf einer Oberfläche des Substrats und nicht auf einer Oberfläche der Oxidschicht derart, dass sich die untere Halbleiterstruktur an einer Grenzfläche zwischen der Oxidschicht und dem Substrat in Kontakt mit einer Seitenwand des Substrats befindet und eine Oberseite eines Hohlraums in der Vertiefung in dem Substrat definiert.

Non-logic printed wiring board test system

Verfahren zum Bilden einer Halbleiterschicht oder -struktur

Die Erfindung bezieht sich auf ein Verfahren zum Bilden einer Halbleiterschicht oder -struktur. Ein Verfahren zum Bilden einer Halbleiterstruktur gemäß der Erfindung beinhaltet ein Bilden einer Oxidschicht (102) auf einem Substrat (100), ein Bilden einer Vertiefung (104) in der Oxidschicht und dem Substrat sowie ein Bilden einer epitaxial aufgewachsenen Halbleiterstruktur (106, 108a) in der Vertiefung, die sich an einer Grenzfläche zwischen der Oxidschicht und dem Substrat in Kontakt mit einer Seitenwand des Substrats befindet und eine Oberseite eines Hohlraums in der Vertiefung in dem Substrat definiert. Verwendung in der Halbleiterfertigungstechnologie.

包括具有最佳化深度的凹入式源／汲極區域之鰭式場效電晶體裝置及形成該裝置之方法

一鰭式場效電晶體(finFET)裝置可包括一具有最佳深度的源/汲極接觸區域，超過該最佳深度則由增大的深度所提供之凹部中的一源/汲極接點的一水平部分之一展佈電阻值的一增量減小係可小於由於增大深度處的源/汲極接點的垂直部分之增大所致的總電阻之一增量增加。

包含電子單能器之量子干涉式邏輯元件

提供一種包含電子單能器的邏輯元件。所述電子單能器包含安置於第一穿隧障壁與第二穿隧障壁之間的量子點、耦接至所述第一穿隧障壁的射極，以及耦接至所述第二穿隧障壁的集極。所述邏輯元件亦包含量子干涉元件。所述量子干涉元件包含源極，所述源極耦接至所述電子單能器的所述集極。

Multi-layer fin field effect transistor devices and methods of forming the same

Multi-layer fin field effect transistor devices and methods of forming the same are provided. The devices may include a fin shaped channel structure on a substrate. The channel structure may include stressor layers stacked on the substrate and a channel layer between the stressor layers, and the stressor layers may include a semiconductor material having a wide bandgap that is sufficient to confine carriers to the channel layer and having a lattice constant different from a lattice constant of the channel layer to induce stress in the channel layer. The devices may also include source/drain regions on respective first opposing sides of the channel structure and a gate on second opposing sides of the channel structure and between the source/drain regions.

FinFET semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same

FinFET semiconductor devices and methods of forming the same are provided. The finFET semiconductor devices may include an insulator layer, a bottom semiconductor layer on the insulator layer, a channel fin on the bottom semiconductor layer, a source region on the bottom semiconductor layer and adjacent a first side of the channel fin, and a drain region on the bottom semiconductor layer and adjacent a second side of the channel fin opposite the first side.

Finfet devices including high mobility channel materials with materials of graded composition in recessed source/drain regions

A finFET device can include a high mobility semiconductor material in a fin structure that can provide a channel region for the finFET device. A source/drain recess can be adjacent to the fin structure and a graded composition epi-grown semiconductor alloy material, that includes a component of the high mobility semiconductor material, can be located in the source/drain recess.

Thermionically-overdriven tunnel FETs and methods of fabricating the same

A field effect transistor (FET) includes a nanosheet stack having first and second stacked semiconductor channel layers. The first channel layer defines a channel region of a tunnel FET, and the second channel layer defines a channel region of a thermionic FET. Source and drain regions are provided on opposite sides of the nanosheet stack such that the first and second channel layers extend therebetween. A first portion of the source region adjacent the first channel layer and a second portion of the source region adjacent the second channel layer have opposite semiconductor conductivity types. Related fabrication and operating methods are also discussed.

Low resistivity damascene interconnect

A damascene interconnect structure may be formed by forming a trench in an ILD. A diffusion barrier may be deposited on trench surfaces, followed by a first liner material. The first liner material may be removed from a bottom surface of the trench. A second liner material may be directionally deposited on the bottom. A conductive seed layer may be deposited on the first and second liner materials, and a conductive material may fill in the trench. A CMP process can remove excess material from the top of the structure. A damascene interconnect may include a dielectric having a trench, a first liner layer arranged on trench sidewalls, and a second liner layer arranged on a trench bottom. A conductive material may fill the trench. The first liner material may have low wettability and the second liner material may have high wettability with respect to the conductive material.

Integrated circuit devices including FinFETs and methods of forming the same

Methods of forming a finFET are provided. The methods may include forming a fin-shaped channel region including indium (In) on a substrate, forming a deep source/drain region adjacent to the channel region on the substrate and forming a source/drain extension region between the channel region and the deep source/drain region. Opposing sidewalls of the source/drain extension region may contact the channel region and the deep source/drain region, respectively, and the source/drain extension region may include In y Ga 1−y As, and y is in a range of about 0.3 to about 0.5.

Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same

A field effect transistor includes a body layer having a strained crystalline semiconductor channel region, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer that is lattice mismatched with the channel region, and a crystalline gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed.

Integrated circuit devices including strained channel regions and methods of forming the same

Integrated circuit devices including strained channel regions and methods of forming the same are provided. The integrated circuit devices may include enhancement-mode field effect transistors. The enhancement-mode field effect transistors may include a quantum well channel region having a well thickness T w sufficient to yield a strain-induced splitting of a plurality of equivalent-type electron conduction states therein to respective unequal energy levels including a lowermost energy level associated with a lowermost surface roughness scattering adjacent a surface of the channel region when, the surface is biased into a state of inversion.

Semiconductor devices with structures for suppression of parasitic bipolar effect in stacked nanosheet FETs and methods of fabricating the same

A device may include a nanosheet field effect transistor (FET) that may include a substrate, a well that is doped with impurities at a surface of the substrate, a channel including a plurality of stacked nanosheets, a gate, a conductive material, and an isolation layer. Ones of the plurality of stacked nanosheets may include a semiconductor material that may be doped with impurities of the same conductivity type as the impurities of the well. The conductive material may be adjacent the plurality of nanosheets and may electrically connect ones of the plurality of nanosheets to the well. The isolation layer may electrically insulate the well from the workfunction metal.