09-05-2019 дата публикации
Номер: US20190140176A1
Автор:
ARNAUD Franck,
Boivin Philippe,
BROUSSOUS Lucile,
BRUN Philippe,
Favennec Laurent,
GALPIN David,
HINSINGER Olivier,
Morin Pierre,
Oddou Jean-Pierre,
Weber Olivier,
Zoll Stephane
Принадлежит:
An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track. 1. A method of manufacturing an electronic chip containing memory cells , comprising a phase-change material and transistors , comprising:a) forming a first metal level comprising first interconnection tracks extending through a first insulating layer; andb) for each memory cell, forming a heating element configured to heat the phase-change material in the first metal level and extending adjacent a side of a portion of the first insulating layer.2. The method of claim 1 , further comprising claim 1 , before step a) claim 1 , forming the transistors and first and second vias extending from terminals of the transistors and reaching a first height claim 1 , wherein the first interconnection tracks of the first metal level are in contact with the first vias at the first height and wherein the heating elements are in contact with the second vias at the first height.3. The method of claim 1 , further comprising claim 1 , after step b) claim 1 , forming the phase-change material of each memory cell on the heating element.4. The method of claim 1 , further comprising claim 1 , after step b):forming a second metal level comprising second interconnection tracks and located above the phase-change materials, andforming third vias extending from the phase-change materials to the second interconnection ...
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