Process for forming an edge structure to seal integrated electronic devices, and corresponding device

A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material. The electronic circuit is of the type that calls for formation above the major surface of at least one dielectric multilayer. The dielectric multilayer includes a layer of amorphous planarizing material having a continuous portion extending between two contiguous areas with a more internal first area and a more external second area in the morphological structure. The device edge morphological structure includes in the substrate an excavation on the side of the major surface at the more internal first area of the morphological structure in a zone in which is present the continuous portion of the dielectric multilayer.

Verfahren zur Herstellung von einer Randstruktur um ein integriertes elektronisches Bauelement zu versiegeln, sowie ein entsprechendes Bauelement

Verfahren zur Herstellung von einer Randstruktur um ein integriertes elektronisches Bauelement zu versiegeln, sowie ein entsprechendes Bauelement

MANUFACTURE OF END STRUCTURE FOR SEALING INTEGRATED ELECTRONIC DEVICE AND APPARATUS THEREFOR

PROBLEM TO BE SOLVED: To perfectly seal the ends of the device by forming recesses into first inner sections of a main surface of a planarized amorphous material layer- made morphologic structure within zones having continuous parts. SOLUTION: A mask 34 in a zone of a device end morphologic structure 30 is opened up to the ends of the device. A second polysilicon etching at an active region 8 located at the left of a field oxide film region 7 forms recesses R1 in a substrate 6. The recesses R1 locate in inner regions 3' of the structure 30 inside which a polymer circuit mask 35 having openings 36 is provided to form other recesses R2 at unmasked surface of Si, thus obtaining the recesses different in depth. This reduces the gradient of the steps between the recess bottom and Si surface 5. COPYRIGHT: (C)1998,JPO ...